Hello,

This series improves the current models of the Aspeed machines in QEMU
and adds new ones. It also prepares ground for the future Aspeed SoC.
You will find patches for :

 - per SoC mappings of the memory space and the interrupt number space 
 - a RTC model from Joel
 - support for multiple CPUs and NICs
 - fixes for the timer model from Joel, Andrew and Christian
 - DMA support for the SMC controller, which was reworked to use a RAM
   container region as suggested by Peter in September 2018

It is based on Eduardo's series" Machine Core queue, 2019-05-24"

  http://patchwork.ozlabs.org/patch/1105091/

I have included Philippe's patch (comes first) in this patchset for
reference only.

Thanks,

C.

Andrew Jeffery (3):
  aspeed/timer: Status register contains reload for stopped timer
  aspeed/timer: Fix match calculations
  aspeed/timer: Provide back-pressure information for short periods

Christian Svensson (2):
  aspeed/timer: Ensure positive muldiv delta
  aspeed/smc: Calculate checksum on normal DMA

Cédric Le Goater (10):
  aspeed: add a per SoC mapping for the interrupt space
  aspeed: add a per SoC mapping for the memory space
  aspeed: introduce a configurable number of CPU per machine
  aspeed: add support for multiple NICs
  aspeed/smc: add a 'sdram_base' propertie
  aspeed: remove the "ram" link
  aspeed: add a RAM memory region container
  aspeed/smc: add support for DMAs
  aspeed/smc: add DMA calibration settings
  aspeed/smc: inject errors in DMA checksum

Joel Stanley (3):
  hw: timer: Add ASPEED RTC device
  hw/arm/aspeed: Add RTC to SoC
  aspeed/timer: Fix behaviour running Linux

Philippe Mathieu-Daudé (1):
  hw/arm/aspeed: Use object_initialize_child for correct ref. counting

 include/hw/arm/aspeed.h         |   1 +
 include/hw/arm/aspeed_soc.h     |  48 ++++-
 include/hw/ssi/aspeed_smc.h     |   9 +
 include/hw/timer/aspeed_rtc.h   |  31 +++
 include/hw/timer/aspeed_timer.h |   1 +
 hw/arm/aspeed.c                 |  35 ++--
 hw/arm/aspeed_soc.c             | 283 ++++++++++++++++++----------
 hw/misc/aspeed_scu.c            |   6 +
 hw/ssi/aspeed_smc.c             | 323 +++++++++++++++++++++++++++++++-
 hw/timer/aspeed_rtc.c           | 180 ++++++++++++++++++
 hw/timer/aspeed_timer.c         |  84 ++++++---
 hw/timer/Makefile.objs          |   2 +-
 hw/timer/trace-events           |   4 +
 13 files changed, 854 insertions(+), 153 deletions(-)
 create mode 100644 include/hw/timer/aspeed_rtc.h
 create mode 100644 hw/timer/aspeed_rtc.c

-- 
2.20.1

On Sat, 25 May 2019 at 16:12, Cédric Le Goater <clg@kaod.org> wrote:
>
> Hello,
>
> This series improves the current models of the Aspeed machines in QEMU
> and adds new ones. It also prepares ground for the future Aspeed SoC.
> You will find patches for :
>
>  - per SoC mappings of the memory space and the interrupt number space
>  - a RTC model from Joel
>  - support for multiple CPUs and NICs
>  - fixes for the timer model from Joel, Andrew and Christian
>  - DMA support for the SMC controller, which was reworked to use a RAM
>    container region as suggested by Peter in September 2018
>
> It is based on Eduardo's series" Machine Core queue, 2019-05-24"
>
>   http://patchwork.ozlabs.org/patch/1105091/
>
> I have included Philippe's patch (comes first) in this patchset for
> reference only.

...I'm hoping some of the other folks interested in Aspeed
are going to review this series.

thanks
-- PMM