Implement PowerPC FPSCR flag Fraction Rounded

[Qemu-devel] [PATCH 0/2] Implement PowerPC FPSCR flag Fraction Rounded

John Arbuckle posted 2 patches 4 years, 11 months ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20190525022008.24788-1-programmingkidx@gmail.com

Maintainers: "Alex Bennée" <alex.bennee@linaro.org>, Aurelien Jarno <aurelien@aurel32.net>, Peter Maydell <peter.maydell@linaro.org>, David Gibson <david@gibson.dropbear.id.au>

fpu/softfloat.c               | 15 ++++++++++++---
include/fpu/softfloat-types.h |  1 +
target/ppc/fpu_helper.c       |  4 ++++
3 files changed, 17 insertions(+), 3 deletions(-)

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[Qemu-devel] [PATCH 0/2] Implement PowerPC FPSCR flag Fraction Rounded

Posted by John Arbuckle 4 years, 11 months ago

In IEEE 754 math, the arithmetic, rounding, and conversion instructions produce an intermediate result that can be regarded as having infinite precision and unbounded exponent range. When the final result has its fraction part incremented is when the Fraction Rounded bit is set.

This patch implements the PowerPC FPSCR flag Fraction Rounded.

Note: there are still functions in softfloat that need to be adjusted so that float_flag_rounded is fully supported. These include round_to_int(), and all legacy roundAndPack* functions. So basically anywhere that sets the float_flag_inexact.

John Arbuckle (2):
  Implement Floating Point flag Fraction Rounded
  Implement the PowerPC Floating Point Status and Control Register
    Fraction Rounded bit

 fpu/softfloat.c               | 15 ++++++++++++---
 include/fpu/softfloat-types.h |  1 +
 target/ppc/fpu_helper.c       |  4 ++++
 3 files changed, 17 insertions(+), 3 deletions(-)

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2.14.3 (Apple Git-98)