hw/arm/smmuv3: Fix decoding of ID register range

[Qemu-devel] [PATCH] hw/arm/smmuv3: Fix decoding of ID register range

Peter Maydell posted 1 patch 4 years, 11 months ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20190524124829.2589-1-peter.maydell@linaro.org

Maintainers: Eric Auger <eric.auger@redhat.com>, Peter Maydell <peter.maydell@linaro.org>

hw/arm/smmuv3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

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[Qemu-devel] [PATCH] hw/arm/smmuv3: Fix decoding of ID register range

Posted by Peter Maydell 4 years, 11 months ago

The SMMUv3 ID registers cover an area 0x30 bytes in size
(12 registers, 4 bytes each). We were incorrectly decoding
only the first 0x20 bytes.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/smmuv3.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index fd8ec7860ee..e96d5beb9a8 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -1232,7 +1232,7 @@ static MemTxResult smmu_readl(SMMUv3State *s, hwaddr offset,
                               uint64_t *data, MemTxAttrs attrs)
 {
     switch (offset) {
-    case A_IDREGS ... A_IDREGS + 0x1f:
+    case A_IDREGS ... A_IDREGS + 0x2f:
         *data = smmuv3_idreg(offset - A_IDREGS);
         return MEMTX_OK;
     case A_IDR0 ... A_IDR5:
-- 
2.20.1

Re: [Qemu-devel] [PATCH] hw/arm/smmuv3: Fix decoding of ID register range

Posted by Auger Eric 4 years, 11 months ago

Hi Peter,
On 5/24/19 2:48 PM, Peter Maydell wrote:
> The SMMUv3 ID registers cover an area 0x30 bytes in size
> (12 registers, 4 bytes each). We were incorrectly decoding
> only the first 0x20 bytes.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>

Thank you for the fix.

Eric

> ---
>  hw/arm/smmuv3.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
> index fd8ec7860ee..e96d5beb9a8 100644
> --- a/hw/arm/smmuv3.c
> +++ b/hw/arm/smmuv3.c
> @@ -1232,7 +1232,7 @@ static MemTxResult smmu_readl(SMMUv3State *s, hwaddr offset,
>                                uint64_t *data, MemTxAttrs attrs)
>  {
>      switch (offset) {
> -    case A_IDREGS ... A_IDREGS + 0x1f:
> +    case A_IDREGS ... A_IDREGS + 0x2f:
>          *data = smmuv3_idreg(offset - A_IDREGS);
>          return MEMTX_OK;
>      case A_IDR0 ... A_IDR5:
>