Series comparison

-[Qemu-devel] [PULL 00/12] target-arm queue
+[PULL 00/21] target-arm queue
-Not very much here, but several people have fallen over
+Hi; here's a target-arm pullreq to go in before softfreeze.
-the vector operation segfault bug, so let's get the fix
+This is actually pretty much entirely bugfixes (since the
-into master.
+SEL2 timers we implement here are a missing part of a feature
 we claim to already implement).
 thanks
 -- PMM
-The following changes since commit d418238dca7b4e0b124135827ead3076233052b1:
+The following changes since commit 98c7362b1efe651327385a25874a73e008c6549e:
-  Merge remote-tracking branch 'remotes/rth/tags/pull-rng-20190522' into staging (2019-05-23 12:57:17 +0100)
+  Merge tag 'accel-cpus-20250306' of https://github.com/philmd/qemu into staging (2025-03-07 07:39:49 +0800)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190523
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20250307
-for you to fetch changes up to 98e4f4fdb8ea05d840f51f47125924c2bb9df2df:
+for you to fetch changes up to 0ce0739d46983e5e88fa9c149cb305689c9d8c6f:
-  hw/arm/exynos4210: QOM'ify the Exynos4210 SoC (2019-05-23 14:47:44 +0100)
+  target/rx: Remove TCG_CALL_NO_WG from helpers which write env (2025-03-07 15:03:20 +0000)
 ----------------------------------------------------------------
 target-arm queue:
- * exynos4210: QOM'ify the Exynos4210 SoC
+ * hw/arm/smmu-common: Remove the repeated ttb field
- * exynos4210: Add DMA support for the Exynos4210
+ * hw/gpio: npcm7xx: fixup out-of-bounds access
- * arm_gicv3: Fix writes to ICC_CTLR_EL3
+ * tests/functional/test_arm_sx1: Check whether the serial console is working
- * arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
+ * target/arm: Fix minor bugs in generic timer register handling
- * target/arm: Fix vector operation segfault
+ * target/arm: Implement SEL2 physical and virtual timers
- * target/arm: Minor improvements to BFXIL, EXTR
+ * target/arm: Correct STRD, LDRD atomicity and fault behaviour
  * target/arm: Make dummy debug registers RAZ, not NOP
  * util/qemu-timer.c: Don't warp timer from timerlist_rearm()
  * include/exec/memop.h: Expand comment for MO_ATOM_SUBALIGN
  * hw/arm/smmu: Introduce smmu_configs_inv_sid_range() helper
  * target/rx: Set exception vector base to 0xffffff80
  * target/rx: Remove TCG_CALL_NO_WG from helpers which write env
 ----------------------------------------------------------------
-Alistair Francis (1):
+Alex Bennée (4):
-      target/arm: Fix vector operation segfault
+      target/arm: Implement SEL2 physical and virtual timers
       target/arm: Document the architectural names of our GTIMERs
       hw/arm: enable secure EL2 timers for virt machine
       hw/arm: enable secure EL2 timers for sbsa machine
-Guenter Roeck (1):
+JianChunfu (2):
-      hw/arm/exynos4210: Add DMA support for the Exynos4210
+      hw/arm/smmu-common: Remove the repeated ttb field
       hw/arm/smmu: Introduce smmu_configs_inv_sid_range() helper
-Peter Maydell (5):
+Keith Packard (2):
-      arm: Move system_clock_scale to armv7m_systick.h
+      target/rx: Set exception vector base to 0xffffff80
-      arm: Remove unnecessary includes of hw/arm/arm.h
+      target/rx: Remove TCG_CALL_NO_WG from helpers which write env
       arm: Rename hw/arm/arm.h to hw/arm/boot.h
       hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
       hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3
-Philippe Mathieu-Daudé (3):
+Patrick Venture (1):
-      hw/arm/exynos4: Remove unuseful debug code
+      hw/gpio: npcm7xx: fixup out-of-bounds access
       hw/arm/exynos4: Use the IEC binary prefix definitions
       hw/arm/exynos4210: QOM'ify the Exynos4210 SoC
-Richard Henderson (2):
+Peter Maydell (11):
-      target/arm: Use extract2 for EXTR
+      target/arm: Apply correct timer offset when calculating deadlines
-      target/arm: Simplify BFXIL expansion
+      target/arm: Don't apply CNTVOFF_EL2 for EL2_VIRT timer
       target/arm: Make CNTPS_* UNDEF from Secure EL1 when Secure EL2 is enabled
       target/arm: Always apply CNTVOFF_EL2 for CNTV_TVAL_EL02 accesses
       target/arm: Refactor handling of timer offset for direct register accesses
       target/arm: Correct LDRD atomicity and fault behaviour
       target/arm: Correct STRD atomicity
       target/arm: Drop unused address_offset from op_addr_{rr, ri}_post()
       target/arm: Make dummy debug registers RAZ, not NOP
       util/qemu-timer.c: Don't warp timer from timerlist_rearm()
       include/exec/memop.h: Expand comment for MO_ATOM_SUBALIGN
- include/hw/arm/allwinner-a10.h    |  2 +-
+Thomas Huth (1):
- include/hw/arm/aspeed_soc.h       |  1 -
+      tests/functional/test_arm_sx1: Check whether the serial console is working
  include/hw/arm/bcm2836.h          |  1 -
  include/hw/arm/{arm.h => boot.h}  | 12 +++------
  include/hw/arm/exynos4210.h       |  9 +++++--
  include/hw/arm/fsl-imx25.h        |  2 +-
  include/hw/arm/fsl-imx31.h        |  2 +-
  include/hw/arm/fsl-imx6.h         |  2 +-
  include/hw/arm/fsl-imx6ul.h       |  2 +-
  include/hw/arm/fsl-imx7.h         |  2 +-
  include/hw/arm/virt.h             |  2 +-
  include/hw/arm/xlnx-versal.h      |  2 +-
  include/hw/arm/xlnx-zynqmp.h      |  2 +-
  include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++
  hw/arm/armsse.c                   |  2 +-
  hw/arm/armv7m.c                   |  2 +-
  hw/arm/aspeed.c                   |  2 +-
  hw/arm/boot.c                     |  2 +-
  hw/arm/collie.c                   |  2 +-
  hw/arm/exynos4210.c               | 54 ++++++++++++++++++++++++++++++++++++---
  hw/arm/exynos4_boards.c           | 40 ++++++++---------------------
  hw/arm/highbank.c                 |  2 +-
  hw/arm/integratorcp.c             |  2 +-
  hw/arm/mainstone.c                |  2 +-
  hw/arm/microbit.c                 |  2 +-
  hw/arm/mps2-tz.c                  |  2 +-
  hw/arm/mps2.c                     |  2 +-
  hw/arm/msf2-soc.c                 |  1 -
  hw/arm/msf2-som.c                 |  2 +-
  hw/arm/musca.c                    |  2 +-
  hw/arm/musicpal.c                 |  2 +-
  hw/arm/netduino2.c                |  2 +-
  hw/arm/nrf51_soc.c                |  2 +-
  hw/arm/nseries.c                  |  2 +-
  hw/arm/omap1.c                    |  2 +-
  hw/arm/omap2.c                    |  2 +-
  hw/arm/omap_sx1.c                 |  2 +-
  hw/arm/palm.c                     |  2 +-
  hw/arm/raspi.c                    |  2 +-
  hw/arm/realview.c                 |  2 +-
  hw/arm/spitz.c                    |  2 +-
  hw/arm/stellaris.c                |  2 +-
  hw/arm/stm32f205_soc.c            |  2 +-
  hw/arm/strongarm.c                |  2 +-
  hw/arm/tosa.c                     |  2 +-
  hw/arm/versatilepb.c              |  2 +-
  hw/arm/vexpress.c                 |  2 +-
  hw/arm/virt.c                     |  2 +-
  hw/arm/xilinx_zynq.c              |  2 +-
  hw/arm/xlnx-versal.c              |  2 +-
  hw/arm/z2.c                       |  2 +-
  hw/intc/arm_gicv3_cpuif.c         |  6 ++---
  hw/intc/armv7m_nvic.c             |  1 -
  target/arm/arm-semi.c             |  1 -
  target/arm/cpu.c                  |  1 -
  target/arm/cpu64.c                |  1 -
  target/arm/kvm.c                  |  1 -
  target/arm/kvm32.c                |  1 -
  target/arm/kvm64.c                |  1 -
  target/arm/translate-a64.c        | 44 ++++++++++++++++---------------
  target/arm/translate.c            |  4 +--
 files changed, 164 insertions(+), 123 deletions(-)
  rename include/hw/arm/{arm.h => boot.h} (96%)
+ MAINTAINERS                      |   1 +
+ hw/arm/smmu-internal.h           |   5 -
+ include/exec/memop.h             |   8 +-
+ include/hw/arm/bsa.h             |   2 +
+ include/hw/arm/smmu-common.h     |   7 +-
+ target/arm/cpu.h                 |   2 +
+ target/arm/gtimer.h              |  14 +-
+ target/arm/internals.h           |   5 +-
+ target/rx/helper.h               |  34 ++--
+ hw/arm/sbsa-ref.c                |   2 +
+ hw/arm/smmu-common.c             |  21 +++
+ hw/arm/smmuv3.c                  |  19 +--
+ hw/arm/virt.c                    |   2 +
+ hw/gpio/npcm7xx_gpio.c           |   3 +-
+ target/arm/cpu.c                 |   4 +
+ target/arm/debug_helper.c        |   7 +-
+ target/arm/helper.c              | 324 ++++++++++++++++++++++++++++++++-------
+ target/arm/tcg/op_helper.c       |   8 +-
+ target/arm/tcg/translate.c       | 147 +++++++++++-------
+ target/rx/helper.c               |   2 +-
+ util/qemu-timer.c                |   4 -
+ hw/arm/trace-events              |   3 +-
+ tests/functional/test_arm_sx1.py |   7 +-
+files changed, 455 insertions(+), 176 deletions(-)

-New patch
+[PULL 01/21] hw/arm/smmu-common: Remove the repeated ttb field
+From: JianChunfu <jansef.jian@hj-micro.com>
+SMMUTransCfg->ttb is never used in QEMU, TT base address
+can be accessed by SMMUTransCfg->tt[i]->ttb.
+Signed-off-by: JianChunfu <jansef.jian@hj-micro.com>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Message-id: 20250221031034.69822-1-jansef.jian@hj-micro.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ include/hw/arm/smmu-common.h | 1 -
+file changed, 1 deletion(-)
+diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/smmu-common.h
++++ b/include/hw/arm/smmu-common.h
+@@ -XXX,XX +XXX,XX @@ typedef struct SMMUTransCfg {
+     /* Used by stage-1 only. */
+     bool aa64;                 /* arch64 or aarch32 translation table */
+     bool record_faults;        /* record fault events */
+-    uint64_t ttb;              /* TT base address */
+     uint8_t oas;               /* output address width */
+     uint8_t tbi;               /* Top Byte Ignore */
+     int asid;
+--
+.43.0

-[Qemu-devel] [PULL 02/12] target/arm: Simplify BFXIL expansion
+[PULL 02/21] hw/gpio: npcm7xx: fixup out-of-bounds access
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Patrick Venture <venture@google.com>
-The mask implied by the extract is redundant with the one
+The reg isn't validated to be a possible register before
-implied by the deposit.  Also, fix spelling of BFXIL.
+it's dereferenced for one case.  The mmio space registered
 for the gpio device is 4KiB but there aren't that many
 registers in the struct.
-Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
+Cc: qemu-stable@nongnu.org
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Fixes: 526dbbe0874 ("hw/gpio: Add GPIO model for Nuvoton NPCM7xx")
-Message-id: 20190514011129.11330-3-richard.henderson@linaro.org
+Signed-off-by: Patrick Venture <venture@google.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20250226024603.493148-1-venture@google.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/translate-a64.c | 6 +++---
+ hw/gpio/npcm7xx_gpio.c | 3 +--
-file changed, 3 insertions(+), 3 deletions(-)
+file changed, 1 insertion(+), 2 deletions(-)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
+diff --git a/hw/gpio/npcm7xx_gpio.c b/hw/gpio/npcm7xx_gpio.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
+--- a/hw/gpio/npcm7xx_gpio.c
-+++ b/target/arm/translate-a64.c
++++ b/hw/gpio/npcm7xx_gpio.c
-@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ static void npcm7xx_gpio_regs_write(void *opaque, hwaddr addr, uint64_t v,
-             tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len);
+         return;
              return;
          }
 -        /* opc == 1, BXFIL fall through to deposit */
 -        tcg_gen_extract_i64(tcg_tmp, tcg_tmp, ri, len);
 +        /* opc == 1, BFXIL fall through to deposit */
 +        tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri);
          pos = 0;
      } else {
          /* Handle the ri > si case with a deposit
@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
          len = ri;
      }
--    if (opc == 1) { /* BFM, BXFIL */
+-    diff = s->regs[reg] ^ value;
-+    if (opc == 1) { /* BFM, BFXIL */
+-
-         tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len);
+     switch (reg) {
-     } else {
+     case NPCM7XX_GPIO_TLOCK1:
-         /* SBFM or UBFM: We start with zero, and we haven't modified
+     case NPCM7XX_GPIO_TLOCK2:
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_gpio_regs_write(void *opaque, hwaddr addr, uint64_t v,
      case NPCM7XX_GPIO_PU:
      case NPCM7XX_GPIO_PD:
      case NPCM7XX_GPIO_IEM:
 +        diff = s->regs[reg] ^ value;
          s->regs[reg] = value;
          npcm7xx_gpio_update_pins(s, diff);
          break;
 --
-.20.1
+.43.0

-[Qemu-devel] [PULL 10/12] hw/arm/exynos4: Use the IEC binary prefix definitions
+[PULL 03/21] tests/functional/test_arm_sx1: Check whether the serial console is working
-From: Philippe Mathieu-Daudé <philmd@redhat.com>
+From: Thomas Huth <thuth@redhat.com>
-It eases code review, unit is explicit.
+The kernel that is used in the sx1 test prints the usual Linux log
 onto the serial console, but this test currently ignores it. To
 make sure that the serial device is working properly, let's check
 for some strings in the output here.
-Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+While we're at it, also add the test to the corresponding section
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+in the MAINTAINERS file.
-Message-id: 20190520214342.13709-3-philmd@redhat.com
 Signed-off-by: Thomas Huth <thuth@redhat.com>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Message-id: 20250226104833.1176253-1-thuth@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/exynos4_boards.c | 5 +++--
+ MAINTAINERS                      | 1 +
-file changed, 3 insertions(+), 2 deletions(-)
+ tests/functional/test_arm_sx1.py | 7 ++++---
 files changed, 5 insertions(+), 3 deletions(-)
-diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
+diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/exynos4_boards.c
+--- a/MAINTAINERS
-+++ b/hw/arm/exynos4_boards.c
++++ b/MAINTAINERS
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ S: Maintained
-  */
+ F: hw/*/omap*
+ F: include/hw/arm/omap.h
- #include "qemu/osdep.h"
+ F: docs/system/arm/sx1.rst
-+#include "qemu/units.h"
++F: tests/functional/test_arm_sx1.py
- #include "qapi/error.h"
- #include "qemu/error-report.h"
+ IPack
- #include "qemu-common.h"
+ M: Alberto Garcia <berto@igalia.com>
-@@ -XXX,XX +XXX,XX @@ static int exynos4_board_smp_bootreg_addr[EXYNOS4_NUM_OF_BOARDS] = {
+diff --git a/tests/functional/test_arm_sx1.py b/tests/functional/test_arm_sx1.py
- };
+index XXXXXXX..XXXXXXX 100755
+--- a/tests/functional/test_arm_sx1.py
- static unsigned long exynos4_board_ram_size[EXYNOS4_NUM_OF_BOARDS] = {
++++ b/tests/functional/test_arm_sx1.py
--    [EXYNOS4_BOARD_NURI]     = 0x40000000,
+@@ -XXX,XX +XXX,XX @@ def test_arm_sx1_initrd(self):
--    [EXYNOS4_BOARD_SMDKC210] = 0x40000000,
+         self.vm.add_args('-append', f'kunit.enable=0 rdinit=/sbin/init {self.CONSOLE_ARGS}')
-+    [EXYNOS4_BOARD_NURI]     = 1 * GiB,
+         self.vm.add_args('-no-reboot')
-+    [EXYNOS4_BOARD_SMDKC210] = 1 * GiB,
+         self.launch_kernel(zimage_path,
- };
+-                           initrd=initrd_path)
++                           initrd=initrd_path,
- static struct arm_boot_info exynos4_board_binfo = {
++                           wait_for='Boot successful')
          self.vm.wait(timeout=120)
      def test_arm_sx1_sd(self):
@@ -XXX,XX +XXX,XX @@ def test_arm_sx1_sd(self):
          self.vm.add_args('-no-reboot')
          self.vm.add_args('-snapshot')
          self.vm.add_args('-drive', f'format=raw,if=sd,file={sd_fs_path}')
 -        self.launch_kernel(zimage_path)
 +        self.launch_kernel(zimage_path, wait_for='Boot successful')
          self.vm.wait(timeout=120)
      def test_arm_sx1_flash(self):
@@ -XXX,XX +XXX,XX @@ def test_arm_sx1_flash(self):
          self.vm.add_args('-no-reboot')
          self.vm.add_args('-snapshot')
          self.vm.add_args('-drive', f'format=raw,if=pflash,file={flash_path}')
 -        self.launch_kernel(zimage_path)
 +        self.launch_kernel(zimage_path, wait_for='Boot successful')
          self.vm.wait(timeout=120)
  if __name__ == '__main__':
 --
-.20.1
+.43.0

-[Qemu-devel] [PULL 11/12] hw/arm/exynos4210: Add DMA support for the Exynos4210
+[PULL 04/21] target/arm: Apply correct timer offset when calculating deadlines
-From: Guenter Roeck <linux@roeck-us.net>
+When we are calculating timer deadlines, the correct definition of
 whether or not to apply an offset to the physical count is described
 in the Arm ARM DDI4087 rev L.a section D12.2.4.1.  This is different
 from when the offset should be applied for a direct read of the
 counter sysreg.
-QEMU already supports pl330. Instantiate it for Exynos4210.
+We got this right for the EL1 physical timer and for the EL1 virtual
 timer, but got all the rest wrong: they should be using a zero offset
 always.
-Relevant part of Linux arch/arm/boot/dts/exynos4.dtsi:
+Factor the offset calculation out into a function that has a comment
 documenting exactly which offset it is calculating and which gets the
 HYP, SEC, and HYPVIRT cases right.
-/ {
+Cc: qemu-stable@nongnu.org
-    soc: soc {
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-        amba {
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-            pdma0: pdma@12680000 {
+Message-id: 20250204125009.2281315-2-peter.maydell@linaro.org
-                compatible = "arm,pl330", "arm,primecell";
+---
-                reg = <0x12680000 0x1000>;
+ target/arm/helper.c | 29 +++++++++++++++++++++++++++--
-                interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+file changed, 27 insertions(+), 2 deletions(-)
                 clocks = <&clock CLK_PDMA0>;
                 clock-names = "apb_pclk";
                 #dma-cells = <1>;
                 #dma-channels = <8>;
                 #dma-requests = <32>;
             };
             pdma1: pdma@12690000 {
                 compatible = "arm,pl330", "arm,primecell";
                 reg = <0x12690000 0x1000>;
                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&clock CLK_PDMA1>;
                 clock-names = "apb_pclk";
                 #dma-cells = <1>;
                 #dma-channels = <8>;
                 #dma-requests = <32>;
             };
             mdma1: mdma@12850000 {
                 compatible = "arm,pl330", "arm,primecell";
                 reg = <0x12850000 0x1000>;
                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&clock CLK_MDMA>;
                 clock-names = "apb_pclk";
                 #dma-cells = <1>;
                 #dma-channels = <8>;
                 #dma-requests = <1>;
             };
         };
     };
 };
-Signed-off-by: Guenter Roeck <linux@roeck-us.net>
+diff --git a/target/arm/helper.c b/target/arm/helper.c
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Message-id: 20190520214342.13709-4-philmd@redhat.com
 [PMD: Do not set default qdev properties, create the controllers in the SoC
       rather than the board (Peter Maydell), add dtsi in commit message]
 Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  hw/arm/exynos4210.c | 26 ++++++++++++++++++++++++++
 file changed, 26 insertions(+)
 diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/exynos4210.c
+--- a/target/arm/helper.c
-+++ b/hw/arm/exynos4210.c
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static uint64_t gt_phys_cnt_offset(CPUARMState *env)
- /* EHCI */
+     return gt_phys_raw_cnt_offset(env);
  #define EXYNOS4210_EHCI_BASE_ADDR           0x12580000
 +/* DMA */
 +#define EXYNOS4210_PL330_BASE0_ADDR         0x12680000
 +#define EXYNOS4210_PL330_BASE1_ADDR         0x12690000
 +#define EXYNOS4210_PL330_BASE2_ADDR         0x12850000
 +
  static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
 x09, 0x00, 0x00, 0x00 };
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu)
      return (0x9 << ARM_AFF1_SHIFT) | cpu;
  }
-+static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
++static uint64_t gt_indirect_access_timer_offset(CPUARMState *env, int timeridx)
 +{
-+    SysBusDevice *busdev;
++    /*
-+    DeviceState *dev;
++     * Return the timer offset to use for indirect accesses to the timer.
-+
++     * This is the Offset value as defined in D12.2.4.1 "Operation of the
-+    dev = qdev_create(NULL, "pl330");
++     * CompareValue views of the timers".
-+    qdev_prop_set_uint8(dev, "num_periph_req",  nreq);
++     *
-+    qdev_init_nofail(dev);
++     * The condition here is not always the same as the condition for
-+    busdev = SYS_BUS_DEVICE(dev);
++     * whether to apply an offset register when doing a direct read of
-+    sysbus_mmio_map(busdev, 0, base);
++     * the counter sysreg; those conditions are described in the
-+    sysbus_connect_irq(busdev, 0, irq);
++     * access pseudocode for each counter register.
 +     */
 +    switch (timeridx) {
 +    case GTIMER_PHYS:
 +        return gt_phys_raw_cnt_offset(env);
 +    case GTIMER_VIRT:
 +        return env->cp15.cntvoff_el2;
 +    case GTIMER_HYP:
 +    case GTIMER_SEC:
 +    case GTIMER_HYPVIRT:
 +        return 0;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
- Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
+ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
  {
-     Exynos4210State *s = g_new0(Exynos4210State, 1);
+     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
-@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
+@@ -XXX,XX +XXX,XX @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
-     sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
+          * Timer enabled: calculate and set current ISTATUS, irq, and
-             s->irq_table[exynos4210_get_irq(28, 3)]);
+          * reset timer to when ISTATUS next has to change
+          */
-+    /*** DMA controllers ***/
+-        uint64_t offset = timeridx == GTIMER_VIRT ?
-+    pl330_create(EXYNOS4210_PL330_BASE0_ADDR,
+-            cpu->env.cp15.cntvoff_el2 : gt_phys_raw_cnt_offset(&cpu->env);
-+                 qemu_irq_invert(s->irq_table[exynos4210_get_irq(35, 1)]), 32);
++        uint64_t offset = gt_indirect_access_timer_offset(&cpu->env, timeridx);
-+    pl330_create(EXYNOS4210_PL330_BASE1_ADDR,
+         uint64_t count = gt_get_countervalue(&cpu->env);
-+                 qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
+         /* Note that this must be unsigned 64 bit arithmetic: */
-+    pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
+         int istatus = count - offset >= gt->cval;
 +                 qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
 +
      return s;
  }
 --
-.20.1
+.43.0

-[Qemu-devel] [PULL 08/12] hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3
+[PULL 05/21] target/arm: Don't apply CNTVOFF_EL2 for EL2_VIRT timer
-The ICC_CTLR_EL3 register includes some bits which are aliases
+The CNTVOFF_EL2 offset register should only be applied for accessses
-of bits in the ICC_CTLR_EL1(S) and (NS) registers. QEMU chooses
+to CNTVCT_EL0 and for the EL1 virtual timer (CNTV_*).  We were
-to keep those bits in the cs->icc_ctlr_el1[] struct fields.
+incorrectly applying it for the EL2 virtual timer (CNTHV_*).
 Unfortunately a missing '~' in the code to update the bits
 in those fields meant that writing to ICC_CTLR_EL3 would corrupt
 the ICC_CLTR_EL1 register values.
+Cc: qemu-stable@nongnu.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Message-id: 20190520162809.2677-5-peter.maydell@linaro.org
+Message-id: 20250204125009.2281315-3-peter.maydell@linaro.org
 ---
- hw/intc/arm_gicv3_cpuif.c | 4 ++--
+ target/arm/helper.c | 2 --
-file changed, 2 insertions(+), 2 deletions(-)
+file changed, 2 deletions(-)
-diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
+diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_cpuif.c
+--- a/target/arm/helper.c
-+++ b/hw/intc/arm_gicv3_cpuif.c
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
+@@ -XXX,XX +XXX,XX @@ static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
-     trace_gicv3_icc_ctlr_el3_write(gicv3_redist_affid(cs), value);
+     switch (timeridx) {
-     /* *_EL1NS and *_EL1S bits are aliases into the ICC_CTLR_EL1 bits. */
+     case GTIMER_VIRT:
--    cs->icc_ctlr_el1[GICV3_NS] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
+-    case GTIMER_HYPVIRT:
-+    cs->icc_ctlr_el1[GICV3_NS] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
+         offset = gt_virt_cnt_offset(env);
-     if (value & ICC_CTLR_EL3_EOIMODE_EL1NS) {
+         break;
-         cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE;
+     case GTIMER_PHYS:
-     }
+@@ -XXX,XX +XXX,XX @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
-@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
-         cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_CBPR;
+     switch (timeridx) {
-     }
+     case GTIMER_VIRT:
+-    case GTIMER_HYPVIRT:
--    cs->icc_ctlr_el1[GICV3_S] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
+         offset = gt_virt_cnt_offset(env);
-+    cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
+         break;
-     if (value & ICC_CTLR_EL3_EOIMODE_EL1S) {
+     case GTIMER_PHYS:
          cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_EOIMODE;
      }
 --
-.20.1
+.43.0

-[Qemu-devel] [PULL 07/12] hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
+[PULL 06/21] target/arm: Make CNTPS_* UNDEF from Secure EL1 when Secure EL2 is enabled
-In ich_vmcr_write() we enforce "writes of BPR fields to less than
+When we added Secure EL2 support, we missed that this needs an update
-their minimum sets them to the minimum" by doing a "read vbpr and
+to the access code for the EL3 physical timer registers.  These are
-write it back" operation.  A typo here meant that we weren't handling
+supposed to UNDEF from Secure EL1 when Secure EL2 is enabled.
 writes to these fields correctly, because we were reading from VBPR0
 but writing to VBPR1.
+(Note for stable backporting: for backports to branches where
+CP_ACCESS_UNDEFINED is not defined, the old name to use instead
+is CP_ACCESS_TRAP_UNCATEGORIZED.)
+Cc: qemu-stable@nongnu.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
-Message-id: 20190520162809.2677-4-peter.maydell@linaro.org
+Message-id: 20250204125009.2281315-4-peter.maydell@linaro.org
 ---
- hw/intc/arm_gicv3_cpuif.c | 2 +-
+ target/arm/helper.c | 3 +++
-file changed, 1 insertion(+), 1 deletion(-)
+file changed, 3 insertions(+)
-diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
+diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/intc/arm_gicv3_cpuif.c
+--- a/target/arm/helper.c
-+++ b/hw/intc/arm_gicv3_cpuif.c
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static void ich_vmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
+@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_stimer_access(CPUARMState *env,
-     /* Enforce "writing BPRs to less than minimum sets them to the minimum"
+         if (!arm_is_secure(env)) {
-      * by reading and writing back the fields.
+             return CP_ACCESS_UNDEFINED;
-      */
+         }
--    write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G0));
++        if (arm_is_el2_enabled(env)) {
-+    write_vbpr(cs, GICV3_G0, read_vbpr(cs, GICV3_G0));
++            return CP_ACCESS_UNDEFINED;
-     write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G1));
++        }
+         if (!(env->cp15.scr_el3 & SCR_ST)) {
-     gicv3_cpuif_virt_update(cs);
+             return CP_ACCESS_TRAP_EL3;
          }
 --
-.20.1
+.43.0

-[Qemu-devel] [PULL 12/12] hw/arm/exynos4210: QOM'ify the Exynos4210 SoC
+[PULL 07/21] target/arm: Always apply CNTVOFF_EL2 for CNTV_TVAL_EL02 accesses
-From: Philippe Mathieu-Daudé <philmd@redhat.com>
+Currently we handle CNTV_TVAL_EL02 by calling gt_tval_read() for the
 EL1 virt timer.  This is almost correct, but the underlying
 CNTV_TVAL_EL0 register behaves slightly differently.  CNTV_TVAL_EL02
 always applies the CNTVOFF_EL2 offset; CNTV_TVAL_EL0 doesn't do so if
 we're at EL2 and HCR_EL2.E2H is 1.
-Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+We were getting this wrong, because we ended up in
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+gt_virt_cnt_offset() and did the E2H check.
-Message-id: 20190520214342.13709-5-philmd@redhat.com
 Factor out the tval read/write calculation from the selection of the
 offset, so that we can special case gt_virt_tval_read() and
 gt_virt_tval_write() to unconditionally pass CNTVOFF_EL2.
 Cc: qemu-stable@nongnu.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Message-id: 20250204125009.2281315-5-peter.maydell@linaro.org
 ---
- include/hw/arm/exynos4210.h |  9 +++++++--
+ target/arm/helper.c | 36 +++++++++++++++++++++++++++---------
- hw/arm/exynos4210.c         | 28 ++++++++++++++++++++++++----
+file changed, 27 insertions(+), 9 deletions(-)
  hw/arm/exynos4_boards.c     |  9 ++++++---
 files changed, 37 insertions(+), 9 deletions(-)
-diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
+diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/exynos4210.h
+--- a/target/arm/helper.c
-+++ b/include/hw/arm/exynos4210.h
++++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210Irq {
+@@ -XXX,XX +XXX,XX @@ static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
- } Exynos4210Irq;
+     gt_recalc_timer(env_archcpu(env), timeridx);
  typedef struct Exynos4210State {
 +    /*< private >*/
 +    SysBusDevice parent_obj;
 +    /*< public >*/
      ARMCPU *cpu[EXYNOS4210_NCPUS];
      Exynos4210Irq irqs;
      qemu_irq *irq_table;
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210State {
      I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
  } Exynos4210State;
 +#define TYPE_EXYNOS4210_SOC "exynos4210"
 +#define EXYNOS4210_SOC(obj) \
 +    OBJECT_CHECK(Exynos4210State, obj, TYPE_EXYNOS4210_SOC)
 +
  void exynos4210_write_secondary(ARMCPU *cpu,
          const struct arm_boot_info *info);
 -Exynos4210State *exynos4210_init(MemoryRegion *system_mem);
 -
  /* Initialize exynos4210 IRQ subsystem stub */
  qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
 diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/exynos4210.c
 +++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
      sysbus_connect_irq(busdev, 0, irq);
  }
--Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
++static uint64_t do_tval_read(CPUARMState *env, int timeridx, uint64_t offset)
 +static void exynos4210_realize(DeviceState *socdev, Error **errp)
  {
 -    Exynos4210State *s = g_new0(Exynos4210State, 1);
 +    Exynos4210State *s = EXYNOS4210_SOC(socdev);
 +    MemoryRegion *system_mem = get_system_memory();
      qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
      SysBusDevice *busdev;
      DeviceState *dev;
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
                   qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
      pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
                   qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
 -
 -    return s;
  }
 +
 +static void exynos4210_class_init(ObjectClass *klass, void *data)
 +{
-+    DeviceClass *dc = DEVICE_CLASS(klass);
++    return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
-+
++                      (gt_get_countervalue(env) - offset));
 +    dc->realize = exynos4210_realize;
 +}
 +
-+static const TypeInfo exynos4210_info = {
+ static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
-+    .name = TYPE_EXYNOS4210_SOC,
+                              int timeridx)
-+    .parent = TYPE_SYS_BUS_DEVICE,
+ {
-+    .instance_size = sizeof(Exynos4210State),
+@@ -XXX,XX +XXX,XX @@ static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
-+    .class_init = exynos4210_class_init,
+         break;
-+};
+     }
-+
-+static void exynos4210_register_types(void)
+-    return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
-+{
+-                      (gt_get_countervalue(env) - offset));
-+    type_register_static(&exynos4210_info);
++    return do_tval_read(env, timeridx, offset);
 +}
 +
-+type_init(exynos4210_register_types)
++static void do_tval_write(CPUARMState *env, int timeridx, uint64_t value,
-diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
++                          uint64_t offset)
-index XXXXXXX..XXXXXXX 100644
++{
---- a/hw/arm/exynos4_boards.c
++    trace_arm_gt_tval_write(timeridx, value);
-+++ b/hw/arm/exynos4_boards.c
++    env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
-@@ -XXX,XX +XXX,XX @@ typedef enum Exynos4BoardType {
++                                         sextract64(value, 0, 32);
- } Exynos4BoardType;
++    gt_recalc_timer(env_archcpu(env), timeridx);
  typedef struct Exynos4BoardState {
 -    Exynos4210State *soc;
 +    Exynos4210State soc;
      MemoryRegion dram0_mem;
      MemoryRegion dram1_mem;
  } Exynos4BoardState;
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
      exynos4_boards_init_ram(s, get_system_memory(),
                              exynos4_board_ram_size[board_type]);
 -    s->soc = exynos4210_init(get_system_memory());
 +    object_initialize(&s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC);
 +    qdev_set_parent_bus(DEVICE(&s->soc), sysbus_get_default());
 +    object_property_set_bool(OBJECT(&s->soc), true, "realized",
 +                             &error_fatal);
      return s;
  }
-@@ -XXX,XX +XXX,XX @@ static void smdkc210_init(MachineState *machine)
-                                                       EXYNOS4_BOARD_SMDKC210);
+ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
+@@ -XXX,XX +XXX,XX @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
-     lan9215_init(SMDK_LAN9118_BASE_ADDR,
+         offset = gt_phys_cnt_offset(env);
--            qemu_irq_invert(s->soc->irq_table[exynos4210_get_irq(37, 1)]));
+         break;
-+            qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)]));
+     }
-     arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo);
+-
 -    trace_arm_gt_tval_write(timeridx, value);
 -    env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
 -                                         sextract64(value, 0, 32);
 -    gt_recalc_timer(env_archcpu(env), timeridx);
 +    do_tval_write(env, timeridx, value, offset);
  }
+ static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
+@@ -XXX,XX +XXX,XX @@ static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
+ {
+-    return gt_tval_read(env, ri, GTIMER_VIRT);
++    /*
++     * This is CNTV_TVAL_EL02; unlike the underlying CNTV_TVAL_EL0
++     * we always apply CNTVOFF_EL2. Special case that here rather
++     * than going into the generic gt_tval_read() and then having
++     * to re-detect that it's this register.
++     * Note that the accessfn/perms mean we know we're at EL2 or EL3 here.
++     */
++    return do_tval_read(env, GTIMER_VIRT, env->cp15.cntvoff_el2);
+ }
+ static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                                uint64_t value)
+ {
+-    gt_tval_write(env, ri, GTIMER_VIRT, value);
++    /* Similarly for writes to CNTV_TVAL_EL02 */
++    do_tval_write(env, GTIMER_VIRT, value, env->cp15.cntvoff_el2);
+ }
+ static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
 --
-.20.1
+.43.0

-New patch
+[PULL 08/21] target/arm: Refactor handling of timer offset for direct register accesses
+When reading or writing the timer registers, sometimes we need to
 apply one of the timer offsets.  Specifically, this happens for
 direct reads of the counter registers CNTPCT_EL0 and CNTVCT_EL0 (and
 their self-synchronized variants CNTVCTSS_EL0 and CNTPCTSS_EL0).  It
 also applies for direct reads and writes of the CNT*_TVAL_EL*
 registers that provide the 32-bit downcounting view of each timer.
 We currently do this with duplicated code in gt_tval_read() and
 gt_tval_write() and a special-case in gt_virt_cnt_read() and
 gt_cnt_read().  Refactor this so that we handle it all in a single
 function gt_direct_access_timer_offset(), to parallel how we handle
 the offset for indirect accesses.
 The call in the WFIT helper previously to gt_virt_cnt_offset() is
 now to gt_direct_access_timer_offset(); this is the correct
 behaviour, but it's not immediately obvious that it shouldn't be
 considered an indirect access, so we add an explanatory comment.
 This commit should make no behavioural changes.
 (Cc to stable because the following bugfix commit will
 depend on this one.)
 Cc: qemu-stable@nongnu.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Message-id: 20250204125009.2281315-6-peter.maydell@linaro.org
 ---
  target/arm/internals.h     |   5 +-
  target/arm/helper.c        | 103 +++++++++++++++++++------------------
  target/arm/tcg/op_helper.c |   8 ++-
 files changed, 62 insertions(+), 54 deletions(-)
 diff --git a/target/arm/internals.h b/target/arm/internals.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/internals.h
 +++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ int delete_hw_watchpoint(target_ulong addr, target_ulong len, int type);
  uint64_t gt_get_countervalue(CPUARMState *env);
  /*
   * Return the currently applicable offset between the system counter
 - * and CNTVCT_EL0 (this will be either 0 or the value of CNTVOFF_EL2).
 + * and the counter for the specified timer, as used for direct register
 + * accesses.
   */
 -uint64_t gt_virt_cnt_offset(CPUARMState *env);
 +uint64_t gt_direct_access_timer_offset(CPUARMState *env, int timeridx);
  /*
   * Return mask of ARMMMUIdxBit values corresponding to an "invalidate
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static uint64_t gt_phys_raw_cnt_offset(CPUARMState *env)
      return 0;
  }
 -static uint64_t gt_phys_cnt_offset(CPUARMState *env)
 -{
 -    if (arm_current_el(env) >= 2) {
 -        return 0;
 -    }
 -    return gt_phys_raw_cnt_offset(env);
 -}
 -
  static uint64_t gt_indirect_access_timer_offset(CPUARMState *env, int timeridx)
  {
      /*
@@ -XXX,XX +XXX,XX @@ static uint64_t gt_indirect_access_timer_offset(CPUARMState *env, int timeridx)
      }
  }
 +uint64_t gt_direct_access_timer_offset(CPUARMState *env, int timeridx)
 +{
 +    /*
 +     * Return the timer offset to use for direct accesses to the
 +     * counter registers CNTPCT and CNTVCT, and for direct accesses
 +     * to the CNT*_TVAL registers.
 +     *
 +     * This isn't exactly the same as the indirect-access offset,
 +     * because here we also care about what EL the register access
 +     * is being made from.
 +     *
 +     * This corresponds to the access pseudocode for the registers.
 +     */
 +    uint64_t hcr;
 +
 +    switch (timeridx) {
 +    case GTIMER_PHYS:
 +        if (arm_current_el(env) >= 2) {
 +            return 0;
 +        }
 +        return gt_phys_raw_cnt_offset(env);
 +    case GTIMER_VIRT:
 +        switch (arm_current_el(env)) {
 +        case 2:
 +            hcr = arm_hcr_el2_eff(env);
 +            if (hcr & HCR_E2H) {
 +                return 0;
 +            }
 +            break;
 +        case 0:
 +            hcr = arm_hcr_el2_eff(env);
 +            if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
 +                return 0;
 +            }
 +            break;
 +        }
 +        return env->cp15.cntvoff_el2;
 +    case GTIMER_HYP:
 +    case GTIMER_SEC:
 +    case GTIMER_HYPVIRT:
 +        return 0;
 +    default:
 +        g_assert_not_reached();
 +    }
 +}
 +
  static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
  {
      ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
@@ -XXX,XX +XXX,XX @@ static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
  static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
  {
 -    return gt_get_countervalue(env) - gt_phys_cnt_offset(env);
 -}
 -
 -uint64_t gt_virt_cnt_offset(CPUARMState *env)
 -{
 -    uint64_t hcr;
 -
 -    switch (arm_current_el(env)) {
 -    case 2:
 -        hcr = arm_hcr_el2_eff(env);
 -        if (hcr & HCR_E2H) {
 -            return 0;
 -        }
 -        break;
 -    case 0:
 -        hcr = arm_hcr_el2_eff(env);
 -        if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
 -            return 0;
 -        }
 -        break;
 -    }
 -
 -    return env->cp15.cntvoff_el2;
 +    uint64_t offset = gt_direct_access_timer_offset(env, GTIMER_PHYS);
 +    return gt_get_countervalue(env) - offset;
  }
  static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
  {
 -    return gt_get_countervalue(env) - gt_virt_cnt_offset(env);
 +    uint64_t offset = gt_direct_access_timer_offset(env, GTIMER_VIRT);
 +    return gt_get_countervalue(env) - offset;
  }
  static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static uint64_t do_tval_read(CPUARMState *env, int timeridx, uint64_t offset)
  static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
                               int timeridx)
  {
 -    uint64_t offset = 0;
 -
 -    switch (timeridx) {
 -    case GTIMER_VIRT:
 -        offset = gt_virt_cnt_offset(env);
 -        break;
 -    case GTIMER_PHYS:
 -        offset = gt_phys_cnt_offset(env);
 -        break;
 -    }
 +    uint64_t offset = gt_direct_access_timer_offset(env, timeridx);
      return do_tval_read(env, timeridx, offset);
  }
@@ -XXX,XX +XXX,XX @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
                            int timeridx,
                            uint64_t value)
  {
 -    uint64_t offset = 0;
 +    uint64_t offset = gt_direct_access_timer_offset(env, timeridx);
 -    switch (timeridx) {
 -    case GTIMER_VIRT:
 -        offset = gt_virt_cnt_offset(env);
 -        break;
 -    case GTIMER_PHYS:
 -        offset = gt_phys_cnt_offset(env);
 -        break;
 -    }
      do_tval_write(env, timeridx, value, offset);
  }
 diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/tcg/op_helper.c
 +++ b/target/arm/tcg/op_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(wfit)(CPUARMState *env, uint64_t timeout)
      int target_el = check_wfx_trap(env, false, &excp);
      /* The WFIT should time out when CNTVCT_EL0 >= the specified value. */
      uint64_t cntval = gt_get_countervalue(env);
 -    uint64_t offset = gt_virt_cnt_offset(env);
 +    /*
 +     * We want the value that we would get if we read CNTVCT_EL0 from
 +     * the current exception level, so the direct_access offset, not
 +     * the indirect_access one. Compare the pseudocode LocalTimeoutEvent(),
 +     * which calls VirtualCounterTimer().
 +     */
 +    uint64_t offset = gt_direct_access_timer_offset(env, GTIMER_VIRT);
      uint64_t cntvct = cntval - offset;
      uint64_t nexttick;
 --
 .43.0

-[Qemu-devel] [PULL 05/12] arm: Remove unnecessary includes of hw/arm/arm.h
+[PULL 09/21] target/arm: Implement SEL2 physical and virtual timers
-The hw/arm/arm.h header now only includes declarations relating
+From: Alex Bennée <alex.bennee@linaro.org>
-to boot.c code, so it is only needed by Arm board or SoC code.
-Remove some unnecessary inclusions of it from target/arm files
+When FEAT_SEL2 was implemented the SEL2 timers were missed. This
-and from hw/intc/armv7m_nvic.c.
+shows up when building the latest Hafnium with SPMC_AT_EL=2. The
+actual implementation utilises the same logic as the rest of the
 timers so all we need to do is:
   - define the timers and their access functions
   - conditionally add the correct system registers
   - create a new accessfn as the rules are subtly different to the
     existing secure timer
 Fixes: e9152ee91c (target/arm: add ARMv8.4-SEL2 system registers)
 Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Message-id: 20250204125009.2281315-7-peter.maydell@linaro.org
-Message-id: 20190516163857.6430-3-peter.maydell@linaro.org
+Cc: qemu-stable@nongnu.org
 Cc: Andrei Homescu <ahomescu@google.com>
 Cc: Arve Hjønnevåg <arve@google.com>
 Cc: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
 [PMM: CP_ACCESS_TRAP_UNCATEGORIZED -> CP_ACCESS_UNDEFINED;
  offset logic now in gt_{indirect,direct}_access_timer_offset() ]
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/intc/armv7m_nvic.c | 1 -
+ include/hw/arm/bsa.h |   2 +
- target/arm/arm-semi.c | 1 -
+ target/arm/cpu.h     |   2 +
- target/arm/cpu.c      | 1 -
+ target/arm/gtimer.h  |   4 +-
- target/arm/cpu64.c    | 1 -
+ target/arm/cpu.c     |   4 ++
- target/arm/kvm.c      | 1 -
+ target/arm/helper.c  | 163 +++++++++++++++++++++++++++++++++++++++++++
- target/arm/kvm32.c    | 1 -
+files changed, 174 insertions(+), 1 deletion(-)
- target/arm/kvm64.c    | 1 -
-files changed, 7 deletions(-)
+diff --git a/include/hw/arm/bsa.h b/include/hw/arm/bsa.h
+index XXXXXXX..XXXXXXX 100644
-diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
+--- a/include/hw/arm/bsa.h
-index XXXXXXX..XXXXXXX 100644
++++ b/include/hw/arm/bsa.h
 --- a/hw/intc/armv7m_nvic.c
 +++ b/hw/intc/armv7m_nvic.c
 @@ -XXX,XX +XXX,XX @@
- #include "cpu.h"
+ #define QEMU_ARM_BSA_H
- #include "hw/sysbus.h"
- #include "qemu/timer.h"
+ /* These are architectural INTID values */
--#include "hw/arm/arm.h"
++#define ARCH_TIMER_S_EL2_VIRT_IRQ  19
- #include "hw/intc/armv7m_nvic.h"
++#define ARCH_TIMER_S_EL2_IRQ       20
- #include "target/arm/cpu.h"
+ #define VIRTUAL_PMU_IRQ            23
- #include "exec/exec-all.h"
+ #define ARCH_GIC_MAINT_IRQ         25
-diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
+ #define ARCH_TIMER_NS_EL2_IRQ      26
-index XXXXXXX..XXXXXXX 100644
+diff --git a/target/arm/cpu.h b/target/arm/cpu.h
---- a/target/arm/arm-semi.c
+index XXXXXXX..XXXXXXX 100644
-+++ b/target/arm/arm-semi.c
+--- a/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@
++++ b/target/arm/cpu.h
- #else
+@@ -XXX,XX +XXX,XX @@ void arm_gt_vtimer_cb(void *opaque);
- #include "qemu-common.h"
+ void arm_gt_htimer_cb(void *opaque);
- #include "exec/gdbstub.h"
+ void arm_gt_stimer_cb(void *opaque);
--#include "hw/arm/arm.h"
+ void arm_gt_hvtimer_cb(void *opaque);
- #include "qemu/cutils.h"
++void arm_gt_sel2timer_cb(void *opaque);
 +void arm_gt_sel2vtimer_cb(void *opaque);
  unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
  void gt_rme_post_el_change(ARMCPU *cpu, void *opaque);
 diff --git a/target/arm/gtimer.h b/target/arm/gtimer.h
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/gtimer.h
 +++ b/target/arm/gtimer.h
@@ -XXX,XX +XXX,XX @@ enum {
      GTIMER_HYP      = 2,
      GTIMER_SEC      = 3,
      GTIMER_HYPVIRT  = 4,
 -#define NUM_GTIMERS   5
 +    GTIMER_S_EL2_PHYS = 5, /* CNTHPS_* ; only if FEAT_SEL2 */
 +    GTIMER_S_EL2_VIRT = 6, /* CNTHVS_* ; only if FEAT_SEL2 */
 +#define NUM_GTIMERS   7
  };
  #endif
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
- #if !defined(CONFIG_USER_ONLY)
+                                               arm_gt_stimer_cb, cpu);
- #include "hw/loader.h"
+         cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
                                                    arm_gt_hvtimer_cb, cpu);
 +        cpu->gt_timer[GTIMER_S_EL2_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
 +                                                     arm_gt_sel2timer_cb, cpu);
 +        cpu->gt_timer[GTIMER_S_EL2_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
 +                                                     arm_gt_sel2vtimer_cb, cpu);
      }
  #endif
--#include "hw/arm/arm.h"
- #include "sysemu/sysemu.h"
+diff --git a/target/arm/helper.c b/target/arm/helper.c
- #include "sysemu/hw_accel.h"
+index XXXXXXX..XXXXXXX 100644
- #include "kvm_arm.h"
+--- a/target/arm/helper.c
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
++++ b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
+@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_stimer_access(CPUARMState *env,
---- a/target/arm/cpu64.c
+     }
-+++ b/target/arm/cpu64.c
+ }
-@@ -XXX,XX +XXX,XX @@
- #if !defined(CONFIG_USER_ONLY)
++static CPAccessResult gt_sel2timer_access(CPUARMState *env,
- #include "hw/loader.h"
++                                          const ARMCPRegInfo *ri,
- #endif
++                                          bool isread)
--#include "hw/arm/arm.h"
++{
- #include "sysemu/sysemu.h"
++    /*
- #include "sysemu/kvm.h"
++     * The AArch64 register view of the secure EL2 timers are mostly
- #include "kvm_arm.h"
++     * accessible from EL3 and EL2 although can also be trapped to EL2
-diff --git a/target/arm/kvm.c b/target/arm/kvm.c
++     * from EL1 depending on nested virt config.
-index XXXXXXX..XXXXXXX 100644
++     */
---- a/target/arm/kvm.c
++    switch (arm_current_el(env)) {
-+++ b/target/arm/kvm.c
++    case 0: /* UNDEFINED */
-@@ -XXX,XX +XXX,XX @@
++        return CP_ACCESS_UNDEFINED;
- #include "cpu.h"
++    case 1:
- #include "trace.h"
++        if (!arm_is_secure(env)) {
- #include "internals.h"
++            /* UNDEFINED */
--#include "hw/arm/arm.h"
++            return CP_ACCESS_UNDEFINED;
- #include "hw/pci/pci.h"
++        } else if (arm_hcr_el2_eff(env) & HCR_NV) {
- #include "exec/memattrs.h"
++            /* Aarch64.SystemAccessTrap(EL2, 0x18) */
- #include "exec/address-spaces.h"
++            return CP_ACCESS_TRAP_EL2;
-diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
++        }
-index XXXXXXX..XXXXXXX 100644
++        /* UNDEFINED */
---- a/target/arm/kvm32.c
++        return CP_ACCESS_UNDEFINED;
-+++ b/target/arm/kvm32.c
++    case 2:
-@@ -XXX,XX +XXX,XX @@
++        if (!arm_is_secure(env)) {
- #include "sysemu/kvm.h"
++            /* UNDEFINED */
- #include "kvm_arm.h"
++            return CP_ACCESS_UNDEFINED;
- #include "internals.h"
++        }
--#include "hw/arm/arm.h"
++        return CP_ACCESS_OK;
- #include "qemu/log.h"
++    case 3:
++        if (env->cp15.scr_el3 & SCR_EEL2) {
- static inline void set_feature(uint64_t *features, int feature)
++            return CP_ACCESS_OK;
-diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
++        } else {
-index XXXXXXX..XXXXXXX 100644
++            return CP_ACCESS_UNDEFINED;
---- a/target/arm/kvm64.c
++        }
-+++ b/target/arm/kvm64.c
++    default:
-@@ -XXX,XX +XXX,XX @@
++        g_assert_not_reached();
- #include "sysemu/kvm.h"
++    }
- #include "kvm_arm.h"
++}
- #include "internals.h"
++
--#include "hw/arm/arm.h"
+ uint64_t gt_get_countervalue(CPUARMState *env)
+ {
- static bool have_guest_debug;
+     ARMCPU *cpu = env_archcpu(env);
+@@ -XXX,XX +XXX,XX @@ static uint64_t gt_indirect_access_timer_offset(CPUARMState *env, int timeridx)
      case GTIMER_HYP:
      case GTIMER_SEC:
      case GTIMER_HYPVIRT:
 +    case GTIMER_S_EL2_PHYS:
 +    case GTIMER_S_EL2_VIRT:
          return 0;
      default:
          g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ uint64_t gt_direct_access_timer_offset(CPUARMState *env, int timeridx)
      case GTIMER_HYP:
      case GTIMER_SEC:
      case GTIMER_HYPVIRT:
 +    case GTIMER_S_EL2_PHYS:
 +    case GTIMER_S_EL2_VIRT:
          return 0;
      default:
          g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
      gt_ctl_write(env, ri, GTIMER_SEC, value);
  }
 +static void gt_sec_pel2_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
 +{
 +    gt_timer_reset(env, ri, GTIMER_S_EL2_PHYS);
 +}
 +
 +static void gt_sec_pel2_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
 +                                   uint64_t value)
 +{
 +    gt_cval_write(env, ri, GTIMER_S_EL2_PHYS, value);
 +}
 +
 +static uint64_t gt_sec_pel2_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
 +{
 +    return gt_tval_read(env, ri, GTIMER_S_EL2_PHYS);
 +}
 +
 +static void gt_sec_pel2_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
 +                              uint64_t value)
 +{
 +    gt_tval_write(env, ri, GTIMER_S_EL2_PHYS, value);
 +}
 +
 +static void gt_sec_pel2_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
 +                              uint64_t value)
 +{
 +    gt_ctl_write(env, ri, GTIMER_S_EL2_PHYS, value);
 +}
 +
 +static void gt_sec_vel2_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
 +{
 +    gt_timer_reset(env, ri, GTIMER_S_EL2_VIRT);
 +}
 +
 +static void gt_sec_vel2_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
 +                              uint64_t value)
 +{
 +    gt_cval_write(env, ri, GTIMER_S_EL2_VIRT, value);
 +}
 +
 +static uint64_t gt_sec_vel2_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
 +{
 +    return gt_tval_read(env, ri, GTIMER_S_EL2_VIRT);
 +}
 +
 +static void gt_sec_vel2_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
 +                                   uint64_t value)
 +{
 +    gt_tval_write(env, ri, GTIMER_S_EL2_VIRT, value);
 +}
 +
 +static void gt_sec_vel2_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
 +                              uint64_t value)
 +{
 +    gt_ctl_write(env, ri, GTIMER_S_EL2_VIRT, value);
 +}
 +
  static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
  {
      gt_timer_reset(env, ri, GTIMER_HYPVIRT);
@@ -XXX,XX +XXX,XX @@ void arm_gt_stimer_cb(void *opaque)
      gt_recalc_timer(cpu, GTIMER_SEC);
  }
 +void arm_gt_sel2timer_cb(void *opaque)
 +{
 +    ARMCPU *cpu = opaque;
 +
 +    gt_recalc_timer(cpu, GTIMER_S_EL2_PHYS);
 +}
 +
 +void arm_gt_sel2vtimer_cb(void *opaque)
 +{
 +    ARMCPU *cpu = opaque;
 +
 +    gt_recalc_timer(cpu, GTIMER_S_EL2_VIRT);
 +}
 +
  void arm_gt_hvtimer_cb(void *opaque)
  {
      ARMCPU *cpu = opaque;
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] = {
        .access = PL2_RW, .accessfn = sel2_access,
        .nv2_redirect_offset = 0x48,
        .fieldoffset = offsetof(CPUARMState, cp15.vstcr_el2) },
 +#ifndef CONFIG_USER_ONLY
 +    /* Secure EL2 Physical Timer */
 +    { .name = "CNTHPS_TVAL_EL2", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 5, .opc2 = 0,
 +      .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW,
 +      .accessfn = gt_sel2timer_access,
 +      .readfn = gt_sec_pel2_tval_read,
 +      .writefn = gt_sec_pel2_tval_write,
 +      .resetfn = gt_sec_pel2_timer_reset,
 +    },
 +    { .name = "CNTHPS_CTL_EL2", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 5, .opc2 = 1,
 +      .type = ARM_CP_IO, .access = PL2_RW,
 +      .accessfn = gt_sel2timer_access,
 +      .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_S_EL2_PHYS].ctl),
 +      .resetvalue = 0,
 +      .writefn = gt_sec_pel2_ctl_write, .raw_writefn = raw_write,
 +    },
 +    { .name = "CNTHPS_CVAL_EL2", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 5, .opc2 = 2,
 +      .type = ARM_CP_IO, .access = PL2_RW,
 +      .accessfn = gt_sel2timer_access,
 +      .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_S_EL2_PHYS].cval),
 +      .writefn = gt_sec_pel2_cval_write, .raw_writefn = raw_write,
 +    },
 +    /* Secure EL2 Virtual Timer */
 +    { .name = "CNTHVS_TVAL_EL2", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 4, .opc2 = 0,
 +      .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW,
 +      .accessfn = gt_sel2timer_access,
 +      .readfn = gt_sec_vel2_tval_read,
 +      .writefn = gt_sec_vel2_tval_write,
 +      .resetfn = gt_sec_vel2_timer_reset,
 +    },
 +    { .name = "CNTHVS_CTL_EL2", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 4, .opc2 = 1,
 +      .type = ARM_CP_IO, .access = PL2_RW,
 +      .accessfn = gt_sel2timer_access,
 +      .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_S_EL2_VIRT].ctl),
 +      .resetvalue = 0,
 +      .writefn = gt_sec_vel2_ctl_write, .raw_writefn = raw_write,
 +    },
 +    { .name = "CNTHVS_CVAL_EL2", .state = ARM_CP_STATE_AA64,
 +      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 4, .opc2 = 2,
 +      .type = ARM_CP_IO, .access = PL2_RW,
 +      .accessfn = gt_sel2timer_access,
 +      .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_S_EL2_VIRT].cval),
 +      .writefn = gt_sec_vel2_cval_write, .raw_writefn = raw_write,
 +    },
 +#endif
  };
  static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
 --
-.20.1
+.43.0

-[Qemu-devel] [PULL 09/12] hw/arm/exynos4: Remove unuseful debug code
+[PULL 10/21] target/arm: Document the architectural names of our GTIMERs
-From: Philippe Mathieu-Daudé <philmd@redhat.com>
+From: Alex Bennée <alex.bennee@linaro.org>
-Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+As we are about to add more physical and virtual timers let's make it
-Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+clear what each timer does.
-Message-id: 20190520214342.13709-2-philmd@redhat.com
 Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Message-id: 20250204125009.2281315-8-peter.maydell@linaro.org
 [PMM: Add timer register name prefix to each comment]
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- hw/arm/exynos4_boards.c | 24 ------------------------
+ target/arm/gtimer.h | 10 +++++-----
-file changed, 24 deletions(-)
+file changed, 5 insertions(+), 5 deletions(-)
-diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
+diff --git a/target/arm/gtimer.h b/target/arm/gtimer.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/exynos4_boards.c
+--- a/target/arm/gtimer.h
-+++ b/hw/arm/exynos4_boards.c
++++ b/target/arm/gtimer.h
 @@ -XXX,XX +XXX,XX @@
- #include "hw/net/lan9118.h"
+ #define TARGET_ARM_GTIMER_H
- #include "hw/boards.h"
+ enum {
--#undef DEBUG
+-    GTIMER_PHYS     = 0,
--
+-    GTIMER_VIRT     = 1,
--//#define DEBUG
+-    GTIMER_HYP      = 2,
--
+-    GTIMER_SEC      = 3,
--#ifdef DEBUG
+-    GTIMER_HYPVIRT  = 4,
--    #undef PRINT_DEBUG
++    GTIMER_PHYS     = 0, /* CNTP_* ; EL1 physical timer */
--    #define  PRINT_DEBUG(fmt, args...) \
++    GTIMER_VIRT     = 1, /* CNTV_* ; EL1 virtual timer */
--        do { \
++    GTIMER_HYP      = 2, /* CNTHP_* ; EL2 physical timer */
--            fprintf(stderr, "  [%s:%d]   "fmt, __func__, __LINE__, ##args); \
++    GTIMER_SEC      = 3, /* CNTPS_* ; EL3 physical timer */
--        } while (0)
++    GTIMER_HYPVIRT  = 4, /* CNTHV_* ; EL2 virtual timer ; only if FEAT_VHE */
--#else
+     GTIMER_S_EL2_PHYS = 5, /* CNTHPS_* ; only if FEAT_SEL2 */
--    #define  PRINT_DEBUG(fmt, args...)  do {} while (0)
+     GTIMER_S_EL2_VIRT = 6, /* CNTHVS_* ; only if FEAT_SEL2 */
--#endif
+ #define NUM_GTIMERS   7
 -
  #define SMDK_LAN9118_BASE_ADDR      0x05000000
  typedef enum Exynos4BoardType {
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
      exynos4_board_binfo.gic_cpu_if_addr =
              EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100;
 -    PRINT_DEBUG("\n ram_size: %luMiB [0x%08lx]\n"
 -            " kernel_filename: %s\n"
 -            " kernel_cmdline: %s\n"
 -            " initrd_filename: %s\n",
 -            exynos4_board_ram_size[board_type] / 1048576,
 -            exynos4_board_ram_size[board_type],
 -            machine->kernel_filename,
 -            machine->kernel_cmdline,
 -            machine->initrd_filename);
 -
      exynos4_boards_init_ram(s, get_system_memory(),
                              exynos4_board_ram_size[board_type]);
 --
-.20.1
+.43.0

-[Qemu-devel] [PULL 06/12] arm: Rename hw/arm/arm.h to hw/arm/boot.h
+[PULL 11/21] hw/arm: enable secure EL2 timers for virt machine
-The header file hw/arm/arm.h now includes only declarations
+From: Alex Bennée <alex.bennee@linaro.org>
 relating to hw/arm/boot.c functionality. Rename it accordingly,
 and adjust its header comment.
-The bulk of this commit was created via
+Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
- perl -pi -e 's|hw/arm/arm.h|hw/arm/boot.h|' hw/arm/*.c include/hw/arm/*.h
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Message-id: 20250204125009.2281315-9-peter.maydell@linaro.org
 Cc: qemu-stable@nongnu.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
  hw/arm/virt.c | 2 ++
 file changed, 2 insertions(+)
-In a few cases we can just delete the #include:
-hw/arm/msf2-soc.c, include/hw/arm/aspeed_soc.h and
-include/hw/arm/bcm2836.h did not require it.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Message-id: 20190516163857.6430-4-peter.maydell@linaro.org
----
- include/hw/arm/allwinner-a10.h   | 2 +-
- include/hw/arm/aspeed_soc.h      | 1 -
- include/hw/arm/bcm2836.h         | 1 -
- include/hw/arm/{arm.h => boot.h} | 8 ++++----
- include/hw/arm/fsl-imx25.h       | 2 +-
- include/hw/arm/fsl-imx31.h       | 2 +-
- include/hw/arm/fsl-imx6.h        | 2 +-
- include/hw/arm/fsl-imx6ul.h      | 2 +-
- include/hw/arm/fsl-imx7.h        | 2 +-
- include/hw/arm/virt.h            | 2 +-
- include/hw/arm/xlnx-versal.h     | 2 +-
- include/hw/arm/xlnx-zynqmp.h     | 2 +-
- hw/arm/armsse.c                  | 2 +-
- hw/arm/armv7m.c                  | 2 +-
- hw/arm/aspeed.c                  | 2 +-
- hw/arm/boot.c                    | 2 +-
- hw/arm/collie.c                  | 2 +-
- hw/arm/exynos4210.c              | 2 +-
- hw/arm/exynos4_boards.c          | 2 +-
- hw/arm/highbank.c                | 2 +-
- hw/arm/integratorcp.c            | 2 +-
- hw/arm/mainstone.c               | 2 +-
- hw/arm/microbit.c                | 2 +-
- hw/arm/mps2-tz.c                 | 2 +-
- hw/arm/mps2.c                    | 2 +-
- hw/arm/msf2-soc.c                | 1 -
- hw/arm/msf2-som.c                | 2 +-
- hw/arm/musca.c                   | 2 +-
- hw/arm/musicpal.c                | 2 +-
- hw/arm/netduino2.c               | 2 +-
- hw/arm/nrf51_soc.c               | 2 +-
- hw/arm/nseries.c                 | 2 +-
- hw/arm/omap1.c                   | 2 +-
- hw/arm/omap2.c                   | 2 +-
- hw/arm/omap_sx1.c                | 2 +-
- hw/arm/palm.c                    | 2 +-
- hw/arm/raspi.c                   | 2 +-
- hw/arm/realview.c                | 2 +-
- hw/arm/spitz.c                   | 2 +-
- hw/arm/stellaris.c               | 2 +-
- hw/arm/stm32f205_soc.c           | 2 +-
- hw/arm/strongarm.c               | 2 +-
- hw/arm/tosa.c                    | 2 +-
- hw/arm/versatilepb.c             | 2 +-
- hw/arm/vexpress.c                | 2 +-
- hw/arm/virt.c                    | 2 +-
- hw/arm/xilinx_zynq.c             | 2 +-
- hw/arm/xlnx-versal.c             | 2 +-
- hw/arm/z2.c                      | 2 +-
-files changed, 49 insertions(+), 52 deletions(-)
- rename include/hw/arm/{arm.h => boot.h} (98%)
-diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/allwinner-a10.h
-+++ b/include/hw/arm/allwinner-a10.h
-@@ -XXX,XX +XXX,XX @@
- #include "qemu-common.h"
- #include "qemu/error-report.h"
- #include "hw/char/serial.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/timer/allwinner-a10-pit.h"
- #include "hw/intc/allwinner-a10-pic.h"
- #include "hw/net/allwinner_emac.h"
-diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/aspeed_soc.h
-+++ b/include/hw/arm/aspeed_soc.h
-@@ -XXX,XX +XXX,XX @@
- #ifndef ASPEED_SOC_H
- #define ASPEED_SOC_H
--#include "hw/arm/arm.h"
- #include "hw/intc/aspeed_vic.h"
- #include "hw/misc/aspeed_scu.h"
- #include "hw/misc/aspeed_sdmc.h"
-diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/bcm2836.h
-+++ b/include/hw/arm/bcm2836.h
-@@ -XXX,XX +XXX,XX @@
- #ifndef BCM2836_H
- #define BCM2836_H
--#include "hw/arm/arm.h"
- #include "hw/arm/bcm2835_peripherals.h"
- #include "hw/intc/bcm2836_control.h"
-diff --git a/include/hw/arm/arm.h b/include/hw/arm/boot.h
-similarity index 98%
-rename from include/hw/arm/arm.h
-rename to include/hw/arm/boot.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/arm.h
-+++ b/include/hw/arm/boot.h
-@@ -XXX,XX +XXX,XX @@
- /*
-- * Misc ARM declarations
-+ * ARM kernel loader.
-  *
-  * Copyright (c) 2006 CodeSourcery.
-  * Written by Paul Brook
-@@ -XXX,XX +XXX,XX @@
-  *
-  */
--#ifndef HW_ARM_H
--#define HW_ARM_H
-+#ifndef HW_ARM_BOOT_H
-+#define HW_ARM_BOOT_H
- #include "exec/memory.h"
- #include "target/arm/cpu-qom.h"
-@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
-                                             const struct arm_boot_info *info,
-                                             hwaddr mvbar_addr);
--#endif /* HW_ARM_H */
-+#endif /* HW_ARM_BOOT_H */
-diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/fsl-imx25.h
-+++ b/include/hw/arm/fsl-imx25.h
-@@ -XXX,XX +XXX,XX @@
- #ifndef FSL_IMX25_H
- #define FSL_IMX25_H
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/intc/imx_avic.h"
- #include "hw/misc/imx25_ccm.h"
- #include "hw/char/imx_serial.h"
-diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/fsl-imx31.h
-+++ b/include/hw/arm/fsl-imx31.h
-@@ -XXX,XX +XXX,XX @@
- #ifndef FSL_IMX31_H
- #define FSL_IMX31_H
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/intc/imx_avic.h"
- #include "hw/misc/imx31_ccm.h"
- #include "hw/char/imx_serial.h"
-diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/fsl-imx6.h
-+++ b/include/hw/arm/fsl-imx6.h
-@@ -XXX,XX +XXX,XX @@
- #ifndef FSL_IMX6_H
- #define FSL_IMX6_H
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/cpu/a9mpcore.h"
- #include "hw/misc/imx6_ccm.h"
- #include "hw/misc/imx6_src.h"
-diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/fsl-imx6ul.h
-+++ b/include/hw/arm/fsl-imx6ul.h
-@@ -XXX,XX +XXX,XX @@
- #ifndef FSL_IMX6UL_H
- #define FSL_IMX6UL_H
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/cpu/a15mpcore.h"
- #include "hw/misc/imx6ul_ccm.h"
- #include "hw/misc/imx6_src.h"
-diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/fsl-imx7.h
-+++ b/include/hw/arm/fsl-imx7.h
-@@ -XXX,XX +XXX,XX @@
- #ifndef FSL_IMX7_H
- #define FSL_IMX7_H
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/cpu/a15mpcore.h"
- #include "hw/intc/imx_gpcv2.h"
- #include "hw/misc/imx7_ccm.h"
-diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/virt.h
-+++ b/include/hw/arm/virt.h
-@@ -XXX,XX +XXX,XX @@
- #include "exec/hwaddr.h"
- #include "qemu/notify.h"
- #include "hw/boards.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/block/flash.h"
- #include "sysemu/kvm.h"
- #include "hw/intc/arm_gicv3_common.h"
-diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/xlnx-versal.h
-+++ b/include/hw/arm/xlnx-versal.h
-@@ -XXX,XX +XXX,XX @@
- #define XLNX_VERSAL_H
- #include "hw/sysbus.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/intc/arm_gicv3.h"
- #define TYPE_XLNX_VERSAL "xlnx-versal"
-diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/xlnx-zynqmp.h
-+++ b/include/hw/arm/xlnx-zynqmp.h
-@@ -XXX,XX +XXX,XX @@
- #ifndef XLNX_ZYNQMP_H
- #include "qemu-common.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/intc/arm_gic.h"
- #include "hw/net/cadence_gem.h"
- #include "hw/char/cadence_uart.h"
-diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/armsse.c
-+++ b/hw/arm/armsse.c
-@@ -XXX,XX +XXX,XX @@
- #include "hw/sysbus.h"
- #include "hw/registerfields.h"
- #include "hw/arm/armsse.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- /* Format of the System Information block SYS_CONFIG register */
- typedef enum SysConfigFormat {
-diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/armv7m.c
-+++ b/hw/arm/armv7m.c
-@@ -XXX,XX +XXX,XX @@
- #include "qemu-common.h"
- #include "cpu.h"
- #include "hw/sysbus.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/loader.h"
- #include "elf.h"
- #include "sysemu/qtest.h"
-diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/aspeed.c
-+++ b/hw/arm/aspeed.c
-@@ -XXX,XX +XXX,XX @@
- #include "qemu-common.h"
- #include "cpu.h"
- #include "exec/address-spaces.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/arm/aspeed.h"
- #include "hw/arm/aspeed_soc.h"
- #include "hw/boards.h"
-diff --git a/hw/arm/boot.c b/hw/arm/boot.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/boot.c
-+++ b/hw/arm/boot.c
-@@ -XXX,XX +XXX,XX @@
- #include "qapi/error.h"
- #include <libfdt.h>
- #include "hw/hw.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/arm/linux-boot-if.h"
- #include "sysemu/kvm.h"
- #include "sysemu/sysemu.h"
-diff --git a/hw/arm/collie.c b/hw/arm/collie.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/collie.c
-+++ b/hw/arm/collie.c
-@@ -XXX,XX +XXX,XX @@
- #include "hw/sysbus.h"
- #include "hw/boards.h"
- #include "strongarm.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/block/flash.h"
- #include "exec/address-spaces.h"
- #include "cpu.h"
-diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/exynos4210.c
-+++ b/hw/arm/exynos4210.c
-@@ -XXX,XX +XXX,XX @@
- #include "hw/boards.h"
- #include "sysemu/sysemu.h"
- #include "hw/sysbus.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/loader.h"
- #include "hw/arm/exynos4210.h"
- #include "hw/sd/sdhci.h"
-diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/exynos4_boards.c
-+++ b/hw/arm/exynos4_boards.c
-@@ -XXX,XX +XXX,XX @@
- #include "sysemu/sysemu.h"
- #include "hw/sysbus.h"
- #include "net/net.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "exec/address-spaces.h"
- #include "hw/arm/exynos4210.h"
- #include "hw/net/lan9118.h"
-diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/highbank.c
-+++ b/hw/arm/highbank.c
-@@ -XXX,XX +XXX,XX @@
- #include "qemu/osdep.h"
- #include "qapi/error.h"
- #include "hw/sysbus.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/loader.h"
- #include "net/net.h"
- #include "sysemu/kvm.h"
-diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/integratorcp.c
-+++ b/hw/arm/integratorcp.c
-@@ -XXX,XX +XXX,XX @@
- #include "cpu.h"
- #include "hw/sysbus.h"
- #include "hw/boards.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/misc/arm_integrator_debug.h"
- #include "hw/net/smc91c111.h"
- #include "net/net.h"
-diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/mainstone.c
-+++ b/hw/arm/mainstone.c
-@@ -XXX,XX +XXX,XX @@
- #include "qapi/error.h"
- #include "hw/hw.h"
- #include "hw/arm/pxa.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "net/net.h"
- #include "hw/net/smc91c111.h"
- #include "hw/boards.h"
-diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/microbit.c
-+++ b/hw/arm/microbit.c
-@@ -XXX,XX +XXX,XX @@
- #include "qemu/osdep.h"
- #include "qapi/error.h"
- #include "hw/boards.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "sysemu/sysemu.h"
- #include "exec/address-spaces.h"
-diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/mps2-tz.c
-+++ b/hw/arm/mps2-tz.c
-@@ -XXX,XX +XXX,XX @@
- #include "qemu/osdep.h"
- #include "qapi/error.h"
- #include "qemu/error-report.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/arm/armv7m.h"
- #include "hw/or-irq.h"
- #include "hw/boards.h"
-diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/mps2.c
-+++ b/hw/arm/mps2.c
-@@ -XXX,XX +XXX,XX @@
- #include "qemu/osdep.h"
- #include "qapi/error.h"
- #include "qemu/error-report.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/arm/armv7m.h"
- #include "hw/or-irq.h"
- #include "hw/boards.h"
-diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/msf2-soc.c
-+++ b/hw/arm/msf2-soc.c
-@@ -XXX,XX +XXX,XX @@
- #include "qemu/units.h"
- #include "qapi/error.h"
- #include "qemu-common.h"
--#include "hw/arm/arm.h"
- #include "exec/address-spaces.h"
- #include "hw/char/serial.h"
- #include "hw/boards.h"
-diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/msf2-som.c
-+++ b/hw/arm/msf2-som.c
-@@ -XXX,XX +XXX,XX @@
- #include "qapi/error.h"
- #include "qemu/error-report.h"
- #include "hw/boards.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "exec/address-spaces.h"
- #include "hw/arm/msf2-soc.h"
- #include "cpu.h"
-diff --git a/hw/arm/musca.c b/hw/arm/musca.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/musca.c
-+++ b/hw/arm/musca.c
-@@ -XXX,XX +XXX,XX @@
- #include "qapi/error.h"
- #include "exec/address-spaces.h"
- #include "sysemu/sysemu.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/arm/armsse.h"
- #include "hw/boards.h"
- #include "hw/char/pl011.h"
-diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/musicpal.c
-+++ b/hw/arm/musicpal.c
-@@ -XXX,XX +XXX,XX @@
- #include "qemu-common.h"
- #include "cpu.h"
- #include "hw/sysbus.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "net/net.h"
- #include "sysemu/sysemu.h"
- #include "hw/boards.h"
-diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/netduino2.c
-+++ b/hw/arm/netduino2.c
-@@ -XXX,XX +XXX,XX @@
- #include "hw/boards.h"
- #include "qemu/error-report.h"
- #include "hw/arm/stm32f205_soc.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- static void netduino2_init(MachineState *machine)
- {
-diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/nrf51_soc.c
-+++ b/hw/arm/nrf51_soc.c
-@@ -XXX,XX +XXX,XX @@
- #include "qemu/osdep.h"
- #include "qapi/error.h"
- #include "qemu-common.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/sysbus.h"
- #include "hw/boards.h"
- #include "hw/misc/unimp.h"
-diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/nseries.c
-+++ b/hw/arm/nseries.c
-@@ -XXX,XX +XXX,XX @@
- #include "qemu/bswap.h"
- #include "sysemu/sysemu.h"
- #include "hw/arm/omap.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/irq.h"
- #include "ui/console.h"
- #include "hw/boards.h"
-diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/omap1.c
-+++ b/hw/arm/omap1.c
-@@ -XXX,XX +XXX,XX @@
- #include "cpu.h"
- #include "hw/boards.h"
- #include "hw/hw.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/arm/omap.h"
- #include "sysemu/sysemu.h"
- #include "hw/arm/soc_dma.h"
-diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/omap2.c
-+++ b/hw/arm/omap2.c
-@@ -XXX,XX +XXX,XX @@
- #include "sysemu/qtest.h"
- #include "hw/boards.h"
- #include "hw/hw.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/arm/omap.h"
- #include "sysemu/sysemu.h"
- #include "qemu/timer.h"
-diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/omap_sx1.c
-+++ b/hw/arm/omap_sx1.c
-@@ -XXX,XX +XXX,XX @@
- #include "ui/console.h"
- #include "hw/arm/omap.h"
- #include "hw/boards.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/block/flash.h"
- #include "sysemu/qtest.h"
- #include "exec/address-spaces.h"
-diff --git a/hw/arm/palm.c b/hw/arm/palm.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/palm.c
-+++ b/hw/arm/palm.c
-@@ -XXX,XX +XXX,XX @@
- #include "ui/console.h"
- #include "hw/arm/omap.h"
- #include "hw/boards.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/input/tsc2xxx.h"
- #include "hw/loader.h"
- #include "exec/address-spaces.h"
-diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/raspi.c
-+++ b/hw/arm/raspi.c
-@@ -XXX,XX +XXX,XX @@
- #include "qemu/error-report.h"
- #include "hw/boards.h"
- #include "hw/loader.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "sysemu/sysemu.h"
- #define SMPBOOT_ADDR    0x300 /* this should leave enough space for ATAGS */
-diff --git a/hw/arm/realview.c b/hw/arm/realview.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/realview.c
-+++ b/hw/arm/realview.c
-@@ -XXX,XX +XXX,XX @@
- #include "qemu-common.h"
- #include "cpu.h"
- #include "hw/sysbus.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/arm/primecell.h"
- #include "hw/net/lan9118.h"
- #include "hw/net/smc91c111.h"
-diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/spitz.c
-+++ b/hw/arm/spitz.c
-@@ -XXX,XX +XXX,XX @@
- #include "qapi/error.h"
- #include "hw/hw.h"
- #include "hw/arm/pxa.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "sysemu/sysemu.h"
- #include "hw/pcmcia.h"
- #include "hw/i2c/i2c.h"
-diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/stellaris.c
-+++ b/hw/arm/stellaris.c
-@@ -XXX,XX +XXX,XX @@
- #include "qapi/error.h"
- #include "hw/sysbus.h"
- #include "hw/ssi/ssi.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "qemu/timer.h"
- #include "hw/i2c/i2c.h"
- #include "net/net.h"
-diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/stm32f205_soc.c
-+++ b/hw/arm/stm32f205_soc.c
-@@ -XXX,XX +XXX,XX @@
- #include "qemu/osdep.h"
- #include "qapi/error.h"
- #include "qemu-common.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "exec/address-spaces.h"
- #include "hw/arm/stm32f205_soc.h"
-diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/strongarm.c
-+++ b/hw/arm/strongarm.c
-@@ -XXX,XX +XXX,XX @@
- #include "hw/sysbus.h"
- #include "strongarm.h"
- #include "qemu/error-report.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "chardev/char-fe.h"
- #include "chardev/char-serial.h"
- #include "sysemu/sysemu.h"
-diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/tosa.c
-+++ b/hw/arm/tosa.c
-@@ -XXX,XX +XXX,XX @@
- #include "qapi/error.h"
- #include "hw/hw.h"
- #include "hw/arm/pxa.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/arm/sharpsl.h"
- #include "hw/pcmcia.h"
- #include "hw/boards.h"
-diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/versatilepb.c
-+++ b/hw/arm/versatilepb.c
-@@ -XXX,XX +XXX,XX @@
- #include "qemu-common.h"
- #include "cpu.h"
- #include "hw/sysbus.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/net/smc91c111.h"
- #include "net/net.h"
- #include "sysemu/sysemu.h"
-diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/vexpress.c
-+++ b/hw/arm/vexpress.c
-@@ -XXX,XX +XXX,XX @@
- #include "qemu-common.h"
- #include "cpu.h"
- #include "hw/sysbus.h"
--#include "hw/arm/arm.h"
-+#include "hw/arm/boot.h"
- #include "hw/arm/primecell.h"
- #include "hw/net/lan9118.h"
- #include "hw/i2c/i2c.h"
 diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/virt.c
 +++ b/hw/arm/virt.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
- #include "qemu/option.h"
+             [GTIMER_HYP]  = ARCH_TIMER_NS_EL2_IRQ,
- #include "qapi/error.h"
+             [GTIMER_SEC]  = ARCH_TIMER_S_EL1_IRQ,
- #include "hw/sysbus.h"
+             [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,
--#include "hw/arm/arm.h"
++            [GTIMER_S_EL2_PHYS] = ARCH_TIMER_S_EL2_IRQ,
-+#include "hw/arm/boot.h"
++            [GTIMER_S_EL2_VIRT] = ARCH_TIMER_S_EL2_VIRT_IRQ,
- #include "hw/arm/primecell.h"
+         };
- #include "hw/arm/virt.h"
- #include "hw/block/flash.h"
+         for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
 diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/xilinx_zynq.c
 +++ b/hw/arm/xilinx_zynq.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu-common.h"
  #include "cpu.h"
  #include "hw/sysbus.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "net/net.h"
  #include "exec/address-spaces.h"
  #include "sysemu/sysemu.h"
 diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/xlnx-versal.c
 +++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@
  #include "net/net.h"
  #include "sysemu/sysemu.h"
  #include "sysemu/kvm.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "kvm_arm.h"
  #include "hw/misc/unimp.h"
  #include "hw/intc/arm_gicv3_common.h"
 diff --git a/hw/arm/z2.c b/hw/arm/z2.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/z2.c
 +++ b/hw/arm/z2.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/osdep.h"
  #include "hw/hw.h"
  #include "hw/arm/pxa.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/i2c/i2c.h"
  #include "hw/ssi/ssi.h"
  #include "hw/boards.h"
 --
-.20.1
+.43.0

-[Qemu-devel] [PULL 01/12] target/arm: Use extract2 for EXTR
+[PULL 12/21] hw/arm: enable secure EL2 timers for sbsa machine
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Alex Bennée <alex.bennee@linaro.org>
-This is, after all, how we implement extract2 in tcg/aarch64.
+Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Message-id: 20190514011129.11330-2-richard.henderson@linaro.org
+Message-id: 20250204125009.2281315-10-peter.maydell@linaro.org
 Cc: qemu-stable@nongnu.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/translate-a64.c | 38 ++++++++++++++++++++------------------
+ hw/arm/sbsa-ref.c | 2 ++
-file changed, 20 insertions(+), 18 deletions(-)
+file changed, 2 insertions(+)
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
+diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
+--- a/hw/arm/sbsa-ref.c
-+++ b/target/arm/translate-a64.c
++++ b/hw/arm/sbsa-ref.c
-@@ -XXX,XX +XXX,XX @@ static void disas_extract(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ static void create_gic(SBSAMachineState *sms, MemoryRegion *mem)
-             } else {
+             [GTIMER_HYP]  = ARCH_TIMER_NS_EL2_IRQ,
-                 tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));
+             [GTIMER_SEC]  = ARCH_TIMER_S_EL1_IRQ,
-             }
+             [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,
--        } else if (rm == rn) { /* ROR */
++            [GTIMER_S_EL2_PHYS] = ARCH_TIMER_S_EL2_IRQ,
--            tcg_rm = cpu_reg(s, rm);
++            [GTIMER_S_EL2_VIRT] = ARCH_TIMER_S_EL2_VIRT_IRQ,
--            if (sf) {
+         };
--                tcg_gen_rotri_i64(tcg_rd, tcg_rm, imm);
--            } else {
+         for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
 -                TCGv_i32 tmp = tcg_temp_new_i32();
 -                tcg_gen_extrl_i64_i32(tmp, tcg_rm);
 -                tcg_gen_rotri_i32(tmp, tmp, imm);
 -                tcg_gen_extu_i32_i64(tcg_rd, tmp);
 -                tcg_temp_free_i32(tmp);
 -            }
          } else {
 -            tcg_rm = read_cpu_reg(s, rm, sf);
 -            tcg_rn = read_cpu_reg(s, rn, sf);
 -            tcg_gen_shri_i64(tcg_rm, tcg_rm, imm);
 -            tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm);
 -            tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn);
 -            if (!sf) {
 -                tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
 +            tcg_rm = cpu_reg(s, rm);
 +            tcg_rn = cpu_reg(s, rn);
 +
 +            if (sf) {
 +                /* Specialization to ROR happens in EXTRACT2.  */
 +                tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, imm);
 +            } else {
 +                TCGv_i32 t0 = tcg_temp_new_i32();
 +
 +                tcg_gen_extrl_i64_i32(t0, tcg_rm);
 +                if (rm == rn) {
 +                    tcg_gen_rotri_i32(t0, t0, imm);
 +                } else {
 +                    TCGv_i32 t1 = tcg_temp_new_i32();
 +                    tcg_gen_extrl_i64_i32(t1, tcg_rn);
 +                    tcg_gen_extract2_i32(t0, t0, t1, imm);
 +                    tcg_temp_free_i32(t1);
 +                }
 +                tcg_gen_extu_i32_i64(tcg_rd, t0);
 +                tcg_temp_free_i32(t0);
              }
          }
      }
 --
-.20.1
+.43.0

-New patch
+[PULL 13/21] target/arm: Correct LDRD atomicity and fault behaviour
+Our LDRD implementation is wrong in two respects:
+ * if the address is 4-aligned and the load crosses a page boundary
+   and the second load faults and the first load was to the
+   base register (as in cases like "ldrd r2, r3, [r2]", then we
+   must not update the base register before taking the fault
+ * if the address is 8-aligned the access must be a 64-bit
+   single-copy atomic access, not two 32-bit accesses
+Rewrite the handling of the loads in LDRD to use a single
+tcg_gen_qemu_ld_i64() and split the result into the destination
+registers. This allows us to get the atomicity requirements
+right, and also implicitly means that we won't update the
+base register too early for the page-crossing case.
+Note that because we no longer increment 'addr' by 4 in the course of
+performing the LDRD we must change the adjustment value we pass to
+op_addr_ri_post() and op_addr_rr_post(): it no longer needs to
+subtract 4 to get the correct value to use if doing base register
+writeback.
+STRD has the same problem with not getting the atomicity right;
+we will deal with that in the following commit.
+Cc: qemu-stable@nongnu.org
+Reported-by: Stu Grossman <stu.grossman@gmail.com>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20250227142746.1698904-2-peter.maydell@linaro.org
+---
+ target/arm/tcg/translate.c | 70 +++++++++++++++++++++++++-------------
+file changed, 46 insertions(+), 24 deletions(-)
+diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/translate.c
++++ b/target/arm/tcg/translate.c
+@@ -XXX,XX +XXX,XX @@ static bool op_store_rr(DisasContext *s, arg_ldst_rr *a,
+     return true;
+ }
++static void do_ldrd_load(DisasContext *s, TCGv_i32 addr, int rt, int rt2)
++{
++    /*
++     * LDRD is required to be an atomic 64-bit access if the
++     * address is 8-aligned, two atomic 32-bit accesses if
++     * it's only 4-aligned, and to give an alignment fault
++     * if it's not 4-aligned. This is MO_ALIGN_4 | MO_ATOM_SUBALIGN.
++     * Rt is always the word from the lower address, and Rt2 the
++     * data from the higher address, regardless of endianness.
++     * So (like gen_load_exclusive) we avoid gen_aa32_ld_i64()
++     * so we don't get its SCTLR_B check, and instead do a 64-bit access
++     * using MO_BE if appropriate and then split the two halves.
++     *
++     * For M-profile, and for A-profile before LPAE, the 64-bit
++     * atomicity is not required. We could model that using
++     * the looser MO_ATOM_IFALIGN_PAIR, but providing a higher
++     * level of atomicity than required is harmless (we would not
++     * currently generate better code for IFALIGN_PAIR here).
++     *
++     * This also gives us the correct behaviour of not updating
++     * rt if the load of rt2 faults; this is required for cases
++     * like "ldrd r2, r3, [r2]" where rt is also the base register.
++     */
++    int mem_idx = get_mem_index(s);
++    MemOp opc = MO_64 | MO_ALIGN_4 | MO_ATOM_SUBALIGN | s->be_data;
++    TCGv taddr = gen_aa32_addr(s, addr, opc);
++    TCGv_i64 t64 = tcg_temp_new_i64();
++    TCGv_i32 tmp = tcg_temp_new_i32();
++    TCGv_i32 tmp2 = tcg_temp_new_i32();
++
++    tcg_gen_qemu_ld_i64(t64, taddr, mem_idx, opc);
++    if (s->be_data == MO_BE) {
++        tcg_gen_extr_i64_i32(tmp2, tmp, t64);
++    } else {
++        tcg_gen_extr_i64_i32(tmp, tmp2, t64);
++    }
++    store_reg(s, rt, tmp);
++    store_reg(s, rt2, tmp2);
++}
++
+ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a)
+ {
+-    int mem_idx = get_mem_index(s);
+-    TCGv_i32 addr, tmp;
++    TCGv_i32 addr;
+     if (!ENABLE_ARCH_5TE) {
+         return false;
+@@ -XXX,XX +XXX,XX @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a)
+     }
+     addr = op_addr_rr_pre(s, a);
+-    tmp = tcg_temp_new_i32();
+-    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
+-    store_reg(s, a->rt, tmp);
+-
+-    tcg_gen_addi_i32(addr, addr, 4);
+-
+-    tmp = tcg_temp_new_i32();
+-    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
+-    store_reg(s, a->rt + 1, tmp);
++    do_ldrd_load(s, addr, a->rt, a->rt + 1);
+     /* LDRD w/ base writeback is undefined if the registers overlap.  */
+-    op_addr_rr_post(s, a, addr, -4);
++    op_addr_rr_post(s, a, addr, 0);
+     return true;
+ }
+@@ -XXX,XX +XXX,XX @@ static bool op_store_ri(DisasContext *s, arg_ldst_ri *a,
+ static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
+ {
+-    int mem_idx = get_mem_index(s);
+-    TCGv_i32 addr, tmp;
++    TCGv_i32 addr;
+     addr = op_addr_ri_pre(s, a);
+-    tmp = tcg_temp_new_i32();
+-    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
+-    store_reg(s, a->rt, tmp);
+-
+-    tcg_gen_addi_i32(addr, addr, 4);
+-
+-    tmp = tcg_temp_new_i32();
+-    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
+-    store_reg(s, rt2, tmp);
++    do_ldrd_load(s, addr, a->rt, rt2);
+     /* LDRD w/ base writeback is undefined if the registers overlap.  */
+-    op_addr_ri_post(s, a, addr, -4);
++    op_addr_ri_post(s, a, addr, 0);
+     return true;
+ }
+--
+.43.0

-New patch
+[PULL 14/21] target/arm: Correct STRD atomicity
+Our STRD implementation doesn't correctly implement the requirement:
+ * if the address is 8-aligned the access must be a 64-bit
+   single-copy atomic access, not two 32-bit accesses
+Rewrite the handling of STRD to use a single tcg_gen_qemu_st_i64()
+of a value produced by concatenating the two 32 bit source registers.
+This allows us to get the atomicity right.
+As with the LDRD change, now that we don't update 'addr' in the
+course of performing the store we need to adjust the offset
+we pass to op_addr_ri_post() and op_addr_rr_post().
+Cc: qemu-stable@nongnu.org
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20250227142746.1698904-3-peter.maydell@linaro.org
+---
+ target/arm/tcg/translate.c | 59 +++++++++++++++++++++++++-------------
+file changed, 39 insertions(+), 20 deletions(-)
+diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/tcg/translate.c
++++ b/target/arm/tcg/translate.c
+@@ -XXX,XX +XXX,XX @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a)
+     return true;
+ }
++static void do_strd_store(DisasContext *s, TCGv_i32 addr, int rt, int rt2)
++{
++    /*
++     * STRD is required to be an atomic 64-bit access if the
++     * address is 8-aligned, two atomic 32-bit accesses if
++     * it's only 4-aligned, and to give an alignment fault
++     * if it's not 4-aligned.
++     * Rt is always the word from the lower address, and Rt2 the
++     * data from the higher address, regardless of endianness.
++     * So (like gen_store_exclusive) we avoid gen_aa32_ld_i64()
++     * so we don't get its SCTLR_B check, and instead do a 64-bit access
++     * using MO_BE if appropriate, using a value constructed
++     * by putting the two halves together in the right order.
++     *
++     * As with LDRD, the 64-bit atomicity is not required for
++     * M-profile, or for A-profile before LPAE, and we provide
++     * the higher guarantee always for simplicity.
++     */
++    int mem_idx = get_mem_index(s);
++    MemOp opc = MO_64 | MO_ALIGN_4 | MO_ATOM_SUBALIGN | s->be_data;
++    TCGv taddr = gen_aa32_addr(s, addr, opc);
++    TCGv_i32 t1 = load_reg(s, rt);
++    TCGv_i32 t2 = load_reg(s, rt2);
++    TCGv_i64 t64 = tcg_temp_new_i64();
++
++    if (s->be_data == MO_BE) {
++        tcg_gen_concat_i32_i64(t64, t2, t1);
++    } else {
++        tcg_gen_concat_i32_i64(t64, t1, t2);
++    }
++    tcg_gen_qemu_st_i64(t64, taddr, mem_idx, opc);
++}
++
+ static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a)
+ {
+-    int mem_idx = get_mem_index(s);
+-    TCGv_i32 addr, tmp;
++    TCGv_i32 addr;
+     if (!ENABLE_ARCH_5TE) {
+         return false;
+@@ -XXX,XX +XXX,XX @@ static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a)
+     }
+     addr = op_addr_rr_pre(s, a);
+-    tmp = load_reg(s, a->rt);
+-    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
++    do_strd_store(s, addr, a->rt, a->rt + 1);
+-    tcg_gen_addi_i32(addr, addr, 4);
+-
+-    tmp = load_reg(s, a->rt + 1);
+-    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
+-
+-    op_addr_rr_post(s, a, addr, -4);
++    op_addr_rr_post(s, a, addr, 0);
+     return true;
+ }
+@@ -XXX,XX +XXX,XX @@ static bool trans_LDRD_ri_t32(DisasContext *s, arg_ldst_ri2 *a)
+ static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
+ {
+-    int mem_idx = get_mem_index(s);
+-    TCGv_i32 addr, tmp;
++    TCGv_i32 addr;
+     addr = op_addr_ri_pre(s, a);
+-    tmp = load_reg(s, a->rt);
+-    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
++    do_strd_store(s, addr, a->rt, rt2);
+-    tcg_gen_addi_i32(addr, addr, 4);
+-
+-    tmp = load_reg(s, rt2);
+-    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
+-
+-    op_addr_ri_post(s, a, addr, -4);
++    op_addr_ri_post(s, a, addr, 0);
+     return true;
+ }
+--
+.43.0

-[Qemu-devel] [PULL 04/12] arm: Move system_clock_scale to armv7m_systick.h
+[PULL 15/21] target/arm: Drop unused address_offset from op_addr_{rr, ri}_post()
-The system_clock_scale global is used only by the armv7m systick
+All the callers of op_addr_rr_post() and op_addr_ri_post() now pass in
-device; move the extern declaration to the armv7m_systick.h header,
+zero for the address_offset, so we can remove that argument.
 and expand the comment to explain what it is and that it should
 ideally be replaced with a different approach.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Message-id: 20190516163857.6430-2-peter.maydell@linaro.org
+Message-id: 20250227142746.1698904-4-peter.maydell@linaro.org
 ---
- include/hw/arm/arm.h              |  4 ----
+ target/arm/tcg/translate.c | 26 +++++++++++++-------------
- include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++++++++
+file changed, 13 insertions(+), 13 deletions(-)
 files changed, 22 insertions(+), 4 deletions(-)
-diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h
+diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/arm.h
+--- a/target/arm/tcg/translate.c
-+++ b/include/hw/arm/arm.h
++++ b/target/arm/tcg/translate.c
-@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
+@@ -XXX,XX +XXX,XX @@ static TCGv_i32 op_addr_rr_pre(DisasContext *s, arg_ldst_rr *a)
-                                             const struct arm_boot_info *info,
+ }
-                                             hwaddr mvbar_addr);
+ static void op_addr_rr_post(DisasContext *s, arg_ldst_rr *a,
--/* Multiplication factor to convert from system clock ticks to qemu timer
+-                            TCGv_i32 addr, int address_offset)
--   ticks.  */
++                            TCGv_i32 addr)
--extern int system_clock_scale;
+ {
--
+     if (!a->p) {
- #endif /* HW_ARM_H */
+         TCGv_i32 ofs = load_reg(s, a->rm);
-diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
+@@ -XXX,XX +XXX,XX @@ static void op_addr_rr_post(DisasContext *s, arg_ldst_rr *a,
-index XXXXXXX..XXXXXXX 100644
+     } else if (!a->w) {
---- a/include/hw/timer/armv7m_systick.h
+         return;
-+++ b/include/hw/timer/armv7m_systick.h
+     }
-@@ -XXX,XX +XXX,XX @@ typedef struct SysTickState {
+-    tcg_gen_addi_i32(addr, addr, address_offset);
-     qemu_irq irq;
+     store_reg(s, a->rn, addr);
- } SysTickState;
+ }
-+/*
+@@ -XXX,XX +XXX,XX @@ static bool op_load_rr(DisasContext *s, arg_ldst_rr *a,
-+ * Multiplication factor to convert from system clock ticks to qemu timer
+      * Perform base writeback before the loaded value to
-+ * ticks. This should be set (by board code, usually) to a value
+      * ensure correct behavior with overlapping index registers.
-+ * equal to NANOSECONDS_PER_SECOND / frq, where frq is the clock frequency
+      */
-+ * in Hz of the CPU.
+-    op_addr_rr_post(s, a, addr, 0);
-+ *
++    op_addr_rr_post(s, a, addr);
-+ * This value is used by the systick device when it is running in
+     store_reg_from_load(s, a->rt, tmp);
-+ * its "use the CPU clock" mode (ie when SYST_CSR.CLKSOURCE == 1) to
+     return true;
-+ * set how fast the timer should tick.
+ }
-+ *
+@@ -XXX,XX +XXX,XX @@ static bool op_store_rr(DisasContext *s, arg_ldst_rr *a,
-+ * TODO: we should refactor this so that rather than using a global
+     gen_aa32_st_i32(s, tmp, addr, mem_idx, mop);
-+ * we use a device property or something similar. This is complicated
+     disas_set_da_iss(s, mop, issinfo);
-+ * because (a) the property would need to be plumbed through from the
-+ * board code down through various layers to the systick device
+-    op_addr_rr_post(s, a, addr, 0);
-+ * and (b) the property needs to be modifiable after realize, because
++    op_addr_rr_post(s, a, addr);
-+ * the stellaris board uses this to implement the behaviour where the
+     return true;
-+ * guest can reprogram the PLL registers to downclock the CPU, and the
+ }
-+ * systick device needs to react accordingly. Possibly this should
-+ * be deferred until we have a good API for modelling clock trees.
+@@ -XXX,XX +XXX,XX @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a)
-+ */
+     do_ldrd_load(s, addr, a->rt, a->rt + 1);
-+extern int system_clock_scale;
-+
+     /* LDRD w/ base writeback is undefined if the registers overlap.  */
- #endif
+-    op_addr_rr_post(s, a, addr, 0);
 +    op_addr_rr_post(s, a, addr);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a)
      do_strd_store(s, addr, a->rt, a->rt + 1);
 -    op_addr_rr_post(s, a, addr, 0);
 +    op_addr_rr_post(s, a, addr);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static TCGv_i32 op_addr_ri_pre(DisasContext *s, arg_ldst_ri *a)
  }
  static void op_addr_ri_post(DisasContext *s, arg_ldst_ri *a,
 -                            TCGv_i32 addr, int address_offset)
 +                            TCGv_i32 addr)
  {
 +    int address_offset = 0;
      if (!a->p) {
          if (a->u) {
 -            address_offset += a->imm;
 +            address_offset = a->imm;
          } else {
 -            address_offset -= a->imm;
 +            address_offset = -a->imm;
          }
      } else if (!a->w) {
          return;
@@ -XXX,XX +XXX,XX @@ static bool op_load_ri(DisasContext *s, arg_ldst_ri *a,
       * Perform base writeback before the loaded value to
       * ensure correct behavior with overlapping index registers.
       */
 -    op_addr_ri_post(s, a, addr, 0);
 +    op_addr_ri_post(s, a, addr);
      store_reg_from_load(s, a->rt, tmp);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool op_store_ri(DisasContext *s, arg_ldst_ri *a,
      gen_aa32_st_i32(s, tmp, addr, mem_idx, mop);
      disas_set_da_iss(s, mop, issinfo);
 -    op_addr_ri_post(s, a, addr, 0);
 +    op_addr_ri_post(s, a, addr);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
      do_ldrd_load(s, addr, a->rt, rt2);
      /* LDRD w/ base writeback is undefined if the registers overlap.  */
 -    op_addr_ri_post(s, a, addr, 0);
 +    op_addr_ri_post(s, a, addr);
      return true;
  }
@@ -XXX,XX +XXX,XX @@ static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
      do_strd_store(s, addr, a->rt, rt2);
 -    op_addr_ri_post(s, a, addr, 0);
 +    op_addr_ri_post(s, a, addr);
      return true;
  }
 --
-.20.1
+.43.0

-New patch
+[PULL 16/21] target/arm: Make dummy debug registers RAZ, not NOP
+In debug_helper.c we provide a few dummy versions of
+debug registers:
+ * DBGVCR (AArch32 only): enable bits for vector-catch
+   debug events
+ * MDCCINT_EL1: interrupt enable bits for the DCC
+   debug communications channel
+ * DBGVCR32_EL2: the AArch64 accessor for the state in
+   DBGVCR
+We implemented these only to stop Linux crashing on startup,
+but we chose to implement them as ARM_CP_NOP. This worked
+for Linux where it only cares about trying to write to these
+registers, but is very confusing behaviour for anything that
+wants to read the registers (perhaps for context state switches),
+because the destination register will be left with whatever
+random value it happened to have before the read.
+Model these registers instead as RAZ.
+Fixes: 5e8b12ffbb8c68 ("target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0")
+Fixes: 5dbdc4342f479d ("target-arm: Implement dummy MDCCINT_EL1")
+Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2708
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20250228162424.1917269-1-peter.maydell@linaro.org
+---
+ target/arm/debug_helper.c | 7 ++++---
+file changed, 4 insertions(+), 3 deletions(-)
+diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/arm/debug_helper.c
++++ b/target/arm/debug_helper.c
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
+     { .name = "DBGVCR",
+       .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
+       .access = PL1_RW, .accessfn = access_tda,
+-      .type = ARM_CP_NOP },
++      .type = ARM_CP_CONST, .resetvalue = 0 },
+     /*
+      * Dummy MDCCINT_EL1, since we don't implement the Debug Communications
+      * Channel but Linux may try to access this register. The 32-bit
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
+     { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
+       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
+       .access = PL1_RW, .accessfn = access_tdcc,
+-      .type = ARM_CP_NOP },
++      .type = ARM_CP_CONST, .resetvalue = 0 },
+     /*
+      * Dummy DBGCLAIM registers.
+      * "The architecture does not define any functionality for the CLAIM tag bits.",
+@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_aa32_el1_reginfo[] = {
+     { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
+       .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
+       .access = PL2_RW, .accessfn = access_dbgvcr32,
+-      .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP },
++      .type = ARM_CP_CONST | ARM_CP_EL3_NO_EL2_KEEP,
++      .resetvalue = 0 },
+ };
+ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
+--
+.43.0

-[Qemu-devel] [PULL 03/12] target/arm: Fix vector operation segfault
+[PULL 17/21] util/qemu-timer.c: Don't warp timer from timerlist_rearm()
-From: Alistair Francis <alistair.francis@wdc.com>
+Currently we call icount_start_warp_timer() from timerlist_rearm().
 This produces incorrect behaviour, because timerlist_rearm() is
 called, for instance, when a timer callback modifies its timer.  We
 cannot decide here to warp the timer forwards to the next timer
 deadline merely because all_cpu_threads_idle() is true, because the
 timer callback we were called from (or some other callback later in
 the list of callbacks being invoked) may be about to raise a CPU
 interrupt and move a CPU from idle to ready.
-Commit 89e68b575 "target/arm: Use vector operations for saturation"
+The only valid place to choose to warp the timer forward is from the
-causes this abort() when booting QEMU ARM with a Cortex-A15:
+main loop, when we know we have no outstanding IO or timer callbacks
 that might be about to wake up a CPU.
-0x00007ffff4c2382f in raise () at /usr/lib/libc.so.6
+For Arm guests, this bug was mostly latent until the refactoring
-0x00007ffff4c0e672 in abort () at /usr/lib/libc.so.6
+commit f6fc36deef6abc ("target/arm/helper: Implement
-0x00005555559c1839 in disas_neon_data_insn (insn=<optimized out>, s=<optimized out>) at ./target/arm/translate.c:6673
+CNTHCTL_EL2.CNT[VP]MASK"), which exposed it because it refactored a
-0x00005555559c1839 in disas_neon_data_insn (s=<optimized out>, insn=<optimized out>) at ./target/arm/translate.c:6386
+timer callback so that it happened to call timer_mod() first and
-0x00005555559cd8a4 in disas_arm_insn (insn=4081107068, s=0x7fffe59a9510) at ./target/arm/translate.c:9289
+raise the interrupt second, when it had previously raised the
-0x00005555559cd8a4 in arm_tr_translate_insn (dcbase=0x7fffe59a9510, cpu=<optimized out>) at ./target/arm/translate.c:13612
+interrupt first and called timer_mod() afterwards.
 0x00005555558d1d39 in translator_loop (ops=0x5555561cc580 <arm_translator_ops>, db=0x7fffe59a9510, cpu=0x55555686a2f0, tb=<optimized out>, max_insns=<optimized out>) at ./accel/tcg/translator.c:96
 0x00005555559d10d4 in gen_intermediate_code (cpu=cpu@entry=0x55555686a2f0, tb=tb@entry=0x7fffd7840080 <code_gen_buffer+126091347>, max_insns=max_insns@entry=512) at ./target/arm/translate.c:13901
 0x00005555558d06b9 in tb_gen_code (cpu=cpu@entry=0x55555686a2f0, pc=3067096216, cs_base=0, flags=192, cflags=-16252928, cflags@entry=524288) at ./accel/tcg/translate-all.c:1736
 0x00005555558ce467 in tb_find (cf_mask=524288, tb_exit=1, last_tb=0x7fffd783e640 <code_gen_buffer+126084627>, cpu=0x1) at ./accel/tcg/cpu-exec.c:407
 0x00005555558ce467 in cpu_exec (cpu=cpu@entry=0x55555686a2f0) at ./accel/tcg/cpu-exec.c:728
 0x000055555588b0cf in tcg_cpu_exec (cpu=0x55555686a2f0) at ./cpus.c:1431
 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=0x55555686a2f0) at ./cpus.c:1735
 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=arg@entry=0x55555686a2f0) at ./cpus.c:1709
 0x0000555555d2629a in qemu_thread_start (args=<optimized out>) at ./util/qemu-thread-posix.c:502
 0x00007ffff4db8a92 in start_thread () at /usr/lib/libpthread.
-This patch ensures that we don't hit the abort() in the second switch
+This call seems to have originally derived from the
-case in disas_neon_data_insn() as we will return from the first case.
+pre-record-and-replay icount code, which (as of e.g.  commit
 db1a49726c3c in 2010) in this location did a call to
 qemu_notify_event(), necessary to get the icount code in the vCPU
 round-robin thread to stop and recalculate the icount deadline when a
 timer was reprogrammed from the IO thread.  In current QEMU,
 everything is done on the vCPU thread when we are in icount mode, so
 there's no need to try to notify another thread here.
-Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+I suspect that the other reason why this call was doing icount timer
 warping is that it pre-dates commit efab87cf79077a from 2015, which
 added a call to icount_start_warp_timer() to main_loop_wait().  Once
 the call in timerlist_rearm() has been removed, if the timer
 callbacks don't cause any CPU to be woken up then we will end up
 calling icount_start_warp_timer() from main_loop_wait() when the rr
 main loop code calls rr_wait_io_event().
 Remove the incorrect call from timerlist_rearm().
 Cc: qemu-stable@nongnu.org
 Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2703
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
 Tested-by: Alex Bennée <alex.bennee@linaro.org>
-Message-id: ad91b397f360b2fc7f4087e476f7df5b04d42ddb.1558021877.git.alistair.francis@wdc.com
+Message-id: 20250210135804.3526943-1-peter.maydell@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/translate.c | 4 ++--
+ util/qemu-timer.c | 4 ----
-file changed, 2 insertions(+), 2 deletions(-)
+file changed, 4 deletions(-)
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+diff --git a/util/qemu-timer.c b/util/qemu-timer.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/util/qemu-timer.c
-+++ b/target/arm/translate.c
++++ b/util/qemu-timer.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ static bool timer_mod_ns_locked(QEMUTimerList *timer_list,
-             tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
-                            rn_ofs, rm_ofs, vec_size, vec_size,
+ static void timerlist_rearm(QEMUTimerList *timer_list)
-                            (u ? uqadd_op : sqadd_op) + size);
+ {
--            break;
+-    /* Interrupt execution to force deadline recalculation.  */
-+            return 0;
+-    if (icount_enabled() && timer_list->clock->type == QEMU_CLOCK_VIRTUAL) {
+-        icount_start_warp_timer();
-         case NEON_3R_VQSUB:
+-    }
-             tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
+     timerlist_notify(timer_list);
-                            rn_ofs, rm_ofs, vec_size, vec_size,
+ }
-                            (u ? uqsub_op : sqsub_op) + size);
 -            break;
 +            return 0;
          case NEON_3R_VMUL: /* VMUL */
              if (u) {
 --
-.20.1
+.43.0

-New patch
+[PULL 18/21] include/exec/memop.h: Expand comment for MO_ATOM_SUBALIGN
+Expand the example in the comment documenting MO_ATOM_SUBALIGN,
+to be clearer about the atomicity guarantees it represents.
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Message-id: 20250228103222.1838913-1-peter.maydell@linaro.org
+---
+ include/exec/memop.h | 8 ++++++--
+file changed, 6 insertions(+), 2 deletions(-)
+diff --git a/include/exec/memop.h b/include/exec/memop.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/exec/memop.h
++++ b/include/exec/memop.h
+@@ -XXX,XX +XXX,XX @@ typedef enum MemOp {
+      *    Depending on alignment, one or both will be single-copy atomic.
+      *    This is the atomicity e.g. of Arm FEAT_LSE2 LDP.
+      * MO_ATOM_SUBALIGN: the operation is single-copy atomic by parts
+-     *    by the alignment.  E.g. if the address is 0 mod 4, then each
+-     *    4-byte subobject is single-copy atomic.
++     *    by the alignment.  E.g. if an 8-byte value is accessed at an
++     *    address which is 0 mod 8, then the whole 8-byte access is
++     *    single-copy atomic; otherwise, if it is accessed at 0 mod 4
++     *    then each 4-byte subobject is single-copy atomic; otherwise
++     *    if it is accessed at 0 mod 2 then the four 2-byte subobjects
++     *    are single-copy atomic.
+      *    This is the atomicity e.g. of IBM Power.
+      * MO_ATOM_NONE: the operation has no atomicity requirements.
+      *
+--
+.43.0

-New patch
+[PULL 19/21] hw/arm/smmu: Introduce smmu_configs_inv_sid_range() helper
+From: JianChunfu <jansef.jian@hj-micro.com>
+Use a similar terminology smmu_hash_remove_by_sid_range() as the one
+being used for other hash table matching functions since
+smmuv3_invalidate_ste() name is not self explanatory, and introduce a
+helper that invokes the g_hash_table_foreach_remove.
+No functional change intended.
+Signed-off-by: JianChunfu <jansef.jian@hj-micro.com>
+Reviewed-by: Eric Auger <eric.auger@redhat.com>
+Message-id: 20250228031438.3916-1-jansef.jian@hj-micro.com
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ hw/arm/smmu-internal.h       |  5 -----
+ include/hw/arm/smmu-common.h |  6 ++++++
+ hw/arm/smmu-common.c         | 21 +++++++++++++++++++++
+ hw/arm/smmuv3.c              | 19 ++-----------------
+ hw/arm/trace-events          |  3 ++-
+files changed, 31 insertions(+), 23 deletions(-)
+diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/smmu-internal.h
++++ b/hw/arm/smmu-internal.h
+@@ -XXX,XX +XXX,XX @@ typedef struct SMMUIOTLBPageInvInfo {
+     uint64_t mask;
+ } SMMUIOTLBPageInvInfo;
+-typedef struct SMMUSIDRange {
+-    uint32_t start;
+-    uint32_t end;
+-} SMMUSIDRange;
+-
+ #endif
+diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
+index XXXXXXX..XXXXXXX 100644
+--- a/include/hw/arm/smmu-common.h
++++ b/include/hw/arm/smmu-common.h
+@@ -XXX,XX +XXX,XX @@ typedef struct SMMUIOTLBKey {
+     uint8_t level;
+ } SMMUIOTLBKey;
++typedef struct SMMUSIDRange {
++    uint32_t start;
++    uint32_t end;
++} SMMUSIDRange;
++
+ struct SMMUState {
+     /* <private> */
+     SysBusDevice  dev;
+@@ -XXX,XX +XXX,XX @@ void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova,
+                          uint8_t tg, uint64_t num_pages, uint8_t ttl);
+ void smmu_iotlb_inv_ipa(SMMUState *s, int vmid, dma_addr_t ipa, uint8_t tg,
+                         uint64_t num_pages, uint8_t ttl);
++void smmu_configs_inv_sid_range(SMMUState *s, SMMUSIDRange sid_range);
+ /* Unmap the range of all the notifiers registered to any IOMMU mr */
+ void smmu_inv_notifiers_all(SMMUState *s);
+diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/smmu-common.c
++++ b/hw/arm/smmu-common.c
+@@ -XXX,XX +XXX,XX @@ static gboolean smmu_hash_remove_by_vmid_ipa(gpointer key, gpointer value,
+            ((entry->iova & ~info->mask) == info->iova);
+ }
++static gboolean
++smmu_hash_remove_by_sid_range(gpointer key, gpointer value, gpointer user_data)
++{
++    SMMUDevice *sdev = (SMMUDevice *)key;
++    uint32_t sid = smmu_get_sid(sdev);
++    SMMUSIDRange *sid_range = (SMMUSIDRange *)user_data;
++
++    if (sid < sid_range->start || sid > sid_range->end) {
++        return false;
++    }
++    trace_smmu_config_cache_inv(sid);
++    return true;
++}
++
++void smmu_configs_inv_sid_range(SMMUState *s, SMMUSIDRange sid_range)
++{
++    trace_smmu_configs_inv_sid_range(sid_range.start, sid_range.end);
++    g_hash_table_foreach_remove(s->configs, smmu_hash_remove_by_sid_range,
++                                &sid_range);
++}
++
+ void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova,
+                          uint8_t tg, uint64_t num_pages, uint8_t ttl)
+ {
+diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/smmuv3.c
++++ b/hw/arm/smmuv3.c
+@@ -XXX,XX +XXX,XX @@ static void smmuv3_flush_config(SMMUDevice *sdev)
+     SMMUv3State *s = sdev->smmu;
+     SMMUState *bc = &s->smmu_state;
+-    trace_smmuv3_config_cache_inv(smmu_get_sid(sdev));
++    trace_smmu_config_cache_inv(smmu_get_sid(sdev));
+     g_hash_table_remove(bc->configs, sdev);
+ }
+@@ -XXX,XX +XXX,XX @@ static void smmuv3_range_inval(SMMUState *s, Cmd *cmd, SMMUStage stage)
+     }
+ }
+-static gboolean
+-smmuv3_invalidate_ste(gpointer key, gpointer value, gpointer user_data)
+-{
+-    SMMUDevice *sdev = (SMMUDevice *)key;
+-    uint32_t sid = smmu_get_sid(sdev);
+-    SMMUSIDRange *sid_range = (SMMUSIDRange *)user_data;
+-
+-    if (sid < sid_range->start || sid > sid_range->end) {
+-        return false;
+-    }
+-    trace_smmuv3_config_cache_inv(sid);
+-    return true;
+-}
+-
+ static int smmuv3_cmdq_consume(SMMUv3State *s)
+ {
+     SMMUState *bs = ARM_SMMU(s);
+@@ -XXX,XX +XXX,XX @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
+             sid_range.end = sid_range.start + mask;
+             trace_smmuv3_cmdq_cfgi_ste_range(sid_range.start, sid_range.end);
+-            g_hash_table_foreach_remove(bs->configs, smmuv3_invalidate_ste,
+-                                        &sid_range);
++            smmu_configs_inv_sid_range(bs, sid_range);
+             break;
+         }
+         case SMMU_CMD_CFGI_CD:
+diff --git a/hw/arm/trace-events b/hw/arm/trace-events
+index XXXXXXX..XXXXXXX 100644
+--- a/hw/arm/trace-events
++++ b/hw/arm/trace-events
+@@ -XXX,XX +XXX,XX @@ smmu_iotlb_inv_asid_vmid(int asid, int vmid) "IOTLB invalidate asid=%d vmid=%d"
+ smmu_iotlb_inv_vmid(int vmid) "IOTLB invalidate vmid=%d"
+ smmu_iotlb_inv_vmid_s1(int vmid) "IOTLB invalidate vmid=%d"
+ smmu_iotlb_inv_iova(int asid, uint64_t addr) "IOTLB invalidate asid=%d addr=0x%"PRIx64
++smmu_configs_inv_sid_range(uint32_t start, uint32_t end) "Config cache INV SID range from 0x%x to 0x%x"
++smmu_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x"
+ smmu_inv_notifiers_mr(const char *name) "iommu mr=%s"
+ smmu_iotlb_lookup_hit(int asid, int vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d vmid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
+ smmu_iotlb_lookup_miss(int asid, int vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=%d vmid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
+@@ -XXX,XX +XXX,XX @@ smmuv3_cmdq_tlbi_nh(int vmid) "vmid=%d"
+ smmuv3_cmdq_tlbi_nsnh(void) ""
+ smmuv3_cmdq_tlbi_nh_asid(int asid) "asid=%d"
+ smmuv3_cmdq_tlbi_s12_vmid(int vmid) "vmid=%d"
+-smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x"
+ smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s"
+ smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s"
+ smmuv3_inv_notifiers_iova(const char *name, int asid, int vmid, uint64_t iova, uint8_t tg, uint64_t num_pages, int stage) "iommu mr=%s asid=%d vmid=%d iova=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" stage=%d"
+--
+.43.0

-New patch
+[PULL 20/21] target/rx: Set exception vector base to 0xffffff80
+From: Keith Packard <keithp@keithp.com>
+The documentation says the vector is at 0xffffff80, instead of the
+previous value of 0xffffffc0. That value must have been a bug because
+the standard vector values (20, 21, 23, 25, 30) were all
+past the end of the array.
+Signed-off-by: Keith Packard <keithp@keithp.com>
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/rx/helper.c | 2 +-
+file changed, 1 insertion(+), 1 deletion(-)
+diff --git a/target/rx/helper.c b/target/rx/helper.c
+index XXXXXXX..XXXXXXX 100644
+--- a/target/rx/helper.c
++++ b/target/rx/helper.c
+@@ -XXX,XX +XXX,XX @@ void rx_cpu_do_interrupt(CPUState *cs)
+         cpu_stl_data(env, env->isp, env->pc);
+         if (vec < 0x100) {
+-            env->pc = cpu_ldl_data(env, 0xffffffc0 + vec * 4);
++            env->pc = cpu_ldl_data(env, 0xffffff80 + vec * 4);
+         } else {
+             env->pc = cpu_ldl_data(env, env->intb + (vec & 0xff) * 4);
+         }
+--
+.43.0

-New patch
+[PULL 21/21] target/rx: Remove TCG_CALL_NO_WG from helpers which write env
+From: Keith Packard <keithp@keithp.com>
+Functions which modify TCG globals must not be marked TCG_CALL_NO_WG,
+as that tells the optimizer that TCG global values already loaded in
+machine registers are still valid, and so any changes which these
+helpers make to the CPU state may be ignored.
+The target/rx code chooses to put (among other things) all the PSW
+bits and also ACC into globals, so the NO_WG flag on various
+functions that touch the PSW or ACC is incorrect and must be removed.
+This includes all the floating point helper functions, because
+update_fpsw() will update PSW Z and S.
+Signed-off-by: Keith Packard <keithp@keithp.com>
+[PMM: Clarified commit message]
+Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+---
+ target/rx/helper.h | 34 +++++++++++++++++-----------------
+file changed, 17 insertions(+), 17 deletions(-)
+diff --git a/target/rx/helper.h b/target/rx/helper.h
+index XXXXXXX..XXXXXXX 100644
+--- a/target/rx/helper.h
++++ b/target/rx/helper.h
+@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(raise_privilege_violation, noreturn, env)
+ DEF_HELPER_1(wait, noreturn, env)
+ DEF_HELPER_2(rxint, noreturn, env, i32)
+ DEF_HELPER_1(rxbrk, noreturn, env)
+-DEF_HELPER_FLAGS_3(fadd, TCG_CALL_NO_WG, f32, env, f32, f32)
+-DEF_HELPER_FLAGS_3(fsub, TCG_CALL_NO_WG, f32, env, f32, f32)
+-DEF_HELPER_FLAGS_3(fmul, TCG_CALL_NO_WG, f32, env, f32, f32)
+-DEF_HELPER_FLAGS_3(fdiv, TCG_CALL_NO_WG, f32, env, f32, f32)
+-DEF_HELPER_FLAGS_3(fcmp, TCG_CALL_NO_WG, void, env, f32, f32)
+-DEF_HELPER_FLAGS_2(ftoi, TCG_CALL_NO_WG, i32, env, f32)
+-DEF_HELPER_FLAGS_2(round, TCG_CALL_NO_WG, i32, env, f32)
+-DEF_HELPER_FLAGS_2(itof, TCG_CALL_NO_WG, f32, env, i32)
++DEF_HELPER_3(fadd, f32, env, f32, f32)
++DEF_HELPER_3(fsub, f32, env, f32, f32)
++DEF_HELPER_3(fmul, f32, env, f32, f32)
++DEF_HELPER_3(fdiv, f32, env, f32, f32)
++DEF_HELPER_3(fcmp, void, env, f32, f32)
++DEF_HELPER_2(ftoi, i32, env, f32)
++DEF_HELPER_2(round, i32, env, f32)
++DEF_HELPER_2(itof, f32, env, i32)
+ DEF_HELPER_2(set_fpsw, void, env, i32)
+-DEF_HELPER_FLAGS_2(racw, TCG_CALL_NO_WG, void, env, i32)
+-DEF_HELPER_FLAGS_2(set_psw_rte, TCG_CALL_NO_WG, void, env, i32)
+-DEF_HELPER_FLAGS_2(set_psw, TCG_CALL_NO_WG, void, env, i32)
++DEF_HELPER_2(racw, void, env, i32)
++DEF_HELPER_2(set_psw_rte, void, env, i32)
++DEF_HELPER_2(set_psw, void, env, i32)
+ DEF_HELPER_1(pack_psw, i32, env)
+-DEF_HELPER_FLAGS_3(div, TCG_CALL_NO_WG, i32, env, i32, i32)
+-DEF_HELPER_FLAGS_3(divu, TCG_CALL_NO_WG, i32, env, i32, i32)
+-DEF_HELPER_FLAGS_1(scmpu, TCG_CALL_NO_WG, void, env)
++DEF_HELPER_3(div, i32, env, i32, i32)
++DEF_HELPER_3(divu, i32, env, i32, i32)
++DEF_HELPER_1(scmpu, void, env)
+ DEF_HELPER_1(smovu, void, env)
+ DEF_HELPER_1(smovf, void, env)
+ DEF_HELPER_1(smovb, void, env)
+ DEF_HELPER_2(sstr, void, env, i32)
+-DEF_HELPER_FLAGS_2(swhile, TCG_CALL_NO_WG, void, env, i32)
+-DEF_HELPER_FLAGS_2(suntil, TCG_CALL_NO_WG, void, env, i32)
+-DEF_HELPER_FLAGS_2(rmpa, TCG_CALL_NO_WG, void, env, i32)
++DEF_HELPER_2(swhile, void, env, i32)
++DEF_HELPER_2(suntil, void, env, i32)
++DEF_HELPER_2(rmpa, void, env, i32)
+ DEF_HELPER_1(satr, void, env)
+--
+.43.0

Not very much here, but several people have fallen over
the vector operation segfault bug, so let's get the fix
into master.

thanks
-- PMM

The following changes since commit d418238dca7b4e0b124135827ead3076233052b1:

Merge remote-tracking branch 'remotes/rth/tags/pull-rng-20190522' into staging (2019-05-23 12:57:17 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190523

for you to fetch changes up to 98e4f4fdb8ea05d840f51f47125924c2bb9df2df:

hw/arm/exynos4210: QOM'ify the Exynos4210 SoC (2019-05-23 14:47:44 +0100)

----------------------------------------------------------------
target-arm queue:
 * exynos4210: QOM'ify the Exynos4210 SoC
 * exynos4210: Add DMA support for the Exynos4210
 * arm_gicv3: Fix writes to ICC_CTLR_EL3
 * arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
 * target/arm: Fix vector operation segfault
 * target/arm: Minor improvements to BFXIL, EXTR

----------------------------------------------------------------
Alistair Francis (1):
      target/arm: Fix vector operation segfault

Guenter Roeck (1):
      hw/arm/exynos4210: Add DMA support for the Exynos4210

Peter Maydell (5):
      arm: Move system_clock_scale to armv7m_systick.h
      arm: Remove unnecessary includes of hw/arm/arm.h
      arm: Rename hw/arm/arm.h to hw/arm/boot.h
      hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
      hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3

Philippe Mathieu-Daudé (3):
      hw/arm/exynos4: Remove unuseful debug code
      hw/arm/exynos4: Use the IEC binary prefix definitions
      hw/arm/exynos4210: QOM'ify the Exynos4210 SoC

Richard Henderson (2):
      target/arm: Use extract2 for EXTR
      target/arm: Simplify BFXIL expansion

include/hw/arm/allwinner-a10.h    |  2 +-
 include/hw/arm/aspeed_soc.h       |  1 -
 include/hw/arm/bcm2836.h          |  1 -
 include/hw/arm/{arm.h => boot.h}  | 12 +++------
 include/hw/arm/exynos4210.h       |  9 +++++--
 include/hw/arm/fsl-imx25.h        |  2 +-
 include/hw/arm/fsl-imx31.h        |  2 +-
 include/hw/arm/fsl-imx6.h         |  2 +-
 include/hw/arm/fsl-imx6ul.h       |  2 +-
 include/hw/arm/fsl-imx7.h         |  2 +-
 include/hw/arm/virt.h             |  2 +-
 include/hw/arm/xlnx-versal.h      |  2 +-
 include/hw/arm/xlnx-zynqmp.h      |  2 +-
 include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++
 hw/arm/armsse.c                   |  2 +-
 hw/arm/armv7m.c                   |  2 +-
 hw/arm/aspeed.c                   |  2 +-
 hw/arm/boot.c                     |  2 +-
 hw/arm/collie.c                   |  2 +-
 hw/arm/exynos4210.c               | 54 ++++++++++++++++++++++++++++++++++++---
 hw/arm/exynos4_boards.c           | 40 ++++++++---------------------
 hw/arm/highbank.c                 |  2 +-
 hw/arm/integratorcp.c             |  2 +-
 hw/arm/mainstone.c                |  2 +-
 hw/arm/microbit.c                 |  2 +-
 hw/arm/mps2-tz.c                  |  2 +-
 hw/arm/mps2.c                     |  2 +-
 hw/arm/msf2-soc.c                 |  1 -
 hw/arm/msf2-som.c                 |  2 +-
 hw/arm/musca.c                    |  2 +-
 hw/arm/musicpal.c                 |  2 +-
 hw/arm/netduino2.c                |  2 +-
 hw/arm/nrf51_soc.c                |  2 +-
 hw/arm/nseries.c                  |  2 +-
 hw/arm/omap1.c                    |  2 +-
 hw/arm/omap2.c                    |  2 +-
 hw/arm/omap_sx1.c                 |  2 +-
 hw/arm/palm.c                     |  2 +-
 hw/arm/raspi.c                    |  2 +-
 hw/arm/realview.c                 |  2 +-
 hw/arm/spitz.c                    |  2 +-
 hw/arm/stellaris.c                |  2 +-
 hw/arm/stm32f205_soc.c            |  2 +-
 hw/arm/strongarm.c                |  2 +-
 hw/arm/tosa.c                     |  2 +-
 hw/arm/versatilepb.c              |  2 +-
 hw/arm/vexpress.c                 |  2 +-
 hw/arm/virt.c                     |  2 +-
 hw/arm/xilinx_zynq.c              |  2 +-
 hw/arm/xlnx-versal.c              |  2 +-
 hw/arm/z2.c                       |  2 +-
 hw/intc/arm_gicv3_cpuif.c         |  6 ++---
 hw/intc/armv7m_nvic.c             |  1 -
 target/arm/arm-semi.c             |  1 -
 target/arm/cpu.c                  |  1 -
 target/arm/cpu64.c                |  1 -
 target/arm/kvm.c                  |  1 -
 target/arm/kvm32.c                |  1 -
 target/arm/kvm64.c                |  1 -
 target/arm/translate-a64.c        | 44 ++++++++++++++++---------------
 target/arm/translate.c            |  4 +--
 61 files changed, 164 insertions(+), 123 deletions(-)
 rename include/hw/arm/{arm.h => boot.h} (96%)

From: Richard Henderson <richard.henderson@linaro.org>

This is, after all, how we implement extract2 in tcg/aarch64.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190514011129.11330-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 38 ++++++++++++++++++++------------------
 1 file changed, 20 insertions(+), 18 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_extract(DisasContext *s, uint32_t insn)
             } else {
                 tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));
             }
-        } else if (rm == rn) { /* ROR */
-            tcg_rm = cpu_reg(s, rm);
-            if (sf) {
-                tcg_gen_rotri_i64(tcg_rd, tcg_rm, imm);
-            } else {
-                TCGv_i32 tmp = tcg_temp_new_i32();
-                tcg_gen_extrl_i64_i32(tmp, tcg_rm);
-                tcg_gen_rotri_i32(tmp, tmp, imm);
-                tcg_gen_extu_i32_i64(tcg_rd, tmp);
-                tcg_temp_free_i32(tmp);
-            }
         } else {
-            tcg_rm = read_cpu_reg(s, rm, sf);
-            tcg_rn = read_cpu_reg(s, rn, sf);
-            tcg_gen_shri_i64(tcg_rm, tcg_rm, imm);
-            tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm);
-            tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn);
-            if (!sf) {
-                tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
+            tcg_rm = cpu_reg(s, rm);
+            tcg_rn = cpu_reg(s, rn);
+
+            if (sf) {
+                /* Specialization to ROR happens in EXTRACT2.  */
+                tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, imm);
+            } else {
+                TCGv_i32 t0 = tcg_temp_new_i32();
+
+                tcg_gen_extrl_i64_i32(t0, tcg_rm);
+                if (rm == rn) {
+                    tcg_gen_rotri_i32(t0, t0, imm);
+                } else {
+                    TCGv_i32 t1 = tcg_temp_new_i32();
+                    tcg_gen_extrl_i64_i32(t1, tcg_rn);
+                    tcg_gen_extract2_i32(t0, t0, t1, imm);
+                    tcg_temp_free_i32(t1);
+                }
+                tcg_gen_extu_i32_i64(tcg_rd, t0);
+                tcg_temp_free_i32(t0);
             }
         }
     }
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

The mask implied by the extract is redundant with the one
implied by the deposit.  Also, fix spelling of BFXIL.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190514011129.11330-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

From: Alistair Francis <alistair.francis@wdc.com>

Commit 89e68b575 "target/arm: Use vector operations for saturation"
causes this abort() when booting QEMU ARM with a Cortex-A15:

0  0x00007ffff4c2382f in raise () at /usr/lib/libc.so.6
1  0x00007ffff4c0e672 in abort () at /usr/lib/libc.so.6
2  0x00005555559c1839 in disas_neon_data_insn (insn=<optimized out>, s=<optimized out>) at ./target/arm/translate.c:6673
3  0x00005555559c1839 in disas_neon_data_insn (s=<optimized out>, insn=<optimized out>) at ./target/arm/translate.c:6386
4  0x00005555559cd8a4 in disas_arm_insn (insn=4081107068, s=0x7fffe59a9510) at ./target/arm/translate.c:9289
5  0x00005555559cd8a4 in arm_tr_translate_insn (dcbase=0x7fffe59a9510, cpu=<optimized out>) at ./target/arm/translate.c:13612
6  0x00005555558d1d39 in translator_loop (ops=0x5555561cc580 <arm_translator_ops>, db=0x7fffe59a9510, cpu=0x55555686a2f0, tb=<optimized out>, max_insns=<optimized out>) at ./accel/tcg/translator.c:96
7  0x00005555559d10d4 in gen_intermediate_code (cpu=cpu@entry=0x55555686a2f0, tb=tb@entry=0x7fffd7840080 <code_gen_buffer+126091347>, max_insns=max_insns@entry=512) at ./target/arm/translate.c:13901
8  0x00005555558d06b9 in tb_gen_code (cpu=cpu@entry=0x55555686a2f0, pc=3067096216, cs_base=0, flags=192, cflags=-16252928, cflags@entry=524288) at ./accel/tcg/translate-all.c:1736
9  0x00005555558ce467 in tb_find (cf_mask=524288, tb_exit=1, last_tb=0x7fffd783e640 <code_gen_buffer+126084627>, cpu=0x1) at ./accel/tcg/cpu-exec.c:407
10 0x00005555558ce467 in cpu_exec (cpu=cpu@entry=0x55555686a2f0) at ./accel/tcg/cpu-exec.c:728
11 0x000055555588b0cf in tcg_cpu_exec (cpu=0x55555686a2f0) at ./cpus.c:1431
12 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=0x55555686a2f0) at ./cpus.c:1735
13 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=arg@entry=0x55555686a2f0) at ./cpus.c:1709
14 0x0000555555d2629a in qemu_thread_start (args=<optimized out>) at ./util/qemu-thread-posix.c:502
15 0x00007ffff4db8a92 in start_thread () at /usr/lib/libpthread.

This patch ensures that we don't hit the abort() in the second switch
case in disas_neon_data_insn() as we will return from the first case.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: ad91b397f360b2fc7f4087e476f7df5b04d42ddb.1558021877.git.alistair.francis@wdc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
             tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
                            rn_ofs, rm_ofs, vec_size, vec_size,
                            (u ? uqadd_op : sqadd_op) + size);
-            break;
+            return 0;
 
         case NEON_3R_VQSUB:
             tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
                            rn_ofs, rm_ofs, vec_size, vec_size,
                            (u ? uqsub_op : sqsub_op) + size);
-            break;
+            return 0;
 
         case NEON_3R_VMUL: /* VMUL */
             if (u) {
-- 
2.20.1

The system_clock_scale global is used only by the armv7m systick
device; move the extern declaration to the armv7m_systick.h header,
and expand the comment to explain what it is and that it should
ideally be replaced with a different approach.

diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/arm.h
+++ b/include/hw/arm/arm.h
@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
                                             const struct arm_boot_info *info,
                                             hwaddr mvbar_addr);
 
-/* Multiplication factor to convert from system clock ticks to qemu timer
-   ticks.  */
-extern int system_clock_scale;
-
 #endif /* HW_ARM_H */
diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/timer/armv7m_systick.h
+++ b/include/hw/timer/armv7m_systick.h
@@ -XXX,XX +XXX,XX @@ typedef struct SysTickState {
     qemu_irq irq;
 } SysTickState;
 
+/*
+ * Multiplication factor to convert from system clock ticks to qemu timer
+ * ticks. This should be set (by board code, usually) to a value
+ * equal to NANOSECONDS_PER_SECOND / frq, where frq is the clock frequency
+ * in Hz of the CPU.
+ *
+ * This value is used by the systick device when it is running in
+ * its "use the CPU clock" mode (ie when SYST_CSR.CLKSOURCE == 1) to
+ * set how fast the timer should tick.
+ *
+ * TODO: we should refactor this so that rather than using a global
+ * we use a device property or something similar. This is complicated
+ * because (a) the property would need to be plumbed through from the
+ * board code down through various layers to the systick device
+ * and (b) the property needs to be modifiable after realize, because
+ * the stellaris board uses this to implement the behaviour where the
+ * guest can reprogram the PLL registers to downclock the CPU, and the
+ * systick device needs to react accordingly. Possibly this should
+ * be deferred until we have a good API for modelling clock trees.
+ */
+extern int system_clock_scale;
+
 #endif
-- 
2.20.1

The hw/arm/arm.h header now only includes declarations relating
to boot.c code, so it is only needed by Arm board or SoC code.
Remove some unnecessary inclusions of it from target/arm files
and from hw/intc/armv7m_nvic.c.

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@
 #include "cpu.h"
 #include "hw/sysbus.h"
 #include "qemu/timer.h"
-#include "hw/arm/arm.h"
 #include "hw/intc/armv7m_nvic.h"
 #include "target/arm/cpu.h"
 #include "exec/exec-all.h"
diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/arm-semi.c
+++ b/target/arm/arm-semi.c
@@ -XXX,XX +XXX,XX @@
 #else
 #include "qemu-common.h"
 #include "exec/gdbstub.h"
-#include "hw/arm/arm.h"
 #include "qemu/cutils.h"
 #endif
 
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
 #if !defined(CONFIG_USER_ONLY)
 #include "hw/loader.h"
 #endif
-#include "hw/arm/arm.h"
 #include "sysemu/sysemu.h"
 #include "sysemu/hw_accel.h"
 #include "kvm_arm.h"
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@
 #if !defined(CONFIG_USER_ONLY)
 #include "hw/loader.h"
 #endif
-#include "hw/arm/arm.h"
 #include "sysemu/sysemu.h"
 #include "sysemu/kvm.h"
 #include "kvm_arm.h"
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@
 #include "cpu.h"
 #include "trace.h"
 #include "internals.h"
-#include "hw/arm/arm.h"
 #include "hw/pci/pci.h"
 #include "exec/memattrs.h"
 #include "exec/address-spaces.h"
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/kvm.h"
 #include "kvm_arm.h"
 #include "internals.h"
-#include "hw/arm/arm.h"
 #include "qemu/log.h"
 
 static inline void set_feature(uint64_t *features, int feature)
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/kvm.h"
 #include "kvm_arm.h"
 #include "internals.h"
-#include "hw/arm/arm.h"
 
 static bool have_guest_debug;
 
-- 
2.20.1

The header file hw/arm/arm.h now includes only declarations
relating to hw/arm/boot.c functionality. Rename it accordingly,
and adjust its header comment.

The bulk of this commit was created via
 perl -pi -e 's|hw/arm/arm.h|hw/arm/boot.h|' hw/arm/*.c include/hw/arm/*.h

In a few cases we can just delete the #include:
hw/arm/msf2-soc.c, include/hw/arm/aspeed_soc.h and
include/hw/arm/bcm2836.h did not require it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190516163857.6430-4-peter.maydell@linaro.org
---
 include/hw/arm/allwinner-a10.h   | 2 +-
 include/hw/arm/aspeed_soc.h      | 1 -
 include/hw/arm/bcm2836.h         | 1 -
 include/hw/arm/{arm.h => boot.h} | 8 ++++----
 include/hw/arm/fsl-imx25.h       | 2 +-
 include/hw/arm/fsl-imx31.h       | 2 +-
 include/hw/arm/fsl-imx6.h        | 2 +-
 include/hw/arm/fsl-imx6ul.h      | 2 +-
 include/hw/arm/fsl-imx7.h        | 2 +-
 include/hw/arm/virt.h            | 2 +-
 include/hw/arm/xlnx-versal.h     | 2 +-
 include/hw/arm/xlnx-zynqmp.h     | 2 +-
 hw/arm/armsse.c                  | 2 +-
 hw/arm/armv7m.c                  | 2 +-
 hw/arm/aspeed.c                  | 2 +-
 hw/arm/boot.c                    | 2 +-
 hw/arm/collie.c                  | 2 +-
 hw/arm/exynos4210.c              | 2 +-
 hw/arm/exynos4_boards.c          | 2 +-
 hw/arm/highbank.c                | 2 +-
 hw/arm/integratorcp.c            | 2 +-
 hw/arm/mainstone.c               | 2 +-
 hw/arm/microbit.c                | 2 +-
 hw/arm/mps2-tz.c                 | 2 +-
 hw/arm/mps2.c                    | 2 +-
 hw/arm/msf2-soc.c                | 1 -
 hw/arm/msf2-som.c                | 2 +-
 hw/arm/musca.c                   | 2 +-
 hw/arm/musicpal.c                | 2 +-
 hw/arm/netduino2.c               | 2 +-
 hw/arm/nrf51_soc.c               | 2 +-
 hw/arm/nseries.c                 | 2 +-
 hw/arm/omap1.c                   | 2 +-
 hw/arm/omap2.c                   | 2 +-
 hw/arm/omap_sx1.c                | 2 +-
 hw/arm/palm.c                    | 2 +-
 hw/arm/raspi.c                   | 2 +-
 hw/arm/realview.c                | 2 +-
 hw/arm/spitz.c                   | 2 +-
 hw/arm/stellaris.c               | 2 +-
 hw/arm/stm32f205_soc.c           | 2 +-
 hw/arm/strongarm.c               | 2 +-
 hw/arm/tosa.c                    | 2 +-
 hw/arm/versatilepb.c             | 2 +-
 hw/arm/vexpress.c                | 2 +-
 hw/arm/virt.c                    | 2 +-
 hw/arm/xilinx_zynq.c             | 2 +-
 hw/arm/xlnx-versal.c             | 2 +-
 hw/arm/z2.c                      | 2 +-
 49 files changed, 49 insertions(+), 52 deletions(-)
 rename include/hw/arm/{arm.h => boot.h} (98%)

diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/allwinner-a10.h
+++ b/include/hw/arm/allwinner-a10.h
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "qemu/error-report.h"
 #include "hw/char/serial.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/timer/allwinner-a10-pit.h"
 #include "hw/intc/allwinner-a10-pic.h"
 #include "hw/net/allwinner_emac.h"
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@
 #ifndef ASPEED_SOC_H
 #define ASPEED_SOC_H
 
-#include "hw/arm/arm.h"
 #include "hw/intc/aspeed_vic.h"
 #include "hw/misc/aspeed_scu.h"
 #include "hw/misc/aspeed_sdmc.h"
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/bcm2836.h
+++ b/include/hw/arm/bcm2836.h
@@ -XXX,XX +XXX,XX @@
 #ifndef BCM2836_H
 #define BCM2836_H
 
-#include "hw/arm/arm.h"
 #include "hw/arm/bcm2835_peripherals.h"
 #include "hw/intc/bcm2836_control.h"
 
diff --git a/include/hw/arm/arm.h b/include/hw/arm/boot.h
similarity index 98%
rename from include/hw/arm/arm.h
rename to include/hw/arm/boot.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/arm.h
+++ b/include/hw/arm/boot.h
@@ -XXX,XX +XXX,XX @@
 /*
- * Misc ARM declarations
+ * ARM kernel loader.
  *
  * Copyright (c) 2006 CodeSourcery.
  * Written by Paul Brook
@@ -XXX,XX +XXX,XX @@
  *
  */
 
-#ifndef HW_ARM_H
-#define HW_ARM_H
+#ifndef HW_ARM_BOOT_H
+#define HW_ARM_BOOT_H
 
 #include "exec/memory.h"
 #include "target/arm/cpu-qom.h"
@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
                                             const struct arm_boot_info *info,
                                             hwaddr mvbar_addr);
 
-#endif /* HW_ARM_H */
+#endif /* HW_ARM_BOOT_H */
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx25.h
+++ b/include/hw/arm/fsl-imx25.h
@@ -XXX,XX +XXX,XX @@
 #ifndef FSL_IMX25_H
 #define FSL_IMX25_H
 
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/intc/imx_avic.h"
 #include "hw/misc/imx25_ccm.h"
 #include "hw/char/imx_serial.h"
diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx31.h
+++ b/include/hw/arm/fsl-imx31.h
@@ -XXX,XX +XXX,XX @@
 #ifndef FSL_IMX31_H
 #define FSL_IMX31_H
 
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/intc/imx_avic.h"
 #include "hw/misc/imx31_ccm.h"
 #include "hw/char/imx_serial.h"
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6.h
+++ b/include/hw/arm/fsl-imx6.h
@@ -XXX,XX +XXX,XX @@
 #ifndef FSL_IMX6_H
 #define FSL_IMX6_H
 
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/cpu/a9mpcore.h"
 #include "hw/misc/imx6_ccm.h"
 #include "hw/misc/imx6_src.h"
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -XXX,XX +XXX,XX @@
 #ifndef FSL_IMX6UL_H
 #define FSL_IMX6UL_H
 
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/cpu/a15mpcore.h"
 #include "hw/misc/imx6ul_ccm.h"
 #include "hw/misc/imx6_src.h"
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -XXX,XX +XXX,XX @@
 #ifndef FSL_IMX7_H
 #define FSL_IMX7_H
 
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/cpu/a15mpcore.h"
 #include "hw/intc/imx_gpcv2.h"
 #include "hw/misc/imx7_ccm.h"
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -XXX,XX +XXX,XX @@
 #include "exec/hwaddr.h"
 #include "qemu/notify.h"
 #include "hw/boards.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/block/flash.h"
 #include "sysemu/kvm.h"
 #include "hw/intc/arm_gicv3_common.h"
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -XXX,XX +XXX,XX @@
 #define XLNX_VERSAL_H
 
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/intc/arm_gicv3.h"
 
 #define TYPE_XLNX_VERSAL "xlnx-versal"
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -XXX,XX +XXX,XX @@
 #ifndef XLNX_ZYNQMP_H
 
 #include "qemu-common.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/intc/arm_gic.h"
 #include "hw/net/cadence_gem.h"
 #include "hw/char/cadence_uart.h"
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "hw/registerfields.h"
 #include "hw/arm/armsse.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 
 /* Format of the System Information block SYS_CONFIG register */
 typedef enum SysConfigFormat {
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/loader.h"
 #include "elf.h"
 #include "sysemu/qtest.h"
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "exec/address-spaces.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/aspeed.h"
 #include "hw/arm/aspeed_soc.h"
 #include "hw/boards.h"
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include <libfdt.h>
 #include "hw/hw.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/linux-boot-if.h"
 #include "sysemu/kvm.h"
 #include "sysemu/sysemu.h"
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/collie.c
+++ b/hw/arm/collie.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "hw/boards.h"
 #include "strongarm.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/block/flash.h"
 #include "exec/address-spaces.h"
 #include "cpu.h"
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/boards.h"
 #include "sysemu/sysemu.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/loader.h"
 #include "hw/arm/exynos4210.h"
 #include "hw/sd/sdhci.h"
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/sysemu.h"
 #include "hw/sysbus.h"
 #include "net/net.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "exec/address-spaces.h"
 #include "hw/arm/exynos4210.h"
 #include "hw/net/lan9118.h"
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/loader.h"
 #include "net/net.h"
 #include "sysemu/kvm.h"
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -XXX,XX +XXX,XX @@
 #include "cpu.h"
 #include "hw/sysbus.h"
 #include "hw/boards.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/misc/arm_integrator_debug.h"
 #include "hw/net/smc91c111.h"
 #include "net/net.h"
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mainstone.c
+++ b/hw/arm/mainstone.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "hw/hw.h"
 #include "hw/arm/pxa.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "net/net.h"
 #include "hw/net/smc91c111.h"
 #include "hw/boards.h"
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/microbit.c
+++ b/hw/arm/microbit.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "hw/boards.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "sysemu/sysemu.h"
 #include "exec/address-spaces.h"
 
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "qemu/error-report.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/armv7m.h"
 #include "hw/or-irq.h"
 #include "hw/boards.h"
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "qemu/error-report.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/armv7m.h"
 #include "hw/or-irq.h"
 #include "hw/boards.h"
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/msf2-soc.c
+++ b/hw/arm/msf2-soc.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/units.h"
 #include "qapi/error.h"
 #include "qemu-common.h"
-#include "hw/arm/arm.h"
 #include "exec/address-spaces.h"
 #include "hw/char/serial.h"
 #include "hw/boards.h"
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/msf2-som.c
+++ b/hw/arm/msf2-som.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "qemu/error-report.h"
 #include "hw/boards.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "exec/address-spaces.h"
 #include "hw/arm/msf2-soc.h"
 #include "cpu.h"
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/musca.c
+++ b/hw/arm/musca.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "exec/address-spaces.h"
 #include "sysemu/sysemu.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/armsse.h"
 #include "hw/boards.h"
 #include "hw/char/pl011.h"
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/musicpal.c
+++ b/hw/arm/musicpal.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "net/net.h"
 #include "sysemu/sysemu.h"
 #include "hw/boards.h"
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/netduino2.c
+++ b/hw/arm/netduino2.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/boards.h"
 #include "qemu/error-report.h"
 #include "hw/arm/stm32f205_soc.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 
 static void netduino2_init(MachineState *machine)
 {
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/nrf51_soc.c
+++ b/hw/arm/nrf51_soc.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "qemu-common.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/sysbus.h"
 #include "hw/boards.h"
 #include "hw/misc/unimp.h"
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/nseries.c
+++ b/hw/arm/nseries.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/bswap.h"
 #include "sysemu/sysemu.h"
 #include "hw/arm/omap.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/irq.h"
 #include "ui/console.h"
 #include "hw/boards.h"
diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/omap1.c
+++ b/hw/arm/omap1.c
@@ -XXX,XX +XXX,XX @@
 #include "cpu.h"
 #include "hw/boards.h"
 #include "hw/hw.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/omap.h"
 #include "sysemu/sysemu.h"
 #include "hw/arm/soc_dma.h"
diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/omap2.c
+++ b/hw/arm/omap2.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/qtest.h"
 #include "hw/boards.h"
 #include "hw/hw.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/omap.h"
 #include "sysemu/sysemu.h"
 #include "qemu/timer.h"
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/omap_sx1.c
+++ b/hw/arm/omap_sx1.c
@@ -XXX,XX +XXX,XX @@
 #include "ui/console.h"
 #include "hw/arm/omap.h"
 #include "hw/boards.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/block/flash.h"
 #include "sysemu/qtest.h"
 #include "exec/address-spaces.h"
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/palm.c
+++ b/hw/arm/palm.c
@@ -XXX,XX +XXX,XX @@
 #include "ui/console.h"
 #include "hw/arm/omap.h"
 #include "hw/boards.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/input/tsc2xxx.h"
 #include "hw/loader.h"
 #include "exec/address-spaces.h"
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/error-report.h"
 #include "hw/boards.h"
 #include "hw/loader.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "sysemu/sysemu.h"
 
 #define SMPBOOT_ADDR    0x300 /* this should leave enough space for ATAGS */
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/primecell.h"
 #include "hw/net/lan9118.h"
 #include "hw/net/smc91c111.h"
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "hw/hw.h"
 #include "hw/arm/pxa.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "sysemu/sysemu.h"
 #include "hw/pcmcia.h"
 #include "hw/i2c/i2c.h"
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "hw/sysbus.h"
 #include "hw/ssi/ssi.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "qemu/timer.h"
 #include "hw/i2c/i2c.h"
 #include "net/net.h"
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/stm32f205_soc.c
+++ b/hw/arm/stm32f205_soc.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "qemu-common.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "exec/address-spaces.h"
 #include "hw/arm/stm32f205_soc.h"
 
diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/strongarm.c
+++ b/hw/arm/strongarm.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "strongarm.h"
 #include "qemu/error-report.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "chardev/char-fe.h"
 #include "chardev/char-serial.h"
 #include "sysemu/sysemu.h"
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/tosa.c
+++ b/hw/arm/tosa.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "hw/hw.h"
 #include "hw/arm/pxa.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/sharpsl.h"
 #include "hw/pcmcia.h"
 #include "hw/boards.h"
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/versatilepb.c
+++ b/hw/arm/versatilepb.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/net/smc91c111.h"
 #include "net/net.h"
 #include "sysemu/sysemu.h"
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/primecell.h"
 #include "hw/net/lan9118.h"
 #include "hw/i2c/i2c.h"
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/option.h"
 #include "qapi/error.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/primecell.h"
 #include "hw/arm/virt.h"
 #include "hw/block/flash.h"
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "net/net.h"
 #include "exec/address-spaces.h"
 #include "sysemu/sysemu.h"
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@
 #include "net/net.h"
 #include "sysemu/sysemu.h"
 #include "sysemu/kvm.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "kvm_arm.h"
 #include "hw/misc/unimp.h"
 #include "hw/intc/arm_gicv3_common.h"
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/z2.c
+++ b/hw/arm/z2.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "hw/hw.h"
 #include "hw/arm/pxa.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/i2c/i2c.h"
 #include "hw/ssi/ssi.h"
 #include "hw/boards.h"
-- 
2.20.1

In ich_vmcr_write() we enforce "writes of BPR fields to less than
their minimum sets them to the minimum" by doing a "read vbpr and
write it back" operation.  A typo here meant that we weren't handling
writes to these fields correctly, because we were reading from VBPR0
but writing to VBPR1.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190520162809.2677-4-peter.maydell@linaro.org
---
 hw/intc/arm_gicv3_cpuif.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

The ICC_CTLR_EL3 register includes some bits which are aliases
of bits in the ICC_CTLR_EL1(S) and (NS) registers. QEMU chooses
to keep those bits in the cs->icc_ctlr_el1[] struct fields.
Unfortunately a missing '~' in the code to update the bits
in those fields meant that writing to ICC_CTLR_EL3 would corrupt
the ICC_CLTR_EL1 register values.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190520162809.2677-5-peter.maydell@linaro.org
---
 hw/intc/arm_gicv3_cpuif.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
     trace_gicv3_icc_ctlr_el3_write(gicv3_redist_affid(cs), value);
 
     /* *_EL1NS and *_EL1S bits are aliases into the ICC_CTLR_EL1 bits. */
-    cs->icc_ctlr_el1[GICV3_NS] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
+    cs->icc_ctlr_el1[GICV3_NS] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
     if (value & ICC_CTLR_EL3_EOIMODE_EL1NS) {
         cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE;
     }
@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
         cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_CBPR;
     }
 
-    cs->icc_ctlr_el1[GICV3_S] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
+    cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
     if (value & ICC_CTLR_EL3_EOIMODE_EL1S) {
         cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_EOIMODE;
     }
-- 
2.20.1

From: Philippe Mathieu-Daudé <philmd@redhat.com>

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20190520214342.13709-2-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/exynos4_boards.c | 24 ------------------------
 1 file changed, 24 deletions(-)

diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/net/lan9118.h"
 #include "hw/boards.h"
 
-#undef DEBUG
-
-//#define DEBUG
-
-#ifdef DEBUG
-    #undef PRINT_DEBUG
-    #define  PRINT_DEBUG(fmt, args...) \
-        do { \
-            fprintf(stderr, "  [%s:%d]   "fmt, __func__, __LINE__, ##args); \
-        } while (0)
-#else
-    #define  PRINT_DEBUG(fmt, args...)  do {} while (0)
-#endif
-
 #define SMDK_LAN9118_BASE_ADDR      0x05000000
 
 typedef enum Exynos4BoardType {
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
     exynos4_board_binfo.gic_cpu_if_addr =
             EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100;
 
-    PRINT_DEBUG("\n ram_size: %luMiB [0x%08lx]\n"
-            " kernel_filename: %s\n"
-            " kernel_cmdline: %s\n"
-            " initrd_filename: %s\n",
-            exynos4_board_ram_size[board_type] / 1048576,
-            exynos4_board_ram_size[board_type],
-            machine->kernel_filename,
-            machine->kernel_cmdline,
-            machine->initrd_filename);
-
     exynos4_boards_init_ram(s, get_system_memory(),
                             exynos4_board_ram_size[board_type]);
 
-- 
2.20.1

From: Philippe Mathieu-Daudé <philmd@redhat.com>

It eases code review, unit is explicit.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20190520214342.13709-3-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/exynos4_boards.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/units.h"
 #include "qapi/error.h"
 #include "qemu/error-report.h"
 #include "qemu-common.h"
@@ -XXX,XX +XXX,XX @@ static int exynos4_board_smp_bootreg_addr[EXYNOS4_NUM_OF_BOARDS] = {
 };
 
 static unsigned long exynos4_board_ram_size[EXYNOS4_NUM_OF_BOARDS] = {
-    [EXYNOS4_BOARD_NURI]     = 0x40000000,
-    [EXYNOS4_BOARD_SMDKC210] = 0x40000000,
+    [EXYNOS4_BOARD_NURI]     = 1 * GiB,
+    [EXYNOS4_BOARD_SMDKC210] = 1 * GiB,
 };
 
 static struct arm_boot_info exynos4_board_binfo = {
-- 
2.20.1

From: Guenter Roeck <linux@roeck-us.net>

QEMU already supports pl330. Instantiate it for Exynos4210.

Relevant part of Linux arch/arm/boot/dts/exynos4.dtsi:

/ {
    soc: soc {
        amba {
            pdma0: pdma@12680000 {
                compatible = "arm,pl330", "arm,primecell";
                reg = <0x12680000 0x1000>;
                interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&clock CLK_PDMA0>;
                clock-names = "apb_pclk";
                #dma-cells = <1>;
                #dma-channels = <8>;
                #dma-requests = <32>;
            };
            pdma1: pdma@12690000 {
                compatible = "arm,pl330", "arm,primecell";
                reg = <0x12690000 0x1000>;
                interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&clock CLK_PDMA1>;
                clock-names = "apb_pclk";
                #dma-cells = <1>;
                #dma-channels = <8>;
                #dma-requests = <32>;
            };
            mdma1: mdma@12850000 {
                compatible = "arm,pl330", "arm,primecell";
                reg = <0x12850000 0x1000>;
                interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&clock CLK_MDMA>;
                clock-names = "apb_pclk";
                #dma-cells = <1>;
                #dma-channels = <8>;
                #dma-requests = <1>;
            };
        };
    };
};

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190520214342.13709-4-philmd@redhat.com
[PMD: Do not set default qdev properties, create the controllers in the SoC
      rather than the board (Peter Maydell), add dtsi in commit message]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/exynos4210.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@
 /* EHCI */
 #define EXYNOS4210_EHCI_BASE_ADDR           0x12580000
 
+/* DMA */
+#define EXYNOS4210_PL330_BASE0_ADDR         0x12680000
+#define EXYNOS4210_PL330_BASE1_ADDR         0x12690000
+#define EXYNOS4210_PL330_BASE2_ADDR         0x12850000
+
 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
                                     0x09, 0x00, 0x00, 0x00 };
 
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu)
     return (0x9 << ARM_AFF1_SHIFT) | cpu;
 }
 
+static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
+{
+    SysBusDevice *busdev;
+    DeviceState *dev;
+
+    dev = qdev_create(NULL, "pl330");
+    qdev_prop_set_uint8(dev, "num_periph_req",  nreq);
+    qdev_init_nofail(dev);
+    busdev = SYS_BUS_DEVICE(dev);
+    sysbus_mmio_map(busdev, 0, base);
+    sysbus_connect_irq(busdev, 0, irq);
+}
+
 Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
 {
     Exynos4210State *s = g_new0(Exynos4210State, 1);
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
     sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
             s->irq_table[exynos4210_get_irq(28, 3)]);
 
+    /*** DMA controllers ***/
+    pl330_create(EXYNOS4210_PL330_BASE0_ADDR,
+                 qemu_irq_invert(s->irq_table[exynos4210_get_irq(35, 1)]), 32);
+    pl330_create(EXYNOS4210_PL330_BASE1_ADDR,
+                 qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
+    pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
+                 qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
+
     return s;
 }
-- 
2.20.1

From: Philippe Mathieu-Daudé <philmd@redhat.com>

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20190520214342.13709-5-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/exynos4210.h |  9 +++++++--
 hw/arm/exynos4210.c         | 28 ++++++++++++++++++++++++----
 hw/arm/exynos4_boards.c     |  9 ++++++---
 3 files changed, 37 insertions(+), 9 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210Irq {
 } Exynos4210Irq;
 
 typedef struct Exynos4210State {
+    /*< private >*/
+    SysBusDevice parent_obj;
+    /*< public >*/
     ARMCPU *cpu[EXYNOS4210_NCPUS];
     Exynos4210Irq irqs;
     qemu_irq *irq_table;
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210State {
     I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
 } Exynos4210State;
 
+#define TYPE_EXYNOS4210_SOC "exynos4210"
+#define EXYNOS4210_SOC(obj) \
+    OBJECT_CHECK(Exynos4210State, obj, TYPE_EXYNOS4210_SOC)
+
 void exynos4210_write_secondary(ARMCPU *cpu,
         const struct arm_boot_info *info);
 
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem);
-
 /* Initialize exynos4210 IRQ subsystem stub */
 qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
 
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
     sysbus_connect_irq(busdev, 0, irq);
 }
 
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
+static void exynos4210_realize(DeviceState *socdev, Error **errp)
 {
-    Exynos4210State *s = g_new0(Exynos4210State, 1);
+    Exynos4210State *s = EXYNOS4210_SOC(socdev);
+    MemoryRegion *system_mem = get_system_memory();
     qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
     SysBusDevice *busdev;
     DeviceState *dev;
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
                  qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
     pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
                  qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
-
-    return s;
 }
+
+static void exynos4210_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->realize = exynos4210_realize;
+}
+
+static const TypeInfo exynos4210_info = {
+    .name = TYPE_EXYNOS4210_SOC,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(Exynos4210State),
+    .class_init = exynos4210_class_init,
+};
+
+static void exynos4210_register_types(void)
+{
+    type_register_static(&exynos4210_info);
+}
+
+type_init(exynos4210_register_types)
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -XXX,XX +XXX,XX @@ typedef enum Exynos4BoardType {
 } Exynos4BoardType;
 
 typedef struct Exynos4BoardState {
-    Exynos4210State *soc;
+    Exynos4210State soc;
     MemoryRegion dram0_mem;
     MemoryRegion dram1_mem;
 } Exynos4BoardState;
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
     exynos4_boards_init_ram(s, get_system_memory(),
                             exynos4_board_ram_size[board_type]);
 
-    s->soc = exynos4210_init(get_system_memory());
+    object_initialize(&s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC);
+    qdev_set_parent_bus(DEVICE(&s->soc), sysbus_get_default());
+    object_property_set_bool(OBJECT(&s->soc), true, "realized",
+                             &error_fatal);
 
     return s;
 }
@@ -XXX,XX +XXX,XX @@ static void smdkc210_init(MachineState *machine)
                                                       EXYNOS4_BOARD_SMDKC210);
 
     lan9215_init(SMDK_LAN9118_BASE_ADDR,
-            qemu_irq_invert(s->soc->irq_table[exynos4210_get_irq(37, 1)]));
+            qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)]));
     arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo);
 }
 
-- 
2.20.1

Hi; here's a target-arm pullreq to go in before softfreeze.
This is actually pretty much entirely bugfixes (since the
SEL2 timers we implement here are a missing part of a feature
we claim to already implement).

thanks
-- PMM

The following changes since commit 98c7362b1efe651327385a25874a73e008c6549e:

Merge tag 'accel-cpus-20250306' of https://github.com/philmd/qemu into staging (2025-03-07 07:39:49 +0800)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20250307

for you to fetch changes up to 0ce0739d46983e5e88fa9c149cb305689c9d8c6f:

target/rx: Remove TCG_CALL_NO_WG from helpers which write env (2025-03-07 15:03:20 +0000)

----------------------------------------------------------------
target-arm queue:
 * hw/arm/smmu-common: Remove the repeated ttb field
 * hw/gpio: npcm7xx: fixup out-of-bounds access
 * tests/functional/test_arm_sx1: Check whether the serial console is working
 * target/arm: Fix minor bugs in generic timer register handling
 * target/arm: Implement SEL2 physical and virtual timers
 * target/arm: Correct STRD, LDRD atomicity and fault behaviour
 * target/arm: Make dummy debug registers RAZ, not NOP
 * util/qemu-timer.c: Don't warp timer from timerlist_rearm()
 * include/exec/memop.h: Expand comment for MO_ATOM_SUBALIGN
 * hw/arm/smmu: Introduce smmu_configs_inv_sid_range() helper
 * target/rx: Set exception vector base to 0xffffff80
 * target/rx: Remove TCG_CALL_NO_WG from helpers which write env

----------------------------------------------------------------
Alex Bennée (4):
      target/arm: Implement SEL2 physical and virtual timers
      target/arm: Document the architectural names of our GTIMERs
      hw/arm: enable secure EL2 timers for virt machine
      hw/arm: enable secure EL2 timers for sbsa machine

JianChunfu (2):
      hw/arm/smmu-common: Remove the repeated ttb field
      hw/arm/smmu: Introduce smmu_configs_inv_sid_range() helper

Keith Packard (2):
      target/rx: Set exception vector base to 0xffffff80
      target/rx: Remove TCG_CALL_NO_WG from helpers which write env

Patrick Venture (1):
      hw/gpio: npcm7xx: fixup out-of-bounds access

Peter Maydell (11):
      target/arm: Apply correct timer offset when calculating deadlines
      target/arm: Don't apply CNTVOFF_EL2 for EL2_VIRT timer
      target/arm: Make CNTPS_* UNDEF from Secure EL1 when Secure EL2 is enabled
      target/arm: Always apply CNTVOFF_EL2 for CNTV_TVAL_EL02 accesses
      target/arm: Refactor handling of timer offset for direct register accesses
      target/arm: Correct LDRD atomicity and fault behaviour
      target/arm: Correct STRD atomicity
      target/arm: Drop unused address_offset from op_addr_{rr, ri}_post()
      target/arm: Make dummy debug registers RAZ, not NOP
      util/qemu-timer.c: Don't warp timer from timerlist_rearm()
      include/exec/memop.h: Expand comment for MO_ATOM_SUBALIGN

Thomas Huth (1):
      tests/functional/test_arm_sx1: Check whether the serial console is working

From: JianChunfu <jansef.jian@hj-micro.com>

SMMUTransCfg->ttb is never used in QEMU, TT base address
can be accessed by SMMUTransCfg->tt[i]->ttb.

Signed-off-by: JianChunfu <jansef.jian@hj-micro.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20250221031034.69822-1-jansef.jian@hj-micro.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/smmu-common.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/smmu-common.h
+++ b/include/hw/arm/smmu-common.h
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUTransCfg {
     /* Used by stage-1 only. */
     bool aa64;                 /* arch64 or aarch32 translation table */
     bool record_faults;        /* record fault events */
-    uint64_t ttb;              /* TT base address */
     uint8_t oas;               /* output address width */
     uint8_t tbi;               /* Top Byte Ignore */
     int asid;
-- 
2.43.0

From: Patrick Venture <venture@google.com>

The reg isn't validated to be a possible register before
it's dereferenced for one case.  The mmio space registered
for the gpio device is 4KiB but there aren't that many
registers in the struct.

Cc: qemu-stable@nongnu.org
Fixes: 526dbbe0874 ("hw/gpio: Add GPIO model for Nuvoton NPCM7xx")
Signed-off-by: Patrick Venture <venture@google.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250226024603.493148-1-venture@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/gpio/npcm7xx_gpio.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/hw/gpio/npcm7xx_gpio.c b/hw/gpio/npcm7xx_gpio.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/gpio/npcm7xx_gpio.c
+++ b/hw/gpio/npcm7xx_gpio.c
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_gpio_regs_write(void *opaque, hwaddr addr, uint64_t v,
         return;
     }
 
-    diff = s->regs[reg] ^ value;
-
     switch (reg) {
     case NPCM7XX_GPIO_TLOCK1:
     case NPCM7XX_GPIO_TLOCK2:
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_gpio_regs_write(void *opaque, hwaddr addr, uint64_t v,
     case NPCM7XX_GPIO_PU:
     case NPCM7XX_GPIO_PD:
     case NPCM7XX_GPIO_IEM:
+        diff = s->regs[reg] ^ value;
         s->regs[reg] = value;
         npcm7xx_gpio_update_pins(s, diff);
         break;
-- 
2.43.0

From: Thomas Huth <thuth@redhat.com>

The kernel that is used in the sx1 test prints the usual Linux log
onto the serial console, but this test currently ignores it. To
make sure that the serial device is working properly, let's check
for some strings in the output here.

While we're at it, also add the test to the corresponding section
in the MAINTAINERS file.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250226104833.1176253-1-thuth@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 MAINTAINERS                      | 1 +
 tests/functional/test_arm_sx1.py | 7 ++++---
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ S: Maintained
 F: hw/*/omap*
 F: include/hw/arm/omap.h
 F: docs/system/arm/sx1.rst
+F: tests/functional/test_arm_sx1.py
 
 IPack
 M: Alberto Garcia <berto@igalia.com>
diff --git a/tests/functional/test_arm_sx1.py b/tests/functional/test_arm_sx1.py
index XXXXXXX..XXXXXXX 100755
--- a/tests/functional/test_arm_sx1.py
+++ b/tests/functional/test_arm_sx1.py
@@ -XXX,XX +XXX,XX @@ def test_arm_sx1_initrd(self):
         self.vm.add_args('-append', f'kunit.enable=0 rdinit=/sbin/init {self.CONSOLE_ARGS}')
         self.vm.add_args('-no-reboot')
         self.launch_kernel(zimage_path,
-                           initrd=initrd_path)
+                           initrd=initrd_path,
+                           wait_for='Boot successful')
         self.vm.wait(timeout=120)
 
     def test_arm_sx1_sd(self):
@@ -XXX,XX +XXX,XX @@ def test_arm_sx1_sd(self):
         self.vm.add_args('-no-reboot')
         self.vm.add_args('-snapshot')
         self.vm.add_args('-drive', f'format=raw,if=sd,file={sd_fs_path}')
-        self.launch_kernel(zimage_path)
+        self.launch_kernel(zimage_path, wait_for='Boot successful')
         self.vm.wait(timeout=120)
 
     def test_arm_sx1_flash(self):
@@ -XXX,XX +XXX,XX @@ def test_arm_sx1_flash(self):
         self.vm.add_args('-no-reboot')
         self.vm.add_args('-snapshot')
         self.vm.add_args('-drive', f'format=raw,if=pflash,file={flash_path}')
-        self.launch_kernel(zimage_path)
+        self.launch_kernel(zimage_path, wait_for='Boot successful')
         self.vm.wait(timeout=120)
 
 if __name__ == '__main__':
-- 
2.43.0

When we are calculating timer deadlines, the correct definition of
whether or not to apply an offset to the physical count is described
in the Arm ARM DDI4087 rev L.a section D12.2.4.1.  This is different
from when the offset should be applied for a direct read of the
counter sysreg.

We got this right for the EL1 physical timer and for the EL1 virtual
timer, but got all the rest wrong: they should be using a zero offset
always.

Factor the offset calculation out into a function that has a comment
documenting exactly which offset it is calculating and which gets the
HYP, SEC, and HYPVIRT cases right.

Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20250204125009.2281315-2-peter.maydell@linaro.org
---
 target/arm/helper.c | 29 +++++++++++++++++++++++++++--
 1 file changed, 27 insertions(+), 2 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static uint64_t gt_phys_cnt_offset(CPUARMState *env)
     return gt_phys_raw_cnt_offset(env);
 }
 
+static uint64_t gt_indirect_access_timer_offset(CPUARMState *env, int timeridx)
+{
+    /*
+     * Return the timer offset to use for indirect accesses to the timer.
+     * This is the Offset value as defined in D12.2.4.1 "Operation of the
+     * CompareValue views of the timers".
+     *
+     * The condition here is not always the same as the condition for
+     * whether to apply an offset register when doing a direct read of
+     * the counter sysreg; those conditions are described in the
+     * access pseudocode for each counter register.
+     */
+    switch (timeridx) {
+    case GTIMER_PHYS:
+        return gt_phys_raw_cnt_offset(env);
+    case GTIMER_VIRT:
+        return env->cp15.cntvoff_el2;
+    case GTIMER_HYP:
+    case GTIMER_SEC:
+    case GTIMER_HYPVIRT:
+        return 0;
+    default:
+        g_assert_not_reached();
+    }
+}
+
 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
 {
     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
@@ -XXX,XX +XXX,XX @@ static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
          * Timer enabled: calculate and set current ISTATUS, irq, and
          * reset timer to when ISTATUS next has to change
          */
-        uint64_t offset = timeridx == GTIMER_VIRT ?
-            cpu->env.cp15.cntvoff_el2 : gt_phys_raw_cnt_offset(&cpu->env);
+        uint64_t offset = gt_indirect_access_timer_offset(&cpu->env, timeridx);
         uint64_t count = gt_get_countervalue(&cpu->env);
         /* Note that this must be unsigned 64 bit arithmetic: */
         int istatus = count - offset >= gt->cval;
-- 
2.43.0

The CNTVOFF_EL2 offset register should only be applied for accessses
to CNTVCT_EL0 and for the EL1 virtual timer (CNTV_*).  We were
incorrectly applying it for the EL2 virtual timer (CNTHV_*).

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
 
     switch (timeridx) {
     case GTIMER_VIRT:
-    case GTIMER_HYPVIRT:
         offset = gt_virt_cnt_offset(env);
         break;
     case GTIMER_PHYS:
@@ -XXX,XX +XXX,XX @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
 
     switch (timeridx) {
     case GTIMER_VIRT:
-    case GTIMER_HYPVIRT:
         offset = gt_virt_cnt_offset(env);
         break;
     case GTIMER_PHYS:
-- 
2.43.0

When we added Secure EL2 support, we missed that this needs an update
to the access code for the EL3 physical timer registers.  These are
supposed to UNDEF from Secure EL1 when Secure EL2 is enabled.

(Note for stable backporting: for backports to branches where
CP_ACCESS_UNDEFINED is not defined, the old name to use instead
is CP_ACCESS_TRAP_UNCATEGORIZED.)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_stimer_access(CPUARMState *env,
         if (!arm_is_secure(env)) {
             return CP_ACCESS_UNDEFINED;
         }
+        if (arm_is_el2_enabled(env)) {
+            return CP_ACCESS_UNDEFINED;
+        }
         if (!(env->cp15.scr_el3 & SCR_ST)) {
             return CP_ACCESS_TRAP_EL3;
         }
-- 
2.43.0

Currently we handle CNTV_TVAL_EL02 by calling gt_tval_read() for the
EL1 virt timer.  This is almost correct, but the underlying
CNTV_TVAL_EL0 register behaves slightly differently.  CNTV_TVAL_EL02
always applies the CNTVOFF_EL2 offset; CNTV_TVAL_EL0 doesn't do so if
we're at EL2 and HCR_EL2.E2H is 1.

We were getting this wrong, because we ended up in
gt_virt_cnt_offset() and did the E2H check.

Factor out the tval read/write calculation from the selection of the
offset, so that we can special case gt_virt_tval_read() and
gt_virt_tval_write() to unconditionally pass CNTVOFF_EL2.

Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20250204125009.2281315-5-peter.maydell@linaro.org
---
 target/arm/helper.c | 36 +++++++++++++++++++++++++++---------
 1 file changed, 27 insertions(+), 9 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
     gt_recalc_timer(env_archcpu(env), timeridx);
 }
 
+static uint64_t do_tval_read(CPUARMState *env, int timeridx, uint64_t offset)
+{
+    return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
+                      (gt_get_countervalue(env) - offset));
+}
+
 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
                              int timeridx)
 {
@@ -XXX,XX +XXX,XX @@ static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
         break;
     }
 
-    return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
-                      (gt_get_countervalue(env) - offset));
+    return do_tval_read(env, timeridx, offset);
+}
+
+static void do_tval_write(CPUARMState *env, int timeridx, uint64_t value,
+                          uint64_t offset)
+{
+    trace_arm_gt_tval_write(timeridx, value);
+    env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
+                                         sextract64(value, 0, 32);
+    gt_recalc_timer(env_archcpu(env), timeridx);
 }
 
 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
         offset = gt_phys_cnt_offset(env);
         break;
     }
-
-    trace_arm_gt_tval_write(timeridx, value);
-    env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) - offset +
-                                         sextract64(value, 0, 32);
-    gt_recalc_timer(env_archcpu(env), timeridx);
+    do_tval_write(env, timeridx, value, offset);
 }
 
 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static void gt_virt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
 
 static uint64_t gt_virt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
-    return gt_tval_read(env, ri, GTIMER_VIRT);
+    /*
+     * This is CNTV_TVAL_EL02; unlike the underlying CNTV_TVAL_EL0
+     * we always apply CNTVOFF_EL2. Special case that here rather
+     * than going into the generic gt_tval_read() and then having
+     * to re-detect that it's this register.
+     * Note that the accessfn/perms mean we know we're at EL2 or EL3 here.
+     */
+    return do_tval_read(env, GTIMER_VIRT, env->cp15.cntvoff_el2);
 }
 
 static void gt_virt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
                                uint64_t value)
 {
-    gt_tval_write(env, ri, GTIMER_VIRT, value);
+    /* Similarly for writes to CNTV_TVAL_EL02 */
+    do_tval_write(env, GTIMER_VIRT, value, env->cp15.cntvoff_el2);
 }
 
 static void gt_virt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
-- 
2.43.0

When reading or writing the timer registers, sometimes we need to
apply one of the timer offsets.  Specifically, this happens for
direct reads of the counter registers CNTPCT_EL0 and CNTVCT_EL0 (and
their self-synchronized variants CNTVCTSS_EL0 and CNTPCTSS_EL0).  It
also applies for direct reads and writes of the CNT*_TVAL_EL*
registers that provide the 32-bit downcounting view of each timer.

We currently do this with duplicated code in gt_tval_read() and
gt_tval_write() and a special-case in gt_virt_cnt_read() and
gt_cnt_read().  Refactor this so that we handle it all in a single
function gt_direct_access_timer_offset(), to parallel how we handle
the offset for indirect accesses.

The call in the WFIT helper previously to gt_virt_cnt_offset() is
now to gt_direct_access_timer_offset(); this is the correct
behaviour, but it's not immediately obvious that it shouldn't be
considered an indirect access, so we add an explanatory comment.

This commit should make no behavioural changes.

(Cc to stable because the following bugfix commit will
depend on this one.)

Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20250204125009.2281315-6-peter.maydell@linaro.org
---
 target/arm/internals.h     |   5 +-
 target/arm/helper.c        | 103 +++++++++++++++++++------------------
 target/arm/tcg/op_helper.c |   8 ++-
 3 files changed, 62 insertions(+), 54 deletions(-)

diff --git a/target/arm/internals.h b/target/arm/internals.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -XXX,XX +XXX,XX @@ int delete_hw_watchpoint(target_ulong addr, target_ulong len, int type);
 uint64_t gt_get_countervalue(CPUARMState *env);
 /*
  * Return the currently applicable offset between the system counter
- * and CNTVCT_EL0 (this will be either 0 or the value of CNTVOFF_EL2).
+ * and the counter for the specified timer, as used for direct register
+ * accesses.
  */
-uint64_t gt_virt_cnt_offset(CPUARMState *env);
+uint64_t gt_direct_access_timer_offset(CPUARMState *env, int timeridx);
 
 /*
  * Return mask of ARMMMUIdxBit values corresponding to an "invalidate
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static uint64_t gt_phys_raw_cnt_offset(CPUARMState *env)
     return 0;
 }
 
-static uint64_t gt_phys_cnt_offset(CPUARMState *env)
-{
-    if (arm_current_el(env) >= 2) {
-        return 0;
-    }
-    return gt_phys_raw_cnt_offset(env);
-}
-
 static uint64_t gt_indirect_access_timer_offset(CPUARMState *env, int timeridx)
 {
     /*
@@ -XXX,XX +XXX,XX @@ static uint64_t gt_indirect_access_timer_offset(CPUARMState *env, int timeridx)
     }
 }
 
+uint64_t gt_direct_access_timer_offset(CPUARMState *env, int timeridx)
+{
+    /*
+     * Return the timer offset to use for direct accesses to the
+     * counter registers CNTPCT and CNTVCT, and for direct accesses
+     * to the CNT*_TVAL registers.
+     *
+     * This isn't exactly the same as the indirect-access offset,
+     * because here we also care about what EL the register access
+     * is being made from.
+     *
+     * This corresponds to the access pseudocode for the registers.
+     */
+    uint64_t hcr;
+
+    switch (timeridx) {
+    case GTIMER_PHYS:
+        if (arm_current_el(env) >= 2) {
+            return 0;
+        }
+        return gt_phys_raw_cnt_offset(env);
+    case GTIMER_VIRT:
+        switch (arm_current_el(env)) {
+        case 2:
+            hcr = arm_hcr_el2_eff(env);
+            if (hcr & HCR_E2H) {
+                return 0;
+            }
+            break;
+        case 0:
+            hcr = arm_hcr_el2_eff(env);
+            if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
+                return 0;
+            }
+            break;
+        }
+        return env->cp15.cntvoff_el2;
+    case GTIMER_HYP:
+    case GTIMER_SEC:
+    case GTIMER_HYPVIRT:
+        return 0;
+    default:
+        g_assert_not_reached();
+    }
+}
+
 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
 {
     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
@@ -XXX,XX +XXX,XX @@ static void gt_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri,
 
 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
-    return gt_get_countervalue(env) - gt_phys_cnt_offset(env);
-}
-
-uint64_t gt_virt_cnt_offset(CPUARMState *env)
-{
-    uint64_t hcr;
-
-    switch (arm_current_el(env)) {
-    case 2:
-        hcr = arm_hcr_el2_eff(env);
-        if (hcr & HCR_E2H) {
-            return 0;
-        }
-        break;
-    case 0:
-        hcr = arm_hcr_el2_eff(env);
-        if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) {
-            return 0;
-        }
-        break;
-    }
-
-    return env->cp15.cntvoff_el2;
+    uint64_t offset = gt_direct_access_timer_offset(env, GTIMER_PHYS);
+    return gt_get_countervalue(env) - offset;
 }
 
 static uint64_t gt_virt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
-    return gt_get_countervalue(env) - gt_virt_cnt_offset(env);
+    uint64_t offset = gt_direct_access_timer_offset(env, GTIMER_VIRT);
+    return gt_get_countervalue(env) - offset;
 }
 
 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -XXX,XX +XXX,XX @@ static uint64_t do_tval_read(CPUARMState *env, int timeridx, uint64_t offset)
 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri,
                              int timeridx)
 {
-    uint64_t offset = 0;
-
-    switch (timeridx) {
-    case GTIMER_VIRT:
-        offset = gt_virt_cnt_offset(env);
-        break;
-    case GTIMER_PHYS:
-        offset = gt_phys_cnt_offset(env);
-        break;
-    }
+    uint64_t offset = gt_direct_access_timer_offset(env, timeridx);
 
     return do_tval_read(env, timeridx, offset);
 }
@@ -XXX,XX +XXX,XX @@ static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
                           int timeridx,
                           uint64_t value)
 {
-    uint64_t offset = 0;
+    uint64_t offset = gt_direct_access_timer_offset(env, timeridx);
 
-    switch (timeridx) {
-    case GTIMER_VIRT:
-        offset = gt_virt_cnt_offset(env);
-        break;
-    case GTIMER_PHYS:
-        offset = gt_phys_cnt_offset(env);
-        break;
-    }
     do_tval_write(env, timeridx, value, offset);
 }
 
diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/op_helper.c
+++ b/target/arm/tcg/op_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(wfit)(CPUARMState *env, uint64_t timeout)
     int target_el = check_wfx_trap(env, false, &excp);
     /* The WFIT should time out when CNTVCT_EL0 >= the specified value. */
     uint64_t cntval = gt_get_countervalue(env);
-    uint64_t offset = gt_virt_cnt_offset(env);
+    /*
+     * We want the value that we would get if we read CNTVCT_EL0 from
+     * the current exception level, so the direct_access offset, not
+     * the indirect_access one. Compare the pseudocode LocalTimeoutEvent(),
+     * which calls VirtualCounterTimer().
+     */
+    uint64_t offset = gt_direct_access_timer_offset(env, GTIMER_VIRT);
     uint64_t cntvct = cntval - offset;
     uint64_t nexttick;
 
-- 
2.43.0

From: Alex Bennée <alex.bennee@linaro.org>

When FEAT_SEL2 was implemented the SEL2 timers were missed. This
shows up when building the latest Hafnium with SPMC_AT_EL=2. The
actual implementation utilises the same logic as the rest of the
timers so all we need to do is:

- define the timers and their access functions
  - conditionally add the correct system registers
  - create a new accessfn as the rules are subtly different to the
    existing secure timer

Fixes: e9152ee91c (target/arm: add ARMv8.4-SEL2 system registers)
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20250204125009.2281315-7-peter.maydell@linaro.org
Cc: qemu-stable@nongnu.org
Cc: Andrei Homescu <ahomescu@google.com>
Cc: Arve Hjønnevåg <arve@google.com>
Cc: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
[PMM: CP_ACCESS_TRAP_UNCATEGORIZED -> CP_ACCESS_UNDEFINED;
 offset logic now in gt_{indirect,direct}_access_timer_offset() ]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/bsa.h |   2 +
 target/arm/cpu.h     |   2 +
 target/arm/gtimer.h  |   4 +-
 target/arm/cpu.c     |   4 ++
 target/arm/helper.c  | 163 +++++++++++++++++++++++++++++++++++++++++++
 5 files changed, 174 insertions(+), 1 deletion(-)

diff --git a/include/hw/arm/bsa.h b/include/hw/arm/bsa.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/bsa.h
+++ b/include/hw/arm/bsa.h
@@ -XXX,XX +XXX,XX @@
 #define QEMU_ARM_BSA_H
 
 /* These are architectural INTID values */
+#define ARCH_TIMER_S_EL2_VIRT_IRQ  19
+#define ARCH_TIMER_S_EL2_IRQ       20
 #define VIRTUAL_PMU_IRQ            23
 #define ARCH_GIC_MAINT_IRQ         25
 #define ARCH_TIMER_NS_EL2_IRQ      26
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ void arm_gt_vtimer_cb(void *opaque);
 void arm_gt_htimer_cb(void *opaque);
 void arm_gt_stimer_cb(void *opaque);
 void arm_gt_hvtimer_cb(void *opaque);
+void arm_gt_sel2timer_cb(void *opaque);
+void arm_gt_sel2vtimer_cb(void *opaque);
 
 unsigned int gt_cntfrq_period_ns(ARMCPU *cpu);
 void gt_rme_post_el_change(ARMCPU *cpu, void *opaque);
diff --git a/target/arm/gtimer.h b/target/arm/gtimer.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gtimer.h
+++ b/target/arm/gtimer.h
@@ -XXX,XX +XXX,XX @@ enum {
     GTIMER_HYP      = 2,
     GTIMER_SEC      = 3,
     GTIMER_HYPVIRT  = 4,
-#define NUM_GTIMERS   5
+    GTIMER_S_EL2_PHYS = 5, /* CNTHPS_* ; only if FEAT_SEL2 */
+    GTIMER_S_EL2_VIRT = 6, /* CNTHVS_* ; only if FEAT_SEL2 */
+#define NUM_GTIMERS   7
 };
 
 #endif
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
                                               arm_gt_stimer_cb, cpu);
         cpu->gt_timer[GTIMER_HYPVIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
                                                   arm_gt_hvtimer_cb, cpu);
+        cpu->gt_timer[GTIMER_S_EL2_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
+                                                     arm_gt_sel2timer_cb, cpu);
+        cpu->gt_timer[GTIMER_S_EL2_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, scale,
+                                                     arm_gt_sel2vtimer_cb, cpu);
     }
 #endif
 
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gt_stimer_access(CPUARMState *env,
     }
 }
 
+static CPAccessResult gt_sel2timer_access(CPUARMState *env,
+                                          const ARMCPRegInfo *ri,
+                                          bool isread)
+{
+    /*
+     * The AArch64 register view of the secure EL2 timers are mostly
+     * accessible from EL3 and EL2 although can also be trapped to EL2
+     * from EL1 depending on nested virt config.
+     */
+    switch (arm_current_el(env)) {
+    case 0: /* UNDEFINED */
+        return CP_ACCESS_UNDEFINED;
+    case 1:
+        if (!arm_is_secure(env)) {
+            /* UNDEFINED */
+            return CP_ACCESS_UNDEFINED;
+        } else if (arm_hcr_el2_eff(env) & HCR_NV) {
+            /* Aarch64.SystemAccessTrap(EL2, 0x18) */
+            return CP_ACCESS_TRAP_EL2;
+        }
+        /* UNDEFINED */
+        return CP_ACCESS_UNDEFINED;
+    case 2:
+        if (!arm_is_secure(env)) {
+            /* UNDEFINED */
+            return CP_ACCESS_UNDEFINED;
+        }
+        return CP_ACCESS_OK;
+    case 3:
+        if (env->cp15.scr_el3 & SCR_EEL2) {
+            return CP_ACCESS_OK;
+        } else {
+            return CP_ACCESS_UNDEFINED;
+        }
+    default:
+        g_assert_not_reached();
+    }
+}
+
 uint64_t gt_get_countervalue(CPUARMState *env)
 {
     ARMCPU *cpu = env_archcpu(env);
@@ -XXX,XX +XXX,XX @@ static uint64_t gt_indirect_access_timer_offset(CPUARMState *env, int timeridx)
     case GTIMER_HYP:
     case GTIMER_SEC:
     case GTIMER_HYPVIRT:
+    case GTIMER_S_EL2_PHYS:
+    case GTIMER_S_EL2_VIRT:
         return 0;
     default:
         g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ uint64_t gt_direct_access_timer_offset(CPUARMState *env, int timeridx)
     case GTIMER_HYP:
     case GTIMER_SEC:
     case GTIMER_HYPVIRT:
+    case GTIMER_S_EL2_PHYS:
+    case GTIMER_S_EL2_VIRT:
         return 0;
     default:
         g_assert_not_reached();
@@ -XXX,XX +XXX,XX @@ static void gt_sec_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
     gt_ctl_write(env, ri, GTIMER_SEC, value);
 }
 
+static void gt_sec_pel2_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    gt_timer_reset(env, ri, GTIMER_S_EL2_PHYS);
+}
+
+static void gt_sec_pel2_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                                   uint64_t value)
+{
+    gt_cval_write(env, ri, GTIMER_S_EL2_PHYS, value);
+}
+
+static uint64_t gt_sec_pel2_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    return gt_tval_read(env, ri, GTIMER_S_EL2_PHYS);
+}
+
+static void gt_sec_pel2_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                              uint64_t value)
+{
+    gt_tval_write(env, ri, GTIMER_S_EL2_PHYS, value);
+}
+
+static void gt_sec_pel2_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                              uint64_t value)
+{
+    gt_ctl_write(env, ri, GTIMER_S_EL2_PHYS, value);
+}
+
+static void gt_sec_vel2_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    gt_timer_reset(env, ri, GTIMER_S_EL2_VIRT);
+}
+
+static void gt_sec_vel2_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                              uint64_t value)
+{
+    gt_cval_write(env, ri, GTIMER_S_EL2_VIRT, value);
+}
+
+static uint64_t gt_sec_vel2_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+    return gt_tval_read(env, ri, GTIMER_S_EL2_VIRT);
+}
+
+static void gt_sec_vel2_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                                   uint64_t value)
+{
+    gt_tval_write(env, ri, GTIMER_S_EL2_VIRT, value);
+}
+
+static void gt_sec_vel2_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
+                              uint64_t value)
+{
+    gt_ctl_write(env, ri, GTIMER_S_EL2_VIRT, value);
+}
+
 static void gt_hv_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri)
 {
     gt_timer_reset(env, ri, GTIMER_HYPVIRT);
@@ -XXX,XX +XXX,XX @@ void arm_gt_stimer_cb(void *opaque)
     gt_recalc_timer(cpu, GTIMER_SEC);
 }
 
+void arm_gt_sel2timer_cb(void *opaque)
+{
+    ARMCPU *cpu = opaque;
+
+    gt_recalc_timer(cpu, GTIMER_S_EL2_PHYS);
+}
+
+void arm_gt_sel2vtimer_cb(void *opaque)
+{
+    ARMCPU *cpu = opaque;
+
+    gt_recalc_timer(cpu, GTIMER_S_EL2_VIRT);
+}
+
 void arm_gt_hvtimer_cb(void *opaque)
 {
     ARMCPU *cpu = opaque;
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] = {
       .access = PL2_RW, .accessfn = sel2_access,
       .nv2_redirect_offset = 0x48,
       .fieldoffset = offsetof(CPUARMState, cp15.vstcr_el2) },
+#ifndef CONFIG_USER_ONLY
+    /* Secure EL2 Physical Timer */
+    { .name = "CNTHPS_TVAL_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 5, .opc2 = 0,
+      .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW,
+      .accessfn = gt_sel2timer_access,
+      .readfn = gt_sec_pel2_tval_read,
+      .writefn = gt_sec_pel2_tval_write,
+      .resetfn = gt_sec_pel2_timer_reset,
+    },
+    { .name = "CNTHPS_CTL_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 5, .opc2 = 1,
+      .type = ARM_CP_IO, .access = PL2_RW,
+      .accessfn = gt_sel2timer_access,
+      .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_S_EL2_PHYS].ctl),
+      .resetvalue = 0,
+      .writefn = gt_sec_pel2_ctl_write, .raw_writefn = raw_write,
+    },
+    { .name = "CNTHPS_CVAL_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 5, .opc2 = 2,
+      .type = ARM_CP_IO, .access = PL2_RW,
+      .accessfn = gt_sel2timer_access,
+      .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_S_EL2_PHYS].cval),
+      .writefn = gt_sec_pel2_cval_write, .raw_writefn = raw_write,
+    },
+    /* Secure EL2 Virtual Timer */
+    { .name = "CNTHVS_TVAL_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 4, .opc2 = 0,
+      .type = ARM_CP_NO_RAW | ARM_CP_IO, .access = PL2_RW,
+      .accessfn = gt_sel2timer_access,
+      .readfn = gt_sec_vel2_tval_read,
+      .writefn = gt_sec_vel2_tval_write,
+      .resetfn = gt_sec_vel2_timer_reset,
+    },
+    { .name = "CNTHVS_CTL_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 4, .opc2 = 1,
+      .type = ARM_CP_IO, .access = PL2_RW,
+      .accessfn = gt_sel2timer_access,
+      .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_S_EL2_VIRT].ctl),
+      .resetvalue = 0,
+      .writefn = gt_sec_vel2_ctl_write, .raw_writefn = raw_write,
+    },
+    { .name = "CNTHVS_CVAL_EL2", .state = ARM_CP_STATE_AA64,
+      .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 4, .opc2 = 2,
+      .type = ARM_CP_IO, .access = PL2_RW,
+      .accessfn = gt_sel2timer_access,
+      .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_S_EL2_VIRT].cval),
+      .writefn = gt_sec_vel2_cval_write, .raw_writefn = raw_write,
+    },
+#endif
 };
 
 static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
-- 
2.43.0

From: Alex Bennée <alex.bennee@linaro.org>

As we are about to add more physical and virtual timers let's make it
clear what each timer does.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20250204125009.2281315-8-peter.maydell@linaro.org
[PMM: Add timer register name prefix to each comment]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/gtimer.h | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/target/arm/gtimer.h b/target/arm/gtimer.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/gtimer.h
+++ b/target/arm/gtimer.h
@@ -XXX,XX +XXX,XX @@
 #define TARGET_ARM_GTIMER_H
 
 enum {
-    GTIMER_PHYS     = 0,
-    GTIMER_VIRT     = 1,
-    GTIMER_HYP      = 2,
-    GTIMER_SEC      = 3,
-    GTIMER_HYPVIRT  = 4,
+    GTIMER_PHYS     = 0, /* CNTP_* ; EL1 physical timer */
+    GTIMER_VIRT     = 1, /* CNTV_* ; EL1 virtual timer */
+    GTIMER_HYP      = 2, /* CNTHP_* ; EL2 physical timer */
+    GTIMER_SEC      = 3, /* CNTPS_* ; EL3 physical timer */
+    GTIMER_HYPVIRT  = 4, /* CNTHV_* ; EL2 virtual timer ; only if FEAT_VHE */
     GTIMER_S_EL2_PHYS = 5, /* CNTHPS_* ; only if FEAT_SEL2 */
     GTIMER_S_EL2_VIRT = 6, /* CNTHVS_* ; only if FEAT_SEL2 */
 #define NUM_GTIMERS   7
-- 
2.43.0

From: Alex Bennée <alex.bennee@linaro.org>

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20250204125009.2281315-9-peter.maydell@linaro.org
Cc: qemu-stable@nongnu.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/virt.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem)
             [GTIMER_HYP]  = ARCH_TIMER_NS_EL2_IRQ,
             [GTIMER_SEC]  = ARCH_TIMER_S_EL1_IRQ,
             [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ,
+            [GTIMER_S_EL2_PHYS] = ARCH_TIMER_S_EL2_IRQ,
+            [GTIMER_S_EL2_VIRT] = ARCH_TIMER_S_EL2_VIRT_IRQ,
         };
 
         for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) {
-- 
2.43.0

Our LDRD implementation is wrong in two respects:

* if the address is 4-aligned and the load crosses a page boundary
   and the second load faults and the first load was to the
   base register (as in cases like "ldrd r2, r3, [r2]", then we
   must not update the base register before taking the fault
 * if the address is 8-aligned the access must be a 64-bit
   single-copy atomic access, not two 32-bit accesses

Rewrite the handling of the loads in LDRD to use a single
tcg_gen_qemu_ld_i64() and split the result into the destination
registers. This allows us to get the atomicity requirements
right, and also implicitly means that we won't update the
base register too early for the page-crossing case.

Note that because we no longer increment 'addr' by 4 in the course of
performing the LDRD we must change the adjustment value we pass to
op_addr_ri_post() and op_addr_rr_post(): it no longer needs to
subtract 4 to get the correct value to use if doing base register
writeback.

STRD has the same problem with not getting the atomicity right;
we will deal with that in the following commit.

Cc: qemu-stable@nongnu.org
Reported-by: Stu Grossman <stu.grossman@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250227142746.1698904-2-peter.maydell@linaro.org
---
 target/arm/tcg/translate.c | 70 +++++++++++++++++++++++++-------------
 1 file changed, 46 insertions(+), 24 deletions(-)

diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -XXX,XX +XXX,XX @@ static bool op_store_rr(DisasContext *s, arg_ldst_rr *a,
     return true;
 }
 
+static void do_ldrd_load(DisasContext *s, TCGv_i32 addr, int rt, int rt2)
+{
+    /*
+     * LDRD is required to be an atomic 64-bit access if the
+     * address is 8-aligned, two atomic 32-bit accesses if
+     * it's only 4-aligned, and to give an alignment fault
+     * if it's not 4-aligned. This is MO_ALIGN_4 | MO_ATOM_SUBALIGN.
+     * Rt is always the word from the lower address, and Rt2 the
+     * data from the higher address, regardless of endianness.
+     * So (like gen_load_exclusive) we avoid gen_aa32_ld_i64()
+     * so we don't get its SCTLR_B check, and instead do a 64-bit access
+     * using MO_BE if appropriate and then split the two halves.
+     *
+     * For M-profile, and for A-profile before LPAE, the 64-bit
+     * atomicity is not required. We could model that using
+     * the looser MO_ATOM_IFALIGN_PAIR, but providing a higher
+     * level of atomicity than required is harmless (we would not
+     * currently generate better code for IFALIGN_PAIR here).
+     *
+     * This also gives us the correct behaviour of not updating
+     * rt if the load of rt2 faults; this is required for cases
+     * like "ldrd r2, r3, [r2]" where rt is also the base register.
+     */
+    int mem_idx = get_mem_index(s);
+    MemOp opc = MO_64 | MO_ALIGN_4 | MO_ATOM_SUBALIGN | s->be_data;
+    TCGv taddr = gen_aa32_addr(s, addr, opc);
+    TCGv_i64 t64 = tcg_temp_new_i64();
+    TCGv_i32 tmp = tcg_temp_new_i32();
+    TCGv_i32 tmp2 = tcg_temp_new_i32();
+
+    tcg_gen_qemu_ld_i64(t64, taddr, mem_idx, opc);
+    if (s->be_data == MO_BE) {
+        tcg_gen_extr_i64_i32(tmp2, tmp, t64);
+    } else {
+        tcg_gen_extr_i64_i32(tmp, tmp2, t64);
+    }
+    store_reg(s, rt, tmp);
+    store_reg(s, rt2, tmp2);
+}
+
 static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a)
 {
-    int mem_idx = get_mem_index(s);
-    TCGv_i32 addr, tmp;
+    TCGv_i32 addr;
 
     if (!ENABLE_ARCH_5TE) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a)
     }
     addr = op_addr_rr_pre(s, a);
 
-    tmp = tcg_temp_new_i32();
-    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
-    store_reg(s, a->rt, tmp);
-
-    tcg_gen_addi_i32(addr, addr, 4);
-
-    tmp = tcg_temp_new_i32();
-    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
-    store_reg(s, a->rt + 1, tmp);
+    do_ldrd_load(s, addr, a->rt, a->rt + 1);
 
     /* LDRD w/ base writeback is undefined if the registers overlap.  */
-    op_addr_rr_post(s, a, addr, -4);
+    op_addr_rr_post(s, a, addr, 0);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool op_store_ri(DisasContext *s, arg_ldst_ri *a,
 
 static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
 {
-    int mem_idx = get_mem_index(s);
-    TCGv_i32 addr, tmp;
+    TCGv_i32 addr;
 
     addr = op_addr_ri_pre(s, a);
 
-    tmp = tcg_temp_new_i32();
-    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
-    store_reg(s, a->rt, tmp);
-
-    tcg_gen_addi_i32(addr, addr, 4);
-
-    tmp = tcg_temp_new_i32();
-    gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
-    store_reg(s, rt2, tmp);
+    do_ldrd_load(s, addr, a->rt, rt2);
 
     /* LDRD w/ base writeback is undefined if the registers overlap.  */
-    op_addr_ri_post(s, a, addr, -4);
+    op_addr_ri_post(s, a, addr, 0);
     return true;
 }
 
-- 
2.43.0

Our STRD implementation doesn't correctly implement the requirement:
 * if the address is 8-aligned the access must be a 64-bit
   single-copy atomic access, not two 32-bit accesses

Rewrite the handling of STRD to use a single tcg_gen_qemu_st_i64()
of a value produced by concatenating the two 32 bit source registers.
This allows us to get the atomicity right.

As with the LDRD change, now that we don't update 'addr' in the
course of performing the store we need to adjust the offset
we pass to op_addr_ri_post() and op_addr_rr_post().

Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250227142746.1698904-3-peter.maydell@linaro.org
---
 target/arm/tcg/translate.c | 59 +++++++++++++++++++++++++-------------
 1 file changed, 39 insertions(+), 20 deletions(-)

diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -XXX,XX +XXX,XX @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a)
     return true;
 }
 
+static void do_strd_store(DisasContext *s, TCGv_i32 addr, int rt, int rt2)
+{
+    /*
+     * STRD is required to be an atomic 64-bit access if the
+     * address is 8-aligned, two atomic 32-bit accesses if
+     * it's only 4-aligned, and to give an alignment fault
+     * if it's not 4-aligned.
+     * Rt is always the word from the lower address, and Rt2 the
+     * data from the higher address, regardless of endianness.
+     * So (like gen_store_exclusive) we avoid gen_aa32_ld_i64()
+     * so we don't get its SCTLR_B check, and instead do a 64-bit access
+     * using MO_BE if appropriate, using a value constructed
+     * by putting the two halves together in the right order.
+     *
+     * As with LDRD, the 64-bit atomicity is not required for
+     * M-profile, or for A-profile before LPAE, and we provide
+     * the higher guarantee always for simplicity.
+     */
+    int mem_idx = get_mem_index(s);
+    MemOp opc = MO_64 | MO_ALIGN_4 | MO_ATOM_SUBALIGN | s->be_data;
+    TCGv taddr = gen_aa32_addr(s, addr, opc);
+    TCGv_i32 t1 = load_reg(s, rt);
+    TCGv_i32 t2 = load_reg(s, rt2);
+    TCGv_i64 t64 = tcg_temp_new_i64();
+
+    if (s->be_data == MO_BE) {
+        tcg_gen_concat_i32_i64(t64, t2, t1);
+    } else {
+        tcg_gen_concat_i32_i64(t64, t1, t2);
+    }
+    tcg_gen_qemu_st_i64(t64, taddr, mem_idx, opc);
+}
+
 static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a)
 {
-    int mem_idx = get_mem_index(s);
-    TCGv_i32 addr, tmp;
+    TCGv_i32 addr;
 
     if (!ENABLE_ARCH_5TE) {
         return false;
@@ -XXX,XX +XXX,XX @@ static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a)
     }
     addr = op_addr_rr_pre(s, a);
 
-    tmp = load_reg(s, a->rt);
-    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
+    do_strd_store(s, addr, a->rt, a->rt + 1);
 
-    tcg_gen_addi_i32(addr, addr, 4);
-
-    tmp = load_reg(s, a->rt + 1);
-    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
-
-    op_addr_rr_post(s, a, addr, -4);
+    op_addr_rr_post(s, a, addr, 0);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_LDRD_ri_t32(DisasContext *s, arg_ldst_ri2 *a)
 
 static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
 {
-    int mem_idx = get_mem_index(s);
-    TCGv_i32 addr, tmp;
+    TCGv_i32 addr;
 
     addr = op_addr_ri_pre(s, a);
 
-    tmp = load_reg(s, a->rt);
-    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
+    do_strd_store(s, addr, a->rt, rt2);
 
-    tcg_gen_addi_i32(addr, addr, 4);
-
-    tmp = load_reg(s, rt2);
-    gen_aa32_st_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN);
-
-    op_addr_ri_post(s, a, addr, -4);
+    op_addr_ri_post(s, a, addr, 0);
     return true;
 }
 
-- 
2.43.0

All the callers of op_addr_rr_post() and op_addr_ri_post() now pass in
zero for the address_offset, so we can remove that argument.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20250227142746.1698904-4-peter.maydell@linaro.org
---
 target/arm/tcg/translate.c | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/tcg/translate.c
+++ b/target/arm/tcg/translate.c
@@ -XXX,XX +XXX,XX @@ static TCGv_i32 op_addr_rr_pre(DisasContext *s, arg_ldst_rr *a)
 }
 
 static void op_addr_rr_post(DisasContext *s, arg_ldst_rr *a,
-                            TCGv_i32 addr, int address_offset)
+                            TCGv_i32 addr)
 {
     if (!a->p) {
         TCGv_i32 ofs = load_reg(s, a->rm);
@@ -XXX,XX +XXX,XX @@ static void op_addr_rr_post(DisasContext *s, arg_ldst_rr *a,
     } else if (!a->w) {
         return;
     }
-    tcg_gen_addi_i32(addr, addr, address_offset);
     store_reg(s, a->rn, addr);
 }
 
@@ -XXX,XX +XXX,XX @@ static bool op_load_rr(DisasContext *s, arg_ldst_rr *a,
      * Perform base writeback before the loaded value to
      * ensure correct behavior with overlapping index registers.
      */
-    op_addr_rr_post(s, a, addr, 0);
+    op_addr_rr_post(s, a, addr);
     store_reg_from_load(s, a->rt, tmp);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool op_store_rr(DisasContext *s, arg_ldst_rr *a,
     gen_aa32_st_i32(s, tmp, addr, mem_idx, mop);
     disas_set_da_iss(s, mop, issinfo);
 
-    op_addr_rr_post(s, a, addr, 0);
+    op_addr_rr_post(s, a, addr);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_LDRD_rr(DisasContext *s, arg_ldst_rr *a)
     do_ldrd_load(s, addr, a->rt, a->rt + 1);
 
     /* LDRD w/ base writeback is undefined if the registers overlap.  */
-    op_addr_rr_post(s, a, addr, 0);
+    op_addr_rr_post(s, a, addr);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool trans_STRD_rr(DisasContext *s, arg_ldst_rr *a)
 
     do_strd_store(s, addr, a->rt, a->rt + 1);
 
-    op_addr_rr_post(s, a, addr, 0);
+    op_addr_rr_post(s, a, addr);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static TCGv_i32 op_addr_ri_pre(DisasContext *s, arg_ldst_ri *a)
 }
 
 static void op_addr_ri_post(DisasContext *s, arg_ldst_ri *a,
-                            TCGv_i32 addr, int address_offset)
+                            TCGv_i32 addr)
 {
+    int address_offset = 0;
     if (!a->p) {
         if (a->u) {
-            address_offset += a->imm;
+            address_offset = a->imm;
         } else {
-            address_offset -= a->imm;
+            address_offset = -a->imm;
         }
     } else if (!a->w) {
         return;
@@ -XXX,XX +XXX,XX @@ static bool op_load_ri(DisasContext *s, arg_ldst_ri *a,
      * Perform base writeback before the loaded value to
      * ensure correct behavior with overlapping index registers.
      */
-    op_addr_ri_post(s, a, addr, 0);
+    op_addr_ri_post(s, a, addr);
     store_reg_from_load(s, a->rt, tmp);
     return true;
 }
@@ -XXX,XX +XXX,XX @@ static bool op_store_ri(DisasContext *s, arg_ldst_ri *a,
     gen_aa32_st_i32(s, tmp, addr, mem_idx, mop);
     disas_set_da_iss(s, mop, issinfo);
 
-    op_addr_ri_post(s, a, addr, 0);
+    op_addr_ri_post(s, a, addr);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool op_ldrd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
     do_ldrd_load(s, addr, a->rt, rt2);
 
     /* LDRD w/ base writeback is undefined if the registers overlap.  */
-    op_addr_ri_post(s, a, addr, 0);
+    op_addr_ri_post(s, a, addr);
     return true;
 }
 
@@ -XXX,XX +XXX,XX @@ static bool op_strd_ri(DisasContext *s, arg_ldst_ri *a, int rt2)
 
     do_strd_store(s, addr, a->rt, rt2);
 
-    op_addr_ri_post(s, a, addr, 0);
+    op_addr_ri_post(s, a, addr);
     return true;
 }
 
-- 
2.43.0

In debug_helper.c we provide a few dummy versions of
debug registers:
 * DBGVCR (AArch32 only): enable bits for vector-catch
   debug events
 * MDCCINT_EL1: interrupt enable bits for the DCC
   debug communications channel
 * DBGVCR32_EL2: the AArch64 accessor for the state in
   DBGVCR

We implemented these only to stop Linux crashing on startup,
but we chose to implement them as ARM_CP_NOP. This worked
for Linux where it only cares about trying to write to these
registers, but is very confusing behaviour for anything that
wants to read the registers (perhaps for context state switches),
because the destination register will be left with whatever
random value it happened to have before the read.

Model these registers instead as RAZ.

Fixes: 5e8b12ffbb8c68 ("target-arm: Implement minimal DBGVCR, OSDLR_EL1, MDCCSR_EL0")
Fixes: 5dbdc4342f479d ("target-arm: Implement dummy MDCCINT_EL1")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2708
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250228162424.1917269-1-peter.maydell@linaro.org
---
 target/arm/debug_helper.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/debug_helper.c
+++ b/target/arm/debug_helper.c
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
     { .name = "DBGVCR",
       .cp = 14, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_tda,
-      .type = ARM_CP_NOP },
+      .type = ARM_CP_CONST, .resetvalue = 0 },
     /*
      * Dummy MDCCINT_EL1, since we don't implement the Debug Communications
      * Channel but Linux may try to access this register. The 32-bit
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_cp_reginfo[] = {
     { .name = "MDCCINT_EL1", .state = ARM_CP_STATE_BOTH,
       .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
       .access = PL1_RW, .accessfn = access_tdcc,
-      .type = ARM_CP_NOP },
+      .type = ARM_CP_CONST, .resetvalue = 0 },
     /*
      * Dummy DBGCLAIM registers.
      * "The architecture does not define any functionality for the CLAIM tag bits.",
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo debug_aa32_el1_reginfo[] = {
     { .name = "DBGVCR32_EL2", .state = ARM_CP_STATE_AA64,
       .opc0 = 2, .opc1 = 4, .crn = 0, .crm = 7, .opc2 = 0,
       .access = PL2_RW, .accessfn = access_dbgvcr32,
-      .type = ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP },
+      .type = ARM_CP_CONST | ARM_CP_EL3_NO_EL2_KEEP,
+      .resetvalue = 0 },
 };
 
 static const ARMCPRegInfo debug_lpae_cp_reginfo[] = {
-- 
2.43.0

Currently we call icount_start_warp_timer() from timerlist_rearm().
This produces incorrect behaviour, because timerlist_rearm() is
called, for instance, when a timer callback modifies its timer.  We
cannot decide here to warp the timer forwards to the next timer
deadline merely because all_cpu_threads_idle() is true, because the
timer callback we were called from (or some other callback later in
the list of callbacks being invoked) may be about to raise a CPU
interrupt and move a CPU from idle to ready.

The only valid place to choose to warp the timer forward is from the
main loop, when we know we have no outstanding IO or timer callbacks
that might be about to wake up a CPU.

For Arm guests, this bug was mostly latent until the refactoring
commit f6fc36deef6abc ("target/arm/helper: Implement
CNTHCTL_EL2.CNT[VP]MASK"), which exposed it because it refactored a
timer callback so that it happened to call timer_mod() first and
raise the interrupt second, when it had previously raised the
interrupt first and called timer_mod() afterwards.

This call seems to have originally derived from the
pre-record-and-replay icount code, which (as of e.g.  commit
db1a49726c3c in 2010) in this location did a call to
qemu_notify_event(), necessary to get the icount code in the vCPU
round-robin thread to stop and recalculate the icount deadline when a
timer was reprogrammed from the IO thread.  In current QEMU,
everything is done on the vCPU thread when we are in icount mode, so
there's no need to try to notify another thread here.

I suspect that the other reason why this call was doing icount timer
warping is that it pre-dates commit efab87cf79077a from 2015, which
added a call to icount_start_warp_timer() to main_loop_wait().  Once
the call in timerlist_rearm() has been removed, if the timer
callbacks don't cause any CPU to be woken up then we will end up
calling icount_start_warp_timer() from main_loop_wait() when the rr
main loop code calls rr_wait_io_event().

Remove the incorrect call from timerlist_rearm().

Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2703
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20250210135804.3526943-1-peter.maydell@linaro.org
---
 util/qemu-timer.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/util/qemu-timer.c b/util/qemu-timer.c
index XXXXXXX..XXXXXXX 100644
--- a/util/qemu-timer.c
+++ b/util/qemu-timer.c
@@ -XXX,XX +XXX,XX @@ static bool timer_mod_ns_locked(QEMUTimerList *timer_list,
 
 static void timerlist_rearm(QEMUTimerList *timer_list)
 {
-    /* Interrupt execution to force deadline recalculation.  */
-    if (icount_enabled() && timer_list->clock->type == QEMU_CLOCK_VIRTUAL) {
-        icount_start_warp_timer();
-    }
     timerlist_notify(timer_list);
 }
 
-- 
2.43.0

Expand the example in the comment documenting MO_ATOM_SUBALIGN,
to be clearer about the atomicity guarantees it represents.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250228103222.1838913-1-peter.maydell@linaro.org
---
 include/exec/memop.h | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/include/exec/memop.h b/include/exec/memop.h
index XXXXXXX..XXXXXXX 100644
--- a/include/exec/memop.h
+++ b/include/exec/memop.h
@@ -XXX,XX +XXX,XX @@ typedef enum MemOp {
      *    Depending on alignment, one or both will be single-copy atomic.
      *    This is the atomicity e.g. of Arm FEAT_LSE2 LDP.
      * MO_ATOM_SUBALIGN: the operation is single-copy atomic by parts
-     *    by the alignment.  E.g. if the address is 0 mod 4, then each
-     *    4-byte subobject is single-copy atomic.
+     *    by the alignment.  E.g. if an 8-byte value is accessed at an
+     *    address which is 0 mod 8, then the whole 8-byte access is
+     *    single-copy atomic; otherwise, if it is accessed at 0 mod 4
+     *    then each 4-byte subobject is single-copy atomic; otherwise
+     *    if it is accessed at 0 mod 2 then the four 2-byte subobjects
+     *    are single-copy atomic.
      *    This is the atomicity e.g. of IBM Power.
      * MO_ATOM_NONE: the operation has no atomicity requirements.
      *
-- 
2.43.0

From: JianChunfu <jansef.jian@hj-micro.com>

Use a similar terminology smmu_hash_remove_by_sid_range() as the one
being used for other hash table matching functions since
smmuv3_invalidate_ste() name is not self explanatory, and introduce a
helper that invokes the g_hash_table_foreach_remove.

No functional change intended.

Signed-off-by: JianChunfu <jansef.jian@hj-micro.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20250228031438.3916-1-jansef.jian@hj-micro.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/smmu-internal.h       |  5 -----
 include/hw/arm/smmu-common.h |  6 ++++++
 hw/arm/smmu-common.c         | 21 +++++++++++++++++++++
 hw/arm/smmuv3.c              | 19 ++-----------------
 hw/arm/trace-events          |  3 ++-
 5 files changed, 31 insertions(+), 23 deletions(-)

diff --git a/hw/arm/smmu-internal.h b/hw/arm/smmu-internal.h
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmu-internal.h
+++ b/hw/arm/smmu-internal.h
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUIOTLBPageInvInfo {
     uint64_t mask;
 } SMMUIOTLBPageInvInfo;
 
-typedef struct SMMUSIDRange {
-    uint32_t start;
-    uint32_t end;
-} SMMUSIDRange;
-
 #endif
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/smmu-common.h
+++ b/include/hw/arm/smmu-common.h
@@ -XXX,XX +XXX,XX @@ typedef struct SMMUIOTLBKey {
     uint8_t level;
 } SMMUIOTLBKey;
 
+typedef struct SMMUSIDRange {
+    uint32_t start;
+    uint32_t end;
+} SMMUSIDRange;
+
 struct SMMUState {
     /* <private> */
     SysBusDevice  dev;
@@ -XXX,XX +XXX,XX @@ void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova,
                          uint8_t tg, uint64_t num_pages, uint8_t ttl);
 void smmu_iotlb_inv_ipa(SMMUState *s, int vmid, dma_addr_t ipa, uint8_t tg,
                         uint64_t num_pages, uint8_t ttl);
+void smmu_configs_inv_sid_range(SMMUState *s, SMMUSIDRange sid_range);
 /* Unmap the range of all the notifiers registered to any IOMMU mr */
 void smmu_inv_notifiers_all(SMMUState *s);
 
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -XXX,XX +XXX,XX @@ static gboolean smmu_hash_remove_by_vmid_ipa(gpointer key, gpointer value,
            ((entry->iova & ~info->mask) == info->iova);
 }
 
+static gboolean
+smmu_hash_remove_by_sid_range(gpointer key, gpointer value, gpointer user_data)
+{
+    SMMUDevice *sdev = (SMMUDevice *)key;
+    uint32_t sid = smmu_get_sid(sdev);
+    SMMUSIDRange *sid_range = (SMMUSIDRange *)user_data;
+
+    if (sid < sid_range->start || sid > sid_range->end) {
+        return false;
+    }
+    trace_smmu_config_cache_inv(sid);
+    return true;
+}
+
+void smmu_configs_inv_sid_range(SMMUState *s, SMMUSIDRange sid_range)
+{
+    trace_smmu_configs_inv_sid_range(sid_range.start, sid_range.end);
+    g_hash_table_foreach_remove(s->configs, smmu_hash_remove_by_sid_range,
+                                &sid_range);
+}
+
 void smmu_iotlb_inv_iova(SMMUState *s, int asid, int vmid, dma_addr_t iova,
                          uint8_t tg, uint64_t num_pages, uint8_t ttl)
 {
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -XXX,XX +XXX,XX @@ static void smmuv3_flush_config(SMMUDevice *sdev)
     SMMUv3State *s = sdev->smmu;
     SMMUState *bc = &s->smmu_state;
 
-    trace_smmuv3_config_cache_inv(smmu_get_sid(sdev));
+    trace_smmu_config_cache_inv(smmu_get_sid(sdev));
     g_hash_table_remove(bc->configs, sdev);
 }
 
@@ -XXX,XX +XXX,XX @@ static void smmuv3_range_inval(SMMUState *s, Cmd *cmd, SMMUStage stage)
     }
 }
 
-static gboolean
-smmuv3_invalidate_ste(gpointer key, gpointer value, gpointer user_data)
-{
-    SMMUDevice *sdev = (SMMUDevice *)key;
-    uint32_t sid = smmu_get_sid(sdev);
-    SMMUSIDRange *sid_range = (SMMUSIDRange *)user_data;
-
-    if (sid < sid_range->start || sid > sid_range->end) {
-        return false;
-    }
-    trace_smmuv3_config_cache_inv(sid);
-    return true;
-}
-
 static int smmuv3_cmdq_consume(SMMUv3State *s)
 {
     SMMUState *bs = ARM_SMMU(s);
@@ -XXX,XX +XXX,XX @@ static int smmuv3_cmdq_consume(SMMUv3State *s)
             sid_range.end = sid_range.start + mask;
 
             trace_smmuv3_cmdq_cfgi_ste_range(sid_range.start, sid_range.end);
-            g_hash_table_foreach_remove(bs->configs, smmuv3_invalidate_ste,
-                                        &sid_range);
+            smmu_configs_inv_sid_range(bs, sid_range);
             break;
         }
         case SMMU_CMD_CFGI_CD:
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/trace-events
+++ b/hw/arm/trace-events
@@ -XXX,XX +XXX,XX @@ smmu_iotlb_inv_asid_vmid(int asid, int vmid) "IOTLB invalidate asid=%d vmid=%d"
 smmu_iotlb_inv_vmid(int vmid) "IOTLB invalidate vmid=%d"
 smmu_iotlb_inv_vmid_s1(int vmid) "IOTLB invalidate vmid=%d"
 smmu_iotlb_inv_iova(int asid, uint64_t addr) "IOTLB invalidate asid=%d addr=0x%"PRIx64
+smmu_configs_inv_sid_range(uint32_t start, uint32_t end) "Config cache INV SID range from 0x%x to 0x%x"
+smmu_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x"
 smmu_inv_notifiers_mr(const char *name) "iommu mr=%s"
 smmu_iotlb_lookup_hit(int asid, int vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache HIT asid=%d vmid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
 smmu_iotlb_lookup_miss(int asid, int vmid, uint64_t addr, uint32_t hit, uint32_t miss, uint32_t p) "IOTLB cache MISS asid=%d vmid=%d addr=0x%"PRIx64" hit=%d miss=%d hit rate=%d"
@@ -XXX,XX +XXX,XX @@ smmuv3_cmdq_tlbi_nh(int vmid) "vmid=%d"
 smmuv3_cmdq_tlbi_nsnh(void) ""
 smmuv3_cmdq_tlbi_nh_asid(int asid) "asid=%d"
 smmuv3_cmdq_tlbi_s12_vmid(int vmid) "vmid=%d"
-smmuv3_config_cache_inv(uint32_t sid) "Config cache INV for sid=0x%x"
 smmuv3_notify_flag_add(const char *iommu) "ADD SMMUNotifier node for iommu mr=%s"
 smmuv3_notify_flag_del(const char *iommu) "DEL SMMUNotifier node for iommu mr=%s"
 smmuv3_inv_notifiers_iova(const char *name, int asid, int vmid, uint64_t iova, uint8_t tg, uint64_t num_pages, int stage) "iommu mr=%s asid=%d vmid=%d iova=0x%"PRIx64" tg=%d num_pages=0x%"PRIx64" stage=%d"
-- 
2.43.0

From: Keith Packard <keithp@keithp.com>

The documentation says the vector is at 0xffffff80, instead of the
previous value of 0xffffffc0. That value must have been a bug because
the standard vector values (20, 21, 23, 25, 30) were all
past the end of the array.

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/rx/helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/rx/helper.c b/target/rx/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/rx/helper.c
+++ b/target/rx/helper.c
@@ -XXX,XX +XXX,XX @@ void rx_cpu_do_interrupt(CPUState *cs)
         cpu_stl_data(env, env->isp, env->pc);
 
         if (vec < 0x100) {
-            env->pc = cpu_ldl_data(env, 0xffffffc0 + vec * 4);
+            env->pc = cpu_ldl_data(env, 0xffffff80 + vec * 4);
         } else {
             env->pc = cpu_ldl_data(env, env->intb + (vec & 0xff) * 4);
         }
-- 
2.43.0

From: Keith Packard <keithp@keithp.com>

Functions which modify TCG globals must not be marked TCG_CALL_NO_WG,
as that tells the optimizer that TCG global values already loaded in
machine registers are still valid, and so any changes which these
helpers make to the CPU state may be ignored.

The target/rx code chooses to put (among other things) all the PSW
bits and also ACC into globals, so the NO_WG flag on various
functions that touch the PSW or ACC is incorrect and must be removed.
This includes all the floating point helper functions, because
update_fpsw() will update PSW Z and S.

Signed-off-by: Keith Packard <keithp@keithp.com>
[PMM: Clarified commit message]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/rx/helper.h | 34 +++++++++++++++++-----------------
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/target/rx/helper.h b/target/rx/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/rx/helper.h
+++ b/target/rx/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(raise_privilege_violation, noreturn, env)
 DEF_HELPER_1(wait, noreturn, env)
 DEF_HELPER_2(rxint, noreturn, env, i32)
 DEF_HELPER_1(rxbrk, noreturn, env)
-DEF_HELPER_FLAGS_3(fadd, TCG_CALL_NO_WG, f32, env, f32, f32)
-DEF_HELPER_FLAGS_3(fsub, TCG_CALL_NO_WG, f32, env, f32, f32)
-DEF_HELPER_FLAGS_3(fmul, TCG_CALL_NO_WG, f32, env, f32, f32)
-DEF_HELPER_FLAGS_3(fdiv, TCG_CALL_NO_WG, f32, env, f32, f32)
-DEF_HELPER_FLAGS_3(fcmp, TCG_CALL_NO_WG, void, env, f32, f32)
-DEF_HELPER_FLAGS_2(ftoi, TCG_CALL_NO_WG, i32, env, f32)
-DEF_HELPER_FLAGS_2(round, TCG_CALL_NO_WG, i32, env, f32)
-DEF_HELPER_FLAGS_2(itof, TCG_CALL_NO_WG, f32, env, i32)
+DEF_HELPER_3(fadd, f32, env, f32, f32)
+DEF_HELPER_3(fsub, f32, env, f32, f32)
+DEF_HELPER_3(fmul, f32, env, f32, f32)
+DEF_HELPER_3(fdiv, f32, env, f32, f32)
+DEF_HELPER_3(fcmp, void, env, f32, f32)
+DEF_HELPER_2(ftoi, i32, env, f32)
+DEF_HELPER_2(round, i32, env, f32)
+DEF_HELPER_2(itof, f32, env, i32)
 DEF_HELPER_2(set_fpsw, void, env, i32)
-DEF_HELPER_FLAGS_2(racw, TCG_CALL_NO_WG, void, env, i32)
-DEF_HELPER_FLAGS_2(set_psw_rte, TCG_CALL_NO_WG, void, env, i32)
-DEF_HELPER_FLAGS_2(set_psw, TCG_CALL_NO_WG, void, env, i32)
+DEF_HELPER_2(racw, void, env, i32)
+DEF_HELPER_2(set_psw_rte, void, env, i32)
+DEF_HELPER_2(set_psw, void, env, i32)
 DEF_HELPER_1(pack_psw, i32, env)
-DEF_HELPER_FLAGS_3(div, TCG_CALL_NO_WG, i32, env, i32, i32)
-DEF_HELPER_FLAGS_3(divu, TCG_CALL_NO_WG, i32, env, i32, i32)
-DEF_HELPER_FLAGS_1(scmpu, TCG_CALL_NO_WG, void, env)
+DEF_HELPER_3(div, i32, env, i32, i32)
+DEF_HELPER_3(divu, i32, env, i32, i32)
+DEF_HELPER_1(scmpu, void, env)
 DEF_HELPER_1(smovu, void, env)
 DEF_HELPER_1(smovf, void, env)
 DEF_HELPER_1(smovb, void, env)
 DEF_HELPER_2(sstr, void, env, i32)
-DEF_HELPER_FLAGS_2(swhile, TCG_CALL_NO_WG, void, env, i32)
-DEF_HELPER_FLAGS_2(suntil, TCG_CALL_NO_WG, void, env, i32)
-DEF_HELPER_FLAGS_2(rmpa, TCG_CALL_NO_WG, void, env, i32)
+DEF_HELPER_2(swhile, void, env, i32)
+DEF_HELPER_2(suntil, void, env, i32)
+DEF_HELPER_2(rmpa, void, env, i32)
 DEF_HELPER_1(satr, void, env)
-- 
2.43.0