[Qemu-devel] [PULL 00/12] target-arm queue
[PULL 00/28] target-arm queue
1
Not very much here, but several people have fallen over
1
Hi; this is the latest target-arm queue; most of this is a refactoring
2
the vector operation segfault bug, so let's get the fix
2
patchset from RTH for the arm page-table-walk emulation.
3
into master.
4
3
5
thanks
4
thanks
6
-- PMM
5
-- PMM
7
6
8
The following changes since commit d418238dca7b4e0b124135827ead3076233052b1:
7
The following changes since commit f1d33f55c47dfdaf8daacd618588ad3ae4c452d1:
9
8
10
Merge remote-tracking branch 'remotes/rth/tags/pull-rng-20190522' into staging (2019-05-23 12:57:17 +0100)
9
Merge tag 'pull-testing-gdbstub-plugins-gitdm-061022-3' of https://github.com/stsquad/qemu into staging (2022-10-06 07:11:56 -0400)
11
10
12
are available in the Git repository at:
11
are available in the Git repository at:
13
12
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190523
13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20221010
15
14
16
for you to fetch changes up to 98e4f4fdb8ea05d840f51f47125924c2bb9df2df:
15
for you to fetch changes up to 915f62844cf62e428c7c178149b5ff1cbe129b07:
17
16
18
hw/arm/exynos4210: QOM'ify the Exynos4210 SoC (2019-05-23 14:47:44 +0100)
17
docs/system/arm/emulation.rst: Report FEAT_GTG support (2022-10-10 14:52:25 +0100)
19
18
20
----------------------------------------------------------------
19
----------------------------------------------------------------
21
target-arm queue:
20
target-arm queue:
22
* exynos4210: QOM'ify the Exynos4210 SoC
21
* Retry KVM_CREATE_VM call if it fails EINTR
23
* exynos4210: Add DMA support for the Exynos4210
22
* allow setting SCR_EL3.EnTP2 when FEAT_SME is implemented
24
* arm_gicv3: Fix writes to ICC_CTLR_EL3
23
* docs/nuvoton: Update URL for images
25
* arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
24
* refactoring of page table walk code
26
* target/arm: Fix vector operation segfault
25
* hw/arm/boot: set CPTR_EL3.ESM and SCR_EL3.EnTP2 when booting Linux with EL3
27
* target/arm: Minor improvements to BFXIL, EXTR
26
* Don't allow guest to use unimplemented granule sizes
27
* Report FEAT_GTG support
28
28
29
----------------------------------------------------------------
29
----------------------------------------------------------------
30
Alistair Francis (1):
30
Jerome Forissier (2):
31
target/arm: Fix vector operation segfault
31
target/arm: allow setting SCR_EL3.EnTP2 when FEAT_SME is implemented
32
hw/arm/boot: set CPTR_EL3.ESM and SCR_EL3.EnTP2 when booting Linux with EL3
32
33
33
Guenter Roeck (1):
34
Joel Stanley (1):
34
hw/arm/exynos4210: Add DMA support for the Exynos4210
35
docs/nuvoton: Update URL for images
35
36
36
Peter Maydell (5):
37
Peter Maydell (4):
37
arm: Move system_clock_scale to armv7m_systick.h
38
target/arm/kvm: Retry KVM_CREATE_VM call if it fails EINTR
38
arm: Remove unnecessary includes of hw/arm/arm.h
39
target/arm: Don't allow guest to use unimplemented granule sizes
39
arm: Rename hw/arm/arm.h to hw/arm/boot.h
40
target/arm: Use ARMGranuleSize in ARMVAParameters
40
hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
41
docs/system/arm/emulation.rst: Report FEAT_GTG support
41
hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3
42
42
43
Philippe Mathieu-Daudé (3):
43
Richard Henderson (21):
44
hw/arm/exynos4: Remove unuseful debug code
44
target/arm: Split s2walk_secure from ipa_secure in get_phys_addr
45
hw/arm/exynos4: Use the IEC binary prefix definitions
45
target/arm: Make the final stage1+2 write to secure be unconditional
46
hw/arm/exynos4210: QOM'ify the Exynos4210 SoC
46
target/arm: Add is_secure parameter to get_phys_addr_lpae
47
target/arm: Fix S2 disabled check in S1_ptw_translate
48
target/arm: Add is_secure parameter to regime_translation_disabled
49
target/arm: Split out get_phys_addr_with_secure
50
target/arm: Add is_secure parameter to v7m_read_half_insn
51
target/arm: Add TBFLAG_M32.SECURE
52
target/arm: Merge regime_is_secure into get_phys_addr
53
target/arm: Add is_secure parameter to do_ats_write
54
target/arm: Fold secure and non-secure a-profile mmu indexes
55
target/arm: Reorg regime_translation_disabled
56
target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M
57
target/arm: Introduce arm_hcr_el2_eff_secstate
58
target/arm: Hoist read of *is_secure in S1_ptw_translate
59
target/arm: Remove env argument from combined_attrs_fwb
60
target/arm: Pass HCR to attribute subroutines.
61
target/arm: Fix ATS12NSO* from S PL1
62
target/arm: Split out get_phys_addr_disabled
63
target/arm: Fix cacheattr in get_phys_addr_disabled
64
target/arm: Use tlb_set_page_full
47
65
48
Richard Henderson (2):
66
docs/system/arm/emulation.rst | 1 +
49
target/arm: Use extract2 for EXTR
67
docs/system/arm/nuvoton.rst | 4 +-
50
target/arm: Simplify BFXIL expansion
68
target/arm/cpu-param.h | 2 +-
51
69
target/arm/cpu.h | 181 ++++++++------
52
include/hw/arm/allwinner-a10.h | 2 +-
70
target/arm/internals.h | 150 ++++++-----
53
include/hw/arm/aspeed_soc.h | 1 -
71
hw/arm/boot.c | 4 +
54
include/hw/arm/bcm2836.h | 1 -
72
target/arm/helper.c | 332 ++++++++++++++----------
55
include/hw/arm/{arm.h => boot.h} | 12 +++------
73
target/arm/kvm.c | 4 +-
56
include/hw/arm/exynos4210.h | 9 +++++--
74
target/arm/m_helper.c | 29 ++-
57
include/hw/arm/fsl-imx25.h | 2 +-
75
target/arm/ptw.c | 570 ++++++++++++++++++++++--------------------
58
include/hw/arm/fsl-imx31.h | 2 +-
76
target/arm/tlb_helper.c | 9 +-
59
include/hw/arm/fsl-imx6.h | 2 +-
77
target/arm/translate-a64.c | 8 -
60
include/hw/arm/fsl-imx6ul.h | 2 +-
78
target/arm/translate.c | 9 +-
61
include/hw/arm/fsl-imx7.h | 2 +-
79
13 files changed, 717 insertions(+), 586 deletions(-)
62
include/hw/arm/virt.h | 2 +-
63
include/hw/arm/xlnx-versal.h | 2 +-
64
include/hw/arm/xlnx-zynqmp.h | 2 +-
65
include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++
66
hw/arm/armsse.c | 2 +-
67
hw/arm/armv7m.c | 2 +-
68
hw/arm/aspeed.c | 2 +-
69
hw/arm/boot.c | 2 +-
70
hw/arm/collie.c | 2 +-
71
hw/arm/exynos4210.c | 54 ++++++++++++++++++++++++++++++++++++---
72
hw/arm/exynos4_boards.c | 40 ++++++++---------------------
73
hw/arm/highbank.c | 2 +-
74
hw/arm/integratorcp.c | 2 +-
75
hw/arm/mainstone.c | 2 +-
76
hw/arm/microbit.c | 2 +-
77
hw/arm/mps2-tz.c | 2 +-
78
hw/arm/mps2.c | 2 +-
79
hw/arm/msf2-soc.c | 1 -
80
hw/arm/msf2-som.c | 2 +-
81
hw/arm/musca.c | 2 +-
82
hw/arm/musicpal.c | 2 +-
83
hw/arm/netduino2.c | 2 +-
84
hw/arm/nrf51_soc.c | 2 +-
85
hw/arm/nseries.c | 2 +-
86
hw/arm/omap1.c | 2 +-
87
hw/arm/omap2.c | 2 +-
88
hw/arm/omap_sx1.c | 2 +-
89
hw/arm/palm.c | 2 +-
90
hw/arm/raspi.c | 2 +-
91
hw/arm/realview.c | 2 +-
92
hw/arm/spitz.c | 2 +-
93
hw/arm/stellaris.c | 2 +-
94
hw/arm/stm32f205_soc.c | 2 +-
95
hw/arm/strongarm.c | 2 +-
96
hw/arm/tosa.c | 2 +-
97
hw/arm/versatilepb.c | 2 +-
98
hw/arm/vexpress.c | 2 +-
99
hw/arm/virt.c | 2 +-
100
hw/arm/xilinx_zynq.c | 2 +-
101
hw/arm/xlnx-versal.c | 2 +-
102
hw/arm/z2.c | 2 +-
103
hw/intc/arm_gicv3_cpuif.c | 6 ++---
104
hw/intc/armv7m_nvic.c | 1 -
105
target/arm/arm-semi.c | 1 -
106
target/arm/cpu.c | 1 -
107
target/arm/cpu64.c | 1 -
108
target/arm/kvm.c | 1 -
109
target/arm/kvm32.c | 1 -
110
target/arm/kvm64.c | 1 -
111
target/arm/translate-a64.c | 44 ++++++++++++++++---------------
112
target/arm/translate.c | 4 +--
113
61 files changed, 164 insertions(+), 123 deletions(-)
114
rename include/hw/arm/{arm.h => boot.h} (96%)
115
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/12] arm: Remove unnecessary includes of hw/arm/arm.h
[PULL 01/28] target/arm/kvm: Retry KVM_CREATE_VM call if it fails EINTR
1
The hw/arm/arm.h header now only includes declarations relating
1
Occasionally the KVM_CREATE_VM ioctl can return EINTR, even though
2
to boot.c code, so it is only needed by Arm board or SoC code.
2
there is no pending signal to be taken. In commit 94ccff13382055
3
Remove some unnecessary inclusions of it from target/arm files
3
we added a retry-on-EINTR loop to the KVM_CREATE_VM call in the
4
and from hw/intc/armv7m_nvic.c.
4
generic KVM code. Adopt the same approach for the use of the
5
ioctl in the Arm-specific KVM code (where we use it to create a
6
scratch VM for probing for various things).
5
7
8
For more information, see the mailing list thread:
9
https://lore.kernel.org/qemu-devel/8735e0s1zw.wl-maz@kernel.org/
10
11
Reported-by: Vitaly Chikunov <vt@altlinux.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Reviewed-by: Vitaly Chikunov <vt@altlinux.org>
8
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Reviewed-by: Eric Auger <eric.auger@redhat.com>
9
Message-id: 20190516163857.6430-3-peter.maydell@linaro.org
15
Acked-by: Marc Zyngier <maz@kernel.org>
16
Message-id: 20220930113824.1933293-1-peter.maydell@linaro.org
10
---
17
---
11
hw/intc/armv7m_nvic.c | 1 -
18
target/arm/kvm.c | 4 +++-
12
target/arm/arm-semi.c | 1 -
19
1 file changed, 3 insertions(+), 1 deletion(-)
13
target/arm/cpu.c | 1 -
14
target/arm/cpu64.c | 1 -
15
target/arm/kvm.c | 1 -
16
target/arm/kvm32.c | 1 -
17
target/arm/kvm64.c | 1 -
18
7 files changed, 7 deletions(-)
19
20
20
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/intc/armv7m_nvic.c
23
+++ b/hw/intc/armv7m_nvic.c
24
@@ -XXX,XX +XXX,XX @@
25
#include "cpu.h"
26
#include "hw/sysbus.h"
27
#include "qemu/timer.h"
28
-#include "hw/arm/arm.h"
29
#include "hw/intc/armv7m_nvic.h"
30
#include "target/arm/cpu.h"
31
#include "exec/exec-all.h"
32
diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/arm-semi.c
35
+++ b/target/arm/arm-semi.c
36
@@ -XXX,XX +XXX,XX @@
37
#else
38
#include "qemu-common.h"
39
#include "exec/gdbstub.h"
40
-#include "hw/arm/arm.h"
41
#include "qemu/cutils.h"
42
#endif
43
44
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/cpu.c
47
+++ b/target/arm/cpu.c
48
@@ -XXX,XX +XXX,XX @@
49
#if !defined(CONFIG_USER_ONLY)
50
#include "hw/loader.h"
51
#endif
52
-#include "hw/arm/arm.h"
53
#include "sysemu/sysemu.h"
54
#include "sysemu/hw_accel.h"
55
#include "kvm_arm.h"
56
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/target/arm/cpu64.c
59
+++ b/target/arm/cpu64.c
60
@@ -XXX,XX +XXX,XX @@
61
#if !defined(CONFIG_USER_ONLY)
62
#include "hw/loader.h"
63
#endif
64
-#include "hw/arm/arm.h"
65
#include "sysemu/sysemu.h"
66
#include "sysemu/kvm.h"
67
#include "kvm_arm.h"
68
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
21
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
69
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
70
--- a/target/arm/kvm.c
23
--- a/target/arm/kvm.c
71
+++ b/target/arm/kvm.c
24
+++ b/target/arm/kvm.c
72
@@ -XXX,XX +XXX,XX @@
25
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_create_scratch_host_vcpu(const uint32_t *cpus_to_try,
73
#include "cpu.h"
26
if (max_vm_pa_size < 0) {
74
#include "trace.h"
27
max_vm_pa_size = 0;
75
#include "internals.h"
28
}
76
-#include "hw/arm/arm.h"
29
- vmfd = ioctl(kvmfd, KVM_CREATE_VM, max_vm_pa_size);
77
#include "hw/pci/pci.h"
30
+ do {
78
#include "exec/memattrs.h"
31
+ vmfd = ioctl(kvmfd, KVM_CREATE_VM, max_vm_pa_size);
79
#include "exec/address-spaces.h"
32
+ } while (vmfd == -1 && errno == EINTR);
80
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
33
if (vmfd < 0) {
81
index XXXXXXX..XXXXXXX 100644
34
goto err;
82
--- a/target/arm/kvm32.c
35
}
83
+++ b/target/arm/kvm32.c
84
@@ -XXX,XX +XXX,XX @@
85
#include "sysemu/kvm.h"
86
#include "kvm_arm.h"
87
#include "internals.h"
88
-#include "hw/arm/arm.h"
89
#include "qemu/log.h"
90
91
static inline void set_feature(uint64_t *features, int feature)
92
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
93
index XXXXXXX..XXXXXXX 100644
94
--- a/target/arm/kvm64.c
95
+++ b/target/arm/kvm64.c
96
@@ -XXX,XX +XXX,XX @@
97
#include "sysemu/kvm.h"
98
#include "kvm_arm.h"
99
#include "internals.h"
100
-#include "hw/arm/arm.h"
101
102
static bool have_guest_debug;
103
104
--
36
--
105
2.20.1
37
2.25.1
106
107
diff view generated by jsdifflib
New patch
[PULL 02/28] target/arm: allow setting SCR_EL3.EnTP2 when FEAT_SME is implemented
1
From: Jerome Forissier <jerome.forissier@linaro.org>
1
2
3
Updates write_scr() to allow setting SCR_EL3.EnTP2 when FEAT_SME is
4
implemented. SCR_EL3 being a 64-bit register, valid_mask is changed
5
to uint64_t and the SCR_* constants in target/arm/cpu.h are extended
6
to 64-bit so that masking and bitwise not (~) behave as expected.
7
8
This enables booting Linux with Trusted Firmware-A at EL3 with
9
"-M virt,secure=on -cpu max".
10
11
Cc: qemu-stable@nongnu.org
12
Fixes: 78cb9776662a ("target/arm: Enable SME for -cpu max")
13
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
14
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Message-id: 20221004072354.27037-1-jerome.forissier@linaro.org
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
---
19
target/arm/cpu.h | 54 ++++++++++++++++++++++-----------------------
20
target/arm/helper.c | 5 ++++-
21
2 files changed, 31 insertions(+), 28 deletions(-)
22
23
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/cpu.h
26
+++ b/target/arm/cpu.h
27
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
28
29
#define HPFAR_NS (1ULL << 63)
30
31
-#define SCR_NS (1U << 0)
32
-#define SCR_IRQ (1U << 1)
33
-#define SCR_FIQ (1U << 2)
34
-#define SCR_EA (1U << 3)
35
-#define SCR_FW (1U << 4)
36
-#define SCR_AW (1U << 5)
37
-#define SCR_NET (1U << 6)
38
-#define SCR_SMD (1U << 7)
39
-#define SCR_HCE (1U << 8)
40
-#define SCR_SIF (1U << 9)
41
-#define SCR_RW (1U << 10)
42
-#define SCR_ST (1U << 11)
43
-#define SCR_TWI (1U << 12)
44
-#define SCR_TWE (1U << 13)
45
-#define SCR_TLOR (1U << 14)
46
-#define SCR_TERR (1U << 15)
47
-#define SCR_APK (1U << 16)
48
-#define SCR_API (1U << 17)
49
-#define SCR_EEL2 (1U << 18)
50
-#define SCR_EASE (1U << 19)
51
-#define SCR_NMEA (1U << 20)
52
-#define SCR_FIEN (1U << 21)
53
-#define SCR_ENSCXT (1U << 25)
54
-#define SCR_ATA (1U << 26)
55
-#define SCR_FGTEN (1U << 27)
56
-#define SCR_ECVEN (1U << 28)
57
-#define SCR_TWEDEN (1U << 29)
58
+#define SCR_NS (1ULL << 0)
59
+#define SCR_IRQ (1ULL << 1)
60
+#define SCR_FIQ (1ULL << 2)
61
+#define SCR_EA (1ULL << 3)
62
+#define SCR_FW (1ULL << 4)
63
+#define SCR_AW (1ULL << 5)
64
+#define SCR_NET (1ULL << 6)
65
+#define SCR_SMD (1ULL << 7)
66
+#define SCR_HCE (1ULL << 8)
67
+#define SCR_SIF (1ULL << 9)
68
+#define SCR_RW (1ULL << 10)
69
+#define SCR_ST (1ULL << 11)
70
+#define SCR_TWI (1ULL << 12)
71
+#define SCR_TWE (1ULL << 13)
72
+#define SCR_TLOR (1ULL << 14)
73
+#define SCR_TERR (1ULL << 15)
74
+#define SCR_APK (1ULL << 16)
75
+#define SCR_API (1ULL << 17)
76
+#define SCR_EEL2 (1ULL << 18)
77
+#define SCR_EASE (1ULL << 19)
78
+#define SCR_NMEA (1ULL << 20)
79
+#define SCR_FIEN (1ULL << 21)
80
+#define SCR_ENSCXT (1ULL << 25)
81
+#define SCR_ATA (1ULL << 26)
82
+#define SCR_FGTEN (1ULL << 27)
83
+#define SCR_ECVEN (1ULL << 28)
84
+#define SCR_TWEDEN (1ULL << 29)
85
#define SCR_TWEDEL MAKE_64BIT_MASK(30, 4)
86
#define SCR_TME (1ULL << 34)
87
#define SCR_AMVOFFEN (1ULL << 35)
88
diff --git a/target/arm/helper.c b/target/arm/helper.c
89
index XXXXXXX..XXXXXXX 100644
90
--- a/target/arm/helper.c
91
+++ b/target/arm/helper.c
92
@@ -XXX,XX +XXX,XX @@ static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
93
static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
94
{
95
/* Begin with base v8.0 state. */
96
- uint32_t valid_mask = 0x3fff;
97
+ uint64_t valid_mask = 0x3fff;
98
ARMCPU *cpu = env_archcpu(env);
99
100
/*
101
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
102
if (cpu_isar_feature(aa64_doublefault, cpu)) {
103
valid_mask |= SCR_EASE | SCR_NMEA;
104
}
105
+ if (cpu_isar_feature(aa64_sme, cpu)) {
106
+ valid_mask |= SCR_ENTP2;
107
+ }
108
} else {
109
valid_mask &= ~(SCR_RW | SCR_ST);
110
if (cpu_isar_feature(aa32_ras, cpu)) {
111
--
112
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/12] hw/arm/exynos4: Use the IEC binary prefix definitions
[PULL 03/28] docs/nuvoton: Update URL for images
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Joel Stanley <joel@jms.id.au>
2
2
3
It eases code review, unit is explicit.
3
openpower.xyz was retired some time ago. The OpenBMC Jenkins is where
4
images can be found these days.
4
5
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Signed-off-by: Joel Stanley <joel@jms.id.au>
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Hao Wu <wuhaotsh@google.com>
7
Message-id: 20190520214342.13709-3-philmd@redhat.com
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20221004050042.22681-1-joel@jms.id.au
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
12
---
10
hw/arm/exynos4_boards.c | 5 +++--
13
docs/system/arm/nuvoton.rst | 4 ++--
11
1 file changed, 3 insertions(+), 2 deletions(-)
14
1 file changed, 2 insertions(+), 2 deletions(-)
12
15
13
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
16
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
14
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/exynos4_boards.c
18
--- a/docs/system/arm/nuvoton.rst
16
+++ b/hw/arm/exynos4_boards.c
19
+++ b/docs/system/arm/nuvoton.rst
17
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ Boot options
18
*/
21
19
22
The Nuvoton machines can boot from an OpenBMC firmware image, or directly into
20
#include "qemu/osdep.h"
23
a kernel using the ``-kernel`` option. OpenBMC images for ``quanta-gsj`` and
21
+#include "qemu/units.h"
24
-possibly others can be downloaded from the OpenPOWER jenkins :
22
#include "qapi/error.h"
25
+possibly others can be downloaded from the OpenBMC jenkins :
23
#include "qemu/error-report.h"
26
24
#include "qemu-common.h"
27
- https://openpower.xyz/
25
@@ -XXX,XX +XXX,XX @@ static int exynos4_board_smp_bootreg_addr[EXYNOS4_NUM_OF_BOARDS] = {
28
+ https://jenkins.openbmc.org/
26
};
29
27
30
The firmware image should be attached as an MTD drive. Example :
28
static unsigned long exynos4_board_ram_size[EXYNOS4_NUM_OF_BOARDS] = {
31
29
- [EXYNOS4_BOARD_NURI] = 0x40000000,
30
- [EXYNOS4_BOARD_SMDKC210] = 0x40000000,
31
+ [EXYNOS4_BOARD_NURI] = 1 * GiB,
32
+ [EXYNOS4_BOARD_SMDKC210] = 1 * GiB,
33
};
34
35
static struct arm_boot_info exynos4_board_binfo = {
36
--
32
--
37
2.20.1
33
2.25.1
38
34
39
35
diff view generated by jsdifflib
New patch
[PULL 04/28] target/arm: Split s2walk_secure from ipa_secure in get_phys_addr
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The starting security state comes with the translation regime,
4
not the current state of arm_is_secure_below_el3().
5
6
Create a new local variable, s2walk_secure, which does not need
7
to be written back to result->attrs.secure -- we compute that
8
value later, after the S2 walk is complete.
9
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Message-id: 20221001162318.153420-2-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
target/arm/ptw.c | 18 +++++++++---------
16
1 file changed, 9 insertions(+), 9 deletions(-)
17
18
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/ptw.c
21
+++ b/target/arm/ptw.c
22
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
23
hwaddr ipa;
24
int s1_prot;
25
int ret;
26
- bool ipa_secure;
27
+ bool ipa_secure, s2walk_secure;
28
ARMCacheAttrs cacheattrs1;
29
ARMMMUIdx s2_mmu_idx;
30
bool is_el0;
31
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
32
33
ipa = result->phys;
34
ipa_secure = result->attrs.secure;
35
- if (arm_is_secure_below_el3(env)) {
36
- if (ipa_secure) {
37
- result->attrs.secure = !(env->cp15.vstcr_el2 & VSTCR_SW);
38
- } else {
39
- result->attrs.secure = !(env->cp15.vtcr_el2 & VTCR_NSW);
40
- }
41
+ if (is_secure) {
42
+ /* Select TCR based on the NS bit from the S1 walk. */
43
+ s2walk_secure = !(ipa_secure
44
+ ? env->cp15.vstcr_el2 & VSTCR_SW
45
+ : env->cp15.vtcr_el2 & VTCR_NSW);
46
} else {
47
assert(!ipa_secure);
48
+ s2walk_secure = false;
49
}
50
51
- s2_mmu_idx = (result->attrs.secure
52
+ s2_mmu_idx = (s2walk_secure
53
? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2);
54
is_el0 = mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_SE10_0;
55
56
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
57
result->cacheattrs);
58
59
/* Check if IPA translates to secure or non-secure PA space. */
60
- if (arm_is_secure_below_el3(env)) {
61
+ if (is_secure) {
62
if (ipa_secure) {
63
result->attrs.secure =
64
!(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW));
65
--
66
2.25.1
diff view generated by jsdifflib
New patch
[PULL 05/28] target/arm: Make the final stage1+2 write to secure be unconditional
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
While the stage2 call to get_phys_addr_lpae should never set
4
attrs.secure when given a non-secure input, it's just as easy
5
to make the final update to attrs.secure be unconditional and
6
false in the case of non-secure input.
7
8
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20221007152159.1414065-1-richard.henderson@linaro.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/ptw.c | 21 ++++++++++-----------
15
1 file changed, 10 insertions(+), 11 deletions(-)
16
17
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/ptw.c
20
+++ b/target/arm/ptw.c
21
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
22
result->cacheattrs = combine_cacheattrs(env, cacheattrs1,
23
result->cacheattrs);
24
25
- /* Check if IPA translates to secure or non-secure PA space. */
26
- if (is_secure) {
27
- if (ipa_secure) {
28
- result->attrs.secure =
29
- !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW));
30
- } else {
31
- result->attrs.secure =
32
- !((env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW))
33
- || (env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)));
34
- }
35
- }
36
+ /*
37
+ * Check if IPA translates to secure or non-secure PA space.
38
+ * Note that VSTCR overrides VTCR and {N}SW overrides {N}SA.
39
+ */
40
+ result->attrs.secure =
41
+ (is_secure
42
+ && !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))
43
+ && (ipa_secure
44
+ || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW))));
45
+
46
return 0;
47
} else {
48
/*
49
--
50
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/12] target/arm: Simplify BFXIL expansion
[PULL 06/28] target/arm: Add is_secure parameter to get_phys_addr_lpae
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The mask implied by the extract is redundant with the one
3
Remove the use of regime_is_secure from get_phys_addr_lpae,
4
implied by the deposit. Also, fix spelling of BFXIL.
4
using the new parameter instead.
5
5
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20190514011129.11330-3-richard.henderson@linaro.org
8
Message-id: 20221001162318.153420-3-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
target/arm/translate-a64.c | 6 +++---
11
target/arm/ptw.c | 20 ++++++++++----------
12
1 file changed, 3 insertions(+), 3 deletions(-)
12
1 file changed, 10 insertions(+), 10 deletions(-)
13
13
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
16
--- a/target/arm/ptw.c
17
+++ b/target/arm/translate-a64.c
17
+++ b/target/arm/ptw.c
18
@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
18
@@ -XXX,XX +XXX,XX @@
19
tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len);
19
20
return;
20
static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
21
}
21
MMUAccessType access_type, ARMMMUIdx mmu_idx,
22
- /* opc == 1, BXFIL fall through to deposit */
22
- bool s1_is_el0, GetPhysAddrResult *result,
23
- tcg_gen_extract_i64(tcg_tmp, tcg_tmp, ri, len);
23
- ARMMMUFaultInfo *fi)
24
+ /* opc == 1, BFXIL fall through to deposit */
24
+ bool is_secure, bool s1_is_el0,
25
+ tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri);
25
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
26
pos = 0;
26
__attribute__((nonnull));
27
} else {
27
28
/* Handle the ri > si case with a deposit
28
/* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */
29
@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
29
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
30
len = ri;
30
GetPhysAddrResult s2 = {};
31
int ret;
32
33
- ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, false,
34
- &s2, fi);
35
+ ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx,
36
+ *is_secure, false, &s2, fi);
37
if (ret) {
38
assert(fi->type != ARMFault_None);
39
fi->s2addr = addr;
40
@@ -XXX,XX +XXX,XX @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
41
*/
42
static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
43
MMUAccessType access_type, ARMMMUIdx mmu_idx,
44
- bool s1_is_el0, GetPhysAddrResult *result,
45
- ARMMMUFaultInfo *fi)
46
+ bool is_secure, bool s1_is_el0,
47
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
48
{
49
ARMCPU *cpu = env_archcpu(env);
50
/* Read an LPAE long-descriptor translation table. */
51
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
52
* remain non-secure. We implement this by just ORing in the NSTable/NS
53
* bits at each step.
54
*/
55
- tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4);
56
+ tableattrs = is_secure ? 0 : (1 << 4);
57
for (;;) {
58
uint64_t descriptor;
59
bool nstable;
60
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
61
memset(result, 0, sizeof(*result));
62
63
ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx,
64
- is_el0, result, fi);
65
+ s2walk_secure, is_el0, result, fi);
66
fi->s2addr = ipa;
67
68
/* Combine the S1 and S2 perms. */
69
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
31
}
70
}
32
71
33
- if (opc == 1) { /* BFM, BXFIL */
72
if (regime_using_lpae_format(env, mmu_idx)) {
34
+ if (opc == 1) { /* BFM, BFXIL */
73
- return get_phys_addr_lpae(env, address, access_type, mmu_idx, false,
35
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len);
74
- result, fi);
36
} else {
75
+ return get_phys_addr_lpae(env, address, access_type, mmu_idx,
37
/* SBFM or UBFM: We start with zero, and we haven't modified
76
+ is_secure, false, result, fi);
77
} else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
78
return get_phys_addr_v6(env, address, access_type, mmu_idx,
79
is_secure, result, fi);
38
--
80
--
39
2.20.1
81
2.25.1
40
82
41
83
diff view generated by jsdifflib
New patch
[PULL 07/28] target/arm: Fix S2 disabled check in S1_ptw_translate
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Pass the correct stage2 mmu_idx to regime_translation_disabled,
4
which we computed afterward.
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20221001162318.153420-4-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/ptw.c | 6 +++---
12
1 file changed, 3 insertions(+), 3 deletions(-)
13
14
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/ptw.c
17
+++ b/target/arm/ptw.c
18
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
19
hwaddr addr, bool *is_secure,
20
ARMMMUFaultInfo *fi)
21
{
22
+ ARMMMUIdx s2_mmu_idx = *is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
23
+
24
if (arm_mmu_idx_is_stage1_of_2(mmu_idx) &&
25
- !regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
26
- ARMMMUIdx s2_mmu_idx = *is_secure ? ARMMMUIdx_Stage2_S
27
- : ARMMMUIdx_Stage2;
28
+ !regime_translation_disabled(env, s2_mmu_idx)) {
29
GetPhysAddrResult s2 = {};
30
int ret;
31
32
--
33
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/12] hw/arm/exynos4: Remove unuseful debug code
[PULL 08/28] target/arm: Add is_secure parameter to regime_translation_disabled
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
3
Remove the use of regime_is_secure from regime_translation_disabled,
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
4
using the new parameter instead.
5
Message-id: 20190520214342.13709-2-philmd@redhat.com
5
6
This fixes a bug in S1_ptw_translate and get_phys_addr where we had
7
passed ARMMMUIdx_Stage2 and not ARMMMUIdx_Stage2_S to determine if
8
Stage2 is disabled, affecting FEAT_SEL2.
9
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20221001162318.153420-5-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
15
---
8
hw/arm/exynos4_boards.c | 24 ------------------------
16
target/arm/ptw.c | 20 +++++++++++---------
9
1 file changed, 24 deletions(-)
17
1 file changed, 11 insertions(+), 9 deletions(-)
10
18
11
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
19
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
12
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/arm/exynos4_boards.c
21
--- a/target/arm/ptw.c
14
+++ b/hw/arm/exynos4_boards.c
22
+++ b/target/arm/ptw.c
15
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ static uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx, int ttbrn)
16
#include "hw/net/lan9118.h"
24
}
17
#include "hw/boards.h"
25
18
26
/* Return true if the specified stage of address translation is disabled */
19
-#undef DEBUG
27
-static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx)
20
-
28
+static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx,
21
-//#define DEBUG
29
+ bool is_secure)
22
-
30
{
23
-#ifdef DEBUG
31
uint64_t hcr_el2;
24
- #undef PRINT_DEBUG
32
25
- #define PRINT_DEBUG(fmt, args...) \
33
if (arm_feature(env, ARM_FEATURE_M)) {
26
- do { \
34
- switch (env->v7m.mpu_ctrl[regime_is_secure(env, mmu_idx)] &
27
- fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
35
+ switch (env->v7m.mpu_ctrl[is_secure] &
28
- } while (0)
36
(R_V7M_MPU_CTRL_ENABLE_MASK | R_V7M_MPU_CTRL_HFNMIENA_MASK)) {
29
-#else
37
case R_V7M_MPU_CTRL_ENABLE_MASK:
30
- #define PRINT_DEBUG(fmt, args...) do {} while (0)
38
/* Enabled, but not for HardFault and NMI */
31
-#endif
39
@@ -XXX,XX +XXX,XX @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx)
32
-
40
33
#define SMDK_LAN9118_BASE_ADDR 0x05000000
41
if (hcr_el2 & HCR_TGE) {
34
42
/* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
35
typedef enum Exynos4BoardType {
43
- if (!regime_is_secure(env, mmu_idx) && regime_el(env, mmu_idx) == 1) {
36
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
44
+ if (!is_secure && regime_el(env, mmu_idx) == 1) {
37
exynos4_board_binfo.gic_cpu_if_addr =
45
return true;
38
EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100;
46
}
39
47
}
40
- PRINT_DEBUG("\n ram_size: %luMiB [0x%08lx]\n"
48
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
41
- " kernel_filename: %s\n"
49
ARMMMUIdx s2_mmu_idx = *is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
42
- " kernel_cmdline: %s\n"
50
43
- " initrd_filename: %s\n",
51
if (arm_mmu_idx_is_stage1_of_2(mmu_idx) &&
44
- exynos4_board_ram_size[board_type] / 1048576,
52
- !regime_translation_disabled(env, s2_mmu_idx)) {
45
- exynos4_board_ram_size[board_type],
53
+ !regime_translation_disabled(env, s2_mmu_idx, *is_secure)) {
46
- machine->kernel_filename,
54
GetPhysAddrResult s2 = {};
47
- machine->kernel_cmdline,
55
int ret;
48
- machine->initrd_filename);
56
49
-
57
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
50
exynos4_boards_init_ram(s, get_system_memory(),
58
uint32_t base;
51
exynos4_board_ram_size[board_type]);
59
bool is_user = regime_is_user(env, mmu_idx);
60
61
- if (regime_translation_disabled(env, mmu_idx)) {
62
+ if (regime_translation_disabled(env, mmu_idx, is_secure)) {
63
/* MPU disabled. */
64
result->phys = address;
65
result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
66
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
67
result->page_size = TARGET_PAGE_SIZE;
68
result->prot = 0;
69
70
- if (regime_translation_disabled(env, mmu_idx) ||
71
+ if (regime_translation_disabled(env, mmu_idx, secure) ||
72
m_is_ppb_region(env, address)) {
73
/*
74
* MPU disabled or M profile PPB access: use default memory map.
75
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
76
* are done in arm_v7m_load_vector(), which always does a direct
77
* read using address_space_ldl(), rather than going via this function.
78
*/
79
- if (regime_translation_disabled(env, mmu_idx)) { /* MPU disabled */
80
+ if (regime_translation_disabled(env, mmu_idx, secure)) { /* MPU disabled */
81
hit = true;
82
} else if (m_is_ppb_region(env, address)) {
83
hit = true;
84
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
85
result, fi);
86
87
/* If S1 fails or S2 is disabled, return early. */
88
- if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2)) {
89
+ if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2,
90
+ is_secure)) {
91
return ret;
92
}
93
94
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
95
96
/* Definitely a real MMU, not an MPU */
97
98
- if (regime_translation_disabled(env, mmu_idx)) {
99
+ if (regime_translation_disabled(env, mmu_idx, is_secure)) {
100
uint64_t hcr;
101
uint8_t memattr;
52
102
53
--
103
--
54
2.20.1
104
2.25.1
55
105
56
106
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/12] hw/arm/exynos4210: Add DMA support for the Exynos4210
[PULL 09/28] target/arm: Split out get_phys_addr_with_secure
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
QEMU already supports pl330. Instantiate it for Exynos4210.
3
Retain the existing get_phys_addr interface using the security
4
state derived from mmu_idx. Move the kerneldoc comments to the
5
header file where they belong.
4
6
5
Relevant part of Linux arch/arm/boot/dts/exynos4.dtsi:
6
7
/ {
8
soc: soc {
9
amba {
10
pdma0: pdma@12680000 {
11
compatible = "arm,pl330", "arm,primecell";
12
reg = <0x12680000 0x1000>;
13
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
14
clocks = <&clock CLK_PDMA0>;
15
clock-names = "apb_pclk";
16
#dma-cells = <1>;
17
#dma-channels = <8>;
18
#dma-requests = <32>;
19
};
20
pdma1: pdma@12690000 {
21
compatible = "arm,pl330", "arm,primecell";
22
reg = <0x12690000 0x1000>;
23
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
24
clocks = <&clock CLK_PDMA1>;
25
clock-names = "apb_pclk";
26
#dma-cells = <1>;
27
#dma-channels = <8>;
28
#dma-requests = <32>;
29
};
30
mdma1: mdma@12850000 {
31
compatible = "arm,pl330", "arm,primecell";
32
reg = <0x12850000 0x1000>;
33
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
34
clocks = <&clock CLK_MDMA>;
35
clock-names = "apb_pclk";
36
#dma-cells = <1>;
37
#dma-channels = <8>;
38
#dma-requests = <1>;
39
};
40
};
41
};
42
};
43
44
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
45
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
46
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
47
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
48
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
49
Message-id: 20190520214342.13709-4-philmd@redhat.com
9
Message-id: 20221001162318.153420-6-richard.henderson@linaro.org
50
[PMD: Do not set default qdev properties, create the controllers in the SoC
51
rather than the board (Peter Maydell), add dtsi in commit message]
52
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
53
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
54
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
55
---
11
---
56
hw/arm/exynos4210.c | 26 ++++++++++++++++++++++++++
12
target/arm/internals.h | 40 ++++++++++++++++++++++++++++++++++++++
57
1 file changed, 26 insertions(+)
13
target/arm/ptw.c | 44 ++++++++++++++----------------------------
14
2 files changed, 55 insertions(+), 29 deletions(-)
58
15
59
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
16
diff --git a/target/arm/internals.h b/target/arm/internals.h
60
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
61
--- a/hw/arm/exynos4210.c
18
--- a/target/arm/internals.h
62
+++ b/hw/arm/exynos4210.c
19
+++ b/target/arm/internals.h
63
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ typedef struct GetPhysAddrResult {
64
/* EHCI */
21
ARMCacheAttrs cacheattrs;
65
#define EXYNOS4210_EHCI_BASE_ADDR 0x12580000
22
} GetPhysAddrResult;
66
23
67
+/* DMA */
24
+/**
68
+#define EXYNOS4210_PL330_BASE0_ADDR 0x12680000
25
+ * get_phys_addr_with_secure: get the physical address for a virtual address
69
+#define EXYNOS4210_PL330_BASE1_ADDR 0x12690000
26
+ * @env: CPUARMState
70
+#define EXYNOS4210_PL330_BASE2_ADDR 0x12850000
27
+ * @address: virtual address to get physical address for
28
+ * @access_type: 0 for read, 1 for write, 2 for execute
29
+ * @mmu_idx: MMU index indicating required translation regime
30
+ * @is_secure: security state for the access
31
+ * @result: set on translation success.
32
+ * @fi: set to fault info if the translation fails
33
+ *
34
+ * Find the physical address corresponding to the given virtual address,
35
+ * by doing a translation table walk on MMU based systems or using the
36
+ * MPU state on MPU based systems.
37
+ *
38
+ * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
39
+ * prot and page_size may not be filled in, and the populated fsr value provides
40
+ * information on why the translation aborted, in the format of a
41
+ * DFSR/IFSR fault register, with the following caveats:
42
+ * * we honour the short vs long DFSR format differences.
43
+ * * the WnR bit is never set (the caller must do this).
44
+ * * for PSMAv5 based systems we don't bother to return a full FSR format
45
+ * value.
46
+ */
47
+bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
48
+ MMUAccessType access_type,
49
+ ARMMMUIdx mmu_idx, bool is_secure,
50
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
51
+ __attribute__((nonnull));
71
+
52
+
72
static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
53
+/**
73
0x09, 0x00, 0x00, 0x00 };
54
+ * get_phys_addr: get the physical address for a virtual address
74
55
+ * @env: CPUARMState
75
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu)
56
+ * @address: virtual address to get physical address for
76
return (0x9 << ARM_AFF1_SHIFT) | cpu;
57
+ * @access_type: 0 for read, 1 for write, 2 for execute
58
+ * @mmu_idx: MMU index indicating required translation regime
59
+ * @result: set on translation success.
60
+ * @fi: set to fault info if the translation fails
61
+ *
62
+ * Similarly, but use the security regime of @mmu_idx.
63
+ */
64
bool get_phys_addr(CPUARMState *env, target_ulong address,
65
MMUAccessType access_type, ARMMMUIdx mmu_idx,
66
GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
67
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
68
index XXXXXXX..XXXXXXX 100644
69
--- a/target/arm/ptw.c
70
+++ b/target/arm/ptw.c
71
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *env,
72
return ret;
77
}
73
}
78
74
79
+static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
75
-/**
76
- * get_phys_addr - get the physical address for this virtual address
77
- *
78
- * Find the physical address corresponding to the given virtual address,
79
- * by doing a translation table walk on MMU based systems or using the
80
- * MPU state on MPU based systems.
81
- *
82
- * Returns false if the translation was successful. Otherwise, phys_ptr, attrs,
83
- * prot and page_size may not be filled in, and the populated fsr value provides
84
- * information on why the translation aborted, in the format of a
85
- * DFSR/IFSR fault register, with the following caveats:
86
- * * we honour the short vs long DFSR format differences.
87
- * * the WnR bit is never set (the caller must do this).
88
- * * for PSMAv5 based systems we don't bother to return a full FSR format
89
- * value.
90
- *
91
- * @env: CPUARMState
92
- * @address: virtual address to get physical address for
93
- * @access_type: 0 for read, 1 for write, 2 for execute
94
- * @mmu_idx: MMU index indicating required translation regime
95
- * @result: set on translation success.
96
- * @fi: set to fault info if the translation fails
97
- */
98
-bool get_phys_addr(CPUARMState *env, target_ulong address,
99
- MMUAccessType access_type, ARMMMUIdx mmu_idx,
100
- GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
101
+bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
102
+ MMUAccessType access_type, ARMMMUIdx mmu_idx,
103
+ bool is_secure, GetPhysAddrResult *result,
104
+ ARMMMUFaultInfo *fi)
105
{
106
ARMMMUIdx s1_mmu_idx = stage_1_mmu_idx(mmu_idx);
107
- bool is_secure = regime_is_secure(env, mmu_idx);
108
109
if (mmu_idx != s1_mmu_idx) {
110
/*
111
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
112
ARMMMUIdx s2_mmu_idx;
113
bool is_el0;
114
115
- ret = get_phys_addr(env, address, access_type, s1_mmu_idx,
116
- result, fi);
117
+ ret = get_phys_addr_with_secure(env, address, access_type,
118
+ s1_mmu_idx, is_secure, result, fi);
119
120
/* If S1 fails or S2 is disabled, return early. */
121
if (ret || regime_translation_disabled(env, ARMMMUIdx_Stage2,
122
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
123
}
124
}
125
126
+bool get_phys_addr(CPUARMState *env, target_ulong address,
127
+ MMUAccessType access_type, ARMMMUIdx mmu_idx,
128
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
80
+{
129
+{
81
+ SysBusDevice *busdev;
130
+ return get_phys_addr_with_secure(env, address, access_type, mmu_idx,
82
+ DeviceState *dev;
131
+ regime_is_secure(env, mmu_idx),
83
+
132
+ result, fi);
84
+ dev = qdev_create(NULL, "pl330");
85
+ qdev_prop_set_uint8(dev, "num_periph_req", nreq);
86
+ qdev_init_nofail(dev);
87
+ busdev = SYS_BUS_DEVICE(dev);
88
+ sysbus_mmio_map(busdev, 0, base);
89
+ sysbus_connect_irq(busdev, 0, irq);
90
+}
133
+}
91
+
134
+
92
Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
135
hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
136
MemTxAttrs *attrs)
93
{
137
{
94
Exynos4210State *s = g_new0(Exynos4210State, 1);
95
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
96
sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
97
s->irq_table[exynos4210_get_irq(28, 3)]);
98
99
+ /*** DMA controllers ***/
100
+ pl330_create(EXYNOS4210_PL330_BASE0_ADDR,
101
+ qemu_irq_invert(s->irq_table[exynos4210_get_irq(35, 1)]), 32);
102
+ pl330_create(EXYNOS4210_PL330_BASE1_ADDR,
103
+ qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
104
+ pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
105
+ qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
106
+
107
return s;
108
}
109
--
138
--
110
2.20.1
139
2.25.1
111
112
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/12] hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3
[PULL 10/28] target/arm: Add is_secure parameter to v7m_read_half_insn
1
The ICC_CTLR_EL3 register includes some bits which are aliases
1
From: Richard Henderson <richard.henderson@linaro.org>
2
of bits in the ICC_CTLR_EL1(S) and (NS) registers. QEMU chooses
3
to keep those bits in the cs->icc_ctlr_el1[] struct fields.
4
Unfortunately a missing '~' in the code to update the bits
5
in those fields meant that writing to ICC_CTLR_EL3 would corrupt
6
the ICC_CLTR_EL1 register values.
7
2
3
Remove the use of regime_is_secure from v7m_read_half_insn, using
4
the new parameter instead.
5
6
As it happens, both callers pass true, propagated from the argument
7
to arm_v7m_mmu_idx_for_secstate which created the mmu_idx argument,
8
but that is a detail of v7m_handle_execute_nsc we need not expose
9
to the callee.
10
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20221001162318.153420-7-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Message-id: 20190520162809.2677-5-peter.maydell@linaro.org
11
---
16
---
12
hw/intc/arm_gicv3_cpuif.c | 4 ++--
17
target/arm/m_helper.c | 9 ++++-----
13
1 file changed, 2 insertions(+), 2 deletions(-)
18
1 file changed, 4 insertions(+), 5 deletions(-)
14
19
15
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
20
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
16
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/intc/arm_gicv3_cpuif.c
22
--- a/target/arm/m_helper.c
18
+++ b/hw/intc/arm_gicv3_cpuif.c
23
+++ b/target/arm/m_helper.c
19
@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
24
@@ -XXX,XX +XXX,XX @@ static bool do_v7m_function_return(ARMCPU *cpu)
20
trace_gicv3_icc_ctlr_el3_write(gicv3_redist_affid(cs), value);
25
return true;
21
26
}
22
/* *_EL1NS and *_EL1S bits are aliases into the ICC_CTLR_EL1 bits. */
27
23
- cs->icc_ctlr_el1[GICV3_NS] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
28
-static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
24
+ cs->icc_ctlr_el1[GICV3_NS] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
29
+static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool secure,
25
if (value & ICC_CTLR_EL3_EOIMODE_EL1NS) {
30
uint32_t addr, uint16_t *insn)
26
cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE;
31
{
32
/*
33
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
34
ARMMMUFaultInfo fi = {};
35
MemTxResult txres;
36
37
- v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx,
38
- regime_is_secure(env, mmu_idx), &sattrs);
39
+ v8m_security_lookup(env, addr, MMU_INST_FETCH, mmu_idx, secure, &sattrs);
40
if (!sattrs.nsc || sattrs.ns) {
41
/*
42
* This must be the second half of the insn, and it straddles a
43
@@ -XXX,XX +XXX,XX @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
44
/* We want to do the MPU lookup as secure; work out what mmu_idx that is */
45
mmu_idx = arm_v7m_mmu_idx_for_secstate(env, true);
46
47
- if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15], &insn)) {
48
+ if (!v7m_read_half_insn(cpu, mmu_idx, true, env->regs[15], &insn)) {
49
return false;
27
}
50
}
28
@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
51
29
cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_CBPR;
52
@@ -XXX,XX +XXX,XX @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
53
goto gen_invep;
30
}
54
}
31
55
32
- cs->icc_ctlr_el1[GICV3_S] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
56
- if (!v7m_read_half_insn(cpu, mmu_idx, env->regs[15] + 2, &insn)) {
33
+ cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
57
+ if (!v7m_read_half_insn(cpu, mmu_idx, true, env->regs[15] + 2, &insn)) {
34
if (value & ICC_CTLR_EL3_EOIMODE_EL1S) {
58
return false;
35
cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_EOIMODE;
36
}
59
}
60
37
--
61
--
38
2.20.1
62
2.25.1
39
63
40
64
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/12] target/arm: Fix vector operation segfault
[PULL 11/28] target/arm: Add TBFLAG_M32.SECURE
1
From: Alistair Francis <alistair.francis@wdc.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Commit 89e68b575 "target/arm: Use vector operations for saturation"
3
Remove the use of regime_is_secure from arm_tr_init_disas_context.
4
causes this abort() when booting QEMU ARM with a Cortex-A15:
4
Instead, provide the value of v8m_secure directly from tb_flags.
5
Rather than use regime_is_secure, use the env->v7m.secure directly,
6
as per arm_mmu_idx_el.
5
7
6
0 0x00007ffff4c2382f in raise () at /usr/lib/libc.so.6
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
1 0x00007ffff4c0e672 in abort () at /usr/lib/libc.so.6
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
2 0x00005555559c1839 in disas_neon_data_insn (insn=<optimized out>, s=<optimized out>) at ./target/arm/translate.c:6673
10
Message-id: 20221001162318.153420-8-richard.henderson@linaro.org
9
3 0x00005555559c1839 in disas_neon_data_insn (s=<optimized out>, insn=<optimized out>) at ./target/arm/translate.c:6386
10
4 0x00005555559cd8a4 in disas_arm_insn (insn=4081107068, s=0x7fffe59a9510) at ./target/arm/translate.c:9289
11
5 0x00005555559cd8a4 in arm_tr_translate_insn (dcbase=0x7fffe59a9510, cpu=<optimized out>) at ./target/arm/translate.c:13612
12
6 0x00005555558d1d39 in translator_loop (ops=0x5555561cc580 <arm_translator_ops>, db=0x7fffe59a9510, cpu=0x55555686a2f0, tb=<optimized out>, max_insns=<optimized out>) at ./accel/tcg/translator.c:96
13
7 0x00005555559d10d4 in gen_intermediate_code (cpu=cpu@entry=0x55555686a2f0, tb=tb@entry=0x7fffd7840080 <code_gen_buffer+126091347>, max_insns=max_insns@entry=512) at ./target/arm/translate.c:13901
14
8 0x00005555558d06b9 in tb_gen_code (cpu=cpu@entry=0x55555686a2f0, pc=3067096216, cs_base=0, flags=192, cflags=-16252928, cflags@entry=524288) at ./accel/tcg/translate-all.c:1736
15
9 0x00005555558ce467 in tb_find (cf_mask=524288, tb_exit=1, last_tb=0x7fffd783e640 <code_gen_buffer+126084627>, cpu=0x1) at ./accel/tcg/cpu-exec.c:407
16
10 0x00005555558ce467 in cpu_exec (cpu=cpu@entry=0x55555686a2f0) at ./accel/tcg/cpu-exec.c:728
17
11 0x000055555588b0cf in tcg_cpu_exec (cpu=0x55555686a2f0) at ./cpus.c:1431
18
12 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=0x55555686a2f0) at ./cpus.c:1735
19
13 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=arg@entry=0x55555686a2f0) at ./cpus.c:1709
20
14 0x0000555555d2629a in qemu_thread_start (args=<optimized out>) at ./util/qemu-thread-posix.c:502
21
15 0x00007ffff4db8a92 in start_thread () at /usr/lib/libpthread.
22
23
This patch ensures that we don't hit the abort() in the second switch
24
case in disas_neon_data_insn() as we will return from the first case.
25
26
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
27
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
28
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
29
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
30
Tested-by: Alex Bennée <alex.bennee@linaro.org>
31
Message-id: ad91b397f360b2fc7f4087e476f7df5b04d42ddb.1558021877.git.alistair.francis@wdc.com
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
---
12
---
34
target/arm/translate.c | 4 ++--
13
target/arm/cpu.h | 2 ++
35
1 file changed, 2 insertions(+), 2 deletions(-)
14
target/arm/helper.c | 4 ++++
15
target/arm/translate.c | 3 +--
16
3 files changed, 7 insertions(+), 2 deletions(-)
36
17
18
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/cpu.h
21
+++ b/target/arm/cpu.h
22
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_M32, NEW_FP_CTXT_NEEDED, 3, 1) /* Not cached. */
23
FIELD(TBFLAG_M32, FPCCR_S_WRONG, 4, 1) /* Not cached. */
24
/* Set if MVE insns are definitely not predicated by VPR or LTPSIZE */
25
FIELD(TBFLAG_M32, MVE_NO_PRED, 5, 1) /* Not cached. */
26
+/* Set if in secure mode */
27
+FIELD(TBFLAG_M32, SECURE, 6, 1)
28
29
/*
30
* Bit usage when in AArch64 state
31
diff --git a/target/arm/helper.c b/target/arm/helper.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/target/arm/helper.c
34
+++ b/target/arm/helper.c
35
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_m32(CPUARMState *env, int fp_el,
36
DP_TBFLAG_M32(flags, STACKCHECK, 1);
37
}
38
39
+ if (arm_feature(env, ARM_FEATURE_M_SECURITY) && env->v7m.secure) {
40
+ DP_TBFLAG_M32(flags, SECURE, 1);
41
+ }
42
+
43
return rebuild_hflags_common_32(env, fp_el, mmu_idx, flags);
44
}
45
37
diff --git a/target/arm/translate.c b/target/arm/translate.c
46
diff --git a/target/arm/translate.c b/target/arm/translate.c
38
index XXXXXXX..XXXXXXX 100644
47
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/translate.c
48
--- a/target/arm/translate.c
40
+++ b/target/arm/translate.c
49
+++ b/target/arm/translate.c
41
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
50
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
42
tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
51
dc->vfp_enabled = 1;
43
rn_ofs, rm_ofs, vec_size, vec_size,
52
dc->be_data = MO_TE;
44
(u ? uqadd_op : sqadd_op) + size);
53
dc->v7m_handler_mode = EX_TBFLAG_M32(tb_flags, HANDLER);
45
- break;
54
- dc->v8m_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) &&
46
+ return 0;
55
- regime_is_secure(env, dc->mmu_idx);
47
56
+ dc->v8m_secure = EX_TBFLAG_M32(tb_flags, SECURE);
48
case NEON_3R_VQSUB:
57
dc->v8m_stackcheck = EX_TBFLAG_M32(tb_flags, STACKCHECK);
49
tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
58
dc->v8m_fpccr_s_wrong = EX_TBFLAG_M32(tb_flags, FPCCR_S_WRONG);
50
rn_ofs, rm_ofs, vec_size, vec_size,
59
dc->v7m_new_fp_ctxt_needed =
51
(u ? uqsub_op : sqsub_op) + size);
52
- break;
53
+ return 0;
54
55
case NEON_3R_VMUL: /* VMUL */
56
if (u) {
57
--
60
--
58
2.20.1
61
2.25.1
59
60
diff view generated by jsdifflib
New patch
[PULL 12/28] target/arm: Merge regime_is_secure into get_phys_addr
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
This is the last use of regime_is_secure; remove it
4
entirely before changing the layout of ARMMMUIdx.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20221001162318.153420-9-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/internals.h | 42 ----------------------------------------
12
target/arm/ptw.c | 44 ++++++++++++++++++++++++++++++++++++++++--
13
2 files changed, 42 insertions(+), 44 deletions(-)
14
15
diff --git a/target/arm/internals.h b/target/arm/internals.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/internals.h
18
+++ b/target/arm/internals.h
19
@@ -XXX,XX +XXX,XX @@ static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx)
20
}
21
}
22
23
-/* Return true if this address translation regime is secure */
24
-static inline bool regime_is_secure(CPUARMState *env, ARMMMUIdx mmu_idx)
25
-{
26
- switch (mmu_idx) {
27
- case ARMMMUIdx_E10_0:
28
- case ARMMMUIdx_E10_1:
29
- case ARMMMUIdx_E10_1_PAN:
30
- case ARMMMUIdx_E20_0:
31
- case ARMMMUIdx_E20_2:
32
- case ARMMMUIdx_E20_2_PAN:
33
- case ARMMMUIdx_Stage1_E0:
34
- case ARMMMUIdx_Stage1_E1:
35
- case ARMMMUIdx_Stage1_E1_PAN:
36
- case ARMMMUIdx_E2:
37
- case ARMMMUIdx_Stage2:
38
- case ARMMMUIdx_MPrivNegPri:
39
- case ARMMMUIdx_MUserNegPri:
40
- case ARMMMUIdx_MPriv:
41
- case ARMMMUIdx_MUser:
42
- return false;
43
- case ARMMMUIdx_SE3:
44
- case ARMMMUIdx_SE10_0:
45
- case ARMMMUIdx_SE10_1:
46
- case ARMMMUIdx_SE10_1_PAN:
47
- case ARMMMUIdx_SE20_0:
48
- case ARMMMUIdx_SE20_2:
49
- case ARMMMUIdx_SE20_2_PAN:
50
- case ARMMMUIdx_Stage1_SE0:
51
- case ARMMMUIdx_Stage1_SE1:
52
- case ARMMMUIdx_Stage1_SE1_PAN:
53
- case ARMMMUIdx_SE2:
54
- case ARMMMUIdx_Stage2_S:
55
- case ARMMMUIdx_MSPrivNegPri:
56
- case ARMMMUIdx_MSUserNegPri:
57
- case ARMMMUIdx_MSPriv:
58
- case ARMMMUIdx_MSUser:
59
- return true;
60
- default:
61
- g_assert_not_reached();
62
- }
63
-}
64
-
65
static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx)
66
{
67
switch (mmu_idx) {
68
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
69
index XXXXXXX..XXXXXXX 100644
70
--- a/target/arm/ptw.c
71
+++ b/target/arm/ptw.c
72
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
73
MMUAccessType access_type, ARMMMUIdx mmu_idx,
74
GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
75
{
76
+ bool is_secure;
77
+
78
+ switch (mmu_idx) {
79
+ case ARMMMUIdx_E10_0:
80
+ case ARMMMUIdx_E10_1:
81
+ case ARMMMUIdx_E10_1_PAN:
82
+ case ARMMMUIdx_E20_0:
83
+ case ARMMMUIdx_E20_2:
84
+ case ARMMMUIdx_E20_2_PAN:
85
+ case ARMMMUIdx_Stage1_E0:
86
+ case ARMMMUIdx_Stage1_E1:
87
+ case ARMMMUIdx_Stage1_E1_PAN:
88
+ case ARMMMUIdx_E2:
89
+ case ARMMMUIdx_Stage2:
90
+ case ARMMMUIdx_MPrivNegPri:
91
+ case ARMMMUIdx_MUserNegPri:
92
+ case ARMMMUIdx_MPriv:
93
+ case ARMMMUIdx_MUser:
94
+ is_secure = false;
95
+ break;
96
+ case ARMMMUIdx_SE3:
97
+ case ARMMMUIdx_SE10_0:
98
+ case ARMMMUIdx_SE10_1:
99
+ case ARMMMUIdx_SE10_1_PAN:
100
+ case ARMMMUIdx_SE20_0:
101
+ case ARMMMUIdx_SE20_2:
102
+ case ARMMMUIdx_SE20_2_PAN:
103
+ case ARMMMUIdx_Stage1_SE0:
104
+ case ARMMMUIdx_Stage1_SE1:
105
+ case ARMMMUIdx_Stage1_SE1_PAN:
106
+ case ARMMMUIdx_SE2:
107
+ case ARMMMUIdx_Stage2_S:
108
+ case ARMMMUIdx_MSPrivNegPri:
109
+ case ARMMMUIdx_MSUserNegPri:
110
+ case ARMMMUIdx_MSPriv:
111
+ case ARMMMUIdx_MSUser:
112
+ is_secure = true;
113
+ break;
114
+ default:
115
+ g_assert_not_reached();
116
+ }
117
return get_phys_addr_with_secure(env, address, access_type, mmu_idx,
118
- regime_is_secure(env, mmu_idx),
119
- result, fi);
120
+ is_secure, result, fi);
121
}
122
123
hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
124
--
125
2.25.1
diff view generated by jsdifflib
New patch
[PULL 13/28] target/arm: Add is_secure parameter to do_ats_write
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Use get_phys_addr_with_secure directly. For a-profile, this is the
4
one place where the value of is_secure may not equal arm_is_secure(env).
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20221001162318.153420-10-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/helper.c | 19 ++++++++++++++-----
12
1 file changed, 14 insertions(+), 5 deletions(-)
13
14
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/helper.c
17
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@ static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri,
19
20
#ifdef CONFIG_TCG
21
static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
22
- MMUAccessType access_type, ARMMMUIdx mmu_idx)
23
+ MMUAccessType access_type, ARMMMUIdx mmu_idx,
24
+ bool is_secure)
25
{
26
bool ret;
27
uint64_t par64;
28
@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
29
ARMMMUFaultInfo fi = {};
30
GetPhysAddrResult res = {};
31
32
- ret = get_phys_addr(env, value, access_type, mmu_idx, &res, &fi);
33
+ ret = get_phys_addr_with_secure(env, value, access_type, mmu_idx,
34
+ is_secure, &res, &fi);
35
36
/*
37
* ATS operations only do S1 or S1+S2 translations, so we never
38
@@ -XXX,XX +XXX,XX @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
39
switch (el) {
40
case 3:
41
mmu_idx = ARMMMUIdx_SE3;
42
+ secure = true;
43
break;
44
case 2:
45
g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */
46
@@ -XXX,XX +XXX,XX @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
47
switch (el) {
48
case 3:
49
mmu_idx = ARMMMUIdx_SE10_0;
50
+ secure = true;
51
break;
52
case 2:
53
g_assert(!secure); /* ARMv8.4-SecEL2 is 64-bit only */
54
@@ -XXX,XX +XXX,XX @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
55
case 4:
56
/* stage 1+2 NonSecure PL1: ATS12NSOPR, ATS12NSOPW */
57
mmu_idx = ARMMMUIdx_E10_1;
58
+ secure = false;
59
break;
60
case 6:
61
/* stage 1+2 NonSecure PL0: ATS12NSOUR, ATS12NSOUW */
62
mmu_idx = ARMMMUIdx_E10_0;
63
+ secure = false;
64
break;
65
default:
66
g_assert_not_reached();
67
}
68
69
- par64 = do_ats_write(env, value, access_type, mmu_idx);
70
+ par64 = do_ats_write(env, value, access_type, mmu_idx, secure);
71
72
A32_BANKED_CURRENT_REG_SET(env, par, par64);
73
#else
74
@@ -XXX,XX +XXX,XX @@ static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
75
MMUAccessType access_type = ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA_LOAD;
76
uint64_t par64;
77
78
- par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2);
79
+ /* There is no SecureEL2 for AArch32. */
80
+ par64 = do_ats_write(env, value, access_type, ARMMMUIdx_E2, false);
81
82
A32_BANKED_CURRENT_REG_SET(env, par, par64);
83
#else
84
@@ -XXX,XX +XXX,XX @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
85
break;
86
case 6: /* AT S1E3R, AT S1E3W */
87
mmu_idx = ARMMMUIdx_SE3;
88
+ secure = true;
89
break;
90
default:
91
g_assert_not_reached();
92
@@ -XXX,XX +XXX,XX @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
93
g_assert_not_reached();
94
}
95
96
- env->cp15.par_el[1] = do_ats_write(env, value, access_type, mmu_idx);
97
+ env->cp15.par_el[1] = do_ats_write(env, value, access_type,
98
+ mmu_idx, secure);
99
#else
100
/* Handled by hardware accelerator. */
101
g_assert_not_reached();
102
--
103
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/12] target/arm: Use extract2 for EXTR
[PULL 14/28] target/arm: Fold secure and non-secure a-profile mmu indexes
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This is, after all, how we implement extract2 in tcg/aarch64.
3
For a-profile aarch64, which does not bank system registers, it takes
4
quite a lot of code to switch between security states. In the process,
5
registers such as TCR_EL{1,2} must be swapped, which in itself requires
6
the flushing of softmmu tlbs. Therefore it doesn't buy us anything to
7
separate tlbs by security state.
8
9
Retain the distinction between Stage2 and Stage2_S.
10
11
This will be important as we implement FEAT_RME, and do not wish to
12
add a third set of mmu indexes for Realm state.
4
13
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20190514011129.11330-2-richard.henderson@linaro.org
16
Message-id: 20221001162318.153420-11-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
18
---
10
target/arm/translate-a64.c | 38 ++++++++++++++++++++------------------
19
target/arm/cpu-param.h | 2 +-
11
1 file changed, 20 insertions(+), 18 deletions(-)
20
target/arm/cpu.h | 72 +++++++------------
21
target/arm/internals.h | 31 +-------
22
target/arm/helper.c | 144 +++++++++++++------------------------
23
target/arm/ptw.c | 25 ++-----
24
target/arm/translate-a64.c | 8 ---
25
target/arm/translate.c | 6 +-
26
7 files changed, 85 insertions(+), 203 deletions(-)
12
27
28
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
29
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/cpu-param.h
31
+++ b/target/arm/cpu-param.h
32
@@ -XXX,XX +XXX,XX @@
33
# define TARGET_PAGE_BITS_MIN 10
34
#endif
35
36
-#define NB_MMU_MODES 15
37
+#define NB_MMU_MODES 8
38
39
#endif
40
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/cpu.h
43
+++ b/target/arm/cpu.h
44
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
45
* table over and over.
46
* 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access
47
* Never (PAN) bit within PSTATE.
48
+ * 7. we fold together the secure and non-secure regimes for A-profile,
49
+ * because there are no banked system registers for aarch64, so the
50
+ * process of switching between secure and non-secure is
51
+ * already heavyweight.
52
*
53
* This gives us the following list of cases:
54
*
55
- * NS EL0 EL1&0 stage 1+2 (aka NS PL0)
56
- * NS EL1 EL1&0 stage 1+2 (aka NS PL1)
57
- * NS EL1 EL1&0 stage 1+2 +PAN
58
- * NS EL0 EL2&0
59
- * NS EL2 EL2&0
60
- * NS EL2 EL2&0 +PAN
61
- * NS EL2 (aka NS PL2)
62
- * S EL0 EL1&0 (aka S PL0)
63
- * S EL1 EL1&0 (not used if EL3 is 32 bit)
64
- * S EL1 EL1&0 +PAN
65
- * S EL3 (aka S PL1)
66
+ * EL0 EL1&0 stage 1+2 (aka NS PL0)
67
+ * EL1 EL1&0 stage 1+2 (aka NS PL1)
68
+ * EL1 EL1&0 stage 1+2 +PAN
69
+ * EL0 EL2&0
70
+ * EL2 EL2&0
71
+ * EL2 EL2&0 +PAN
72
+ * EL2 (aka NS PL2)
73
+ * EL3 (aka S PL1)
74
*
75
- * for a total of 11 different mmu_idx.
76
+ * for a total of 8 different mmu_idx.
77
*
78
* R profile CPUs have an MPU, but can use the same set of MMU indexes
79
- * as A profile. They only need to distinguish NS EL0 and NS EL1 (and
80
- * NS EL2 if we ever model a Cortex-R52).
81
+ * as A profile. They only need to distinguish EL0 and EL1 (and
82
+ * EL2 if we ever model a Cortex-R52).
83
*
84
* M profile CPUs are rather different as they do not have a true MMU.
85
* They have the following different MMU indexes:
86
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
87
#define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */
88
#define ARM_MMU_IDX_M 0x40 /* M profile */
89
90
-/* Meanings of the bits for A profile mmu idx values */
91
-#define ARM_MMU_IDX_A_NS 0x8
92
-
93
/* Meanings of the bits for M profile mmu idx values */
94
#define ARM_MMU_IDX_M_PRIV 0x1
95
#define ARM_MMU_IDX_M_NEGPRI 0x2
96
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
97
/*
98
* A-profile.
99
*/
100
- ARMMMUIdx_SE10_0 = 0 | ARM_MMU_IDX_A,
101
- ARMMMUIdx_SE20_0 = 1 | ARM_MMU_IDX_A,
102
- ARMMMUIdx_SE10_1 = 2 | ARM_MMU_IDX_A,
103
- ARMMMUIdx_SE20_2 = 3 | ARM_MMU_IDX_A,
104
- ARMMMUIdx_SE10_1_PAN = 4 | ARM_MMU_IDX_A,
105
- ARMMMUIdx_SE20_2_PAN = 5 | ARM_MMU_IDX_A,
106
- ARMMMUIdx_SE2 = 6 | ARM_MMU_IDX_A,
107
- ARMMMUIdx_SE3 = 7 | ARM_MMU_IDX_A,
108
-
109
- ARMMMUIdx_E10_0 = ARMMMUIdx_SE10_0 | ARM_MMU_IDX_A_NS,
110
- ARMMMUIdx_E20_0 = ARMMMUIdx_SE20_0 | ARM_MMU_IDX_A_NS,
111
- ARMMMUIdx_E10_1 = ARMMMUIdx_SE10_1 | ARM_MMU_IDX_A_NS,
112
- ARMMMUIdx_E20_2 = ARMMMUIdx_SE20_2 | ARM_MMU_IDX_A_NS,
113
- ARMMMUIdx_E10_1_PAN = ARMMMUIdx_SE10_1_PAN | ARM_MMU_IDX_A_NS,
114
- ARMMMUIdx_E20_2_PAN = ARMMMUIdx_SE20_2_PAN | ARM_MMU_IDX_A_NS,
115
- ARMMMUIdx_E2 = ARMMMUIdx_SE2 | ARM_MMU_IDX_A_NS,
116
+ ARMMMUIdx_E10_0 = 0 | ARM_MMU_IDX_A,
117
+ ARMMMUIdx_E20_0 = 1 | ARM_MMU_IDX_A,
118
+ ARMMMUIdx_E10_1 = 2 | ARM_MMU_IDX_A,
119
+ ARMMMUIdx_E20_2 = 3 | ARM_MMU_IDX_A,
120
+ ARMMMUIdx_E10_1_PAN = 4 | ARM_MMU_IDX_A,
121
+ ARMMMUIdx_E20_2_PAN = 5 | ARM_MMU_IDX_A,
122
+ ARMMMUIdx_E2 = 6 | ARM_MMU_IDX_A,
123
+ ARMMMUIdx_E3 = 7 | ARM_MMU_IDX_A,
124
125
/*
126
* These are not allocated TLBs and are used only for AT system
127
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
128
ARMMMUIdx_Stage1_E0 = 0 | ARM_MMU_IDX_NOTLB,
129
ARMMMUIdx_Stage1_E1 = 1 | ARM_MMU_IDX_NOTLB,
130
ARMMMUIdx_Stage1_E1_PAN = 2 | ARM_MMU_IDX_NOTLB,
131
- ARMMMUIdx_Stage1_SE0 = 3 | ARM_MMU_IDX_NOTLB,
132
- ARMMMUIdx_Stage1_SE1 = 4 | ARM_MMU_IDX_NOTLB,
133
- ARMMMUIdx_Stage1_SE1_PAN = 5 | ARM_MMU_IDX_NOTLB,
134
/*
135
* Not allocated a TLB: used only for second stage of an S12 page
136
* table walk, or for descriptor loads during first stage of an S1
137
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdx {
138
* then various TLB flush insns which currently are no-ops or flush
139
* only stage 1 MMU indexes will need to change to flush stage 2.
140
*/
141
- ARMMMUIdx_Stage2 = 6 | ARM_MMU_IDX_NOTLB,
142
- ARMMMUIdx_Stage2_S = 7 | ARM_MMU_IDX_NOTLB,
143
+ ARMMMUIdx_Stage2 = 3 | ARM_MMU_IDX_NOTLB,
144
+ ARMMMUIdx_Stage2_S = 4 | ARM_MMU_IDX_NOTLB,
145
146
/*
147
* M-profile.
148
@@ -XXX,XX +XXX,XX @@ typedef enum ARMMMUIdxBit {
149
TO_CORE_BIT(E2),
150
TO_CORE_BIT(E20_2),
151
TO_CORE_BIT(E20_2_PAN),
152
- TO_CORE_BIT(SE10_0),
153
- TO_CORE_BIT(SE20_0),
154
- TO_CORE_BIT(SE10_1),
155
- TO_CORE_BIT(SE20_2),
156
- TO_CORE_BIT(SE10_1_PAN),
157
- TO_CORE_BIT(SE20_2_PAN),
158
- TO_CORE_BIT(SE2),
159
- TO_CORE_BIT(SE3),
160
+ TO_CORE_BIT(E3),
161
162
TO_CORE_BIT(MUser),
163
TO_CORE_BIT(MPriv),
164
diff --git a/target/arm/internals.h b/target/arm/internals.h
165
index XXXXXXX..XXXXXXX 100644
166
--- a/target/arm/internals.h
167
+++ b/target/arm/internals.h
168
@@ -XXX,XX +XXX,XX @@ static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx)
169
case ARMMMUIdx_Stage1_E0:
170
case ARMMMUIdx_Stage1_E1:
171
case ARMMMUIdx_Stage1_E1_PAN:
172
- case ARMMMUIdx_Stage1_SE0:
173
- case ARMMMUIdx_Stage1_SE1:
174
- case ARMMMUIdx_Stage1_SE1_PAN:
175
case ARMMMUIdx_E10_0:
176
case ARMMMUIdx_E10_1:
177
case ARMMMUIdx_E10_1_PAN:
178
case ARMMMUIdx_E20_0:
179
case ARMMMUIdx_E20_2:
180
case ARMMMUIdx_E20_2_PAN:
181
- case ARMMMUIdx_SE10_0:
182
- case ARMMMUIdx_SE10_1:
183
- case ARMMMUIdx_SE10_1_PAN:
184
- case ARMMMUIdx_SE20_0:
185
- case ARMMMUIdx_SE20_2:
186
- case ARMMMUIdx_SE20_2_PAN:
187
return true;
188
default:
189
return false;
190
@@ -XXX,XX +XXX,XX @@ static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx)
191
{
192
switch (mmu_idx) {
193
case ARMMMUIdx_Stage1_E1_PAN:
194
- case ARMMMUIdx_Stage1_SE1_PAN:
195
case ARMMMUIdx_E10_1_PAN:
196
case ARMMMUIdx_E20_2_PAN:
197
- case ARMMMUIdx_SE10_1_PAN:
198
- case ARMMMUIdx_SE20_2_PAN:
199
return true;
200
default:
201
return false;
202
@@ -XXX,XX +XXX,XX @@ static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx)
203
static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
204
{
205
switch (mmu_idx) {
206
- case ARMMMUIdx_SE20_0:
207
- case ARMMMUIdx_SE20_2:
208
- case ARMMMUIdx_SE20_2_PAN:
209
case ARMMMUIdx_E20_0:
210
case ARMMMUIdx_E20_2:
211
case ARMMMUIdx_E20_2_PAN:
212
case ARMMMUIdx_Stage2:
213
case ARMMMUIdx_Stage2_S:
214
- case ARMMMUIdx_SE2:
215
case ARMMMUIdx_E2:
216
return 2;
217
- case ARMMMUIdx_SE3:
218
+ case ARMMMUIdx_E3:
219
return 3;
220
- case ARMMMUIdx_SE10_0:
221
- case ARMMMUIdx_Stage1_SE0:
222
- return arm_el_is_aa64(env, 3) ? 1 : 3;
223
- case ARMMMUIdx_SE10_1:
224
- case ARMMMUIdx_SE10_1_PAN:
225
+ case ARMMMUIdx_E10_0:
226
case ARMMMUIdx_Stage1_E0:
227
+ return arm_el_is_aa64(env, 3) || !arm_is_secure_below_el3(env) ? 1 : 3;
228
case ARMMMUIdx_Stage1_E1:
229
case ARMMMUIdx_Stage1_E1_PAN:
230
- case ARMMMUIdx_Stage1_SE1:
231
- case ARMMMUIdx_Stage1_SE1_PAN:
232
- case ARMMMUIdx_E10_0:
233
case ARMMMUIdx_E10_1:
234
case ARMMMUIdx_E10_1_PAN:
235
case ARMMMUIdx_MPrivNegPri:
236
@@ -XXX,XX +XXX,XX @@ static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx)
237
case ARMMMUIdx_Stage1_E0:
238
case ARMMMUIdx_Stage1_E1:
239
case ARMMMUIdx_Stage1_E1_PAN:
240
- case ARMMMUIdx_Stage1_SE0:
241
- case ARMMMUIdx_Stage1_SE1:
242
- case ARMMMUIdx_Stage1_SE1_PAN:
243
return true;
244
default:
245
return false;
246
diff --git a/target/arm/helper.c b/target/arm/helper.c
247
index XXXXXXX..XXXXXXX 100644
248
--- a/target/arm/helper.c
249
+++ b/target/arm/helper.c
250
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
251
/* Begin with base v8.0 state. */
252
uint64_t valid_mask = 0x3fff;
253
ARMCPU *cpu = env_archcpu(env);
254
+ uint64_t changed;
255
256
/*
257
* Because SCR_EL3 is the "real" cpreg and SCR is the alias, reset always
258
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
259
260
/* Clear all-context RES0 bits. */
261
value &= valid_mask;
262
- raw_write(env, ri, value);
263
+ changed = env->cp15.scr_el3 ^ value;
264
+ env->cp15.scr_el3 = value;
265
+
266
+ /*
267
+ * If SCR_EL3.NS changes, i.e. arm_is_secure_below_el3, then
268
+ * we must invalidate all TLBs below EL3.
269
+ */
270
+ if (changed & SCR_NS) {
271
+ tlb_flush_by_mmuidx(env_cpu(env), (ARMMMUIdxBit_E10_0 |
272
+ ARMMMUIdxBit_E20_0 |
273
+ ARMMMUIdxBit_E10_1 |
274
+ ARMMMUIdxBit_E20_2 |
275
+ ARMMMUIdxBit_E10_1_PAN |
276
+ ARMMMUIdxBit_E20_2_PAN |
277
+ ARMMMUIdxBit_E2));
278
+ }
279
}
280
281
static void scr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
282
@@ -XXX,XX +XXX,XX @@ static int gt_phys_redir_timeridx(CPUARMState *env)
283
case ARMMMUIdx_E20_0:
284
case ARMMMUIdx_E20_2:
285
case ARMMMUIdx_E20_2_PAN:
286
- case ARMMMUIdx_SE20_0:
287
- case ARMMMUIdx_SE20_2:
288
- case ARMMMUIdx_SE20_2_PAN:
289
return GTIMER_HYP;
290
default:
291
return GTIMER_PHYS;
292
@@ -XXX,XX +XXX,XX @@ static int gt_virt_redir_timeridx(CPUARMState *env)
293
case ARMMMUIdx_E20_0:
294
case ARMMMUIdx_E20_2:
295
case ARMMMUIdx_E20_2_PAN:
296
- case ARMMMUIdx_SE20_0:
297
- case ARMMMUIdx_SE20_2:
298
- case ARMMMUIdx_SE20_2_PAN:
299
return GTIMER_HYPVIRT;
300
default:
301
return GTIMER_VIRT;
302
@@ -XXX,XX +XXX,XX @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
303
/* stage 1 current state PL1: ATS1CPR, ATS1CPW, ATS1CPRP, ATS1CPWP */
304
switch (el) {
305
case 3:
306
- mmu_idx = ARMMMUIdx_SE3;
307
+ mmu_idx = ARMMMUIdx_E3;
308
secure = true;
309
break;
310
case 2:
311
@@ -XXX,XX +XXX,XX @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
312
/* fall through */
313
case 1:
314
if (ri->crm == 9 && (env->uncached_cpsr & CPSR_PAN)) {
315
- mmu_idx = (secure ? ARMMMUIdx_Stage1_SE1_PAN
316
- : ARMMMUIdx_Stage1_E1_PAN);
317
+ mmu_idx = ARMMMUIdx_Stage1_E1_PAN;
318
} else {
319
- mmu_idx = secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stage1_E1;
320
+ mmu_idx = ARMMMUIdx_Stage1_E1;
321
}
322
break;
323
default:
324
@@ -XXX,XX +XXX,XX @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
325
/* stage 1 current state PL0: ATS1CUR, ATS1CUW */
326
switch (el) {
327
case 3:
328
- mmu_idx = ARMMMUIdx_SE10_0;
329
+ mmu_idx = ARMMMUIdx_E10_0;
330
secure = true;
331
break;
332
case 2:
333
@@ -XXX,XX +XXX,XX @@ static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
334
mmu_idx = ARMMMUIdx_Stage1_E0;
335
break;
336
case 1:
337
- mmu_idx = secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E0;
338
+ mmu_idx = ARMMMUIdx_Stage1_E0;
339
break;
340
default:
341
g_assert_not_reached();
342
@@ -XXX,XX +XXX,XX @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
343
switch (ri->opc1) {
344
case 0: /* AT S1E1R, AT S1E1W, AT S1E1RP, AT S1E1WP */
345
if (ri->crm == 9 && (env->pstate & PSTATE_PAN)) {
346
- mmu_idx = (secure ? ARMMMUIdx_Stage1_SE1_PAN
347
- : ARMMMUIdx_Stage1_E1_PAN);
348
+ mmu_idx = ARMMMUIdx_Stage1_E1_PAN;
349
} else {
350
- mmu_idx = secure ? ARMMMUIdx_Stage1_SE1 : ARMMMUIdx_Stage1_E1;
351
+ mmu_idx = ARMMMUIdx_Stage1_E1;
352
}
353
break;
354
case 4: /* AT S1E2R, AT S1E2W */
355
- mmu_idx = secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2;
356
+ mmu_idx = ARMMMUIdx_E2;
357
break;
358
case 6: /* AT S1E3R, AT S1E3W */
359
- mmu_idx = ARMMMUIdx_SE3;
360
+ mmu_idx = ARMMMUIdx_E3;
361
secure = true;
362
break;
363
default:
364
@@ -XXX,XX +XXX,XX @@ static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri,
365
}
366
break;
367
case 2: /* AT S1E0R, AT S1E0W */
368
- mmu_idx = secure ? ARMMMUIdx_Stage1_SE0 : ARMMMUIdx_Stage1_E0;
369
+ mmu_idx = ARMMMUIdx_Stage1_E0;
370
break;
371
case 4: /* AT S12E1R, AT S12E1W */
372
- mmu_idx = secure ? ARMMMUIdx_SE10_1 : ARMMMUIdx_E10_1;
373
+ mmu_idx = ARMMMUIdx_E10_1;
374
break;
375
case 6: /* AT S12E0R, AT S12E0W */
376
- mmu_idx = secure ? ARMMMUIdx_SE10_0 : ARMMMUIdx_E10_0;
377
+ mmu_idx = ARMMMUIdx_E10_0;
378
break;
379
default:
380
g_assert_not_reached();
381
@@ -XXX,XX +XXX,XX @@ static void vmsa_tcr_ttbr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
382
uint16_t mask = ARMMMUIdxBit_E20_2 |
383
ARMMMUIdxBit_E20_2_PAN |
384
ARMMMUIdxBit_E20_0;
385
-
386
- if (arm_is_secure_below_el3(env)) {
387
- mask >>= ARM_MMU_IDX_A_NS;
388
- }
389
-
390
tlb_flush_by_mmuidx(env_cpu(env), mask);
391
}
392
raw_write(env, ri, value);
393
@@ -XXX,XX +XXX,XX @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
394
uint16_t mask = ARMMMUIdxBit_E10_1 |
395
ARMMMUIdxBit_E10_1_PAN |
396
ARMMMUIdxBit_E10_0;
397
-
398
- if (arm_is_secure_below_el3(env)) {
399
- mask >>= ARM_MMU_IDX_A_NS;
400
- }
401
-
402
tlb_flush_by_mmuidx(cs, mask);
403
raw_write(env, ri, value);
404
}
405
@@ -XXX,XX +XXX,XX @@ static int vae1_tlbmask(CPUARMState *env)
406
ARMMMUIdxBit_E10_1_PAN |
407
ARMMMUIdxBit_E10_0;
408
}
409
-
410
- if (arm_is_secure_below_el3(env)) {
411
- mask >>= ARM_MMU_IDX_A_NS;
412
- }
413
-
414
return mask;
415
}
416
417
@@ -XXX,XX +XXX,XX @@ static int vae1_tlbbits(CPUARMState *env, uint64_t addr)
418
mmu_idx = ARMMMUIdx_E10_0;
419
}
420
421
- if (arm_is_secure_below_el3(env)) {
422
- mmu_idx &= ~ARM_MMU_IDX_A_NS;
423
- }
424
-
425
return tlbbits_for_regime(env, mmu_idx, addr);
426
}
427
428
@@ -XXX,XX +XXX,XX @@ static int alle1_tlbmask(CPUARMState *env)
429
* stage 2 translations, whereas most other scopes only invalidate
430
* stage 1 translations.
431
*/
432
- if (arm_is_secure_below_el3(env)) {
433
- return ARMMMUIdxBit_SE10_1 |
434
- ARMMMUIdxBit_SE10_1_PAN |
435
- ARMMMUIdxBit_SE10_0;
436
- } else {
437
- return ARMMMUIdxBit_E10_1 |
438
- ARMMMUIdxBit_E10_1_PAN |
439
- ARMMMUIdxBit_E10_0;
440
- }
441
+ return (ARMMMUIdxBit_E10_1 |
442
+ ARMMMUIdxBit_E10_1_PAN |
443
+ ARMMMUIdxBit_E10_0);
444
}
445
446
static int e2_tlbmask(CPUARMState *env)
447
{
448
- if (arm_is_secure_below_el3(env)) {
449
- return ARMMMUIdxBit_SE20_0 |
450
- ARMMMUIdxBit_SE20_2 |
451
- ARMMMUIdxBit_SE20_2_PAN |
452
- ARMMMUIdxBit_SE2;
453
- } else {
454
- return ARMMMUIdxBit_E20_0 |
455
- ARMMMUIdxBit_E20_2 |
456
- ARMMMUIdxBit_E20_2_PAN |
457
- ARMMMUIdxBit_E2;
458
- }
459
+ return (ARMMMUIdxBit_E20_0 |
460
+ ARMMMUIdxBit_E20_2 |
461
+ ARMMMUIdxBit_E20_2_PAN |
462
+ ARMMMUIdxBit_E2);
463
}
464
465
static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
466
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
467
ARMCPU *cpu = env_archcpu(env);
468
CPUState *cs = CPU(cpu);
469
470
- tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_SE3);
471
+ tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E3);
472
}
473
474
static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
475
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
476
{
477
CPUState *cs = env_cpu(env);
478
479
- tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_SE3);
480
+ tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E3);
481
}
482
483
static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
484
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
485
CPUState *cs = CPU(cpu);
486
uint64_t pageaddr = sextract64(value << 12, 0, 56);
487
488
- tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_SE3);
489
+ tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E3);
490
}
491
492
static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
493
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
494
{
495
CPUState *cs = env_cpu(env);
496
uint64_t pageaddr = sextract64(value << 12, 0, 56);
497
- bool secure = arm_is_secure_below_el3(env);
498
- int mask = secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2;
499
- int bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2,
500
- pageaddr);
501
+ int bits = tlbbits_for_regime(env, ARMMMUIdx_E2, pageaddr);
502
503
- tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits);
504
+ tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr,
505
+ ARMMMUIdxBit_E2, bits);
506
}
507
508
static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
509
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
510
{
511
CPUState *cs = env_cpu(env);
512
uint64_t pageaddr = sextract64(value << 12, 0, 56);
513
- int bits = tlbbits_for_regime(env, ARMMMUIdx_SE3, pageaddr);
514
+ int bits = tlbbits_for_regime(env, ARMMMUIdx_E3, pageaddr);
515
516
tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr,
517
- ARMMMUIdxBit_SE3, bits);
518
+ ARMMMUIdxBit_E3, bits);
519
}
520
521
#ifdef TARGET_AARCH64
522
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_rvae1is_write(CPUARMState *env,
523
524
static int vae2_tlbmask(CPUARMState *env)
525
{
526
- return (arm_is_secure_below_el3(env)
527
- ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2);
528
+ return ARMMMUIdxBit_E2;
529
}
530
531
static void tlbi_aa64_rvae2_write(CPUARMState *env,
532
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_rvae3_write(CPUARMState *env,
533
* flush-last-level-only.
534
*/
535
536
- do_rvae_write(env, value, ARMMMUIdxBit_SE3,
537
- tlb_force_broadcast(env));
538
+ do_rvae_write(env, value, ARMMMUIdxBit_E3, tlb_force_broadcast(env));
539
}
540
541
static void tlbi_aa64_rvae3is_write(CPUARMState *env,
542
@@ -XXX,XX +XXX,XX @@ static void tlbi_aa64_rvae3is_write(CPUARMState *env,
543
* flush-last-level-only or inner/outer specific flushes.
544
*/
545
546
- do_rvae_write(env, value, ARMMMUIdxBit_SE3, true);
547
+ do_rvae_write(env, value, ARMMMUIdxBit_E3, true);
548
}
549
#endif
550
551
@@ -XXX,XX +XXX,XX @@ uint64_t arm_sctlr(CPUARMState *env, int el)
552
/* Only EL0 needs to be adjusted for EL1&0 or EL2&0. */
553
if (el == 0) {
554
ARMMMUIdx mmu_idx = arm_mmu_idx_el(env, 0);
555
- el = (mmu_idx == ARMMMUIdx_E20_0 || mmu_idx == ARMMMUIdx_SE20_0)
556
- ? 2 : 1;
557
+ el = mmu_idx == ARMMMUIdx_E20_0 ? 2 : 1;
558
}
559
return env->cp15.sctlr_el[el];
560
}
561
@@ -XXX,XX +XXX,XX @@ int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
562
switch (mmu_idx) {
563
case ARMMMUIdx_E10_0:
564
case ARMMMUIdx_E20_0:
565
- case ARMMMUIdx_SE10_0:
566
- case ARMMMUIdx_SE20_0:
567
return 0;
568
case ARMMMUIdx_E10_1:
569
case ARMMMUIdx_E10_1_PAN:
570
- case ARMMMUIdx_SE10_1:
571
- case ARMMMUIdx_SE10_1_PAN:
572
return 1;
573
case ARMMMUIdx_E2:
574
case ARMMMUIdx_E20_2:
575
case ARMMMUIdx_E20_2_PAN:
576
- case ARMMMUIdx_SE2:
577
- case ARMMMUIdx_SE20_2:
578
- case ARMMMUIdx_SE20_2_PAN:
579
return 2;
580
- case ARMMMUIdx_SE3:
581
+ case ARMMMUIdx_E3:
582
return 3;
583
default:
584
g_assert_not_reached();
585
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_mmu_idx_el(CPUARMState *env, int el)
586
}
587
break;
588
case 3:
589
- return ARMMMUIdx_SE3;
590
+ return ARMMMUIdx_E3;
591
default:
592
g_assert_not_reached();
593
}
594
595
- if (arm_is_secure_below_el3(env)) {
596
- idx &= ~ARM_MMU_IDX_A_NS;
597
- }
598
-
599
return idx;
600
}
601
602
@@ -XXX,XX +XXX,XX @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el,
603
switch (mmu_idx) {
604
case ARMMMUIdx_E10_1:
605
case ARMMMUIdx_E10_1_PAN:
606
- case ARMMMUIdx_SE10_1:
607
- case ARMMMUIdx_SE10_1_PAN:
608
/* TODO: ARMv8.3-NV */
609
DP_TBFLAG_A64(flags, UNPRIV, 1);
610
break;
611
case ARMMMUIdx_E20_2:
612
case ARMMMUIdx_E20_2_PAN:
613
- case ARMMMUIdx_SE20_2:
614
- case ARMMMUIdx_SE20_2_PAN:
615
/*
616
* Note that EL20_2 is gated by HCR_EL2.E2H == 1, but EL20_0 is
617
* gated by HCR_EL2.<E2H,TGE> == '11', and so is LDTR.
618
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
619
index XXXXXXX..XXXXXXX 100644
620
--- a/target/arm/ptw.c
621
+++ b/target/arm/ptw.c
622
@@ -XXX,XX +XXX,XX @@ unsigned int arm_pamax(ARMCPU *cpu)
623
ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)
624
{
625
switch (mmu_idx) {
626
- case ARMMMUIdx_SE10_0:
627
- return ARMMMUIdx_Stage1_SE0;
628
- case ARMMMUIdx_SE10_1:
629
- return ARMMMUIdx_Stage1_SE1;
630
- case ARMMMUIdx_SE10_1_PAN:
631
- return ARMMMUIdx_Stage1_SE1_PAN;
632
case ARMMMUIdx_E10_0:
633
return ARMMMUIdx_Stage1_E0;
634
case ARMMMUIdx_E10_1:
635
@@ -XXX,XX +XXX,XX @@ static bool regime_translation_big_endian(CPUARMState *env, ARMMMUIdx mmu_idx)
636
static bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx)
637
{
638
switch (mmu_idx) {
639
- case ARMMMUIdx_SE10_0:
640
case ARMMMUIdx_E20_0:
641
- case ARMMMUIdx_SE20_0:
642
case ARMMMUIdx_Stage1_E0:
643
- case ARMMMUIdx_Stage1_SE0:
644
case ARMMMUIdx_MUser:
645
case ARMMMUIdx_MSUser:
646
case ARMMMUIdx_MUserNegPri:
647
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
648
649
s2_mmu_idx = (s2walk_secure
650
? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2);
651
- is_el0 = mmu_idx == ARMMMUIdx_E10_0 || mmu_idx == ARMMMUIdx_SE10_0;
652
+ is_el0 = mmu_idx == ARMMMUIdx_E10_0;
653
654
/*
655
* S1 is done, now do S2 translation.
656
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
657
case ARMMMUIdx_Stage1_E1:
658
case ARMMMUIdx_Stage1_E1_PAN:
659
case ARMMMUIdx_E2:
660
+ is_secure = arm_is_secure_below_el3(env);
661
+ break;
662
case ARMMMUIdx_Stage2:
663
case ARMMMUIdx_MPrivNegPri:
664
case ARMMMUIdx_MUserNegPri:
665
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
666
case ARMMMUIdx_MUser:
667
is_secure = false;
668
break;
669
- case ARMMMUIdx_SE3:
670
- case ARMMMUIdx_SE10_0:
671
- case ARMMMUIdx_SE10_1:
672
- case ARMMMUIdx_SE10_1_PAN:
673
- case ARMMMUIdx_SE20_0:
674
- case ARMMMUIdx_SE20_2:
675
- case ARMMMUIdx_SE20_2_PAN:
676
- case ARMMMUIdx_Stage1_SE0:
677
- case ARMMMUIdx_Stage1_SE1:
678
- case ARMMMUIdx_Stage1_SE1_PAN:
679
- case ARMMMUIdx_SE2:
680
+ case ARMMMUIdx_E3:
681
case ARMMMUIdx_Stage2_S:
682
case ARMMMUIdx_MSPrivNegPri:
683
case ARMMMUIdx_MSUserNegPri:
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
684
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
index XXXXXXX..XXXXXXX 100644
685
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
686
--- a/target/arm/translate-a64.c
16
+++ b/target/arm/translate-a64.c
687
+++ b/target/arm/translate-a64.c
17
@@ -XXX,XX +XXX,XX @@ static void disas_extract(DisasContext *s, uint32_t insn)
688
@@ -XXX,XX +XXX,XX @@ static int get_a64_user_mem_index(DisasContext *s)
18
} else {
689
case ARMMMUIdx_E20_2_PAN:
19
tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));
690
useridx = ARMMMUIdx_E20_0;
20
}
691
break;
21
- } else if (rm == rn) { /* ROR */
692
- case ARMMMUIdx_SE10_1:
22
- tcg_rm = cpu_reg(s, rm);
693
- case ARMMMUIdx_SE10_1_PAN:
23
- if (sf) {
694
- useridx = ARMMMUIdx_SE10_0;
24
- tcg_gen_rotri_i64(tcg_rd, tcg_rm, imm);
695
- break;
25
- } else {
696
- case ARMMMUIdx_SE20_2:
26
- TCGv_i32 tmp = tcg_temp_new_i32();
697
- case ARMMMUIdx_SE20_2_PAN:
27
- tcg_gen_extrl_i64_i32(tmp, tcg_rm);
698
- useridx = ARMMMUIdx_SE20_0;
28
- tcg_gen_rotri_i32(tmp, tmp, imm);
699
- break;
29
- tcg_gen_extu_i32_i64(tcg_rd, tmp);
700
default:
30
- tcg_temp_free_i32(tmp);
701
g_assert_not_reached();
31
- }
32
} else {
33
- tcg_rm = read_cpu_reg(s, rm, sf);
34
- tcg_rn = read_cpu_reg(s, rn, sf);
35
- tcg_gen_shri_i64(tcg_rm, tcg_rm, imm);
36
- tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm);
37
- tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn);
38
- if (!sf) {
39
- tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
40
+ tcg_rm = cpu_reg(s, rm);
41
+ tcg_rn = cpu_reg(s, rn);
42
+
43
+ if (sf) {
44
+ /* Specialization to ROR happens in EXTRACT2. */
45
+ tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, imm);
46
+ } else {
47
+ TCGv_i32 t0 = tcg_temp_new_i32();
48
+
49
+ tcg_gen_extrl_i64_i32(t0, tcg_rm);
50
+ if (rm == rn) {
51
+ tcg_gen_rotri_i32(t0, t0, imm);
52
+ } else {
53
+ TCGv_i32 t1 = tcg_temp_new_i32();
54
+ tcg_gen_extrl_i64_i32(t1, tcg_rn);
55
+ tcg_gen_extract2_i32(t0, t0, t1, imm);
56
+ tcg_temp_free_i32(t1);
57
+ }
58
+ tcg_gen_extu_i32_i64(tcg_rd, t0);
59
+ tcg_temp_free_i32(t0);
60
}
61
}
702
}
62
}
703
diff --git a/target/arm/translate.c b/target/arm/translate.c
704
index XXXXXXX..XXXXXXX 100644
705
--- a/target/arm/translate.c
706
+++ b/target/arm/translate.c
707
@@ -XXX,XX +XXX,XX @@ static inline int get_a32_user_mem_index(DisasContext *s)
708
* otherwise, access as if at PL0.
709
*/
710
switch (s->mmu_idx) {
711
+ case ARMMMUIdx_E3:
712
case ARMMMUIdx_E2: /* this one is UNPREDICTABLE */
713
case ARMMMUIdx_E10_0:
714
case ARMMMUIdx_E10_1:
715
case ARMMMUIdx_E10_1_PAN:
716
return arm_to_core_mmu_idx(ARMMMUIdx_E10_0);
717
- case ARMMMUIdx_SE3:
718
- case ARMMMUIdx_SE10_0:
719
- case ARMMMUIdx_SE10_1:
720
- case ARMMMUIdx_SE10_1_PAN:
721
- return arm_to_core_mmu_idx(ARMMMUIdx_SE10_0);
722
case ARMMMUIdx_MUser:
723
case ARMMMUIdx_MPriv:
724
return arm_to_core_mmu_idx(ARMMMUIdx_MUser);
63
--
725
--
64
2.20.1
726
2.25.1
65
66
diff view generated by jsdifflib
New patch
[PULL 15/28] target/arm: Reorg regime_translation_disabled
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Use a switch on mmu_idx for the a-profile indexes, instead of
4
three different if's vs regime_el and arm_mmu_idx_is_stage1_of_2.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20221001162318.153420-12-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/ptw.c | 32 +++++++++++++++++++++++++-------
12
1 file changed, 25 insertions(+), 7 deletions(-)
13
14
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/ptw.c
17
+++ b/target/arm/ptw.c
18
@@ -XXX,XX +XXX,XX @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx,
19
20
hcr_el2 = arm_hcr_el2_eff(env);
21
22
- if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
23
+ switch (mmu_idx) {
24
+ case ARMMMUIdx_Stage2:
25
+ case ARMMMUIdx_Stage2_S:
26
/* HCR.DC means HCR.VM behaves as 1 */
27
return (hcr_el2 & (HCR_DC | HCR_VM)) == 0;
28
- }
29
30
- if (hcr_el2 & HCR_TGE) {
31
+ case ARMMMUIdx_E10_0:
32
+ case ARMMMUIdx_E10_1:
33
+ case ARMMMUIdx_E10_1_PAN:
34
/* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
35
- if (!is_secure && regime_el(env, mmu_idx) == 1) {
36
+ if (!is_secure && (hcr_el2 & HCR_TGE)) {
37
return true;
38
}
39
- }
40
+ break;
41
42
- if ((hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) {
43
+ case ARMMMUIdx_Stage1_E0:
44
+ case ARMMMUIdx_Stage1_E1:
45
+ case ARMMMUIdx_Stage1_E1_PAN:
46
/* HCR.DC means SCTLR_EL1.M behaves as 0 */
47
- return true;
48
+ if (hcr_el2 & HCR_DC) {
49
+ return true;
50
+ }
51
+ break;
52
+
53
+ case ARMMMUIdx_E20_0:
54
+ case ARMMMUIdx_E20_2:
55
+ case ARMMMUIdx_E20_2_PAN:
56
+ case ARMMMUIdx_E2:
57
+ case ARMMMUIdx_E3:
58
+ break;
59
+
60
+ default:
61
+ g_assert_not_reached();
62
}
63
64
return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
65
--
66
2.25.1
diff view generated by jsdifflib
New patch
[PULL 16/28] target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
The effect of TGE does not only apply to non-secure state,
4
now that Secure EL2 exists.
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20221001162318.153420-13-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/ptw.c | 4 ++--
12
1 file changed, 2 insertions(+), 2 deletions(-)
13
14
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/ptw.c
17
+++ b/target/arm/ptw.c
18
@@ -XXX,XX +XXX,XX @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx,
19
case ARMMMUIdx_E10_0:
20
case ARMMMUIdx_E10_1:
21
case ARMMMUIdx_E10_1_PAN:
22
- /* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
23
- if (!is_secure && (hcr_el2 & HCR_TGE)) {
24
+ /* TGE means that EL0/1 act as if SCTLR_EL1.M is zero */
25
+ if (hcr_el2 & HCR_TGE) {
26
return true;
27
}
28
break;
29
--
30
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/12] hw/arm/exynos4210: QOM'ify the Exynos4210 SoC
[PULL 17/28] target/arm: Introduce arm_hcr_el2_eff_secstate
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
3
For page walking, we may require HCR for a security state
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
4
that is not "current".
5
Message-id: 20190520214342.13709-5-philmd@redhat.com
5
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20221001162318.153420-14-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
10
---
8
include/hw/arm/exynos4210.h | 9 +++++++--
11
target/arm/cpu.h | 20 +++++++++++++-------
9
hw/arm/exynos4210.c | 28 ++++++++++++++++++++++++----
12
target/arm/helper.c | 11 ++++++++---
10
hw/arm/exynos4_boards.c | 9 ++++++---
13
2 files changed, 21 insertions(+), 10 deletions(-)
11
3 files changed, 37 insertions(+), 9 deletions(-)
12
14
13
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/arm/exynos4210.h
17
--- a/target/arm/cpu.h
16
+++ b/include/hw/arm/exynos4210.h
18
+++ b/target/arm/cpu.h
17
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210Irq {
19
@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_secure(CPUARMState *env)
18
} Exynos4210Irq;
20
* Return true if the current security state has AArch64 EL2 or AArch32 Hyp.
19
21
* This corresponds to the pseudocode EL2Enabled()
20
typedef struct Exynos4210State {
22
*/
21
+ /*< private >*/
23
+static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure)
22
+ SysBusDevice parent_obj;
23
+ /*< public >*/
24
ARMCPU *cpu[EXYNOS4210_NCPUS];
25
Exynos4210Irq irqs;
26
qemu_irq *irq_table;
27
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210State {
28
I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
29
} Exynos4210State;
30
31
+#define TYPE_EXYNOS4210_SOC "exynos4210"
32
+#define EXYNOS4210_SOC(obj) \
33
+ OBJECT_CHECK(Exynos4210State, obj, TYPE_EXYNOS4210_SOC)
34
+
35
void exynos4210_write_secondary(ARMCPU *cpu,
36
const struct arm_boot_info *info);
37
38
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem);
39
-
40
/* Initialize exynos4210 IRQ subsystem stub */
41
qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
42
43
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/arm/exynos4210.c
46
+++ b/hw/arm/exynos4210.c
47
@@ -XXX,XX +XXX,XX @@ static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
48
sysbus_connect_irq(busdev, 0, irq);
49
}
50
51
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
52
+static void exynos4210_realize(DeviceState *socdev, Error **errp)
53
{
54
- Exynos4210State *s = g_new0(Exynos4210State, 1);
55
+ Exynos4210State *s = EXYNOS4210_SOC(socdev);
56
+ MemoryRegion *system_mem = get_system_memory();
57
qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
58
SysBusDevice *busdev;
59
DeviceState *dev;
60
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
61
qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
62
pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
63
qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
64
-
65
- return s;
66
}
67
+
68
+static void exynos4210_class_init(ObjectClass *klass, void *data)
69
+{
24
+{
70
+ DeviceClass *dc = DEVICE_CLASS(klass);
25
+ return arm_feature(env, ARM_FEATURE_EL2)
71
+
26
+ && (!secure || (env->cp15.scr_el3 & SCR_EEL2));
72
+ dc->realize = exynos4210_realize;
73
+}
27
+}
74
+
28
+
75
+static const TypeInfo exynos4210_info = {
29
static inline bool arm_is_el2_enabled(CPUARMState *env)
76
+ .name = TYPE_EXYNOS4210_SOC,
30
{
77
+ .parent = TYPE_SYS_BUS_DEVICE,
31
- if (arm_feature(env, ARM_FEATURE_EL2)) {
78
+ .instance_size = sizeof(Exynos4210State),
32
- if (arm_is_secure_below_el3(env)) {
79
+ .class_init = exynos4210_class_init,
33
- return (env->cp15.scr_el3 & SCR_EEL2) != 0;
80
+};
34
- }
81
+
35
- return true;
82
+static void exynos4210_register_types(void)
36
- }
37
- return false;
38
+ return arm_is_el2_enabled_secstate(env, arm_is_secure_below_el3(env));
39
}
40
41
#else
42
@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_secure(CPUARMState *env)
43
return false;
44
}
45
46
+static inline bool arm_is_el2_enabled_secstate(CPUARMState *env, bool secure)
83
+{
47
+{
84
+ type_register_static(&exynos4210_info);
48
+ return false;
85
+}
49
+}
86
+
50
+
87
+type_init(exynos4210_register_types)
51
static inline bool arm_is_el2_enabled(CPUARMState *env)
88
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
52
{
53
return false;
54
@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_el2_enabled(CPUARMState *env)
55
* "for all purposes other than a direct read or write access of HCR_EL2."
56
* Not included here is HCR_RW.
57
*/
58
+uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure);
59
uint64_t arm_hcr_el2_eff(CPUARMState *env);
60
uint64_t arm_hcrx_el2_eff(CPUARMState *env);
61
62
diff --git a/target/arm/helper.c b/target/arm/helper.c
89
index XXXXXXX..XXXXXXX 100644
63
index XXXXXXX..XXXXXXX 100644
90
--- a/hw/arm/exynos4_boards.c
64
--- a/target/arm/helper.c
91
+++ b/hw/arm/exynos4_boards.c
65
+++ b/target/arm/helper.c
92
@@ -XXX,XX +XXX,XX @@ typedef enum Exynos4BoardType {
66
@@ -XXX,XX +XXX,XX @@ static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri,
93
} Exynos4BoardType;
94
95
typedef struct Exynos4BoardState {
96
- Exynos4210State *soc;
97
+ Exynos4210State soc;
98
MemoryRegion dram0_mem;
99
MemoryRegion dram1_mem;
100
} Exynos4BoardState;
101
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
102
exynos4_boards_init_ram(s, get_system_memory(),
103
exynos4_board_ram_size[board_type]);
104
105
- s->soc = exynos4210_init(get_system_memory());
106
+ object_initialize(&s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC);
107
+ qdev_set_parent_bus(DEVICE(&s->soc), sysbus_get_default());
108
+ object_property_set_bool(OBJECT(&s->soc), true, "realized",
109
+ &error_fatal);
110
111
return s;
112
}
67
}
113
@@ -XXX,XX +XXX,XX @@ static void smdkc210_init(MachineState *machine)
68
114
EXYNOS4_BOARD_SMDKC210);
69
/*
115
70
- * Return the effective value of HCR_EL2.
116
lan9215_init(SMDK_LAN9118_BASE_ADDR,
71
+ * Return the effective value of HCR_EL2, at the given security state.
117
- qemu_irq_invert(s->soc->irq_table[exynos4210_get_irq(37, 1)]));
72
* Bits that are not included here:
118
+ qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)]));
73
* RW (read from SCR_EL3.RW as needed)
119
arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo);
74
*/
75
-uint64_t arm_hcr_el2_eff(CPUARMState *env)
76
+uint64_t arm_hcr_el2_eff_secstate(CPUARMState *env, bool secure)
77
{
78
uint64_t ret = env->cp15.hcr_el2;
79
80
- if (!arm_is_el2_enabled(env)) {
81
+ if (!arm_is_el2_enabled_secstate(env, secure)) {
82
/*
83
* "This register has no effect if EL2 is not enabled in the
84
* current Security state". This is ARMv8.4-SecEL2 speak for
85
@@ -XXX,XX +XXX,XX @@ uint64_t arm_hcr_el2_eff(CPUARMState *env)
86
return ret;
120
}
87
}
121
88
89
+uint64_t arm_hcr_el2_eff(CPUARMState *env)
90
+{
91
+ return arm_hcr_el2_eff_secstate(env, arm_is_secure_below_el3(env));
92
+}
93
+
94
/*
95
* Corresponds to ARM pseudocode function ELIsInHost().
96
*/
122
--
97
--
123
2.20.1
98
2.25.1
124
125
diff view generated by jsdifflib
New patch
[PULL 18/28] target/arm: Hoist read of *is_secure in S1_ptw_translate
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Rename the argument to is_secure_ptr, and introduce a
4
local variable is_secure with the value. We only write
5
back to the pointer toward the end of the function.
6
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20221001162318.153420-15-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/ptw.c | 22 ++++++++++++----------
13
1 file changed, 12 insertions(+), 10 deletions(-)
14
15
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/ptw.c
18
+++ b/target/arm/ptw.c
19
@@ -XXX,XX +XXX,XX @@ static bool ptw_attrs_are_device(CPUARMState *env, ARMCacheAttrs cacheattrs)
20
21
/* Translate a S1 pagetable walk through S2 if needed. */
22
static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
23
- hwaddr addr, bool *is_secure,
24
+ hwaddr addr, bool *is_secure_ptr,
25
ARMMMUFaultInfo *fi)
26
{
27
- ARMMMUIdx s2_mmu_idx = *is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
28
+ bool is_secure = *is_secure_ptr;
29
+ ARMMMUIdx s2_mmu_idx = is_secure ? ARMMMUIdx_Stage2_S : ARMMMUIdx_Stage2;
30
31
if (arm_mmu_idx_is_stage1_of_2(mmu_idx) &&
32
- !regime_translation_disabled(env, s2_mmu_idx, *is_secure)) {
33
+ !regime_translation_disabled(env, s2_mmu_idx, is_secure)) {
34
GetPhysAddrResult s2 = {};
35
int ret;
36
37
ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx,
38
- *is_secure, false, &s2, fi);
39
+ is_secure, false, &s2, fi);
40
if (ret) {
41
assert(fi->type != ARMFault_None);
42
fi->s2addr = addr;
43
fi->stage2 = true;
44
fi->s1ptw = true;
45
- fi->s1ns = !*is_secure;
46
+ fi->s1ns = !is_secure;
47
return ~0;
48
}
49
if ((arm_hcr_el2_eff(env) & HCR_PTW) &&
50
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
51
fi->s2addr = addr;
52
fi->stage2 = true;
53
fi->s1ptw = true;
54
- fi->s1ns = !*is_secure;
55
+ fi->s1ns = !is_secure;
56
return ~0;
57
}
58
59
if (arm_is_secure_below_el3(env)) {
60
/* Check if page table walk is to secure or non-secure PA space. */
61
- if (*is_secure) {
62
- *is_secure = !(env->cp15.vstcr_el2 & VSTCR_SW);
63
+ if (is_secure) {
64
+ is_secure = !(env->cp15.vstcr_el2 & VSTCR_SW);
65
} else {
66
- *is_secure = !(env->cp15.vtcr_el2 & VTCR_NSW);
67
+ is_secure = !(env->cp15.vtcr_el2 & VTCR_NSW);
68
}
69
+ *is_secure_ptr = is_secure;
70
} else {
71
- assert(!*is_secure);
72
+ assert(!is_secure);
73
}
74
75
addr = s2.phys;
76
--
77
2.25.1
diff view generated by jsdifflib
New patch
[PULL 19/28] target/arm: Remove env argument from combined_attrs_fwb
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
This value is unused.
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20221001162318.153420-16-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/ptw.c | 5 ++---
11
1 file changed, 2 insertions(+), 3 deletions(-)
12
13
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/ptw.c
16
+++ b/target/arm/ptw.c
17
@@ -XXX,XX +XXX,XX @@ static uint8_t force_cacheattr_nibble_wb(uint8_t attr)
18
* s1 and s2 for the HCR_EL2.FWB == 1 case, returning the
19
* combined attributes in MAIR_EL1 format.
20
*/
21
-static uint8_t combined_attrs_fwb(CPUARMState *env,
22
- ARMCacheAttrs s1, ARMCacheAttrs s2)
23
+static uint8_t combined_attrs_fwb(ARMCacheAttrs s1, ARMCacheAttrs s2)
24
{
25
switch (s2.attrs) {
26
case 7:
27
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *env,
28
29
/* Combine memory type and cacheability attributes */
30
if (arm_hcr_el2_eff(env) & HCR_FWB) {
31
- ret.attrs = combined_attrs_fwb(env, s1, s2);
32
+ ret.attrs = combined_attrs_fwb(s1, s2);
33
} else {
34
ret.attrs = combined_attrs_nofwb(env, s1, s2);
35
}
36
--
37
2.25.1
diff view generated by jsdifflib
New patch
[PULL 20/28] target/arm: Pass HCR to attribute subroutines.
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
These subroutines did not need ENV for anything except
4
retrieving the effective value of HCR anyway.
5
6
We have computed the effective value of HCR in the callers,
7
and this will be especially important for interpreting HCR
8
in a non-current security state.
9
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20221001162318.153420-17-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
target/arm/ptw.c | 30 +++++++++++++++++-------------
16
1 file changed, 17 insertions(+), 13 deletions(-)
17
18
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/ptw.c
21
+++ b/target/arm/ptw.c
22
@@ -XXX,XX +XXX,XX @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx,
23
return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
24
}
25
26
-static bool ptw_attrs_are_device(CPUARMState *env, ARMCacheAttrs cacheattrs)
27
+static bool ptw_attrs_are_device(uint64_t hcr, ARMCacheAttrs cacheattrs)
28
{
29
/*
30
* For an S1 page table walk, the stage 1 attributes are always
31
@@ -XXX,XX +XXX,XX @@ static bool ptw_attrs_are_device(CPUARMState *env, ARMCacheAttrs cacheattrs)
32
* when cacheattrs.attrs bit [2] is 0.
33
*/
34
assert(cacheattrs.is_s2_format);
35
- if (arm_hcr_el2_eff(env) & HCR_FWB) {
36
+ if (hcr & HCR_FWB) {
37
return (cacheattrs.attrs & 0x4) == 0;
38
} else {
39
return (cacheattrs.attrs & 0xc) == 0;
40
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
41
if (arm_mmu_idx_is_stage1_of_2(mmu_idx) &&
42
!regime_translation_disabled(env, s2_mmu_idx, is_secure)) {
43
GetPhysAddrResult s2 = {};
44
+ uint64_t hcr;
45
int ret;
46
47
ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx,
48
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
49
fi->s1ns = !is_secure;
50
return ~0;
51
}
52
- if ((arm_hcr_el2_eff(env) & HCR_PTW) &&
53
- ptw_attrs_are_device(env, s2.cacheattrs)) {
54
+
55
+ hcr = arm_hcr_el2_eff(env);
56
+ if ((hcr & HCR_PTW) && ptw_attrs_are_device(hcr, s2.cacheattrs)) {
57
/*
58
* PTW set and S1 walk touched S2 Device memory:
59
* generate Permission fault.
60
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
61
* ref: shared/translation/attrs/S2AttrDecode()
62
* .../S2ConvertAttrsHints()
63
*/
64
-static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs)
65
+static uint8_t convert_stage2_attrs(uint64_t hcr, uint8_t s2attrs)
66
{
67
uint8_t hiattr = extract32(s2attrs, 2, 2);
68
uint8_t loattr = extract32(s2attrs, 0, 2);
69
uint8_t hihint = 0, lohint = 0;
70
71
if (hiattr != 0) { /* normal memory */
72
- if (arm_hcr_el2_eff(env) & HCR_CD) { /* cache disabled */
73
+ if (hcr & HCR_CD) { /* cache disabled */
74
hiattr = loattr = 1; /* non-cacheable */
75
} else {
76
if (hiattr != 1) { /* Write-through or write-back */
77
@@ -XXX,XX +XXX,XX @@ static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2)
78
* s1 and s2 for the HCR_EL2.FWB == 0 case, returning the
79
* combined attributes in MAIR_EL1 format.
80
*/
81
-static uint8_t combined_attrs_nofwb(CPUARMState *env,
82
+static uint8_t combined_attrs_nofwb(uint64_t hcr,
83
ARMCacheAttrs s1, ARMCacheAttrs s2)
84
{
85
uint8_t s1lo, s2lo, s1hi, s2hi, s2_mair_attrs, ret_attrs;
86
87
- s2_mair_attrs = convert_stage2_attrs(env, s2.attrs);
88
+ s2_mair_attrs = convert_stage2_attrs(hcr, s2.attrs);
89
90
s1lo = extract32(s1.attrs, 0, 4);
91
s2lo = extract32(s2_mair_attrs, 0, 4);
92
@@ -XXX,XX +XXX,XX @@ static uint8_t combined_attrs_fwb(ARMCacheAttrs s1, ARMCacheAttrs s2)
93
* @s1: Attributes from stage 1 walk
94
* @s2: Attributes from stage 2 walk
95
*/
96
-static ARMCacheAttrs combine_cacheattrs(CPUARMState *env,
97
+static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
98
ARMCacheAttrs s1, ARMCacheAttrs s2)
99
{
100
ARMCacheAttrs ret;
101
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(CPUARMState *env,
102
}
103
104
/* Combine memory type and cacheability attributes */
105
- if (arm_hcr_el2_eff(env) & HCR_FWB) {
106
+ if (hcr & HCR_FWB) {
107
ret.attrs = combined_attrs_fwb(s1, s2);
108
} else {
109
- ret.attrs = combined_attrs_nofwb(env, s1, s2);
110
+ ret.attrs = combined_attrs_nofwb(hcr, s1, s2);
111
}
112
113
/*
114
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
115
ARMCacheAttrs cacheattrs1;
116
ARMMMUIdx s2_mmu_idx;
117
bool is_el0;
118
+ uint64_t hcr;
119
120
ret = get_phys_addr_with_secure(env, address, access_type,
121
s1_mmu_idx, is_secure, result, fi);
122
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
123
}
124
125
/* Combine the S1 and S2 cache attributes. */
126
- if (arm_hcr_el2_eff(env) & HCR_DC) {
127
+ hcr = arm_hcr_el2_eff(env);
128
+ if (hcr & HCR_DC) {
129
/*
130
* HCR.DC forces the first stage attributes to
131
* Normal Non-Shareable,
132
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
133
}
134
cacheattrs1.shareability = 0;
135
}
136
- result->cacheattrs = combine_cacheattrs(env, cacheattrs1,
137
+ result->cacheattrs = combine_cacheattrs(hcr, cacheattrs1,
138
result->cacheattrs);
139
140
/*
141
--
142
2.25.1
diff view generated by jsdifflib
New patch
[PULL 21/28] target/arm: Fix ATS12NSO* from S PL1
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Use arm_hcr_el2_eff_secstate instead of arm_hcr_el2_eff, so
4
that we use is_secure instead of the current security state.
5
These AT* operations have been broken since arm_hcr_el2_eff
6
gained a check for "el2 enabled" for Secure EL2.
7
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20221001162318.153420-18-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/ptw.c | 8 ++++----
14
1 file changed, 4 insertions(+), 4 deletions(-)
15
16
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/ptw.c
19
+++ b/target/arm/ptw.c
20
@@ -XXX,XX +XXX,XX @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx,
21
}
22
}
23
24
- hcr_el2 = arm_hcr_el2_eff(env);
25
+ hcr_el2 = arm_hcr_el2_eff_secstate(env, is_secure);
26
27
switch (mmu_idx) {
28
case ARMMMUIdx_Stage2:
29
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
30
return ~0;
31
}
32
33
- hcr = arm_hcr_el2_eff(env);
34
+ hcr = arm_hcr_el2_eff_secstate(env, is_secure);
35
if ((hcr & HCR_PTW) && ptw_attrs_are_device(hcr, s2.cacheattrs)) {
36
/*
37
* PTW set and S1 walk touched S2 Device memory:
38
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
39
}
40
41
/* Combine the S1 and S2 cache attributes. */
42
- hcr = arm_hcr_el2_eff(env);
43
+ hcr = arm_hcr_el2_eff_secstate(env, is_secure);
44
if (hcr & HCR_DC) {
45
/*
46
* HCR.DC forces the first stage attributes to
47
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
48
result->page_size = TARGET_PAGE_SIZE;
49
50
/* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
51
- hcr = arm_hcr_el2_eff(env);
52
+ hcr = arm_hcr_el2_eff_secstate(env, is_secure);
53
result->cacheattrs.shareability = 0;
54
result->cacheattrs.is_s2_format = false;
55
if (hcr & HCR_DC) {
56
--
57
2.25.1
diff view generated by jsdifflib
New patch
[PULL 22/28] target/arm: Split out get_phys_addr_disabled
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20221001162318.153420-19-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
target/arm/ptw.c | 138 +++++++++++++++++++++++++----------------------
9
1 file changed, 74 insertions(+), 64 deletions(-)
10
11
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/ptw.c
14
+++ b/target/arm/ptw.c
15
@@ -XXX,XX +XXX,XX @@ static ARMCacheAttrs combine_cacheattrs(uint64_t hcr,
16
return ret;
17
}
18
19
+/*
20
+ * MMU disabled. S1 addresses within aa64 translation regimes are
21
+ * still checked for bounds -- see AArch64.S1DisabledOutput().
22
+ */
23
+static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address,
24
+ MMUAccessType access_type,
25
+ ARMMMUIdx mmu_idx, bool is_secure,
26
+ GetPhysAddrResult *result,
27
+ ARMMMUFaultInfo *fi)
28
+{
29
+ uint64_t hcr;
30
+ uint8_t memattr;
31
+
32
+ if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) {
33
+ int r_el = regime_el(env, mmu_idx);
34
+ if (arm_el_is_aa64(env, r_el)) {
35
+ int pamax = arm_pamax(env_archcpu(env));
36
+ uint64_t tcr = env->cp15.tcr_el[r_el];
37
+ int addrtop, tbi;
38
+
39
+ tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
40
+ if (access_type == MMU_INST_FETCH) {
41
+ tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx);
42
+ }
43
+ tbi = (tbi >> extract64(address, 55, 1)) & 1;
44
+ addrtop = (tbi ? 55 : 63);
45
+
46
+ if (extract64(address, pamax, addrtop - pamax + 1) != 0) {
47
+ fi->type = ARMFault_AddressSize;
48
+ fi->level = 0;
49
+ fi->stage2 = false;
50
+ return 1;
51
+ }
52
+
53
+ /*
54
+ * When TBI is disabled, we've just validated that all of the
55
+ * bits above PAMax are zero, so logically we only need to
56
+ * clear the top byte for TBI. But it's clearer to follow
57
+ * the pseudocode set of addrdesc.paddress.
58
+ */
59
+ address = extract64(address, 0, 52);
60
+ }
61
+ }
62
+
63
+ result->phys = address;
64
+ result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
65
+ result->page_size = TARGET_PAGE_SIZE;
66
+
67
+ /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
68
+ hcr = arm_hcr_el2_eff_secstate(env, is_secure);
69
+ result->cacheattrs.shareability = 0;
70
+ result->cacheattrs.is_s2_format = false;
71
+ if (hcr & HCR_DC) {
72
+ if (hcr & HCR_DCT) {
73
+ memattr = 0xf0; /* Tagged, Normal, WB, RWA */
74
+ } else {
75
+ memattr = 0xff; /* Normal, WB, RWA */
76
+ }
77
+ } else if (access_type == MMU_INST_FETCH) {
78
+ if (regime_sctlr(env, mmu_idx) & SCTLR_I) {
79
+ memattr = 0xee; /* Normal, WT, RA, NT */
80
+ } else {
81
+ memattr = 0x44; /* Normal, NC, No */
82
+ }
83
+ result->cacheattrs.shareability = 2; /* outer sharable */
84
+ } else {
85
+ memattr = 0x00; /* Device, nGnRnE */
86
+ }
87
+ result->cacheattrs.attrs = memattr;
88
+ return 0;
89
+}
90
+
91
bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
92
MMUAccessType access_type, ARMMMUIdx mmu_idx,
93
bool is_secure, GetPhysAddrResult *result,
94
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
95
/* Definitely a real MMU, not an MPU */
96
97
if (regime_translation_disabled(env, mmu_idx, is_secure)) {
98
- uint64_t hcr;
99
- uint8_t memattr;
100
-
101
- /*
102
- * MMU disabled. S1 addresses within aa64 translation regimes are
103
- * still checked for bounds -- see AArch64.TranslateAddressS1Off.
104
- */
105
- if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) {
106
- int r_el = regime_el(env, mmu_idx);
107
- if (arm_el_is_aa64(env, r_el)) {
108
- int pamax = arm_pamax(env_archcpu(env));
109
- uint64_t tcr = env->cp15.tcr_el[r_el];
110
- int addrtop, tbi;
111
-
112
- tbi = aa64_va_parameter_tbi(tcr, mmu_idx);
113
- if (access_type == MMU_INST_FETCH) {
114
- tbi &= ~aa64_va_parameter_tbid(tcr, mmu_idx);
115
- }
116
- tbi = (tbi >> extract64(address, 55, 1)) & 1;
117
- addrtop = (tbi ? 55 : 63);
118
-
119
- if (extract64(address, pamax, addrtop - pamax + 1) != 0) {
120
- fi->type = ARMFault_AddressSize;
121
- fi->level = 0;
122
- fi->stage2 = false;
123
- return 1;
124
- }
125
-
126
- /*
127
- * When TBI is disabled, we've just validated that all of the
128
- * bits above PAMax are zero, so logically we only need to
129
- * clear the top byte for TBI. But it's clearer to follow
130
- * the pseudocode set of addrdesc.paddress.
131
- */
132
- address = extract64(address, 0, 52);
133
- }
134
- }
135
- result->phys = address;
136
- result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
137
- result->page_size = TARGET_PAGE_SIZE;
138
-
139
- /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
140
- hcr = arm_hcr_el2_eff_secstate(env, is_secure);
141
- result->cacheattrs.shareability = 0;
142
- result->cacheattrs.is_s2_format = false;
143
- if (hcr & HCR_DC) {
144
- if (hcr & HCR_DCT) {
145
- memattr = 0xf0; /* Tagged, Normal, WB, RWA */
146
- } else {
147
- memattr = 0xff; /* Normal, WB, RWA */
148
- }
149
- } else if (access_type == MMU_INST_FETCH) {
150
- if (regime_sctlr(env, mmu_idx) & SCTLR_I) {
151
- memattr = 0xee; /* Normal, WT, RA, NT */
152
- } else {
153
- memattr = 0x44; /* Normal, NC, No */
154
- }
155
- result->cacheattrs.shareability = 2; /* outer sharable */
156
- } else {
157
- memattr = 0x00; /* Device, nGnRnE */
158
- }
159
- result->cacheattrs.attrs = memattr;
160
- return 0;
161
+ return get_phys_addr_disabled(env, address, access_type, mmu_idx,
162
+ is_secure, result, fi);
163
}
164
-
165
if (regime_using_lpae_format(env, mmu_idx)) {
166
return get_phys_addr_lpae(env, address, access_type, mmu_idx,
167
is_secure, false, result, fi);
168
--
169
2.25.1
diff view generated by jsdifflib
New patch
[PULL 23/28] target/arm: Fix cacheattr in get_phys_addr_disabled
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Do not apply memattr or shareability for Stage2 translations.
4
Make sure to apply HCR_{DC,DCT} only to Regime_EL10, per the
5
pseudocode in AArch64.S1DisabledOutput.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20221001162318.153420-20-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/ptw.c | 48 +++++++++++++++++++++++++-----------------------
13
1 file changed, 25 insertions(+), 23 deletions(-)
14
15
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/ptw.c
18
+++ b/target/arm/ptw.c
19
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address,
20
GetPhysAddrResult *result,
21
ARMMMUFaultInfo *fi)
22
{
23
- uint64_t hcr;
24
- uint8_t memattr;
25
+ uint8_t memattr = 0x00; /* Device nGnRnE */
26
+ uint8_t shareability = 0; /* non-sharable */
27
28
if (mmu_idx != ARMMMUIdx_Stage2 && mmu_idx != ARMMMUIdx_Stage2_S) {
29
int r_el = regime_el(env, mmu_idx);
30
+
31
if (arm_el_is_aa64(env, r_el)) {
32
int pamax = arm_pamax(env_archcpu(env));
33
uint64_t tcr = env->cp15.tcr_el[r_el];
34
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address,
35
*/
36
address = extract64(address, 0, 52);
37
}
38
+
39
+ /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
40
+ if (r_el == 1) {
41
+ uint64_t hcr = arm_hcr_el2_eff_secstate(env, is_secure);
42
+ if (hcr & HCR_DC) {
43
+ if (hcr & HCR_DCT) {
44
+ memattr = 0xf0; /* Tagged, Normal, WB, RWA */
45
+ } else {
46
+ memattr = 0xff; /* Normal, WB, RWA */
47
+ }
48
+ }
49
+ }
50
+ if (memattr == 0 && access_type == MMU_INST_FETCH) {
51
+ if (regime_sctlr(env, mmu_idx) & SCTLR_I) {
52
+ memattr = 0xee; /* Normal, WT, RA, NT */
53
+ } else {
54
+ memattr = 0x44; /* Normal, NC, No */
55
+ }
56
+ shareability = 2; /* outer sharable */
57
+ }
58
+ result->cacheattrs.is_s2_format = false;
59
}
60
61
result->phys = address;
62
result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
63
result->page_size = TARGET_PAGE_SIZE;
64
-
65
- /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
66
- hcr = arm_hcr_el2_eff_secstate(env, is_secure);
67
- result->cacheattrs.shareability = 0;
68
- result->cacheattrs.is_s2_format = false;
69
- if (hcr & HCR_DC) {
70
- if (hcr & HCR_DCT) {
71
- memattr = 0xf0; /* Tagged, Normal, WB, RWA */
72
- } else {
73
- memattr = 0xff; /* Normal, WB, RWA */
74
- }
75
- } else if (access_type == MMU_INST_FETCH) {
76
- if (regime_sctlr(env, mmu_idx) & SCTLR_I) {
77
- memattr = 0xee; /* Normal, WT, RA, NT */
78
- } else {
79
- memattr = 0x44; /* Normal, NC, No */
80
- }
81
- result->cacheattrs.shareability = 2; /* outer sharable */
82
- } else {
83
- memattr = 0x00; /* Device, nGnRnE */
84
- }
85
+ result->cacheattrs.shareability = shareability;
86
result->cacheattrs.attrs = memattr;
87
return 0;
88
}
89
--
90
2.25.1
diff view generated by jsdifflib
New patch
[PULL 24/28] target/arm: Use tlb_set_page_full
1
From: Richard Henderson <richard.henderson@linaro.org>
1
2
3
Adjust GetPhysAddrResult to fill in CPUTLBEntryFull,
4
so that it may be passed directly to tlb_set_page_full.
5
6
The change is large, but mostly mechanical. The major
7
non-mechanical change is page_size -> lg_page_size.
8
Most of the time this is obvious, and is related to
9
TARGET_PAGE_BITS.
10
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Message-id: 20221001162318.153420-21-richard.henderson@linaro.org
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
target/arm/internals.h | 5 +-
17
target/arm/helper.c | 12 +--
18
target/arm/m_helper.c | 20 ++---
19
target/arm/ptw.c | 179 ++++++++++++++++++++--------------------
20
target/arm/tlb_helper.c | 9 +-
21
5 files changed, 111 insertions(+), 114 deletions(-)
22
23
diff --git a/target/arm/internals.h b/target/arm/internals.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/internals.h
26
+++ b/target/arm/internals.h
27
@@ -XXX,XX +XXX,XX @@ typedef struct ARMCacheAttrs {
28
29
/* Fields that are valid upon success. */
30
typedef struct GetPhysAddrResult {
31
- hwaddr phys;
32
- target_ulong page_size;
33
- int prot;
34
- MemTxAttrs attrs;
35
+ CPUTLBEntryFull f;
36
ARMCacheAttrs cacheattrs;
37
} GetPhysAddrResult;
38
39
diff --git a/target/arm/helper.c b/target/arm/helper.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/target/arm/helper.c
42
+++ b/target/arm/helper.c
43
@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
44
/* Create a 64-bit PAR */
45
par64 = (1 << 11); /* LPAE bit always set */
46
if (!ret) {
47
- par64 |= res.phys & ~0xfffULL;
48
- if (!res.attrs.secure) {
49
+ par64 |= res.f.phys_addr & ~0xfffULL;
50
+ if (!res.f.attrs.secure) {
51
par64 |= (1 << 9); /* NS */
52
}
53
par64 |= (uint64_t)res.cacheattrs.attrs << 56; /* ATTR */
54
@@ -XXX,XX +XXX,XX @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t value,
55
*/
56
if (!ret) {
57
/* We do not set any attribute bits in the PAR */
58
- if (res.page_size == (1 << 24)
59
+ if (res.f.lg_page_size == 24
60
&& arm_feature(env, ARM_FEATURE_V7)) {
61
- par64 = (res.phys & 0xff000000) | (1 << 1);
62
+ par64 = (res.f.phys_addr & 0xff000000) | (1 << 1);
63
} else {
64
- par64 = res.phys & 0xfffff000;
65
+ par64 = res.f.phys_addr & 0xfffff000;
66
}
67
- if (!res.attrs.secure) {
68
+ if (!res.f.attrs.secure) {
69
par64 |= (1 << 9); /* NS */
70
}
71
} else {
72
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
73
index XXXXXXX..XXXXXXX 100644
74
--- a/target/arm/m_helper.c
75
+++ b/target/arm/m_helper.c
76
@@ -XXX,XX +XXX,XX @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value,
77
}
78
goto pend_fault;
79
}
80
- address_space_stl_le(arm_addressspace(cs, res.attrs), res.phys, value,
81
- res.attrs, &txres);
82
+ address_space_stl_le(arm_addressspace(cs, res.f.attrs), res.f.phys_addr,
83
+ value, res.f.attrs, &txres);
84
if (txres != MEMTX_OK) {
85
/* BusFault trying to write the data */
86
if (mode == STACK_LAZYFP) {
87
@@ -XXX,XX +XXX,XX @@ static bool v7m_stack_read(ARMCPU *cpu, uint32_t *dest, uint32_t addr,
88
goto pend_fault;
89
}
90
91
- value = address_space_ldl(arm_addressspace(cs, res.attrs), res.phys,
92
- res.attrs, &txres);
93
+ value = address_space_ldl(arm_addressspace(cs, res.f.attrs),
94
+ res.f.phys_addr, res.f.attrs, &txres);
95
if (txres != MEMTX_OK) {
96
/* BusFault trying to read the data */
97
qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.UNSTKERR\n");
98
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool secure,
99
qemu_log_mask(CPU_LOG_INT, "...really MemManage with CFSR.IACCVIOL\n");
100
return false;
101
}
102
- *insn = address_space_lduw_le(arm_addressspace(cs, res.attrs), res.phys,
103
- res.attrs, &txres);
104
+ *insn = address_space_lduw_le(arm_addressspace(cs, res.f.attrs),
105
+ res.f.phys_addr, res.f.attrs, &txres);
106
if (txres != MEMTX_OK) {
107
env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_IBUSERR_MASK;
108
armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
109
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx,
110
}
111
return false;
112
}
113
- value = address_space_ldl(arm_addressspace(cs, res.attrs), res.phys,
114
- res.attrs, &txres);
115
+ value = address_space_ldl(arm_addressspace(cs, res.f.attrs),
116
+ res.f.phys_addr, res.f.attrs, &txres);
117
if (txres != MEMTX_OK) {
118
/* BusFault trying to read the data */
119
qemu_log_mask(CPU_LOG_INT,
120
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op)
121
} else {
122
mrvalid = true;
123
}
124
- r = res.prot & PAGE_READ;
125
- rw = res.prot & PAGE_WRITE;
126
+ r = res.f.prot & PAGE_READ;
127
+ rw = res.f.prot & PAGE_WRITE;
128
} else {
129
r = false;
130
rw = false;
131
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
132
index XXXXXXX..XXXXXXX 100644
133
--- a/target/arm/ptw.c
134
+++ b/target/arm/ptw.c
135
@@ -XXX,XX +XXX,XX @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx,
136
assert(!is_secure);
137
}
138
139
- addr = s2.phys;
140
+ addr = s2.f.phys_addr;
141
}
142
return addr;
143
}
144
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
145
/* 1Mb section. */
146
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
147
ap = (desc >> 10) & 3;
148
- result->page_size = 1024 * 1024;
149
+ result->f.lg_page_size = 20; /* 1MB */
150
} else {
151
/* Lookup l2 entry. */
152
if (type == 1) {
153
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
154
case 1: /* 64k page. */
155
phys_addr = (desc & 0xffff0000) | (address & 0xffff);
156
ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
157
- result->page_size = 0x10000;
158
+ result->f.lg_page_size = 16;
159
break;
160
case 2: /* 4k page. */
161
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
162
ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
163
- result->page_size = 0x1000;
164
+ result->f.lg_page_size = 12;
165
break;
166
case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */
167
if (type == 1) {
168
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
169
if (arm_feature(env, ARM_FEATURE_XSCALE)
170
|| arm_feature(env, ARM_FEATURE_V6)) {
171
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
172
- result->page_size = 0x1000;
173
+ result->f.lg_page_size = 12;
174
} else {
175
/*
176
* UNPREDICTABLE in ARMv5; we choose to take a
177
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
178
}
179
} else {
180
phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
181
- result->page_size = 0x400;
182
+ result->f.lg_page_size = 10;
183
}
184
ap = (desc >> 4) & 3;
185
break;
186
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
187
g_assert_not_reached();
188
}
189
}
190
- result->prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
191
- result->prot |= result->prot ? PAGE_EXEC : 0;
192
- if (!(result->prot & (1 << access_type))) {
193
+ result->f.prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
194
+ result->f.prot |= result->f.prot ? PAGE_EXEC : 0;
195
+ if (!(result->f.prot & (1 << access_type))) {
196
/* Access permission fault. */
197
fi->type = ARMFault_Permission;
198
goto do_fault;
199
}
200
- result->phys = phys_addr;
201
+ result->f.phys_addr = phys_addr;
202
return false;
203
do_fault:
204
fi->domain = domain;
205
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
206
phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
207
phys_addr |= (uint64_t)extract32(desc, 20, 4) << 32;
208
phys_addr |= (uint64_t)extract32(desc, 5, 4) << 36;
209
- result->page_size = 0x1000000;
210
+ result->f.lg_page_size = 24; /* 16MB */
211
} else {
212
/* Section. */
213
phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
214
- result->page_size = 0x100000;
215
+ result->f.lg_page_size = 20; /* 1MB */
216
}
217
ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
218
xn = desc & (1 << 4);
219
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
220
case 1: /* 64k page. */
221
phys_addr = (desc & 0xffff0000) | (address & 0xffff);
222
xn = desc & (1 << 15);
223
- result->page_size = 0x10000;
224
+ result->f.lg_page_size = 16;
225
break;
226
case 2: case 3: /* 4k page. */
227
phys_addr = (desc & 0xfffff000) | (address & 0xfff);
228
xn = desc & 1;
229
- result->page_size = 0x1000;
230
+ result->f.lg_page_size = 12;
231
break;
232
default:
233
/* Never happens, but compiler isn't smart enough to tell. */
234
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
235
}
236
}
237
if (domain_prot == 3) {
238
- result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
239
+ result->f.prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
240
} else {
241
if (pxn && !regime_is_user(env, mmu_idx)) {
242
xn = 1;
243
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
244
fi->type = ARMFault_AccessFlag;
245
goto do_fault;
246
}
247
- result->prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
248
+ result->f.prot = simple_ap_to_rw_prot(env, mmu_idx, ap >> 1);
249
} else {
250
- result->prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
251
+ result->f.prot = ap_to_rw_prot(env, mmu_idx, ap, domain_prot);
252
}
253
- if (result->prot && !xn) {
254
- result->prot |= PAGE_EXEC;
255
+ if (result->f.prot && !xn) {
256
+ result->f.prot |= PAGE_EXEC;
257
}
258
- if (!(result->prot & (1 << access_type))) {
259
+ if (!(result->f.prot & (1 << access_type))) {
260
/* Access permission fault. */
261
fi->type = ARMFault_Permission;
262
goto do_fault;
263
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
264
* the CPU doesn't support TZ or this is a non-secure translation
265
* regime, because the attribute will already be non-secure.
266
*/
267
- result->attrs.secure = false;
268
+ result->f.attrs.secure = false;
269
}
270
- result->phys = phys_addr;
271
+ result->f.phys_addr = phys_addr;
272
return false;
273
do_fault:
274
fi->domain = domain;
275
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
276
if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
277
ns = mmu_idx == ARMMMUIdx_Stage2;
278
xn = extract32(attrs, 11, 2);
279
- result->prot = get_S2prot(env, ap, xn, s1_is_el0);
280
+ result->f.prot = get_S2prot(env, ap, xn, s1_is_el0);
281
} else {
282
ns = extract32(attrs, 3, 1);
283
xn = extract32(attrs, 12, 1);
284
pxn = extract32(attrs, 11, 1);
285
- result->prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
286
+ result->f.prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
287
}
288
289
fault_type = ARMFault_Permission;
290
- if (!(result->prot & (1 << access_type))) {
291
+ if (!(result->f.prot & (1 << access_type))) {
292
goto do_fault;
293
}
294
295
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
296
* the CPU doesn't support TZ or this is a non-secure translation
297
* regime, because the attribute will already be non-secure.
298
*/
299
- result->attrs.secure = false;
300
+ result->f.attrs.secure = false;
301
}
302
/* When in aarch64 mode, and BTI is enabled, remember GP in the IOTLB. */
303
if (aarch64 && guarded && cpu_isar_feature(aa64_bti, cpu)) {
304
- arm_tlb_bti_gp(&result->attrs) = true;
305
+ arm_tlb_bti_gp(&result->f.attrs) = true;
306
}
307
308
if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
309
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
310
result->cacheattrs.shareability = extract32(attrs, 6, 2);
311
}
312
313
- result->phys = descaddr;
314
- result->page_size = page_size;
315
+ result->f.phys_addr = descaddr;
316
+ result->f.lg_page_size = ctz64(page_size);
317
return false;
318
319
do_fault:
320
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
321
322
if (regime_translation_disabled(env, mmu_idx, is_secure)) {
323
/* MPU disabled. */
324
- result->phys = address;
325
- result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
326
+ result->f.phys_addr = address;
327
+ result->f.prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
328
return false;
329
}
330
331
- result->phys = address;
332
+ result->f.phys_addr = address;
333
for (n = 7; n >= 0; n--) {
334
base = env->cp15.c6_region[n];
335
if ((base & 1) == 0) {
336
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
337
fi->level = 1;
338
return true;
339
}
340
- result->prot = PAGE_READ | PAGE_WRITE;
341
+ result->f.prot = PAGE_READ | PAGE_WRITE;
342
break;
343
case 2:
344
- result->prot = PAGE_READ;
345
+ result->f.prot = PAGE_READ;
346
if (!is_user) {
347
- result->prot |= PAGE_WRITE;
348
+ result->f.prot |= PAGE_WRITE;
349
}
350
break;
351
case 3:
352
- result->prot = PAGE_READ | PAGE_WRITE;
353
+ result->f.prot = PAGE_READ | PAGE_WRITE;
354
break;
355
case 5:
356
if (is_user) {
357
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
358
fi->level = 1;
359
return true;
360
}
361
- result->prot = PAGE_READ;
362
+ result->f.prot = PAGE_READ;
363
break;
364
case 6:
365
- result->prot = PAGE_READ;
366
+ result->f.prot = PAGE_READ;
367
break;
368
default:
369
/* Bad permission. */
370
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
371
fi->level = 1;
372
return true;
373
}
374
- result->prot |= PAGE_EXEC;
375
+ result->f.prot |= PAGE_EXEC;
376
return false;
377
}
378
379
static void get_phys_addr_pmsav7_default(CPUARMState *env, ARMMMUIdx mmu_idx,
380
- int32_t address, int *prot)
381
+ int32_t address, uint8_t *prot)
382
{
383
if (!arm_feature(env, ARM_FEATURE_M)) {
384
*prot = PAGE_READ | PAGE_WRITE;
385
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
386
int n;
387
bool is_user = regime_is_user(env, mmu_idx);
388
389
- result->phys = address;
390
- result->page_size = TARGET_PAGE_SIZE;
391
- result->prot = 0;
392
+ result->f.phys_addr = address;
393
+ result->f.lg_page_size = TARGET_PAGE_BITS;
394
+ result->f.prot = 0;
395
396
if (regime_translation_disabled(env, mmu_idx, secure) ||
397
m_is_ppb_region(env, address)) {
398
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
399
* which always does a direct read using address_space_ldl(), rather
400
* than going via this function, so we don't need to check that here.
401
*/
402
- get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot);
403
+ get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->f.prot);
404
} else { /* MPU enabled */
405
for (n = (int)cpu->pmsav7_dregion - 1; n >= 0; n--) {
406
/* region search */
407
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
408
if (ranges_overlap(base, rmask,
409
address & TARGET_PAGE_MASK,
410
TARGET_PAGE_SIZE)) {
411
- result->page_size = 1;
412
+ result->f.lg_page_size = 0;
413
}
414
continue;
415
}
416
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
417
continue;
418
}
419
if (rsize < TARGET_PAGE_BITS) {
420
- result->page_size = 1 << rsize;
421
+ result->f.lg_page_size = rsize;
422
}
423
break;
424
}
425
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
426
fi->type = ARMFault_Background;
427
return true;
428
}
429
- get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot);
430
+ get_phys_addr_pmsav7_default(env, mmu_idx, address,
431
+ &result->f.prot);
432
} else { /* a MPU hit! */
433
uint32_t ap = extract32(env->pmsav7.dracr[n], 8, 3);
434
uint32_t xn = extract32(env->pmsav7.dracr[n], 12, 1);
435
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
436
case 5:
437
break; /* no access */
438
case 3:
439
- result->prot |= PAGE_WRITE;
440
+ result->f.prot |= PAGE_WRITE;
441
/* fall through */
442
case 2:
443
case 6:
444
- result->prot |= PAGE_READ | PAGE_EXEC;
445
+ result->f.prot |= PAGE_READ | PAGE_EXEC;
446
break;
447
case 7:
448
/* for v7M, same as 6; for R profile a reserved value */
449
if (arm_feature(env, ARM_FEATURE_M)) {
450
- result->prot |= PAGE_READ | PAGE_EXEC;
451
+ result->f.prot |= PAGE_READ | PAGE_EXEC;
452
break;
453
}
454
/* fall through */
455
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
456
case 1:
457
case 2:
458
case 3:
459
- result->prot |= PAGE_WRITE;
460
+ result->f.prot |= PAGE_WRITE;
461
/* fall through */
462
case 5:
463
case 6:
464
- result->prot |= PAGE_READ | PAGE_EXEC;
465
+ result->f.prot |= PAGE_READ | PAGE_EXEC;
466
break;
467
case 7:
468
/* for v7M, same as 6; for R profile a reserved value */
469
if (arm_feature(env, ARM_FEATURE_M)) {
470
- result->prot |= PAGE_READ | PAGE_EXEC;
471
+ result->f.prot |= PAGE_READ | PAGE_EXEC;
472
break;
473
}
474
/* fall through */
475
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address,
476
477
/* execute never */
478
if (xn) {
479
- result->prot &= ~PAGE_EXEC;
480
+ result->f.prot &= ~PAGE_EXEC;
481
}
482
}
483
}
484
485
fi->type = ARMFault_Permission;
486
fi->level = 1;
487
- return !(result->prot & (1 << access_type));
488
+ return !(result->f.prot & (1 << access_type));
489
}
490
491
bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
492
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
493
uint32_t addr_page_base = address & TARGET_PAGE_MASK;
494
uint32_t addr_page_limit = addr_page_base + (TARGET_PAGE_SIZE - 1);
495
496
- result->page_size = TARGET_PAGE_SIZE;
497
- result->phys = address;
498
- result->prot = 0;
499
+ result->f.lg_page_size = TARGET_PAGE_BITS;
500
+ result->f.phys_addr = address;
501
+ result->f.prot = 0;
502
if (mregion) {
503
*mregion = -1;
504
}
505
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
506
ranges_overlap(base, limit - base + 1,
507
addr_page_base,
508
TARGET_PAGE_SIZE)) {
509
- result->page_size = 1;
510
+ result->f.lg_page_size = 0;
511
}
512
continue;
513
}
514
515
if (base > addr_page_base || limit < addr_page_limit) {
516
- result->page_size = 1;
517
+ result->f.lg_page_size = 0;
518
}
519
520
if (matchregion != -1) {
521
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
522
523
if (matchregion == -1) {
524
/* hit using the background region */
525
- get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->prot);
526
+ get_phys_addr_pmsav7_default(env, mmu_idx, address, &result->f.prot);
527
} else {
528
uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2);
529
uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1);
530
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
531
xn = 1;
532
}
533
534
- result->prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
535
- if (result->prot && !xn && !(pxn && !is_user)) {
536
- result->prot |= PAGE_EXEC;
537
+ result->f.prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
538
+ if (result->f.prot && !xn && !(pxn && !is_user)) {
539
+ result->f.prot |= PAGE_EXEC;
540
}
541
/*
542
* We don't need to look the attribute up in the MAIR0/MAIR1
543
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
544
545
fi->type = ARMFault_Permission;
546
fi->level = 1;
547
- return !(result->prot & (1 << access_type));
548
+ return !(result->f.prot & (1 << access_type));
549
}
550
551
static bool v8m_is_sau_exempt(CPUARMState *env,
552
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
553
} else {
554
fi->type = ARMFault_QEMU_SFault;
555
}
556
- result->page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
557
- result->phys = address;
558
- result->prot = 0;
559
+ result->f.lg_page_size = sattrs.subpage ? 0 : TARGET_PAGE_BITS;
560
+ result->f.phys_addr = address;
561
+ result->f.prot = 0;
562
return true;
563
}
564
} else {
565
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
566
* might downgrade a secure access to nonsecure.
567
*/
568
if (sattrs.ns) {
569
- result->attrs.secure = false;
570
+ result->f.attrs.secure = false;
571
} else if (!secure) {
572
/*
573
* NS access to S memory must fault.
574
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
575
* for M_FAKE_FSR_SFAULT in arm_v7m_cpu_do_interrupt().
576
*/
577
fi->type = ARMFault_QEMU_SFault;
578
- result->page_size = sattrs.subpage ? 1 : TARGET_PAGE_SIZE;
579
- result->phys = address;
580
- result->prot = 0;
581
+ result->f.lg_page_size = sattrs.subpage ? 0 : TARGET_PAGE_BITS;
582
+ result->f.phys_addr = address;
583
+ result->f.prot = 0;
584
return true;
585
}
586
}
587
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
588
ret = pmsav8_mpu_lookup(env, address, access_type, mmu_idx, secure,
589
result, fi, NULL);
590
if (sattrs.subpage) {
591
- result->page_size = 1;
592
+ result->f.lg_page_size = 0;
593
}
594
return ret;
595
}
596
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_disabled(CPUARMState *env, target_ulong address,
597
result->cacheattrs.is_s2_format = false;
598
}
599
600
- result->phys = address;
601
- result->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
602
- result->page_size = TARGET_PAGE_SIZE;
603
+ result->f.phys_addr = address;
604
+ result->f.prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
605
+ result->f.lg_page_size = TARGET_PAGE_BITS;
606
result->cacheattrs.shareability = shareability;
607
result->cacheattrs.attrs = memattr;
608
return 0;
609
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
610
return ret;
611
}
612
613
- ipa = result->phys;
614
- ipa_secure = result->attrs.secure;
615
+ ipa = result->f.phys_addr;
616
+ ipa_secure = result->f.attrs.secure;
617
if (is_secure) {
618
/* Select TCR based on the NS bit from the S1 walk. */
619
s2walk_secure = !(ipa_secure
620
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
621
* Save the stage1 results so that we may merge
622
* prot and cacheattrs later.
623
*/
624
- s1_prot = result->prot;
625
+ s1_prot = result->f.prot;
626
cacheattrs1 = result->cacheattrs;
627
memset(result, 0, sizeof(*result));
628
629
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
630
fi->s2addr = ipa;
631
632
/* Combine the S1 and S2 perms. */
633
- result->prot &= s1_prot;
634
+ result->f.prot &= s1_prot;
635
636
/* If S2 fails, return early. */
637
if (ret) {
638
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
639
* Check if IPA translates to secure or non-secure PA space.
640
* Note that VSTCR overrides VTCR and {N}SW overrides {N}SA.
641
*/
642
- result->attrs.secure =
643
+ result->f.attrs.secure =
644
(is_secure
645
&& !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))
646
&& (ipa_secure
647
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
648
* cannot upgrade an non-secure translation regime's attributes
649
* to secure.
650
*/
651
- result->attrs.secure = is_secure;
652
- result->attrs.user = regime_is_user(env, mmu_idx);
653
+ result->f.attrs.secure = is_secure;
654
+ result->f.attrs.user = regime_is_user(env, mmu_idx);
655
656
/*
657
* Fast Context Switch Extension. This doesn't exist at all in v8.
658
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
659
660
if (arm_feature(env, ARM_FEATURE_PMSA)) {
661
bool ret;
662
- result->page_size = TARGET_PAGE_SIZE;
663
+ result->f.lg_page_size = TARGET_PAGE_BITS;
664
665
if (arm_feature(env, ARM_FEATURE_V8)) {
666
/* PMSAv8 */
667
@@ -XXX,XX +XXX,XX @@ bool get_phys_addr_with_secure(CPUARMState *env, target_ulong address,
668
(access_type == MMU_DATA_STORE ? "writing" : "execute"),
669
(uint32_t)address, mmu_idx,
670
ret ? "Miss" : "Hit",
671
- result->prot & PAGE_READ ? 'r' : '-',
672
- result->prot & PAGE_WRITE ? 'w' : '-',
673
- result->prot & PAGE_EXEC ? 'x' : '-');
674
+ result->f.prot & PAGE_READ ? 'r' : '-',
675
+ result->f.prot & PAGE_WRITE ? 'w' : '-',
676
+ result->f.prot & PAGE_EXEC ? 'x' : '-');
677
678
return ret;
679
}
680
@@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
681
bool ret;
682
683
ret = get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &res, &fi);
684
- *attrs = res.attrs;
685
+ *attrs = res.f.attrs;
686
687
if (ret) {
688
return -1;
689
}
690
- return res.phys;
691
+ return res.f.phys_addr;
692
}
693
diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c
694
index XXXXXXX..XXXXXXX 100644
695
--- a/target/arm/tlb_helper.c
696
+++ b/target/arm/tlb_helper.c
697
@@ -XXX,XX +XXX,XX @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
698
* target page size are handled specially, so for those we
699
* pass in the exact addresses.
700
*/
701
- if (res.page_size >= TARGET_PAGE_SIZE) {
702
- res.phys &= TARGET_PAGE_MASK;
703
+ if (res.f.lg_page_size >= TARGET_PAGE_BITS) {
704
+ res.f.phys_addr &= TARGET_PAGE_MASK;
705
address &= TARGET_PAGE_MASK;
706
}
707
/* Notice and record tagged memory. */
708
if (cpu_isar_feature(aa64_mte, cpu) && res.cacheattrs.attrs == 0xf0) {
709
- arm_tlb_mte_tagged(&res.attrs) = true;
710
+ arm_tlb_mte_tagged(&res.f.attrs) = true;
711
}
712
713
- tlb_set_page_with_attrs(cs, address, res.phys, res.attrs,
714
- res.prot, mmu_idx, res.page_size);
715
+ tlb_set_page_full(cs, mmu_idx, address, &res.f);
716
return true;
717
} else if (probe) {
718
return false;
719
--
720
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/12] arm: Rename hw/arm/arm.h to hw/arm/boot.h
[PULL 25/28] hw/arm/boot: set CPTR_EL3.ESM and SCR_EL3.EnTP2 when booting Linux with EL3
1
The header file hw/arm/arm.h now includes only declarations
1
From: Jerome Forissier <jerome.forissier@linaro.org>
2
relating to hw/arm/boot.c functionality. Rename it accordingly,
3
and adjust its header comment.
4
2
5
The bulk of this commit was created via
3
According to the Linux kernel booting.rst [1], CPTR_EL3.ESM and
6
perl -pi -e 's|hw/arm/arm.h|hw/arm/boot.h|' hw/arm/*.c include/hw/arm/*.h
4
SCR_EL3.EnTP2 must be initialized to 1 when EL3 is present and FEAT_SME
5
is advertised. This has to be taken care of when QEMU boots directly
6
into the kernel (i.e., "-M virt,secure=on -cpu max -kernel Image").
7
7
8
In a few cases we can just delete the #include:
8
Cc: qemu-stable@nongnu.org
9
hw/arm/msf2-soc.c, include/hw/arm/aspeed_soc.h and
9
Fixes: 78cb9776662a ("target/arm: Enable SME for -cpu max")
10
include/hw/arm/bcm2836.h did not require it.
10
Link: [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/arm64/booting.rst?h=v6.0#n321
11
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
12
Message-id: 20221003145641.1921467-1-jerome.forissier@linaro.org
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/arm/boot.c | 4 ++++
17
1 file changed, 4 insertions(+)
11
18
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Message-id: 20190516163857.6430-4-peter.maydell@linaro.org
16
---
17
include/hw/arm/allwinner-a10.h | 2 +-
18
include/hw/arm/aspeed_soc.h | 1 -
19
include/hw/arm/bcm2836.h | 1 -
20
include/hw/arm/{arm.h => boot.h} | 8 ++++----
21
include/hw/arm/fsl-imx25.h | 2 +-
22
include/hw/arm/fsl-imx31.h | 2 +-
23
include/hw/arm/fsl-imx6.h | 2 +-
24
include/hw/arm/fsl-imx6ul.h | 2 +-
25
include/hw/arm/fsl-imx7.h | 2 +-
26
include/hw/arm/virt.h | 2 +-
27
include/hw/arm/xlnx-versal.h | 2 +-
28
include/hw/arm/xlnx-zynqmp.h | 2 +-
29
hw/arm/armsse.c | 2 +-
30
hw/arm/armv7m.c | 2 +-
31
hw/arm/aspeed.c | 2 +-
32
hw/arm/boot.c | 2 +-
33
hw/arm/collie.c | 2 +-
34
hw/arm/exynos4210.c | 2 +-
35
hw/arm/exynos4_boards.c | 2 +-
36
hw/arm/highbank.c | 2 +-
37
hw/arm/integratorcp.c | 2 +-
38
hw/arm/mainstone.c | 2 +-
39
hw/arm/microbit.c | 2 +-
40
hw/arm/mps2-tz.c | 2 +-
41
hw/arm/mps2.c | 2 +-
42
hw/arm/msf2-soc.c | 1 -
43
hw/arm/msf2-som.c | 2 +-
44
hw/arm/musca.c | 2 +-
45
hw/arm/musicpal.c | 2 +-
46
hw/arm/netduino2.c | 2 +-
47
hw/arm/nrf51_soc.c | 2 +-
48
hw/arm/nseries.c | 2 +-
49
hw/arm/omap1.c | 2 +-
50
hw/arm/omap2.c | 2 +-
51
hw/arm/omap_sx1.c | 2 +-
52
hw/arm/palm.c | 2 +-
53
hw/arm/raspi.c | 2 +-
54
hw/arm/realview.c | 2 +-
55
hw/arm/spitz.c | 2 +-
56
hw/arm/stellaris.c | 2 +-
57
hw/arm/stm32f205_soc.c | 2 +-
58
hw/arm/strongarm.c | 2 +-
59
hw/arm/tosa.c | 2 +-
60
hw/arm/versatilepb.c | 2 +-
61
hw/arm/vexpress.c | 2 +-
62
hw/arm/virt.c | 2 +-
63
hw/arm/xilinx_zynq.c | 2 +-
64
hw/arm/xlnx-versal.c | 2 +-
65
hw/arm/z2.c | 2 +-
66
49 files changed, 49 insertions(+), 52 deletions(-)
67
rename include/hw/arm/{arm.h => boot.h} (98%)
68
69
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
70
index XXXXXXX..XXXXXXX 100644
71
--- a/include/hw/arm/allwinner-a10.h
72
+++ b/include/hw/arm/allwinner-a10.h
73
@@ -XXX,XX +XXX,XX @@
74
#include "qemu-common.h"
75
#include "qemu/error-report.h"
76
#include "hw/char/serial.h"
77
-#include "hw/arm/arm.h"
78
+#include "hw/arm/boot.h"
79
#include "hw/timer/allwinner-a10-pit.h"
80
#include "hw/intc/allwinner-a10-pic.h"
81
#include "hw/net/allwinner_emac.h"
82
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
83
index XXXXXXX..XXXXXXX 100644
84
--- a/include/hw/arm/aspeed_soc.h
85
+++ b/include/hw/arm/aspeed_soc.h
86
@@ -XXX,XX +XXX,XX @@
87
#ifndef ASPEED_SOC_H
88
#define ASPEED_SOC_H
89
90
-#include "hw/arm/arm.h"
91
#include "hw/intc/aspeed_vic.h"
92
#include "hw/misc/aspeed_scu.h"
93
#include "hw/misc/aspeed_sdmc.h"
94
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
95
index XXXXXXX..XXXXXXX 100644
96
--- a/include/hw/arm/bcm2836.h
97
+++ b/include/hw/arm/bcm2836.h
98
@@ -XXX,XX +XXX,XX @@
99
#ifndef BCM2836_H
100
#define BCM2836_H
101
102
-#include "hw/arm/arm.h"
103
#include "hw/arm/bcm2835_peripherals.h"
104
#include "hw/intc/bcm2836_control.h"
105
106
diff --git a/include/hw/arm/arm.h b/include/hw/arm/boot.h
107
similarity index 98%
108
rename from include/hw/arm/arm.h
109
rename to include/hw/arm/boot.h
110
index XXXXXXX..XXXXXXX 100644
111
--- a/include/hw/arm/arm.h
112
+++ b/include/hw/arm/boot.h
113
@@ -XXX,XX +XXX,XX @@
114
/*
115
- * Misc ARM declarations
116
+ * ARM kernel loader.
117
*
118
* Copyright (c) 2006 CodeSourcery.
119
* Written by Paul Brook
120
@@ -XXX,XX +XXX,XX @@
121
*
122
*/
123
124
-#ifndef HW_ARM_H
125
-#define HW_ARM_H
126
+#ifndef HW_ARM_BOOT_H
127
+#define HW_ARM_BOOT_H
128
129
#include "exec/memory.h"
130
#include "target/arm/cpu-qom.h"
131
@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
132
const struct arm_boot_info *info,
133
hwaddr mvbar_addr);
134
135
-#endif /* HW_ARM_H */
136
+#endif /* HW_ARM_BOOT_H */
137
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
138
index XXXXXXX..XXXXXXX 100644
139
--- a/include/hw/arm/fsl-imx25.h
140
+++ b/include/hw/arm/fsl-imx25.h
141
@@ -XXX,XX +XXX,XX @@
142
#ifndef FSL_IMX25_H
143
#define FSL_IMX25_H
144
145
-#include "hw/arm/arm.h"
146
+#include "hw/arm/boot.h"
147
#include "hw/intc/imx_avic.h"
148
#include "hw/misc/imx25_ccm.h"
149
#include "hw/char/imx_serial.h"
150
diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h
151
index XXXXXXX..XXXXXXX 100644
152
--- a/include/hw/arm/fsl-imx31.h
153
+++ b/include/hw/arm/fsl-imx31.h
154
@@ -XXX,XX +XXX,XX @@
155
#ifndef FSL_IMX31_H
156
#define FSL_IMX31_H
157
158
-#include "hw/arm/arm.h"
159
+#include "hw/arm/boot.h"
160
#include "hw/intc/imx_avic.h"
161
#include "hw/misc/imx31_ccm.h"
162
#include "hw/char/imx_serial.h"
163
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
164
index XXXXXXX..XXXXXXX 100644
165
--- a/include/hw/arm/fsl-imx6.h
166
+++ b/include/hw/arm/fsl-imx6.h
167
@@ -XXX,XX +XXX,XX @@
168
#ifndef FSL_IMX6_H
169
#define FSL_IMX6_H
170
171
-#include "hw/arm/arm.h"
172
+#include "hw/arm/boot.h"
173
#include "hw/cpu/a9mpcore.h"
174
#include "hw/misc/imx6_ccm.h"
175
#include "hw/misc/imx6_src.h"
176
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
177
index XXXXXXX..XXXXXXX 100644
178
--- a/include/hw/arm/fsl-imx6ul.h
179
+++ b/include/hw/arm/fsl-imx6ul.h
180
@@ -XXX,XX +XXX,XX @@
181
#ifndef FSL_IMX6UL_H
182
#define FSL_IMX6UL_H
183
184
-#include "hw/arm/arm.h"
185
+#include "hw/arm/boot.h"
186
#include "hw/cpu/a15mpcore.h"
187
#include "hw/misc/imx6ul_ccm.h"
188
#include "hw/misc/imx6_src.h"
189
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
190
index XXXXXXX..XXXXXXX 100644
191
--- a/include/hw/arm/fsl-imx7.h
192
+++ b/include/hw/arm/fsl-imx7.h
193
@@ -XXX,XX +XXX,XX @@
194
#ifndef FSL_IMX7_H
195
#define FSL_IMX7_H
196
197
-#include "hw/arm/arm.h"
198
+#include "hw/arm/boot.h"
199
#include "hw/cpu/a15mpcore.h"
200
#include "hw/intc/imx_gpcv2.h"
201
#include "hw/misc/imx7_ccm.h"
202
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
203
index XXXXXXX..XXXXXXX 100644
204
--- a/include/hw/arm/virt.h
205
+++ b/include/hw/arm/virt.h
206
@@ -XXX,XX +XXX,XX @@
207
#include "exec/hwaddr.h"
208
#include "qemu/notify.h"
209
#include "hw/boards.h"
210
-#include "hw/arm/arm.h"
211
+#include "hw/arm/boot.h"
212
#include "hw/block/flash.h"
213
#include "sysemu/kvm.h"
214
#include "hw/intc/arm_gicv3_common.h"
215
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
216
index XXXXXXX..XXXXXXX 100644
217
--- a/include/hw/arm/xlnx-versal.h
218
+++ b/include/hw/arm/xlnx-versal.h
219
@@ -XXX,XX +XXX,XX @@
220
#define XLNX_VERSAL_H
221
222
#include "hw/sysbus.h"
223
-#include "hw/arm/arm.h"
224
+#include "hw/arm/boot.h"
225
#include "hw/intc/arm_gicv3.h"
226
227
#define TYPE_XLNX_VERSAL "xlnx-versal"
228
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
229
index XXXXXXX..XXXXXXX 100644
230
--- a/include/hw/arm/xlnx-zynqmp.h
231
+++ b/include/hw/arm/xlnx-zynqmp.h
232
@@ -XXX,XX +XXX,XX @@
233
#ifndef XLNX_ZYNQMP_H
234
235
#include "qemu-common.h"
236
-#include "hw/arm/arm.h"
237
+#include "hw/arm/boot.h"
238
#include "hw/intc/arm_gic.h"
239
#include "hw/net/cadence_gem.h"
240
#include "hw/char/cadence_uart.h"
241
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
242
index XXXXXXX..XXXXXXX 100644
243
--- a/hw/arm/armsse.c
244
+++ b/hw/arm/armsse.c
245
@@ -XXX,XX +XXX,XX @@
246
#include "hw/sysbus.h"
247
#include "hw/registerfields.h"
248
#include "hw/arm/armsse.h"
249
-#include "hw/arm/arm.h"
250
+#include "hw/arm/boot.h"
251
252
/* Format of the System Information block SYS_CONFIG register */
253
typedef enum SysConfigFormat {
254
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
255
index XXXXXXX..XXXXXXX 100644
256
--- a/hw/arm/armv7m.c
257
+++ b/hw/arm/armv7m.c
258
@@ -XXX,XX +XXX,XX @@
259
#include "qemu-common.h"
260
#include "cpu.h"
261
#include "hw/sysbus.h"
262
-#include "hw/arm/arm.h"
263
+#include "hw/arm/boot.h"
264
#include "hw/loader.h"
265
#include "elf.h"
266
#include "sysemu/qtest.h"
267
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
268
index XXXXXXX..XXXXXXX 100644
269
--- a/hw/arm/aspeed.c
270
+++ b/hw/arm/aspeed.c
271
@@ -XXX,XX +XXX,XX @@
272
#include "qemu-common.h"
273
#include "cpu.h"
274
#include "exec/address-spaces.h"
275
-#include "hw/arm/arm.h"
276
+#include "hw/arm/boot.h"
277
#include "hw/arm/aspeed.h"
278
#include "hw/arm/aspeed_soc.h"
279
#include "hw/boards.h"
280
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
19
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
281
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
282
--- a/hw/arm/boot.c
21
--- a/hw/arm/boot.c
283
+++ b/hw/arm/boot.c
22
+++ b/hw/arm/boot.c
284
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque)
285
#include "qapi/error.h"
24
if (cpu_isar_feature(aa64_sve, cpu)) {
286
#include <libfdt.h>
25
env->cp15.cptr_el[3] |= R_CPTR_EL3_EZ_MASK;
287
#include "hw/hw.h"
26
}
288
-#include "hw/arm/arm.h"
27
+ if (cpu_isar_feature(aa64_sme, cpu)) {
289
+#include "hw/arm/boot.h"
28
+ env->cp15.cptr_el[3] |= R_CPTR_EL3_ESM_MASK;
290
#include "hw/arm/linux-boot-if.h"
29
+ env->cp15.scr_el3 |= SCR_ENTP2;
291
#include "sysemu/kvm.h"
30
+ }
292
#include "sysemu/sysemu.h"
31
/* AArch64 kernels never boot in secure mode */
293
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
32
assert(!info->secure_boot);
294
index XXXXXXX..XXXXXXX 100644
33
/* This hook is only supported for AArch32 currently:
295
--- a/hw/arm/collie.c
296
+++ b/hw/arm/collie.c
297
@@ -XXX,XX +XXX,XX @@
298
#include "hw/sysbus.h"
299
#include "hw/boards.h"
300
#include "strongarm.h"
301
-#include "hw/arm/arm.h"
302
+#include "hw/arm/boot.h"
303
#include "hw/block/flash.h"
304
#include "exec/address-spaces.h"
305
#include "cpu.h"
306
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
307
index XXXXXXX..XXXXXXX 100644
308
--- a/hw/arm/exynos4210.c
309
+++ b/hw/arm/exynos4210.c
310
@@ -XXX,XX +XXX,XX @@
311
#include "hw/boards.h"
312
#include "sysemu/sysemu.h"
313
#include "hw/sysbus.h"
314
-#include "hw/arm/arm.h"
315
+#include "hw/arm/boot.h"
316
#include "hw/loader.h"
317
#include "hw/arm/exynos4210.h"
318
#include "hw/sd/sdhci.h"
319
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
320
index XXXXXXX..XXXXXXX 100644
321
--- a/hw/arm/exynos4_boards.c
322
+++ b/hw/arm/exynos4_boards.c
323
@@ -XXX,XX +XXX,XX @@
324
#include "sysemu/sysemu.h"
325
#include "hw/sysbus.h"
326
#include "net/net.h"
327
-#include "hw/arm/arm.h"
328
+#include "hw/arm/boot.h"
329
#include "exec/address-spaces.h"
330
#include "hw/arm/exynos4210.h"
331
#include "hw/net/lan9118.h"
332
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
333
index XXXXXXX..XXXXXXX 100644
334
--- a/hw/arm/highbank.c
335
+++ b/hw/arm/highbank.c
336
@@ -XXX,XX +XXX,XX @@
337
#include "qemu/osdep.h"
338
#include "qapi/error.h"
339
#include "hw/sysbus.h"
340
-#include "hw/arm/arm.h"
341
+#include "hw/arm/boot.h"
342
#include "hw/loader.h"
343
#include "net/net.h"
344
#include "sysemu/kvm.h"
345
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
346
index XXXXXXX..XXXXXXX 100644
347
--- a/hw/arm/integratorcp.c
348
+++ b/hw/arm/integratorcp.c
349
@@ -XXX,XX +XXX,XX @@
350
#include "cpu.h"
351
#include "hw/sysbus.h"
352
#include "hw/boards.h"
353
-#include "hw/arm/arm.h"
354
+#include "hw/arm/boot.h"
355
#include "hw/misc/arm_integrator_debug.h"
356
#include "hw/net/smc91c111.h"
357
#include "net/net.h"
358
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
359
index XXXXXXX..XXXXXXX 100644
360
--- a/hw/arm/mainstone.c
361
+++ b/hw/arm/mainstone.c
362
@@ -XXX,XX +XXX,XX @@
363
#include "qapi/error.h"
364
#include "hw/hw.h"
365
#include "hw/arm/pxa.h"
366
-#include "hw/arm/arm.h"
367
+#include "hw/arm/boot.h"
368
#include "net/net.h"
369
#include "hw/net/smc91c111.h"
370
#include "hw/boards.h"
371
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
372
index XXXXXXX..XXXXXXX 100644
373
--- a/hw/arm/microbit.c
374
+++ b/hw/arm/microbit.c
375
@@ -XXX,XX +XXX,XX @@
376
#include "qemu/osdep.h"
377
#include "qapi/error.h"
378
#include "hw/boards.h"
379
-#include "hw/arm/arm.h"
380
+#include "hw/arm/boot.h"
381
#include "sysemu/sysemu.h"
382
#include "exec/address-spaces.h"
383
384
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
385
index XXXXXXX..XXXXXXX 100644
386
--- a/hw/arm/mps2-tz.c
387
+++ b/hw/arm/mps2-tz.c
388
@@ -XXX,XX +XXX,XX @@
389
#include "qemu/osdep.h"
390
#include "qapi/error.h"
391
#include "qemu/error-report.h"
392
-#include "hw/arm/arm.h"
393
+#include "hw/arm/boot.h"
394
#include "hw/arm/armv7m.h"
395
#include "hw/or-irq.h"
396
#include "hw/boards.h"
397
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
398
index XXXXXXX..XXXXXXX 100644
399
--- a/hw/arm/mps2.c
400
+++ b/hw/arm/mps2.c
401
@@ -XXX,XX +XXX,XX @@
402
#include "qemu/osdep.h"
403
#include "qapi/error.h"
404
#include "qemu/error-report.h"
405
-#include "hw/arm/arm.h"
406
+#include "hw/arm/boot.h"
407
#include "hw/arm/armv7m.h"
408
#include "hw/or-irq.h"
409
#include "hw/boards.h"
410
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
411
index XXXXXXX..XXXXXXX 100644
412
--- a/hw/arm/msf2-soc.c
413
+++ b/hw/arm/msf2-soc.c
414
@@ -XXX,XX +XXX,XX @@
415
#include "qemu/units.h"
416
#include "qapi/error.h"
417
#include "qemu-common.h"
418
-#include "hw/arm/arm.h"
419
#include "exec/address-spaces.h"
420
#include "hw/char/serial.h"
421
#include "hw/boards.h"
422
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
423
index XXXXXXX..XXXXXXX 100644
424
--- a/hw/arm/msf2-som.c
425
+++ b/hw/arm/msf2-som.c
426
@@ -XXX,XX +XXX,XX @@
427
#include "qapi/error.h"
428
#include "qemu/error-report.h"
429
#include "hw/boards.h"
430
-#include "hw/arm/arm.h"
431
+#include "hw/arm/boot.h"
432
#include "exec/address-spaces.h"
433
#include "hw/arm/msf2-soc.h"
434
#include "cpu.h"
435
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
436
index XXXXXXX..XXXXXXX 100644
437
--- a/hw/arm/musca.c
438
+++ b/hw/arm/musca.c
439
@@ -XXX,XX +XXX,XX @@
440
#include "qapi/error.h"
441
#include "exec/address-spaces.h"
442
#include "sysemu/sysemu.h"
443
-#include "hw/arm/arm.h"
444
+#include "hw/arm/boot.h"
445
#include "hw/arm/armsse.h"
446
#include "hw/boards.h"
447
#include "hw/char/pl011.h"
448
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
449
index XXXXXXX..XXXXXXX 100644
450
--- a/hw/arm/musicpal.c
451
+++ b/hw/arm/musicpal.c
452
@@ -XXX,XX +XXX,XX @@
453
#include "qemu-common.h"
454
#include "cpu.h"
455
#include "hw/sysbus.h"
456
-#include "hw/arm/arm.h"
457
+#include "hw/arm/boot.h"
458
#include "net/net.h"
459
#include "sysemu/sysemu.h"
460
#include "hw/boards.h"
461
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
462
index XXXXXXX..XXXXXXX 100644
463
--- a/hw/arm/netduino2.c
464
+++ b/hw/arm/netduino2.c
465
@@ -XXX,XX +XXX,XX @@
466
#include "hw/boards.h"
467
#include "qemu/error-report.h"
468
#include "hw/arm/stm32f205_soc.h"
469
-#include "hw/arm/arm.h"
470
+#include "hw/arm/boot.h"
471
472
static void netduino2_init(MachineState *machine)
473
{
474
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
475
index XXXXXXX..XXXXXXX 100644
476
--- a/hw/arm/nrf51_soc.c
477
+++ b/hw/arm/nrf51_soc.c
478
@@ -XXX,XX +XXX,XX @@
479
#include "qemu/osdep.h"
480
#include "qapi/error.h"
481
#include "qemu-common.h"
482
-#include "hw/arm/arm.h"
483
+#include "hw/arm/boot.h"
484
#include "hw/sysbus.h"
485
#include "hw/boards.h"
486
#include "hw/misc/unimp.h"
487
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
488
index XXXXXXX..XXXXXXX 100644
489
--- a/hw/arm/nseries.c
490
+++ b/hw/arm/nseries.c
491
@@ -XXX,XX +XXX,XX @@
492
#include "qemu/bswap.h"
493
#include "sysemu/sysemu.h"
494
#include "hw/arm/omap.h"
495
-#include "hw/arm/arm.h"
496
+#include "hw/arm/boot.h"
497
#include "hw/irq.h"
498
#include "ui/console.h"
499
#include "hw/boards.h"
500
diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
501
index XXXXXXX..XXXXXXX 100644
502
--- a/hw/arm/omap1.c
503
+++ b/hw/arm/omap1.c
504
@@ -XXX,XX +XXX,XX @@
505
#include "cpu.h"
506
#include "hw/boards.h"
507
#include "hw/hw.h"
508
-#include "hw/arm/arm.h"
509
+#include "hw/arm/boot.h"
510
#include "hw/arm/omap.h"
511
#include "sysemu/sysemu.h"
512
#include "hw/arm/soc_dma.h"
513
diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
514
index XXXXXXX..XXXXXXX 100644
515
--- a/hw/arm/omap2.c
516
+++ b/hw/arm/omap2.c
517
@@ -XXX,XX +XXX,XX @@
518
#include "sysemu/qtest.h"
519
#include "hw/boards.h"
520
#include "hw/hw.h"
521
-#include "hw/arm/arm.h"
522
+#include "hw/arm/boot.h"
523
#include "hw/arm/omap.h"
524
#include "sysemu/sysemu.h"
525
#include "qemu/timer.h"
526
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
527
index XXXXXXX..XXXXXXX 100644
528
--- a/hw/arm/omap_sx1.c
529
+++ b/hw/arm/omap_sx1.c
530
@@ -XXX,XX +XXX,XX @@
531
#include "ui/console.h"
532
#include "hw/arm/omap.h"
533
#include "hw/boards.h"
534
-#include "hw/arm/arm.h"
535
+#include "hw/arm/boot.h"
536
#include "hw/block/flash.h"
537
#include "sysemu/qtest.h"
538
#include "exec/address-spaces.h"
539
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
540
index XXXXXXX..XXXXXXX 100644
541
--- a/hw/arm/palm.c
542
+++ b/hw/arm/palm.c
543
@@ -XXX,XX +XXX,XX @@
544
#include "ui/console.h"
545
#include "hw/arm/omap.h"
546
#include "hw/boards.h"
547
-#include "hw/arm/arm.h"
548
+#include "hw/arm/boot.h"
549
#include "hw/input/tsc2xxx.h"
550
#include "hw/loader.h"
551
#include "exec/address-spaces.h"
552
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
553
index XXXXXXX..XXXXXXX 100644
554
--- a/hw/arm/raspi.c
555
+++ b/hw/arm/raspi.c
556
@@ -XXX,XX +XXX,XX @@
557
#include "qemu/error-report.h"
558
#include "hw/boards.h"
559
#include "hw/loader.h"
560
-#include "hw/arm/arm.h"
561
+#include "hw/arm/boot.h"
562
#include "sysemu/sysemu.h"
563
564
#define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS */
565
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
566
index XXXXXXX..XXXXXXX 100644
567
--- a/hw/arm/realview.c
568
+++ b/hw/arm/realview.c
569
@@ -XXX,XX +XXX,XX @@
570
#include "qemu-common.h"
571
#include "cpu.h"
572
#include "hw/sysbus.h"
573
-#include "hw/arm/arm.h"
574
+#include "hw/arm/boot.h"
575
#include "hw/arm/primecell.h"
576
#include "hw/net/lan9118.h"
577
#include "hw/net/smc91c111.h"
578
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
579
index XXXXXXX..XXXXXXX 100644
580
--- a/hw/arm/spitz.c
581
+++ b/hw/arm/spitz.c
582
@@ -XXX,XX +XXX,XX @@
583
#include "qapi/error.h"
584
#include "hw/hw.h"
585
#include "hw/arm/pxa.h"
586
-#include "hw/arm/arm.h"
587
+#include "hw/arm/boot.h"
588
#include "sysemu/sysemu.h"
589
#include "hw/pcmcia.h"
590
#include "hw/i2c/i2c.h"
591
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
592
index XXXXXXX..XXXXXXX 100644
593
--- a/hw/arm/stellaris.c
594
+++ b/hw/arm/stellaris.c
595
@@ -XXX,XX +XXX,XX @@
596
#include "qapi/error.h"
597
#include "hw/sysbus.h"
598
#include "hw/ssi/ssi.h"
599
-#include "hw/arm/arm.h"
600
+#include "hw/arm/boot.h"
601
#include "qemu/timer.h"
602
#include "hw/i2c/i2c.h"
603
#include "net/net.h"
604
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
605
index XXXXXXX..XXXXXXX 100644
606
--- a/hw/arm/stm32f205_soc.c
607
+++ b/hw/arm/stm32f205_soc.c
608
@@ -XXX,XX +XXX,XX @@
609
#include "qemu/osdep.h"
610
#include "qapi/error.h"
611
#include "qemu-common.h"
612
-#include "hw/arm/arm.h"
613
+#include "hw/arm/boot.h"
614
#include "exec/address-spaces.h"
615
#include "hw/arm/stm32f205_soc.h"
616
617
diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
618
index XXXXXXX..XXXXXXX 100644
619
--- a/hw/arm/strongarm.c
620
+++ b/hw/arm/strongarm.c
621
@@ -XXX,XX +XXX,XX @@
622
#include "hw/sysbus.h"
623
#include "strongarm.h"
624
#include "qemu/error-report.h"
625
-#include "hw/arm/arm.h"
626
+#include "hw/arm/boot.h"
627
#include "chardev/char-fe.h"
628
#include "chardev/char-serial.h"
629
#include "sysemu/sysemu.h"
630
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
631
index XXXXXXX..XXXXXXX 100644
632
--- a/hw/arm/tosa.c
633
+++ b/hw/arm/tosa.c
634
@@ -XXX,XX +XXX,XX @@
635
#include "qapi/error.h"
636
#include "hw/hw.h"
637
#include "hw/arm/pxa.h"
638
-#include "hw/arm/arm.h"
639
+#include "hw/arm/boot.h"
640
#include "hw/arm/sharpsl.h"
641
#include "hw/pcmcia.h"
642
#include "hw/boards.h"
643
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
644
index XXXXXXX..XXXXXXX 100644
645
--- a/hw/arm/versatilepb.c
646
+++ b/hw/arm/versatilepb.c
647
@@ -XXX,XX +XXX,XX @@
648
#include "qemu-common.h"
649
#include "cpu.h"
650
#include "hw/sysbus.h"
651
-#include "hw/arm/arm.h"
652
+#include "hw/arm/boot.h"
653
#include "hw/net/smc91c111.h"
654
#include "net/net.h"
655
#include "sysemu/sysemu.h"
656
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
657
index XXXXXXX..XXXXXXX 100644
658
--- a/hw/arm/vexpress.c
659
+++ b/hw/arm/vexpress.c
660
@@ -XXX,XX +XXX,XX @@
661
#include "qemu-common.h"
662
#include "cpu.h"
663
#include "hw/sysbus.h"
664
-#include "hw/arm/arm.h"
665
+#include "hw/arm/boot.h"
666
#include "hw/arm/primecell.h"
667
#include "hw/net/lan9118.h"
668
#include "hw/i2c/i2c.h"
669
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
670
index XXXXXXX..XXXXXXX 100644
671
--- a/hw/arm/virt.c
672
+++ b/hw/arm/virt.c
673
@@ -XXX,XX +XXX,XX @@
674
#include "qemu/option.h"
675
#include "qapi/error.h"
676
#include "hw/sysbus.h"
677
-#include "hw/arm/arm.h"
678
+#include "hw/arm/boot.h"
679
#include "hw/arm/primecell.h"
680
#include "hw/arm/virt.h"
681
#include "hw/block/flash.h"
682
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
683
index XXXXXXX..XXXXXXX 100644
684
--- a/hw/arm/xilinx_zynq.c
685
+++ b/hw/arm/xilinx_zynq.c
686
@@ -XXX,XX +XXX,XX @@
687
#include "qemu-common.h"
688
#include "cpu.h"
689
#include "hw/sysbus.h"
690
-#include "hw/arm/arm.h"
691
+#include "hw/arm/boot.h"
692
#include "net/net.h"
693
#include "exec/address-spaces.h"
694
#include "sysemu/sysemu.h"
695
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
696
index XXXXXXX..XXXXXXX 100644
697
--- a/hw/arm/xlnx-versal.c
698
+++ b/hw/arm/xlnx-versal.c
699
@@ -XXX,XX +XXX,XX @@
700
#include "net/net.h"
701
#include "sysemu/sysemu.h"
702
#include "sysemu/kvm.h"
703
-#include "hw/arm/arm.h"
704
+#include "hw/arm/boot.h"
705
#include "kvm_arm.h"
706
#include "hw/misc/unimp.h"
707
#include "hw/intc/arm_gicv3_common.h"
708
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
709
index XXXXXXX..XXXXXXX 100644
710
--- a/hw/arm/z2.c
711
+++ b/hw/arm/z2.c
712
@@ -XXX,XX +XXX,XX @@
713
#include "qemu/osdep.h"
714
#include "hw/hw.h"
715
#include "hw/arm/pxa.h"
716
-#include "hw/arm/arm.h"
717
+#include "hw/arm/boot.h"
718
#include "hw/i2c/i2c.h"
719
#include "hw/ssi/ssi.h"
720
#include "hw/boards.h"
721
--
34
--
722
2.20.1
35
2.25.1
723
724
diff view generated by jsdifflib
New patch
[PULL 26/28] target/arm: Don't allow guest to use unimplemented granule sizes
1
1
Arm CPUs support some subset of the granule (page) sizes 4K, 16K and
2
64K. The guest selects the one it wants using bits in the TCR_ELx
3
registers. If it tries to program these registers with a value that
4
is either reserved or which requests a size that the CPU does not
5
implement, the architecture requires that the CPU behaves as if the
6
field was programmed to some size that has been implemented.
7
Currently we don't implement this, and instead let the guest use any
8
granule size, even if the CPU ID register fields say it isn't
9
present.
10
11
Make aa64_va_parameters() check against the supported granule size
12
and force use of a different one if it is not implemented.
13
14
(A subsequent commit will make ARMVAParameters use the new enum
15
rather than the current pair of using16k/using64k bools.)
16
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Message-id: 20221003162315.2833797-2-peter.maydell@linaro.org
20
---
21
target/arm/cpu.h | 33 +++++++++++++
22
target/arm/internals.h | 9 ++++
23
target/arm/helper.c | 102 +++++++++++++++++++++++++++++++++++++----
24
3 files changed, 136 insertions(+), 8 deletions(-)
25
26
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
27
index XXXXXXX..XXXXXXX 100644
28
--- a/target/arm/cpu.h
29
+++ b/target/arm/cpu.h
30
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_tgran16_2_lpa2(const ARMISARegisters *id)
31
return t >= 3 || (t == 0 && isar_feature_aa64_tgran16_lpa2(id));
32
}
33
34
+static inline bool isar_feature_aa64_tgran4(const ARMISARegisters *id)
35
+{
36
+ return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4) >= 0;
37
+}
38
+
39
+static inline bool isar_feature_aa64_tgran16(const ARMISARegisters *id)
40
+{
41
+ return FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16) >= 1;
42
+}
43
+
44
+static inline bool isar_feature_aa64_tgran64(const ARMISARegisters *id)
45
+{
46
+ return FIELD_SEX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64) >= 0;
47
+}
48
+
49
+static inline bool isar_feature_aa64_tgran4_2(const ARMISARegisters *id)
50
+{
51
+ unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN4_2);
52
+ return t >= 2 || (t == 0 && isar_feature_aa64_tgran4(id));
53
+}
54
+
55
+static inline bool isar_feature_aa64_tgran16_2(const ARMISARegisters *id)
56
+{
57
+ unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN16_2);
58
+ return t >= 2 || (t == 0 && isar_feature_aa64_tgran16(id));
59
+}
60
+
61
+static inline bool isar_feature_aa64_tgran64_2(const ARMISARegisters *id)
62
+{
63
+ unsigned t = FIELD_EX64(id->id_aa64mmfr0, ID_AA64MMFR0, TGRAN64_2);
64
+ return t >= 2 || (t == 0 && isar_feature_aa64_tgran64(id));
65
+}
66
+
67
static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id)
68
{
69
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) != 0;
70
diff --git a/target/arm/internals.h b/target/arm/internals.h
71
index XXXXXXX..XXXXXXX 100644
72
--- a/target/arm/internals.h
73
+++ b/target/arm/internals.h
74
@@ -XXX,XX +XXX,XX @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id)
75
return valid;
76
}
77
78
+/* Granule size (i.e. page size) */
79
+typedef enum ARMGranuleSize {
80
+ /* Same order as TG0 encoding */
81
+ Gran4K,
82
+ Gran64K,
83
+ Gran16K,
84
+ GranInvalid,
85
+} ARMGranuleSize;
86
+
87
/*
88
* Parameters of a given virtual address, as extracted from the
89
* translation control register (TCR) for a given regime.
90
diff --git a/target/arm/helper.c b/target/arm/helper.c
91
index XXXXXXX..XXXXXXX 100644
92
--- a/target/arm/helper.c
93
+++ b/target/arm/helper.c
94
@@ -XXX,XX +XXX,XX @@ static int aa64_va_parameter_tcma(uint64_t tcr, ARMMMUIdx mmu_idx)
95
}
96
}
97
98
+static ARMGranuleSize tg0_to_gran_size(int tg)
99
+{
100
+ switch (tg) {
101
+ case 0:
102
+ return Gran4K;
103
+ case 1:
104
+ return Gran64K;
105
+ case 2:
106
+ return Gran16K;
107
+ default:
108
+ return GranInvalid;
109
+ }
110
+}
111
+
112
+static ARMGranuleSize tg1_to_gran_size(int tg)
113
+{
114
+ switch (tg) {
115
+ case 1:
116
+ return Gran16K;
117
+ case 2:
118
+ return Gran4K;
119
+ case 3:
120
+ return Gran64K;
121
+ default:
122
+ return GranInvalid;
123
+ }
124
+}
125
+
126
+static inline bool have4k(ARMCPU *cpu, bool stage2)
127
+{
128
+ return stage2 ? cpu_isar_feature(aa64_tgran4_2, cpu)
129
+ : cpu_isar_feature(aa64_tgran4, cpu);
130
+}
131
+
132
+static inline bool have16k(ARMCPU *cpu, bool stage2)
133
+{
134
+ return stage2 ? cpu_isar_feature(aa64_tgran16_2, cpu)
135
+ : cpu_isar_feature(aa64_tgran16, cpu);
136
+}
137
+
138
+static inline bool have64k(ARMCPU *cpu, bool stage2)
139
+{
140
+ return stage2 ? cpu_isar_feature(aa64_tgran64_2, cpu)
141
+ : cpu_isar_feature(aa64_tgran64, cpu);
142
+}
143
+
144
+static ARMGranuleSize sanitize_gran_size(ARMCPU *cpu, ARMGranuleSize gran,
145
+ bool stage2)
146
+{
147
+ switch (gran) {
148
+ case Gran4K:
149
+ if (have4k(cpu, stage2)) {
150
+ return gran;
151
+ }
152
+ break;
153
+ case Gran16K:
154
+ if (have16k(cpu, stage2)) {
155
+ return gran;
156
+ }
157
+ break;
158
+ case Gran64K:
159
+ if (have64k(cpu, stage2)) {
160
+ return gran;
161
+ }
162
+ break;
163
+ case GranInvalid:
164
+ break;
165
+ }
166
+ /*
167
+ * If the guest selects a granule size that isn't implemented,
168
+ * the architecture requires that we behave as if it selected one
169
+ * that is (with an IMPDEF choice of which one to pick). We choose
170
+ * to implement the smallest supported granule size.
171
+ */
172
+ if (have4k(cpu, stage2)) {
173
+ return Gran4K;
174
+ }
175
+ if (have16k(cpu, stage2)) {
176
+ return Gran16K;
177
+ }
178
+ assert(have64k(cpu, stage2));
179
+ return Gran64K;
180
+}
181
+
182
ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
183
ARMMMUIdx mmu_idx, bool data)
184
{
185
uint64_t tcr = regime_tcr(env, mmu_idx);
186
bool epd, hpd, using16k, using64k, tsz_oob, ds;
187
int select, tsz, tbi, max_tsz, min_tsz, ps, sh;
188
+ ARMGranuleSize gran;
189
ARMCPU *cpu = env_archcpu(env);
190
+ bool stage2 = mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S;
191
192
if (!regime_has_2_ranges(mmu_idx)) {
193
select = 0;
194
tsz = extract32(tcr, 0, 6);
195
- using64k = extract32(tcr, 14, 1);
196
- using16k = extract32(tcr, 15, 1);
197
- if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
198
+ gran = tg0_to_gran_size(extract32(tcr, 14, 2));
199
+ if (stage2) {
200
/* VTCR_EL2 */
201
hpd = false;
202
} else {
203
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
204
select = extract64(va, 55, 1);
205
if (!select) {
206
tsz = extract32(tcr, 0, 6);
207
+ gran = tg0_to_gran_size(extract32(tcr, 14, 2));
208
epd = extract32(tcr, 7, 1);
209
sh = extract32(tcr, 12, 2);
210
- using64k = extract32(tcr, 14, 1);
211
- using16k = extract32(tcr, 15, 1);
212
hpd = extract64(tcr, 41, 1);
213
} else {
214
- int tg = extract32(tcr, 30, 2);
215
- using16k = tg == 1;
216
- using64k = tg == 3;
217
tsz = extract32(tcr, 16, 6);
218
+ gran = tg1_to_gran_size(extract32(tcr, 30, 2));
219
epd = extract32(tcr, 23, 1);
220
sh = extract32(tcr, 28, 2);
221
hpd = extract64(tcr, 42, 1);
222
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
223
ds = extract64(tcr, 59, 1);
224
}
225
226
+ gran = sanitize_gran_size(cpu, gran, stage2);
227
+ using64k = gran == Gran64K;
228
+ using16k = gran == Gran16K;
229
+
230
if (cpu_isar_feature(aa64_st, cpu)) {
231
max_tsz = 48 - using64k;
232
} else {
233
--
234
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/12] hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
[PULL 27/28] target/arm: Use ARMGranuleSize in ARMVAParameters
1
In ich_vmcr_write() we enforce "writes of BPR fields to less than
1
Now we have an enum for the granule size, use it in the
2
their minimum sets them to the minimum" by doing a "read vbpr and
2
ARMVAParameters struct instead of the using16k/using64k bools.
3
write it back" operation. A typo here meant that we weren't handling
4
writes to these fields correctly, because we were reading from VBPR0
5
but writing to VBPR1.
6
3
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20190520162809.2677-4-peter.maydell@linaro.org
6
Message-id: 20221003162315.2833797-3-peter.maydell@linaro.org
10
---
7
---
11
hw/intc/arm_gicv3_cpuif.c | 2 +-
8
target/arm/internals.h | 23 +++++++++++++++++++++--
12
1 file changed, 1 insertion(+), 1 deletion(-)
9
target/arm/helper.c | 39 ++++++++++++++++++++++++++++-----------
10
target/arm/ptw.c | 8 +-------
11
3 files changed, 50 insertions(+), 20 deletions(-)
13
12
14
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
13
diff --git a/target/arm/internals.h b/target/arm/internals.h
15
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/arm_gicv3_cpuif.c
15
--- a/target/arm/internals.h
17
+++ b/hw/intc/arm_gicv3_cpuif.c
16
+++ b/target/arm/internals.h
18
@@ -XXX,XX +XXX,XX @@ static void ich_vmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
17
@@ -XXX,XX +XXX,XX @@ typedef enum ARMGranuleSize {
19
/* Enforce "writing BPRs to less than minimum sets them to the minimum"
18
GranInvalid,
20
* by reading and writing back the fields.
19
} ARMGranuleSize;
20
21
+/**
22
+ * arm_granule_bits: Return address size of the granule in bits
23
+ *
24
+ * Return the address size of the granule in bits. This corresponds
25
+ * to the pseudocode TGxGranuleBits().
26
+ */
27
+static inline int arm_granule_bits(ARMGranuleSize gran)
28
+{
29
+ switch (gran) {
30
+ case Gran64K:
31
+ return 16;
32
+ case Gran16K:
33
+ return 14;
34
+ case Gran4K:
35
+ return 12;
36
+ default:
37
+ g_assert_not_reached();
38
+ }
39
+}
40
+
41
/*
42
* Parameters of a given virtual address, as extracted from the
43
* translation control register (TCR) for a given regime.
44
@@ -XXX,XX +XXX,XX @@ typedef struct ARMVAParameters {
45
bool tbi : 1;
46
bool epd : 1;
47
bool hpd : 1;
48
- bool using16k : 1;
49
- bool using64k : 1;
50
bool tsz_oob : 1; /* tsz has been clamped to legal range */
51
bool ds : 1;
52
+ ARMGranuleSize gran : 2;
53
} ARMVAParameters;
54
55
ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
56
diff --git a/target/arm/helper.c b/target/arm/helper.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/target/arm/helper.c
59
+++ b/target/arm/helper.c
60
@@ -XXX,XX +XXX,XX @@ typedef struct {
61
uint64_t length;
62
} TLBIRange;
63
64
+static ARMGranuleSize tlbi_range_tg_to_gran_size(int tg)
65
+{
66
+ /*
67
+ * Note that the TLBI range TG field encoding differs from both
68
+ * TG0 and TG1 encodings.
69
+ */
70
+ switch (tg) {
71
+ case 1:
72
+ return Gran4K;
73
+ case 2:
74
+ return Gran16K;
75
+ case 3:
76
+ return Gran64K;
77
+ default:
78
+ return GranInvalid;
79
+ }
80
+}
81
+
82
static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx,
83
uint64_t value)
84
{
85
@@ -XXX,XX +XXX,XX @@ static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx,
86
uint64_t select = sextract64(value, 36, 1);
87
ARMVAParameters param = aa64_va_parameters(env, select, mmuidx, true);
88
TLBIRange ret = { };
89
+ ARMGranuleSize gran;
90
91
page_size_granule = extract64(value, 46, 2);
92
+ gran = tlbi_range_tg_to_gran_size(page_size_granule);
93
94
/* The granule encoded in value must match the granule in use. */
95
- if (page_size_granule != (param.using64k ? 3 : param.using16k ? 2 : 1)) {
96
+ if (gran != param.gran) {
97
qemu_log_mask(LOG_GUEST_ERROR, "Invalid tlbi page size granule %d\n",
98
page_size_granule);
99
return ret;
100
}
101
102
- page_shift = (page_size_granule - 1) * 2 + 12;
103
+ page_shift = arm_granule_bits(gran);
104
num = extract64(value, 39, 5);
105
scale = extract64(value, 44, 2);
106
exponent = (5 * scale) + 1;
107
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
108
ARMMMUIdx mmu_idx, bool data)
109
{
110
uint64_t tcr = regime_tcr(env, mmu_idx);
111
- bool epd, hpd, using16k, using64k, tsz_oob, ds;
112
+ bool epd, hpd, tsz_oob, ds;
113
int select, tsz, tbi, max_tsz, min_tsz, ps, sh;
114
ARMGranuleSize gran;
115
ARMCPU *cpu = env_archcpu(env);
116
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
117
}
118
119
gran = sanitize_gran_size(cpu, gran, stage2);
120
- using64k = gran == Gran64K;
121
- using16k = gran == Gran16K;
122
123
if (cpu_isar_feature(aa64_st, cpu)) {
124
- max_tsz = 48 - using64k;
125
+ max_tsz = 48 - (gran == Gran64K);
126
} else {
127
max_tsz = 39;
128
}
129
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
130
* adjust the effective value of DS, as documented.
21
*/
131
*/
22
- write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G0));
132
min_tsz = 16;
23
+ write_vbpr(cs, GICV3_G0, read_vbpr(cs, GICV3_G0));
133
- if (using64k) {
24
write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G1));
134
+ if (gran == Gran64K) {
25
135
if (cpu_isar_feature(aa64_lva, cpu)) {
26
gicv3_cpuif_virt_update(cs);
136
min_tsz = 12;
137
}
138
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
139
switch (mmu_idx) {
140
case ARMMMUIdx_Stage2:
141
case ARMMMUIdx_Stage2_S:
142
- if (using16k) {
143
+ if (gran == Gran16K) {
144
ds = cpu_isar_feature(aa64_tgran16_2_lpa2, cpu);
145
} else {
146
ds = cpu_isar_feature(aa64_tgran4_2_lpa2, cpu);
147
}
148
break;
149
default:
150
- if (using16k) {
151
+ if (gran == Gran16K) {
152
ds = cpu_isar_feature(aa64_tgran16_lpa2, cpu);
153
} else {
154
ds = cpu_isar_feature(aa64_tgran4_lpa2, cpu);
155
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
156
.tbi = tbi,
157
.epd = epd,
158
.hpd = hpd,
159
- .using16k = using16k,
160
- .using64k = using64k,
161
.tsz_oob = tsz_oob,
162
.ds = ds,
163
+ .gran = gran,
164
};
165
}
166
167
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
168
index XXXXXXX..XXXXXXX 100644
169
--- a/target/arm/ptw.c
170
+++ b/target/arm/ptw.c
171
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
172
}
173
}
174
175
- if (param.using64k) {
176
- stride = 13;
177
- } else if (param.using16k) {
178
- stride = 11;
179
- } else {
180
- stride = 9;
181
- }
182
+ stride = arm_granule_bits(param.gran) - 3;
183
184
/*
185
* Note that QEMU ignores shareability and cacheability attributes,
27
--
186
--
28
2.20.1
187
2.25.1
29
30
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/12] arm: Move system_clock_scale to armv7m_systick.h
[PULL 28/28] docs/system/arm/emulation.rst: Report FEAT_GTG support
1
The system_clock_scale global is used only by the armv7m systick
1
FEAT_GTG is a change tho the ID register ID_AA64MMFR0_EL1 so that it
2
device; move the extern declaration to the armv7m_systick.h header,
2
can report a different set of supported granule (page) sizes for
3
and expand the comment to explain what it is and that it should
3
stage 1 and stage 2 translation tables. As of commit c20281b2a5048
4
ideally be replaced with a different approach.
4
we already report the granule sizes that way for '-cpu max', and now
5
we also correctly make attempts to use unimplemented granule sizes
6
fail, so we can report the support of the feature in the
7
documentation.
5
8
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Message-id: 20221003162315.2833797-4-peter.maydell@linaro.org
8
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20190516163857.6430-2-peter.maydell@linaro.org
10
---
12
---
11
include/hw/arm/arm.h | 4 ----
13
docs/system/arm/emulation.rst | 1 +
12
include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++++++++
14
1 file changed, 1 insertion(+)
13
2 files changed, 22 insertions(+), 4 deletions(-)
14
15
15
diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h
16
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
16
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/arm.h
18
--- a/docs/system/arm/emulation.rst
18
+++ b/include/hw/arm/arm.h
19
+++ b/docs/system/arm/emulation.rst
19
@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
20
@@ -XXX,XX +XXX,XX @@ the following architecture extensions:
20
const struct arm_boot_info *info,
21
- FEAT_FRINTTS (Floating-point to integer instructions)
21
hwaddr mvbar_addr);
22
- FEAT_FlagM (Flag manipulation instructions v2)
22
23
- FEAT_FlagM2 (Enhancements to flag manipulation instructions)
23
-/* Multiplication factor to convert from system clock ticks to qemu timer
24
+- FEAT_GTG (Guest translation granule size)
24
- ticks. */
25
- FEAT_HCX (Support for the HCRX_EL2 register)
25
-extern int system_clock_scale;
26
- FEAT_HPDS (Hierarchical permission disables)
26
-
27
- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
27
#endif /* HW_ARM_H */
28
diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
29
index XXXXXXX..XXXXXXX 100644
30
--- a/include/hw/timer/armv7m_systick.h
31
+++ b/include/hw/timer/armv7m_systick.h
32
@@ -XXX,XX +XXX,XX @@ typedef struct SysTickState {
33
qemu_irq irq;
34
} SysTickState;
35
36
+/*
37
+ * Multiplication factor to convert from system clock ticks to qemu timer
38
+ * ticks. This should be set (by board code, usually) to a value
39
+ * equal to NANOSECONDS_PER_SECOND / frq, where frq is the clock frequency
40
+ * in Hz of the CPU.
41
+ *
42
+ * This value is used by the systick device when it is running in
43
+ * its "use the CPU clock" mode (ie when SYST_CSR.CLKSOURCE == 1) to
44
+ * set how fast the timer should tick.
45
+ *
46
+ * TODO: we should refactor this so that rather than using a global
47
+ * we use a device property or something similar. This is complicated
48
+ * because (a) the property would need to be plumbed through from the
49
+ * board code down through various layers to the systick device
50
+ * and (b) the property needs to be modifiable after realize, because
51
+ * the stellaris board uses this to implement the behaviour where the
52
+ * guest can reprogram the PLL registers to downclock the CPU, and the
53
+ * systick device needs to react accordingly. Possibly this should
54
+ * be deferred until we have a good API for modelling clock trees.
55
+ */
56
+extern int system_clock_scale;
57
+
58
#endif
59
--
28
--
60
2.20.1
29
2.25.1
61
62
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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