[Qemu-devel] [PULL 00/12] target-arm queue
[PULL 00/10] target-arm queue
1
Not very much here, but several people have fallen over
1
Hi; not so many patches in this one, but notably it includes the
2
the vector operation segfault bug, so let's get the fix
2
fix for various Avocado CI tests failing (incorrectly reported by
3
into master.
3
Avocado as a timeout, but really a QEMU exit-with-error).
4
4
5
thanks
5
thanks
6
-- PMM
6
-- PMM
7
7
8
The following changes since commit d418238dca7b4e0b124135827ead3076233052b1:
8
The following changes since commit c8de6ec63d766ca1998c5af468483ce912fdc0c2:
9
9
10
Merge remote-tracking branch 'remotes/rth/tags/pull-rng-20190522' into staging (2019-05-23 12:57:17 +0100)
10
Merge tag 'pull-request-2022-09-28' of https://gitlab.com/thuth/qemu into staging (2022-09-28 17:04:11 -0400)
11
11
12
are available in the Git repository at:
12
are available in the Git repository at:
13
13
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190523
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220930
15
15
16
for you to fetch changes up to 98e4f4fdb8ea05d840f51f47125924c2bb9df2df:
16
for you to fetch changes up to beeec926d24aac28f95cc7694ef3837d7a4cd3bb:
17
17
18
hw/arm/exynos4210: QOM'ify the Exynos4210 SoC (2019-05-23 14:47:44 +0100)
18
target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP (2022-09-29 18:01:09 +0100)
19
19
20
----------------------------------------------------------------
20
----------------------------------------------------------------
21
target-arm queue:
21
target-arm queue:
22
* exynos4210: QOM'ify the Exynos4210 SoC
22
* Fix breakage of icount mode when guest touches MDCR_EL3, MDCR_EL2,
23
* exynos4210: Add DMA support for the Exynos4210
23
PMCNTENSET_EL0 or PMCNTENCLR_EL0
24
* arm_gicv3: Fix writes to ICC_CTLR_EL3
24
* Make writes to MDCR_EL3 use PMU start/finish calls
25
* arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
25
* Let AArch32 write to SDCR.SCCD
26
* target/arm: Fix vector operation segfault
26
* Rearrange cpu64.c so all the CPU initfns are together
27
* target/arm: Minor improvements to BFXIL, EXTR
27
* hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
28
* hw/arm/virt: fix some minor issues with generated device tree
29
* Fix regression where EL3 could not write to SP_EL1 if there is no EL2
28
30
29
----------------------------------------------------------------
31
----------------------------------------------------------------
30
Alistair Francis (1):
32
Francisco Iglesias (1):
31
target/arm: Fix vector operation segfault
33
hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
32
34
33
Guenter Roeck (1):
35
Jean-Philippe Brucker (4):
34
hw/arm/exynos4210: Add DMA support for the Exynos4210
36
hw/arm/virt: Fix devicetree warning about the root node
37
hw/arm/virt: Fix devicetree warning about the GIC node
38
hw/arm/virt: Use "msi-map" devicetree property for PCI
39
hw/arm/virt: Fix devicetree warning about the SMMU node
35
40
36
Peter Maydell (5):
41
Jerome Forissier (1):
37
arm: Move system_clock_scale to armv7m_systick.h
42
target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP
38
arm: Remove unnecessary includes of hw/arm/arm.h
39
arm: Rename hw/arm/arm.h to hw/arm/boot.h
40
hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
41
hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3
42
43
43
Philippe Mathieu-Daudé (3):
44
Peter Maydell (4):
44
hw/arm/exynos4: Remove unuseful debug code
45
target/arm: Mark registers which call pmu_op_start() as ARM_CP_IO
45
hw/arm/exynos4: Use the IEC binary prefix definitions
46
target/arm: Make writes to MDCR_EL3 use PMU start/finish calls
46
hw/arm/exynos4210: QOM'ify the Exynos4210 SoC
47
target/arm: Update SDCR_VALID_MASK to include SCCD
48
target/arm: Rearrange cpu64.c so all the CPU initfns are together
47
49
48
Richard Henderson (2):
50
include/hw/arm/xlnx-zynqmp.h | 3 +
49
target/arm: Use extract2 for EXTR
51
target/arm/cpu.h | 8 +-
50
target/arm: Simplify BFXIL expansion
52
hw/arm/virt.c | 8 +-
51
53
hw/arm/xlnx-zynqmp.c | 36 +++
52
include/hw/arm/allwinner-a10.h | 2 +-
54
target/arm/cpu64.c | 712 +++++++++++++++++++++----------------------
53
include/hw/arm/aspeed_soc.h | 1 -
55
target/arm/helper.c | 32 +-
54
include/hw/arm/bcm2836.h | 1 -
56
6 files changed, 427 insertions(+), 372 deletions(-)
55
include/hw/arm/{arm.h => boot.h} | 12 +++------
56
include/hw/arm/exynos4210.h | 9 +++++--
57
include/hw/arm/fsl-imx25.h | 2 +-
58
include/hw/arm/fsl-imx31.h | 2 +-
59
include/hw/arm/fsl-imx6.h | 2 +-
60
include/hw/arm/fsl-imx6ul.h | 2 +-
61
include/hw/arm/fsl-imx7.h | 2 +-
62
include/hw/arm/virt.h | 2 +-
63
include/hw/arm/xlnx-versal.h | 2 +-
64
include/hw/arm/xlnx-zynqmp.h | 2 +-
65
include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++
66
hw/arm/armsse.c | 2 +-
67
hw/arm/armv7m.c | 2 +-
68
hw/arm/aspeed.c | 2 +-
69
hw/arm/boot.c | 2 +-
70
hw/arm/collie.c | 2 +-
71
hw/arm/exynos4210.c | 54 ++++++++++++++++++++++++++++++++++++---
72
hw/arm/exynos4_boards.c | 40 ++++++++---------------------
73
hw/arm/highbank.c | 2 +-
74
hw/arm/integratorcp.c | 2 +-
75
hw/arm/mainstone.c | 2 +-
76
hw/arm/microbit.c | 2 +-
77
hw/arm/mps2-tz.c | 2 +-
78
hw/arm/mps2.c | 2 +-
79
hw/arm/msf2-soc.c | 1 -
80
hw/arm/msf2-som.c | 2 +-
81
hw/arm/musca.c | 2 +-
82
hw/arm/musicpal.c | 2 +-
83
hw/arm/netduino2.c | 2 +-
84
hw/arm/nrf51_soc.c | 2 +-
85
hw/arm/nseries.c | 2 +-
86
hw/arm/omap1.c | 2 +-
87
hw/arm/omap2.c | 2 +-
88
hw/arm/omap_sx1.c | 2 +-
89
hw/arm/palm.c | 2 +-
90
hw/arm/raspi.c | 2 +-
91
hw/arm/realview.c | 2 +-
92
hw/arm/spitz.c | 2 +-
93
hw/arm/stellaris.c | 2 +-
94
hw/arm/stm32f205_soc.c | 2 +-
95
hw/arm/strongarm.c | 2 +-
96
hw/arm/tosa.c | 2 +-
97
hw/arm/versatilepb.c | 2 +-
98
hw/arm/vexpress.c | 2 +-
99
hw/arm/virt.c | 2 +-
100
hw/arm/xilinx_zynq.c | 2 +-
101
hw/arm/xlnx-versal.c | 2 +-
102
hw/arm/z2.c | 2 +-
103
hw/intc/arm_gicv3_cpuif.c | 6 ++---
104
hw/intc/armv7m_nvic.c | 1 -
105
target/arm/arm-semi.c | 1 -
106
target/arm/cpu.c | 1 -
107
target/arm/cpu64.c | 1 -
108
target/arm/kvm.c | 1 -
109
target/arm/kvm32.c | 1 -
110
target/arm/kvm64.c | 1 -
111
target/arm/translate-a64.c | 44 ++++++++++++++++---------------
112
target/arm/translate.c | 4 +--
113
61 files changed, 164 insertions(+), 123 deletions(-)
114
rename include/hw/arm/{arm.h => boot.h} (96%)
115
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/12] target/arm: Use extract2 for EXTR
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
This is, after all, how we implement extract2 in tcg/aarch64.
4
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20190514011129.11330-2-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/translate-a64.c | 38 ++++++++++++++++++++------------------
11
1 file changed, 20 insertions(+), 18 deletions(-)
12
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
16
+++ b/target/arm/translate-a64.c
17
@@ -XXX,XX +XXX,XX @@ static void disas_extract(DisasContext *s, uint32_t insn)
18
} else {
19
tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));
20
}
21
- } else if (rm == rn) { /* ROR */
22
- tcg_rm = cpu_reg(s, rm);
23
- if (sf) {
24
- tcg_gen_rotri_i64(tcg_rd, tcg_rm, imm);
25
- } else {
26
- TCGv_i32 tmp = tcg_temp_new_i32();
27
- tcg_gen_extrl_i64_i32(tmp, tcg_rm);
28
- tcg_gen_rotri_i32(tmp, tmp, imm);
29
- tcg_gen_extu_i32_i64(tcg_rd, tmp);
30
- tcg_temp_free_i32(tmp);
31
- }
32
} else {
33
- tcg_rm = read_cpu_reg(s, rm, sf);
34
- tcg_rn = read_cpu_reg(s, rn, sf);
35
- tcg_gen_shri_i64(tcg_rm, tcg_rm, imm);
36
- tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm);
37
- tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn);
38
- if (!sf) {
39
- tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
40
+ tcg_rm = cpu_reg(s, rm);
41
+ tcg_rn = cpu_reg(s, rn);
42
+
43
+ if (sf) {
44
+ /* Specialization to ROR happens in EXTRACT2. */
45
+ tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, imm);
46
+ } else {
47
+ TCGv_i32 t0 = tcg_temp_new_i32();
48
+
49
+ tcg_gen_extrl_i64_i32(t0, tcg_rm);
50
+ if (rm == rn) {
51
+ tcg_gen_rotri_i32(t0, t0, imm);
52
+ } else {
53
+ TCGv_i32 t1 = tcg_temp_new_i32();
54
+ tcg_gen_extrl_i64_i32(t1, tcg_rn);
55
+ tcg_gen_extract2_i32(t0, t0, t1, imm);
56
+ tcg_temp_free_i32(t1);
57
+ }
58
+ tcg_gen_extu_i32_i64(tcg_rd, t0);
59
+ tcg_temp_free_i32(t0);
60
}
61
}
62
}
63
--
64
2.20.1
65
66
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/12] hw/arm/exynos4: Use the IEC binary prefix definitions
[PULL 01/10] target/arm: Mark registers which call pmu_op_start() as ARM_CP_IO
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
In commit 01765386a888 we made some system register write functions
2
call pmu_op_start()/pmu_op_finish(). This means that they now touch
3
timers, so for icount to work these registers must have the ARM_CP_IO
4
flag set.
2
5
3
It eases code review, unit is explicit.
6
This fixes a bug where when icount is enabled a guest that touches
7
MDCR_EL3, MDCR_EL2, PMCNTENSET_EL0 or PMCNTENCLR_EL0 would cause
8
QEMU to print an error message and exit, for example:
4
9
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
[ 2.495971] TCP: Hash tables configured (established 1024 bind 1024)
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
[ 2.496213] UDP hash table entries: 256 (order: 1, 8192 bytes)
7
Message-id: 20190520214342.13709-3-philmd@redhat.com
12
[ 2.496386] UDP-Lite hash table entries: 256 (order: 1, 8192 bytes)
13
[ 2.496917] NET: Registered protocol family 1
14
qemu-system-aarch64: Bad icount read
15
16
Reported-by: Thomas Huth <thuth@redhat.com>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
19
Message-id: 20220923123412.1214041-2-peter.maydell@linaro.org
9
---
20
---
10
hw/arm/exynos4_boards.c | 5 +++--
21
target/arm/helper.c | 12 ++++++------
11
1 file changed, 3 insertions(+), 2 deletions(-)
22
1 file changed, 6 insertions(+), 6 deletions(-)
12
23
13
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
24
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/exynos4_boards.c
26
--- a/target/arm/helper.c
16
+++ b/hw/arm/exynos4_boards.c
27
+++ b/target/arm/helper.c
17
@@ -XXX,XX +XXX,XX @@
28
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
18
*/
29
* or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
19
30
*/
20
#include "qemu/osdep.h"
31
{ .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
21
+#include "qemu/units.h"
32
- .access = PL0_RW, .type = ARM_CP_ALIAS,
22
#include "qapi/error.h"
33
+ .access = PL0_RW, .type = ARM_CP_ALIAS | ARM_CP_IO,
23
#include "qemu/error-report.h"
34
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
24
#include "qemu-common.h"
35
.writefn = pmcntenset_write,
25
@@ -XXX,XX +XXX,XX @@ static int exynos4_board_smp_bootreg_addr[EXYNOS4_NUM_OF_BOARDS] = {
36
.accessfn = pmreg_access,
26
};
37
.raw_writefn = raw_write },
27
38
- { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64,
28
static unsigned long exynos4_board_ram_size[EXYNOS4_NUM_OF_BOARDS] = {
39
+ { .name = "PMCNTENSET_EL0", .state = ARM_CP_STATE_AA64, .type = ARM_CP_IO,
29
- [EXYNOS4_BOARD_NURI] = 0x40000000,
40
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 1,
30
- [EXYNOS4_BOARD_SMDKC210] = 0x40000000,
41
.access = PL0_RW, .accessfn = pmreg_access,
31
+ [EXYNOS4_BOARD_NURI] = 1 * GiB,
42
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten), .resetvalue = 0,
32
+ [EXYNOS4_BOARD_SMDKC210] = 1 * GiB,
43
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
33
};
44
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmcnten),
34
45
.accessfn = pmreg_access,
35
static struct arm_boot_info exynos4_board_binfo = {
46
.writefn = pmcntenclr_write,
47
- .type = ARM_CP_ALIAS },
48
+ .type = ARM_CP_ALIAS | ARM_CP_IO },
49
{ .name = "PMCNTENCLR_EL0", .state = ARM_CP_STATE_AA64,
50
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 2,
51
.access = PL0_RW, .accessfn = pmreg_access,
52
- .type = ARM_CP_ALIAS,
53
+ .type = ARM_CP_ALIAS | ARM_CP_IO,
54
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
55
.writefn = pmcntenclr_write },
56
{ .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
57
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
58
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
59
.resetvalue = 0,
60
.access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
61
- { .name = "SDCR", .type = ARM_CP_ALIAS,
62
+ { .name = "SDCR", .type = ARM_CP_ALIAS | ARM_CP_IO,
63
.cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
64
.access = PL1_RW, .accessfn = access_trap_aa32s_el1,
65
.writefn = sdcr_write,
66
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
67
* value is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N.
68
*/
69
ARMCPRegInfo mdcr_el2 = {
70
- .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
71
+ .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, .type = ARM_CP_IO,
72
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1,
73
.writefn = mdcr_el2_write,
74
.access = PL2_RW, .resetvalue = pmu_num_counters(env),
36
--
75
--
37
2.20.1
76
2.25.1
38
39
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/12] hw/arm/exynos4210: QOM'ify the Exynos4210 SoC
[PULL 02/10] target/arm: Make writes to MDCR_EL3 use PMU start/finish calls
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
In commit 01765386a88868 we fixed a bug where we weren't correctly
2
bracketing changes to some registers with pmu_op_start() and
3
pmu_op_finish() calls for changes which affect whether the PMU
4
counters might be enabled. However, we missed the case of writes to
5
the AArch64 MDCR_EL3 register, because (unlike its AArch32
6
counterpart) they are currently done directly to the CPU state struct
7
without going through the sdcr_write() function.
2
8
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Give MDCR_EL3 a writefn which handles the PMU start/finish calls.
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
The SDCR writefn then simplfies to "call the MDCR_EL3 writefn after
5
Message-id: 20190520214342.13709-5-philmd@redhat.com
11
masking off the bits which don't exist in the AArch32 register".
12
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20220923123412.1214041-3-peter.maydell@linaro.org
7
---
16
---
8
include/hw/arm/exynos4210.h | 9 +++++++--
17
target/arm/helper.c | 18 ++++++++++++++----
9
hw/arm/exynos4210.c | 28 ++++++++++++++++++++++++----
18
1 file changed, 14 insertions(+), 4 deletions(-)
10
hw/arm/exynos4_boards.c | 9 ++++++---
11
3 files changed, 37 insertions(+), 9 deletions(-)
12
19
13
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
20
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/arm/exynos4210.h
22
--- a/target/arm/helper.c
16
+++ b/include/hw/arm/exynos4210.h
23
+++ b/target/arm/helper.c
17
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210Irq {
24
@@ -XXX,XX +XXX,XX @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
18
} Exynos4210Irq;
25
}
19
20
typedef struct Exynos4210State {
21
+ /*< private >*/
22
+ SysBusDevice parent_obj;
23
+ /*< public >*/
24
ARMCPU *cpu[EXYNOS4210_NCPUS];
25
Exynos4210Irq irqs;
26
qemu_irq *irq_table;
27
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210State {
28
I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
29
} Exynos4210State;
30
31
+#define TYPE_EXYNOS4210_SOC "exynos4210"
32
+#define EXYNOS4210_SOC(obj) \
33
+ OBJECT_CHECK(Exynos4210State, obj, TYPE_EXYNOS4210_SOC)
34
+
35
void exynos4210_write_secondary(ARMCPU *cpu,
36
const struct arm_boot_info *info);
37
38
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem);
39
-
40
/* Initialize exynos4210 IRQ subsystem stub */
41
qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
42
43
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/arm/exynos4210.c
46
+++ b/hw/arm/exynos4210.c
47
@@ -XXX,XX +XXX,XX @@ static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
48
sysbus_connect_irq(busdev, 0, irq);
49
}
26
}
50
27
51
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
28
-static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
52
+static void exynos4210_realize(DeviceState *socdev, Error **errp)
29
- uint64_t value)
30
+static void mdcr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
31
+ uint64_t value)
53
{
32
{
54
- Exynos4210State *s = g_new0(Exynos4210State, 1);
33
/*
55
+ Exynos4210State *s = EXYNOS4210_SOC(socdev);
34
* Some MDCR_EL3 bits affect whether PMU counters are running:
56
+ MemoryRegion *system_mem = get_system_memory();
35
@@ -XXX,XX +XXX,XX @@ static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
57
qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
36
if (pmu_op) {
58
SysBusDevice *busdev;
37
pmu_op_start(env);
59
DeviceState *dev;
38
}
60
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
39
- env->cp15.mdcr_el3 = value & SDCR_VALID_MASK;
61
qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
40
+ env->cp15.mdcr_el3 = value;
62
pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
41
if (pmu_op) {
63
qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
42
pmu_op_finish(env);
64
-
43
}
65
- return s;
66
}
44
}
67
+
45
68
+static void exynos4210_class_init(ObjectClass *klass, void *data)
46
+static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
47
+ uint64_t value)
69
+{
48
+{
70
+ DeviceClass *dc = DEVICE_CLASS(klass);
49
+ /* Not all bits defined for MDCR_EL3 exist in the AArch32 SDCR */
71
+
50
+ mdcr_el3_write(env, ri, value & SDCR_VALID_MASK);
72
+ dc->realize = exynos4210_realize;
73
+}
51
+}
74
+
52
+
75
+static const TypeInfo exynos4210_info = {
53
static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri,
76
+ .name = TYPE_EXYNOS4210_SOC,
54
uint64_t value)
77
+ .parent = TYPE_SYS_BUS_DEVICE,
55
{
78
+ .instance_size = sizeof(Exynos4210State),
56
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
79
+ .class_init = exynos4210_class_init,
57
.access = PL2_RW,
80
+};
58
.fieldoffset = offsetof(CPUARMState, banked_spsr[BANK_FIQ]) },
81
+
59
{ .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64,
82
+static void exynos4210_register_types(void)
60
+ .type = ARM_CP_IO,
83
+{
61
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
84
+ type_register_static(&exynos4210_info);
62
.resetvalue = 0,
85
+}
63
- .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
86
+
64
+ .access = PL3_RW,
87
+type_init(exynos4210_register_types)
65
+ .writefn = mdcr_el3_write,
88
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
66
+ .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el3) },
89
index XXXXXXX..XXXXXXX 100644
67
{ .name = "SDCR", .type = ARM_CP_ALIAS | ARM_CP_IO,
90
--- a/hw/arm/exynos4_boards.c
68
.cp = 15, .opc1 = 0, .crn = 1, .crm = 3, .opc2 = 1,
91
+++ b/hw/arm/exynos4_boards.c
69
.access = PL1_RW, .accessfn = access_trap_aa32s_el1,
92
@@ -XXX,XX +XXX,XX @@ typedef enum Exynos4BoardType {
93
} Exynos4BoardType;
94
95
typedef struct Exynos4BoardState {
96
- Exynos4210State *soc;
97
+ Exynos4210State soc;
98
MemoryRegion dram0_mem;
99
MemoryRegion dram1_mem;
100
} Exynos4BoardState;
101
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
102
exynos4_boards_init_ram(s, get_system_memory(),
103
exynos4_board_ram_size[board_type]);
104
105
- s->soc = exynos4210_init(get_system_memory());
106
+ object_initialize(&s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC);
107
+ qdev_set_parent_bus(DEVICE(&s->soc), sysbus_get_default());
108
+ object_property_set_bool(OBJECT(&s->soc), true, "realized",
109
+ &error_fatal);
110
111
return s;
112
}
113
@@ -XXX,XX +XXX,XX @@ static void smdkc210_init(MachineState *machine)
114
EXYNOS4_BOARD_SMDKC210);
115
116
lan9215_init(SMDK_LAN9118_BASE_ADDR,
117
- qemu_irq_invert(s->soc->irq_table[exynos4210_get_irq(37, 1)]));
118
+ qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)]));
119
arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo);
120
}
121
122
--
70
--
123
2.20.1
71
2.25.1
124
125
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/12] hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3
[PULL 03/10] target/arm: Update SDCR_VALID_MASK to include SCCD
1
The ICC_CTLR_EL3 register includes some bits which are aliases
1
Our SDCR_VALID_MASK doesn't include all of the bits which are defined
2
of bits in the ICC_CTLR_EL1(S) and (NS) registers. QEMU chooses
2
by the current architecture. In particular in commit 0b42f4fab9d3 we
3
to keep those bits in the cs->icc_ctlr_el1[] struct fields.
3
forgot to add SCCD, which meant that an AArch32 guest couldn't
4
Unfortunately a missing '~' in the code to update the bits
4
actually use the SCCD bit to disable counting in Secure state.
5
in those fields meant that writing to ICC_CTLR_EL3 would corrupt
5
6
the ICC_CLTR_EL1 register values.
6
Add all the currently defined bits; we don't implement all of them,
7
but this makes them be reads-as-written, which is architecturally
8
valid and matches how we currently handle most of the others in the
9
mask.
7
10
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20190520162809.2677-5-peter.maydell@linaro.org
13
Message-id: 20220923123412.1214041-4-peter.maydell@linaro.org
11
---
14
---
12
hw/intc/arm_gicv3_cpuif.c | 4 ++--
15
target/arm/cpu.h | 8 +++++++-
13
1 file changed, 2 insertions(+), 2 deletions(-)
16
1 file changed, 7 insertions(+), 1 deletion(-)
14
17
15
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
18
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/intc/arm_gicv3_cpuif.c
20
--- a/target/arm/cpu.h
18
+++ b/hw/intc/arm_gicv3_cpuif.c
21
+++ b/target/arm/cpu.h
19
@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
22
@@ -XXX,XX +XXX,XX @@ FIELD(CPTR_EL3, TTA, 20, 1)
20
trace_gicv3_icc_ctlr_el3_write(gicv3_redist_affid(cs), value);
23
FIELD(CPTR_EL3, TAM, 30, 1)
21
24
FIELD(CPTR_EL3, TCPAC, 31, 1)
22
/* *_EL1NS and *_EL1S bits are aliases into the ICC_CTLR_EL1 bits. */
25
23
- cs->icc_ctlr_el1[GICV3_NS] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
26
+#define MDCR_MTPME (1U << 28)
24
+ cs->icc_ctlr_el1[GICV3_NS] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
27
+#define MDCR_TDCC (1U << 27)
25
if (value & ICC_CTLR_EL3_EOIMODE_EL1NS) {
28
#define MDCR_HLP (1U << 26) /* MDCR_EL2 */
26
cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE;
29
#define MDCR_SCCD (1U << 23) /* MDCR_EL3 */
27
}
30
#define MDCR_HCCD (1U << 23) /* MDCR_EL2 */
28
@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
31
#define MDCR_EPMAD (1U << 21)
29
cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_CBPR;
32
#define MDCR_EDAD (1U << 20)
30
}
33
+#define MDCR_TTRF (1U << 19)
31
34
+#define MDCR_STE (1U << 18) /* MDCR_EL3 */
32
- cs->icc_ctlr_el1[GICV3_S] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
35
#define MDCR_SPME (1U << 17) /* MDCR_EL3 */
33
+ cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
36
#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */
34
if (value & ICC_CTLR_EL3_EOIMODE_EL1S) {
37
#define MDCR_SDD (1U << 16)
35
cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_EOIMODE;
38
@@ -XXX,XX +XXX,XX @@ FIELD(CPTR_EL3, TCPAC, 31, 1)
36
}
39
#define MDCR_HPMN (0x1fU)
40
41
/* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
42
-#define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
43
+#define SDCR_VALID_MASK (MDCR_MTPME | MDCR_TDCC | MDCR_SCCD | \
44
+ MDCR_EPMAD | MDCR_EDAD | MDCR_TTRF | \
45
+ MDCR_STE | MDCR_SPME | MDCR_SPD)
46
47
#define CPSR_M (0x1fU)
48
#define CPSR_T (1U << 5)
37
--
49
--
38
2.20.1
50
2.25.1
39
40
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/12] arm: Remove unnecessary includes of hw/arm/arm.h
[PULL 04/10] target/arm: Rearrange cpu64.c so all the CPU initfns are together
1
The hw/arm/arm.h header now only includes declarations relating
1
cpu64.c has ended up in a slightly odd order -- it starts with the
2
to boot.c code, so it is only needed by Arm board or SoC code.
2
initfns for most of the models-real-hardware CPUs; after that comes a
3
Remove some unnecessary inclusions of it from target/arm files
3
bunch of support code for SVE, SME, pauth and LPA2 properties. Then
4
and from hw/intc/armv7m_nvic.c.
4
come the initfns for the 'host' and 'max' CPU types, and then after
5
that one more models-real-hardware CPU initfn, for a64fx. (This
6
ordering is partly historical and partly required because a64fx needs
7
the SVE properties.)
8
9
Reorder the file into:
10
* CPU property support functions
11
* initfns for real hardware CPUs
12
* initfns for host and max
13
* class boilerplate
5
14
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
16
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20190516163857.6430-3-peter.maydell@linaro.org
10
---
18
---
11
hw/intc/armv7m_nvic.c | 1 -
19
target/arm/cpu64.c | 712 ++++++++++++++++++++++-----------------------
12
target/arm/arm-semi.c | 1 -
20
1 file changed, 356 insertions(+), 356 deletions(-)
13
target/arm/cpu.c | 1 -
14
target/arm/cpu64.c | 1 -
15
target/arm/kvm.c | 1 -
16
target/arm/kvm32.c | 1 -
17
target/arm/kvm64.c | 1 -
18
7 files changed, 7 deletions(-)
19
21
20
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/intc/armv7m_nvic.c
23
+++ b/hw/intc/armv7m_nvic.c
24
@@ -XXX,XX +XXX,XX @@
25
#include "cpu.h"
26
#include "hw/sysbus.h"
27
#include "qemu/timer.h"
28
-#include "hw/arm/arm.h"
29
#include "hw/intc/armv7m_nvic.h"
30
#include "target/arm/cpu.h"
31
#include "exec/exec-all.h"
32
diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/arm-semi.c
35
+++ b/target/arm/arm-semi.c
36
@@ -XXX,XX +XXX,XX @@
37
#else
38
#include "qemu-common.h"
39
#include "exec/gdbstub.h"
40
-#include "hw/arm/arm.h"
41
#include "qemu/cutils.h"
42
#endif
43
44
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/cpu.c
47
+++ b/target/arm/cpu.c
48
@@ -XXX,XX +XXX,XX @@
49
#if !defined(CONFIG_USER_ONLY)
50
#include "hw/loader.h"
51
#endif
52
-#include "hw/arm/arm.h"
53
#include "sysemu/sysemu.h"
54
#include "sysemu/hw_accel.h"
55
#include "kvm_arm.h"
56
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
22
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
57
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
58
--- a/target/arm/cpu64.c
24
--- a/target/arm/cpu64.c
59
+++ b/target/arm/cpu64.c
25
+++ b/target/arm/cpu64.c
60
@@ -XXX,XX +XXX,XX @@
26
@@ -XXX,XX +XXX,XX @@ static void aarch64_a35_initfn(Object *obj)
61
#if !defined(CONFIG_USER_ONLY)
27
define_cortex_a72_a57_a53_cp_reginfo(cpu);
62
#include "hw/loader.h"
28
}
63
#endif
29
64
-#include "hw/arm/arm.h"
30
-static void aarch64_a57_initfn(Object *obj)
65
#include "sysemu/sysemu.h"
31
-{
66
#include "sysemu/kvm.h"
32
- ARMCPU *cpu = ARM_CPU(obj);
67
#include "kvm_arm.h"
33
-
68
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
34
- cpu->dtb_compatible = "arm,cortex-a57";
69
index XXXXXXX..XXXXXXX 100644
35
- set_feature(&cpu->env, ARM_FEATURE_V8);
70
--- a/target/arm/kvm.c
36
- set_feature(&cpu->env, ARM_FEATURE_NEON);
71
+++ b/target/arm/kvm.c
37
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
72
@@ -XXX,XX +XXX,XX @@
38
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
73
#include "cpu.h"
39
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
74
#include "trace.h"
40
- set_feature(&cpu->env, ARM_FEATURE_EL2);
75
#include "internals.h"
41
- set_feature(&cpu->env, ARM_FEATURE_EL3);
76
-#include "hw/arm/arm.h"
42
- set_feature(&cpu->env, ARM_FEATURE_PMU);
77
#include "hw/pci/pci.h"
43
- cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
78
#include "exec/memattrs.h"
44
- cpu->midr = 0x411fd070;
79
#include "exec/address-spaces.h"
45
- cpu->revidr = 0x00000000;
80
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
46
- cpu->reset_fpsid = 0x41034070;
81
index XXXXXXX..XXXXXXX 100644
47
- cpu->isar.mvfr0 = 0x10110222;
82
--- a/target/arm/kvm32.c
48
- cpu->isar.mvfr1 = 0x12111111;
83
+++ b/target/arm/kvm32.c
49
- cpu->isar.mvfr2 = 0x00000043;
84
@@ -XXX,XX +XXX,XX @@
50
- cpu->ctr = 0x8444c004;
85
#include "sysemu/kvm.h"
51
- cpu->reset_sctlr = 0x00c50838;
86
#include "kvm_arm.h"
52
- cpu->isar.id_pfr0 = 0x00000131;
87
#include "internals.h"
53
- cpu->isar.id_pfr1 = 0x00011011;
88
-#include "hw/arm/arm.h"
54
- cpu->isar.id_dfr0 = 0x03010066;
89
#include "qemu/log.h"
55
- cpu->id_afr0 = 0x00000000;
90
56
- cpu->isar.id_mmfr0 = 0x10101105;
91
static inline void set_feature(uint64_t *features, int feature)
57
- cpu->isar.id_mmfr1 = 0x40000000;
92
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
58
- cpu->isar.id_mmfr2 = 0x01260000;
93
index XXXXXXX..XXXXXXX 100644
59
- cpu->isar.id_mmfr3 = 0x02102211;
94
--- a/target/arm/kvm64.c
60
- cpu->isar.id_isar0 = 0x02101110;
95
+++ b/target/arm/kvm64.c
61
- cpu->isar.id_isar1 = 0x13112111;
96
@@ -XXX,XX +XXX,XX @@
62
- cpu->isar.id_isar2 = 0x21232042;
97
#include "sysemu/kvm.h"
63
- cpu->isar.id_isar3 = 0x01112131;
98
#include "kvm_arm.h"
64
- cpu->isar.id_isar4 = 0x00011142;
99
#include "internals.h"
65
- cpu->isar.id_isar5 = 0x00011121;
100
-#include "hw/arm/arm.h"
66
- cpu->isar.id_isar6 = 0;
101
67
- cpu->isar.id_aa64pfr0 = 0x00002222;
102
static bool have_guest_debug;
68
- cpu->isar.id_aa64dfr0 = 0x10305106;
103
69
- cpu->isar.id_aa64isar0 = 0x00011120;
70
- cpu->isar.id_aa64mmfr0 = 0x00001124;
71
- cpu->isar.dbgdidr = 0x3516d000;
72
- cpu->isar.dbgdevid = 0x01110f13;
73
- cpu->isar.dbgdevid1 = 0x2;
74
- cpu->isar.reset_pmcr_el0 = 0x41013000;
75
- cpu->clidr = 0x0a200023;
76
- cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
77
- cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
78
- cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
79
- cpu->dcz_blocksize = 4; /* 64 bytes */
80
- cpu->gic_num_lrs = 4;
81
- cpu->gic_vpribits = 5;
82
- cpu->gic_vprebits = 5;
83
- cpu->gic_pribits = 5;
84
- define_cortex_a72_a57_a53_cp_reginfo(cpu);
85
-}
86
-
87
-static void aarch64_a53_initfn(Object *obj)
88
-{
89
- ARMCPU *cpu = ARM_CPU(obj);
90
-
91
- cpu->dtb_compatible = "arm,cortex-a53";
92
- set_feature(&cpu->env, ARM_FEATURE_V8);
93
- set_feature(&cpu->env, ARM_FEATURE_NEON);
94
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
95
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
96
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
97
- set_feature(&cpu->env, ARM_FEATURE_EL2);
98
- set_feature(&cpu->env, ARM_FEATURE_EL3);
99
- set_feature(&cpu->env, ARM_FEATURE_PMU);
100
- cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
101
- cpu->midr = 0x410fd034;
102
- cpu->revidr = 0x00000000;
103
- cpu->reset_fpsid = 0x41034070;
104
- cpu->isar.mvfr0 = 0x10110222;
105
- cpu->isar.mvfr1 = 0x12111111;
106
- cpu->isar.mvfr2 = 0x00000043;
107
- cpu->ctr = 0x84448004; /* L1Ip = VIPT */
108
- cpu->reset_sctlr = 0x00c50838;
109
- cpu->isar.id_pfr0 = 0x00000131;
110
- cpu->isar.id_pfr1 = 0x00011011;
111
- cpu->isar.id_dfr0 = 0x03010066;
112
- cpu->id_afr0 = 0x00000000;
113
- cpu->isar.id_mmfr0 = 0x10101105;
114
- cpu->isar.id_mmfr1 = 0x40000000;
115
- cpu->isar.id_mmfr2 = 0x01260000;
116
- cpu->isar.id_mmfr3 = 0x02102211;
117
- cpu->isar.id_isar0 = 0x02101110;
118
- cpu->isar.id_isar1 = 0x13112111;
119
- cpu->isar.id_isar2 = 0x21232042;
120
- cpu->isar.id_isar3 = 0x01112131;
121
- cpu->isar.id_isar4 = 0x00011142;
122
- cpu->isar.id_isar5 = 0x00011121;
123
- cpu->isar.id_isar6 = 0;
124
- cpu->isar.id_aa64pfr0 = 0x00002222;
125
- cpu->isar.id_aa64dfr0 = 0x10305106;
126
- cpu->isar.id_aa64isar0 = 0x00011120;
127
- cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
128
- cpu->isar.dbgdidr = 0x3516d000;
129
- cpu->isar.dbgdevid = 0x00110f13;
130
- cpu->isar.dbgdevid1 = 0x1;
131
- cpu->isar.reset_pmcr_el0 = 0x41033000;
132
- cpu->clidr = 0x0a200023;
133
- cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
134
- cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
135
- cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
136
- cpu->dcz_blocksize = 4; /* 64 bytes */
137
- cpu->gic_num_lrs = 4;
138
- cpu->gic_vpribits = 5;
139
- cpu->gic_vprebits = 5;
140
- cpu->gic_pribits = 5;
141
- define_cortex_a72_a57_a53_cp_reginfo(cpu);
142
-}
143
-
144
-static void aarch64_a72_initfn(Object *obj)
145
-{
146
- ARMCPU *cpu = ARM_CPU(obj);
147
-
148
- cpu->dtb_compatible = "arm,cortex-a72";
149
- set_feature(&cpu->env, ARM_FEATURE_V8);
150
- set_feature(&cpu->env, ARM_FEATURE_NEON);
151
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
152
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
153
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
154
- set_feature(&cpu->env, ARM_FEATURE_EL2);
155
- set_feature(&cpu->env, ARM_FEATURE_EL3);
156
- set_feature(&cpu->env, ARM_FEATURE_PMU);
157
- cpu->midr = 0x410fd083;
158
- cpu->revidr = 0x00000000;
159
- cpu->reset_fpsid = 0x41034080;
160
- cpu->isar.mvfr0 = 0x10110222;
161
- cpu->isar.mvfr1 = 0x12111111;
162
- cpu->isar.mvfr2 = 0x00000043;
163
- cpu->ctr = 0x8444c004;
164
- cpu->reset_sctlr = 0x00c50838;
165
- cpu->isar.id_pfr0 = 0x00000131;
166
- cpu->isar.id_pfr1 = 0x00011011;
167
- cpu->isar.id_dfr0 = 0x03010066;
168
- cpu->id_afr0 = 0x00000000;
169
- cpu->isar.id_mmfr0 = 0x10201105;
170
- cpu->isar.id_mmfr1 = 0x40000000;
171
- cpu->isar.id_mmfr2 = 0x01260000;
172
- cpu->isar.id_mmfr3 = 0x02102211;
173
- cpu->isar.id_isar0 = 0x02101110;
174
- cpu->isar.id_isar1 = 0x13112111;
175
- cpu->isar.id_isar2 = 0x21232042;
176
- cpu->isar.id_isar3 = 0x01112131;
177
- cpu->isar.id_isar4 = 0x00011142;
178
- cpu->isar.id_isar5 = 0x00011121;
179
- cpu->isar.id_aa64pfr0 = 0x00002222;
180
- cpu->isar.id_aa64dfr0 = 0x10305106;
181
- cpu->isar.id_aa64isar0 = 0x00011120;
182
- cpu->isar.id_aa64mmfr0 = 0x00001124;
183
- cpu->isar.dbgdidr = 0x3516d000;
184
- cpu->isar.dbgdevid = 0x01110f13;
185
- cpu->isar.dbgdevid1 = 0x2;
186
- cpu->isar.reset_pmcr_el0 = 0x41023000;
187
- cpu->clidr = 0x0a200023;
188
- cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
189
- cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
190
- cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
191
- cpu->dcz_blocksize = 4; /* 64 bytes */
192
- cpu->gic_num_lrs = 4;
193
- cpu->gic_vpribits = 5;
194
- cpu->gic_vprebits = 5;
195
- cpu->gic_pribits = 5;
196
- define_cortex_a72_a57_a53_cp_reginfo(cpu);
197
-}
198
-
199
-static void aarch64_a76_initfn(Object *obj)
200
-{
201
- ARMCPU *cpu = ARM_CPU(obj);
202
-
203
- cpu->dtb_compatible = "arm,cortex-a76";
204
- set_feature(&cpu->env, ARM_FEATURE_V8);
205
- set_feature(&cpu->env, ARM_FEATURE_NEON);
206
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
207
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
208
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
209
- set_feature(&cpu->env, ARM_FEATURE_EL2);
210
- set_feature(&cpu->env, ARM_FEATURE_EL3);
211
- set_feature(&cpu->env, ARM_FEATURE_PMU);
212
-
213
- /* Ordered by B2.4 AArch64 registers by functional group */
214
- cpu->clidr = 0x82000023;
215
- cpu->ctr = 0x8444C004;
216
- cpu->dcz_blocksize = 4;
217
- cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
218
- cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
219
- cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
220
- cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
221
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
222
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
223
- cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
224
- cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
225
- cpu->id_afr0 = 0x00000000;
226
- cpu->isar.id_dfr0 = 0x04010088;
227
- cpu->isar.id_isar0 = 0x02101110;
228
- cpu->isar.id_isar1 = 0x13112111;
229
- cpu->isar.id_isar2 = 0x21232042;
230
- cpu->isar.id_isar3 = 0x01112131;
231
- cpu->isar.id_isar4 = 0x00010142;
232
- cpu->isar.id_isar5 = 0x01011121;
233
- cpu->isar.id_isar6 = 0x00000010;
234
- cpu->isar.id_mmfr0 = 0x10201105;
235
- cpu->isar.id_mmfr1 = 0x40000000;
236
- cpu->isar.id_mmfr2 = 0x01260000;
237
- cpu->isar.id_mmfr3 = 0x02122211;
238
- cpu->isar.id_mmfr4 = 0x00021110;
239
- cpu->isar.id_pfr0 = 0x10010131;
240
- cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
241
- cpu->isar.id_pfr2 = 0x00000011;
242
- cpu->midr = 0x414fd0b1; /* r4p1 */
243
- cpu->revidr = 0;
244
-
245
- /* From B2.18 CCSIDR_EL1 */
246
- cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
247
- cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
248
- cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
249
-
250
- /* From B2.93 SCTLR_EL3 */
251
- cpu->reset_sctlr = 0x30c50838;
252
-
253
- /* From B4.23 ICH_VTR_EL2 */
254
- cpu->gic_num_lrs = 4;
255
- cpu->gic_vpribits = 5;
256
- cpu->gic_vprebits = 5;
257
- cpu->gic_pribits = 5;
258
-
259
- /* From B5.1 AdvSIMD AArch64 register summary */
260
- cpu->isar.mvfr0 = 0x10110222;
261
- cpu->isar.mvfr1 = 0x13211111;
262
- cpu->isar.mvfr2 = 0x00000043;
263
-
264
- /* From D5.1 AArch64 PMU register summary */
265
- cpu->isar.reset_pmcr_el0 = 0x410b3000;
266
-}
267
-
268
-static void aarch64_neoverse_n1_initfn(Object *obj)
269
-{
270
- ARMCPU *cpu = ARM_CPU(obj);
271
-
272
- cpu->dtb_compatible = "arm,neoverse-n1";
273
- set_feature(&cpu->env, ARM_FEATURE_V8);
274
- set_feature(&cpu->env, ARM_FEATURE_NEON);
275
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
276
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
277
- set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
278
- set_feature(&cpu->env, ARM_FEATURE_EL2);
279
- set_feature(&cpu->env, ARM_FEATURE_EL3);
280
- set_feature(&cpu->env, ARM_FEATURE_PMU);
281
-
282
- /* Ordered by B2.4 AArch64 registers by functional group */
283
- cpu->clidr = 0x82000023;
284
- cpu->ctr = 0x8444c004;
285
- cpu->dcz_blocksize = 4;
286
- cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
287
- cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
288
- cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
289
- cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
290
- cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
291
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
292
- cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
293
- cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
294
- cpu->id_afr0 = 0x00000000;
295
- cpu->isar.id_dfr0 = 0x04010088;
296
- cpu->isar.id_isar0 = 0x02101110;
297
- cpu->isar.id_isar1 = 0x13112111;
298
- cpu->isar.id_isar2 = 0x21232042;
299
- cpu->isar.id_isar3 = 0x01112131;
300
- cpu->isar.id_isar4 = 0x00010142;
301
- cpu->isar.id_isar5 = 0x01011121;
302
- cpu->isar.id_isar6 = 0x00000010;
303
- cpu->isar.id_mmfr0 = 0x10201105;
304
- cpu->isar.id_mmfr1 = 0x40000000;
305
- cpu->isar.id_mmfr2 = 0x01260000;
306
- cpu->isar.id_mmfr3 = 0x02122211;
307
- cpu->isar.id_mmfr4 = 0x00021110;
308
- cpu->isar.id_pfr0 = 0x10010131;
309
- cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
310
- cpu->isar.id_pfr2 = 0x00000011;
311
- cpu->midr = 0x414fd0c1; /* r4p1 */
312
- cpu->revidr = 0;
313
-
314
- /* From B2.23 CCSIDR_EL1 */
315
- cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
316
- cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
317
- cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
318
-
319
- /* From B2.98 SCTLR_EL3 */
320
- cpu->reset_sctlr = 0x30c50838;
321
-
322
- /* From B4.23 ICH_VTR_EL2 */
323
- cpu->gic_num_lrs = 4;
324
- cpu->gic_vpribits = 5;
325
- cpu->gic_vprebits = 5;
326
- cpu->gic_pribits = 5;
327
-
328
- /* From B5.1 AdvSIMD AArch64 register summary */
329
- cpu->isar.mvfr0 = 0x10110222;
330
- cpu->isar.mvfr1 = 0x13211111;
331
- cpu->isar.mvfr2 = 0x00000043;
332
-
333
- /* From D5.1 AArch64 PMU register summary */
334
- cpu->isar.reset_pmcr_el0 = 0x410c3000;
335
-}
336
-
337
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
338
{
339
/*
340
@@ -XXX,XX +XXX,XX @@ void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
341
cpu->isar.id_aa64mmfr0 = t;
342
}
343
344
+static void aarch64_a57_initfn(Object *obj)
345
+{
346
+ ARMCPU *cpu = ARM_CPU(obj);
347
+
348
+ cpu->dtb_compatible = "arm,cortex-a57";
349
+ set_feature(&cpu->env, ARM_FEATURE_V8);
350
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
351
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
352
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
353
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
354
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
355
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
356
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
357
+ cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
358
+ cpu->midr = 0x411fd070;
359
+ cpu->revidr = 0x00000000;
360
+ cpu->reset_fpsid = 0x41034070;
361
+ cpu->isar.mvfr0 = 0x10110222;
362
+ cpu->isar.mvfr1 = 0x12111111;
363
+ cpu->isar.mvfr2 = 0x00000043;
364
+ cpu->ctr = 0x8444c004;
365
+ cpu->reset_sctlr = 0x00c50838;
366
+ cpu->isar.id_pfr0 = 0x00000131;
367
+ cpu->isar.id_pfr1 = 0x00011011;
368
+ cpu->isar.id_dfr0 = 0x03010066;
369
+ cpu->id_afr0 = 0x00000000;
370
+ cpu->isar.id_mmfr0 = 0x10101105;
371
+ cpu->isar.id_mmfr1 = 0x40000000;
372
+ cpu->isar.id_mmfr2 = 0x01260000;
373
+ cpu->isar.id_mmfr3 = 0x02102211;
374
+ cpu->isar.id_isar0 = 0x02101110;
375
+ cpu->isar.id_isar1 = 0x13112111;
376
+ cpu->isar.id_isar2 = 0x21232042;
377
+ cpu->isar.id_isar3 = 0x01112131;
378
+ cpu->isar.id_isar4 = 0x00011142;
379
+ cpu->isar.id_isar5 = 0x00011121;
380
+ cpu->isar.id_isar6 = 0;
381
+ cpu->isar.id_aa64pfr0 = 0x00002222;
382
+ cpu->isar.id_aa64dfr0 = 0x10305106;
383
+ cpu->isar.id_aa64isar0 = 0x00011120;
384
+ cpu->isar.id_aa64mmfr0 = 0x00001124;
385
+ cpu->isar.dbgdidr = 0x3516d000;
386
+ cpu->isar.dbgdevid = 0x01110f13;
387
+ cpu->isar.dbgdevid1 = 0x2;
388
+ cpu->isar.reset_pmcr_el0 = 0x41013000;
389
+ cpu->clidr = 0x0a200023;
390
+ cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
391
+ cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
392
+ cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
393
+ cpu->dcz_blocksize = 4; /* 64 bytes */
394
+ cpu->gic_num_lrs = 4;
395
+ cpu->gic_vpribits = 5;
396
+ cpu->gic_vprebits = 5;
397
+ cpu->gic_pribits = 5;
398
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
399
+}
400
+
401
+static void aarch64_a53_initfn(Object *obj)
402
+{
403
+ ARMCPU *cpu = ARM_CPU(obj);
404
+
405
+ cpu->dtb_compatible = "arm,cortex-a53";
406
+ set_feature(&cpu->env, ARM_FEATURE_V8);
407
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
408
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
409
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
410
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
411
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
412
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
413
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
414
+ cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
415
+ cpu->midr = 0x410fd034;
416
+ cpu->revidr = 0x00000000;
417
+ cpu->reset_fpsid = 0x41034070;
418
+ cpu->isar.mvfr0 = 0x10110222;
419
+ cpu->isar.mvfr1 = 0x12111111;
420
+ cpu->isar.mvfr2 = 0x00000043;
421
+ cpu->ctr = 0x84448004; /* L1Ip = VIPT */
422
+ cpu->reset_sctlr = 0x00c50838;
423
+ cpu->isar.id_pfr0 = 0x00000131;
424
+ cpu->isar.id_pfr1 = 0x00011011;
425
+ cpu->isar.id_dfr0 = 0x03010066;
426
+ cpu->id_afr0 = 0x00000000;
427
+ cpu->isar.id_mmfr0 = 0x10101105;
428
+ cpu->isar.id_mmfr1 = 0x40000000;
429
+ cpu->isar.id_mmfr2 = 0x01260000;
430
+ cpu->isar.id_mmfr3 = 0x02102211;
431
+ cpu->isar.id_isar0 = 0x02101110;
432
+ cpu->isar.id_isar1 = 0x13112111;
433
+ cpu->isar.id_isar2 = 0x21232042;
434
+ cpu->isar.id_isar3 = 0x01112131;
435
+ cpu->isar.id_isar4 = 0x00011142;
436
+ cpu->isar.id_isar5 = 0x00011121;
437
+ cpu->isar.id_isar6 = 0;
438
+ cpu->isar.id_aa64pfr0 = 0x00002222;
439
+ cpu->isar.id_aa64dfr0 = 0x10305106;
440
+ cpu->isar.id_aa64isar0 = 0x00011120;
441
+ cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
442
+ cpu->isar.dbgdidr = 0x3516d000;
443
+ cpu->isar.dbgdevid = 0x00110f13;
444
+ cpu->isar.dbgdevid1 = 0x1;
445
+ cpu->isar.reset_pmcr_el0 = 0x41033000;
446
+ cpu->clidr = 0x0a200023;
447
+ cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
448
+ cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
449
+ cpu->ccsidr[2] = 0x707fe07a; /* 1024KB L2 cache */
450
+ cpu->dcz_blocksize = 4; /* 64 bytes */
451
+ cpu->gic_num_lrs = 4;
452
+ cpu->gic_vpribits = 5;
453
+ cpu->gic_vprebits = 5;
454
+ cpu->gic_pribits = 5;
455
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
456
+}
457
+
458
+static void aarch64_a72_initfn(Object *obj)
459
+{
460
+ ARMCPU *cpu = ARM_CPU(obj);
461
+
462
+ cpu->dtb_compatible = "arm,cortex-a72";
463
+ set_feature(&cpu->env, ARM_FEATURE_V8);
464
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
465
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
466
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
467
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
468
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
469
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
470
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
471
+ cpu->midr = 0x410fd083;
472
+ cpu->revidr = 0x00000000;
473
+ cpu->reset_fpsid = 0x41034080;
474
+ cpu->isar.mvfr0 = 0x10110222;
475
+ cpu->isar.mvfr1 = 0x12111111;
476
+ cpu->isar.mvfr2 = 0x00000043;
477
+ cpu->ctr = 0x8444c004;
478
+ cpu->reset_sctlr = 0x00c50838;
479
+ cpu->isar.id_pfr0 = 0x00000131;
480
+ cpu->isar.id_pfr1 = 0x00011011;
481
+ cpu->isar.id_dfr0 = 0x03010066;
482
+ cpu->id_afr0 = 0x00000000;
483
+ cpu->isar.id_mmfr0 = 0x10201105;
484
+ cpu->isar.id_mmfr1 = 0x40000000;
485
+ cpu->isar.id_mmfr2 = 0x01260000;
486
+ cpu->isar.id_mmfr3 = 0x02102211;
487
+ cpu->isar.id_isar0 = 0x02101110;
488
+ cpu->isar.id_isar1 = 0x13112111;
489
+ cpu->isar.id_isar2 = 0x21232042;
490
+ cpu->isar.id_isar3 = 0x01112131;
491
+ cpu->isar.id_isar4 = 0x00011142;
492
+ cpu->isar.id_isar5 = 0x00011121;
493
+ cpu->isar.id_aa64pfr0 = 0x00002222;
494
+ cpu->isar.id_aa64dfr0 = 0x10305106;
495
+ cpu->isar.id_aa64isar0 = 0x00011120;
496
+ cpu->isar.id_aa64mmfr0 = 0x00001124;
497
+ cpu->isar.dbgdidr = 0x3516d000;
498
+ cpu->isar.dbgdevid = 0x01110f13;
499
+ cpu->isar.dbgdevid1 = 0x2;
500
+ cpu->isar.reset_pmcr_el0 = 0x41023000;
501
+ cpu->clidr = 0x0a200023;
502
+ cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
503
+ cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
504
+ cpu->ccsidr[2] = 0x707fe07a; /* 1MB L2 cache */
505
+ cpu->dcz_blocksize = 4; /* 64 bytes */
506
+ cpu->gic_num_lrs = 4;
507
+ cpu->gic_vpribits = 5;
508
+ cpu->gic_vprebits = 5;
509
+ cpu->gic_pribits = 5;
510
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
511
+}
512
+
513
+static void aarch64_a76_initfn(Object *obj)
514
+{
515
+ ARMCPU *cpu = ARM_CPU(obj);
516
+
517
+ cpu->dtb_compatible = "arm,cortex-a76";
518
+ set_feature(&cpu->env, ARM_FEATURE_V8);
519
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
520
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
521
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
522
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
523
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
524
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
525
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
526
+
527
+ /* Ordered by B2.4 AArch64 registers by functional group */
528
+ cpu->clidr = 0x82000023;
529
+ cpu->ctr = 0x8444C004;
530
+ cpu->dcz_blocksize = 4;
531
+ cpu->isar.id_aa64dfr0 = 0x0000000010305408ull;
532
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
533
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
534
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101122ull;
535
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
536
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
537
+ cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
538
+ cpu->isar.id_aa64pfr1 = 0x0000000000000010ull;
539
+ cpu->id_afr0 = 0x00000000;
540
+ cpu->isar.id_dfr0 = 0x04010088;
541
+ cpu->isar.id_isar0 = 0x02101110;
542
+ cpu->isar.id_isar1 = 0x13112111;
543
+ cpu->isar.id_isar2 = 0x21232042;
544
+ cpu->isar.id_isar3 = 0x01112131;
545
+ cpu->isar.id_isar4 = 0x00010142;
546
+ cpu->isar.id_isar5 = 0x01011121;
547
+ cpu->isar.id_isar6 = 0x00000010;
548
+ cpu->isar.id_mmfr0 = 0x10201105;
549
+ cpu->isar.id_mmfr1 = 0x40000000;
550
+ cpu->isar.id_mmfr2 = 0x01260000;
551
+ cpu->isar.id_mmfr3 = 0x02122211;
552
+ cpu->isar.id_mmfr4 = 0x00021110;
553
+ cpu->isar.id_pfr0 = 0x10010131;
554
+ cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
555
+ cpu->isar.id_pfr2 = 0x00000011;
556
+ cpu->midr = 0x414fd0b1; /* r4p1 */
557
+ cpu->revidr = 0;
558
+
559
+ /* From B2.18 CCSIDR_EL1 */
560
+ cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
561
+ cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
562
+ cpu->ccsidr[2] = 0x707fe03a; /* 512KB L2 cache */
563
+
564
+ /* From B2.93 SCTLR_EL3 */
565
+ cpu->reset_sctlr = 0x30c50838;
566
+
567
+ /* From B4.23 ICH_VTR_EL2 */
568
+ cpu->gic_num_lrs = 4;
569
+ cpu->gic_vpribits = 5;
570
+ cpu->gic_vprebits = 5;
571
+ cpu->gic_pribits = 5;
572
+
573
+ /* From B5.1 AdvSIMD AArch64 register summary */
574
+ cpu->isar.mvfr0 = 0x10110222;
575
+ cpu->isar.mvfr1 = 0x13211111;
576
+ cpu->isar.mvfr2 = 0x00000043;
577
+
578
+ /* From D5.1 AArch64 PMU register summary */
579
+ cpu->isar.reset_pmcr_el0 = 0x410b3000;
580
+}
581
+
582
+static void aarch64_a64fx_initfn(Object *obj)
583
+{
584
+ ARMCPU *cpu = ARM_CPU(obj);
585
+
586
+ cpu->dtb_compatible = "arm,a64fx";
587
+ set_feature(&cpu->env, ARM_FEATURE_V8);
588
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
589
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
590
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
591
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
592
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
593
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
594
+ cpu->midr = 0x461f0010;
595
+ cpu->revidr = 0x00000000;
596
+ cpu->ctr = 0x86668006;
597
+ cpu->reset_sctlr = 0x30000180;
598
+ cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */
599
+ cpu->isar.id_aa64pfr1 = 0x0000000000000000;
600
+ cpu->isar.id_aa64dfr0 = 0x0000000010305408;
601
+ cpu->isar.id_aa64dfr1 = 0x0000000000000000;
602
+ cpu->id_aa64afr0 = 0x0000000000000000;
603
+ cpu->id_aa64afr1 = 0x0000000000000000;
604
+ cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
605
+ cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
606
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
607
+ cpu->isar.id_aa64isar0 = 0x0000000010211120;
608
+ cpu->isar.id_aa64isar1 = 0x0000000000010001;
609
+ cpu->isar.id_aa64zfr0 = 0x0000000000000000;
610
+ cpu->clidr = 0x0000000080000023;
611
+ cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
612
+ cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
613
+ cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
614
+ cpu->dcz_blocksize = 6; /* 256 bytes */
615
+ cpu->gic_num_lrs = 4;
616
+ cpu->gic_vpribits = 5;
617
+ cpu->gic_vprebits = 5;
618
+ cpu->gic_pribits = 5;
619
+
620
+ /* The A64FX supports only 128, 256 and 512 bit vector lengths */
621
+ aarch64_add_sve_properties(obj);
622
+ cpu->sve_vq.supported = (1 << 0) /* 128bit */
623
+ | (1 << 1) /* 256bit */
624
+ | (1 << 3); /* 512bit */
625
+
626
+ cpu->isar.reset_pmcr_el0 = 0x46014040;
627
+
628
+ /* TODO: Add A64FX specific HPC extension registers */
629
+}
630
+
631
+static void aarch64_neoverse_n1_initfn(Object *obj)
632
+{
633
+ ARMCPU *cpu = ARM_CPU(obj);
634
+
635
+ cpu->dtb_compatible = "arm,neoverse-n1";
636
+ set_feature(&cpu->env, ARM_FEATURE_V8);
637
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
638
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
639
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
640
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
641
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
642
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
643
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
644
+
645
+ /* Ordered by B2.4 AArch64 registers by functional group */
646
+ cpu->clidr = 0x82000023;
647
+ cpu->ctr = 0x8444c004;
648
+ cpu->dcz_blocksize = 4;
649
+ cpu->isar.id_aa64dfr0 = 0x0000000110305408ull;
650
+ cpu->isar.id_aa64isar0 = 0x0000100010211120ull;
651
+ cpu->isar.id_aa64isar1 = 0x0000000000100001ull;
652
+ cpu->isar.id_aa64mmfr0 = 0x0000000000101125ull;
653
+ cpu->isar.id_aa64mmfr1 = 0x0000000010212122ull;
654
+ cpu->isar.id_aa64mmfr2 = 0x0000000000001011ull;
655
+ cpu->isar.id_aa64pfr0 = 0x1100000010111112ull; /* GIC filled in later */
656
+ cpu->isar.id_aa64pfr1 = 0x0000000000000020ull;
657
+ cpu->id_afr0 = 0x00000000;
658
+ cpu->isar.id_dfr0 = 0x04010088;
659
+ cpu->isar.id_isar0 = 0x02101110;
660
+ cpu->isar.id_isar1 = 0x13112111;
661
+ cpu->isar.id_isar2 = 0x21232042;
662
+ cpu->isar.id_isar3 = 0x01112131;
663
+ cpu->isar.id_isar4 = 0x00010142;
664
+ cpu->isar.id_isar5 = 0x01011121;
665
+ cpu->isar.id_isar6 = 0x00000010;
666
+ cpu->isar.id_mmfr0 = 0x10201105;
667
+ cpu->isar.id_mmfr1 = 0x40000000;
668
+ cpu->isar.id_mmfr2 = 0x01260000;
669
+ cpu->isar.id_mmfr3 = 0x02122211;
670
+ cpu->isar.id_mmfr4 = 0x00021110;
671
+ cpu->isar.id_pfr0 = 0x10010131;
672
+ cpu->isar.id_pfr1 = 0x00010000; /* GIC filled in later */
673
+ cpu->isar.id_pfr2 = 0x00000011;
674
+ cpu->midr = 0x414fd0c1; /* r4p1 */
675
+ cpu->revidr = 0;
676
+
677
+ /* From B2.23 CCSIDR_EL1 */
678
+ cpu->ccsidr[0] = 0x701fe01a; /* 64KB L1 dcache */
679
+ cpu->ccsidr[1] = 0x201fe01a; /* 64KB L1 icache */
680
+ cpu->ccsidr[2] = 0x70ffe03a; /* 1MB L2 cache */
681
+
682
+ /* From B2.98 SCTLR_EL3 */
683
+ cpu->reset_sctlr = 0x30c50838;
684
+
685
+ /* From B4.23 ICH_VTR_EL2 */
686
+ cpu->gic_num_lrs = 4;
687
+ cpu->gic_vpribits = 5;
688
+ cpu->gic_vprebits = 5;
689
+ cpu->gic_pribits = 5;
690
+
691
+ /* From B5.1 AdvSIMD AArch64 register summary */
692
+ cpu->isar.mvfr0 = 0x10110222;
693
+ cpu->isar.mvfr1 = 0x13211111;
694
+ cpu->isar.mvfr2 = 0x00000043;
695
+
696
+ /* From D5.1 AArch64 PMU register summary */
697
+ cpu->isar.reset_pmcr_el0 = 0x410c3000;
698
+}
699
+
700
static void aarch64_host_initfn(Object *obj)
701
{
702
#if defined(CONFIG_KVM)
703
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
704
qdev_property_add_static(DEVICE(obj), &arm_cpu_lpa2_property);
705
}
706
707
-static void aarch64_a64fx_initfn(Object *obj)
708
-{
709
- ARMCPU *cpu = ARM_CPU(obj);
710
-
711
- cpu->dtb_compatible = "arm,a64fx";
712
- set_feature(&cpu->env, ARM_FEATURE_V8);
713
- set_feature(&cpu->env, ARM_FEATURE_NEON);
714
- set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
715
- set_feature(&cpu->env, ARM_FEATURE_AARCH64);
716
- set_feature(&cpu->env, ARM_FEATURE_EL2);
717
- set_feature(&cpu->env, ARM_FEATURE_EL3);
718
- set_feature(&cpu->env, ARM_FEATURE_PMU);
719
- cpu->midr = 0x461f0010;
720
- cpu->revidr = 0x00000000;
721
- cpu->ctr = 0x86668006;
722
- cpu->reset_sctlr = 0x30000180;
723
- cpu->isar.id_aa64pfr0 = 0x0000000101111111; /* No RAS Extensions */
724
- cpu->isar.id_aa64pfr1 = 0x0000000000000000;
725
- cpu->isar.id_aa64dfr0 = 0x0000000010305408;
726
- cpu->isar.id_aa64dfr1 = 0x0000000000000000;
727
- cpu->id_aa64afr0 = 0x0000000000000000;
728
- cpu->id_aa64afr1 = 0x0000000000000000;
729
- cpu->isar.id_aa64mmfr0 = 0x0000000000001122;
730
- cpu->isar.id_aa64mmfr1 = 0x0000000011212100;
731
- cpu->isar.id_aa64mmfr2 = 0x0000000000001011;
732
- cpu->isar.id_aa64isar0 = 0x0000000010211120;
733
- cpu->isar.id_aa64isar1 = 0x0000000000010001;
734
- cpu->isar.id_aa64zfr0 = 0x0000000000000000;
735
- cpu->clidr = 0x0000000080000023;
736
- cpu->ccsidr[0] = 0x7007e01c; /* 64KB L1 dcache */
737
- cpu->ccsidr[1] = 0x2007e01c; /* 64KB L1 icache */
738
- cpu->ccsidr[2] = 0x70ffe07c; /* 8MB L2 cache */
739
- cpu->dcz_blocksize = 6; /* 256 bytes */
740
- cpu->gic_num_lrs = 4;
741
- cpu->gic_vpribits = 5;
742
- cpu->gic_vprebits = 5;
743
- cpu->gic_pribits = 5;
744
-
745
- /* The A64FX supports only 128, 256 and 512 bit vector lengths */
746
- aarch64_add_sve_properties(obj);
747
- cpu->sve_vq.supported = (1 << 0) /* 128bit */
748
- | (1 << 1) /* 256bit */
749
- | (1 << 3); /* 512bit */
750
-
751
- cpu->isar.reset_pmcr_el0 = 0x46014040;
752
-
753
- /* TODO: Add A64FX specific HPC extension registers */
754
-}
755
-
756
static const ARMCPUInfo aarch64_cpus[] = {
757
{ .name = "cortex-a35", .initfn = aarch64_a35_initfn },
758
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
104
--
759
--
105
2.20.1
760
2.25.1
106
761
107
762
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/12] hw/arm/exynos4210: Add DMA support for the Exynos4210
[PULL 05/10] hw/arm/xlnx-zynqmp: Connect ZynqMP's USB controllers
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Francisco Iglesias <francisco.iglesias@amd.com>
2
2
3
QEMU already supports pl330. Instantiate it for Exynos4210.
3
Connect ZynqMP's USB controllers.
4
4
5
Relevant part of Linux arch/arm/boot/dts/exynos4.dtsi:
5
Signed-off-by: Francisco Iglesias <francisco.iglesias@amd.com>
6
6
Acked-by: Alistair Francis <alistair.francis@wdc.com>
7
/ {
7
Message-id: 20220920081517.25401-1-frasse.iglesias@gmail.com
8
soc: soc {
9
amba {
10
pdma0: pdma@12680000 {
11
compatible = "arm,pl330", "arm,primecell";
12
reg = <0x12680000 0x1000>;
13
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
14
clocks = <&clock CLK_PDMA0>;
15
clock-names = "apb_pclk";
16
#dma-cells = <1>;
17
#dma-channels = <8>;
18
#dma-requests = <32>;
19
};
20
pdma1: pdma@12690000 {
21
compatible = "arm,pl330", "arm,primecell";
22
reg = <0x12690000 0x1000>;
23
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
24
clocks = <&clock CLK_PDMA1>;
25
clock-names = "apb_pclk";
26
#dma-cells = <1>;
27
#dma-channels = <8>;
28
#dma-requests = <32>;
29
};
30
mdma1: mdma@12850000 {
31
compatible = "arm,pl330", "arm,primecell";
32
reg = <0x12850000 0x1000>;
33
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
34
clocks = <&clock CLK_MDMA>;
35
clock-names = "apb_pclk";
36
#dma-cells = <1>;
37
#dma-channels = <8>;
38
#dma-requests = <1>;
39
};
40
};
41
};
42
};
43
44
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
45
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
46
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
47
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
48
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
49
Message-id: 20190520214342.13709-4-philmd@redhat.com
50
[PMD: Do not set default qdev properties, create the controllers in the SoC
51
rather than the board (Peter Maydell), add dtsi in commit message]
52
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
53
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
54
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
55
---
10
---
56
hw/arm/exynos4210.c | 26 ++++++++++++++++++++++++++
11
include/hw/arm/xlnx-zynqmp.h | 3 +++
57
1 file changed, 26 insertions(+)
12
hw/arm/xlnx-zynqmp.c | 36 ++++++++++++++++++++++++++++++++++++
13
2 files changed, 39 insertions(+)
58
14
59
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
15
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
60
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
61
--- a/hw/arm/exynos4210.c
17
--- a/include/hw/arm/xlnx-zynqmp.h
62
+++ b/hw/arm/exynos4210.c
18
+++ b/include/hw/arm/xlnx-zynqmp.h
63
@@ -XXX,XX +XXX,XX @@
19
@@ -XXX,XX +XXX,XX @@
64
/* EHCI */
20
#include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
65
#define EXYNOS4210_EHCI_BASE_ADDR 0x12580000
21
#include "hw/misc/xlnx-zynqmp-crf.h"
66
22
#include "hw/timer/cadence_ttc.h"
67
+/* DMA */
23
+#include "hw/usb/hcd-dwc3.h"
68
+#define EXYNOS4210_PL330_BASE0_ADDR 0x12680000
24
69
+#define EXYNOS4210_PL330_BASE1_ADDR 0x12690000
25
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
70
+#define EXYNOS4210_PL330_BASE2_ADDR 0x12850000
26
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
27
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
28
#define XLNX_ZYNQMP_NUM_SPIS 2
29
#define XLNX_ZYNQMP_NUM_GDMA_CH 8
30
#define XLNX_ZYNQMP_NUM_ADMA_CH 8
31
+#define XLNX_ZYNQMP_NUM_USB 2
32
33
#define XLNX_ZYNQMP_NUM_QSPI_BUS 2
34
#define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2
35
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
36
XlnxZynqMPAPUCtrl apu_ctrl;
37
XlnxZynqMPCRF crf;
38
CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
39
+ USBDWC3 usb[XLNX_ZYNQMP_NUM_USB];
40
41
char *boot_cpu;
42
ARMCPU *boot_cpu_ptr;
43
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/arm/xlnx-zynqmp.c
46
+++ b/hw/arm/xlnx-zynqmp.c
47
@@ -XXX,XX +XXX,XX @@ static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
48
77, 78, 79, 80, 81, 82, 83, 84
49
};
50
51
+static const uint64_t usb_addr[XLNX_ZYNQMP_NUM_USB] = {
52
+ 0xFE200000, 0xFE300000
53
+};
71
+
54
+
72
static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
55
+static const int usb_intr[XLNX_ZYNQMP_NUM_USB] = {
73
0x09, 0x00, 0x00, 0x00 };
56
+ 65, 70
74
57
+};
75
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu)
58
+
76
return (0x9 << ARM_AFF1_SHIFT) | cpu;
59
typedef struct XlnxZynqMPGICRegion {
60
int region_index;
61
uint32_t address;
62
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(Object *obj)
63
object_initialize_child(obj, "qspi-dma", &s->qspi_dma, TYPE_XLNX_CSU_DMA);
64
object_initialize_child(obj, "qspi-irq-orgate",
65
&s->qspi_irq_orgate, TYPE_OR_IRQ);
66
+
67
+ for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) {
68
+ object_initialize_child(obj, "usb[*]", &s->usb[i], TYPE_USB_DWC3);
69
+ }
77
}
70
}
78
71
79
+static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
72
static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
80
+{
73
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
81
+ SysBusDevice *busdev;
74
object_property_add_alias(OBJECT(s), bus_name,
82
+ DeviceState *dev;
75
OBJECT(&s->qspi), target_bus);
76
}
83
+
77
+
84
+ dev = qdev_create(NULL, "pl330");
78
+ for (i = 0; i < XLNX_ZYNQMP_NUM_USB; i++) {
85
+ qdev_prop_set_uint8(dev, "num_periph_req", nreq);
79
+ if (!object_property_set_link(OBJECT(&s->usb[i].sysbus_xhci), "dma",
86
+ qdev_init_nofail(dev);
80
+ OBJECT(system_memory), errp)) {
87
+ busdev = SYS_BUS_DEVICE(dev);
81
+ return;
88
+ sysbus_mmio_map(busdev, 0, base);
82
+ }
89
+ sysbus_connect_irq(busdev, 0, irq);
90
+}
91
+
83
+
92
Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
84
+ qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "intrs", 4);
93
{
85
+ qdev_prop_set_uint32(DEVICE(&s->usb[i].sysbus_xhci), "slots", 2);
94
Exynos4210State *s = g_new0(Exynos4210State, 1);
95
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
96
sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
97
s->irq_table[exynos4210_get_irq(28, 3)]);
98
99
+ /*** DMA controllers ***/
100
+ pl330_create(EXYNOS4210_PL330_BASE0_ADDR,
101
+ qemu_irq_invert(s->irq_table[exynos4210_get_irq(35, 1)]), 32);
102
+ pl330_create(EXYNOS4210_PL330_BASE1_ADDR,
103
+ qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
104
+ pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
105
+ qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
106
+
86
+
107
return s;
87
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->usb[i]), errp)) {
88
+ return;
89
+ }
90
+
91
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_addr[i]);
92
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 0,
93
+ gic_spi[usb_intr[i]]);
94
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 1,
95
+ gic_spi[usb_intr[i] + 1]);
96
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 2,
97
+ gic_spi[usb_intr[i] + 2]);
98
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i].sysbus_xhci), 3,
99
+ gic_spi[usb_intr[i] + 3]);
100
+ }
108
}
101
}
102
103
static Property xlnx_zynqmp_props[] = {
109
--
104
--
110
2.20.1
105
2.25.1
111
112
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/12] hw/arm/exynos4: Remove unuseful debug code
[PULL 06/10] hw/arm/virt: Fix devicetree warning about the root node
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
3
The devicetree specification requires a 'model' property in the root
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
4
node. Fix the corresponding dt-validate warning:
5
Message-id: 20190520214342.13709-2-philmd@redhat.com
5
6
/: 'model' is a required property
7
From schema: dtschema/schemas/root-node.yaml
8
9
Use the same name for model as for compatible. The specification
10
recommends that 'compatible' follows the format 'manufacturer,model' and
11
'model' follows the format 'manufacturer,model-number'. Since our
12
'compatible' doesn't observe this, 'model' doesn't really need to
13
either.
14
15
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
17
Reviewed-by: Eric Auger <eric.auger@redhat.com>
18
Message-id: 20220927100347.176606-2-jean-philippe@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
20
---
8
hw/arm/exynos4_boards.c | 24 ------------------------
21
hw/arm/virt.c | 1 +
9
1 file changed, 24 deletions(-)
22
1 file changed, 1 insertion(+)
10
23
11
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
24
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
12
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/arm/exynos4_boards.c
26
--- a/hw/arm/virt.c
14
+++ b/hw/arm/exynos4_boards.c
27
+++ b/hw/arm/virt.c
15
@@ -XXX,XX +XXX,XX @@
28
@@ -XXX,XX +XXX,XX @@ static void create_fdt(VirtMachineState *vms)
16
#include "hw/net/lan9118.h"
29
qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt");
17
#include "hw/boards.h"
30
qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
18
31
qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2);
19
-#undef DEBUG
32
+ qemu_fdt_setprop_string(fdt, "/", "model", "linux,dummy-virt");
20
-
33
21
-//#define DEBUG
34
/* /chosen must exist for load_dtb to fill in necessary properties later */
22
-
35
qemu_fdt_add_subnode(fdt, "/chosen");
23
-#ifdef DEBUG
24
- #undef PRINT_DEBUG
25
- #define PRINT_DEBUG(fmt, args...) \
26
- do { \
27
- fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
28
- } while (0)
29
-#else
30
- #define PRINT_DEBUG(fmt, args...) do {} while (0)
31
-#endif
32
-
33
#define SMDK_LAN9118_BASE_ADDR 0x05000000
34
35
typedef enum Exynos4BoardType {
36
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
37
exynos4_board_binfo.gic_cpu_if_addr =
38
EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100;
39
40
- PRINT_DEBUG("\n ram_size: %luMiB [0x%08lx]\n"
41
- " kernel_filename: %s\n"
42
- " kernel_cmdline: %s\n"
43
- " initrd_filename: %s\n",
44
- exynos4_board_ram_size[board_type] / 1048576,
45
- exynos4_board_ram_size[board_type],
46
- machine->kernel_filename,
47
- machine->kernel_cmdline,
48
- machine->initrd_filename);
49
-
50
exynos4_boards_init_ram(s, get_system_memory(),
51
exynos4_board_ram_size[board_type]);
52
53
--
36
--
54
2.20.1
37
2.25.1
55
56
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/12] target/arm: Fix vector operation segfault
[PULL 07/10] hw/arm/virt: Fix devicetree warning about the GIC node
1
From: Alistair Francis <alistair.francis@wdc.com>
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
Commit 89e68b575 "target/arm: Use vector operations for saturation"
3
The GICv3 bindings requires a #msi-cells property for the ITS node. Fix
4
causes this abort() when booting QEMU ARM with a Cortex-A15:
4
the corresponding dt-validate warning:
5
5
6
0 0x00007ffff4c2382f in raise () at /usr/lib/libc.so.6
6
interrupt-controller@8000000: msi-controller@8080000: '#msi-cells' is a required property
7
1 0x00007ffff4c0e672 in abort () at /usr/lib/libc.so.6
7
From schema: linux/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml
8
2 0x00005555559c1839 in disas_neon_data_insn (insn=<optimized out>, s=<optimized out>) at ./target/arm/translate.c:6673
9
3 0x00005555559c1839 in disas_neon_data_insn (s=<optimized out>, insn=<optimized out>) at ./target/arm/translate.c:6386
10
4 0x00005555559cd8a4 in disas_arm_insn (insn=4081107068, s=0x7fffe59a9510) at ./target/arm/translate.c:9289
11
5 0x00005555559cd8a4 in arm_tr_translate_insn (dcbase=0x7fffe59a9510, cpu=<optimized out>) at ./target/arm/translate.c:13612
12
6 0x00005555558d1d39 in translator_loop (ops=0x5555561cc580 <arm_translator_ops>, db=0x7fffe59a9510, cpu=0x55555686a2f0, tb=<optimized out>, max_insns=<optimized out>) at ./accel/tcg/translator.c:96
13
7 0x00005555559d10d4 in gen_intermediate_code (cpu=cpu@entry=0x55555686a2f0, tb=tb@entry=0x7fffd7840080 <code_gen_buffer+126091347>, max_insns=max_insns@entry=512) at ./target/arm/translate.c:13901
14
8 0x00005555558d06b9 in tb_gen_code (cpu=cpu@entry=0x55555686a2f0, pc=3067096216, cs_base=0, flags=192, cflags=-16252928, cflags@entry=524288) at ./accel/tcg/translate-all.c:1736
15
9 0x00005555558ce467 in tb_find (cf_mask=524288, tb_exit=1, last_tb=0x7fffd783e640 <code_gen_buffer+126084627>, cpu=0x1) at ./accel/tcg/cpu-exec.c:407
16
10 0x00005555558ce467 in cpu_exec (cpu=cpu@entry=0x55555686a2f0) at ./accel/tcg/cpu-exec.c:728
17
11 0x000055555588b0cf in tcg_cpu_exec (cpu=0x55555686a2f0) at ./cpus.c:1431
18
12 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=0x55555686a2f0) at ./cpus.c:1735
19
13 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=arg@entry=0x55555686a2f0) at ./cpus.c:1709
20
14 0x0000555555d2629a in qemu_thread_start (args=<optimized out>) at ./util/qemu-thread-posix.c:502
21
15 0x00007ffff4db8a92 in start_thread () at /usr/lib/libpthread.
22
8
23
This patch ensures that we don't hit the abort() in the second switch
9
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
24
case in disas_neon_data_insn() as we will return from the first case.
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
25
11
Reviewed-by: Eric Auger <eric.auger@redhat.com>
26
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-id: 20220927100347.176606-3-jean-philippe@linaro.org
27
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
28
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
29
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
30
Tested-by: Alex Bennée <alex.bennee@linaro.org>
31
Message-id: ad91b397f360b2fc7f4087e476f7df5b04d42ddb.1558021877.git.alistair.francis@wdc.com
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
---
14
---
34
target/arm/translate.c | 4 ++--
15
hw/arm/virt.c | 1 +
35
1 file changed, 2 insertions(+), 2 deletions(-)
16
1 file changed, 1 insertion(+)
36
17
37
diff --git a/target/arm/translate.c b/target/arm/translate.c
18
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
38
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/translate.c
20
--- a/hw/arm/virt.c
40
+++ b/target/arm/translate.c
21
+++ b/hw/arm/virt.c
41
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
22
@@ -XXX,XX +XXX,XX @@ static void fdt_add_its_gic_node(VirtMachineState *vms)
42
tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
23
qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
43
rn_ofs, rm_ofs, vec_size, vec_size,
24
"arm,gic-v3-its");
44
(u ? uqadd_op : sqadd_op) + size);
25
qemu_fdt_setprop(ms->fdt, nodename, "msi-controller", NULL, 0);
45
- break;
26
+ qemu_fdt_setprop_cell(ms->fdt, nodename, "#msi-cells", 1);
46
+ return 0;
27
qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
47
28
2, vms->memmap[VIRT_GIC_ITS].base,
48
case NEON_3R_VQSUB:
29
2, vms->memmap[VIRT_GIC_ITS].size);
49
tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
50
rn_ofs, rm_ofs, vec_size, vec_size,
51
(u ? uqsub_op : sqsub_op) + size);
52
- break;
53
+ return 0;
54
55
case NEON_3R_VMUL: /* VMUL */
56
if (u) {
57
--
30
--
58
2.20.1
31
2.25.1
59
60
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/12] target/arm: Simplify BFXIL expansion
[PULL 08/10] hw/arm/virt: Use "msi-map" devicetree property for PCI
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
2
3
The mask implied by the extract is redundant with the one
3
The "msi-parent" property can be used on the PCI node when MSIs do not
4
implied by the deposit. Also, fix spelling of BFXIL.
4
contain sideband data (device IDs) [1]. In QEMU, MSI transactions
5
contain the requester ID, so the PCI node should use the "msi-map"
6
property instead of "msi-parent". In our case the property describes an
7
identity map between requester ID and sideband data.
5
8
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
This fixes a warning when passing the DTB generated by QEMU to dtc,
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
following a recent change to the GICv3 node:
8
Message-id: 20190514011129.11330-3-richard.henderson@linaro.org
11
12
Warning (msi_parent_property): /pcie@10000000:msi-parent: property size (4) too small for cell size 1
13
14
[1] linux/Documentation/devicetree/bindings/pci/pci-msi.txt
15
16
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Reviewed-by: Eric Auger <eric.auger@redhat.com>
19
Message-id: 20220927100347.176606-4-jean-philippe@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
21
---
11
target/arm/translate-a64.c | 6 +++---
22
hw/arm/virt.c | 4 ++--
12
1 file changed, 3 insertions(+), 3 deletions(-)
23
1 file changed, 2 insertions(+), 2 deletions(-)
13
24
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
25
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
15
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
27
--- a/hw/arm/virt.c
17
+++ b/target/arm/translate-a64.c
28
+++ b/hw/arm/virt.c
18
@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
29
@@ -XXX,XX +XXX,XX @@ static void create_pcie(VirtMachineState *vms)
19
tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len);
30
qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0);
20
return;
31
21
}
32
if (vms->msi_phandle) {
22
- /* opc == 1, BXFIL fall through to deposit */
33
- qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-parent",
23
- tcg_gen_extract_i64(tcg_tmp, tcg_tmp, ri, len);
34
- vms->msi_phandle);
24
+ /* opc == 1, BFXIL fall through to deposit */
35
+ qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map",
25
+ tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri);
36
+ 0, vms->msi_phandle, 0, 0x10000);
26
pos = 0;
27
} else {
28
/* Handle the ri > si case with a deposit
29
@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
30
len = ri;
31
}
37
}
32
38
33
- if (opc == 1) { /* BFM, BXFIL */
39
qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg",
34
+ if (opc == 1) { /* BFM, BFXIL */
35
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len);
36
} else {
37
/* SBFM or UBFM: We start with zero, and we haven't modified
38
--
40
--
39
2.20.1
41
2.25.1
40
41
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/12] arm: Move system_clock_scale to armv7m_systick.h
Deleted patch
1
The system_clock_scale global is used only by the armv7m systick
2
device; move the extern declaration to the armv7m_systick.h header,
3
and expand the comment to explain what it is and that it should
4
ideally be replaced with a different approach.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20190516163857.6430-2-peter.maydell@linaro.org
10
---
11
include/hw/arm/arm.h | 4 ----
12
include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++++++++
13
2 files changed, 22 insertions(+), 4 deletions(-)
14
15
diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/arm.h
18
+++ b/include/hw/arm/arm.h
19
@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
20
const struct arm_boot_info *info,
21
hwaddr mvbar_addr);
22
23
-/* Multiplication factor to convert from system clock ticks to qemu timer
24
- ticks. */
25
-extern int system_clock_scale;
26
-
27
#endif /* HW_ARM_H */
28
diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
29
index XXXXXXX..XXXXXXX 100644
30
--- a/include/hw/timer/armv7m_systick.h
31
+++ b/include/hw/timer/armv7m_systick.h
32
@@ -XXX,XX +XXX,XX @@ typedef struct SysTickState {
33
qemu_irq irq;
34
} SysTickState;
35
36
+/*
37
+ * Multiplication factor to convert from system clock ticks to qemu timer
38
+ * ticks. This should be set (by board code, usually) to a value
39
+ * equal to NANOSECONDS_PER_SECOND / frq, where frq is the clock frequency
40
+ * in Hz of the CPU.
41
+ *
42
+ * This value is used by the systick device when it is running in
43
+ * its "use the CPU clock" mode (ie when SYST_CSR.CLKSOURCE == 1) to
44
+ * set how fast the timer should tick.
45
+ *
46
+ * TODO: we should refactor this so that rather than using a global
47
+ * we use a device property or something similar. This is complicated
48
+ * because (a) the property would need to be plumbed through from the
49
+ * board code down through various layers to the systick device
50
+ * and (b) the property needs to be modifiable after realize, because
51
+ * the stellaris board uses this to implement the behaviour where the
52
+ * guest can reprogram the PLL registers to downclock the CPU, and the
53
+ * systick device needs to react accordingly. Possibly this should
54
+ * be deferred until we have a good API for modelling clock trees.
55
+ */
56
+extern int system_clock_scale;
57
+
58
#endif
59
--
60
2.20.1
61
62
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/12] arm: Rename hw/arm/arm.h to hw/arm/boot.h
[PULL 09/10] hw/arm/virt: Fix devicetree warning about the SMMU node
1
The header file hw/arm/arm.h now includes only declarations
1
From: Jean-Philippe Brucker <jean-philippe@linaro.org>
2
relating to hw/arm/boot.c functionality. Rename it accordingly,
3
and adjust its header comment.
4
2
5
The bulk of this commit was created via
3
The SMMUv3 node isn't expected to have clock properties
6
perl -pi -e 's|hw/arm/arm.h|hw/arm/boot.h|' hw/arm/*.c include/hw/arm/*.h
4
(unlike the SMMUv2). Fix the corresponding dt-validate warning:
7
5
8
In a few cases we can just delete the #include:
6
smmuv3@9050000: 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+'
9
hw/arm/msf2-soc.c, include/hw/arm/aspeed_soc.h and
7
From schema: linux/Documentation/devicetree/bindings/iommu/arm,smmu-v3.yaml
10
include/hw/arm/bcm2836.h did not require it.
11
8
9
Signed-off-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
[PMM: tweaked commit message as suggested by Eric]
12
Reviewed-by: Eric Auger <eric.auger@redhat.com>
13
Message-id: 20220927100347.176606-7-jean-philippe@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Message-id: 20190516163857.6430-4-peter.maydell@linaro.org
16
---
15
---
17
include/hw/arm/allwinner-a10.h | 2 +-
16
hw/arm/virt.c | 2 --
18
include/hw/arm/aspeed_soc.h | 1 -
17
1 file changed, 2 deletions(-)
19
include/hw/arm/bcm2836.h | 1 -
20
include/hw/arm/{arm.h => boot.h} | 8 ++++----
21
include/hw/arm/fsl-imx25.h | 2 +-
22
include/hw/arm/fsl-imx31.h | 2 +-
23
include/hw/arm/fsl-imx6.h | 2 +-
24
include/hw/arm/fsl-imx6ul.h | 2 +-
25
include/hw/arm/fsl-imx7.h | 2 +-
26
include/hw/arm/virt.h | 2 +-
27
include/hw/arm/xlnx-versal.h | 2 +-
28
include/hw/arm/xlnx-zynqmp.h | 2 +-
29
hw/arm/armsse.c | 2 +-
30
hw/arm/armv7m.c | 2 +-
31
hw/arm/aspeed.c | 2 +-
32
hw/arm/boot.c | 2 +-
33
hw/arm/collie.c | 2 +-
34
hw/arm/exynos4210.c | 2 +-
35
hw/arm/exynos4_boards.c | 2 +-
36
hw/arm/highbank.c | 2 +-
37
hw/arm/integratorcp.c | 2 +-
38
hw/arm/mainstone.c | 2 +-
39
hw/arm/microbit.c | 2 +-
40
hw/arm/mps2-tz.c | 2 +-
41
hw/arm/mps2.c | 2 +-
42
hw/arm/msf2-soc.c | 1 -
43
hw/arm/msf2-som.c | 2 +-
44
hw/arm/musca.c | 2 +-
45
hw/arm/musicpal.c | 2 +-
46
hw/arm/netduino2.c | 2 +-
47
hw/arm/nrf51_soc.c | 2 +-
48
hw/arm/nseries.c | 2 +-
49
hw/arm/omap1.c | 2 +-
50
hw/arm/omap2.c | 2 +-
51
hw/arm/omap_sx1.c | 2 +-
52
hw/arm/palm.c | 2 +-
53
hw/arm/raspi.c | 2 +-
54
hw/arm/realview.c | 2 +-
55
hw/arm/spitz.c | 2 +-
56
hw/arm/stellaris.c | 2 +-
57
hw/arm/stm32f205_soc.c | 2 +-
58
hw/arm/strongarm.c | 2 +-
59
hw/arm/tosa.c | 2 +-
60
hw/arm/versatilepb.c | 2 +-
61
hw/arm/vexpress.c | 2 +-
62
hw/arm/virt.c | 2 +-
63
hw/arm/xilinx_zynq.c | 2 +-
64
hw/arm/xlnx-versal.c | 2 +-
65
hw/arm/z2.c | 2 +-
66
49 files changed, 49 insertions(+), 52 deletions(-)
67
rename include/hw/arm/{arm.h => boot.h} (98%)
68
18
69
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
70
index XXXXXXX..XXXXXXX 100644
71
--- a/include/hw/arm/allwinner-a10.h
72
+++ b/include/hw/arm/allwinner-a10.h
73
@@ -XXX,XX +XXX,XX @@
74
#include "qemu-common.h"
75
#include "qemu/error-report.h"
76
#include "hw/char/serial.h"
77
-#include "hw/arm/arm.h"
78
+#include "hw/arm/boot.h"
79
#include "hw/timer/allwinner-a10-pit.h"
80
#include "hw/intc/allwinner-a10-pic.h"
81
#include "hw/net/allwinner_emac.h"
82
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
83
index XXXXXXX..XXXXXXX 100644
84
--- a/include/hw/arm/aspeed_soc.h
85
+++ b/include/hw/arm/aspeed_soc.h
86
@@ -XXX,XX +XXX,XX @@
87
#ifndef ASPEED_SOC_H
88
#define ASPEED_SOC_H
89
90
-#include "hw/arm/arm.h"
91
#include "hw/intc/aspeed_vic.h"
92
#include "hw/misc/aspeed_scu.h"
93
#include "hw/misc/aspeed_sdmc.h"
94
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
95
index XXXXXXX..XXXXXXX 100644
96
--- a/include/hw/arm/bcm2836.h
97
+++ b/include/hw/arm/bcm2836.h
98
@@ -XXX,XX +XXX,XX @@
99
#ifndef BCM2836_H
100
#define BCM2836_H
101
102
-#include "hw/arm/arm.h"
103
#include "hw/arm/bcm2835_peripherals.h"
104
#include "hw/intc/bcm2836_control.h"
105
106
diff --git a/include/hw/arm/arm.h b/include/hw/arm/boot.h
107
similarity index 98%
108
rename from include/hw/arm/arm.h
109
rename to include/hw/arm/boot.h
110
index XXXXXXX..XXXXXXX 100644
111
--- a/include/hw/arm/arm.h
112
+++ b/include/hw/arm/boot.h
113
@@ -XXX,XX +XXX,XX @@
114
/*
115
- * Misc ARM declarations
116
+ * ARM kernel loader.
117
*
118
* Copyright (c) 2006 CodeSourcery.
119
* Written by Paul Brook
120
@@ -XXX,XX +XXX,XX @@
121
*
122
*/
123
124
-#ifndef HW_ARM_H
125
-#define HW_ARM_H
126
+#ifndef HW_ARM_BOOT_H
127
+#define HW_ARM_BOOT_H
128
129
#include "exec/memory.h"
130
#include "target/arm/cpu-qom.h"
131
@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
132
const struct arm_boot_info *info,
133
hwaddr mvbar_addr);
134
135
-#endif /* HW_ARM_H */
136
+#endif /* HW_ARM_BOOT_H */
137
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
138
index XXXXXXX..XXXXXXX 100644
139
--- a/include/hw/arm/fsl-imx25.h
140
+++ b/include/hw/arm/fsl-imx25.h
141
@@ -XXX,XX +XXX,XX @@
142
#ifndef FSL_IMX25_H
143
#define FSL_IMX25_H
144
145
-#include "hw/arm/arm.h"
146
+#include "hw/arm/boot.h"
147
#include "hw/intc/imx_avic.h"
148
#include "hw/misc/imx25_ccm.h"
149
#include "hw/char/imx_serial.h"
150
diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h
151
index XXXXXXX..XXXXXXX 100644
152
--- a/include/hw/arm/fsl-imx31.h
153
+++ b/include/hw/arm/fsl-imx31.h
154
@@ -XXX,XX +XXX,XX @@
155
#ifndef FSL_IMX31_H
156
#define FSL_IMX31_H
157
158
-#include "hw/arm/arm.h"
159
+#include "hw/arm/boot.h"
160
#include "hw/intc/imx_avic.h"
161
#include "hw/misc/imx31_ccm.h"
162
#include "hw/char/imx_serial.h"
163
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
164
index XXXXXXX..XXXXXXX 100644
165
--- a/include/hw/arm/fsl-imx6.h
166
+++ b/include/hw/arm/fsl-imx6.h
167
@@ -XXX,XX +XXX,XX @@
168
#ifndef FSL_IMX6_H
169
#define FSL_IMX6_H
170
171
-#include "hw/arm/arm.h"
172
+#include "hw/arm/boot.h"
173
#include "hw/cpu/a9mpcore.h"
174
#include "hw/misc/imx6_ccm.h"
175
#include "hw/misc/imx6_src.h"
176
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
177
index XXXXXXX..XXXXXXX 100644
178
--- a/include/hw/arm/fsl-imx6ul.h
179
+++ b/include/hw/arm/fsl-imx6ul.h
180
@@ -XXX,XX +XXX,XX @@
181
#ifndef FSL_IMX6UL_H
182
#define FSL_IMX6UL_H
183
184
-#include "hw/arm/arm.h"
185
+#include "hw/arm/boot.h"
186
#include "hw/cpu/a15mpcore.h"
187
#include "hw/misc/imx6ul_ccm.h"
188
#include "hw/misc/imx6_src.h"
189
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
190
index XXXXXXX..XXXXXXX 100644
191
--- a/include/hw/arm/fsl-imx7.h
192
+++ b/include/hw/arm/fsl-imx7.h
193
@@ -XXX,XX +XXX,XX @@
194
#ifndef FSL_IMX7_H
195
#define FSL_IMX7_H
196
197
-#include "hw/arm/arm.h"
198
+#include "hw/arm/boot.h"
199
#include "hw/cpu/a15mpcore.h"
200
#include "hw/intc/imx_gpcv2.h"
201
#include "hw/misc/imx7_ccm.h"
202
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
203
index XXXXXXX..XXXXXXX 100644
204
--- a/include/hw/arm/virt.h
205
+++ b/include/hw/arm/virt.h
206
@@ -XXX,XX +XXX,XX @@
207
#include "exec/hwaddr.h"
208
#include "qemu/notify.h"
209
#include "hw/boards.h"
210
-#include "hw/arm/arm.h"
211
+#include "hw/arm/boot.h"
212
#include "hw/block/flash.h"
213
#include "sysemu/kvm.h"
214
#include "hw/intc/arm_gicv3_common.h"
215
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
216
index XXXXXXX..XXXXXXX 100644
217
--- a/include/hw/arm/xlnx-versal.h
218
+++ b/include/hw/arm/xlnx-versal.h
219
@@ -XXX,XX +XXX,XX @@
220
#define XLNX_VERSAL_H
221
222
#include "hw/sysbus.h"
223
-#include "hw/arm/arm.h"
224
+#include "hw/arm/boot.h"
225
#include "hw/intc/arm_gicv3.h"
226
227
#define TYPE_XLNX_VERSAL "xlnx-versal"
228
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
229
index XXXXXXX..XXXXXXX 100644
230
--- a/include/hw/arm/xlnx-zynqmp.h
231
+++ b/include/hw/arm/xlnx-zynqmp.h
232
@@ -XXX,XX +XXX,XX @@
233
#ifndef XLNX_ZYNQMP_H
234
235
#include "qemu-common.h"
236
-#include "hw/arm/arm.h"
237
+#include "hw/arm/boot.h"
238
#include "hw/intc/arm_gic.h"
239
#include "hw/net/cadence_gem.h"
240
#include "hw/char/cadence_uart.h"
241
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
242
index XXXXXXX..XXXXXXX 100644
243
--- a/hw/arm/armsse.c
244
+++ b/hw/arm/armsse.c
245
@@ -XXX,XX +XXX,XX @@
246
#include "hw/sysbus.h"
247
#include "hw/registerfields.h"
248
#include "hw/arm/armsse.h"
249
-#include "hw/arm/arm.h"
250
+#include "hw/arm/boot.h"
251
252
/* Format of the System Information block SYS_CONFIG register */
253
typedef enum SysConfigFormat {
254
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
255
index XXXXXXX..XXXXXXX 100644
256
--- a/hw/arm/armv7m.c
257
+++ b/hw/arm/armv7m.c
258
@@ -XXX,XX +XXX,XX @@
259
#include "qemu-common.h"
260
#include "cpu.h"
261
#include "hw/sysbus.h"
262
-#include "hw/arm/arm.h"
263
+#include "hw/arm/boot.h"
264
#include "hw/loader.h"
265
#include "elf.h"
266
#include "sysemu/qtest.h"
267
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
268
index XXXXXXX..XXXXXXX 100644
269
--- a/hw/arm/aspeed.c
270
+++ b/hw/arm/aspeed.c
271
@@ -XXX,XX +XXX,XX @@
272
#include "qemu-common.h"
273
#include "cpu.h"
274
#include "exec/address-spaces.h"
275
-#include "hw/arm/arm.h"
276
+#include "hw/arm/boot.h"
277
#include "hw/arm/aspeed.h"
278
#include "hw/arm/aspeed_soc.h"
279
#include "hw/boards.h"
280
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
281
index XXXXXXX..XXXXXXX 100644
282
--- a/hw/arm/boot.c
283
+++ b/hw/arm/boot.c
284
@@ -XXX,XX +XXX,XX @@
285
#include "qapi/error.h"
286
#include <libfdt.h>
287
#include "hw/hw.h"
288
-#include "hw/arm/arm.h"
289
+#include "hw/arm/boot.h"
290
#include "hw/arm/linux-boot-if.h"
291
#include "sysemu/kvm.h"
292
#include "sysemu/sysemu.h"
293
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
294
index XXXXXXX..XXXXXXX 100644
295
--- a/hw/arm/collie.c
296
+++ b/hw/arm/collie.c
297
@@ -XXX,XX +XXX,XX @@
298
#include "hw/sysbus.h"
299
#include "hw/boards.h"
300
#include "strongarm.h"
301
-#include "hw/arm/arm.h"
302
+#include "hw/arm/boot.h"
303
#include "hw/block/flash.h"
304
#include "exec/address-spaces.h"
305
#include "cpu.h"
306
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
307
index XXXXXXX..XXXXXXX 100644
308
--- a/hw/arm/exynos4210.c
309
+++ b/hw/arm/exynos4210.c
310
@@ -XXX,XX +XXX,XX @@
311
#include "hw/boards.h"
312
#include "sysemu/sysemu.h"
313
#include "hw/sysbus.h"
314
-#include "hw/arm/arm.h"
315
+#include "hw/arm/boot.h"
316
#include "hw/loader.h"
317
#include "hw/arm/exynos4210.h"
318
#include "hw/sd/sdhci.h"
319
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
320
index XXXXXXX..XXXXXXX 100644
321
--- a/hw/arm/exynos4_boards.c
322
+++ b/hw/arm/exynos4_boards.c
323
@@ -XXX,XX +XXX,XX @@
324
#include "sysemu/sysemu.h"
325
#include "hw/sysbus.h"
326
#include "net/net.h"
327
-#include "hw/arm/arm.h"
328
+#include "hw/arm/boot.h"
329
#include "exec/address-spaces.h"
330
#include "hw/arm/exynos4210.h"
331
#include "hw/net/lan9118.h"
332
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
333
index XXXXXXX..XXXXXXX 100644
334
--- a/hw/arm/highbank.c
335
+++ b/hw/arm/highbank.c
336
@@ -XXX,XX +XXX,XX @@
337
#include "qemu/osdep.h"
338
#include "qapi/error.h"
339
#include "hw/sysbus.h"
340
-#include "hw/arm/arm.h"
341
+#include "hw/arm/boot.h"
342
#include "hw/loader.h"
343
#include "net/net.h"
344
#include "sysemu/kvm.h"
345
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
346
index XXXXXXX..XXXXXXX 100644
347
--- a/hw/arm/integratorcp.c
348
+++ b/hw/arm/integratorcp.c
349
@@ -XXX,XX +XXX,XX @@
350
#include "cpu.h"
351
#include "hw/sysbus.h"
352
#include "hw/boards.h"
353
-#include "hw/arm/arm.h"
354
+#include "hw/arm/boot.h"
355
#include "hw/misc/arm_integrator_debug.h"
356
#include "hw/net/smc91c111.h"
357
#include "net/net.h"
358
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
359
index XXXXXXX..XXXXXXX 100644
360
--- a/hw/arm/mainstone.c
361
+++ b/hw/arm/mainstone.c
362
@@ -XXX,XX +XXX,XX @@
363
#include "qapi/error.h"
364
#include "hw/hw.h"
365
#include "hw/arm/pxa.h"
366
-#include "hw/arm/arm.h"
367
+#include "hw/arm/boot.h"
368
#include "net/net.h"
369
#include "hw/net/smc91c111.h"
370
#include "hw/boards.h"
371
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
372
index XXXXXXX..XXXXXXX 100644
373
--- a/hw/arm/microbit.c
374
+++ b/hw/arm/microbit.c
375
@@ -XXX,XX +XXX,XX @@
376
#include "qemu/osdep.h"
377
#include "qapi/error.h"
378
#include "hw/boards.h"
379
-#include "hw/arm/arm.h"
380
+#include "hw/arm/boot.h"
381
#include "sysemu/sysemu.h"
382
#include "exec/address-spaces.h"
383
384
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
385
index XXXXXXX..XXXXXXX 100644
386
--- a/hw/arm/mps2-tz.c
387
+++ b/hw/arm/mps2-tz.c
388
@@ -XXX,XX +XXX,XX @@
389
#include "qemu/osdep.h"
390
#include "qapi/error.h"
391
#include "qemu/error-report.h"
392
-#include "hw/arm/arm.h"
393
+#include "hw/arm/boot.h"
394
#include "hw/arm/armv7m.h"
395
#include "hw/or-irq.h"
396
#include "hw/boards.h"
397
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
398
index XXXXXXX..XXXXXXX 100644
399
--- a/hw/arm/mps2.c
400
+++ b/hw/arm/mps2.c
401
@@ -XXX,XX +XXX,XX @@
402
#include "qemu/osdep.h"
403
#include "qapi/error.h"
404
#include "qemu/error-report.h"
405
-#include "hw/arm/arm.h"
406
+#include "hw/arm/boot.h"
407
#include "hw/arm/armv7m.h"
408
#include "hw/or-irq.h"
409
#include "hw/boards.h"
410
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
411
index XXXXXXX..XXXXXXX 100644
412
--- a/hw/arm/msf2-soc.c
413
+++ b/hw/arm/msf2-soc.c
414
@@ -XXX,XX +XXX,XX @@
415
#include "qemu/units.h"
416
#include "qapi/error.h"
417
#include "qemu-common.h"
418
-#include "hw/arm/arm.h"
419
#include "exec/address-spaces.h"
420
#include "hw/char/serial.h"
421
#include "hw/boards.h"
422
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
423
index XXXXXXX..XXXXXXX 100644
424
--- a/hw/arm/msf2-som.c
425
+++ b/hw/arm/msf2-som.c
426
@@ -XXX,XX +XXX,XX @@
427
#include "qapi/error.h"
428
#include "qemu/error-report.h"
429
#include "hw/boards.h"
430
-#include "hw/arm/arm.h"
431
+#include "hw/arm/boot.h"
432
#include "exec/address-spaces.h"
433
#include "hw/arm/msf2-soc.h"
434
#include "cpu.h"
435
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
436
index XXXXXXX..XXXXXXX 100644
437
--- a/hw/arm/musca.c
438
+++ b/hw/arm/musca.c
439
@@ -XXX,XX +XXX,XX @@
440
#include "qapi/error.h"
441
#include "exec/address-spaces.h"
442
#include "sysemu/sysemu.h"
443
-#include "hw/arm/arm.h"
444
+#include "hw/arm/boot.h"
445
#include "hw/arm/armsse.h"
446
#include "hw/boards.h"
447
#include "hw/char/pl011.h"
448
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
449
index XXXXXXX..XXXXXXX 100644
450
--- a/hw/arm/musicpal.c
451
+++ b/hw/arm/musicpal.c
452
@@ -XXX,XX +XXX,XX @@
453
#include "qemu-common.h"
454
#include "cpu.h"
455
#include "hw/sysbus.h"
456
-#include "hw/arm/arm.h"
457
+#include "hw/arm/boot.h"
458
#include "net/net.h"
459
#include "sysemu/sysemu.h"
460
#include "hw/boards.h"
461
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
462
index XXXXXXX..XXXXXXX 100644
463
--- a/hw/arm/netduino2.c
464
+++ b/hw/arm/netduino2.c
465
@@ -XXX,XX +XXX,XX @@
466
#include "hw/boards.h"
467
#include "qemu/error-report.h"
468
#include "hw/arm/stm32f205_soc.h"
469
-#include "hw/arm/arm.h"
470
+#include "hw/arm/boot.h"
471
472
static void netduino2_init(MachineState *machine)
473
{
474
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
475
index XXXXXXX..XXXXXXX 100644
476
--- a/hw/arm/nrf51_soc.c
477
+++ b/hw/arm/nrf51_soc.c
478
@@ -XXX,XX +XXX,XX @@
479
#include "qemu/osdep.h"
480
#include "qapi/error.h"
481
#include "qemu-common.h"
482
-#include "hw/arm/arm.h"
483
+#include "hw/arm/boot.h"
484
#include "hw/sysbus.h"
485
#include "hw/boards.h"
486
#include "hw/misc/unimp.h"
487
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
488
index XXXXXXX..XXXXXXX 100644
489
--- a/hw/arm/nseries.c
490
+++ b/hw/arm/nseries.c
491
@@ -XXX,XX +XXX,XX @@
492
#include "qemu/bswap.h"
493
#include "sysemu/sysemu.h"
494
#include "hw/arm/omap.h"
495
-#include "hw/arm/arm.h"
496
+#include "hw/arm/boot.h"
497
#include "hw/irq.h"
498
#include "ui/console.h"
499
#include "hw/boards.h"
500
diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
501
index XXXXXXX..XXXXXXX 100644
502
--- a/hw/arm/omap1.c
503
+++ b/hw/arm/omap1.c
504
@@ -XXX,XX +XXX,XX @@
505
#include "cpu.h"
506
#include "hw/boards.h"
507
#include "hw/hw.h"
508
-#include "hw/arm/arm.h"
509
+#include "hw/arm/boot.h"
510
#include "hw/arm/omap.h"
511
#include "sysemu/sysemu.h"
512
#include "hw/arm/soc_dma.h"
513
diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
514
index XXXXXXX..XXXXXXX 100644
515
--- a/hw/arm/omap2.c
516
+++ b/hw/arm/omap2.c
517
@@ -XXX,XX +XXX,XX @@
518
#include "sysemu/qtest.h"
519
#include "hw/boards.h"
520
#include "hw/hw.h"
521
-#include "hw/arm/arm.h"
522
+#include "hw/arm/boot.h"
523
#include "hw/arm/omap.h"
524
#include "sysemu/sysemu.h"
525
#include "qemu/timer.h"
526
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
527
index XXXXXXX..XXXXXXX 100644
528
--- a/hw/arm/omap_sx1.c
529
+++ b/hw/arm/omap_sx1.c
530
@@ -XXX,XX +XXX,XX @@
531
#include "ui/console.h"
532
#include "hw/arm/omap.h"
533
#include "hw/boards.h"
534
-#include "hw/arm/arm.h"
535
+#include "hw/arm/boot.h"
536
#include "hw/block/flash.h"
537
#include "sysemu/qtest.h"
538
#include "exec/address-spaces.h"
539
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
540
index XXXXXXX..XXXXXXX 100644
541
--- a/hw/arm/palm.c
542
+++ b/hw/arm/palm.c
543
@@ -XXX,XX +XXX,XX @@
544
#include "ui/console.h"
545
#include "hw/arm/omap.h"
546
#include "hw/boards.h"
547
-#include "hw/arm/arm.h"
548
+#include "hw/arm/boot.h"
549
#include "hw/input/tsc2xxx.h"
550
#include "hw/loader.h"
551
#include "exec/address-spaces.h"
552
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
553
index XXXXXXX..XXXXXXX 100644
554
--- a/hw/arm/raspi.c
555
+++ b/hw/arm/raspi.c
556
@@ -XXX,XX +XXX,XX @@
557
#include "qemu/error-report.h"
558
#include "hw/boards.h"
559
#include "hw/loader.h"
560
-#include "hw/arm/arm.h"
561
+#include "hw/arm/boot.h"
562
#include "sysemu/sysemu.h"
563
564
#define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS */
565
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
566
index XXXXXXX..XXXXXXX 100644
567
--- a/hw/arm/realview.c
568
+++ b/hw/arm/realview.c
569
@@ -XXX,XX +XXX,XX @@
570
#include "qemu-common.h"
571
#include "cpu.h"
572
#include "hw/sysbus.h"
573
-#include "hw/arm/arm.h"
574
+#include "hw/arm/boot.h"
575
#include "hw/arm/primecell.h"
576
#include "hw/net/lan9118.h"
577
#include "hw/net/smc91c111.h"
578
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
579
index XXXXXXX..XXXXXXX 100644
580
--- a/hw/arm/spitz.c
581
+++ b/hw/arm/spitz.c
582
@@ -XXX,XX +XXX,XX @@
583
#include "qapi/error.h"
584
#include "hw/hw.h"
585
#include "hw/arm/pxa.h"
586
-#include "hw/arm/arm.h"
587
+#include "hw/arm/boot.h"
588
#include "sysemu/sysemu.h"
589
#include "hw/pcmcia.h"
590
#include "hw/i2c/i2c.h"
591
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
592
index XXXXXXX..XXXXXXX 100644
593
--- a/hw/arm/stellaris.c
594
+++ b/hw/arm/stellaris.c
595
@@ -XXX,XX +XXX,XX @@
596
#include "qapi/error.h"
597
#include "hw/sysbus.h"
598
#include "hw/ssi/ssi.h"
599
-#include "hw/arm/arm.h"
600
+#include "hw/arm/boot.h"
601
#include "qemu/timer.h"
602
#include "hw/i2c/i2c.h"
603
#include "net/net.h"
604
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
605
index XXXXXXX..XXXXXXX 100644
606
--- a/hw/arm/stm32f205_soc.c
607
+++ b/hw/arm/stm32f205_soc.c
608
@@ -XXX,XX +XXX,XX @@
609
#include "qemu/osdep.h"
610
#include "qapi/error.h"
611
#include "qemu-common.h"
612
-#include "hw/arm/arm.h"
613
+#include "hw/arm/boot.h"
614
#include "exec/address-spaces.h"
615
#include "hw/arm/stm32f205_soc.h"
616
617
diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
618
index XXXXXXX..XXXXXXX 100644
619
--- a/hw/arm/strongarm.c
620
+++ b/hw/arm/strongarm.c
621
@@ -XXX,XX +XXX,XX @@
622
#include "hw/sysbus.h"
623
#include "strongarm.h"
624
#include "qemu/error-report.h"
625
-#include "hw/arm/arm.h"
626
+#include "hw/arm/boot.h"
627
#include "chardev/char-fe.h"
628
#include "chardev/char-serial.h"
629
#include "sysemu/sysemu.h"
630
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
631
index XXXXXXX..XXXXXXX 100644
632
--- a/hw/arm/tosa.c
633
+++ b/hw/arm/tosa.c
634
@@ -XXX,XX +XXX,XX @@
635
#include "qapi/error.h"
636
#include "hw/hw.h"
637
#include "hw/arm/pxa.h"
638
-#include "hw/arm/arm.h"
639
+#include "hw/arm/boot.h"
640
#include "hw/arm/sharpsl.h"
641
#include "hw/pcmcia.h"
642
#include "hw/boards.h"
643
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
644
index XXXXXXX..XXXXXXX 100644
645
--- a/hw/arm/versatilepb.c
646
+++ b/hw/arm/versatilepb.c
647
@@ -XXX,XX +XXX,XX @@
648
#include "qemu-common.h"
649
#include "cpu.h"
650
#include "hw/sysbus.h"
651
-#include "hw/arm/arm.h"
652
+#include "hw/arm/boot.h"
653
#include "hw/net/smc91c111.h"
654
#include "net/net.h"
655
#include "sysemu/sysemu.h"
656
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
657
index XXXXXXX..XXXXXXX 100644
658
--- a/hw/arm/vexpress.c
659
+++ b/hw/arm/vexpress.c
660
@@ -XXX,XX +XXX,XX @@
661
#include "qemu-common.h"
662
#include "cpu.h"
663
#include "hw/sysbus.h"
664
-#include "hw/arm/arm.h"
665
+#include "hw/arm/boot.h"
666
#include "hw/arm/primecell.h"
667
#include "hw/net/lan9118.h"
668
#include "hw/i2c/i2c.h"
669
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
19
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
670
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
671
--- a/hw/arm/virt.c
21
--- a/hw/arm/virt.c
672
+++ b/hw/arm/virt.c
22
+++ b/hw/arm/virt.c
673
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ static void create_smmu(const VirtMachineState *vms,
674
#include "qemu/option.h"
24
qemu_fdt_setprop(ms->fdt, node, "interrupt-names", irq_names,
675
#include "qapi/error.h"
25
sizeof(irq_names));
676
#include "hw/sysbus.h"
26
677
-#include "hw/arm/arm.h"
27
- qemu_fdt_setprop_cell(ms->fdt, node, "clocks", vms->clock_phandle);
678
+#include "hw/arm/boot.h"
28
- qemu_fdt_setprop_string(ms->fdt, node, "clock-names", "apb_pclk");
679
#include "hw/arm/primecell.h"
29
qemu_fdt_setprop(ms->fdt, node, "dma-coherent", NULL, 0);
680
#include "hw/arm/virt.h"
30
681
#include "hw/block/flash.h"
31
qemu_fdt_setprop_cell(ms->fdt, node, "#iommu-cells", 1);
682
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
683
index XXXXXXX..XXXXXXX 100644
684
--- a/hw/arm/xilinx_zynq.c
685
+++ b/hw/arm/xilinx_zynq.c
686
@@ -XXX,XX +XXX,XX @@
687
#include "qemu-common.h"
688
#include "cpu.h"
689
#include "hw/sysbus.h"
690
-#include "hw/arm/arm.h"
691
+#include "hw/arm/boot.h"
692
#include "net/net.h"
693
#include "exec/address-spaces.h"
694
#include "sysemu/sysemu.h"
695
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
696
index XXXXXXX..XXXXXXX 100644
697
--- a/hw/arm/xlnx-versal.c
698
+++ b/hw/arm/xlnx-versal.c
699
@@ -XXX,XX +XXX,XX @@
700
#include "net/net.h"
701
#include "sysemu/sysemu.h"
702
#include "sysemu/kvm.h"
703
-#include "hw/arm/arm.h"
704
+#include "hw/arm/boot.h"
705
#include "kvm_arm.h"
706
#include "hw/misc/unimp.h"
707
#include "hw/intc/arm_gicv3_common.h"
708
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
709
index XXXXXXX..XXXXXXX 100644
710
--- a/hw/arm/z2.c
711
+++ b/hw/arm/z2.c
712
@@ -XXX,XX +XXX,XX @@
713
#include "qemu/osdep.h"
714
#include "hw/hw.h"
715
#include "hw/arm/pxa.h"
716
-#include "hw/arm/arm.h"
717
+#include "hw/arm/boot.h"
718
#include "hw/i2c/i2c.h"
719
#include "hw/ssi/ssi.h"
720
#include "hw/boards.h"
721
--
32
--
722
2.20.1
33
2.25.1
723
724
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/12] hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
[PULL 10/10] target/arm: mark SP_EL1 with ARM_CP_EL3_NO_EL2_KEEP
1
In ich_vmcr_write() we enforce "writes of BPR fields to less than
1
From: Jerome Forissier <jerome.forissier@linaro.org>
2
their minimum sets them to the minimum" by doing a "read vbpr and
3
write it back" operation. A typo here meant that we weren't handling
4
writes to these fields correctly, because we were reading from VBPR0
5
but writing to VBPR1.
6
2
3
SP_EL1 must be kept when EL3 is present but EL2 is not. Therefore mark
4
it with ARM_CP_EL3_NO_EL2_KEEP.
5
6
Cc: qemu-stable@nongnu.org
7
Fixes: 696ba3771894 ("target/arm: Handle cpreg registration for missing EL")
8
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20220927120058.670901-1-jerome.forissier@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20190520162809.2677-4-peter.maydell@linaro.org
10
---
12
---
11
hw/intc/arm_gicv3_cpuif.c | 2 +-
13
target/arm/helper.c | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
13
15
14
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/arm_gicv3_cpuif.c
18
--- a/target/arm/helper.c
17
+++ b/hw/intc/arm_gicv3_cpuif.c
19
+++ b/target/arm/helper.c
18
@@ -XXX,XX +XXX,XX @@ static void ich_vmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
20
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
19
/* Enforce "writing BPRs to less than minimum sets them to the minimum"
21
.fieldoffset = offsetof(CPUARMState, sp_el[0]) },
20
* by reading and writing back the fields.
22
{ .name = "SP_EL1", .state = ARM_CP_STATE_AA64,
21
*/
23
.opc0 = 3, .opc1 = 4, .crn = 4, .crm = 1, .opc2 = 0,
22
- write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G0));
24
- .access = PL2_RW, .type = ARM_CP_ALIAS,
23
+ write_vbpr(cs, GICV3_G0, read_vbpr(cs, GICV3_G0));
25
+ .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_KEEP,
24
write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G1));
26
.fieldoffset = offsetof(CPUARMState, sp_el[1]) },
25
27
{ .name = "SPSel", .state = ARM_CP_STATE_AA64,
26
gicv3_cpuif_virt_update(cs);
28
.opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
27
--
29
--
28
2.20.1
30
2.25.1
29
30
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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