[Qemu-devel] [PULL 00/12] target-arm queue
[PULL 00/21] target-arm queue
1
Not very much here, but several people have fallen over
1
Mostly straightforward bugfixes. The new Xilinx devices are
2
the vector operation segfault bug, so let's get the fix
2
arguably 'new feature', but they're fixing a regression where
3
into master.
3
our changes to PSCI in commit 3f37979bf mean that EL3 guest
4
code now needs to talk to a proper emulated power-controller
5
device to turn on secondary CPUs; and it's not yet rc1 and
6
they only affect the Xilinx board, so it seems OK to me.
4
7
5
thanks
8
thanks
6
-- PMM
9
-- PMM
7
10
8
The following changes since commit d418238dca7b4e0b124135827ead3076233052b1:
11
The following changes since commit 1d60bb4b14601e38ed17384277aa4c30c57925d3:
9
12
10
Merge remote-tracking branch 'remotes/rth/tags/pull-rng-20190522' into staging (2019-05-23 12:57:17 +0100)
13
Merge tag 'pull-request-2022-03-15v2' of https://gitlab.com/thuth/qemu into staging (2022-03-16 10:43:58 +0000)
11
14
12
are available in the Git repository at:
15
are available in the Git repository at:
13
16
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190523
17
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220318
15
18
16
for you to fetch changes up to 98e4f4fdb8ea05d840f51f47125924c2bb9df2df:
19
for you to fetch changes up to 79d54c9eac04c554e3c081589542f801ace71797:
17
20
18
hw/arm/exynos4210: QOM'ify the Exynos4210 SoC (2019-05-23 14:47:44 +0100)
21
util/osdep: Remove some early cruft (2022-03-18 11:32:13 +0000)
19
22
20
----------------------------------------------------------------
23
----------------------------------------------------------------
21
target-arm queue:
24
target-arm queue:
22
* exynos4210: QOM'ify the Exynos4210 SoC
25
* Fix sve2 ldnt1 and stnt1
23
* exynos4210: Add DMA support for the Exynos4210
26
* Fix pauth_check_trap vs SEL2
24
* arm_gicv3: Fix writes to ICC_CTLR_EL3
27
* Fix handling of LPAE block descriptors
25
* arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
28
* hw/dma/xlnx_csu_dma: Set TYPE_XLNX_CSU_DMA class_size
26
* target/arm: Fix vector operation segfault
29
* hw/misc/npcm7xx_clk: Don't leak string in npcm7xx_clk_sel_init()
27
* target/arm: Minor improvements to BFXIL, EXTR
30
* nsis installer: List emulators in alphabetical order
31
* nsis installer: Suppress "ANSI targets are deprecated" warning
32
* nsis installer: Fix mouse-over descriptions for emulators
33
* hw/arm/virt: Fix gic-version=max when CONFIG_ARM_GICV3_TCG is unset
34
* Improve M-profile vector table access logging
35
* Xilinx ZynqMP: model CRF and APU control
36
* Fix compile issues on modern Solaris
28
37
29
----------------------------------------------------------------
38
----------------------------------------------------------------
30
Alistair Francis (1):
39
Andrew Deason (3):
31
target/arm: Fix vector operation segfault
40
util/osdep: Avoid madvise proto on modern Solaris
41
hw/i386/acpi-build: Avoid 'sun' identifier
42
util/osdep: Remove some early cruft
32
43
33
Guenter Roeck (1):
44
Edgar E. Iglesias (6):
34
hw/arm/exynos4210: Add DMA support for the Exynos4210
45
hw/arm/xlnx-zynqmp: Add an unimplemented SERDES area
46
target/arm: Make rvbar settable after realize
47
hw/misc: Add a model of the Xilinx ZynqMP CRF
48
hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF
49
hw/misc: Add a model of the Xilinx ZynqMP APU Control
50
hw/arm/xlnx-zynqmp: Connect the ZynqMP APU Control
35
51
36
Peter Maydell (5):
52
Eric Auger (2):
37
arm: Move system_clock_scale to armv7m_systick.h
53
hw/intc: Rename CONFIG_ARM_GIC_TCG into CONFIG_ARM_GICV3_TCG
38
arm: Remove unnecessary includes of hw/arm/arm.h
54
hw/arm/virt: Fix gic-version=max when CONFIG_ARM_GICV3_TCG is unset
39
arm: Rename hw/arm/arm.h to hw/arm/boot.h
40
hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
41
hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3
42
55
43
Philippe Mathieu-Daudé (3):
56
Peter Maydell (8):
44
hw/arm/exynos4: Remove unuseful debug code
57
target/arm: Fix handling of LPAE block descriptors
45
hw/arm/exynos4: Use the IEC binary prefix definitions
58
hw/dma/xlnx_csu_dma: Set TYPE_XLNX_CSU_DMA class_size
46
hw/arm/exynos4210: QOM'ify the Exynos4210 SoC
59
hw/misc/npcm7xx_clk: Don't leak string in npcm7xx_clk_sel_init()
60
nsis installer: List emulators in alphabetical order
61
nsis installer: Suppress "ANSI targets are deprecated" warning
62
nsis installer: Fix mouse-over descriptions for emulators
63
target/arm: Log M-profile vector table accesses
64
target/arm: Log fault address for M-profile faults
47
65
48
Richard Henderson (2):
66
Richard Henderson (2):
49
target/arm: Use extract2 for EXTR
67
target/arm: Fix sve2 ldnt1 and stnt1
50
target/arm: Simplify BFXIL expansion
68
target/arm: Fix pauth_check_trap vs SEL2
51
69
52
include/hw/arm/allwinner-a10.h | 2 +-
70
meson.build | 23 ++-
53
include/hw/arm/aspeed_soc.h | 1 -
71
include/hw/arm/xlnx-zynqmp.h | 4 +
54
include/hw/arm/bcm2836.h | 1 -
72
include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 93 ++++++++++++
55
include/hw/arm/{arm.h => boot.h} | 12 +++------
73
include/hw/misc/xlnx-zynqmp-crf.h | 211 ++++++++++++++++++++++++++
56
include/hw/arm/exynos4210.h | 9 +++++--
74
include/qemu/osdep.h | 8 +
57
include/hw/arm/fsl-imx25.h | 2 +-
75
target/arm/cpu.h | 3 +-
58
include/hw/arm/fsl-imx31.h | 2 +-
76
target/arm/sve.decode | 5 +-
59
include/hw/arm/fsl-imx6.h | 2 +-
77
hw/arm/virt.c | 7 +-
60
include/hw/arm/fsl-imx6ul.h | 2 +-
78
hw/arm/xlnx-zynqmp.c | 46 +++++-
61
include/hw/arm/fsl-imx7.h | 2 +-
79
hw/dma/xlnx_csu_dma.c | 1 +
62
include/hw/arm/virt.h | 2 +-
80
hw/i386/acpi-build.c | 4 +-
63
include/hw/arm/xlnx-versal.h | 2 +-
81
hw/misc/npcm7xx_clk.c | 4 +-
64
include/hw/arm/xlnx-zynqmp.h | 2 +-
82
hw/misc/xlnx-zynqmp-apu-ctrl.c | 253 +++++++++++++++++++++++++++++++
65
include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++
83
hw/misc/xlnx-zynqmp-crf.c | 266 +++++++++++++++++++++++++++++++++
66
hw/arm/armsse.c | 2 +-
84
target/arm/cpu.c | 17 ++-
67
hw/arm/armv7m.c | 2 +-
85
target/arm/helper.c | 20 ++-
68
hw/arm/aspeed.c | 2 +-
86
target/arm/m_helper.c | 11 ++
69
hw/arm/boot.c | 2 +-
87
target/arm/pauth_helper.c | 2 +-
70
hw/arm/collie.c | 2 +-
88
target/arm/translate-sve.c | 51 ++++++-
71
hw/arm/exynos4210.c | 54 ++++++++++++++++++++++++++++++++++++---
89
tests/tcg/aarch64/test-826.c | 50 +++++++
72
hw/arm/exynos4_boards.c | 40 ++++++++---------------------
90
util/osdep.c | 10 --
73
hw/arm/highbank.c | 2 +-
91
hw/intc/Kconfig | 2 +-
74
hw/arm/integratorcp.c | 2 +-
92
hw/intc/meson.build | 4 +-
75
hw/arm/mainstone.c | 2 +-
93
hw/misc/meson.build | 2 +
76
hw/arm/microbit.c | 2 +-
94
qemu.nsi | 8 +-
77
hw/arm/mps2-tz.c | 2 +-
95
scripts/nsis.py | 17 ++-
78
hw/arm/mps2.c | 2 +-
96
tests/tcg/aarch64/Makefile.target | 4 +
79
hw/arm/msf2-soc.c | 1 -
97
tests/tcg/configure.sh | 4 +
80
hw/arm/msf2-som.c | 2 +-
98
28 files changed, 1084 insertions(+), 46 deletions(-)
81
hw/arm/musca.c | 2 +-
99
create mode 100644 include/hw/misc/xlnx-zynqmp-apu-ctrl.h
82
hw/arm/musicpal.c | 2 +-
100
create mode 100644 include/hw/misc/xlnx-zynqmp-crf.h
83
hw/arm/netduino2.c | 2 +-
101
create mode 100644 hw/misc/xlnx-zynqmp-apu-ctrl.c
84
hw/arm/nrf51_soc.c | 2 +-
102
create mode 100644 hw/misc/xlnx-zynqmp-crf.c
85
hw/arm/nseries.c | 2 +-
103
create mode 100644 tests/tcg/aarch64/test-826.c
86
hw/arm/omap1.c | 2 +-
87
hw/arm/omap2.c | 2 +-
88
hw/arm/omap_sx1.c | 2 +-
89
hw/arm/palm.c | 2 +-
90
hw/arm/raspi.c | 2 +-
91
hw/arm/realview.c | 2 +-
92
hw/arm/spitz.c | 2 +-
93
hw/arm/stellaris.c | 2 +-
94
hw/arm/stm32f205_soc.c | 2 +-
95
hw/arm/strongarm.c | 2 +-
96
hw/arm/tosa.c | 2 +-
97
hw/arm/versatilepb.c | 2 +-
98
hw/arm/vexpress.c | 2 +-
99
hw/arm/virt.c | 2 +-
100
hw/arm/xilinx_zynq.c | 2 +-
101
hw/arm/xlnx-versal.c | 2 +-
102
hw/arm/z2.c | 2 +-
103
hw/intc/arm_gicv3_cpuif.c | 6 ++---
104
hw/intc/armv7m_nvic.c | 1 -
105
target/arm/arm-semi.c | 1 -
106
target/arm/cpu.c | 1 -
107
target/arm/cpu64.c | 1 -
108
target/arm/kvm.c | 1 -
109
target/arm/kvm32.c | 1 -
110
target/arm/kvm64.c | 1 -
111
target/arm/translate-a64.c | 44 ++++++++++++++++---------------
112
target/arm/translate.c | 4 +--
113
61 files changed, 164 insertions(+), 123 deletions(-)
114
rename include/hw/arm/{arm.h => boot.h} (96%)
115
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/12] target/arm: Simplify BFXIL expansion
[PULL 01/21] target/arm: Fix sve2 ldnt1 and stnt1
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The mask implied by the extract is redundant with the one
3
For both ldnt1 and stnt1, the meaning of the Rn and Rm are different
4
implied by the deposit. Also, fix spelling of BFXIL.
4
from ld1 and st1: the vector and integer registers are reversed, and
5
5
the integer register 31 refers to XZR instead of SP.
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
7
Secondly, the 64-bit version of ldnt1 was being interpreted as
8
32-bit unpacked unscaled offset instead of 64-bit unscaled offset,
9
which discarded the upper 32 bits of the address coming from
10
the vector argument.
11
12
Thirdly, validate that the memory element size is in range for the
13
vector element size for ldnt1. For ld1, we do this via independent
14
decode patterns, but for ldnt1 we need to do it manually.
15
16
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/826
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
17
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20190514011129.11330-3-richard.henderson@linaro.org
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Message-id: 20220308031655.240710-1-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
21
---
11
target/arm/translate-a64.c | 6 +++---
22
target/arm/sve.decode | 5 ++-
12
1 file changed, 3 insertions(+), 3 deletions(-)
23
target/arm/translate-sve.c | 51 +++++++++++++++++++++++++++++--
13
24
tests/tcg/aarch64/test-826.c | 50 ++++++++++++++++++++++++++++++
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
25
tests/tcg/aarch64/Makefile.target | 4 +++
26
tests/tcg/configure.sh | 4 +++
27
5 files changed, 109 insertions(+), 5 deletions(-)
28
create mode 100644 tests/tcg/aarch64/test-826.c
29
30
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
15
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
32
--- a/target/arm/sve.decode
17
+++ b/target/arm/translate-a64.c
33
+++ b/target/arm/sve.decode
18
@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
34
@@ -XXX,XX +XXX,XX @@ USDOT_zzzz 01000100 .. 0 ..... 011 110 ..... ..... @rda_rn_rm
19
tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len);
35
20
return;
36
### SVE2 Memory Gather Load Group
21
}
37
22
- /* opc == 1, BXFIL fall through to deposit */
38
-# SVE2 64-bit gather non-temporal load
23
- tcg_gen_extract_i64(tcg_tmp, tcg_tmp, ri, len);
39
-# (scalar plus unpacked 32-bit unscaled offsets)
24
+ /* opc == 1, BFXIL fall through to deposit */
40
+# SVE2 64-bit gather non-temporal load (scalar plus 64-bit unscaled offsets)
25
+ tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri);
41
LDNT1_zprz 1100010 msz:2 00 rm:5 1 u:1 0 pg:3 rn:5 rd:5 \
26
pos = 0;
42
- &rprr_gather_load xs=0 esz=3 scale=0 ff=0
27
} else {
43
+ &rprr_gather_load xs=2 esz=3 scale=0 ff=0
28
/* Handle the ri > si case with a deposit
44
29
@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
45
# SVE2 32-bit gather non-temporal load (scalar plus 32-bit unscaled offsets)
30
len = ri;
46
LDNT1_zprz 1000010 msz:2 00 rm:5 10 u:1 pg:3 rn:5 rd:5 \
47
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/translate-sve.c
50
+++ b/target/arm/translate-sve.c
51
@@ -XXX,XX +XXX,XX @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_zpiz *a)
52
53
static bool trans_LDNT1_zprz(DisasContext *s, arg_LD1_zprz *a)
54
{
55
+ gen_helper_gvec_mem_scatter *fn = NULL;
56
+ bool be = s->be_data == MO_BE;
57
+ bool mte = s->mte_active[0];
58
+
59
+ if (a->esz < a->msz + !a->u) {
60
+ return false;
61
+ }
62
if (!dc_isar_feature(aa64_sve2, s)) {
63
return false;
31
}
64
}
32
65
- return trans_LD1_zprz(s, a);
33
- if (opc == 1) { /* BFM, BXFIL */
66
+ if (!sve_access_check(s)) {
34
+ if (opc == 1) { /* BFM, BFXIL */
67
+ return true;
35
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len);
68
+ }
36
} else {
69
+
37
/* SBFM or UBFM: We start with zero, and we haven't modified
70
+ switch (a->esz) {
71
+ case MO_32:
72
+ fn = gather_load_fn32[mte][be][0][0][a->u][a->msz];
73
+ break;
74
+ case MO_64:
75
+ fn = gather_load_fn64[mte][be][0][2][a->u][a->msz];
76
+ break;
77
+ }
78
+ assert(fn != NULL);
79
+
80
+ do_mem_zpz(s, a->rd, a->pg, a->rn, 0,
81
+ cpu_reg(s, a->rm), a->msz, false, fn);
82
+ return true;
83
}
84
85
/* Indexed by [mte][be][xs][msz]. */
86
@@ -XXX,XX +XXX,XX @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_zpiz *a)
87
88
static bool trans_STNT1_zprz(DisasContext *s, arg_ST1_zprz *a)
89
{
90
+ gen_helper_gvec_mem_scatter *fn;
91
+ bool be = s->be_data == MO_BE;
92
+ bool mte = s->mte_active[0];
93
+
94
+ if (a->esz < a->msz) {
95
+ return false;
96
+ }
97
if (!dc_isar_feature(aa64_sve2, s)) {
98
return false;
99
}
100
- return trans_ST1_zprz(s, a);
101
+ if (!sve_access_check(s)) {
102
+ return true;
103
+ }
104
+
105
+ switch (a->esz) {
106
+ case MO_32:
107
+ fn = scatter_store_fn32[mte][be][0][a->msz];
108
+ break;
109
+ case MO_64:
110
+ fn = scatter_store_fn64[mte][be][2][a->msz];
111
+ break;
112
+ default:
113
+ g_assert_not_reached();
114
+ }
115
+
116
+ do_mem_zpz(s, a->rd, a->pg, a->rn, 0,
117
+ cpu_reg(s, a->rm), a->msz, true, fn);
118
+ return true;
119
}
120
121
/*
122
diff --git a/tests/tcg/aarch64/test-826.c b/tests/tcg/aarch64/test-826.c
123
new file mode 100644
124
index XXXXXXX..XXXXXXX
125
--- /dev/null
126
+++ b/tests/tcg/aarch64/test-826.c
127
@@ -XXX,XX +XXX,XX @@
128
+#include <sys/mman.h>
129
+#include <unistd.h>
130
+#include <signal.h>
131
+#include <stdlib.h>
132
+#include <stdio.h>
133
+#include <assert.h>
134
+
135
+static void *expected;
136
+
137
+void sigsegv(int sig, siginfo_t *info, void *vuc)
138
+{
139
+ ucontext_t *uc = vuc;
140
+
141
+ assert(info->si_addr == expected);
142
+ uc->uc_mcontext.pc += 4;
143
+}
144
+
145
+int main()
146
+{
147
+ struct sigaction sa = {
148
+ .sa_sigaction = sigsegv,
149
+ .sa_flags = SA_SIGINFO
150
+ };
151
+
152
+ void *page;
153
+ long ofs;
154
+
155
+ if (sigaction(SIGSEGV, &sa, NULL) < 0) {
156
+ perror("sigaction");
157
+ return EXIT_FAILURE;
158
+ }
159
+
160
+ page = mmap(0, getpagesize(), PROT_NONE, MAP_PRIVATE | MAP_ANON, -1, 0);
161
+ if (page == MAP_FAILED) {
162
+ perror("mmap");
163
+ return EXIT_FAILURE;
164
+ }
165
+
166
+ ofs = 0x124;
167
+ expected = page + ofs;
168
+
169
+ asm("ptrue p0.d, vl1\n\t"
170
+ "dup z0.d, %0\n\t"
171
+ "ldnt1h {z1.d}, p0/z, [z0.d, %1]\n\t"
172
+ "dup z1.d, %1\n\t"
173
+ "ldnt1h {z0.d}, p0/z, [z1.d, %0]"
174
+ : : "r"(page), "r"(ofs) : "v0", "v1");
175
+
176
+ return EXIT_SUCCESS;
177
+}
178
diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target
179
index XXXXXXX..XXXXXXX 100644
180
--- a/tests/tcg/aarch64/Makefile.target
181
+++ b/tests/tcg/aarch64/Makefile.target
182
@@ -XXX,XX +XXX,XX @@ run-gdbstub-sve-ioctls: sve-ioctls
183
184
EXTRA_RUNS += run-gdbstub-sysregs run-gdbstub-sve-ioctls
185
endif
186
+endif
187
188
+ifneq ($(DOCKER_IMAGE)$(CROSS_CC_HAS_SVE2),)
189
+AARCH64_TESTS += test-826
190
+test-826: CFLAGS+=-march=armv8.1-a+sve2
191
endif
192
193
TESTS += $(AARCH64_TESTS)
194
diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh
195
index XXXXXXX..XXXXXXX 100755
196
--- a/tests/tcg/configure.sh
197
+++ b/tests/tcg/configure.sh
198
@@ -XXX,XX +XXX,XX @@ for target in $target_list; do
199
-march=armv8.1-a+sve -o $TMPE $TMPC; then
200
echo "CROSS_CC_HAS_SVE=y" >> $config_target_mak
201
fi
202
+ if do_compiler "$target_compiler" $target_compiler_cflags \
203
+ -march=armv8.1-a+sve2 -o $TMPE $TMPC; then
204
+ echo "CROSS_CC_HAS_SVE2=y" >> $config_target_mak
205
+ fi
206
if do_compiler "$target_compiler" $target_compiler_cflags \
207
-march=armv8.3-a -o $TMPE $TMPC; then
208
echo "CROSS_CC_HAS_ARMV8_3=y" >> $config_target_mak
38
--
209
--
39
2.20.1
210
2.25.1
40
41
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/12] target/arm: Use extract2 for EXTR
[PULL 02/21] target/arm: Fix pauth_check_trap vs SEL2
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This is, after all, how we implement extract2 in tcg/aarch64.
3
When arm_is_el2_enabled was introduced, we missed
4
updating pauth_check_trap.
4
5
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/788
7
Fixes: e6ef0169264b ("target/arm: use arm_is_el2_enabled() where applicable")
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20190514011129.11330-2-richard.henderson@linaro.org
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20220315021205.342768-1-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
12
---
10
target/arm/translate-a64.c | 38 ++++++++++++++++++++------------------
13
target/arm/pauth_helper.c | 2 +-
11
1 file changed, 20 insertions(+), 18 deletions(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
12
15
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c
14
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
18
--- a/target/arm/pauth_helper.c
16
+++ b/target/arm/translate-a64.c
19
+++ b/target/arm/pauth_helper.c
17
@@ -XXX,XX +XXX,XX @@ static void disas_extract(DisasContext *s, uint32_t insn)
20
@@ -XXX,XX +XXX,XX @@ static void QEMU_NORETURN pauth_trap(CPUARMState *env, int target_el,
18
} else {
21
19
tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));
22
static void pauth_check_trap(CPUARMState *env, int el, uintptr_t ra)
20
}
23
{
21
- } else if (rm == rn) { /* ROR */
24
- if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) {
22
- tcg_rm = cpu_reg(s, rm);
25
+ if (el < 2 && arm_is_el2_enabled(env)) {
23
- if (sf) {
26
uint64_t hcr = arm_hcr_el2_eff(env);
24
- tcg_gen_rotri_i64(tcg_rd, tcg_rm, imm);
27
bool trap = !(hcr & HCR_API);
25
- } else {
28
if (el == 0) {
26
- TCGv_i32 tmp = tcg_temp_new_i32();
27
- tcg_gen_extrl_i64_i32(tmp, tcg_rm);
28
- tcg_gen_rotri_i32(tmp, tmp, imm);
29
- tcg_gen_extu_i32_i64(tcg_rd, tmp);
30
- tcg_temp_free_i32(tmp);
31
- }
32
} else {
33
- tcg_rm = read_cpu_reg(s, rm, sf);
34
- tcg_rn = read_cpu_reg(s, rn, sf);
35
- tcg_gen_shri_i64(tcg_rm, tcg_rm, imm);
36
- tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm);
37
- tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn);
38
- if (!sf) {
39
- tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
40
+ tcg_rm = cpu_reg(s, rm);
41
+ tcg_rn = cpu_reg(s, rn);
42
+
43
+ if (sf) {
44
+ /* Specialization to ROR happens in EXTRACT2. */
45
+ tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, imm);
46
+ } else {
47
+ TCGv_i32 t0 = tcg_temp_new_i32();
48
+
49
+ tcg_gen_extrl_i64_i32(t0, tcg_rm);
50
+ if (rm == rn) {
51
+ tcg_gen_rotri_i32(t0, t0, imm);
52
+ } else {
53
+ TCGv_i32 t1 = tcg_temp_new_i32();
54
+ tcg_gen_extrl_i64_i32(t1, tcg_rn);
55
+ tcg_gen_extract2_i32(t0, t0, t1, imm);
56
+ tcg_temp_free_i32(t1);
57
+ }
58
+ tcg_gen_extu_i32_i64(tcg_rd, t0);
59
+ tcg_temp_free_i32(t0);
60
}
61
}
62
}
63
--
29
--
64
2.20.1
30
2.25.1
65
31
66
32
diff view generated by jsdifflib
New patch
[PULL 03/21] target/arm: Fix handling of LPAE block descriptors
1
LPAE descriptors come in three forms:
1
2
3
* table descriptors, giving the address of the next level page table
4
* page descriptors, which occur only at level 3 and describe the
5
mapping of one page (which might be 4K, 16K or 64K)
6
* block descriptors, which occur at higher page table levels, and
7
describe the mapping of huge pages
8
9
QEMU's page-table-walk code treats block and page entries
10
identically, simply ORing in a number of bits from the input virtual
11
address that depends on the level of the page table that we stopped
12
at; we depend on the previous masking of descaddr with descaddrmask
13
to have already cleared out the low bits of the descriptor word.
14
15
This is not quite right: the address field in a block descriptor is
16
smaller, and so there are bits which are valid address bits in a page
17
descriptor or a table descriptor but which are not supposed to be
18
part of the address in a block descriptor, and descaddrmask does not
19
clear them. We previously mostly got away with this because those
20
descriptor bits are RES0; however with FEAT_BBM (part of Armv8.4)
21
block descriptor bit 16 is defined to be the nT bit. No emulated
22
QEMU CPU has FEAT_BBM yet, but if the host CPU has it then we might
23
see it when using KVM or hvf.
24
25
Explicitly zero out all the descaddr bits we're about to OR vaddr
26
bits into.
27
28
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/790
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
30
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
31
Message-id: 20220304165628.2345765-1-peter.maydell@linaro.org
32
---
33
target/arm/helper.c | 10 ++++++++--
34
1 file changed, 8 insertions(+), 2 deletions(-)
35
36
diff --git a/target/arm/helper.c b/target/arm/helper.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/helper.c
39
+++ b/target/arm/helper.c
40
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
41
indexmask = indexmask_grainsize;
42
continue;
43
}
44
- /* Block entry at level 1 or 2, or page entry at level 3.
45
+ /*
46
+ * Block entry at level 1 or 2, or page entry at level 3.
47
* These are basically the same thing, although the number
48
- * of bits we pull in from the vaddr varies.
49
+ * of bits we pull in from the vaddr varies. Note that although
50
+ * descaddrmask masks enough of the low bits of the descriptor
51
+ * to give a correct page or table address, the address field
52
+ * in a block descriptor is smaller; so we need to explicitly
53
+ * clear the lower bits here before ORing in the low vaddr bits.
54
*/
55
page_size = (1ULL << ((stride * (4 - level)) + 3));
56
+ descaddr &= ~(page_size - 1);
57
descaddr |= (address & (page_size - 1));
58
/* Extract attributes from the descriptor */
59
attrs = extract64(descriptor, 2, 10)
60
--
61
2.25.1
diff view generated by jsdifflib
New patch
[PULL 04/21] hw/dma/xlnx_csu_dma: Set TYPE_XLNX_CSU_DMA class_size
1
In commit 00f05c02f9e7342f we gave the TYPE_XLNX_CSU_DMA object its
2
own class struct, but forgot to update the TypeInfo::class_size
3
accordingly. This meant that not enough memory was allocated for the
4
class struct, and the initialization of xcdc->read in the class init
5
function wrote off the end of the memory. Add the missing line.
1
6
7
Found by running 'check-qtest-aarch64' with a clang
8
address-sanitizer build, which complains:
9
10
==2542634==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x61000000ab00 at pc 0x559a20aebc29 bp 0x7fff97df74d0 sp 0x7fff97df74c8
11
WRITE of size 8 at 0x61000000ab00 thread T0
12
#0 0x559a20aebc28 in xlnx_csu_dma_class_init /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../hw/dma/xlnx_csu_dma.c:722:16
13
#1 0x559a21bf297c in type_initialize /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:365:9
14
#2 0x559a21bf3442 in object_class_foreach_tramp /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:1070:5
15
#3 0x7f09bcb641b7 in g_hash_table_foreach (/usr/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x401b7)
16
#4 0x559a21bf3c27 in object_class_foreach /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:1092:5
17
#5 0x559a21bf3c27 in object_class_get_list /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:1149:5
18
#6 0x559a2081a2fd in select_machine /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../softmmu/vl.c:1661:24
19
#7 0x559a2081a2fd in qemu_create_machine /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../softmmu/vl.c:2146:35
20
#8 0x559a2081a2fd in qemu_init /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../softmmu/vl.c:3706:5
21
#9 0x559a20720ed5 in main /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../softmmu/main.c:49:5
22
#10 0x7f09baec00b2 in __libc_start_main /build/glibc-sMfBJT/glibc-2.31/csu/../csu/libc-start.c:308:16
23
#11 0x559a2067673d in _start (/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/qemu-system-aarch64+0xf4b73d)
24
25
0x61000000ab00 is located 0 bytes to the right of 192-byte region [0x61000000aa40,0x61000000ab00)
26
allocated by thread T0 here:
27
#0 0x559a206eeff2 in calloc (/mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/qemu-system-aarch64+0xfc3ff2)
28
#1 0x7f09bcb7bef0 in g_malloc0 (/usr/lib/x86_64-linux-gnu/libglib-2.0.so.0+0x57ef0)
29
#2 0x559a21bf3442 in object_class_foreach_tramp /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/san/../../qom/object.c:1070:5
30
31
Fixes: 00f05c02f9e7342f ("hw/dma/xlnx_csu_dma: Support starting a read transfer through a class method")
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
34
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
35
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
36
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
37
Message-id: 20220308150207.2546272-1-peter.maydell@linaro.org
38
---
39
hw/dma/xlnx_csu_dma.c | 1 +
40
1 file changed, 1 insertion(+)
41
42
diff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/hw/dma/xlnx_csu_dma.c
45
+++ b/hw/dma/xlnx_csu_dma.c
46
@@ -XXX,XX +XXX,XX @@ static const TypeInfo xlnx_csu_dma_info = {
47
.parent = TYPE_SYS_BUS_DEVICE,
48
.instance_size = sizeof(XlnxCSUDMA),
49
.class_init = xlnx_csu_dma_class_init,
50
+ .class_size = sizeof(XlnxCSUDMAClass),
51
.instance_init = xlnx_csu_dma_init,
52
.interfaces = (InterfaceInfo[]) {
53
{ TYPE_STREAM_SINK },
54
--
55
2.25.1
56
57
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/12] hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3
[PULL 05/21] hw/misc/npcm7xx_clk: Don't leak string in npcm7xx_clk_sel_init()
1
The ICC_CTLR_EL3 register includes some bits which are aliases
1
In npcm7xx_clk_sel_init() we allocate a string with g_strdup_printf().
2
of bits in the ICC_CTLR_EL1(S) and (NS) registers. QEMU chooses
2
Use g_autofree so we free it rather than leaking it.
3
to keep those bits in the cs->icc_ctlr_el1[] struct fields.
3
4
Unfortunately a missing '~' in the code to update the bits
4
(Detected with the clang leak sanitizer.)
5
in those fields meant that writing to ICC_CTLR_EL3 would corrupt
6
the ICC_CLTR_EL1 register values.
7
5
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20190520162809.2677-5-peter.maydell@linaro.org
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20220308170302.2582820-1-peter.maydell@linaro.org
11
---
10
---
12
hw/intc/arm_gicv3_cpuif.c | 4 ++--
11
hw/misc/npcm7xx_clk.c | 4 ++--
13
1 file changed, 2 insertions(+), 2 deletions(-)
12
1 file changed, 2 insertions(+), 2 deletions(-)
14
13
15
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
14
diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/intc/arm_gicv3_cpuif.c
16
--- a/hw/misc/npcm7xx_clk.c
18
+++ b/hw/intc/arm_gicv3_cpuif.c
17
+++ b/hw/misc/npcm7xx_clk.c
19
@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
18
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_sel_init(Object *obj)
20
trace_gicv3_icc_ctlr_el3_write(gicv3_redist_affid(cs), value);
19
NPCM7xxClockSELState *sel = NPCM7XX_CLOCK_SEL(obj);
21
20
22
/* *_EL1NS and *_EL1S bits are aliases into the ICC_CTLR_EL1 bits. */
21
for (i = 0; i < NPCM7XX_CLK_SEL_MAX_INPUT; ++i) {
23
- cs->icc_ctlr_el1[GICV3_NS] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
22
- sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel),
24
+ cs->icc_ctlr_el1[GICV3_NS] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
23
- g_strdup_printf("clock-in[%d]", i),
25
if (value & ICC_CTLR_EL3_EOIMODE_EL1NS) {
24
+ g_autofree char *s = g_strdup_printf("clock-in[%d]", i);
26
cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE;
25
+ sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel), s,
26
npcm7xx_clk_update_sel_cb, sel, ClockUpdate);
27
}
27
}
28
@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
28
sel->clock_out = qdev_init_clock_out(DEVICE(sel), "clock-out");
29
cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_CBPR;
30
}
31
32
- cs->icc_ctlr_el1[GICV3_S] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
33
+ cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
34
if (value & ICC_CTLR_EL3_EOIMODE_EL1S) {
35
cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_EOIMODE;
36
}
37
--
29
--
38
2.20.1
30
2.25.1
39
31
40
32
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/12] target/arm: Fix vector operation segfault
[PULL 06/21] nsis installer: List emulators in alphabetical order
1
From: Alistair Francis <alistair.francis@wdc.com>
1
We currently list the emulators in the Windows installer's dialog
2
in an essentially random order (it's whatever glob.glob() returns
3
them to, which is filesystem-implementation-dependent). Add a
4
call to sorted() so they appear in alphabetical order.
2
5
3
Commit 89e68b575 "target/arm: Use vector operations for saturation"
4
causes this abort() when booting QEMU ARM with a Cortex-A15:
5
6
0 0x00007ffff4c2382f in raise () at /usr/lib/libc.so.6
7
1 0x00007ffff4c0e672 in abort () at /usr/lib/libc.so.6
8
2 0x00005555559c1839 in disas_neon_data_insn (insn=<optimized out>, s=<optimized out>) at ./target/arm/translate.c:6673
9
3 0x00005555559c1839 in disas_neon_data_insn (s=<optimized out>, insn=<optimized out>) at ./target/arm/translate.c:6386
10
4 0x00005555559cd8a4 in disas_arm_insn (insn=4081107068, s=0x7fffe59a9510) at ./target/arm/translate.c:9289
11
5 0x00005555559cd8a4 in arm_tr_translate_insn (dcbase=0x7fffe59a9510, cpu=<optimized out>) at ./target/arm/translate.c:13612
12
6 0x00005555558d1d39 in translator_loop (ops=0x5555561cc580 <arm_translator_ops>, db=0x7fffe59a9510, cpu=0x55555686a2f0, tb=<optimized out>, max_insns=<optimized out>) at ./accel/tcg/translator.c:96
13
7 0x00005555559d10d4 in gen_intermediate_code (cpu=cpu@entry=0x55555686a2f0, tb=tb@entry=0x7fffd7840080 <code_gen_buffer+126091347>, max_insns=max_insns@entry=512) at ./target/arm/translate.c:13901
14
8 0x00005555558d06b9 in tb_gen_code (cpu=cpu@entry=0x55555686a2f0, pc=3067096216, cs_base=0, flags=192, cflags=-16252928, cflags@entry=524288) at ./accel/tcg/translate-all.c:1736
15
9 0x00005555558ce467 in tb_find (cf_mask=524288, tb_exit=1, last_tb=0x7fffd783e640 <code_gen_buffer+126084627>, cpu=0x1) at ./accel/tcg/cpu-exec.c:407
16
10 0x00005555558ce467 in cpu_exec (cpu=cpu@entry=0x55555686a2f0) at ./accel/tcg/cpu-exec.c:728
17
11 0x000055555588b0cf in tcg_cpu_exec (cpu=0x55555686a2f0) at ./cpus.c:1431
18
12 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=0x55555686a2f0) at ./cpus.c:1735
19
13 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=arg@entry=0x55555686a2f0) at ./cpus.c:1709
20
14 0x0000555555d2629a in qemu_thread_start (args=<optimized out>) at ./util/qemu-thread-posix.c:502
21
15 0x00007ffff4db8a92 in start_thread () at /usr/lib/libpthread.
22
23
This patch ensures that we don't hit the abort() in the second switch
24
case in disas_neon_data_insn() as we will return from the first case.
25
26
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
27
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
28
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
29
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
30
Tested-by: Alex Bennée <alex.bennee@linaro.org>
31
Message-id: ad91b397f360b2fc7f4087e476f7df5b04d42ddb.1558021877.git.alistair.francis@wdc.com
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Stefan Weil <sw@weilnetz.de>
9
Reviewed-by: John Snow <jsnow@redhat.com>
10
Message-id: 20220305105743.2384766-2-peter.maydell@linaro.org
33
---
11
---
34
target/arm/translate.c | 4 ++--
12
scripts/nsis.py | 4 ++--
35
1 file changed, 2 insertions(+), 2 deletions(-)
13
1 file changed, 2 insertions(+), 2 deletions(-)
36
14
37
diff --git a/target/arm/translate.c b/target/arm/translate.c
15
diff --git a/scripts/nsis.py b/scripts/nsis.py
38
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/translate.c
17
--- a/scripts/nsis.py
40
+++ b/target/arm/translate.c
18
+++ b/scripts/nsis.py
41
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
19
@@ -XXX,XX +XXX,XX @@ def main():
42
tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
20
with open(
43
rn_ofs, rm_ofs, vec_size, vec_size,
21
os.path.join(destdir + args.prefix, "system-emulations.nsh"), "w"
44
(u ? uqadd_op : sqadd_op) + size);
22
) as nsh:
45
- break;
23
- for exe in glob.glob(
46
+ return 0;
24
+ for exe in sorted(glob.glob(
47
25
os.path.join(destdir + args.prefix, "qemu-system-*.exe")
48
case NEON_3R_VQSUB:
26
- ):
49
tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
27
+ )):
50
rn_ofs, rm_ofs, vec_size, vec_size,
28
exe = os.path.basename(exe)
51
(u ? uqsub_op : sqsub_op) + size);
29
arch = exe[12:-4]
52
- break;
30
nsh.write(
53
+ return 0;
54
55
case NEON_3R_VMUL: /* VMUL */
56
if (u) {
57
--
31
--
58
2.20.1
32
2.25.1
59
33
60
34
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/12] hw/arm/exynos4210: QOM'ify the Exynos4210 SoC
[PULL 07/21] nsis installer: Suppress "ANSI targets are deprecated" warning
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
When we build our Windows installer, it emits the warning:
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
3
warning 7998: ANSI targets are deprecated
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
4
5
Message-id: 20190520214342.13709-5-philmd@redhat.com
5
Fix this by making our installer a Unicode installer instead. These
6
won't work on Win95/98/ME, but we already do not support those.
7
8
See
9
https://nsis.sourceforge.io/Docs/Chapter4.html#aunicodetarget
10
for the documentation of the Unicode directive.
11
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Reviewed-by: Stefan Weil <sw@weilnetz.de>
15
Message-id: 20220305105743.2384766-3-peter.maydell@linaro.org
7
---
16
---
8
include/hw/arm/exynos4210.h | 9 +++++++--
17
qemu.nsi | 3 +++
9
hw/arm/exynos4210.c | 28 ++++++++++++++++++++++++----
18
1 file changed, 3 insertions(+)
10
hw/arm/exynos4_boards.c | 9 ++++++---
11
3 files changed, 37 insertions(+), 9 deletions(-)
12
19
13
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
20
diff --git a/qemu.nsi b/qemu.nsi
14
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/arm/exynos4210.h
22
--- a/qemu.nsi
16
+++ b/include/hw/arm/exynos4210.h
23
+++ b/qemu.nsi
17
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210Irq {
24
@@ -XXX,XX +XXX,XX @@
18
} Exynos4210Irq;
25
!define OUTFILE "qemu-setup.exe"
19
26
!endif
20
typedef struct Exynos4210State {
27
21
+ /*< private >*/
28
+; Build a unicode installer
22
+ SysBusDevice parent_obj;
29
+Unicode true
23
+ /*< public >*/
24
ARMCPU *cpu[EXYNOS4210_NCPUS];
25
Exynos4210Irq irqs;
26
qemu_irq *irq_table;
27
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210State {
28
I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
29
} Exynos4210State;
30
31
+#define TYPE_EXYNOS4210_SOC "exynos4210"
32
+#define EXYNOS4210_SOC(obj) \
33
+ OBJECT_CHECK(Exynos4210State, obj, TYPE_EXYNOS4210_SOC)
34
+
30
+
35
void exynos4210_write_secondary(ARMCPU *cpu,
31
; Use maximum compression.
36
const struct arm_boot_info *info);
32
SetCompressor /SOLID lzma
37
38
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem);
39
-
40
/* Initialize exynos4210 IRQ subsystem stub */
41
qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
42
43
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/arm/exynos4210.c
46
+++ b/hw/arm/exynos4210.c
47
@@ -XXX,XX +XXX,XX @@ static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
48
sysbus_connect_irq(busdev, 0, irq);
49
}
50
51
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
52
+static void exynos4210_realize(DeviceState *socdev, Error **errp)
53
{
54
- Exynos4210State *s = g_new0(Exynos4210State, 1);
55
+ Exynos4210State *s = EXYNOS4210_SOC(socdev);
56
+ MemoryRegion *system_mem = get_system_memory();
57
qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
58
SysBusDevice *busdev;
59
DeviceState *dev;
60
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
61
qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
62
pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
63
qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
64
-
65
- return s;
66
}
67
+
68
+static void exynos4210_class_init(ObjectClass *klass, void *data)
69
+{
70
+ DeviceClass *dc = DEVICE_CLASS(klass);
71
+
72
+ dc->realize = exynos4210_realize;
73
+}
74
+
75
+static const TypeInfo exynos4210_info = {
76
+ .name = TYPE_EXYNOS4210_SOC,
77
+ .parent = TYPE_SYS_BUS_DEVICE,
78
+ .instance_size = sizeof(Exynos4210State),
79
+ .class_init = exynos4210_class_init,
80
+};
81
+
82
+static void exynos4210_register_types(void)
83
+{
84
+ type_register_static(&exynos4210_info);
85
+}
86
+
87
+type_init(exynos4210_register_types)
88
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
89
index XXXXXXX..XXXXXXX 100644
90
--- a/hw/arm/exynos4_boards.c
91
+++ b/hw/arm/exynos4_boards.c
92
@@ -XXX,XX +XXX,XX @@ typedef enum Exynos4BoardType {
93
} Exynos4BoardType;
94
95
typedef struct Exynos4BoardState {
96
- Exynos4210State *soc;
97
+ Exynos4210State soc;
98
MemoryRegion dram0_mem;
99
MemoryRegion dram1_mem;
100
} Exynos4BoardState;
101
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
102
exynos4_boards_init_ram(s, get_system_memory(),
103
exynos4_board_ram_size[board_type]);
104
105
- s->soc = exynos4210_init(get_system_memory());
106
+ object_initialize(&s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC);
107
+ qdev_set_parent_bus(DEVICE(&s->soc), sysbus_get_default());
108
+ object_property_set_bool(OBJECT(&s->soc), true, "realized",
109
+ &error_fatal);
110
111
return s;
112
}
113
@@ -XXX,XX +XXX,XX @@ static void smdkc210_init(MachineState *machine)
114
EXYNOS4_BOARD_SMDKC210);
115
116
lan9215_init(SMDK_LAN9118_BASE_ADDR,
117
- qemu_irq_invert(s->soc->irq_table[exynos4210_get_irq(37, 1)]));
118
+ qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)]));
119
arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo);
120
}
121
33
122
--
34
--
123
2.20.1
35
2.25.1
124
36
125
37
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/12] hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
[PULL 08/21] nsis installer: Fix mouse-over descriptions for emulators
1
In ich_vmcr_write() we enforce "writes of BPR fields to less than
1
We use the nsis.py script to write out an installer script Section
2
their minimum sets them to the minimum" by doing a "read vbpr and
2
for each emulator executable, so the exact set of Sections depends on
3
write it back" operation. A typo here meant that we weren't handling
3
which executables were built. However the part of qemu.nsi which
4
writes to these fields correctly, because we were reading from VBPR0
4
specifies mouse-over descriptions for each Section still has a
5
but writing to VBPR1.
5
hard-coded and very outdated list (with just i386 and alpha). This
6
causes two problems. Firstly, if you build the installer for a
7
configuration where you didn't build the i386 binaries you get
8
warnings like this:
9
warning 6000: unknown variable/constant "{Section_i386}" detected, ignoring (macro:_==:1)
10
warning 6000: unknown variable/constant "{Section_i386w}" detected, ignoring (macro:_==:1)
11
(this happens in our gitlab CI jobs, for instance).
12
Secondly, most of the emulators in the generated installer don't have
13
any mouseover text.
14
15
Make nsis.py generate a second output file which has the necessary
16
MUI_DESCRIPTION_TEXT lines for each Section it creates, so we can
17
include that at the right point in qemu.nsi to set the mouse-over
18
text.
6
19
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
21
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20190520162809.2677-4-peter.maydell@linaro.org
22
Reviewed-by: John Snow <jsnow@redhat.com>
23
Message-id: 20220305105743.2384766-4-peter.maydell@linaro.org
10
---
24
---
11
hw/intc/arm_gicv3_cpuif.c | 2 +-
25
qemu.nsi | 5 +----
12
1 file changed, 1 insertion(+), 1 deletion(-)
26
scripts/nsis.py | 13 ++++++++++++-
27
2 files changed, 13 insertions(+), 5 deletions(-)
13
28
14
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
29
diff --git a/qemu.nsi b/qemu.nsi
15
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/arm_gicv3_cpuif.c
31
--- a/qemu.nsi
17
+++ b/hw/intc/arm_gicv3_cpuif.c
32
+++ b/qemu.nsi
18
@@ -XXX,XX +XXX,XX @@ static void ich_vmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
33
@@ -XXX,XX +XXX,XX @@ SectionEnd
19
/* Enforce "writing BPRs to less than minimum sets them to the minimum"
34
; Descriptions (mouse-over).
20
* by reading and writing back the fields.
35
!insertmacro MUI_FUNCTION_DESCRIPTION_BEGIN
21
*/
36
!insertmacro MUI_DESCRIPTION_TEXT ${SectionSystem} "System emulation."
22
- write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G0));
37
- !insertmacro MUI_DESCRIPTION_TEXT ${Section_alpha} "Alpha system emulation."
23
+ write_vbpr(cs, GICV3_G0, read_vbpr(cs, GICV3_G0));
38
- !insertmacro MUI_DESCRIPTION_TEXT ${Section_alphaw} "Alpha system emulation (GUI)."
24
write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G1));
39
- !insertmacro MUI_DESCRIPTION_TEXT ${Section_i386} "PC i386 system emulation."
25
40
- !insertmacro MUI_DESCRIPTION_TEXT ${Section_i386w} "PC i386 system emulation (GUI)."
26
gicv3_cpuif_virt_update(cs);
41
+!include "${BINDIR}\system-mui-text.nsh"
42
!insertmacro MUI_DESCRIPTION_TEXT ${SectionTools} "Tools."
43
!ifdef DLLDIR
44
!insertmacro MUI_DESCRIPTION_TEXT ${SectionDll} "Runtime Libraries (DLL)."
45
diff --git a/scripts/nsis.py b/scripts/nsis.py
46
index XXXXXXX..XXXXXXX 100644
47
--- a/scripts/nsis.py
48
+++ b/scripts/nsis.py
49
@@ -XXX,XX +XXX,XX @@ def main():
50
subprocess.run(["make", "install", "DESTDIR=" + destdir + os.path.sep])
51
with open(
52
os.path.join(destdir + args.prefix, "system-emulations.nsh"), "w"
53
- ) as nsh:
54
+ ) as nsh, open(
55
+ os.path.join(destdir + args.prefix, "system-mui-text.nsh"), "w"
56
+ ) as muinsh:
57
for exe in sorted(glob.glob(
58
os.path.join(destdir + args.prefix, "qemu-system-*.exe")
59
)):
60
@@ -XXX,XX +XXX,XX @@ def main():
61
arch, exe
62
)
63
)
64
+ if arch.endswith('w'):
65
+ desc = arch[:-1] + " emulation (GUI)."
66
+ else:
67
+ desc = arch + " emulation."
68
+
69
+ muinsh.write(
70
+ """
71
+ !insertmacro MUI_DESCRIPTION_TEXT ${{Section_{0}}} "{1}"
72
+ """.format(arch, desc))
73
74
for exe in glob.glob(os.path.join(destdir + args.prefix, "*.exe")):
75
signcode(exe)
27
--
76
--
28
2.20.1
77
2.25.1
29
78
30
79
diff view generated by jsdifflib
New patch
[PULL 09/21] hw/intc: Rename CONFIG_ARM_GIC_TCG into CONFIG_ARM_GICV3_TCG
1
From: Eric Auger <eric.auger@redhat.com>
1
2
3
CONFIG_ARM_GIC_TCG actually guards the compilation of TCG GICv3
4
specific files. So let's rename it into CONFIG_ARM_GICV3_TCG
5
6
Signed-off-by: Eric Auger <eric.auger@redhat.com>
7
Reviewed-by: Andrew Jones <drjones@redhat.com>
8
Message-id: 20220308182452.223473-2-eric.auger@redhat.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/intc/Kconfig | 2 +-
13
hw/intc/meson.build | 4 ++--
14
2 files changed, 3 insertions(+), 3 deletions(-)
15
16
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/intc/Kconfig
19
+++ b/hw/intc/Kconfig
20
@@ -XXX,XX +XXX,XX @@ config APIC
21
select MSI_NONBROKEN
22
select I8259
23
24
-config ARM_GIC_TCG
25
+config ARM_GICV3_TCG
26
bool
27
default y
28
depends on ARM_GIC && TCG
29
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/intc/meson.build
32
+++ b/hw/intc/meson.build
33
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_ARM_GIC', if_true: files(
34
'arm_gicv3_common.c',
35
'arm_gicv3_its_common.c',
36
))
37
-softmmu_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files(
38
+softmmu_ss.add(when: 'CONFIG_ARM_GICV3_TCG', if_true: files(
39
'arm_gicv3.c',
40
'arm_gicv3_dist.c',
41
'arm_gicv3_its.c',
42
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_PMU', if_true: files('xlnx-pmu-iomod-in
43
specific_ss.add(when: 'CONFIG_ALLWINNER_A10_PIC', if_true: files('allwinner-a10-pic.c'))
44
specific_ss.add(when: 'CONFIG_APIC', if_true: files('apic.c', 'apic_common.c'))
45
specific_ss.add(when: 'CONFIG_ARM_GIC', if_true: files('arm_gicv3_cpuif_common.c'))
46
-specific_ss.add(when: 'CONFIG_ARM_GIC_TCG', if_true: files('arm_gicv3_cpuif.c'))
47
+specific_ss.add(when: 'CONFIG_ARM_GICV3_TCG', if_true: files('arm_gicv3_cpuif.c'))
48
specific_ss.add(when: 'CONFIG_ARM_GIC_KVM', if_true: files('arm_gic_kvm.c'))
49
specific_ss.add(when: ['CONFIG_ARM_GIC_KVM', 'TARGET_AARCH64'], if_true: files('arm_gicv3_kvm.c', 'arm_gicv3_its_kvm.c'))
50
specific_ss.add(when: 'CONFIG_ARM_V7M', if_true: files('armv7m_nvic.c'))
51
--
52
2.25.1
diff view generated by jsdifflib
New patch
[PULL 10/21] hw/arm/virt: Fix gic-version=max when CONFIG_ARM_GICV3_TCG is unset
1
From: Eric Auger <eric.auger@redhat.com>
1
2
3
In TCG mode, if gic-version=max we always select GICv3 even if
4
CONFIG_ARM_GICV3_TCG is unset. We shall rather select GICv2.
5
This also brings the benefit of fixing qos tests errors for tests
6
using gic-version=max with CONFIG_ARM_GICV3_TCG unset.
7
8
Signed-off-by: Eric Auger <eric.auger@redhat.com>
9
Reviewed-by: Andrew Jones <drjones@redhat.com>
10
Message-id: 20220308182452.223473-3-eric.auger@redhat.com
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/arm/virt.c | 7 ++++++-
15
1 file changed, 6 insertions(+), 1 deletion(-)
16
17
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/arm/virt.c
20
+++ b/hw/arm/virt.c
21
@@ -XXX,XX +XXX,XX @@ static void finalize_gic_version(VirtMachineState *vms)
22
vms->gic_version = VIRT_GIC_VERSION_2;
23
break;
24
case VIRT_GIC_VERSION_MAX:
25
- vms->gic_version = VIRT_GIC_VERSION_3;
26
+ if (module_object_class_by_name("arm-gicv3")) {
27
+ /* CONFIG_ARM_GICV3_TCG was set */
28
+ vms->gic_version = VIRT_GIC_VERSION_3;
29
+ } else {
30
+ vms->gic_version = VIRT_GIC_VERSION_2;
31
+ }
32
break;
33
case VIRT_GIC_VERSION_HOST:
34
error_report("gic-version=host requires KVM");
35
--
36
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/12] arm: Remove unnecessary includes of hw/arm/arm.h
[PULL 11/21] target/arm: Log M-profile vector table accesses
1
The hw/arm/arm.h header now only includes declarations relating
1
Currently the CPU_LOG_INT logging misses some useful information
2
to boot.c code, so it is only needed by Arm board or SoC code.
2
about loads from the vector table. Add logging where we load vector
3
Remove some unnecessary inclusions of it from target/arm files
3
table entries. This is particularly helpful for cases where the user
4
and from hw/intc/armv7m_nvic.c.
4
has accidentally not put a vector table in their image at all, which
5
can result in confusing guest crashes at startup.
6
7
Here's an example of the new logging for a case where
8
the vector table contains garbage:
9
10
Loaded reset SP 0x0 PC 0x0 from vector table
11
Loaded reset SP 0xd008f8df PC 0xf000bf00 from vector table
12
Taking exception 3 [Prefetch Abort] on CPU 0
13
...with CFSR.IACCVIOL
14
...BusFault with BFSR.STKERR
15
...taking pending nonsecure exception 3
16
...loading from element 3 of non-secure vector table at 0xc
17
...loaded new PC 0x20000558
18
----------------
19
IN:
20
0x20000558: 08000079 stmdaeq r0, {r0, r3, r4, r5, r6}
21
22
(The double reset logging is the result of our long-standing
23
"CPUs all get reset twice" weirdness; it looks a bit ugly
24
but it'll go away if we ever fix that :-))
5
25
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
27
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
28
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20190516163857.6430-3-peter.maydell@linaro.org
29
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
30
Message-id: 20220315204306.2797684-2-peter.maydell@linaro.org
10
---
31
---
11
hw/intc/armv7m_nvic.c | 1 -
32
target/arm/cpu.c | 5 +++++
12
target/arm/arm-semi.c | 1 -
33
target/arm/m_helper.c | 5 +++++
13
target/arm/cpu.c | 1 -
34
2 files changed, 10 insertions(+)
14
target/arm/cpu64.c | 1 -
15
target/arm/kvm.c | 1 -
16
target/arm/kvm32.c | 1 -
17
target/arm/kvm64.c | 1 -
18
7 files changed, 7 deletions(-)
19
35
20
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/intc/armv7m_nvic.c
23
+++ b/hw/intc/armv7m_nvic.c
24
@@ -XXX,XX +XXX,XX @@
25
#include "cpu.h"
26
#include "hw/sysbus.h"
27
#include "qemu/timer.h"
28
-#include "hw/arm/arm.h"
29
#include "hw/intc/armv7m_nvic.h"
30
#include "target/arm/cpu.h"
31
#include "exec/exec-all.h"
32
diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/arm-semi.c
35
+++ b/target/arm/arm-semi.c
36
@@ -XXX,XX +XXX,XX @@
37
#else
38
#include "qemu-common.h"
39
#include "exec/gdbstub.h"
40
-#include "hw/arm/arm.h"
41
#include "qemu/cutils.h"
42
#endif
43
44
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
36
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
45
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/cpu.c
38
--- a/target/arm/cpu.c
47
+++ b/target/arm/cpu.c
39
+++ b/target/arm/cpu.c
48
@@ -XXX,XX +XXX,XX @@
40
@@ -XXX,XX +XXX,XX @@
49
#if !defined(CONFIG_USER_ONLY)
41
#include "qemu/osdep.h"
50
#include "hw/loader.h"
42
#include "qemu/qemu-print.h"
51
#endif
43
#include "qemu/timer.h"
52
-#include "hw/arm/arm.h"
44
+#include "qemu/log.h"
53
#include "sysemu/sysemu.h"
45
#include "qemu-common.h"
54
#include "sysemu/hw_accel.h"
46
#include "target/arm/idau.h"
55
#include "kvm_arm.h"
47
#include "qemu/module.h"
56
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
48
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
49
initial_pc = ldl_phys(s->as, vecbase + 4);
50
}
51
52
+ qemu_log_mask(CPU_LOG_INT,
53
+ "Loaded reset SP 0x%x PC 0x%x from vector table\n",
54
+ initial_msp, initial_pc);
55
+
56
env->regs[13] = initial_msp & 0xFFFFFFFC;
57
env->regs[15] = initial_pc & ~1;
58
env->thumb = initial_pc & 1;
59
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
57
index XXXXXXX..XXXXXXX 100644
60
index XXXXXXX..XXXXXXX 100644
58
--- a/target/arm/cpu64.c
61
--- a/target/arm/m_helper.c
59
+++ b/target/arm/cpu64.c
62
+++ b/target/arm/m_helper.c
60
@@ -XXX,XX +XXX,XX @@
63
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
61
#if !defined(CONFIG_USER_ONLY)
64
ARMMMUIdx mmu_idx;
62
#include "hw/loader.h"
65
bool exc_secure;
63
#endif
66
64
-#include "hw/arm/arm.h"
67
+ qemu_log_mask(CPU_LOG_INT,
65
#include "sysemu/sysemu.h"
68
+ "...loading from element %d of %s vector table at 0x%x\n",
66
#include "sysemu/kvm.h"
69
+ exc, targets_secure ? "secure" : "non-secure", addr);
67
#include "kvm_arm.h"
70
+
68
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
71
mmu_idx = arm_v7m_mmu_idx_for_secstate_and_priv(env, targets_secure, true);
69
index XXXXXXX..XXXXXXX 100644
72
70
--- a/target/arm/kvm.c
73
/*
71
+++ b/target/arm/kvm.c
74
@@ -XXX,XX +XXX,XX @@ static bool arm_v7m_load_vector(ARMCPU *cpu, int exc, bool targets_secure,
72
@@ -XXX,XX +XXX,XX @@
75
goto load_fail;
73
#include "cpu.h"
76
}
74
#include "trace.h"
77
*pvec = vector_entry;
75
#include "internals.h"
78
+ qemu_log_mask(CPU_LOG_INT, "...loaded new PC 0x%x\n", *pvec);
76
-#include "hw/arm/arm.h"
79
return true;
77
#include "hw/pci/pci.h"
80
78
#include "exec/memattrs.h"
81
load_fail:
79
#include "exec/address-spaces.h"
80
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
81
index XXXXXXX..XXXXXXX 100644
82
--- a/target/arm/kvm32.c
83
+++ b/target/arm/kvm32.c
84
@@ -XXX,XX +XXX,XX @@
85
#include "sysemu/kvm.h"
86
#include "kvm_arm.h"
87
#include "internals.h"
88
-#include "hw/arm/arm.h"
89
#include "qemu/log.h"
90
91
static inline void set_feature(uint64_t *features, int feature)
92
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
93
index XXXXXXX..XXXXXXX 100644
94
--- a/target/arm/kvm64.c
95
+++ b/target/arm/kvm64.c
96
@@ -XXX,XX +XXX,XX @@
97
#include "sysemu/kvm.h"
98
#include "kvm_arm.h"
99
#include "internals.h"
100
-#include "hw/arm/arm.h"
101
102
static bool have_guest_debug;
103
104
--
82
--
105
2.20.1
83
2.25.1
106
84
107
85
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/12] arm: Move system_clock_scale to armv7m_systick.h
[PULL 12/21] target/arm: Log fault address for M-profile faults
1
The system_clock_scale global is used only by the armv7m systick
1
For M-profile, the fault address is not always exposed to the guest
2
device; move the extern declaration to the armv7m_systick.h header,
2
in a fault register (for instance the BFAR bus fault address register
3
and expand the comment to explain what it is and that it should
3
is only updated for bus faults on data accesses, not instruction
4
ideally be replaced with a different approach.
4
accesses). Currently we log the address only if we're putting it
5
into a particular guest-visible register. Since we always have it,
6
log it generically, to make logs of i-side faults a bit clearer.
5
7
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20190516163857.6430-2-peter.maydell@linaro.org
11
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Message-id: 20220315204306.2797684-3-peter.maydell@linaro.org
10
---
13
---
11
include/hw/arm/arm.h | 4 ----
14
target/arm/m_helper.c | 6 ++++++
12
include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++++++++
15
1 file changed, 6 insertions(+)
13
2 files changed, 22 insertions(+), 4 deletions(-)
14
16
15
diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h
17
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
16
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/arm.h
19
--- a/target/arm/m_helper.c
18
+++ b/include/hw/arm/arm.h
20
+++ b/target/arm/m_helper.c
19
@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
21
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
20
const struct arm_boot_info *info,
22
* Note that for M profile we don't have a guest facing FSR, but
21
hwaddr mvbar_addr);
23
* the env->exception.fsr will be populated by the code that
22
24
* raises the fault, in the A profile short-descriptor format.
23
-/* Multiplication factor to convert from system clock ticks to qemu timer
25
+ *
24
- ticks. */
26
+ * Log the exception.vaddress now regardless of subtype, because
25
-extern int system_clock_scale;
27
+ * logging below only logs it when it goes into a guest visible
26
-
28
+ * register.
27
#endif /* HW_ARM_H */
29
*/
28
diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
30
+ qemu_log_mask(CPU_LOG_INT, "...at fault address 0x%x\n",
29
index XXXXXXX..XXXXXXX 100644
31
+ (uint32_t)env->exception.vaddress);
30
--- a/include/hw/timer/armv7m_systick.h
32
switch (env->exception.fsr & 0xf) {
31
+++ b/include/hw/timer/armv7m_systick.h
33
case M_FAKE_FSR_NSC_EXEC:
32
@@ -XXX,XX +XXX,XX @@ typedef struct SysTickState {
34
/*
33
qemu_irq irq;
34
} SysTickState;
35
36
+/*
37
+ * Multiplication factor to convert from system clock ticks to qemu timer
38
+ * ticks. This should be set (by board code, usually) to a value
39
+ * equal to NANOSECONDS_PER_SECOND / frq, where frq is the clock frequency
40
+ * in Hz of the CPU.
41
+ *
42
+ * This value is used by the systick device when it is running in
43
+ * its "use the CPU clock" mode (ie when SYST_CSR.CLKSOURCE == 1) to
44
+ * set how fast the timer should tick.
45
+ *
46
+ * TODO: we should refactor this so that rather than using a global
47
+ * we use a device property or something similar. This is complicated
48
+ * because (a) the property would need to be plumbed through from the
49
+ * board code down through various layers to the systick device
50
+ * and (b) the property needs to be modifiable after realize, because
51
+ * the stellaris board uses this to implement the behaviour where the
52
+ * guest can reprogram the PLL registers to downclock the CPU, and the
53
+ * systick device needs to react accordingly. Possibly this should
54
+ * be deferred until we have a good API for modelling clock trees.
55
+ */
56
+extern int system_clock_scale;
57
+
58
#endif
59
--
35
--
60
2.20.1
36
2.25.1
61
37
62
38
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/12] hw/arm/exynos4: Remove unuseful debug code
[PULL 13/21] hw/arm/xlnx-zynqmp: Add an unimplemented SERDES area
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
3
Add an unimplemented SERDES (Serializer/Deserializer) area.
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
4
5
Message-id: 20190520214342.13709-2-philmd@redhat.com
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
7
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8
Message-id: 20220316164645.2303510-2-edgar.iglesias@gmail.com
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
10
---
8
hw/arm/exynos4_boards.c | 24 ------------------------
11
include/hw/arm/xlnx-zynqmp.h | 2 +-
9
1 file changed, 24 deletions(-)
12
hw/arm/xlnx-zynqmp.c | 5 +++++
13
2 files changed, 6 insertions(+), 1 deletion(-)
10
14
11
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
15
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
12
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/arm/exynos4_boards.c
17
--- a/include/hw/arm/xlnx-zynqmp.h
14
+++ b/hw/arm/exynos4_boards.c
18
+++ b/include/hw/arm/xlnx-zynqmp.h
19
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
20
/*
21
* Unimplemented mmio regions needed to boot some images.
22
*/
23
-#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 1
24
+#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 2
25
26
struct XlnxZynqMPState {
27
/*< private >*/
28
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/arm/xlnx-zynqmp.c
31
+++ b/hw/arm/xlnx-zynqmp.c
15
@@ -XXX,XX +XXX,XX @@
32
@@ -XXX,XX +XXX,XX @@
16
#include "hw/net/lan9118.h"
33
#define QSPI_DMA_ADDR 0xff0f0800
17
#include "hw/boards.h"
34
#define NUM_QSPI_IRQ_LINES 2
18
35
19
-#undef DEBUG
36
+/* Serializer/Deserializer. */
20
-
37
+#define SERDES_ADDR 0xfd400000
21
-//#define DEBUG
38
+#define SERDES_SIZE 0x20000
22
-
39
+
23
-#ifdef DEBUG
40
#define DP_ADDR 0xfd4a0000
24
- #undef PRINT_DEBUG
41
#define DP_IRQ 113
25
- #define PRINT_DEBUG(fmt, args...) \
42
26
- do { \
43
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
27
- fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
44
hwaddr size;
28
- } while (0)
45
} unimp_areas[ARRAY_SIZE(s->mr_unimp)] = {
29
-#else
46
{ .name = "apu", APU_ADDR, APU_SIZE },
30
- #define PRINT_DEBUG(fmt, args...) do {} while (0)
47
+ { .name = "serdes", SERDES_ADDR, SERDES_SIZE },
31
-#endif
48
};
32
-
49
unsigned int nr;
33
#define SMDK_LAN9118_BASE_ADDR 0x05000000
34
35
typedef enum Exynos4BoardType {
36
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
37
exynos4_board_binfo.gic_cpu_if_addr =
38
EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100;
39
40
- PRINT_DEBUG("\n ram_size: %luMiB [0x%08lx]\n"
41
- " kernel_filename: %s\n"
42
- " kernel_cmdline: %s\n"
43
- " initrd_filename: %s\n",
44
- exynos4_board_ram_size[board_type] / 1048576,
45
- exynos4_board_ram_size[board_type],
46
- machine->kernel_filename,
47
- machine->kernel_cmdline,
48
- machine->initrd_filename);
49
-
50
exynos4_boards_init_ram(s, get_system_memory(),
51
exynos4_board_ram_size[board_type]);
52
50
53
--
51
--
54
2.20.1
52
2.25.1
55
53
56
54
diff view generated by jsdifflib
New patch
[PULL 14/21] target/arm: Make rvbar settable after realize
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
2
3
Make the rvbar property settable after realize. This is done
4
in preparation to model the ZynqMP's runtime configurable rvbar.
5
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Message-id: 20220316164645.2303510-3-edgar.iglesias@gmail.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/cpu.h | 3 ++-
12
target/arm/cpu.c | 12 +++++++-----
13
target/arm/helper.c | 10 +++++++---
14
3 files changed, 16 insertions(+), 9 deletions(-)
15
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
19
+++ b/target/arm/cpu.h
20
@@ -XXX,XX +XXX,XX @@ typedef struct CPUArchState {
21
uint64_t vbar_el[4];
22
};
23
uint32_t mvbar; /* (monitor) vector base address register */
24
+ uint64_t rvbar; /* rvbar sampled from rvbar property at reset */
25
struct { /* FCSE PID. */
26
uint32_t fcseidr_ns;
27
uint32_t fcseidr_s;
28
@@ -XXX,XX +XXX,XX @@ struct ArchCPU {
29
30
/* DCZ blocksize, in log_2(words), ie low 4 bits of DCZID_EL0 */
31
uint32_t dcz_blocksize;
32
- uint64_t rvbar;
33
+ uint64_t rvbar_prop; /* Property/input signals. */
34
35
/* Configurable aspects of GIC cpu interface (which is part of the CPU) */
36
int gic_num_lrs; /* number of list registers */
37
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/cpu.c
40
+++ b/target/arm/cpu.c
41
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
42
} else {
43
env->pstate = PSTATE_MODE_EL1h;
44
}
45
- env->pc = cpu->rvbar;
46
+
47
+ /* Sample rvbar at reset. */
48
+ env->cp15.rvbar = cpu->rvbar_prop;
49
+ env->pc = env->cp15.rvbar;
50
#endif
51
} else {
52
#if defined(CONFIG_USER_ONLY)
53
@@ -XXX,XX +XXX,XX @@ static Property arm_cpu_reset_cbar_property =
54
static Property arm_cpu_reset_hivecs_property =
55
DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
56
57
-static Property arm_cpu_rvbar_property =
58
- DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
59
-
60
#ifndef CONFIG_USER_ONLY
61
static Property arm_cpu_has_el2_property =
62
DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true);
63
@@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj)
64
}
65
66
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
67
- qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property);
68
+ object_property_add_uint64_ptr(obj, "rvbar",
69
+ &cpu->rvbar_prop,
70
+ OBJ_PROP_FLAG_READWRITE);
71
}
72
73
#ifndef CONFIG_USER_ONLY
74
diff --git a/target/arm/helper.c b/target/arm/helper.c
75
index XXXXXXX..XXXXXXX 100644
76
--- a/target/arm/helper.c
77
+++ b/target/arm/helper.c
78
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
79
ARMCPRegInfo rvbar = {
80
.name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
81
.opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
82
- .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
83
+ .access = PL1_R,
84
+ .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
85
};
86
define_one_arm_cp_reg(cpu, &rvbar);
87
}
88
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
89
ARMCPRegInfo rvbar = {
90
.name = "RVBAR_EL2", .state = ARM_CP_STATE_AA64,
91
.opc0 = 3, .opc1 = 4, .crn = 12, .crm = 0, .opc2 = 1,
92
- .type = ARM_CP_CONST, .access = PL2_R, .resetvalue = cpu->rvbar
93
+ .access = PL2_R,
94
+ .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
95
};
96
define_one_arm_cp_reg(cpu, &rvbar);
97
}
98
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
99
ARMCPRegInfo el3_regs[] = {
100
{ .name = "RVBAR_EL3", .state = ARM_CP_STATE_AA64,
101
.opc0 = 3, .opc1 = 6, .crn = 12, .crm = 0, .opc2 = 1,
102
- .type = ARM_CP_CONST, .access = PL3_R, .resetvalue = cpu->rvbar },
103
+ .access = PL3_R,
104
+ .fieldoffset = offsetof(CPUARMState, cp15.rvbar),
105
+ },
106
{ .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
107
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 0, .opc2 = 0,
108
.access = PL3_RW,
109
--
110
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/12] hw/arm/exynos4: Use the IEC binary prefix definitions
[PULL 15/21] hw/misc: Add a model of the Xilinx ZynqMP CRF
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
2
2
3
It eases code review, unit is explicit.
3
Add a model of the Xilinx ZynqMP CRF. At the moment this
4
is mostly a stub model.
4
5
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20190520214342.13709-3-philmd@redhat.com
8
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
9
Message-id: 20220316164645.2303510-4-edgar.iglesias@gmail.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
11
---
10
hw/arm/exynos4_boards.c | 5 +++--
12
include/hw/misc/xlnx-zynqmp-crf.h | 211 ++++++++++++++++++++++++
11
1 file changed, 3 insertions(+), 2 deletions(-)
13
hw/misc/xlnx-zynqmp-crf.c | 266 ++++++++++++++++++++++++++++++
14
hw/misc/meson.build | 1 +
15
3 files changed, 478 insertions(+)
16
create mode 100644 include/hw/misc/xlnx-zynqmp-crf.h
17
create mode 100644 hw/misc/xlnx-zynqmp-crf.c
12
18
13
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
19
diff --git a/include/hw/misc/xlnx-zynqmp-crf.h b/include/hw/misc/xlnx-zynqmp-crf.h
20
new file mode 100644
21
index XXXXXXX..XXXXXXX
22
--- /dev/null
23
+++ b/include/hw/misc/xlnx-zynqmp-crf.h
24
@@ -XXX,XX +XXX,XX @@
25
+/*
26
+ * QEMU model of the CRF - Clock Reset FPD.
27
+ *
28
+ * Copyright (c) 2022 Xilinx Inc.
29
+ * SPDX-License-Identifier: GPL-2.0-or-later
30
+ * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
31
+ */
32
+#ifndef HW_MISC_XLNX_ZYNQMP_CRF_H
33
+#define HW_MISC_XLNX_ZYNQMP_CRF_H
34
+
35
+#include "hw/sysbus.h"
36
+#include "hw/register.h"
37
+
38
+#define TYPE_XLNX_ZYNQMP_CRF "xlnx.zynqmp_crf"
39
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPCRF, XLNX_ZYNQMP_CRF)
40
+
41
+REG32(ERR_CTRL, 0x0)
42
+ FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1)
43
+REG32(IR_STATUS, 0x4)
44
+ FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1)
45
+REG32(IR_MASK, 0x8)
46
+ FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1)
47
+REG32(IR_ENABLE, 0xc)
48
+ FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1)
49
+REG32(IR_DISABLE, 0x10)
50
+ FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1)
51
+REG32(CRF_WPROT, 0x1c)
52
+ FIELD(CRF_WPROT, ACTIVE, 0, 1)
53
+REG32(APLL_CTRL, 0x20)
54
+ FIELD(APLL_CTRL, POST_SRC, 24, 3)
55
+ FIELD(APLL_CTRL, PRE_SRC, 20, 3)
56
+ FIELD(APLL_CTRL, CLKOUTDIV, 17, 1)
57
+ FIELD(APLL_CTRL, DIV2, 16, 1)
58
+ FIELD(APLL_CTRL, FBDIV, 8, 7)
59
+ FIELD(APLL_CTRL, BYPASS, 3, 1)
60
+ FIELD(APLL_CTRL, RESET, 0, 1)
61
+REG32(APLL_CFG, 0x24)
62
+ FIELD(APLL_CFG, LOCK_DLY, 25, 7)
63
+ FIELD(APLL_CFG, LOCK_CNT, 13, 10)
64
+ FIELD(APLL_CFG, LFHF, 10, 2)
65
+ FIELD(APLL_CFG, CP, 5, 4)
66
+ FIELD(APLL_CFG, RES, 0, 4)
67
+REG32(APLL_FRAC_CFG, 0x28)
68
+ FIELD(APLL_FRAC_CFG, ENABLED, 31, 1)
69
+ FIELD(APLL_FRAC_CFG, SEED, 22, 3)
70
+ FIELD(APLL_FRAC_CFG, ALGRTHM, 19, 1)
71
+ FIELD(APLL_FRAC_CFG, ORDER, 18, 1)
72
+ FIELD(APLL_FRAC_CFG, DATA, 0, 16)
73
+REG32(DPLL_CTRL, 0x2c)
74
+ FIELD(DPLL_CTRL, POST_SRC, 24, 3)
75
+ FIELD(DPLL_CTRL, PRE_SRC, 20, 3)
76
+ FIELD(DPLL_CTRL, CLKOUTDIV, 17, 1)
77
+ FIELD(DPLL_CTRL, DIV2, 16, 1)
78
+ FIELD(DPLL_CTRL, FBDIV, 8, 7)
79
+ FIELD(DPLL_CTRL, BYPASS, 3, 1)
80
+ FIELD(DPLL_CTRL, RESET, 0, 1)
81
+REG32(DPLL_CFG, 0x30)
82
+ FIELD(DPLL_CFG, LOCK_DLY, 25, 7)
83
+ FIELD(DPLL_CFG, LOCK_CNT, 13, 10)
84
+ FIELD(DPLL_CFG, LFHF, 10, 2)
85
+ FIELD(DPLL_CFG, CP, 5, 4)
86
+ FIELD(DPLL_CFG, RES, 0, 4)
87
+REG32(DPLL_FRAC_CFG, 0x34)
88
+ FIELD(DPLL_FRAC_CFG, ENABLED, 31, 1)
89
+ FIELD(DPLL_FRAC_CFG, SEED, 22, 3)
90
+ FIELD(DPLL_FRAC_CFG, ALGRTHM, 19, 1)
91
+ FIELD(DPLL_FRAC_CFG, ORDER, 18, 1)
92
+ FIELD(DPLL_FRAC_CFG, DATA, 0, 16)
93
+REG32(VPLL_CTRL, 0x38)
94
+ FIELD(VPLL_CTRL, POST_SRC, 24, 3)
95
+ FIELD(VPLL_CTRL, PRE_SRC, 20, 3)
96
+ FIELD(VPLL_CTRL, CLKOUTDIV, 17, 1)
97
+ FIELD(VPLL_CTRL, DIV2, 16, 1)
98
+ FIELD(VPLL_CTRL, FBDIV, 8, 7)
99
+ FIELD(VPLL_CTRL, BYPASS, 3, 1)
100
+ FIELD(VPLL_CTRL, RESET, 0, 1)
101
+REG32(VPLL_CFG, 0x3c)
102
+ FIELD(VPLL_CFG, LOCK_DLY, 25, 7)
103
+ FIELD(VPLL_CFG, LOCK_CNT, 13, 10)
104
+ FIELD(VPLL_CFG, LFHF, 10, 2)
105
+ FIELD(VPLL_CFG, CP, 5, 4)
106
+ FIELD(VPLL_CFG, RES, 0, 4)
107
+REG32(VPLL_FRAC_CFG, 0x40)
108
+ FIELD(VPLL_FRAC_CFG, ENABLED, 31, 1)
109
+ FIELD(VPLL_FRAC_CFG, SEED, 22, 3)
110
+ FIELD(VPLL_FRAC_CFG, ALGRTHM, 19, 1)
111
+ FIELD(VPLL_FRAC_CFG, ORDER, 18, 1)
112
+ FIELD(VPLL_FRAC_CFG, DATA, 0, 16)
113
+REG32(PLL_STATUS, 0x44)
114
+ FIELD(PLL_STATUS, VPLL_STABLE, 5, 1)
115
+ FIELD(PLL_STATUS, DPLL_STABLE, 4, 1)
116
+ FIELD(PLL_STATUS, APLL_STABLE, 3, 1)
117
+ FIELD(PLL_STATUS, VPLL_LOCK, 2, 1)
118
+ FIELD(PLL_STATUS, DPLL_LOCK, 1, 1)
119
+ FIELD(PLL_STATUS, APLL_LOCK, 0, 1)
120
+REG32(APLL_TO_LPD_CTRL, 0x48)
121
+ FIELD(APLL_TO_LPD_CTRL, DIVISOR0, 8, 6)
122
+REG32(DPLL_TO_LPD_CTRL, 0x4c)
123
+ FIELD(DPLL_TO_LPD_CTRL, DIVISOR0, 8, 6)
124
+REG32(VPLL_TO_LPD_CTRL, 0x50)
125
+ FIELD(VPLL_TO_LPD_CTRL, DIVISOR0, 8, 6)
126
+REG32(ACPU_CTRL, 0x60)
127
+ FIELD(ACPU_CTRL, CLKACT_HALF, 25, 1)
128
+ FIELD(ACPU_CTRL, CLKACT_FULL, 24, 1)
129
+ FIELD(ACPU_CTRL, DIVISOR0, 8, 6)
130
+ FIELD(ACPU_CTRL, SRCSEL, 0, 3)
131
+REG32(DBG_TRACE_CTRL, 0x64)
132
+ FIELD(DBG_TRACE_CTRL, CLKACT, 24, 1)
133
+ FIELD(DBG_TRACE_CTRL, DIVISOR0, 8, 6)
134
+ FIELD(DBG_TRACE_CTRL, SRCSEL, 0, 3)
135
+REG32(DBG_FPD_CTRL, 0x68)
136
+ FIELD(DBG_FPD_CTRL, CLKACT, 24, 1)
137
+ FIELD(DBG_FPD_CTRL, DIVISOR0, 8, 6)
138
+ FIELD(DBG_FPD_CTRL, SRCSEL, 0, 3)
139
+REG32(DP_VIDEO_REF_CTRL, 0x70)
140
+ FIELD(DP_VIDEO_REF_CTRL, CLKACT, 24, 1)
141
+ FIELD(DP_VIDEO_REF_CTRL, DIVISOR1, 16, 6)
142
+ FIELD(DP_VIDEO_REF_CTRL, DIVISOR0, 8, 6)
143
+ FIELD(DP_VIDEO_REF_CTRL, SRCSEL, 0, 3)
144
+REG32(DP_AUDIO_REF_CTRL, 0x74)
145
+ FIELD(DP_AUDIO_REF_CTRL, CLKACT, 24, 1)
146
+ FIELD(DP_AUDIO_REF_CTRL, DIVISOR1, 16, 6)
147
+ FIELD(DP_AUDIO_REF_CTRL, DIVISOR0, 8, 6)
148
+ FIELD(DP_AUDIO_REF_CTRL, SRCSEL, 0, 3)
149
+REG32(DP_STC_REF_CTRL, 0x7c)
150
+ FIELD(DP_STC_REF_CTRL, CLKACT, 24, 1)
151
+ FIELD(DP_STC_REF_CTRL, DIVISOR1, 16, 6)
152
+ FIELD(DP_STC_REF_CTRL, DIVISOR0, 8, 6)
153
+ FIELD(DP_STC_REF_CTRL, SRCSEL, 0, 3)
154
+REG32(DDR_CTRL, 0x80)
155
+ FIELD(DDR_CTRL, CLKACT, 24, 1)
156
+ FIELD(DDR_CTRL, DIVISOR0, 8, 6)
157
+ FIELD(DDR_CTRL, SRCSEL, 0, 3)
158
+REG32(GPU_REF_CTRL, 0x84)
159
+ FIELD(GPU_REF_CTRL, PP1_CLKACT, 26, 1)
160
+ FIELD(GPU_REF_CTRL, PP0_CLKACT, 25, 1)
161
+ FIELD(GPU_REF_CTRL, CLKACT, 24, 1)
162
+ FIELD(GPU_REF_CTRL, DIVISOR0, 8, 6)
163
+ FIELD(GPU_REF_CTRL, SRCSEL, 0, 3)
164
+REG32(SATA_REF_CTRL, 0xa0)
165
+ FIELD(SATA_REF_CTRL, CLKACT, 24, 1)
166
+ FIELD(SATA_REF_CTRL, DIVISOR0, 8, 6)
167
+ FIELD(SATA_REF_CTRL, SRCSEL, 0, 3)
168
+REG32(PCIE_REF_CTRL, 0xb4)
169
+ FIELD(PCIE_REF_CTRL, CLKACT, 24, 1)
170
+ FIELD(PCIE_REF_CTRL, DIVISOR0, 8, 6)
171
+ FIELD(PCIE_REF_CTRL, SRCSEL, 0, 3)
172
+REG32(GDMA_REF_CTRL, 0xb8)
173
+ FIELD(GDMA_REF_CTRL, CLKACT, 24, 1)
174
+ FIELD(GDMA_REF_CTRL, DIVISOR0, 8, 6)
175
+ FIELD(GDMA_REF_CTRL, SRCSEL, 0, 3)
176
+REG32(DPDMA_REF_CTRL, 0xbc)
177
+ FIELD(DPDMA_REF_CTRL, CLKACT, 24, 1)
178
+ FIELD(DPDMA_REF_CTRL, DIVISOR0, 8, 6)
179
+ FIELD(DPDMA_REF_CTRL, SRCSEL, 0, 3)
180
+REG32(TOPSW_MAIN_CTRL, 0xc0)
181
+ FIELD(TOPSW_MAIN_CTRL, CLKACT, 24, 1)
182
+ FIELD(TOPSW_MAIN_CTRL, DIVISOR0, 8, 6)
183
+ FIELD(TOPSW_MAIN_CTRL, SRCSEL, 0, 3)
184
+REG32(TOPSW_LSBUS_CTRL, 0xc4)
185
+ FIELD(TOPSW_LSBUS_CTRL, CLKACT, 24, 1)
186
+ FIELD(TOPSW_LSBUS_CTRL, DIVISOR0, 8, 6)
187
+ FIELD(TOPSW_LSBUS_CTRL, SRCSEL, 0, 3)
188
+REG32(DBG_TSTMP_CTRL, 0xf8)
189
+ FIELD(DBG_TSTMP_CTRL, DIVISOR0, 8, 6)
190
+ FIELD(DBG_TSTMP_CTRL, SRCSEL, 0, 3)
191
+REG32(RST_FPD_TOP, 0x100)
192
+ FIELD(RST_FPD_TOP, PCIE_CFG_RESET, 19, 1)
193
+ FIELD(RST_FPD_TOP, PCIE_BRIDGE_RESET, 18, 1)
194
+ FIELD(RST_FPD_TOP, PCIE_CTRL_RESET, 17, 1)
195
+ FIELD(RST_FPD_TOP, DP_RESET, 16, 1)
196
+ FIELD(RST_FPD_TOP, SWDT_RESET, 15, 1)
197
+ FIELD(RST_FPD_TOP, AFI_FM5_RESET, 12, 1)
198
+ FIELD(RST_FPD_TOP, AFI_FM4_RESET, 11, 1)
199
+ FIELD(RST_FPD_TOP, AFI_FM3_RESET, 10, 1)
200
+ FIELD(RST_FPD_TOP, AFI_FM2_RESET, 9, 1)
201
+ FIELD(RST_FPD_TOP, AFI_FM1_RESET, 8, 1)
202
+ FIELD(RST_FPD_TOP, AFI_FM0_RESET, 7, 1)
203
+ FIELD(RST_FPD_TOP, GDMA_RESET, 6, 1)
204
+ FIELD(RST_FPD_TOP, GPU_PP1_RESET, 5, 1)
205
+ FIELD(RST_FPD_TOP, GPU_PP0_RESET, 4, 1)
206
+ FIELD(RST_FPD_TOP, GPU_RESET, 3, 1)
207
+ FIELD(RST_FPD_TOP, GT_RESET, 2, 1)
208
+ FIELD(RST_FPD_TOP, SATA_RESET, 1, 1)
209
+REG32(RST_FPD_APU, 0x104)
210
+ FIELD(RST_FPD_APU, ACPU3_PWRON_RESET, 13, 1)
211
+ FIELD(RST_FPD_APU, ACPU2_PWRON_RESET, 12, 1)
212
+ FIELD(RST_FPD_APU, ACPU1_PWRON_RESET, 11, 1)
213
+ FIELD(RST_FPD_APU, ACPU0_PWRON_RESET, 10, 1)
214
+ FIELD(RST_FPD_APU, APU_L2_RESET, 8, 1)
215
+ FIELD(RST_FPD_APU, ACPU3_RESET, 3, 1)
216
+ FIELD(RST_FPD_APU, ACPU2_RESET, 2, 1)
217
+ FIELD(RST_FPD_APU, ACPU1_RESET, 1, 1)
218
+ FIELD(RST_FPD_APU, ACPU0_RESET, 0, 1)
219
+REG32(RST_DDR_SS, 0x108)
220
+ FIELD(RST_DDR_SS, DDR_RESET, 3, 1)
221
+ FIELD(RST_DDR_SS, APM_RESET, 2, 1)
222
+
223
+#define CRF_R_MAX (R_RST_DDR_SS + 1)
224
+
225
+struct XlnxZynqMPCRF {
226
+ SysBusDevice parent_obj;
227
+ MemoryRegion iomem;
228
+ qemu_irq irq_ir;
229
+
230
+ RegisterInfoArray *reg_array;
231
+ uint32_t regs[CRF_R_MAX];
232
+ RegisterInfo regs_info[CRF_R_MAX];
233
+};
234
+
235
+#endif
236
diff --git a/hw/misc/xlnx-zynqmp-crf.c b/hw/misc/xlnx-zynqmp-crf.c
237
new file mode 100644
238
index XXXXXXX..XXXXXXX
239
--- /dev/null
240
+++ b/hw/misc/xlnx-zynqmp-crf.c
241
@@ -XXX,XX +XXX,XX @@
242
+/*
243
+ * QEMU model of the CRF - Clock Reset FPD.
244
+ *
245
+ * Copyright (c) 2022 Xilinx Inc.
246
+ * SPDX-License-Identifier: GPL-2.0-or-later
247
+ * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>
248
+ */
249
+
250
+#include "qemu/osdep.h"
251
+#include "hw/sysbus.h"
252
+#include "hw/register.h"
253
+#include "qemu/bitops.h"
254
+#include "qemu/log.h"
255
+#include "migration/vmstate.h"
256
+#include "hw/irq.h"
257
+#include "hw/misc/xlnx-zynqmp-crf.h"
258
+#include "target/arm/arm-powerctl.h"
259
+
260
+#ifndef XLNX_ZYNQMP_CRF_ERR_DEBUG
261
+#define XLNX_ZYNQMP_CRF_ERR_DEBUG 0
262
+#endif
263
+
264
+#define CRF_MAX_CPU 4
265
+
266
+static void ir_update_irq(XlnxZynqMPCRF *s)
267
+{
268
+ bool pending = s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK];
269
+ qemu_set_irq(s->irq_ir, pending);
270
+}
271
+
272
+static void ir_status_postw(RegisterInfo *reg, uint64_t val64)
273
+{
274
+ XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque);
275
+ ir_update_irq(s);
276
+}
277
+
278
+static uint64_t ir_enable_prew(RegisterInfo *reg, uint64_t val64)
279
+{
280
+ XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque);
281
+ uint32_t val = val64;
282
+
283
+ s->regs[R_IR_MASK] &= ~val;
284
+ ir_update_irq(s);
285
+ return 0;
286
+}
287
+
288
+static uint64_t ir_disable_prew(RegisterInfo *reg, uint64_t val64)
289
+{
290
+ XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque);
291
+ uint32_t val = val64;
292
+
293
+ s->regs[R_IR_MASK] |= val;
294
+ ir_update_irq(s);
295
+ return 0;
296
+}
297
+
298
+static uint64_t rst_fpd_apu_prew(RegisterInfo *reg, uint64_t val64)
299
+{
300
+ XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(reg->opaque);
301
+ uint32_t val = val64;
302
+ uint32_t val_old = s->regs[R_RST_FPD_APU];
303
+ unsigned int i;
304
+
305
+ for (i = 0; i < CRF_MAX_CPU; i++) {
306
+ uint32_t mask = (1 << (R_RST_FPD_APU_ACPU0_RESET_SHIFT + i));
307
+
308
+ if ((val ^ val_old) & mask) {
309
+ if (val & mask) {
310
+ arm_set_cpu_off(i);
311
+ } else {
312
+ arm_set_cpu_on_and_reset(i);
313
+ }
314
+ }
315
+ }
316
+ return val64;
317
+}
318
+
319
+static const RegisterAccessInfo crf_regs_info[] = {
320
+ { .name = "ERR_CTRL", .addr = A_ERR_CTRL,
321
+ },{ .name = "IR_STATUS", .addr = A_IR_STATUS,
322
+ .w1c = 0x1,
323
+ .post_write = ir_status_postw,
324
+ },{ .name = "IR_MASK", .addr = A_IR_MASK,
325
+ .reset = 0x1,
326
+ .ro = 0x1,
327
+ },{ .name = "IR_ENABLE", .addr = A_IR_ENABLE,
328
+ .pre_write = ir_enable_prew,
329
+ },{ .name = "IR_DISABLE", .addr = A_IR_DISABLE,
330
+ .pre_write = ir_disable_prew,
331
+ },{ .name = "CRF_WPROT", .addr = A_CRF_WPROT,
332
+ },{ .name = "APLL_CTRL", .addr = A_APLL_CTRL,
333
+ .reset = 0x12c09,
334
+ .rsvd = 0xf88c80f6,
335
+ },{ .name = "APLL_CFG", .addr = A_APLL_CFG,
336
+ .rsvd = 0x1801210,
337
+ },{ .name = "APLL_FRAC_CFG", .addr = A_APLL_FRAC_CFG,
338
+ .rsvd = 0x7e330000,
339
+ },{ .name = "DPLL_CTRL", .addr = A_DPLL_CTRL,
340
+ .reset = 0x2c09,
341
+ .rsvd = 0xf88c80f6,
342
+ },{ .name = "DPLL_CFG", .addr = A_DPLL_CFG,
343
+ .rsvd = 0x1801210,
344
+ },{ .name = "DPLL_FRAC_CFG", .addr = A_DPLL_FRAC_CFG,
345
+ .rsvd = 0x7e330000,
346
+ },{ .name = "VPLL_CTRL", .addr = A_VPLL_CTRL,
347
+ .reset = 0x12809,
348
+ .rsvd = 0xf88c80f6,
349
+ },{ .name = "VPLL_CFG", .addr = A_VPLL_CFG,
350
+ .rsvd = 0x1801210,
351
+ },{ .name = "VPLL_FRAC_CFG", .addr = A_VPLL_FRAC_CFG,
352
+ .rsvd = 0x7e330000,
353
+ },{ .name = "PLL_STATUS", .addr = A_PLL_STATUS,
354
+ .reset = 0x3f,
355
+ .rsvd = 0xc0,
356
+ .ro = 0x3f,
357
+ },{ .name = "APLL_TO_LPD_CTRL", .addr = A_APLL_TO_LPD_CTRL,
358
+ .reset = 0x400,
359
+ .rsvd = 0xc0ff,
360
+ },{ .name = "DPLL_TO_LPD_CTRL", .addr = A_DPLL_TO_LPD_CTRL,
361
+ .reset = 0x400,
362
+ .rsvd = 0xc0ff,
363
+ },{ .name = "VPLL_TO_LPD_CTRL", .addr = A_VPLL_TO_LPD_CTRL,
364
+ .reset = 0x400,
365
+ .rsvd = 0xc0ff,
366
+ },{ .name = "ACPU_CTRL", .addr = A_ACPU_CTRL,
367
+ .reset = 0x3000400,
368
+ .rsvd = 0xfcffc0f8,
369
+ },{ .name = "DBG_TRACE_CTRL", .addr = A_DBG_TRACE_CTRL,
370
+ .reset = 0x2500,
371
+ .rsvd = 0xfeffc0f8,
372
+ },{ .name = "DBG_FPD_CTRL", .addr = A_DBG_FPD_CTRL,
373
+ .reset = 0x1002500,
374
+ .rsvd = 0xfeffc0f8,
375
+ },{ .name = "DP_VIDEO_REF_CTRL", .addr = A_DP_VIDEO_REF_CTRL,
376
+ .reset = 0x1002300,
377
+ .rsvd = 0xfec0c0f8,
378
+ },{ .name = "DP_AUDIO_REF_CTRL", .addr = A_DP_AUDIO_REF_CTRL,
379
+ .reset = 0x1032300,
380
+ .rsvd = 0xfec0c0f8,
381
+ },{ .name = "DP_STC_REF_CTRL", .addr = A_DP_STC_REF_CTRL,
382
+ .reset = 0x1203200,
383
+ .rsvd = 0xfec0c0f8,
384
+ },{ .name = "DDR_CTRL", .addr = A_DDR_CTRL,
385
+ .reset = 0x1000500,
386
+ .rsvd = 0xfeffc0f8,
387
+ },{ .name = "GPU_REF_CTRL", .addr = A_GPU_REF_CTRL,
388
+ .reset = 0x1500,
389
+ .rsvd = 0xf8ffc0f8,
390
+ },{ .name = "SATA_REF_CTRL", .addr = A_SATA_REF_CTRL,
391
+ .reset = 0x1001600,
392
+ .rsvd = 0xfeffc0f8,
393
+ },{ .name = "PCIE_REF_CTRL", .addr = A_PCIE_REF_CTRL,
394
+ .reset = 0x1500,
395
+ .rsvd = 0xfeffc0f8,
396
+ },{ .name = "GDMA_REF_CTRL", .addr = A_GDMA_REF_CTRL,
397
+ .reset = 0x1000500,
398
+ .rsvd = 0xfeffc0f8,
399
+ },{ .name = "DPDMA_REF_CTRL", .addr = A_DPDMA_REF_CTRL,
400
+ .reset = 0x1000500,
401
+ .rsvd = 0xfeffc0f8,
402
+ },{ .name = "TOPSW_MAIN_CTRL", .addr = A_TOPSW_MAIN_CTRL,
403
+ .reset = 0x1000400,
404
+ .rsvd = 0xfeffc0f8,
405
+ },{ .name = "TOPSW_LSBUS_CTRL", .addr = A_TOPSW_LSBUS_CTRL,
406
+ .reset = 0x1000800,
407
+ .rsvd = 0xfeffc0f8,
408
+ },{ .name = "DBG_TSTMP_CTRL", .addr = A_DBG_TSTMP_CTRL,
409
+ .reset = 0xa00,
410
+ .rsvd = 0xffffc0f8,
411
+ },
412
+ { .name = "RST_FPD_TOP", .addr = A_RST_FPD_TOP,
413
+ .reset = 0xf9ffe,
414
+ .rsvd = 0xf06001,
415
+ },{ .name = "RST_FPD_APU", .addr = A_RST_FPD_APU,
416
+ .reset = 0x3d0f,
417
+ .rsvd = 0xc2f0,
418
+ .pre_write = rst_fpd_apu_prew,
419
+ },{ .name = "RST_DDR_SS", .addr = A_RST_DDR_SS,
420
+ .reset = 0xf,
421
+ .rsvd = 0xf3,
422
+ }
423
+};
424
+
425
+static void crf_reset_enter(Object *obj, ResetType type)
426
+{
427
+ XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj);
428
+ unsigned int i;
429
+
430
+ for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
431
+ register_reset(&s->regs_info[i]);
432
+ }
433
+}
434
+
435
+static void crf_reset_hold(Object *obj)
436
+{
437
+ XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj);
438
+ ir_update_irq(s);
439
+}
440
+
441
+static const MemoryRegionOps crf_ops = {
442
+ .read = register_read_memory,
443
+ .write = register_write_memory,
444
+ .endianness = DEVICE_LITTLE_ENDIAN,
445
+ .valid = {
446
+ .min_access_size = 4,
447
+ .max_access_size = 4,
448
+ },
449
+};
450
+
451
+static void crf_init(Object *obj)
452
+{
453
+ XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj);
454
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
455
+
456
+ s->reg_array =
457
+ register_init_block32(DEVICE(obj), crf_regs_info,
458
+ ARRAY_SIZE(crf_regs_info),
459
+ s->regs_info, s->regs,
460
+ &crf_ops,
461
+ XLNX_ZYNQMP_CRF_ERR_DEBUG,
462
+ CRF_R_MAX * 4);
463
+ sysbus_init_mmio(sbd, &s->reg_array->mem);
464
+ sysbus_init_irq(sbd, &s->irq_ir);
465
+}
466
+
467
+static void crf_finalize(Object *obj)
468
+{
469
+ XlnxZynqMPCRF *s = XLNX_ZYNQMP_CRF(obj);
470
+ register_finalize_block(s->reg_array);
471
+}
472
+
473
+static const VMStateDescription vmstate_crf = {
474
+ .name = TYPE_XLNX_ZYNQMP_CRF,
475
+ .version_id = 1,
476
+ .minimum_version_id = 1,
477
+ .fields = (VMStateField[]) {
478
+ VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPCRF, CRF_R_MAX),
479
+ VMSTATE_END_OF_LIST(),
480
+ }
481
+};
482
+
483
+static void crf_class_init(ObjectClass *klass, void *data)
484
+{
485
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
486
+ DeviceClass *dc = DEVICE_CLASS(klass);
487
+
488
+ dc->vmsd = &vmstate_crf;
489
+ rc->phases.enter = crf_reset_enter;
490
+ rc->phases.hold = crf_reset_hold;
491
+}
492
+
493
+static const TypeInfo crf_info = {
494
+ .name = TYPE_XLNX_ZYNQMP_CRF,
495
+ .parent = TYPE_SYS_BUS_DEVICE,
496
+ .instance_size = sizeof(XlnxZynqMPCRF),
497
+ .class_init = crf_class_init,
498
+ .instance_init = crf_init,
499
+ .instance_finalize = crf_finalize,
500
+};
501
+
502
+static void crf_register_types(void)
503
+{
504
+ type_register_static(&crf_info);
505
+}
506
+
507
+type_init(crf_register_types)
508
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
14
index XXXXXXX..XXXXXXX 100644
509
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/exynos4_boards.c
510
--- a/hw/misc/meson.build
16
+++ b/hw/arm/exynos4_boards.c
511
+++ b/hw/misc/meson.build
17
@@ -XXX,XX +XXX,XX @@
512
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
18
*/
513
))
19
514
softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
20
#include "qemu/osdep.h"
515
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c'))
21
+#include "qemu/units.h"
516
+specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
22
#include "qapi/error.h"
517
softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
23
#include "qemu/error-report.h"
518
'xlnx-versal-xramc.c',
24
#include "qemu-common.h"
519
'xlnx-versal-pmc-iou-slcr.c',
25
@@ -XXX,XX +XXX,XX @@ static int exynos4_board_smp_bootreg_addr[EXYNOS4_NUM_OF_BOARDS] = {
26
};
27
28
static unsigned long exynos4_board_ram_size[EXYNOS4_NUM_OF_BOARDS] = {
29
- [EXYNOS4_BOARD_NURI] = 0x40000000,
30
- [EXYNOS4_BOARD_SMDKC210] = 0x40000000,
31
+ [EXYNOS4_BOARD_NURI] = 1 * GiB,
32
+ [EXYNOS4_BOARD_SMDKC210] = 1 * GiB,
33
};
34
35
static struct arm_boot_info exynos4_board_binfo = {
36
--
520
--
37
2.20.1
521
2.25.1
38
522
39
523
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/12] hw/arm/exynos4210: Add DMA support for the Exynos4210
[PULL 16/21] hw/arm/xlnx-zynqmp: Connect the ZynqMP CRF
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
2
2
3
QEMU already supports pl330. Instantiate it for Exynos4210.
3
Connect the ZynqMP CRF - Clock Reset FPD device.
4
4
5
Relevant part of Linux arch/arm/boot/dts/exynos4.dtsi:
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
6
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
7
/ {
7
Reviewed-by: Luc Michel <luc@lmichel.fr>
8
soc: soc {
8
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
9
amba {
9
Message-id: 20220316164645.2303510-5-edgar.iglesias@gmail.com
10
pdma0: pdma@12680000 {
11
compatible = "arm,pl330", "arm,primecell";
12
reg = <0x12680000 0x1000>;
13
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
14
clocks = <&clock CLK_PDMA0>;
15
clock-names = "apb_pclk";
16
#dma-cells = <1>;
17
#dma-channels = <8>;
18
#dma-requests = <32>;
19
};
20
pdma1: pdma@12690000 {
21
compatible = "arm,pl330", "arm,primecell";
22
reg = <0x12690000 0x1000>;
23
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
24
clocks = <&clock CLK_PDMA1>;
25
clock-names = "apb_pclk";
26
#dma-cells = <1>;
27
#dma-channels = <8>;
28
#dma-requests = <32>;
29
};
30
mdma1: mdma@12850000 {
31
compatible = "arm,pl330", "arm,primecell";
32
reg = <0x12850000 0x1000>;
33
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
34
clocks = <&clock CLK_MDMA>;
35
clock-names = "apb_pclk";
36
#dma-cells = <1>;
37
#dma-channels = <8>;
38
#dma-requests = <1>;
39
};
40
};
41
};
42
};
43
44
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
45
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
46
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
47
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
48
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
49
Message-id: 20190520214342.13709-4-philmd@redhat.com
50
[PMD: Do not set default qdev properties, create the controllers in the SoC
51
rather than the board (Peter Maydell), add dtsi in commit message]
52
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
53
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
54
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
55
---
11
---
56
hw/arm/exynos4210.c | 26 ++++++++++++++++++++++++++
12
include/hw/arm/xlnx-zynqmp.h | 2 ++
57
1 file changed, 26 insertions(+)
13
hw/arm/xlnx-zynqmp.c | 16 ++++++++++++++++
14
2 files changed, 18 insertions(+)
58
15
59
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
16
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
60
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
61
--- a/hw/arm/exynos4210.c
18
--- a/include/hw/arm/xlnx-zynqmp.h
62
+++ b/hw/arm/exynos4210.c
19
+++ b/include/hw/arm/xlnx-zynqmp.h
63
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@
64
/* EHCI */
21
#include "hw/nvram/xlnx-bbram.h"
65
#define EXYNOS4210_EHCI_BASE_ADDR 0x12580000
22
#include "hw/nvram/xlnx-zynqmp-efuse.h"
66
23
#include "hw/or-irq.h"
67
+/* DMA */
24
+#include "hw/misc/xlnx-zynqmp-crf.h"
68
+#define EXYNOS4210_PL330_BASE0_ADDR 0x12680000
25
69
+#define EXYNOS4210_PL330_BASE1_ADDR 0x12690000
26
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
70
+#define EXYNOS4210_PL330_BASE2_ADDR 0x12850000
27
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
28
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
29
XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH];
30
XlnxCSUDMA qspi_dma;
31
qemu_or_irq qspi_irq_orgate;
32
+ XlnxZynqMPCRF crf;
33
34
char *boot_cpu;
35
ARMCPU *boot_cpu_ptr;
36
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/hw/arm/xlnx-zynqmp.c
39
+++ b/hw/arm/xlnx-zynqmp.c
40
@@ -XXX,XX +XXX,XX @@
41
#define QSPI_DMA_ADDR 0xff0f0800
42
#define NUM_QSPI_IRQ_LINES 2
43
44
+#define CRF_ADDR 0xfd1a0000
45
+#define CRF_IRQ 120
71
+
46
+
72
static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
47
/* Serializer/Deserializer. */
73
0x09, 0x00, 0x00, 0x00 };
48
#define SERDES_ADDR 0xfd400000
74
49
#define SERDES_SIZE 0x20000
75
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu)
50
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic)
76
return (0x9 << ARM_AFF1_SHIFT) | cpu;
51
sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]);
77
}
52
}
78
53
79
+static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
54
+static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic)
80
+{
55
+{
81
+ SysBusDevice *busdev;
56
+ SysBusDevice *sbd;
82
+ DeviceState *dev;
83
+
57
+
84
+ dev = qdev_create(NULL, "pl330");
58
+ object_initialize_child(OBJECT(s), "crf", &s->crf, TYPE_XLNX_ZYNQMP_CRF);
85
+ qdev_prop_set_uint8(dev, "num_periph_req", nreq);
59
+ sbd = SYS_BUS_DEVICE(&s->crf);
86
+ qdev_init_nofail(dev);
60
+
87
+ busdev = SYS_BUS_DEVICE(dev);
61
+ sysbus_realize(sbd, &error_fatal);
88
+ sysbus_mmio_map(busdev, 0, base);
62
+ sysbus_mmio_map(sbd, 0, CRF_ADDR);
89
+ sysbus_connect_irq(busdev, 0, irq);
63
+ sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]);
90
+}
64
+}
91
+
65
+
92
Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
66
static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
93
{
67
{
94
Exynos4210State *s = g_new0(Exynos4210State, 1);
68
static const struct UnimpInfo {
95
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
69
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
96
sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
70
97
s->irq_table[exynos4210_get_irq(28, 3)]);
71
xlnx_zynqmp_create_bbram(s, gic_spi);
98
72
xlnx_zynqmp_create_efuse(s, gic_spi);
99
+ /*** DMA controllers ***/
73
+ xlnx_zynqmp_create_crf(s, gic_spi);
100
+ pl330_create(EXYNOS4210_PL330_BASE0_ADDR,
74
xlnx_zynqmp_create_unimp_mmio(s);
101
+ qemu_irq_invert(s->irq_table[exynos4210_get_irq(35, 1)]), 32);
75
102
+ pl330_create(EXYNOS4210_PL330_BASE1_ADDR,
76
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
103
+ qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
104
+ pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
105
+ qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
106
+
107
return s;
108
}
109
--
77
--
110
2.20.1
78
2.25.1
111
79
112
80
diff view generated by jsdifflib
New patch
[PULL 17/21] hw/misc: Add a model of the Xilinx ZynqMP APU Control
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
2
3
Add a model of the Xilinx ZynqMP APU Control.
4
5
Reviewed-by: Luc Michel <luc@lmichel.fr>
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Message-id: 20220316164645.2303510-6-edgar.iglesias@gmail.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
include/hw/misc/xlnx-zynqmp-apu-ctrl.h | 93 +++++++++
11
hw/misc/xlnx-zynqmp-apu-ctrl.c | 253 +++++++++++++++++++++++++
12
hw/misc/meson.build | 1 +
13
3 files changed, 347 insertions(+)
14
create mode 100644 include/hw/misc/xlnx-zynqmp-apu-ctrl.h
15
create mode 100644 hw/misc/xlnx-zynqmp-apu-ctrl.c
16
17
diff --git a/include/hw/misc/xlnx-zynqmp-apu-ctrl.h b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
18
new file mode 100644
19
index XXXXXXX..XXXXXXX
20
--- /dev/null
21
+++ b/include/hw/misc/xlnx-zynqmp-apu-ctrl.h
22
@@ -XXX,XX +XXX,XX @@
23
+/*
24
+ * QEMU model of ZynqMP APU Control.
25
+ *
26
+ * Copyright (c) 2013-2022 Xilinx Inc
27
+ * SPDX-License-Identifier: GPL-2.0-or-later
28
+ *
29
+ * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> and
30
+ * Edgar E. Iglesias <edgar.iglesias@xilinx.com>
31
+ *
32
+ */
33
+#ifndef HW_MISC_XLNX_ZYNQMP_APU_CTRL_H
34
+#define HW_MISC_XLNX_ZYNQMP_APU_CTRL_H
35
+
36
+#include "hw/sysbus.h"
37
+#include "hw/register.h"
38
+#include "target/arm/cpu.h"
39
+
40
+#define TYPE_XLNX_ZYNQMP_APU_CTRL "xlnx.apu-ctrl"
41
+OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPAPUCtrl, XLNX_ZYNQMP_APU_CTRL)
42
+
43
+REG32(APU_ERR_CTRL, 0x0)
44
+ FIELD(APU_ERR_CTRL, PSLVERR, 0, 1)
45
+REG32(ISR, 0x10)
46
+ FIELD(ISR, INV_APB, 0, 1)
47
+REG32(IMR, 0x14)
48
+ FIELD(IMR, INV_APB, 0, 1)
49
+REG32(IEN, 0x18)
50
+ FIELD(IEN, INV_APB, 0, 1)
51
+REG32(IDS, 0x1c)
52
+ FIELD(IDS, INV_APB, 0, 1)
53
+REG32(CONFIG_0, 0x20)
54
+ FIELD(CONFIG_0, CFGTE, 24, 4)
55
+ FIELD(CONFIG_0, CFGEND, 16, 4)
56
+ FIELD(CONFIG_0, VINITHI, 8, 4)
57
+ FIELD(CONFIG_0, AA64NAA32, 0, 4)
58
+REG32(CONFIG_1, 0x24)
59
+ FIELD(CONFIG_1, L2RSTDISABLE, 29, 1)
60
+ FIELD(CONFIG_1, L1RSTDISABLE, 28, 1)
61
+ FIELD(CONFIG_1, CP15DISABLE, 0, 4)
62
+REG32(RVBARADDR0L, 0x40)
63
+ FIELD(RVBARADDR0L, ADDR, 2, 30)
64
+REG32(RVBARADDR0H, 0x44)
65
+ FIELD(RVBARADDR0H, ADDR, 0, 8)
66
+REG32(RVBARADDR1L, 0x48)
67
+ FIELD(RVBARADDR1L, ADDR, 2, 30)
68
+REG32(RVBARADDR1H, 0x4c)
69
+ FIELD(RVBARADDR1H, ADDR, 0, 8)
70
+REG32(RVBARADDR2L, 0x50)
71
+ FIELD(RVBARADDR2L, ADDR, 2, 30)
72
+REG32(RVBARADDR2H, 0x54)
73
+ FIELD(RVBARADDR2H, ADDR, 0, 8)
74
+REG32(RVBARADDR3L, 0x58)
75
+ FIELD(RVBARADDR3L, ADDR, 2, 30)
76
+REG32(RVBARADDR3H, 0x5c)
77
+ FIELD(RVBARADDR3H, ADDR, 0, 8)
78
+REG32(ACE_CTRL, 0x60)
79
+ FIELD(ACE_CTRL, AWQOS, 16, 4)
80
+ FIELD(ACE_CTRL, ARQOS, 0, 4)
81
+REG32(SNOOP_CTRL, 0x80)
82
+ FIELD(SNOOP_CTRL, ACE_INACT, 4, 1)
83
+ FIELD(SNOOP_CTRL, ACP_INACT, 0, 1)
84
+REG32(PWRCTL, 0x90)
85
+ FIELD(PWRCTL, CLREXMONREQ, 17, 1)
86
+ FIELD(PWRCTL, L2FLUSHREQ, 16, 1)
87
+ FIELD(PWRCTL, CPUPWRDWNREQ, 0, 4)
88
+REG32(PWRSTAT, 0x94)
89
+ FIELD(PWRSTAT, CLREXMONACK, 17, 1)
90
+ FIELD(PWRSTAT, L2FLUSHDONE, 16, 1)
91
+ FIELD(PWRSTAT, DBGNOPWRDWN, 0, 4)
92
+
93
+#define APU_R_MAX ((R_PWRSTAT) + 1)
94
+
95
+#define APU_MAX_CPU 4
96
+
97
+struct XlnxZynqMPAPUCtrl {
98
+ SysBusDevice busdev;
99
+
100
+ ARMCPU *cpus[APU_MAX_CPU];
101
+ /* WFIs towards PMU. */
102
+ qemu_irq wfi_out[4];
103
+ /* CPU Power status towards INTC Redirect. */
104
+ qemu_irq cpu_power_status[4];
105
+ qemu_irq irq_imr;
106
+
107
+ uint8_t cpu_pwrdwn_req;
108
+ uint8_t cpu_in_wfi;
109
+
110
+ RegisterInfoArray *reg_array;
111
+ uint32_t regs[APU_R_MAX];
112
+ RegisterInfo regs_info[APU_R_MAX];
113
+};
114
+
115
+#endif
116
diff --git a/hw/misc/xlnx-zynqmp-apu-ctrl.c b/hw/misc/xlnx-zynqmp-apu-ctrl.c
117
new file mode 100644
118
index XXXXXXX..XXXXXXX
119
--- /dev/null
120
+++ b/hw/misc/xlnx-zynqmp-apu-ctrl.c
121
@@ -XXX,XX +XXX,XX @@
122
+/*
123
+ * QEMU model of the ZynqMP APU Control.
124
+ *
125
+ * Copyright (c) 2013-2022 Xilinx Inc
126
+ * SPDX-License-Identifier: GPL-2.0-or-later
127
+ *
128
+ * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> and
129
+ * Edgar E. Iglesias <edgar.iglesias@xilinx.com>
130
+ */
131
+
132
+#include "qemu/osdep.h"
133
+#include "qapi/error.h"
134
+#include "qemu/log.h"
135
+#include "migration/vmstate.h"
136
+#include "hw/qdev-properties.h"
137
+#include "hw/sysbus.h"
138
+#include "hw/irq.h"
139
+#include "hw/register.h"
140
+
141
+#include "qemu/bitops.h"
142
+#include "qapi/qmp/qerror.h"
143
+
144
+#include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
145
+
146
+#ifndef XILINX_ZYNQMP_APU_ERR_DEBUG
147
+#define XILINX_ZYNQMP_APU_ERR_DEBUG 0
148
+#endif
149
+
150
+static void update_wfi_out(void *opaque)
151
+{
152
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(opaque);
153
+ unsigned int i, wfi_pending;
154
+
155
+ wfi_pending = s->cpu_pwrdwn_req & s->cpu_in_wfi;
156
+ for (i = 0; i < APU_MAX_CPU; i++) {
157
+ qemu_set_irq(s->wfi_out[i], !!(wfi_pending & (1 << i)));
158
+ }
159
+}
160
+
161
+static void zynqmp_apu_rvbar_post_write(RegisterInfo *reg, uint64_t val)
162
+{
163
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
164
+ int i;
165
+
166
+ for (i = 0; i < APU_MAX_CPU; ++i) {
167
+ uint64_t rvbar = s->regs[R_RVBARADDR0L + 2 * i] +
168
+ ((uint64_t)s->regs[R_RVBARADDR0H + 2 * i] << 32);
169
+ if (s->cpus[i]) {
170
+ object_property_set_int(OBJECT(s->cpus[i]), "rvbar", rvbar,
171
+ &error_abort);
172
+ }
173
+ }
174
+}
175
+
176
+static void zynqmp_apu_pwrctl_post_write(RegisterInfo *reg, uint64_t val)
177
+{
178
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
179
+ unsigned int i, new;
180
+
181
+ for (i = 0; i < APU_MAX_CPU; i++) {
182
+ new = val & (1 << i);
183
+ /* Check if CPU's CPUPWRDNREQ has changed. If yes, update GPIOs. */
184
+ if (new != (s->cpu_pwrdwn_req & (1 << i))) {
185
+ qemu_set_irq(s->cpu_power_status[i], !!new);
186
+ }
187
+ s->cpu_pwrdwn_req &= ~(1 << i);
188
+ s->cpu_pwrdwn_req |= new;
189
+ }
190
+ update_wfi_out(s);
191
+}
192
+
193
+static void imr_update_irq(XlnxZynqMPAPUCtrl *s)
194
+{
195
+ bool pending = s->regs[R_ISR] & ~s->regs[R_IMR];
196
+ qemu_set_irq(s->irq_imr, pending);
197
+}
198
+
199
+static void isr_postw(RegisterInfo *reg, uint64_t val64)
200
+{
201
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
202
+ imr_update_irq(s);
203
+}
204
+
205
+static uint64_t ien_prew(RegisterInfo *reg, uint64_t val64)
206
+{
207
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
208
+ uint32_t val = val64;
209
+
210
+ s->regs[R_IMR] &= ~val;
211
+ imr_update_irq(s);
212
+ return 0;
213
+}
214
+
215
+static uint64_t ids_prew(RegisterInfo *reg, uint64_t val64)
216
+{
217
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(reg->opaque);
218
+ uint32_t val = val64;
219
+
220
+ s->regs[R_IMR] |= val;
221
+ imr_update_irq(s);
222
+ return 0;
223
+}
224
+
225
+static const RegisterAccessInfo zynqmp_apu_regs_info[] = {
226
+#define RVBAR_REGDEF(n) \
227
+ { .name = "RVBAR CPU " #n " Low", .addr = A_RVBARADDR ## n ## L, \
228
+ .reset = 0xffff0000ul, \
229
+ .post_write = zynqmp_apu_rvbar_post_write, \
230
+ },{ .name = "RVBAR CPU " #n " High", .addr = A_RVBARADDR ## n ## H, \
231
+ .post_write = zynqmp_apu_rvbar_post_write, \
232
+ }
233
+ { .name = "ERR_CTRL", .addr = A_APU_ERR_CTRL,
234
+ },{ .name = "ISR", .addr = A_ISR,
235
+ .w1c = 0x1,
236
+ .post_write = isr_postw,
237
+ },{ .name = "IMR", .addr = A_IMR,
238
+ .reset = 0x1,
239
+ .ro = 0x1,
240
+ },{ .name = "IEN", .addr = A_IEN,
241
+ .pre_write = ien_prew,
242
+ },{ .name = "IDS", .addr = A_IDS,
243
+ .pre_write = ids_prew,
244
+ },{ .name = "CONFIG_0", .addr = A_CONFIG_0,
245
+ .reset = 0xf0f,
246
+ },{ .name = "CONFIG_1", .addr = A_CONFIG_1,
247
+ },
248
+ RVBAR_REGDEF(0),
249
+ RVBAR_REGDEF(1),
250
+ RVBAR_REGDEF(2),
251
+ RVBAR_REGDEF(3),
252
+ { .name = "ACE_CTRL", .addr = A_ACE_CTRL,
253
+ .reset = 0xf000f,
254
+ },{ .name = "SNOOP_CTRL", .addr = A_SNOOP_CTRL,
255
+ },{ .name = "PWRCTL", .addr = A_PWRCTL,
256
+ .post_write = zynqmp_apu_pwrctl_post_write,
257
+ },{ .name = "PWRSTAT", .addr = A_PWRSTAT,
258
+ .ro = 0x3000f,
259
+ }
260
+};
261
+
262
+static void zynqmp_apu_reset_enter(Object *obj, ResetType type)
263
+{
264
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj);
265
+ int i;
266
+
267
+ for (i = 0; i < APU_R_MAX; ++i) {
268
+ register_reset(&s->regs_info[i]);
269
+ }
270
+
271
+ s->cpu_pwrdwn_req = 0;
272
+ s->cpu_in_wfi = 0;
273
+}
274
+
275
+static void zynqmp_apu_reset_hold(Object *obj)
276
+{
277
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj);
278
+
279
+ update_wfi_out(s);
280
+ imr_update_irq(s);
281
+}
282
+
283
+static const MemoryRegionOps zynqmp_apu_ops = {
284
+ .read = register_read_memory,
285
+ .write = register_write_memory,
286
+ .endianness = DEVICE_LITTLE_ENDIAN,
287
+ .valid = {
288
+ .min_access_size = 4,
289
+ .max_access_size = 4,
290
+ }
291
+};
292
+
293
+static void zynqmp_apu_handle_wfi(void *opaque, int irq, int level)
294
+{
295
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(opaque);
296
+
297
+ s->cpu_in_wfi = deposit32(s->cpu_in_wfi, irq, 1, level);
298
+ update_wfi_out(s);
299
+}
300
+
301
+static void zynqmp_apu_init(Object *obj)
302
+{
303
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj);
304
+ int i;
305
+
306
+ s->reg_array =
307
+ register_init_block32(DEVICE(obj), zynqmp_apu_regs_info,
308
+ ARRAY_SIZE(zynqmp_apu_regs_info),
309
+ s->regs_info, s->regs,
310
+ &zynqmp_apu_ops,
311
+ XILINX_ZYNQMP_APU_ERR_DEBUG,
312
+ APU_R_MAX * 4);
313
+ sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->reg_array->mem);
314
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq_imr);
315
+
316
+ for (i = 0; i < APU_MAX_CPU; ++i) {
317
+ g_autofree gchar *prop_name = g_strdup_printf("cpu%d", i);
318
+ object_property_add_link(obj, prop_name, TYPE_ARM_CPU,
319
+ (Object **)&s->cpus[i],
320
+ qdev_prop_allow_set_link_before_realize,
321
+ OBJ_PROP_LINK_STRONG);
322
+ }
323
+
324
+ /* wfi_out is used to connect to PMU GPIs. */
325
+ qdev_init_gpio_out_named(DEVICE(obj), s->wfi_out, "wfi_out", 4);
326
+ /* CPU_POWER_STATUS is used to connect to INTC redirect. */
327
+ qdev_init_gpio_out_named(DEVICE(obj), s->cpu_power_status,
328
+ "CPU_POWER_STATUS", 4);
329
+ /* wfi_in is used as input from CPUs as wfi request. */
330
+ qdev_init_gpio_in_named(DEVICE(obj), zynqmp_apu_handle_wfi, "wfi_in", 4);
331
+}
332
+
333
+static void zynqmp_apu_finalize(Object *obj)
334
+{
335
+ XlnxZynqMPAPUCtrl *s = XLNX_ZYNQMP_APU_CTRL(obj);
336
+ register_finalize_block(s->reg_array);
337
+}
338
+
339
+static const VMStateDescription vmstate_zynqmp_apu = {
340
+ .name = TYPE_XLNX_ZYNQMP_APU_CTRL,
341
+ .version_id = 1,
342
+ .minimum_version_id = 1,
343
+ .fields = (VMStateField[]) {
344
+ VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPAPUCtrl, APU_R_MAX),
345
+ VMSTATE_END_OF_LIST(),
346
+ }
347
+};
348
+
349
+static void zynqmp_apu_class_init(ObjectClass *klass, void *data)
350
+{
351
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
352
+ DeviceClass *dc = DEVICE_CLASS(klass);
353
+
354
+ dc->vmsd = &vmstate_zynqmp_apu;
355
+
356
+ rc->phases.enter = zynqmp_apu_reset_enter;
357
+ rc->phases.hold = zynqmp_apu_reset_hold;
358
+}
359
+
360
+static const TypeInfo zynqmp_apu_info = {
361
+ .name = TYPE_XLNX_ZYNQMP_APU_CTRL,
362
+ .parent = TYPE_SYS_BUS_DEVICE,
363
+ .instance_size = sizeof(XlnxZynqMPAPUCtrl),
364
+ .class_init = zynqmp_apu_class_init,
365
+ .instance_init = zynqmp_apu_init,
366
+ .instance_finalize = zynqmp_apu_finalize,
367
+};
368
+
369
+static void zynqmp_apu_register_types(void)
370
+{
371
+ type_register_static(&zynqmp_apu_info);
372
+}
373
+
374
+type_init(zynqmp_apu_register_types)
375
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
376
index XXXXXXX..XXXXXXX 100644
377
--- a/hw/misc/meson.build
378
+++ b/hw/misc/meson.build
379
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files(
380
softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('slavio_misc.c'))
381
softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c'))
382
specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-crf.c'))
383
+specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqmp-apu-ctrl.c'))
384
softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files(
385
'xlnx-versal-xramc.c',
386
'xlnx-versal-pmc-iou-slcr.c',
387
--
388
2.25.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/12] arm: Rename hw/arm/arm.h to hw/arm/boot.h
[PULL 18/21] hw/arm/xlnx-zynqmp: Connect the ZynqMP APU Control
1
The header file hw/arm/arm.h now includes only declarations
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
2
relating to hw/arm/boot.c functionality. Rename it accordingly,
3
and adjust its header comment.
4
2
5
The bulk of this commit was created via
3
Connect the ZynqMP APU Control device.
6
perl -pi -e 's|hw/arm/arm.h|hw/arm/boot.h|' hw/arm/*.c include/hw/arm/*.h
7
4
8
In a few cases we can just delete the #include:
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
hw/arm/msf2-soc.c, include/hw/arm/aspeed_soc.h and
6
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
10
include/hw/arm/bcm2836.h did not require it.
7
Reviewed-by: Luc Michel <luc@lmichel.fr>
8
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
9
Message-id: 20220316164645.2303510-7-edgar.iglesias@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/arm/xlnx-zynqmp.h | 4 +++-
13
hw/arm/xlnx-zynqmp.c | 25 +++++++++++++++++++++++--
14
2 files changed, 26 insertions(+), 3 deletions(-)
11
15
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Message-id: 20190516163857.6430-4-peter.maydell@linaro.org
16
---
17
include/hw/arm/allwinner-a10.h | 2 +-
18
include/hw/arm/aspeed_soc.h | 1 -
19
include/hw/arm/bcm2836.h | 1 -
20
include/hw/arm/{arm.h => boot.h} | 8 ++++----
21
include/hw/arm/fsl-imx25.h | 2 +-
22
include/hw/arm/fsl-imx31.h | 2 +-
23
include/hw/arm/fsl-imx6.h | 2 +-
24
include/hw/arm/fsl-imx6ul.h | 2 +-
25
include/hw/arm/fsl-imx7.h | 2 +-
26
include/hw/arm/virt.h | 2 +-
27
include/hw/arm/xlnx-versal.h | 2 +-
28
include/hw/arm/xlnx-zynqmp.h | 2 +-
29
hw/arm/armsse.c | 2 +-
30
hw/arm/armv7m.c | 2 +-
31
hw/arm/aspeed.c | 2 +-
32
hw/arm/boot.c | 2 +-
33
hw/arm/collie.c | 2 +-
34
hw/arm/exynos4210.c | 2 +-
35
hw/arm/exynos4_boards.c | 2 +-
36
hw/arm/highbank.c | 2 +-
37
hw/arm/integratorcp.c | 2 +-
38
hw/arm/mainstone.c | 2 +-
39
hw/arm/microbit.c | 2 +-
40
hw/arm/mps2-tz.c | 2 +-
41
hw/arm/mps2.c | 2 +-
42
hw/arm/msf2-soc.c | 1 -
43
hw/arm/msf2-som.c | 2 +-
44
hw/arm/musca.c | 2 +-
45
hw/arm/musicpal.c | 2 +-
46
hw/arm/netduino2.c | 2 +-
47
hw/arm/nrf51_soc.c | 2 +-
48
hw/arm/nseries.c | 2 +-
49
hw/arm/omap1.c | 2 +-
50
hw/arm/omap2.c | 2 +-
51
hw/arm/omap_sx1.c | 2 +-
52
hw/arm/palm.c | 2 +-
53
hw/arm/raspi.c | 2 +-
54
hw/arm/realview.c | 2 +-
55
hw/arm/spitz.c | 2 +-
56
hw/arm/stellaris.c | 2 +-
57
hw/arm/stm32f205_soc.c | 2 +-
58
hw/arm/strongarm.c | 2 +-
59
hw/arm/tosa.c | 2 +-
60
hw/arm/versatilepb.c | 2 +-
61
hw/arm/vexpress.c | 2 +-
62
hw/arm/virt.c | 2 +-
63
hw/arm/xilinx_zynq.c | 2 +-
64
hw/arm/xlnx-versal.c | 2 +-
65
hw/arm/z2.c | 2 +-
66
49 files changed, 49 insertions(+), 52 deletions(-)
67
rename include/hw/arm/{arm.h => boot.h} (98%)
68
69
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
70
index XXXXXXX..XXXXXXX 100644
71
--- a/include/hw/arm/allwinner-a10.h
72
+++ b/include/hw/arm/allwinner-a10.h
73
@@ -XXX,XX +XXX,XX @@
74
#include "qemu-common.h"
75
#include "qemu/error-report.h"
76
#include "hw/char/serial.h"
77
-#include "hw/arm/arm.h"
78
+#include "hw/arm/boot.h"
79
#include "hw/timer/allwinner-a10-pit.h"
80
#include "hw/intc/allwinner-a10-pic.h"
81
#include "hw/net/allwinner_emac.h"
82
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
83
index XXXXXXX..XXXXXXX 100644
84
--- a/include/hw/arm/aspeed_soc.h
85
+++ b/include/hw/arm/aspeed_soc.h
86
@@ -XXX,XX +XXX,XX @@
87
#ifndef ASPEED_SOC_H
88
#define ASPEED_SOC_H
89
90
-#include "hw/arm/arm.h"
91
#include "hw/intc/aspeed_vic.h"
92
#include "hw/misc/aspeed_scu.h"
93
#include "hw/misc/aspeed_sdmc.h"
94
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
95
index XXXXXXX..XXXXXXX 100644
96
--- a/include/hw/arm/bcm2836.h
97
+++ b/include/hw/arm/bcm2836.h
98
@@ -XXX,XX +XXX,XX @@
99
#ifndef BCM2836_H
100
#define BCM2836_H
101
102
-#include "hw/arm/arm.h"
103
#include "hw/arm/bcm2835_peripherals.h"
104
#include "hw/intc/bcm2836_control.h"
105
106
diff --git a/include/hw/arm/arm.h b/include/hw/arm/boot.h
107
similarity index 98%
108
rename from include/hw/arm/arm.h
109
rename to include/hw/arm/boot.h
110
index XXXXXXX..XXXXXXX 100644
111
--- a/include/hw/arm/arm.h
112
+++ b/include/hw/arm/boot.h
113
@@ -XXX,XX +XXX,XX @@
114
/*
115
- * Misc ARM declarations
116
+ * ARM kernel loader.
117
*
118
* Copyright (c) 2006 CodeSourcery.
119
* Written by Paul Brook
120
@@ -XXX,XX +XXX,XX @@
121
*
122
*/
123
124
-#ifndef HW_ARM_H
125
-#define HW_ARM_H
126
+#ifndef HW_ARM_BOOT_H
127
+#define HW_ARM_BOOT_H
128
129
#include "exec/memory.h"
130
#include "target/arm/cpu-qom.h"
131
@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
132
const struct arm_boot_info *info,
133
hwaddr mvbar_addr);
134
135
-#endif /* HW_ARM_H */
136
+#endif /* HW_ARM_BOOT_H */
137
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
138
index XXXXXXX..XXXXXXX 100644
139
--- a/include/hw/arm/fsl-imx25.h
140
+++ b/include/hw/arm/fsl-imx25.h
141
@@ -XXX,XX +XXX,XX @@
142
#ifndef FSL_IMX25_H
143
#define FSL_IMX25_H
144
145
-#include "hw/arm/arm.h"
146
+#include "hw/arm/boot.h"
147
#include "hw/intc/imx_avic.h"
148
#include "hw/misc/imx25_ccm.h"
149
#include "hw/char/imx_serial.h"
150
diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h
151
index XXXXXXX..XXXXXXX 100644
152
--- a/include/hw/arm/fsl-imx31.h
153
+++ b/include/hw/arm/fsl-imx31.h
154
@@ -XXX,XX +XXX,XX @@
155
#ifndef FSL_IMX31_H
156
#define FSL_IMX31_H
157
158
-#include "hw/arm/arm.h"
159
+#include "hw/arm/boot.h"
160
#include "hw/intc/imx_avic.h"
161
#include "hw/misc/imx31_ccm.h"
162
#include "hw/char/imx_serial.h"
163
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
164
index XXXXXXX..XXXXXXX 100644
165
--- a/include/hw/arm/fsl-imx6.h
166
+++ b/include/hw/arm/fsl-imx6.h
167
@@ -XXX,XX +XXX,XX @@
168
#ifndef FSL_IMX6_H
169
#define FSL_IMX6_H
170
171
-#include "hw/arm/arm.h"
172
+#include "hw/arm/boot.h"
173
#include "hw/cpu/a9mpcore.h"
174
#include "hw/misc/imx6_ccm.h"
175
#include "hw/misc/imx6_src.h"
176
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
177
index XXXXXXX..XXXXXXX 100644
178
--- a/include/hw/arm/fsl-imx6ul.h
179
+++ b/include/hw/arm/fsl-imx6ul.h
180
@@ -XXX,XX +XXX,XX @@
181
#ifndef FSL_IMX6UL_H
182
#define FSL_IMX6UL_H
183
184
-#include "hw/arm/arm.h"
185
+#include "hw/arm/boot.h"
186
#include "hw/cpu/a15mpcore.h"
187
#include "hw/misc/imx6ul_ccm.h"
188
#include "hw/misc/imx6_src.h"
189
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
190
index XXXXXXX..XXXXXXX 100644
191
--- a/include/hw/arm/fsl-imx7.h
192
+++ b/include/hw/arm/fsl-imx7.h
193
@@ -XXX,XX +XXX,XX @@
194
#ifndef FSL_IMX7_H
195
#define FSL_IMX7_H
196
197
-#include "hw/arm/arm.h"
198
+#include "hw/arm/boot.h"
199
#include "hw/cpu/a15mpcore.h"
200
#include "hw/intc/imx_gpcv2.h"
201
#include "hw/misc/imx7_ccm.h"
202
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
203
index XXXXXXX..XXXXXXX 100644
204
--- a/include/hw/arm/virt.h
205
+++ b/include/hw/arm/virt.h
206
@@ -XXX,XX +XXX,XX @@
207
#include "exec/hwaddr.h"
208
#include "qemu/notify.h"
209
#include "hw/boards.h"
210
-#include "hw/arm/arm.h"
211
+#include "hw/arm/boot.h"
212
#include "hw/block/flash.h"
213
#include "sysemu/kvm.h"
214
#include "hw/intc/arm_gicv3_common.h"
215
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
216
index XXXXXXX..XXXXXXX 100644
217
--- a/include/hw/arm/xlnx-versal.h
218
+++ b/include/hw/arm/xlnx-versal.h
219
@@ -XXX,XX +XXX,XX @@
220
#define XLNX_VERSAL_H
221
222
#include "hw/sysbus.h"
223
-#include "hw/arm/arm.h"
224
+#include "hw/arm/boot.h"
225
#include "hw/intc/arm_gicv3.h"
226
227
#define TYPE_XLNX_VERSAL "xlnx-versal"
228
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
16
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
229
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
230
--- a/include/hw/arm/xlnx-zynqmp.h
18
--- a/include/hw/arm/xlnx-zynqmp.h
231
+++ b/include/hw/arm/xlnx-zynqmp.h
19
+++ b/include/hw/arm/xlnx-zynqmp.h
232
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@
233
#ifndef XLNX_ZYNQMP_H
21
#include "hw/nvram/xlnx-bbram.h"
234
22
#include "hw/nvram/xlnx-zynqmp-efuse.h"
235
#include "qemu-common.h"
23
#include "hw/or-irq.h"
236
-#include "hw/arm/arm.h"
24
+#include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
237
+#include "hw/arm/boot.h"
25
#include "hw/misc/xlnx-zynqmp-crf.h"
238
#include "hw/intc/arm_gic.h"
26
239
#include "hw/net/cadence_gem.h"
27
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
240
#include "hw/char/cadence_uart.h"
28
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
241
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
29
/*
30
* Unimplemented mmio regions needed to boot some images.
31
*/
32
-#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 2
33
+#define XLNX_ZYNQMP_NUM_UNIMP_AREAS 1
34
35
struct XlnxZynqMPState {
36
/*< private >*/
37
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
38
XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH];
39
XlnxCSUDMA qspi_dma;
40
qemu_or_irq qspi_irq_orgate;
41
+ XlnxZynqMPAPUCtrl apu_ctrl;
42
XlnxZynqMPCRF crf;
43
44
char *boot_cpu;
45
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
242
index XXXXXXX..XXXXXXX 100644
46
index XXXXXXX..XXXXXXX 100644
243
--- a/hw/arm/armsse.c
47
--- a/hw/arm/xlnx-zynqmp.c
244
+++ b/hw/arm/armsse.c
48
+++ b/hw/arm/xlnx-zynqmp.c
245
@@ -XXX,XX +XXX,XX @@
49
@@ -XXX,XX +XXX,XX @@
246
#include "hw/sysbus.h"
50
#define DPDMA_IRQ 116
247
#include "hw/registerfields.h"
51
248
#include "hw/arm/armsse.h"
52
#define APU_ADDR 0xfd5c0000
249
-#include "hw/arm/arm.h"
53
-#define APU_SIZE 0x100
250
+#include "hw/arm/boot.h"
54
+#define APU_IRQ 153
251
55
252
/* Format of the System Information block SYS_CONFIG register */
56
#define IPI_ADDR 0xFF300000
253
typedef enum SysConfigFormat {
57
#define IPI_IRQ 64
254
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
58
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_efuse(XlnxZynqMPState *s, qemu_irq *gic)
255
index XXXXXXX..XXXXXXX 100644
59
sysbus_connect_irq(sbd, 0, gic[EFUSE_IRQ]);
256
--- a/hw/arm/armv7m.c
60
}
257
+++ b/hw/arm/armv7m.c
61
258
@@ -XXX,XX +XXX,XX @@
62
+static void xlnx_zynqmp_create_apu_ctrl(XlnxZynqMPState *s, qemu_irq *gic)
259
#include "qemu-common.h"
63
+{
260
#include "cpu.h"
64
+ SysBusDevice *sbd;
261
#include "hw/sysbus.h"
65
+ int i;
262
-#include "hw/arm/arm.h"
66
+
263
+#include "hw/arm/boot.h"
67
+ object_initialize_child(OBJECT(s), "apu-ctrl", &s->apu_ctrl,
264
#include "hw/loader.h"
68
+ TYPE_XLNX_ZYNQMP_APU_CTRL);
265
#include "elf.h"
69
+ sbd = SYS_BUS_DEVICE(&s->apu_ctrl);
266
#include "sysemu/qtest.h"
70
+
267
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
71
+ for (i = 0; i < XLNX_ZYNQMP_NUM_APU_CPUS; i++) {
268
index XXXXXXX..XXXXXXX 100644
72
+ g_autofree gchar *name = g_strdup_printf("cpu%d", i);
269
--- a/hw/arm/aspeed.c
73
+
270
+++ b/hw/arm/aspeed.c
74
+ object_property_set_link(OBJECT(&s->apu_ctrl), name,
271
@@ -XXX,XX +XXX,XX @@
75
+ OBJECT(&s->apu_cpu[i]), &error_abort);
272
#include "qemu-common.h"
76
+ }
273
#include "cpu.h"
77
+
274
#include "exec/address-spaces.h"
78
+ sysbus_realize(sbd, &error_fatal);
275
-#include "hw/arm/arm.h"
79
+ sysbus_mmio_map(sbd, 0, APU_ADDR);
276
+#include "hw/arm/boot.h"
80
+ sysbus_connect_irq(sbd, 0, gic[APU_IRQ]);
277
#include "hw/arm/aspeed.h"
81
+}
278
#include "hw/arm/aspeed_soc.h"
82
+
279
#include "hw/boards.h"
83
static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic)
280
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
281
index XXXXXXX..XXXXXXX 100644
282
--- a/hw/arm/boot.c
283
+++ b/hw/arm/boot.c
284
@@ -XXX,XX +XXX,XX @@
285
#include "qapi/error.h"
286
#include <libfdt.h>
287
#include "hw/hw.h"
288
-#include "hw/arm/arm.h"
289
+#include "hw/arm/boot.h"
290
#include "hw/arm/linux-boot-if.h"
291
#include "sysemu/kvm.h"
292
#include "sysemu/sysemu.h"
293
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
294
index XXXXXXX..XXXXXXX 100644
295
--- a/hw/arm/collie.c
296
+++ b/hw/arm/collie.c
297
@@ -XXX,XX +XXX,XX @@
298
#include "hw/sysbus.h"
299
#include "hw/boards.h"
300
#include "strongarm.h"
301
-#include "hw/arm/arm.h"
302
+#include "hw/arm/boot.h"
303
#include "hw/block/flash.h"
304
#include "exec/address-spaces.h"
305
#include "cpu.h"
306
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
307
index XXXXXXX..XXXXXXX 100644
308
--- a/hw/arm/exynos4210.c
309
+++ b/hw/arm/exynos4210.c
310
@@ -XXX,XX +XXX,XX @@
311
#include "hw/boards.h"
312
#include "sysemu/sysemu.h"
313
#include "hw/sysbus.h"
314
-#include "hw/arm/arm.h"
315
+#include "hw/arm/boot.h"
316
#include "hw/loader.h"
317
#include "hw/arm/exynos4210.h"
318
#include "hw/sd/sdhci.h"
319
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
320
index XXXXXXX..XXXXXXX 100644
321
--- a/hw/arm/exynos4_boards.c
322
+++ b/hw/arm/exynos4_boards.c
323
@@ -XXX,XX +XXX,XX @@
324
#include "sysemu/sysemu.h"
325
#include "hw/sysbus.h"
326
#include "net/net.h"
327
-#include "hw/arm/arm.h"
328
+#include "hw/arm/boot.h"
329
#include "exec/address-spaces.h"
330
#include "hw/arm/exynos4210.h"
331
#include "hw/net/lan9118.h"
332
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
333
index XXXXXXX..XXXXXXX 100644
334
--- a/hw/arm/highbank.c
335
+++ b/hw/arm/highbank.c
336
@@ -XXX,XX +XXX,XX @@
337
#include "qemu/osdep.h"
338
#include "qapi/error.h"
339
#include "hw/sysbus.h"
340
-#include "hw/arm/arm.h"
341
+#include "hw/arm/boot.h"
342
#include "hw/loader.h"
343
#include "net/net.h"
344
#include "sysemu/kvm.h"
345
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
346
index XXXXXXX..XXXXXXX 100644
347
--- a/hw/arm/integratorcp.c
348
+++ b/hw/arm/integratorcp.c
349
@@ -XXX,XX +XXX,XX @@
350
#include "cpu.h"
351
#include "hw/sysbus.h"
352
#include "hw/boards.h"
353
-#include "hw/arm/arm.h"
354
+#include "hw/arm/boot.h"
355
#include "hw/misc/arm_integrator_debug.h"
356
#include "hw/net/smc91c111.h"
357
#include "net/net.h"
358
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
359
index XXXXXXX..XXXXXXX 100644
360
--- a/hw/arm/mainstone.c
361
+++ b/hw/arm/mainstone.c
362
@@ -XXX,XX +XXX,XX @@
363
#include "qapi/error.h"
364
#include "hw/hw.h"
365
#include "hw/arm/pxa.h"
366
-#include "hw/arm/arm.h"
367
+#include "hw/arm/boot.h"
368
#include "net/net.h"
369
#include "hw/net/smc91c111.h"
370
#include "hw/boards.h"
371
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
372
index XXXXXXX..XXXXXXX 100644
373
--- a/hw/arm/microbit.c
374
+++ b/hw/arm/microbit.c
375
@@ -XXX,XX +XXX,XX @@
376
#include "qemu/osdep.h"
377
#include "qapi/error.h"
378
#include "hw/boards.h"
379
-#include "hw/arm/arm.h"
380
+#include "hw/arm/boot.h"
381
#include "sysemu/sysemu.h"
382
#include "exec/address-spaces.h"
383
384
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
385
index XXXXXXX..XXXXXXX 100644
386
--- a/hw/arm/mps2-tz.c
387
+++ b/hw/arm/mps2-tz.c
388
@@ -XXX,XX +XXX,XX @@
389
#include "qemu/osdep.h"
390
#include "qapi/error.h"
391
#include "qemu/error-report.h"
392
-#include "hw/arm/arm.h"
393
+#include "hw/arm/boot.h"
394
#include "hw/arm/armv7m.h"
395
#include "hw/or-irq.h"
396
#include "hw/boards.h"
397
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
398
index XXXXXXX..XXXXXXX 100644
399
--- a/hw/arm/mps2.c
400
+++ b/hw/arm/mps2.c
401
@@ -XXX,XX +XXX,XX @@
402
#include "qemu/osdep.h"
403
#include "qapi/error.h"
404
#include "qemu/error-report.h"
405
-#include "hw/arm/arm.h"
406
+#include "hw/arm/boot.h"
407
#include "hw/arm/armv7m.h"
408
#include "hw/or-irq.h"
409
#include "hw/boards.h"
410
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
411
index XXXXXXX..XXXXXXX 100644
412
--- a/hw/arm/msf2-soc.c
413
+++ b/hw/arm/msf2-soc.c
414
@@ -XXX,XX +XXX,XX @@
415
#include "qemu/units.h"
416
#include "qapi/error.h"
417
#include "qemu-common.h"
418
-#include "hw/arm/arm.h"
419
#include "exec/address-spaces.h"
420
#include "hw/char/serial.h"
421
#include "hw/boards.h"
422
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
423
index XXXXXXX..XXXXXXX 100644
424
--- a/hw/arm/msf2-som.c
425
+++ b/hw/arm/msf2-som.c
426
@@ -XXX,XX +XXX,XX @@
427
#include "qapi/error.h"
428
#include "qemu/error-report.h"
429
#include "hw/boards.h"
430
-#include "hw/arm/arm.h"
431
+#include "hw/arm/boot.h"
432
#include "exec/address-spaces.h"
433
#include "hw/arm/msf2-soc.h"
434
#include "cpu.h"
435
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
436
index XXXXXXX..XXXXXXX 100644
437
--- a/hw/arm/musca.c
438
+++ b/hw/arm/musca.c
439
@@ -XXX,XX +XXX,XX @@
440
#include "qapi/error.h"
441
#include "exec/address-spaces.h"
442
#include "sysemu/sysemu.h"
443
-#include "hw/arm/arm.h"
444
+#include "hw/arm/boot.h"
445
#include "hw/arm/armsse.h"
446
#include "hw/boards.h"
447
#include "hw/char/pl011.h"
448
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
449
index XXXXXXX..XXXXXXX 100644
450
--- a/hw/arm/musicpal.c
451
+++ b/hw/arm/musicpal.c
452
@@ -XXX,XX +XXX,XX @@
453
#include "qemu-common.h"
454
#include "cpu.h"
455
#include "hw/sysbus.h"
456
-#include "hw/arm/arm.h"
457
+#include "hw/arm/boot.h"
458
#include "net/net.h"
459
#include "sysemu/sysemu.h"
460
#include "hw/boards.h"
461
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
462
index XXXXXXX..XXXXXXX 100644
463
--- a/hw/arm/netduino2.c
464
+++ b/hw/arm/netduino2.c
465
@@ -XXX,XX +XXX,XX @@
466
#include "hw/boards.h"
467
#include "qemu/error-report.h"
468
#include "hw/arm/stm32f205_soc.h"
469
-#include "hw/arm/arm.h"
470
+#include "hw/arm/boot.h"
471
472
static void netduino2_init(MachineState *machine)
473
{
84
{
474
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
85
SysBusDevice *sbd;
475
index XXXXXXX..XXXXXXX 100644
86
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
476
--- a/hw/arm/nrf51_soc.c
87
hwaddr base;
477
+++ b/hw/arm/nrf51_soc.c
88
hwaddr size;
478
@@ -XXX,XX +XXX,XX @@
89
} unimp_areas[ARRAY_SIZE(s->mr_unimp)] = {
479
#include "qemu/osdep.h"
90
- { .name = "apu", APU_ADDR, APU_SIZE },
480
#include "qapi/error.h"
91
{ .name = "serdes", SERDES_ADDR, SERDES_SIZE },
481
#include "qemu-common.h"
92
};
482
-#include "hw/arm/arm.h"
93
unsigned int nr;
483
+#include "hw/arm/boot.h"
94
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
484
#include "hw/sysbus.h"
95
485
#include "hw/boards.h"
96
xlnx_zynqmp_create_bbram(s, gic_spi);
486
#include "hw/misc/unimp.h"
97
xlnx_zynqmp_create_efuse(s, gic_spi);
487
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
98
+ xlnx_zynqmp_create_apu_ctrl(s, gic_spi);
488
index XXXXXXX..XXXXXXX 100644
99
xlnx_zynqmp_create_crf(s, gic_spi);
489
--- a/hw/arm/nseries.c
100
xlnx_zynqmp_create_unimp_mmio(s);
490
+++ b/hw/arm/nseries.c
101
491
@@ -XXX,XX +XXX,XX @@
492
#include "qemu/bswap.h"
493
#include "sysemu/sysemu.h"
494
#include "hw/arm/omap.h"
495
-#include "hw/arm/arm.h"
496
+#include "hw/arm/boot.h"
497
#include "hw/irq.h"
498
#include "ui/console.h"
499
#include "hw/boards.h"
500
diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
501
index XXXXXXX..XXXXXXX 100644
502
--- a/hw/arm/omap1.c
503
+++ b/hw/arm/omap1.c
504
@@ -XXX,XX +XXX,XX @@
505
#include "cpu.h"
506
#include "hw/boards.h"
507
#include "hw/hw.h"
508
-#include "hw/arm/arm.h"
509
+#include "hw/arm/boot.h"
510
#include "hw/arm/omap.h"
511
#include "sysemu/sysemu.h"
512
#include "hw/arm/soc_dma.h"
513
diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
514
index XXXXXXX..XXXXXXX 100644
515
--- a/hw/arm/omap2.c
516
+++ b/hw/arm/omap2.c
517
@@ -XXX,XX +XXX,XX @@
518
#include "sysemu/qtest.h"
519
#include "hw/boards.h"
520
#include "hw/hw.h"
521
-#include "hw/arm/arm.h"
522
+#include "hw/arm/boot.h"
523
#include "hw/arm/omap.h"
524
#include "sysemu/sysemu.h"
525
#include "qemu/timer.h"
526
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
527
index XXXXXXX..XXXXXXX 100644
528
--- a/hw/arm/omap_sx1.c
529
+++ b/hw/arm/omap_sx1.c
530
@@ -XXX,XX +XXX,XX @@
531
#include "ui/console.h"
532
#include "hw/arm/omap.h"
533
#include "hw/boards.h"
534
-#include "hw/arm/arm.h"
535
+#include "hw/arm/boot.h"
536
#include "hw/block/flash.h"
537
#include "sysemu/qtest.h"
538
#include "exec/address-spaces.h"
539
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
540
index XXXXXXX..XXXXXXX 100644
541
--- a/hw/arm/palm.c
542
+++ b/hw/arm/palm.c
543
@@ -XXX,XX +XXX,XX @@
544
#include "ui/console.h"
545
#include "hw/arm/omap.h"
546
#include "hw/boards.h"
547
-#include "hw/arm/arm.h"
548
+#include "hw/arm/boot.h"
549
#include "hw/input/tsc2xxx.h"
550
#include "hw/loader.h"
551
#include "exec/address-spaces.h"
552
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
553
index XXXXXXX..XXXXXXX 100644
554
--- a/hw/arm/raspi.c
555
+++ b/hw/arm/raspi.c
556
@@ -XXX,XX +XXX,XX @@
557
#include "qemu/error-report.h"
558
#include "hw/boards.h"
559
#include "hw/loader.h"
560
-#include "hw/arm/arm.h"
561
+#include "hw/arm/boot.h"
562
#include "sysemu/sysemu.h"
563
564
#define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS */
565
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
566
index XXXXXXX..XXXXXXX 100644
567
--- a/hw/arm/realview.c
568
+++ b/hw/arm/realview.c
569
@@ -XXX,XX +XXX,XX @@
570
#include "qemu-common.h"
571
#include "cpu.h"
572
#include "hw/sysbus.h"
573
-#include "hw/arm/arm.h"
574
+#include "hw/arm/boot.h"
575
#include "hw/arm/primecell.h"
576
#include "hw/net/lan9118.h"
577
#include "hw/net/smc91c111.h"
578
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
579
index XXXXXXX..XXXXXXX 100644
580
--- a/hw/arm/spitz.c
581
+++ b/hw/arm/spitz.c
582
@@ -XXX,XX +XXX,XX @@
583
#include "qapi/error.h"
584
#include "hw/hw.h"
585
#include "hw/arm/pxa.h"
586
-#include "hw/arm/arm.h"
587
+#include "hw/arm/boot.h"
588
#include "sysemu/sysemu.h"
589
#include "hw/pcmcia.h"
590
#include "hw/i2c/i2c.h"
591
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
592
index XXXXXXX..XXXXXXX 100644
593
--- a/hw/arm/stellaris.c
594
+++ b/hw/arm/stellaris.c
595
@@ -XXX,XX +XXX,XX @@
596
#include "qapi/error.h"
597
#include "hw/sysbus.h"
598
#include "hw/ssi/ssi.h"
599
-#include "hw/arm/arm.h"
600
+#include "hw/arm/boot.h"
601
#include "qemu/timer.h"
602
#include "hw/i2c/i2c.h"
603
#include "net/net.h"
604
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
605
index XXXXXXX..XXXXXXX 100644
606
--- a/hw/arm/stm32f205_soc.c
607
+++ b/hw/arm/stm32f205_soc.c
608
@@ -XXX,XX +XXX,XX @@
609
#include "qemu/osdep.h"
610
#include "qapi/error.h"
611
#include "qemu-common.h"
612
-#include "hw/arm/arm.h"
613
+#include "hw/arm/boot.h"
614
#include "exec/address-spaces.h"
615
#include "hw/arm/stm32f205_soc.h"
616
617
diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
618
index XXXXXXX..XXXXXXX 100644
619
--- a/hw/arm/strongarm.c
620
+++ b/hw/arm/strongarm.c
621
@@ -XXX,XX +XXX,XX @@
622
#include "hw/sysbus.h"
623
#include "strongarm.h"
624
#include "qemu/error-report.h"
625
-#include "hw/arm/arm.h"
626
+#include "hw/arm/boot.h"
627
#include "chardev/char-fe.h"
628
#include "chardev/char-serial.h"
629
#include "sysemu/sysemu.h"
630
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
631
index XXXXXXX..XXXXXXX 100644
632
--- a/hw/arm/tosa.c
633
+++ b/hw/arm/tosa.c
634
@@ -XXX,XX +XXX,XX @@
635
#include "qapi/error.h"
636
#include "hw/hw.h"
637
#include "hw/arm/pxa.h"
638
-#include "hw/arm/arm.h"
639
+#include "hw/arm/boot.h"
640
#include "hw/arm/sharpsl.h"
641
#include "hw/pcmcia.h"
642
#include "hw/boards.h"
643
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
644
index XXXXXXX..XXXXXXX 100644
645
--- a/hw/arm/versatilepb.c
646
+++ b/hw/arm/versatilepb.c
647
@@ -XXX,XX +XXX,XX @@
648
#include "qemu-common.h"
649
#include "cpu.h"
650
#include "hw/sysbus.h"
651
-#include "hw/arm/arm.h"
652
+#include "hw/arm/boot.h"
653
#include "hw/net/smc91c111.h"
654
#include "net/net.h"
655
#include "sysemu/sysemu.h"
656
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
657
index XXXXXXX..XXXXXXX 100644
658
--- a/hw/arm/vexpress.c
659
+++ b/hw/arm/vexpress.c
660
@@ -XXX,XX +XXX,XX @@
661
#include "qemu-common.h"
662
#include "cpu.h"
663
#include "hw/sysbus.h"
664
-#include "hw/arm/arm.h"
665
+#include "hw/arm/boot.h"
666
#include "hw/arm/primecell.h"
667
#include "hw/net/lan9118.h"
668
#include "hw/i2c/i2c.h"
669
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
670
index XXXXXXX..XXXXXXX 100644
671
--- a/hw/arm/virt.c
672
+++ b/hw/arm/virt.c
673
@@ -XXX,XX +XXX,XX @@
674
#include "qemu/option.h"
675
#include "qapi/error.h"
676
#include "hw/sysbus.h"
677
-#include "hw/arm/arm.h"
678
+#include "hw/arm/boot.h"
679
#include "hw/arm/primecell.h"
680
#include "hw/arm/virt.h"
681
#include "hw/block/flash.h"
682
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
683
index XXXXXXX..XXXXXXX 100644
684
--- a/hw/arm/xilinx_zynq.c
685
+++ b/hw/arm/xilinx_zynq.c
686
@@ -XXX,XX +XXX,XX @@
687
#include "qemu-common.h"
688
#include "cpu.h"
689
#include "hw/sysbus.h"
690
-#include "hw/arm/arm.h"
691
+#include "hw/arm/boot.h"
692
#include "net/net.h"
693
#include "exec/address-spaces.h"
694
#include "sysemu/sysemu.h"
695
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
696
index XXXXXXX..XXXXXXX 100644
697
--- a/hw/arm/xlnx-versal.c
698
+++ b/hw/arm/xlnx-versal.c
699
@@ -XXX,XX +XXX,XX @@
700
#include "net/net.h"
701
#include "sysemu/sysemu.h"
702
#include "sysemu/kvm.h"
703
-#include "hw/arm/arm.h"
704
+#include "hw/arm/boot.h"
705
#include "kvm_arm.h"
706
#include "hw/misc/unimp.h"
707
#include "hw/intc/arm_gicv3_common.h"
708
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
709
index XXXXXXX..XXXXXXX 100644
710
--- a/hw/arm/z2.c
711
+++ b/hw/arm/z2.c
712
@@ -XXX,XX +XXX,XX @@
713
#include "qemu/osdep.h"
714
#include "hw/hw.h"
715
#include "hw/arm/pxa.h"
716
-#include "hw/arm/arm.h"
717
+#include "hw/arm/boot.h"
718
#include "hw/i2c/i2c.h"
719
#include "hw/ssi/ssi.h"
720
#include "hw/boards.h"
721
--
102
--
722
2.20.1
103
2.25.1
723
104
724
105
diff view generated by jsdifflib
New patch
[PULL 19/21] util/osdep: Avoid madvise proto on modern Solaris
1
From: Andrew Deason <adeason@sinenomine.net>
1
2
3
On older Solaris releases (before Solaris 11), we didn't get a
4
prototype for madvise, and so util/osdep.c provides its own prototype.
5
Some time between the public Solaris 11.4 release and Solaris 11.4.42
6
CBE, we started getting an madvise prototype that looks like this:
7
8
extern int madvise(void *, size_t, int);
9
10
which conflicts with the prototype in util/osdeps.c. Instead of always
11
declaring this prototype, check if we're missing the madvise()
12
prototype, and only declare it ourselves if the prototype is missing.
13
Move the prototype to include/qemu/osdep.h, the normal place to handle
14
platform-specific header quirks.
15
16
The 'missing_madvise_proto' meson check contains an obviously wrong
17
prototype for madvise. So if that code compiles and links, we must be
18
missing the actual prototype for madvise.
19
20
Signed-off-by: Andrew Deason <adeason@sinenomine.net>
21
Message-id: 20220316035227.3702-2-adeason@sinenomine.net
22
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
23
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
---
25
meson.build | 23 +++++++++++++++++++++--
26
include/qemu/osdep.h | 8 ++++++++
27
util/osdep.c | 3 ---
28
3 files changed, 29 insertions(+), 5 deletions(-)
29
30
diff --git a/meson.build b/meson.build
31
index XXXXXXX..XXXXXXX 100644
32
--- a/meson.build
33
+++ b/meson.build
34
@@ -XXX,XX +XXX,XX @@ config_host_data.set('CONFIG_FDATASYNC', cc.links(gnu_source_prefix + '''
35
#error Not supported
36
#endif
37
}'''))
38
-config_host_data.set('CONFIG_MADVISE', cc.links(gnu_source_prefix + '''
39
+
40
+has_madvise = cc.links(gnu_source_prefix + '''
41
#include <sys/types.h>
42
#include <sys/mman.h>
43
#include <stddef.h>
44
- int main(void) { return madvise(NULL, 0, MADV_DONTNEED); }'''))
45
+ int main(void) { return madvise(NULL, 0, MADV_DONTNEED); }''')
46
+missing_madvise_proto = false
47
+if has_madvise
48
+ # Some platforms (illumos and Solaris before Solaris 11) provide madvise()
49
+ # but forget to prototype it. In this case, has_madvise will be true (the
50
+ # test program links despite a compile warning). To detect the
51
+ # missing-prototype case, we try again with a definitely-bogus prototype.
52
+ # This will only compile if the system headers don't provide the prototype;
53
+ # otherwise the conflicting prototypes will cause a compiler error.
54
+ missing_madvise_proto = cc.links(gnu_source_prefix + '''
55
+ #include <sys/types.h>
56
+ #include <sys/mman.h>
57
+ #include <stddef.h>
58
+ extern int madvise(int);
59
+ int main(void) { return madvise(0); }''')
60
+endif
61
+config_host_data.set('CONFIG_MADVISE', has_madvise)
62
+config_host_data.set('HAVE_MADVISE_WITHOUT_PROTOTYPE', missing_madvise_proto)
63
+
64
config_host_data.set('CONFIG_MEMFD', cc.links(gnu_source_prefix + '''
65
#include <sys/mman.h>
66
int main(void) { return memfd_create("foo", MFD_ALLOW_SEALING); }'''))
67
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
68
index XXXXXXX..XXXXXXX 100644
69
--- a/include/qemu/osdep.h
70
+++ b/include/qemu/osdep.h
71
@@ -XXX,XX +XXX,XX @@ void qemu_anon_ram_free(void *ptr, size_t size);
72
#define SIGIO SIGPOLL
73
#endif
74
75
+#ifdef HAVE_MADVISE_WITHOUT_PROTOTYPE
76
+/*
77
+ * See MySQL bug #7156 (http://bugs.mysql.com/bug.php?id=7156) for discussion
78
+ * about Solaris missing the madvise() prototype.
79
+ */
80
+extern int madvise(char *, size_t, int);
81
+#endif
82
+
83
#if defined(CONFIG_LINUX)
84
#ifndef BUS_MCEERR_AR
85
#define BUS_MCEERR_AR 4
86
diff --git a/util/osdep.c b/util/osdep.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/util/osdep.c
89
+++ b/util/osdep.c
90
@@ -XXX,XX +XXX,XX @@
91
92
#ifdef CONFIG_SOLARIS
93
#include <sys/statvfs.h>
94
-/* See MySQL bug #7156 (http://bugs.mysql.com/bug.php?id=7156) for
95
- discussion about Solaris header problems */
96
-extern int madvise(char *, size_t, int);
97
#endif
98
99
#include "qemu-common.h"
100
--
101
2.25.1
diff view generated by jsdifflib
New patch
[PULL 20/21] hw/i386/acpi-build: Avoid 'sun' identifier
1
From: Andrew Deason <adeason@sinenomine.net>
1
2
3
On Solaris, 'sun' is #define'd to 1, which causes errors if a variable
4
is named 'sun'. Slightly change the name of the var for the Slot User
5
Number so we can build on Solaris.
6
7
Reviewed-by: Ani Sinha <ani@anisinha.ca>
8
Signed-off-by: Andrew Deason <adeason@sinenomine.net>
9
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
10
Message-id: 20220316035227.3702-3-adeason@sinenomine.net
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/i386/acpi-build.c | 4 ++--
14
1 file changed, 2 insertions(+), 2 deletions(-)
15
16
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/i386/acpi-build.c
19
+++ b/hw/i386/acpi-build.c
20
@@ -XXX,XX +XXX,XX @@ Aml *aml_pci_device_dsm(void)
21
Aml *bnum = aml_arg(4);
22
Aml *func = aml_arg(2);
23
Aml *rev = aml_arg(1);
24
- Aml *sun = aml_arg(5);
25
+ Aml *sunum = aml_arg(5);
26
27
method = aml_method("PDSM", 6, AML_SERIALIZED);
28
29
@@ -XXX,XX +XXX,XX @@ Aml *aml_pci_device_dsm(void)
30
UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D");
31
ifctx = aml_if(aml_equal(aml_arg(0), UUID));
32
{
33
- aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sun), acpi_index));
34
+ aml_append(ifctx, aml_store(aml_call2("AIDX", bnum, sunum), acpi_index));
35
ifctx1 = aml_if(aml_equal(func, zero));
36
{
37
uint8_t byte_list[1];
38
--
39
2.25.1
diff view generated by jsdifflib
New patch
[PULL 21/21] util/osdep: Remove some early cruft
1
From: Andrew Deason <adeason@sinenomine.net>
1
2
3
The include for statvfs.h has not been needed since all statvfs calls
4
were removed in commit 4a1418e07bdc ("Unbreak large mem support by
5
removing kqemu").
6
7
The comment mentioning CONFIG_BSD hasn't made sense since an include
8
for config-host.h was removed in commit aafd75841001 ("util: Clean up
9
includes").
10
11
Remove this cruft.
12
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Andrew Deason <adeason@sinenomine.net>
15
Message-id: 20220316035227.3702-4-adeason@sinenomine.net
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
util/osdep.c | 7 -------
19
1 file changed, 7 deletions(-)
20
21
diff --git a/util/osdep.c b/util/osdep.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/util/osdep.c
24
+++ b/util/osdep.c
25
@@ -XXX,XX +XXX,XX @@
26
*/
27
#include "qemu/osdep.h"
28
#include "qapi/error.h"
29
-
30
-/* Needed early for CONFIG_BSD etc. */
31
-
32
-#ifdef CONFIG_SOLARIS
33
-#include <sys/statvfs.h>
34
-#endif
35
-
36
#include "qemu-common.h"
37
#include "qemu/cutils.h"
38
#include "qemu/sockets.h"
39
--
40
2.25.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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