The following changes since commit 64ada298b98a51eb2512607f6e6180cb330c47b1:

Merge remote-tracking branch 'remotes/legoater/tags/pull-ppc-20220302' into staging (2022-03-02 12:38:46 +0000)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220302

for you to fetch changes up to 268c11984e67867c22f53beb3c7f8b98900d66b2:

ui/cocoa.m: Remove unnecessary NSAutoreleasePools (2022-03-02 19:27:37 +0000)

* mps3-an547: Add missing user ahb interfaces

* hw/arm/mps2-tz.c: Update AN547 documentation URL

* hw/input/tsc210x: Don't abort on bad SPI word widths

* hw/i2c: flatten pca954x mux device

* target/arm: Support PSCI 1.1 and SMCCC 1.0

* target/arm: Fix early free of TCG temp in handle_simd_shift_fpint_conv()

* tests/qtest: add qtests for npcm7xx sdhci

* Implement FEAT_LVA

* Implement FEAT_LPA

* Implement FEAT_LPA2 (but do not enable it yet)

* Report KVM's actual PSCI version to guest in dtb

* ui/cocoa.m: Fix updateUIInfo threading issues

* ui/cocoa.m: Remove unnecessary NSAutoreleasePools

Akihiko Odaki (1):

target/arm: Support PSCI 1.1 and SMCCC 1.0

Jimmy Brisson (1):

mps3-an547: Add missing user ahb interfaces

Patrick Venture (1):

hw/i2c: flatten pca954x mux device

hw/arm/mps2-tz.c: Update AN547 documentation URL

hw/input/tsc210x: Don't abort on bad SPI word widths

target/arm: Report KVM's actual PSCI version to guest in dtb

ui/cocoa.m: Fix updateUIInfo threading issues

ui/cocoa.m: Remove unnecessary NSAutoreleasePools

Richard Henderson (16):

hw/registerfields: Add FIELD_SEX<N> and FIELD_SDP<N>

target/arm: Set TCR_EL1.TSZ for user-only

target/arm: Fault on invalid TCR_ELx.TxSZ

target/arm: Move arm_pamax out of line

target/arm: Pass outputsize down to check_s2_mmu_setup

target/arm: Use MAKE_64BIT_MASK to compute indexmask

target/arm: Honor TCR_ELx.{I}PS

target/arm: Prepare DBGBVR and DBGWVR for FEAT_LVA

target/arm: Implement FEAT_LVA

target/arm: Implement FEAT_LPA

target/arm: Extend arm_fi_to_lfsc to level -1

target/arm: Introduce tlbi_aa64_get_range

target/arm: Fix TLBIRange.base for 16k and 64k pages

target/arm: Validate tlbi TG matches translation granule in use

target/arm: Advertise all page sizes for -cpu max

target/arm: Implement FEAT_LPA2

Shengtan Mao (1):

tests/qtest: add qtests for npcm7xx sdhci

Wentao_Liang (1):

target/arm: Fix early free of TCG temp in handle_simd_shift_fpint_conv()

The AN547 application note URL has changed: update our comment

accordingly. (Rev B is still downloadable from the old URL,

but there is a new Rev C of the document now.)

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20220221094144.426191-1-peter.maydell@linaro.org

hw/arm/mps2-tz.c | 2 +-

1 file changed, 1 insertion(+), 1 deletion(-)

* Application Note AN524:

* https://developer.arm.com/documentation/dai0524/latest/

* Application Note AN547:

- * https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/DAI0547B_SSE300_PLUS_U55_FPGA_for_mps3.pdf

+ * https://developer.arm.com/documentation/dai0547/latest/

*

* The AN505 defers to the Cortex-M33 processor ARMv8M IoT Kit FVP User Guide

* (ARM ECM0601256) for the details of some of the device layout:

2.25.1

The tsc210x doesn't support anything other than 16-bit reads on the

SPI bus, but the guest can program the SPI controller to attempt

them anyway. If this happens, don't abort QEMU, just log this as

a guest error.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

Message-id: 20220221140750.514557-1-peter.maydell@linaro.org

hw/input/tsc210x.c | 8 ++++++--

1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/hw/input/tsc210x.c b/hw/input/tsc210x.c

--- a/hw/input/tsc210x.c

+++ b/hw/input/tsc210x.c

@@ -XXX,XX +XXX,XX @@

#include "hw/hw.h"

#include "audio/audio.h"

#include "qemu/timer.h"

+#include "qemu/log.h"

#include "sysemu/reset.h"

#include "ui/console.h"

#include "hw/arm/omap.h" /* For I2SCodec */

@@ -XXX,XX +XXX,XX @@ uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len)

TSC210xState *s = opaque;

uint32_t ret = 0;

- if (len != 16)

- hw_error("%s: FIXME: bad SPI word width %i\n", __func__, len);

+ if (len != 16) {

+ qemu_log_mask(LOG_GUEST_ERROR,

+ "%s: bad SPI word width %i\n", __func__, len);

+ return 0;

+ }

/* TODO: sequential reads etc - how do we make sure the host doesn't

* unintentionally read out a conversion result from a register while

2.25.1

From: Patrick Venture <venture@google.com>

Previously this device created N subdevices which each owned an i2c bus.

Now this device simply owns the N i2c busses directly.

Tested: Verified devices behind mux are still accessible via qmp and i2c

from within an arm32 SoC.

Reviewed-by: Hao Wu <wuhaotsh@google.com>

Signed-off-by: Patrick Venture <venture@google.com>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20220202164533.1283668-1-venture@google.com

hw/i2c/i2c_mux_pca954x.c | 77 +++++++---------------------------------

1 file changed, 13 insertions(+), 64 deletions(-)

diff --git a/hw/i2c/i2c_mux_pca954x.c b/hw/i2c/i2c_mux_pca954x.c

--- a/hw/i2c/i2c_mux_pca954x.c

+++ b/hw/i2c/i2c_mux_pca954x.c

#define PCA9548_CHANNEL_COUNT 8

#define PCA9546_CHANNEL_COUNT 4

-/*

- * struct Pca954xChannel - The i2c mux device will have N of these states

- * that own the i2c channel bus.

- * @bus: The owned channel bus.

- * @enabled: Is this channel active?

- */

-typedef struct Pca954xChannel {

- SysBusDevice parent;

-

- I2CBus *bus;

-

- bool enabled;

-} Pca954xChannel;

-

-#define TYPE_PCA954X_CHANNEL "pca954x-channel"

-#define PCA954X_CHANNEL(obj) \

- OBJECT_CHECK(Pca954xChannel, (obj), TYPE_PCA954X_CHANNEL)

-

/*

* struct Pca954xState - The pca954x state object.

* @control: The value written to the mux control.

@@ -XXX,XX +XXX,XX @@ typedef struct Pca954xState {

uint8_t control;

- /* The channel i2c buses. */

- Pca954xChannel channel[PCA9548_CHANNEL_COUNT];

+ bool enabled[PCA9548_CHANNEL_COUNT];

+ I2CBus *bus[PCA9548_CHANNEL_COUNT];

} Pca954xState;

/*

@@ -XXX,XX +XXX,XX @@ static bool pca954x_match(I2CSlave *candidate, uint8_t address,

}

for (i = 0; i < mc->nchans; i++) {

- if (!mux->channel[i].enabled) {

+ if (!mux->enabled[i]) {

continue;

}

- if (i2c_scan_bus(mux->channel[i].bus, address, broadcast,

+ if (i2c_scan_bus(mux->bus[i], address, broadcast,

current_devs)) {

if (!broadcast) {

return true;

@@ -XXX,XX +XXX,XX @@ static void pca954x_enable_channel(Pca954xState *s, uint8_t enable_mask)

*/

for (i = 0; i < mc->nchans; i++) {

if (enable_mask & (1 << i)) {

- s->channel[i].enabled = true;

+ s->enabled[i] = true;

} else {

- s->channel[i].enabled = false;

+ s->enabled[i] = false;

}

}

}

@@ -XXX,XX +XXX,XX @@ I2CBus *pca954x_i2c_get_bus(I2CSlave *mux, uint8_t channel)

Pca954xState *pca954x = PCA954X(mux);

g_assert(channel < pc->nchans);

- return I2C_BUS(qdev_get_child_bus(DEVICE(&pca954x->channel[channel]),

- "i2c-bus"));

-}

-

-static void pca954x_channel_init(Object *obj)

-{

- Pca954xChannel *s = PCA954X_CHANNEL(obj);

- s->bus = i2c_init_bus(DEVICE(s), "i2c-bus");

-

- /* Start all channels as disabled. */

- s->enabled = false;

-}

-

-static void pca954x_channel_class_init(ObjectClass *klass, void *data)

-{

- DeviceClass *dc = DEVICE_CLASS(klass);

- dc->desc = "Pca954x Channel";

+ return pca954x->bus[channel];

}

static void pca9546_class_init(ObjectClass *klass, void *data)

@@ -XXX,XX +XXX,XX @@ static void pca9548_class_init(ObjectClass *klass, void *data)

s->nchans = PCA9548_CHANNEL_COUNT;

}

-static void pca954x_realize(DeviceState *dev, Error **errp)

-{

- Pca954xState *s = PCA954X(dev);

- Pca954xClass *c = PCA954X_GET_CLASS(s);

- int i;

-

- /* SMBus modules. Cannot fail. */

- for (i = 0; i < c->nchans; i++) {

- sysbus_realize(SYS_BUS_DEVICE(&s->channel[i]), &error_abort);

- }

-}

-

static void pca954x_init(Object *obj)

{

Pca954xState *s = PCA954X(obj);

Pca954xClass *c = PCA954X_GET_CLASS(obj);

int i;

- /* Only initialize the children we expect. */

+ /* SMBus modules. Cannot fail. */

for (i = 0; i < c->nchans; i++) {

- object_initialize_child(obj, "channel[*]", &s->channel[i],

- TYPE_PCA954X_CHANNEL);

+ g_autofree gchar *bus_name = g_strdup_printf("i2c.%d", i);

+

+ /* start all channels as disabled. */

+ s->enabled[i] = false;

+ s->bus[i] = i2c_init_bus(DEVICE(s), bus_name);

}

}

@@ -XXX,XX +XXX,XX @@ static void pca954x_class_init(ObjectClass *klass, void *data)

rc->phases.enter = pca954x_enter_reset;

dc->desc = "Pca954x i2c-mux";

- dc->realize = pca954x_realize;

k->write_data = pca954x_write_data;

k->receive_byte = pca954x_read_byte;

@@ -XXX,XX +XXX,XX @@ static const TypeInfo pca954x_info[] = {

.parent = TYPE_PCA954X,

.class_init = pca9548_class_init,

},

- {

- .name = TYPE_PCA954X_CHANNEL,

- .parent = TYPE_SYS_BUS_DEVICE,

- .class_init = pca954x_channel_class_init,

- .instance_size = sizeof(Pca954xChannel),

- .instance_init = pca954x_channel_init,

- }

DEFINE_TYPES(pca954x_info)

2.25.1

From: Akihiko Odaki <akihiko.odaki@gmail.com>

target/arm/kvm-consts.h | 13 +++++++++----

hw/arm/boot.c | 12 +++++++++---

target/arm/cpu.c | 5 +++--

target/arm/hvf/hvf.c | 27 ++++++++++++++++++++++++++-

target/arm/kvm64.c | 2 +-

target/arm/psci.c | 35 ++++++++++++++++++++++++++++++++---

6 files changed, 80 insertions(+), 14 deletions(-)

diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/kvm-consts.h

+++ b/target/arm/kvm-consts.h

@@ -XXX,XX +XXX,XX @@ MISMATCH_CHECK(QEMU_PSCI_0_1_FN_MIGRATE, KVM_PSCI_FN_MIGRATE);

#define QEMU_PSCI_0_2_FN64_AFFINITY_INFO QEMU_PSCI_0_2_FN64(4)

#define QEMU_PSCI_0_2_FN64_MIGRATE QEMU_PSCI_0_2_FN64(5)

+#define QEMU_PSCI_1_0_FN_PSCI_FEATURES QEMU_PSCI_0_2_FN(10)

+

MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_SUSPEND, PSCI_0_2_FN_CPU_SUSPEND);

MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_OFF, PSCI_0_2_FN_CPU_OFF);

MISMATCH_CHECK(QEMU_PSCI_0_2_FN_CPU_ON, PSCI_0_2_FN_CPU_ON);

@@ -XXX,XX +XXX,XX @@ MISMATCH_CHECK(QEMU_PSCI_0_2_FN_MIGRATE, PSCI_0_2_FN_MIGRATE);

MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_CPU_SUSPEND, PSCI_0_2_FN64_CPU_SUSPEND);

MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_CPU_ON, PSCI_0_2_FN64_CPU_ON);

MISMATCH_CHECK(QEMU_PSCI_0_2_FN64_MIGRATE, PSCI_0_2_FN64_MIGRATE);

+MISMATCH_CHECK(QEMU_PSCI_1_0_FN_PSCI_FEATURES, PSCI_1_0_FN_PSCI_FEATURES);

/* PSCI v0.2 return values used by TCG emulation of PSCI */

/* No Trusted OS migration to worry about when offlining CPUs */

#define QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED 2

-/* We implement version 0.2 only */

-#define QEMU_PSCI_0_2_RET_VERSION_0_2 2

+#define QEMU_PSCI_VERSION_0_1 0x00001

+#define QEMU_PSCI_VERSION_0_2 0x00002

+#define QEMU_PSCI_VERSION_1_1 0x10001

MISMATCH_CHECK(QEMU_PSCI_0_2_RET_TOS_MIGRATION_NOT_REQUIRED, PSCI_0_2_TOS_MP);

-MISMATCH_CHECK(QEMU_PSCI_0_2_RET_VERSION_0_2,

- (PSCI_VERSION_MAJOR(0) | PSCI_VERSION_MINOR(2)));

+/* We don't bother to check every possible version value */

+MISMATCH_CHECK(QEMU_PSCI_VERSION_0_2, PSCI_VERSION(0, 2));

+MISMATCH_CHECK(QEMU_PSCI_VERSION_1_1, PSCI_VERSION(1, 1));

/* PSCI return values (inclusive of all PSCI versions) */

#define QEMU_PSCI_RET_SUCCESS 0

diff --git a/hw/arm/boot.c b/hw/arm/boot.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/boot.c

+++ b/hw/arm/boot.c

@@ -XXX,XX +XXX,XX @@ static void fdt_add_psci_node(void *fdt)

}

qemu_fdt_add_subnode(fdt, "/psci");

- if (armcpu->psci_version == 2) {

- const char comp[] = "arm,psci-0.2\0arm,psci";

- qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp));

+ if (armcpu->psci_version == QEMU_PSCI_VERSION_0_2 ||

+ armcpu->psci_version == QEMU_PSCI_VERSION_1_1) {

+ if (armcpu->psci_version == QEMU_PSCI_VERSION_0_2) {

+ const char comp[] = "arm,psci-0.2\0arm,psci";

+ qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp));

+ } else {

+ const char comp[] = "arm,psci-1.0\0arm,psci-0.2\0arm,psci";

+ qemu_fdt_setprop(fdt, "/psci", "compatible", comp, sizeof(comp));

+ }

cpu_off_fn = QEMU_PSCI_0_2_FN_CPU_OFF;

if (arm_feature(&armcpu->env, ARM_FEATURE_AARCH64)) {

@@ -XXX,XX +XXX,XX @@ static void arm_cpu_initfn(Object *obj)

* picky DTB consumer will also provide a helpful error message.

*/

cpu->dtb_compatible = "qemu,unknown";

- cpu->psci_version = 1; /* By default assume PSCI v0.1 */

+ cpu->psci_version = QEMU_PSCI_VERSION_0_1; /* By default assume PSCI v0.1 */

cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;

if (tcg_enabled() || hvf_enabled()) {

- cpu->psci_version = 2; /* TCG and HVF implement PSCI 0.2 */

+ /* TCG and HVF implement PSCI 1.1 */

+ cpu->psci_version = QEMU_PSCI_VERSION_1_1;

}

}

diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/hvf/hvf.c

+++ b/target/arm/hvf/hvf.c

@@ -XXX,XX +XXX,XX @@ static bool hvf_handle_psci_call(CPUState *cpu)

switch (param[0]) {

case QEMU_PSCI_0_2_FN_PSCI_VERSION: