docs/system/arm/aspeed.rst | 1 +

docs/system/arm/nuvoton.rst | 5 +-

include/hw/arm/bcm2835_peripherals.h | 3 +-

include/hw/misc/bcm2835_powermgt.h | 29 ++

target/arm/helper-mve.h | 108 +++++++

target/arm/translate.h | 41 +++

target/arm/mve.decode | 177 ++++++++++-

target/arm/t32.decode | 71 ++++-

hw/arm/bcm2835_peripherals.c | 13 +-

hw/gpio/gpio_pwr.c | 2 +-

hw/misc/bcm2835_powermgt.c | 160 ++++++++++

target/arm/helper-a64.c | 12 +-

target/arm/mve_helper.c | 524 +++++++++++++++++++++++++++++++--

target/arm/translate-a64.c | 86 +-----

target/arm/translate-mve.c | 261 +++++++++++++++-

target/arm/translate-neon.c | 81 -----

target/arm/translate.c | 327 +++++++++++++++++++-

target/arm/vfp_helper.c | 24 +-

hw/misc/meson.build | 1 +

tests/acceptance/boot_linux_console.py | 43 +++

20 files changed, 1760 insertions(+), 209 deletions(-)

create mode 100644 include/hw/misc/bcm2835_powermgt.h

create mode 100644 hw/misc/bcm2835_powermgt.c

From: Patrick Venture <venture@google.com>

Adds a line-item reference to the supported quanta-q71l-bmc aspeed

entry.

Signed-off-by: Patrick Venture <venture@google.com>

Reviewed-by: Cédric Le Goater <clg@kaod.org>

Message-id: 20210615192848.1065297-2-venture@google.com

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

docs/system/arm/aspeed.rst | 1 +

1 file changed, 1 insertion(+)

diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst

index XXXXXXX..XXXXXXX 100644

--- a/docs/system/arm/aspeed.rst

+++ b/docs/system/arm/aspeed.rst

@@ -XXX,XX +XXX,XX @@ etc.

AST2400 SoC based machines :

- ``palmetto-bmc`` OpenPOWER Palmetto POWER8 BMC

+- ``quanta-q71l-bmc`` OpenBMC Quanta BMC

AST2500 SoC based machines :

--

2.20.1

From: Patrick Venture <venture@google.com>

Add line item reference to quanta-gbs-bmc machine.

Signed-off-by: Patrick Venture <venture@google.com>

Reviewed-by: Cédric Le Goater <clg@kaod.org>

Message-id: 20210615192848.1065297-3-venture@google.com

[PMM: fixed underline Sphinx warning]

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

docs/system/arm/nuvoton.rst | 5 +++--

1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst

index XXXXXXX..XXXXXXX 100644

--- a/docs/system/arm/nuvoton.rst

+++ b/docs/system/arm/nuvoton.rst

@@ -XXX,XX +XXX,XX @@

-Nuvoton iBMC boards (``npcm750-evb``, ``quanta-gsj``)

-=====================================================

+Nuvoton iBMC boards (``*-bmc``, ``npcm750-evb``, ``quanta-gsj``)

+================================================================

The `Nuvoton iBMC`_ chips (NPCM7xx) are a family of ARM-based SoCs that are

designed to be used as Baseboard Management Controllers (BMCs) in various

@@ -XXX,XX +XXX,XX @@ segment. The following machines are based on this chip :

The NPCM730 SoC has two Cortex-A9 cores and is targeted for Data Center and

Hyperscale applications. The following machines are based on this chip :

+- ``quanta-gbs-bmc`` Quanta GBS server BMC

- ``quanta-gsj`` Quanta GSJ server BMC

There are also two more SoCs, NPCM710 and NPCM705, which are single-core

--

2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

Add a test booting and quickly shutdown a raspi2 machine,

to test the power management model:

(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_raspi2_initrd:

console: [ 0.000000] Booting Linux on physical CPU 0xf00

console: [ 0.000000] Linux version 4.14.98-v7+ (dom@dom-XPS-13-9370) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #1200 SMP Tue Feb 12 20:27:48 GMT 2019

console: [ 0.000000] CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=10c5387d

console: [ 0.000000] CPU: div instructions available: patching division code

console: [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache

console: [ 0.000000] OF: fdt: Machine model: Raspberry Pi 2 Model B

...

console: Boot successful.

console: cat /proc/cpuinfo

console: / # cat /proc/cpuinfo

...

console: processor : 3

console: model name : ARMv7 Processor rev 5 (v7l)

console: BogoMIPS : 125.00

console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm

console: CPU implementer : 0x41

console: CPU architecture: 7

console: CPU variant : 0x0

console: CPU part : 0xc07

console: CPU revision : 5

console: Hardware : BCM2835

console: Revision : 0000

console: Serial : 0000000000000000

console: cat /proc/iomem

console: / # cat /proc/iomem

console: 00000000-3bffffff : System RAM

console: 00008000-00afffff : Kernel code

console: 00c00000-00d468ef : Kernel data

console: 3f006000-3f006fff : dwc_otg

console: 3f007000-3f007eff : /soc/dma@7e007000

console: 3f00b880-3f00b8bf : /soc/mailbox@7e00b880

console: 3f100000-3f100027 : /soc/watchdog@7e100000

console: 3f101000-3f102fff : /soc/cprman@7e101000

console: 3f200000-3f2000b3 : /soc/gpio@7e200000

PASS (24.59 s)

RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | CANCEL 0

JOB TIME : 25.02 s

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>

Message-id: 20210531113837.1689775-1-f4bug@amsat.org

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

tests/acceptance/boot_linux_console.py | 43 ++++++++++++++++++++++++++

1 file changed, 43 insertions(+)

diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py

index XXXXXXX..XXXXXXX 100644

--- a/tests/acceptance/boot_linux_console.py

+++ b/tests/acceptance/boot_linux_console.py

@@ -XXX,XX +XXX,XX @@

from avocado import skip

from avocado import skipUnless

from avocado_qemu import Test

+from avocado_qemu import exec_command

from avocado_qemu import exec_command_and_wait_for_pattern

from avocado_qemu import interrupt_interactive_console_until_pattern

from avocado_qemu import wait_for_console_pattern

@@ -XXX,XX +XXX,XX @@ def test_arm_raspi2_uart0(self):

"""

self.do_test_arm_raspi2(0)

+ def test_arm_raspi2_initrd(self):

+ """

+ :avocado: tags=arch:arm

+ :avocado: tags=machine:raspi2

+ """

+ deb_url = ('http://archive.raspberrypi.org/debian/'

+ 'pool/main/r/raspberrypi-firmware/'

+ 'raspberrypi-kernel_1.20190215-1_armhf.deb')

+ deb_hash = 'cd284220b32128c5084037553db3c482426f3972'

+ deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash)

+ kernel_path = self.extract_from_deb(deb_path, '/boot/kernel7.img')

+ dtb_path = self.extract_from_deb(deb_path, '/boot/bcm2709-rpi-2-b.dtb')

+

+ initrd_url = ('https://github.com/groeck/linux-build-test/raw/'

+ '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'

+ 'arm/rootfs-armv7a.cpio.gz')

+ initrd_hash = '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'

+ initrd_path_gz = self.fetch_asset(initrd_url, asset_hash=initrd_hash)

+ initrd_path = os.path.join(self.workdir, 'rootfs.cpio')

+ archive.gzip_uncompress(initrd_path_gz, initrd_path)

+

+ self.vm.set_console()

+ kernel_command_line = (self.KERNEL_COMMON_COMMAND_LINE +

+ 'earlycon=pl011,0x3f201000 console=ttyAMA0 '

+ 'panic=-1 noreboot ' +

+ 'dwc_otg.fiq_fsm_enable=0')

+ self.vm.add_args('-kernel', kernel_path,

+ '-dtb', dtb_path,

+ '-initrd', initrd_path,

+ '-append', kernel_command_line,

+ '-no-reboot')

+ self.vm.launch()

+ self.wait_for_console_pattern('Boot successful.')

+

+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',

+ 'BCM2835')

+ exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',

+ '/soc/cprman@7e101000')

+ exec_command(self, 'halt')

+ # Wait for VM to shut down gracefully

+ self.vm.wait()

+

def test_arm_exynos4210_initrd(self):

"""

:avocado: tags=arch:arm

--

2.20.1

From: Joe Komlodi <joe.komlodi@xilinx.com>

If the CPU is running in default NaN mode (FPCR.DN == 1) and we execute

FRSQRTE, FRECPE, or FRECPX with a signaling NaN, parts_silence_nan_frac() will

assert due to fpst->default_nan_mode being set.

To avoid this, we check to see what NaN mode we're running in before we call

floatxx_silence_nan().

Signed-off-by: Joe Komlodi <joe.komlodi@xilinx.com>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 1624662174-175828-2-git-send-email-joe.komlodi@xilinx.com

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/helper-a64.c | 12 +++++++++---

target/arm/vfp_helper.c | 24 ++++++++++++++++++------

2 files changed, 27 insertions(+), 9 deletions(-)

diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/helper-a64.c

+++ b/target/arm/helper-a64.c

@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)

float16 nan = a;

if (float16_is_signaling_nan(a, fpst)) {

float_raise(float_flag_invalid, fpst);

- nan = float16_silence_nan(a, fpst);

+ if (!fpst->default_nan_mode) {

+ nan = float16_silence_nan(a, fpst);

+ }

}

if (fpst->default_nan_mode) {

nan = float16_default_nan(fpst);

@@ -XXX,XX +XXX,XX @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)

float32 nan = a;

if (float32_is_signaling_nan(a, fpst)) {

float_raise(float_flag_invalid, fpst);

- nan = float32_silence_nan(a, fpst);

+ if (!fpst->default_nan_mode) {

+ nan = float32_silence_nan(a, fpst);

+ }

}

if (fpst->default_nan_mode) {

nan = float32_default_nan(fpst);

@@ -XXX,XX +XXX,XX @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)

float64 nan = a;

if (float64_is_signaling_nan(a, fpst)) {

float_raise(float_flag_invalid, fpst);

- nan = float64_silence_nan(a, fpst);

+ if (!fpst->default_nan_mode) {

+ nan = float64_silence_nan(a, fpst);

+ }

}

if (fpst->default_nan_mode) {

nan = float64_default_nan(fpst);

diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/vfp_helper.c

+++ b/target/arm/vfp_helper.c

@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)

float16 nan = f16;

if (float16_is_signaling_nan(f16, fpst)) {

float_raise(float_flag_invalid, fpst);

- nan = float16_silence_nan(f16, fpst);

+ if (!fpst->default_nan_mode) {

+ nan = float16_silence_nan(f16, fpst);

+ }

}

if (fpst->default_nan_mode) {

nan = float16_default_nan(fpst);

@@ -XXX,XX +XXX,XX @@ float32 HELPER(recpe_f32)(float32 input, void *fpstp)

float32 nan = f32;

if (float32_is_signaling_nan(f32, fpst)) {

float_raise(float_flag_invalid, fpst);

- nan = float32_silence_nan(f32, fpst);

+ if (!fpst->default_nan_mode) {

+ nan = float32_silence_nan(f32, fpst);

+ }

}

if (fpst->default_nan_mode) {

nan = float32_default_nan(fpst);

@@ -XXX,XX +XXX,XX @@ float64 HELPER(recpe_f64)(float64 input, void *fpstp)

float64 nan = f64;

if (float64_is_signaling_nan(f64, fpst)) {

float_raise(float_flag_invalid, fpst);

- nan = float64_silence_nan(f64, fpst);

+ if (!fpst->default_nan_mode) {

+ nan = float64_silence_nan(f64, fpst);

+ }

}

if (fpst->default_nan_mode) {

nan = float64_default_nan(fpst);

@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)

float16 nan = f16;

if (float16_is_signaling_nan(f16, s)) {

float_raise(float_flag_invalid, s);

- nan = float16_silence_nan(f16, s);

+ if (!s->default_nan_mode) {

+ nan = float16_silence_nan(f16, fpstp);

+ }

}

if (s->default_nan_mode) {

nan = float16_default_nan(s);

@@ -XXX,XX +XXX,XX @@ float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)

float32 nan = f32;

if (float32_is_signaling_nan(f32, s)) {

float_raise(float_flag_invalid, s);

- nan = float32_silence_nan(f32, s);

+ if (!s->default_nan_mode) {

+ nan = float32_silence_nan(f32, fpstp);

+ }

}

if (s->default_nan_mode) {

nan = float32_default_nan(s);

@@ -XXX,XX +XXX,XX @@ float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)

float64 nan = f64;

if (float64_is_signaling_nan(f64, s)) {

float_raise(float_flag_invalid, s);

- nan = float64_silence_nan(f64, s);

+ if (!s->default_nan_mode) {

+ nan = float64_silence_nan(f64, fpstp);

+ }

}

if (s->default_nan_mode) {

nan = float64_default_nan(s);

--

2.20.1

@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a)

{ gen_helper_mve_vstrw, gen_helper_mve_vldrw },

{ NULL, NULL }

};

- return do_ldst(s, a, ldstfns[a->size][a->l]);

+ return do_ldst(s, a, ldstfns[a->size][a->l], a->size);

}

-#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST) \

+#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST, MSIZE) \

static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \

{ \

static MVEGenLdStFn * const ldstfns[2][2] = { \

{ gen_helper_mve_##ST, gen_helper_mve_##SLD }, \

{ NULL, gen_helper_mve_##ULD }, \

}; \

- return do_ldst(s, a, ldstfns[a->u][a->l]); \

+ return do_ldst(s, a, ldstfns[a->u][a->l], MSIZE); \

}

-DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h)

-DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w)

-DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w)

+DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h, MO_8)

+DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w, MO_8)

+DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w, MO_16)

static bool trans_VDUP(DisasContext *s, arg_VDUP *a)

{

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20210628135835.6690-3-peter.maydell@linaro.org

The function asimd_imm_const() in translate-neon.c is an

implementation of the pseudocode AdvSIMDExpandImm(), which we will

also want for MVE. Move the implementation to translate.c, with a

prototype in translate.h.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20210628135835.6690-4-peter.maydell@linaro.org

---

target/arm/translate.h | 16 ++++++++++

target/arm/translate-neon.c | 63 -------------------------------------

target/arm/translate.c | 57 +++++++++++++++++++++++++++++++++

3 files changed, 73 insertions(+), 63 deletions(-)

diff --git a/target/arm/translate.h b/target/arm/translate.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate.h

+++ b/target/arm/translate.h

@@ -XXX,XX +XXX,XX @@ static inline MemOp finalize_memop(DisasContext *s, MemOp opc)

return opc | s->be_data;

}

+/**

+ * asimd_imm_const: Expand an encoded SIMD constant value

+ *

+ * Expand a SIMD constant value. This is essentially the pseudocode

+ * AdvSIMDExpandImm, except that we also perform the boolean NOT needed for

+ * VMVN and VBIC (when cmode < 14 && op == 1).

+ *

+ * The combination cmode == 15 op == 1 is a reserved encoding for AArch32;

+ * callers must catch this.

+ *

+ * cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 was UNPREDICTABLE in v7A but

+ * is either not unpredictable or merely CONSTRAINED UNPREDICTABLE in v8A;

+ * we produce an immediate constant value of 0 in these cases.

+ */

+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op);

+

#endif /* TARGET_ARM_TRANSLATE_H */

diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-neon.c

+++ b/target/arm/translate-neon.c

@@ -XXX,XX +XXX,XX @@ DO_FP_2SH(VCVT_UH, gen_helper_gvec_vcvt_uh)

DO_FP_2SH(VCVT_HS, gen_helper_gvec_vcvt_hs)

DO_FP_2SH(VCVT_HU, gen_helper_gvec_vcvt_hu)

-static uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)

-{

- /*

- * Expand the encoded constant.

- * Note that cmode = 2,3,4,5,6,7,10,11,12,13 imm=0 is UNPREDICTABLE.

- * We choose to not special-case this and will behave as if a

- * valid constant encoding of 0 had been given.

- * cmode = 15 op = 1 must UNDEF; we assume decode has handled that.

- */

- switch (cmode) {

- case 0: case 1:

- /* no-op */

- break;

- case 2: case 3:

- imm <<= 8;

- break;

- case 4: case 5:

- imm <<= 16;

- break;

- case 6: case 7:

- imm <<= 24;

- break;

- case 8: case 9:

- imm |= imm << 16;

- break;

- case 10: case 11:

- imm = (imm << 8) | (imm << 24);

- break;

- case 12:

- imm = (imm << 8) | 0xff;

- break;

- case 13:

- imm = (imm << 16) | 0xffff;

- break;

- case 14:

- if (op) {

- /*

- * This is the only case where the top and bottom 32 bits

- * of the encoded constant differ.

- */

- uint64_t imm64 = 0;

- int n;

-

- for (n = 0; n < 8; n++) {

- if (imm & (1 << n)) {

- imm64 |= (0xffULL << (n * 8));

- }

- }

- return imm64;

- }

- imm |= (imm << 8) | (imm << 16) | (imm << 24);

- break;

- case 15:

- imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)

- | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));

- break;

- }

- if (op) {

- imm = ~imm;

- }

- return dup_const(MO_32, imm);

-}

-

static bool do_1reg_imm(DisasContext *s, arg_1reg_imm *a,

GVecGen2iFn *fn)

{

diff --git a/target/arm/translate.c b/target/arm/translate.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate.c

+++ b/target/arm/translate.c

@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)

a64_translate_init();

}

+uint64_t asimd_imm_const(uint32_t imm, int cmode, int op)

+{

+ /* Expand the encoded constant as per AdvSIMDExpandImm pseudocode */

+ switch (cmode) {

+ case 0: case 1:

+ /* no-op */

+ break;

+ case 2: case 3:

+ imm <<= 8;

+ break;

+ case 4: case 5:

+ imm <<= 16;

+ break;

+ case 6: case 7:

+ imm <<= 24;

+ break;

+ case 8: case 9:

+ imm |= imm << 16;

+ break;

+ case 10: case 11:

+ imm = (imm << 8) | (imm << 24);

+ break;

+ case 12:

+ imm = (imm << 8) | 0xff;

+ break;

+ case 13:

+ imm = (imm << 16) | 0xffff;

+ break;

+ case 14:

+ if (op) {

+ /*

+ * This is the only case where the top and bottom 32 bits

+ * of the encoded constant differ.

+ */

+ uint64_t imm64 = 0;

+ int n;

+

+ for (n = 0; n < 8; n++) {

+ if (imm & (1 << n)) {

+ imm64 |= (0xffULL << (n * 8));

+ }

+ }

+ return imm64;

+ }

+ imm |= (imm << 8) | (imm << 16) | (imm << 24);

+ break;

+ case 15:

+ imm = ((imm & 0x80) << 24) | ((imm & 0x3f) << 19)

+ | ((imm & 0x40) ? (0x1f << 25) : (1 << 30));

+ break;

+ }

+ if (op) {

+ imm = ~imm;

+ }

+ return dup_const(MO_32, imm);

+}

+

/* Generate a label used for skipping this instruction */

void arm_gen_condlabel(DisasContext *s)

{

--

2.20.1