[Qemu-devel] [PULL 00/12] target-arm queue
[PULL 00/18] target-arm queue
1
Not very much here, but several people have fallen over
1
Nothing very exciting this time around...
2
the vector operation segfault bug, so let's get the fix
3
into master.
4
2
5
thanks
6
-- PMM
3
-- PMM
7
4
8
The following changes since commit d418238dca7b4e0b124135827ead3076233052b1:
5
The following changes since commit 37a712a0f969ca2df7f01182409a6c4825cebfb5:
9
6
10
Merge remote-tracking branch 'remotes/rth/tags/pull-rng-20190522' into staging (2019-05-23 12:57:17 +0100)
7
Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging (2020-10-01 12:23:19 +0100)
11
8
12
are available in the Git repository at:
9
are available in the Git repository at:
13
10
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190523
11
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201001
15
12
16
for you to fetch changes up to 98e4f4fdb8ea05d840f51f47125924c2bb9df2df:
13
for you to fetch changes up to cdfaa57dcb53ba012439765a1462247dfda8595d:
17
14
18
hw/arm/exynos4210: QOM'ify the Exynos4210 SoC (2019-05-23 14:47:44 +0100)
15
hw/arm/raspi: Remove use of the 'version' value in the board code (2020-10-01 15:31:01 +0100)
19
16
20
----------------------------------------------------------------
17
----------------------------------------------------------------
21
target-arm queue:
18
target-arm queue:
22
* exynos4210: QOM'ify the Exynos4210 SoC
19
* Make isar_feature_aa32_fp16_arith() handle M-profile
23
* exynos4210: Add DMA support for the Exynos4210
20
* Fix SVE splice
24
* arm_gicv3: Fix writes to ICC_CTLR_EL3
21
* Fix SVE LDR/STR
25
* arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
22
* Remove ignore_memory_transaction_failures on the raspi2
26
* target/arm: Fix vector operation segfault
23
* raspi: Various cleanup/refactoring
27
* target/arm: Minor improvements to BFXIL, EXTR
28
24
29
----------------------------------------------------------------
25
----------------------------------------------------------------
30
Alistair Francis (1):
26
Peter Maydell (5):
31
target/arm: Fix vector operation segfault
27
target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check
28
target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters
29
hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUs
30
target/arm: Add ID register values for Cortex-M0
31
target/arm: Make isar_feature_aa32_fp16_arith() handle M-profile
32
32
33
Guenter Roeck (1):
33
Philippe Mathieu-Daudé (11):
34
hw/arm/exynos4210: Add DMA support for the Exynos4210
34
hw/arm/raspi: Define various blocks base addresses
35
35
hw/arm/bcm2835: Add more unimplemented peripherals
36
Peter Maydell (5):
36
hw/arm/raspi: Remove ignore_memory_transaction_failures on the raspi2
37
arm: Move system_clock_scale to armv7m_systick.h
37
hw/arm/raspi: Display the board revision in the machine description
38
arm: Remove unnecessary includes of hw/arm/arm.h
38
hw/arm/raspi: Load the firmware on the first core
39
arm: Rename hw/arm/arm.h to hw/arm/boot.h
39
hw/arm/raspi: Move arm_boot_info structure to RaspiMachineState
40
hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
40
hw/arm/raspi: Avoid using TypeInfo::class_data pointer
41
hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3
41
hw/arm/raspi: Use more specific machine names
42
42
hw/arm/raspi: Introduce RaspiProcessorId enum
43
Philippe Mathieu-Daudé (3):
43
hw/arm/raspi: Use RaspiProcessorId to set the firmware load address
44
hw/arm/exynos4: Remove unuseful debug code
44
hw/arm/raspi: Remove use of the 'version' value in the board code
45
hw/arm/exynos4: Use the IEC binary prefix definitions
46
hw/arm/exynos4210: QOM'ify the Exynos4210 SoC
47
45
48
Richard Henderson (2):
46
Richard Henderson (2):
49
target/arm: Use extract2 for EXTR
47
target/arm: Fix sve ldr/str
50
target/arm: Simplify BFXIL expansion
48
target/arm: Fix SVE splice
51
49
52
include/hw/arm/allwinner-a10.h | 2 +-
50
include/hw/arm/bcm2835_peripherals.h | 2 +
53
include/hw/arm/aspeed_soc.h | 1 -
51
include/hw/arm/raspi_platform.h | 51 ++++++++++--
54
include/hw/arm/bcm2836.h | 1 -
52
target/arm/cpu.h | 50 +++++++++--
55
include/hw/arm/{arm.h => boot.h} | 12 +++------
53
hw/arm/bcm2835_peripherals.c | 2 +
56
include/hw/arm/exynos4210.h | 9 +++++--
54
hw/arm/raspi.c | 155 +++++++++++++++++++----------------
57
include/hw/arm/fsl-imx25.h | 2 +-
55
hw/intc/armv7m_nvic.c | 46 ++++++++++-
58
include/hw/arm/fsl-imx31.h | 2 +-
56
target/arm/cpu.c | 21 +++--
59
include/hw/arm/fsl-imx6.h | 2 +-
57
target/arm/cpu64.c | 12 +--
60
include/hw/arm/fsl-imx6ul.h | 2 +-
58
target/arm/cpu_tcg.c | 60 ++++++++++----
61
include/hw/arm/fsl-imx7.h | 2 +-
59
target/arm/helper.c | 9 +-
62
include/hw/arm/virt.h | 2 +-
60
target/arm/kvm64.c | 4 +
63
include/hw/arm/xlnx-versal.h | 2 +-
61
target/arm/translate-sve.c | 6 +-
64
include/hw/arm/xlnx-zynqmp.h | 2 +-
62
12 files changed, 286 insertions(+), 132 deletions(-)
65
include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++
66
hw/arm/armsse.c | 2 +-
67
hw/arm/armv7m.c | 2 +-
68
hw/arm/aspeed.c | 2 +-
69
hw/arm/boot.c | 2 +-
70
hw/arm/collie.c | 2 +-
71
hw/arm/exynos4210.c | 54 ++++++++++++++++++++++++++++++++++++---
72
hw/arm/exynos4_boards.c | 40 ++++++++---------------------
73
hw/arm/highbank.c | 2 +-
74
hw/arm/integratorcp.c | 2 +-
75
hw/arm/mainstone.c | 2 +-
76
hw/arm/microbit.c | 2 +-
77
hw/arm/mps2-tz.c | 2 +-
78
hw/arm/mps2.c | 2 +-
79
hw/arm/msf2-soc.c | 1 -
80
hw/arm/msf2-som.c | 2 +-
81
hw/arm/musca.c | 2 +-
82
hw/arm/musicpal.c | 2 +-
83
hw/arm/netduino2.c | 2 +-
84
hw/arm/nrf51_soc.c | 2 +-
85
hw/arm/nseries.c | 2 +-
86
hw/arm/omap1.c | 2 +-
87
hw/arm/omap2.c | 2 +-
88
hw/arm/omap_sx1.c | 2 +-
89
hw/arm/palm.c | 2 +-
90
hw/arm/raspi.c | 2 +-
91
hw/arm/realview.c | 2 +-
92
hw/arm/spitz.c | 2 +-
93
hw/arm/stellaris.c | 2 +-
94
hw/arm/stm32f205_soc.c | 2 +-
95
hw/arm/strongarm.c | 2 +-
96
hw/arm/tosa.c | 2 +-
97
hw/arm/versatilepb.c | 2 +-
98
hw/arm/vexpress.c | 2 +-
99
hw/arm/virt.c | 2 +-
100
hw/arm/xilinx_zynq.c | 2 +-
101
hw/arm/xlnx-versal.c | 2 +-
102
hw/arm/z2.c | 2 +-
103
hw/intc/arm_gicv3_cpuif.c | 6 ++---
104
hw/intc/armv7m_nvic.c | 1 -
105
target/arm/arm-semi.c | 1 -
106
target/arm/cpu.c | 1 -
107
target/arm/cpu64.c | 1 -
108
target/arm/kvm.c | 1 -
109
target/arm/kvm32.c | 1 -
110
target/arm/kvm64.c | 1 -
111
target/arm/translate-a64.c | 44 ++++++++++++++++---------------
112
target/arm/translate.c | 4 +--
113
61 files changed, 164 insertions(+), 123 deletions(-)
114
rename include/hw/arm/{arm.h => boot.h} (96%)
115
63
diff view generated by jsdifflib
New patch
[PULL 01/18] target/arm: Replace ARM_FEATURE_PXN with ID_MMFR0.VMSA check
1
The ARM_FEATURE_PXN bit indicates whether the CPU supports the PXN
2
bit in short-descriptor translation table format descriptors. This
3
is indicated by ID_MMFR0.VMSA being at least 0b0100. Replace the
4
feature bit with an ID register check, in line with our preference
5
for ID register checks over feature bits.
1
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200910173855.4068-2-peter.maydell@linaro.org
10
---
11
target/arm/cpu.h | 15 ++++++++++++++-
12
target/arm/cpu.c | 1 -
13
target/arm/helper.c | 5 +++--
14
3 files changed, 17 insertions(+), 4 deletions(-)
15
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
19
+++ b/target/arm/cpu.h
20
@@ -XXX,XX +XXX,XX @@ FIELD(ID_ISAR6, FHM, 8, 4)
21
FIELD(ID_ISAR6, SB, 12, 4)
22
FIELD(ID_ISAR6, SPECRES, 16, 4)
23
24
+FIELD(ID_MMFR0, VMSA, 0, 4)
25
+FIELD(ID_MMFR0, PMSA, 4, 4)
26
+FIELD(ID_MMFR0, OUTERSHR, 8, 4)
27
+FIELD(ID_MMFR0, SHARELVL, 12, 4)
28
+FIELD(ID_MMFR0, TCM, 16, 4)
29
+FIELD(ID_MMFR0, AUXREG, 20, 4)
30
+FIELD(ID_MMFR0, FCSE, 24, 4)
31
+FIELD(ID_MMFR0, INNERSHR, 28, 4)
32
+
33
FIELD(ID_MMFR3, CMAINTVA, 0, 4)
34
FIELD(ID_MMFR3, CMAINTSW, 4, 4)
35
FIELD(ID_MMFR3, BPMAINT, 8, 4)
36
@@ -XXX,XX +XXX,XX @@ enum arm_features {
37
ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
38
ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
39
ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
40
- ARM_FEATURE_PXN, /* has Privileged Execute Never bit */
41
ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
42
ARM_FEATURE_V8,
43
ARM_FEATURE_AARCH64, /* supports 64 bit mode */
44
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
45
return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >= 4;
46
}
47
48
+static inline bool isar_feature_aa32_pxn(const ARMISARegisters *id)
49
+{
50
+ return FIELD_EX32(id->id_mmfr0, ID_MMFR0, VMSA) >= 4;
51
+}
52
+
53
static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
54
{
55
return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0;
56
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/target/arm/cpu.c
59
+++ b/target/arm/cpu.c
60
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
61
}
62
if (arm_feature(env, ARM_FEATURE_LPAE)) {
63
set_feature(env, ARM_FEATURE_V7MP);
64
- set_feature(env, ARM_FEATURE_PXN);
65
}
66
if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
67
set_feature(env, ARM_FEATURE_CBAR);
68
diff --git a/target/arm/helper.c b/target/arm/helper.c
69
index XXXXXXX..XXXXXXX 100644
70
--- a/target/arm/helper.c
71
+++ b/target/arm/helper.c
72
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
73
target_ulong *page_size, ARMMMUFaultInfo *fi)
74
{
75
CPUState *cs = env_cpu(env);
76
+ ARMCPU *cpu = env_archcpu(env);
77
int level = 1;
78
uint32_t table;
79
uint32_t desc;
80
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
81
goto do_fault;
82
}
83
type = (desc & 3);
84
- if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
85
+ if (type == 0 || (type == 3 && !cpu_isar_feature(aa32_pxn, cpu))) {
86
/* Section translation fault, or attempt to use the encoding
87
* which is Reserved on implementations without PXN.
88
*/
89
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_v6(CPUARMState *env, uint32_t address,
90
pxn = desc & 1;
91
ns = extract32(desc, 19, 1);
92
} else {
93
- if (arm_feature(env, ARM_FEATURE_PXN)) {
94
+ if (cpu_isar_feature(aa32_pxn, cpu)) {
95
pxn = (desc >> 2) & 1;
96
}
97
ns = extract32(desc, 3, 1);
98
--
99
2.20.1
100
101
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/12] arm: Remove unnecessary includes of hw/arm/arm.h
[PULL 02/18] target/arm: Move id_pfr0, id_pfr1 into ARMISARegisters
1
The hw/arm/arm.h header now only includes declarations relating
1
Move the id_pfr0 and id_pfr1 fields into the ARMISARegisters
2
to boot.c code, so it is only needed by Arm board or SoC code.
2
sub-struct. We're going to want id_pfr1 for an isar_features
3
Remove some unnecessary inclusions of it from target/arm files
3
check, and moving both at the same time avoids an odd
4
and from hw/intc/armv7m_nvic.c.
4
inconsistency.
5
6
Changes other than the ones to cpu.h and kvm64.c made
7
automatically with:
8
perl -p -i -e 's/cpu->id_pfr/cpu->isar.id_pfr/' target/arm/*.c hw/intc/armv7m_nvic.c
5
9
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Message-id: 20200910173855.4068-3-peter.maydell@linaro.org
9
Message-id: 20190516163857.6430-3-peter.maydell@linaro.org
10
---
13
---
11
hw/intc/armv7m_nvic.c | 1 -
14
target/arm/cpu.h | 4 ++--
12
target/arm/arm-semi.c | 1 -
15
hw/intc/armv7m_nvic.c | 4 ++--
13
target/arm/cpu.c | 1 -
16
target/arm/cpu.c | 20 ++++++++++----------
14
target/arm/cpu64.c | 1 -
17
target/arm/cpu64.c | 12 ++++++------
15
target/arm/kvm.c | 1 -
18
target/arm/cpu_tcg.c | 36 ++++++++++++++++++------------------
16
target/arm/kvm32.c | 1 -
19
target/arm/helper.c | 4 ++--
17
target/arm/kvm64.c | 1 -
20
target/arm/kvm64.c | 4 ++++
18
7 files changed, 7 deletions(-)
21
7 files changed, 44 insertions(+), 40 deletions(-)
19
22
23
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
24
index XXXXXXX..XXXXXXX 100644
25
--- a/target/arm/cpu.h
26
+++ b/target/arm/cpu.h
27
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
28
uint32_t id_mmfr2;
29
uint32_t id_mmfr3;
30
uint32_t id_mmfr4;
31
+ uint32_t id_pfr0;
32
+ uint32_t id_pfr1;
33
uint32_t mvfr0;
34
uint32_t mvfr1;
35
uint32_t mvfr2;
36
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
37
uint32_t reset_fpsid;
38
uint32_t ctr;
39
uint32_t reset_sctlr;
40
- uint32_t id_pfr0;
41
- uint32_t id_pfr1;
42
uint64_t pmceid0;
43
uint64_t pmceid1;
44
uint32_t id_afr0;
20
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
45
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
21
index XXXXXXX..XXXXXXX 100644
46
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/intc/armv7m_nvic.c
47
--- a/hw/intc/armv7m_nvic.c
23
+++ b/hw/intc/armv7m_nvic.c
48
+++ b/hw/intc/armv7m_nvic.c
24
@@ -XXX,XX +XXX,XX @@
49
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
25
#include "cpu.h"
50
"Aux Fault status registers unimplemented\n");
26
#include "hw/sysbus.h"
51
return 0;
27
#include "qemu/timer.h"
52
case 0xd40: /* PFR0. */
28
-#include "hw/arm/arm.h"
53
- return cpu->id_pfr0;
29
#include "hw/intc/armv7m_nvic.h"
54
+ return cpu->isar.id_pfr0;
30
#include "target/arm/cpu.h"
55
case 0xd44: /* PFR1. */
31
#include "exec/exec-all.h"
56
- return cpu->id_pfr1;
32
diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
57
+ return cpu->isar.id_pfr1;
33
index XXXXXXX..XXXXXXX 100644
58
case 0xd48: /* DFR0. */
34
--- a/target/arm/arm-semi.c
59
return cpu->isar.id_dfr0;
35
+++ b/target/arm/arm-semi.c
60
case 0xd4c: /* AFR0. */
36
@@ -XXX,XX +XXX,XX @@
37
#else
38
#include "qemu-common.h"
39
#include "exec/gdbstub.h"
40
-#include "hw/arm/arm.h"
41
#include "qemu/cutils.h"
42
#endif
43
44
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
61
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
45
index XXXXXXX..XXXXXXX 100644
62
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/cpu.c
63
--- a/target/arm/cpu.c
47
+++ b/target/arm/cpu.c
64
+++ b/target/arm/cpu.c
48
@@ -XXX,XX +XXX,XX @@
65
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
49
#if !defined(CONFIG_USER_ONLY)
66
/* Disable the security extension feature bits in the processor feature
50
#include "hw/loader.h"
67
* registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
51
#endif
68
*/
52
-#include "hw/arm/arm.h"
69
- cpu->id_pfr1 &= ~0xf0;
53
#include "sysemu/sysemu.h"
70
+ cpu->isar.id_pfr1 &= ~0xf0;
54
#include "sysemu/hw_accel.h"
71
cpu->isar.id_aa64pfr0 &= ~0xf000;
55
#include "kvm_arm.h"
72
}
73
74
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
75
* id_aa64pfr0_el1[11:8].
76
*/
77
cpu->isar.id_aa64pfr0 &= ~0xf00;
78
- cpu->id_pfr1 &= ~0xf000;
79
+ cpu->isar.id_pfr1 &= ~0xf000;
80
}
81
82
#ifndef CONFIG_USER_ONLY
83
@@ -XXX,XX +XXX,XX @@ static void cortex_a8_initfn(Object *obj)
84
cpu->isar.mvfr1 = 0x00011111;
85
cpu->ctr = 0x82048004;
86
cpu->reset_sctlr = 0x00c50078;
87
- cpu->id_pfr0 = 0x1031;
88
- cpu->id_pfr1 = 0x11;
89
+ cpu->isar.id_pfr0 = 0x1031;
90
+ cpu->isar.id_pfr1 = 0x11;
91
cpu->isar.id_dfr0 = 0x400;
92
cpu->id_afr0 = 0;
93
cpu->isar.id_mmfr0 = 0x31100003;
94
@@ -XXX,XX +XXX,XX @@ static void cortex_a9_initfn(Object *obj)
95
cpu->isar.mvfr1 = 0x01111111;
96
cpu->ctr = 0x80038003;
97
cpu->reset_sctlr = 0x00c50078;
98
- cpu->id_pfr0 = 0x1031;
99
- cpu->id_pfr1 = 0x11;
100
+ cpu->isar.id_pfr0 = 0x1031;
101
+ cpu->isar.id_pfr1 = 0x11;
102
cpu->isar.id_dfr0 = 0x000;
103
cpu->id_afr0 = 0;
104
cpu->isar.id_mmfr0 = 0x00100103;
105
@@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj)
106
cpu->isar.mvfr1 = 0x11111111;
107
cpu->ctr = 0x84448003;
108
cpu->reset_sctlr = 0x00c50078;
109
- cpu->id_pfr0 = 0x00001131;
110
- cpu->id_pfr1 = 0x00011011;
111
+ cpu->isar.id_pfr0 = 0x00001131;
112
+ cpu->isar.id_pfr1 = 0x00011011;
113
cpu->isar.id_dfr0 = 0x02010555;
114
cpu->id_afr0 = 0x00000000;
115
cpu->isar.id_mmfr0 = 0x10101105;
116
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
117
cpu->isar.mvfr1 = 0x11111111;
118
cpu->ctr = 0x8444c004;
119
cpu->reset_sctlr = 0x00c50078;
120
- cpu->id_pfr0 = 0x00001131;
121
- cpu->id_pfr1 = 0x00011011;
122
+ cpu->isar.id_pfr0 = 0x00001131;
123
+ cpu->isar.id_pfr1 = 0x00011011;
124
cpu->isar.id_dfr0 = 0x02010555;
125
cpu->id_afr0 = 0x00000000;
126
cpu->isar.id_mmfr0 = 0x10201105;
56
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
127
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
57
index XXXXXXX..XXXXXXX 100644
128
index XXXXXXX..XXXXXXX 100644
58
--- a/target/arm/cpu64.c
129
--- a/target/arm/cpu64.c
59
+++ b/target/arm/cpu64.c
130
+++ b/target/arm/cpu64.c
60
@@ -XXX,XX +XXX,XX @@
131
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
61
#if !defined(CONFIG_USER_ONLY)
132
cpu->isar.mvfr2 = 0x00000043;
62
#include "hw/loader.h"
133
cpu->ctr = 0x8444c004;
63
#endif
134
cpu->reset_sctlr = 0x00c50838;
64
-#include "hw/arm/arm.h"
135
- cpu->id_pfr0 = 0x00000131;
65
#include "sysemu/sysemu.h"
136
- cpu->id_pfr1 = 0x00011011;
66
#include "sysemu/kvm.h"
137
+ cpu->isar.id_pfr0 = 0x00000131;
67
#include "kvm_arm.h"
138
+ cpu->isar.id_pfr1 = 0x00011011;
68
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
139
cpu->isar.id_dfr0 = 0x03010066;
69
index XXXXXXX..XXXXXXX 100644
140
cpu->id_afr0 = 0x00000000;
70
--- a/target/arm/kvm.c
141
cpu->isar.id_mmfr0 = 0x10101105;
71
+++ b/target/arm/kvm.c
142
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
72
@@ -XXX,XX +XXX,XX @@
143
cpu->isar.mvfr2 = 0x00000043;
73
#include "cpu.h"
144
cpu->ctr = 0x84448004; /* L1Ip = VIPT */
74
#include "trace.h"
145
cpu->reset_sctlr = 0x00c50838;
75
#include "internals.h"
146
- cpu->id_pfr0 = 0x00000131;
76
-#include "hw/arm/arm.h"
147
- cpu->id_pfr1 = 0x00011011;
77
#include "hw/pci/pci.h"
148
+ cpu->isar.id_pfr0 = 0x00000131;
78
#include "exec/memattrs.h"
149
+ cpu->isar.id_pfr1 = 0x00011011;
79
#include "exec/address-spaces.h"
150
cpu->isar.id_dfr0 = 0x03010066;
80
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
151
cpu->id_afr0 = 0x00000000;
81
index XXXXXXX..XXXXXXX 100644
152
cpu->isar.id_mmfr0 = 0x10101105;
82
--- a/target/arm/kvm32.c
153
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
83
+++ b/target/arm/kvm32.c
154
cpu->isar.mvfr2 = 0x00000043;
84
@@ -XXX,XX +XXX,XX @@
155
cpu->ctr = 0x8444c004;
85
#include "sysemu/kvm.h"
156
cpu->reset_sctlr = 0x00c50838;
86
#include "kvm_arm.h"
157
- cpu->id_pfr0 = 0x00000131;
87
#include "internals.h"
158
- cpu->id_pfr1 = 0x00011011;
88
-#include "hw/arm/arm.h"
159
+ cpu->isar.id_pfr0 = 0x00000131;
89
#include "qemu/log.h"
160
+ cpu->isar.id_pfr1 = 0x00011011;
90
161
cpu->isar.id_dfr0 = 0x03010066;
91
static inline void set_feature(uint64_t *features, int feature)
162
cpu->id_afr0 = 0x00000000;
163
cpu->isar.id_mmfr0 = 0x10201105;
164
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
165
index XXXXXXX..XXXXXXX 100644
166
--- a/target/arm/cpu_tcg.c
167
+++ b/target/arm/cpu_tcg.c
168
@@ -XXX,XX +XXX,XX @@ static void arm1136_r2_initfn(Object *obj)
169
cpu->isar.mvfr1 = 0x00000000;
170
cpu->ctr = 0x1dd20d2;
171
cpu->reset_sctlr = 0x00050078;
172
- cpu->id_pfr0 = 0x111;
173
- cpu->id_pfr1 = 0x1;
174
+ cpu->isar.id_pfr0 = 0x111;
175
+ cpu->isar.id_pfr1 = 0x1;
176
cpu->isar.id_dfr0 = 0x2;
177
cpu->id_afr0 = 0x3;
178
cpu->isar.id_mmfr0 = 0x01130003;
179
@@ -XXX,XX +XXX,XX @@ static void arm1136_initfn(Object *obj)
180
cpu->isar.mvfr1 = 0x00000000;
181
cpu->ctr = 0x1dd20d2;
182
cpu->reset_sctlr = 0x00050078;
183
- cpu->id_pfr0 = 0x111;
184
- cpu->id_pfr1 = 0x1;
185
+ cpu->isar.id_pfr0 = 0x111;
186
+ cpu->isar.id_pfr1 = 0x1;
187
cpu->isar.id_dfr0 = 0x2;
188
cpu->id_afr0 = 0x3;
189
cpu->isar.id_mmfr0 = 0x01130003;
190
@@ -XXX,XX +XXX,XX @@ static void arm1176_initfn(Object *obj)
191
cpu->isar.mvfr1 = 0x00000000;
192
cpu->ctr = 0x1dd20d2;
193
cpu->reset_sctlr = 0x00050078;
194
- cpu->id_pfr0 = 0x111;
195
- cpu->id_pfr1 = 0x11;
196
+ cpu->isar.id_pfr0 = 0x111;
197
+ cpu->isar.id_pfr1 = 0x11;
198
cpu->isar.id_dfr0 = 0x33;
199
cpu->id_afr0 = 0;
200
cpu->isar.id_mmfr0 = 0x01130003;
201
@@ -XXX,XX +XXX,XX @@ static void arm11mpcore_initfn(Object *obj)
202
cpu->isar.mvfr0 = 0x11111111;
203
cpu->isar.mvfr1 = 0x00000000;
204
cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
205
- cpu->id_pfr0 = 0x111;
206
- cpu->id_pfr1 = 0x1;
207
+ cpu->isar.id_pfr0 = 0x111;
208
+ cpu->isar.id_pfr1 = 0x1;
209
cpu->isar.id_dfr0 = 0;
210
cpu->id_afr0 = 0x2;
211
cpu->isar.id_mmfr0 = 0x01100103;
212
@@ -XXX,XX +XXX,XX @@ static void cortex_m3_initfn(Object *obj)
213
set_feature(&cpu->env, ARM_FEATURE_M_MAIN);
214
cpu->midr = 0x410fc231;
215
cpu->pmsav7_dregion = 8;
216
- cpu->id_pfr0 = 0x00000030;
217
- cpu->id_pfr1 = 0x00000200;
218
+ cpu->isar.id_pfr0 = 0x00000030;
219
+ cpu->isar.id_pfr1 = 0x00000200;
220
cpu->isar.id_dfr0 = 0x00100000;
221
cpu->id_afr0 = 0x00000000;
222
cpu->isar.id_mmfr0 = 0x00000030;
223
@@ -XXX,XX +XXX,XX @@ static void cortex_m4_initfn(Object *obj)
224
cpu->isar.mvfr0 = 0x10110021;
225
cpu->isar.mvfr1 = 0x11000011;
226
cpu->isar.mvfr2 = 0x00000000;
227
- cpu->id_pfr0 = 0x00000030;
228
- cpu->id_pfr1 = 0x00000200;
229
+ cpu->isar.id_pfr0 = 0x00000030;
230
+ cpu->isar.id_pfr1 = 0x00000200;
231
cpu->isar.id_dfr0 = 0x00100000;
232
cpu->id_afr0 = 0x00000000;
233
cpu->isar.id_mmfr0 = 0x00000030;
234
@@ -XXX,XX +XXX,XX @@ static void cortex_m7_initfn(Object *obj)
235
cpu->isar.mvfr0 = 0x10110221;
236
cpu->isar.mvfr1 = 0x12000011;
237
cpu->isar.mvfr2 = 0x00000040;
238
- cpu->id_pfr0 = 0x00000030;
239
- cpu->id_pfr1 = 0x00000200;
240
+ cpu->isar.id_pfr0 = 0x00000030;
241
+ cpu->isar.id_pfr1 = 0x00000200;
242
cpu->isar.id_dfr0 = 0x00100000;
243
cpu->id_afr0 = 0x00000000;
244
cpu->isar.id_mmfr0 = 0x00100030;
245
@@ -XXX,XX +XXX,XX @@ static void cortex_m33_initfn(Object *obj)
246
cpu->isar.mvfr0 = 0x10110021;
247
cpu->isar.mvfr1 = 0x11000011;
248
cpu->isar.mvfr2 = 0x00000040;
249
- cpu->id_pfr0 = 0x00000030;
250
- cpu->id_pfr1 = 0x00000210;
251
+ cpu->isar.id_pfr0 = 0x00000030;
252
+ cpu->isar.id_pfr1 = 0x00000210;
253
cpu->isar.id_dfr0 = 0x00200000;
254
cpu->id_afr0 = 0x00000000;
255
cpu->isar.id_mmfr0 = 0x00101F40;
256
@@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj)
257
set_feature(&cpu->env, ARM_FEATURE_PMSA);
258
set_feature(&cpu->env, ARM_FEATURE_PMU);
259
cpu->midr = 0x411fc153; /* r1p3 */
260
- cpu->id_pfr0 = 0x0131;
261
- cpu->id_pfr1 = 0x001;
262
+ cpu->isar.id_pfr0 = 0x0131;
263
+ cpu->isar.id_pfr1 = 0x001;
264
cpu->isar.id_dfr0 = 0x010400;
265
cpu->id_afr0 = 0x0;
266
cpu->isar.id_mmfr0 = 0x0210030;
267
diff --git a/target/arm/helper.c b/target/arm/helper.c
268
index XXXXXXX..XXXXXXX 100644
269
--- a/target/arm/helper.c
270
+++ b/target/arm/helper.c
271
@@ -XXX,XX +XXX,XX @@ static void define_pmu_regs(ARMCPU *cpu)
272
static uint64_t id_pfr1_read(CPUARMState *env, const ARMCPRegInfo *ri)
273
{
274
ARMCPU *cpu = env_archcpu(env);
275
- uint64_t pfr1 = cpu->id_pfr1;
276
+ uint64_t pfr1 = cpu->isar.id_pfr1;
277
278
if (env->gicv3state) {
279
pfr1 |= 1 << 28;
280
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
281
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
282
.access = PL1_R, .type = ARM_CP_CONST,
283
.accessfn = access_aa32_tid3,
284
- .resetvalue = cpu->id_pfr0 },
285
+ .resetvalue = cpu->isar.id_pfr0 },
286
/* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
287
* the value of the GIC field until after we define these regs.
288
*/
92
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
289
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
93
index XXXXXXX..XXXXXXX 100644
290
index XXXXXXX..XXXXXXX 100644
94
--- a/target/arm/kvm64.c
291
--- a/target/arm/kvm64.c
95
+++ b/target/arm/kvm64.c
292
+++ b/target/arm/kvm64.c
96
@@ -XXX,XX +XXX,XX @@
293
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
97
#include "sysemu/kvm.h"
294
* than skipping the reads and leaving 0, as we must avoid
98
#include "kvm_arm.h"
295
* considering the values in every case.
99
#include "internals.h"
296
*/
100
-#include "hw/arm/arm.h"
297
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr0,
101
298
+ ARM64_SYS_REG(3, 0, 0, 1, 0));
102
static bool have_guest_debug;
299
+ err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_pfr1,
103
300
+ ARM64_SYS_REG(3, 0, 0, 1, 1));
301
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0,
302
ARM64_SYS_REG(3, 0, 0, 1, 2));
303
err |= read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0,
104
--
304
--
105
2.20.1
305
2.20.1
106
306
107
307
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/12] hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
[PULL 03/18] hw/intc/armv7m_nvic: Only show ID register values for Main Extension CPUs
1
In ich_vmcr_write() we enforce "writes of BPR fields to less than
1
M-profile CPUs only implement the ID registers as guest-visible if
2
their minimum sets them to the minimum" by doing a "read vbpr and
2
the CPU implements the Main Extension (all our current CPUs except
3
write it back" operation. A typo here meant that we weren't handling
3
the Cortex-M0 do).
4
writes to these fields correctly, because we were reading from VBPR0
4
5
but writing to VBPR1.
5
Currently we handle this by having the Cortex-M0 leave the ID
6
register values in the ARMCPU struct as zero, but this conflicts with
7
our design decision to make QEMU behaviour be keyed off ID register
8
fields wherever possible.
9
10
Explicitly code the ID registers in the NVIC to return 0 if the Main
11
Extension is not implemented, so we can make the M0 model set the
12
ARMCPU struct fields to obtain the correct behaviour without those
13
values becoming guest-visible.
6
14
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20190520162809.2677-4-peter.maydell@linaro.org
17
Message-id: 20200910173855.4068-4-peter.maydell@linaro.org
10
---
18
---
11
hw/intc/arm_gicv3_cpuif.c | 2 +-
19
hw/intc/armv7m_nvic.c | 42 ++++++++++++++++++++++++++++++++++++++++++
12
1 file changed, 1 insertion(+), 1 deletion(-)
20
1 file changed, 42 insertions(+)
13
21
14
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
22
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
15
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/arm_gicv3_cpuif.c
24
--- a/hw/intc/armv7m_nvic.c
17
+++ b/hw/intc/arm_gicv3_cpuif.c
25
+++ b/hw/intc/armv7m_nvic.c
18
@@ -XXX,XX +XXX,XX @@ static void ich_vmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
26
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
19
/* Enforce "writing BPRs to less than minimum sets them to the minimum"
27
"Aux Fault status registers unimplemented\n");
20
* by reading and writing back the fields.
28
return 0;
21
*/
29
case 0xd40: /* PFR0. */
22
- write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G0));
30
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
23
+ write_vbpr(cs, GICV3_G0, read_vbpr(cs, GICV3_G0));
31
+ goto bad_offset;
24
write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G1));
32
+ }
25
33
return cpu->isar.id_pfr0;
26
gicv3_cpuif_virt_update(cs);
34
case 0xd44: /* PFR1. */
35
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
36
+ goto bad_offset;
37
+ }
38
return cpu->isar.id_pfr1;
39
case 0xd48: /* DFR0. */
40
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
41
+ goto bad_offset;
42
+ }
43
return cpu->isar.id_dfr0;
44
case 0xd4c: /* AFR0. */
45
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
46
+ goto bad_offset;
47
+ }
48
return cpu->id_afr0;
49
case 0xd50: /* MMFR0. */
50
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
51
+ goto bad_offset;
52
+ }
53
return cpu->isar.id_mmfr0;
54
case 0xd54: /* MMFR1. */
55
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
56
+ goto bad_offset;
57
+ }
58
return cpu->isar.id_mmfr1;
59
case 0xd58: /* MMFR2. */
60
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
61
+ goto bad_offset;
62
+ }
63
return cpu->isar.id_mmfr2;
64
case 0xd5c: /* MMFR3. */
65
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
66
+ goto bad_offset;
67
+ }
68
return cpu->isar.id_mmfr3;
69
case 0xd60: /* ISAR0. */
70
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
71
+ goto bad_offset;
72
+ }
73
return cpu->isar.id_isar0;
74
case 0xd64: /* ISAR1. */
75
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
76
+ goto bad_offset;
77
+ }
78
return cpu->isar.id_isar1;
79
case 0xd68: /* ISAR2. */
80
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
81
+ goto bad_offset;
82
+ }
83
return cpu->isar.id_isar2;
84
case 0xd6c: /* ISAR3. */
85
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
86
+ goto bad_offset;
87
+ }
88
return cpu->isar.id_isar3;
89
case 0xd70: /* ISAR4. */
90
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
91
+ goto bad_offset;
92
+ }
93
return cpu->isar.id_isar4;
94
case 0xd74: /* ISAR5. */
95
+ if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
96
+ goto bad_offset;
97
+ }
98
return cpu->isar.id_isar5;
99
case 0xd78: /* CLIDR */
100
return cpu->clidr;
27
--
101
--
28
2.20.1
102
2.20.1
29
103
30
104
diff view generated by jsdifflib
New patch
[PULL 04/18] target/arm: Add ID register values for Cortex-M0
1
Give the Cortex-M0 ID register values corresponding to its
2
implemented behaviour. These will not be guest-visible but will be
3
used to govern the behaviour of QEMU's emulation. We use the same
4
values that the Cortex-M3 does.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20200910173855.4068-5-peter.maydell@linaro.org
9
---
10
target/arm/cpu_tcg.c | 24 ++++++++++++++++++++++++
11
1 file changed, 24 insertions(+)
12
13
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/cpu_tcg.c
16
+++ b/target/arm/cpu_tcg.c
17
@@ -XXX,XX +XXX,XX @@ static void cortex_m0_initfn(Object *obj)
18
set_feature(&cpu->env, ARM_FEATURE_M);
19
20
cpu->midr = 0x410cc200;
21
+
22
+ /*
23
+ * These ID register values are not guest visible, because
24
+ * we do not implement the Main Extension. They must be set
25
+ * to values corresponding to the Cortex-M0's implemented
26
+ * features, because QEMU generally controls its emulation
27
+ * by looking at ID register fields. We use the same values as
28
+ * for the M3.
29
+ */
30
+ cpu->isar.id_pfr0 = 0x00000030;
31
+ cpu->isar.id_pfr1 = 0x00000200;
32
+ cpu->isar.id_dfr0 = 0x00100000;
33
+ cpu->id_afr0 = 0x00000000;
34
+ cpu->isar.id_mmfr0 = 0x00000030;
35
+ cpu->isar.id_mmfr1 = 0x00000000;
36
+ cpu->isar.id_mmfr2 = 0x00000000;
37
+ cpu->isar.id_mmfr3 = 0x00000000;
38
+ cpu->isar.id_isar0 = 0x01141110;
39
+ cpu->isar.id_isar1 = 0x02111000;
40
+ cpu->isar.id_isar2 = 0x21112231;
41
+ cpu->isar.id_isar3 = 0x01111110;
42
+ cpu->isar.id_isar4 = 0x01310102;
43
+ cpu->isar.id_isar5 = 0x00000000;
44
+ cpu->isar.id_isar6 = 0x00000000;
45
}
46
47
static void cortex_m3_initfn(Object *obj)
48
--
49
2.20.1
50
51
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/12] hw/arm/exynos4210: Add DMA support for the Exynos4210
[PULL 05/18] target/arm: Make isar_feature_aa32_fp16_arith() handle M-profile
1
From: Guenter Roeck <linux@roeck-us.net>
1
The M-profile definition of the MVFR1 ID register differs slightly
2
from the A-profile one, and in particular the check for "does the CPU
3
support fp16 arithmetic" is not the same.
2
4
3
QEMU already supports pl330. Instantiate it for Exynos4210.
5
We don't currently implement any M-profile CPUs with fp16 arithmetic,
6
so this is not yet a visible bug, but correcting the logic now
7
disarms this beartrap for when we eventually do.
4
8
5
Relevant part of Linux arch/arm/boot/dts/exynos4.dtsi:
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20200910173855.4068-6-peter.maydell@linaro.org
12
---
13
target/arm/cpu.h | 31 ++++++++++++++++++++++++++-----
14
1 file changed, 26 insertions(+), 5 deletions(-)
6
15
7
/ {
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
8
soc: soc {
9
amba {
10
pdma0: pdma@12680000 {
11
compatible = "arm,pl330", "arm,primecell";
12
reg = <0x12680000 0x1000>;
13
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
14
clocks = <&clock CLK_PDMA0>;
15
clock-names = "apb_pclk";
16
#dma-cells = <1>;
17
#dma-channels = <8>;
18
#dma-requests = <32>;
19
};
20
pdma1: pdma@12690000 {
21
compatible = "arm,pl330", "arm,primecell";
22
reg = <0x12690000 0x1000>;
23
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
24
clocks = <&clock CLK_PDMA1>;
25
clock-names = "apb_pclk";
26
#dma-cells = <1>;
27
#dma-channels = <8>;
28
#dma-requests = <32>;
29
};
30
mdma1: mdma@12850000 {
31
compatible = "arm,pl330", "arm,primecell";
32
reg = <0x12850000 0x1000>;
33
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
34
clocks = <&clock CLK_MDMA>;
35
clock-names = "apb_pclk";
36
#dma-cells = <1>;
37
#dma-channels = <8>;
38
#dma-requests = <1>;
39
};
40
};
41
};
42
};
43
44
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
45
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
46
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
47
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
48
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
49
Message-id: 20190520214342.13709-4-philmd@redhat.com
50
[PMD: Do not set default qdev properties, create the controllers in the SoC
51
rather than the board (Peter Maydell), add dtsi in commit message]
52
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
53
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
54
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
55
---
56
hw/arm/exynos4210.c | 26 ++++++++++++++++++++++++++
57
1 file changed, 26 insertions(+)
58
59
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
60
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
61
--- a/hw/arm/exynos4210.c
18
--- a/target/arm/cpu.h
62
+++ b/hw/arm/exynos4210.c
19
+++ b/target/arm/cpu.h
63
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR4, LSM, 20, 4)
64
/* EHCI */
21
FIELD(ID_MMFR4, CCIDX, 24, 4)
65
#define EXYNOS4210_EHCI_BASE_ADDR 0x12580000
22
FIELD(ID_MMFR4, EVT, 28, 4)
66
23
67
+/* DMA */
24
+FIELD(ID_PFR1, PROGMOD, 0, 4)
68
+#define EXYNOS4210_PL330_BASE0_ADDR 0x12680000
25
+FIELD(ID_PFR1, SECURITY, 4, 4)
69
+#define EXYNOS4210_PL330_BASE1_ADDR 0x12690000
26
+FIELD(ID_PFR1, MPROGMOD, 8, 4)
70
+#define EXYNOS4210_PL330_BASE2_ADDR 0x12850000
27
+FIELD(ID_PFR1, VIRTUALIZATION, 12, 4)
28
+FIELD(ID_PFR1, GENTIMER, 16, 4)
29
+FIELD(ID_PFR1, SEC_FRAC, 20, 4)
30
+FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
31
+FIELD(ID_PFR1, GIC, 28, 4)
71
+
32
+
72
static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
33
FIELD(ID_AA64ISAR0, AES, 4, 4)
73
0x09, 0x00, 0x00, 0x00 };
34
FIELD(ID_AA64ISAR0, SHA1, 8, 4)
74
35
FIELD(ID_AA64ISAR0, SHA2, 12, 4)
75
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu)
36
@@ -XXX,XX +XXX,XX @@ FIELD(MVFR0, FPROUND, 28, 4)
76
return (0x9 << ARM_AFF1_SHIFT) | cpu;
37
38
FIELD(MVFR1, FPFTZ, 0, 4)
39
FIELD(MVFR1, FPDNAN, 4, 4)
40
-FIELD(MVFR1, SIMDLS, 8, 4)
41
-FIELD(MVFR1, SIMDINT, 12, 4)
42
-FIELD(MVFR1, SIMDSP, 16, 4)
43
-FIELD(MVFR1, SIMDHP, 20, 4)
44
+FIELD(MVFR1, SIMDLS, 8, 4) /* A-profile only */
45
+FIELD(MVFR1, SIMDINT, 12, 4) /* A-profile only */
46
+FIELD(MVFR1, SIMDSP, 16, 4) /* A-profile only */
47
+FIELD(MVFR1, SIMDHP, 20, 4) /* A-profile only */
48
+FIELD(MVFR1, MVE, 8, 4) /* M-profile only */
49
+FIELD(MVFR1, FP16, 20, 4) /* M-profile only */
50
FIELD(MVFR1, FPHP, 24, 4)
51
FIELD(MVFR1, SIMDFMAC, 28, 4)
52
53
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
54
return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
77
}
55
}
78
56
79
+static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
57
+static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
80
+{
58
+{
81
+ SysBusDevice *busdev;
59
+ return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
82
+ DeviceState *dev;
83
+
84
+ dev = qdev_create(NULL, "pl330");
85
+ qdev_prop_set_uint8(dev, "num_periph_req", nreq);
86
+ qdev_init_nofail(dev);
87
+ busdev = SYS_BUS_DEVICE(dev);
88
+ sysbus_mmio_map(busdev, 0, base);
89
+ sysbus_connect_irq(busdev, 0, irq);
90
+}
60
+}
91
+
61
+
92
Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
62
static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
93
{
63
{
94
Exynos4210State *s = g_new0(Exynos4210State, 1);
64
- return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3;
95
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
65
+ /* Sadly this is encoded differently for A-profile and M-profile */
96
sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
66
+ if (isar_feature_aa32_mprofile(id)) {
97
s->irq_table[exynos4210_get_irq(28, 3)]);
67
+ return FIELD_EX32(id->mvfr1, MVFR1, FP16) > 0;
98
68
+ } else {
99
+ /*** DMA controllers ***/
69
+ return FIELD_EX32(id->mvfr1, MVFR1, FPHP) >= 3;
100
+ pl330_create(EXYNOS4210_PL330_BASE0_ADDR,
70
+ }
101
+ qemu_irq_invert(s->irq_table[exynos4210_get_irq(35, 1)]), 32);
102
+ pl330_create(EXYNOS4210_PL330_BASE1_ADDR,
103
+ qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
104
+ pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
105
+ qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
106
+
107
return s;
108
}
71
}
72
73
static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id)
109
--
74
--
110
2.20.1
75
2.20.1
111
76
112
77
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/12] target/arm: Simplify BFXIL expansion
[PULL 06/18] target/arm: Fix sve ldr/str
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The mask implied by the extract is redundant with the one
3
The mte update missed a bit when producing clean addresses.
4
implied by the deposit. Also, fix spelling of BFXIL.
5
4
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Fixes: b2aa8879b88
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20190514011129.11330-3-richard.henderson@linaro.org
7
Message-id: 20200916014102.2446323-1-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
target/arm/translate-a64.c | 6 +++---
11
target/arm/translate-sve.c | 4 ++--
12
1 file changed, 3 insertions(+), 3 deletions(-)
12
1 file changed, 2 insertions(+), 2 deletions(-)
13
13
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
16
--- a/target/arm/translate-sve.c
17
+++ b/target/arm/translate-a64.c
17
+++ b/target/arm/translate-sve.c
18
@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
18
@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
19
tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len);
19
for (i = 0; i < len_align; i += 8) {
20
return;
20
tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEQ);
21
tcg_gen_st_i64(t0, cpu_env, vofs + i);
22
- tcg_gen_addi_i64(clean_addr, cpu_reg_sp(s, rn), 8);
23
+ tcg_gen_addi_i64(clean_addr, clean_addr, 8);
21
}
24
}
22
- /* opc == 1, BXFIL fall through to deposit */
25
tcg_temp_free_i64(t0);
23
- tcg_gen_extract_i64(tcg_tmp, tcg_tmp, ri, len);
24
+ /* opc == 1, BFXIL fall through to deposit */
25
+ tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri);
26
pos = 0;
27
} else {
26
} else {
28
/* Handle the ri > si case with a deposit
27
@@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
29
@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
28
for (i = 0; i < len_align; i += 8) {
30
len = ri;
29
tcg_gen_ld_i64(t0, cpu_env, vofs + i);
31
}
30
tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEQ);
32
31
- tcg_gen_addi_i64(clean_addr, cpu_reg_sp(s, rn), 8);
33
- if (opc == 1) { /* BFM, BXFIL */
32
+ tcg_gen_addi_i64(clean_addr, clean_addr, 8);
34
+ if (opc == 1) { /* BFM, BFXIL */
33
}
35
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len);
34
tcg_temp_free_i64(t0);
36
} else {
35
} else {
37
/* SBFM or UBFM: We start with zero, and we haven't modified
38
--
36
--
39
2.20.1
37
2.20.1
40
38
41
39
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/12] target/arm: Use extract2 for EXTR
[PULL 07/18] target/arm: Fix SVE splice
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This is, after all, how we implement extract2 in tcg/aarch64.
3
While converting to gen_gvec_ool_zzzp, we lost passing
4
a->esz as the data argument to the function.
4
5
6
Fixes: 36cbb7a8e71
7
Cc: qemu-stable@nongnu.org
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20200918000500.2690937-1-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20190514011129.11330-2-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
12
---
10
target/arm/translate-a64.c | 38 ++++++++++++++++++++------------------
13
target/arm/translate-sve.c | 2 +-
11
1 file changed, 20 insertions(+), 18 deletions(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
12
15
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
14
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
18
--- a/target/arm/translate-sve.c
16
+++ b/target/arm/translate-a64.c
19
+++ b/target/arm/translate-sve.c
17
@@ -XXX,XX +XXX,XX @@ static void disas_extract(DisasContext *s, uint32_t insn)
20
@@ -XXX,XX +XXX,XX @@ static bool trans_SPLICE(DisasContext *s, arg_rprr_esz *a)
18
} else {
21
{
19
tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));
22
if (sve_access_check(s)) {
20
}
23
gen_gvec_ool_zzzp(s, gen_helper_sve_splice,
21
- } else if (rm == rn) { /* ROR */
24
- a->rd, a->rn, a->rm, a->pg, 0);
22
- tcg_rm = cpu_reg(s, rm);
25
+ a->rd, a->rn, a->rm, a->pg, a->esz);
23
- if (sf) {
24
- tcg_gen_rotri_i64(tcg_rd, tcg_rm, imm);
25
- } else {
26
- TCGv_i32 tmp = tcg_temp_new_i32();
27
- tcg_gen_extrl_i64_i32(tmp, tcg_rm);
28
- tcg_gen_rotri_i32(tmp, tmp, imm);
29
- tcg_gen_extu_i32_i64(tcg_rd, tmp);
30
- tcg_temp_free_i32(tmp);
31
- }
32
} else {
33
- tcg_rm = read_cpu_reg(s, rm, sf);
34
- tcg_rn = read_cpu_reg(s, rn, sf);
35
- tcg_gen_shri_i64(tcg_rm, tcg_rm, imm);
36
- tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm);
37
- tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn);
38
- if (!sf) {
39
- tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
40
+ tcg_rm = cpu_reg(s, rm);
41
+ tcg_rn = cpu_reg(s, rn);
42
+
43
+ if (sf) {
44
+ /* Specialization to ROR happens in EXTRACT2. */
45
+ tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, imm);
46
+ } else {
47
+ TCGv_i32 t0 = tcg_temp_new_i32();
48
+
49
+ tcg_gen_extrl_i64_i32(t0, tcg_rm);
50
+ if (rm == rn) {
51
+ tcg_gen_rotri_i32(t0, t0, imm);
52
+ } else {
53
+ TCGv_i32 t1 = tcg_temp_new_i32();
54
+ tcg_gen_extrl_i64_i32(t1, tcg_rn);
55
+ tcg_gen_extract2_i32(t0, t0, t1, imm);
56
+ tcg_temp_free_i32(t1);
57
+ }
58
+ tcg_gen_extu_i32_i64(tcg_rd, t0);
59
+ tcg_temp_free_i32(t0);
60
}
61
}
62
}
26
}
27
return true;
28
}
63
--
29
--
64
2.20.1
30
2.20.1
65
31
66
32
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/12] target/arm: Fix vector operation segfault
[PULL 08/18] hw/arm/raspi: Define various blocks base addresses
1
From: Alistair Francis <alistair.francis@wdc.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Commit 89e68b575 "target/arm: Use vector operations for saturation"
3
The Raspberry firmware is closed-source. While running it, it
4
causes this abort() when booting QEMU ARM with a Cortex-A15:
4
accesses various I/O registers. Logging these accesses as UNIMP
5
(unimplemented) help to understand what the firmware is doing
6
(ideally we want it able to boot a Linux kernel).
5
7
6
0 0x00007ffff4c2382f in raise () at /usr/lib/libc.so.6
8
Document various blocks we might use later.
7
1 0x00007ffff4c0e672 in abort () at /usr/lib/libc.so.6
8
2 0x00005555559c1839 in disas_neon_data_insn (insn=<optimized out>, s=<optimized out>) at ./target/arm/translate.c:6673
9
3 0x00005555559c1839 in disas_neon_data_insn (s=<optimized out>, insn=<optimized out>) at ./target/arm/translate.c:6386
10
4 0x00005555559cd8a4 in disas_arm_insn (insn=4081107068, s=0x7fffe59a9510) at ./target/arm/translate.c:9289
11
5 0x00005555559cd8a4 in arm_tr_translate_insn (dcbase=0x7fffe59a9510, cpu=<optimized out>) at ./target/arm/translate.c:13612
12
6 0x00005555558d1d39 in translator_loop (ops=0x5555561cc580 <arm_translator_ops>, db=0x7fffe59a9510, cpu=0x55555686a2f0, tb=<optimized out>, max_insns=<optimized out>) at ./accel/tcg/translator.c:96
13
7 0x00005555559d10d4 in gen_intermediate_code (cpu=cpu@entry=0x55555686a2f0, tb=tb@entry=0x7fffd7840080 <code_gen_buffer+126091347>, max_insns=max_insns@entry=512) at ./target/arm/translate.c:13901
14
8 0x00005555558d06b9 in tb_gen_code (cpu=cpu@entry=0x55555686a2f0, pc=3067096216, cs_base=0, flags=192, cflags=-16252928, cflags@entry=524288) at ./accel/tcg/translate-all.c:1736
15
9 0x00005555558ce467 in tb_find (cf_mask=524288, tb_exit=1, last_tb=0x7fffd783e640 <code_gen_buffer+126084627>, cpu=0x1) at ./accel/tcg/cpu-exec.c:407
16
10 0x00005555558ce467 in cpu_exec (cpu=cpu@entry=0x55555686a2f0) at ./accel/tcg/cpu-exec.c:728
17
11 0x000055555588b0cf in tcg_cpu_exec (cpu=0x55555686a2f0) at ./cpus.c:1431
18
12 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=0x55555686a2f0) at ./cpus.c:1735
19
13 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=arg@entry=0x55555686a2f0) at ./cpus.c:1709
20
14 0x0000555555d2629a in qemu_thread_start (args=<optimized out>) at ./util/qemu-thread-posix.c:502
21
15 0x00007ffff4db8a92 in start_thread () at /usr/lib/libpthread.
22
9
23
This patch ensures that we don't hit the abort() in the second switch
24
case in disas_neon_data_insn() as we will return from the first case.
25
26
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
27
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
28
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
29
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
30
Tested-by: Alex Bennée <alex.bennee@linaro.org>
11
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
31
Message-id: ad91b397f360b2fc7f4087e476f7df5b04d42ddb.1558021877.git.alistair.francis@wdc.com
12
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
13
Message-id: 20200921034729.432931-2-f4bug@amsat.org
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
---
15
---
34
target/arm/translate.c | 4 ++--
16
include/hw/arm/raspi_platform.h | 51 +++++++++++++++++++++++++++------
35
1 file changed, 2 insertions(+), 2 deletions(-)
17
1 file changed, 43 insertions(+), 8 deletions(-)
36
18
37
diff --git a/target/arm/translate.c b/target/arm/translate.c
19
diff --git a/include/hw/arm/raspi_platform.h b/include/hw/arm/raspi_platform.h
38
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/translate.c
21
--- a/include/hw/arm/raspi_platform.h
40
+++ b/target/arm/translate.c
22
+++ b/include/hw/arm/raspi_platform.h
41
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
23
@@ -XXX,XX +XXX,XX @@
42
tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
24
* You should have received a copy of the GNU General Public License
43
rn_ofs, rm_ofs, vec_size, vec_size,
25
* along with this program; if not, write to the Free Software
44
(u ? uqadd_op : sqadd_op) + size);
26
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
45
- break;
27
+ *
46
+ return 0;
28
+ * Various undocumented addresses and names come from Herman Hermitage's VC4
47
29
+ * documentation:
48
case NEON_3R_VQSUB:
30
+ * https://github.com/hermanhermitage/videocoreiv/wiki/MMIO-Register-map
49
tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
31
*/
50
rn_ofs, rm_ofs, vec_size, vec_size,
32
51
(u ? uqsub_op : sqsub_op) + size);
33
#ifndef HW_ARM_RASPI_PLATFORM_H
52
- break;
34
#define HW_ARM_RASPI_PLATFORM_H
53
+ return 0;
35
54
36
#define MSYNC_OFFSET 0x0000 /* Multicore Sync Block */
55
case NEON_3R_VMUL: /* VMUL */
37
-#define IC0_OFFSET 0x2000
56
if (u) {
38
+#define CCPT_OFFSET 0x1000 /* Compact Camera Port 2 TX */
39
+#define INTE_OFFSET 0x2000 /* VC Interrupt controller */
40
#define ST_OFFSET 0x3000 /* System Timer */
41
+#define TXP_OFFSET 0x4000 /* Transposer */
42
+#define JPEG_OFFSET 0x5000
43
#define MPHI_OFFSET 0x6000 /* Message-based Parallel Host Intf. */
44
#define DMA_OFFSET 0x7000 /* DMA controller, channels 0-14 */
45
-#define ARM_OFFSET 0xB000 /* BCM2708 ARM control block */
46
+#define ARBA_OFFSET 0x9000
47
+#define BRDG_OFFSET 0xa000
48
+#define ARM_OFFSET 0xB000 /* ARM control block */
49
#define ARMCTRL_OFFSET (ARM_OFFSET + 0x000)
50
#define ARMCTRL_IC_OFFSET (ARM_OFFSET + 0x200) /* Interrupt controller */
51
-#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 */
52
+#define ARMCTRL_TIMER0_1_OFFSET (ARM_OFFSET + 0x400) /* Timer 0 and 1 (SP804) */
53
#define ARMCTRL_0_SBM_OFFSET (ARM_OFFSET + 0x800) /* User 0 (ARM) Semaphores
54
* Doorbells & Mailboxes */
55
#define CPRMAN_OFFSET 0x100000 /* Power Management, Watchdog */
56
@@ -XXX,XX +XXX,XX @@
57
#define AVS_OFFSET 0x103000 /* Audio Video Standard */
58
#define RNG_OFFSET 0x104000
59
#define GPIO_OFFSET 0x200000
60
-#define UART0_OFFSET 0x201000
61
-#define MMCI0_OFFSET 0x202000
62
-#define I2S_OFFSET 0x203000
63
-#define SPI0_OFFSET 0x204000
64
+#define UART0_OFFSET 0x201000 /* PL011 */
65
+#define MMCI0_OFFSET 0x202000 /* Legacy MMC */
66
+#define I2S_OFFSET 0x203000 /* PCM */
67
+#define SPI0_OFFSET 0x204000 /* SPI master */
68
#define BSC0_OFFSET 0x205000 /* BSC0 I2C/TWI */
69
+#define PIXV0_OFFSET 0x206000
70
+#define PIXV1_OFFSET 0x207000
71
+#define DPI_OFFSET 0x208000
72
+#define DSI0_OFFSET 0x209000 /* Display Serial Interface */
73
+#define PWM_OFFSET 0x20c000
74
+#define PERM_OFFSET 0x20d000
75
+#define TEC_OFFSET 0x20e000
76
#define OTP_OFFSET 0x20f000
77
+#define SLIM_OFFSET 0x210000 /* SLIMbus */
78
+#define CPG_OFFSET 0x211000
79
#define THERMAL_OFFSET 0x212000
80
-#define BSC_SL_OFFSET 0x214000 /* SPI slave */
81
+#define AVSP_OFFSET 0x213000
82
+#define BSC_SL_OFFSET 0x214000 /* SPI slave (bootrom) */
83
#define AUX_OFFSET 0x215000 /* AUX: UART1/SPI1/SPI2 */
84
#define EMMC1_OFFSET 0x300000
85
+#define EMMC2_OFFSET 0x340000
86
+#define HVS_OFFSET 0x400000
87
#define SMI_OFFSET 0x600000
88
+#define DSI1_OFFSET 0x700000
89
+#define UCAM_OFFSET 0x800000
90
+#define CMI_OFFSET 0x802000
91
#define BSC1_OFFSET 0x804000 /* BSC1 I2C/TWI */
92
#define BSC2_OFFSET 0x805000 /* BSC2 I2C/TWI */
93
+#define VECA_OFFSET 0x806000
94
+#define PIXV2_OFFSET 0x807000
95
+#define HDMI_OFFSET 0x808000
96
+#define HDCP_OFFSET 0x809000
97
+#define ARBR0_OFFSET 0x80a000
98
#define DBUS_OFFSET 0x900000
99
#define AVE0_OFFSET 0x910000
100
#define USB_OTG_OFFSET 0x980000 /* DTC_OTG USB controller */
101
+#define V3D_OFFSET 0xc00000
102
#define SDRAMC_OFFSET 0xe00000
103
+#define L2CC_OFFSET 0xe01000 /* Level 2 Cache controller */
104
+#define L1CC_OFFSET 0xe02000 /* Level 1 Cache controller */
105
+#define ARBR1_OFFSET 0xe04000
106
#define DMA15_OFFSET 0xE05000 /* DMA controller, channel 15 */
107
+#define DCRC_OFFSET 0xe07000
108
+#define AXIP_OFFSET 0xe08000
109
110
/* GPU interrupts */
111
#define INTERRUPT_TIMER0 0
57
--
112
--
58
2.20.1
113
2.20.1
59
114
60
115
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/12] hw/arm/exynos4: Remove unuseful debug code
[PULL 09/18] hw/arm/bcm2835: Add more unimplemented peripherals
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
3
The bcm2835-v3d is used since Linux 4.7, see commit
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
4
49ac67e0c39c ("ARM: bcm2835: Add VC4 to the device tree"),
5
Message-id: 20190520214342.13709-2-philmd@redhat.com
5
and the bcm2835-txp since Linux 4.19, see commit
6
b7dd29b401f5 ("ARM: dts: bcm283x: Add Transposer block").
7
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
10
Message-id: 20200921034729.432931-3-f4bug@amsat.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
12
---
8
hw/arm/exynos4_boards.c | 24 ------------------------
13
include/hw/arm/bcm2835_peripherals.h | 2 ++
9
1 file changed, 24 deletions(-)
14
hw/arm/bcm2835_peripherals.c | 2 ++
15
2 files changed, 4 insertions(+)
10
16
11
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
17
diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h
12
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/arm/exynos4_boards.c
19
--- a/include/hw/arm/bcm2835_peripherals.h
14
+++ b/hw/arm/exynos4_boards.c
20
+++ b/include/hw/arm/bcm2835_peripherals.h
15
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
16
#include "hw/net/lan9118.h"
22
17
#include "hw/boards.h"
23
BCM2835SystemTimerState systmr;
18
24
BCM2835MphiState mphi;
19
-#undef DEBUG
25
+ UnimplementedDeviceState txp;
20
-
26
UnimplementedDeviceState armtmr;
21
-//#define DEBUG
27
UnimplementedDeviceState cprman;
22
-
28
UnimplementedDeviceState a2w;
23
-#ifdef DEBUG
29
@@ -XXX,XX +XXX,XX @@ struct BCM2835PeripheralState {
24
- #undef PRINT_DEBUG
30
UnimplementedDeviceState otp;
25
- #define PRINT_DEBUG(fmt, args...) \
31
UnimplementedDeviceState dbus;
26
- do { \
32
UnimplementedDeviceState ave0;
27
- fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
33
+ UnimplementedDeviceState v3d;
28
- } while (0)
34
UnimplementedDeviceState bscsl;
29
-#else
35
UnimplementedDeviceState smi;
30
- #define PRINT_DEBUG(fmt, args...) do {} while (0)
36
DWC2State dwc2;
31
-#endif
37
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
32
-
38
index XXXXXXX..XXXXXXX 100644
33
#define SMDK_LAN9118_BASE_ADDR 0x05000000
39
--- a/hw/arm/bcm2835_peripherals.c
34
40
+++ b/hw/arm/bcm2835_peripherals.c
35
typedef enum Exynos4BoardType {
41
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
36
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
42
qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ,
37
exynos4_board_binfo.gic_cpu_if_addr =
43
INTERRUPT_USB));
38
EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100;
44
39
45
+ create_unimp(s, &s->txp, "bcm2835-txp", TXP_OFFSET, 0x1000);
40
- PRINT_DEBUG("\n ram_size: %luMiB [0x%08lx]\n"
46
create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, 0x40);
41
- " kernel_filename: %s\n"
47
create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000);
42
- " kernel_cmdline: %s\n"
48
create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000);
43
- " initrd_filename: %s\n",
49
@@ -XXX,XX +XXX,XX @@ static void bcm2835_peripherals_realize(DeviceState *dev, Error **errp)
44
- exynos4_board_ram_size[board_type] / 1048576,
50
create_unimp(s, &s->otp, "bcm2835-otp", OTP_OFFSET, 0x80);
45
- exynos4_board_ram_size[board_type],
51
create_unimp(s, &s->dbus, "bcm2835-dbus", DBUS_OFFSET, 0x8000);
46
- machine->kernel_filename,
52
create_unimp(s, &s->ave0, "bcm2835-ave0", AVE0_OFFSET, 0x8000);
47
- machine->kernel_cmdline,
53
+ create_unimp(s, &s->v3d, "bcm2835-v3d", V3D_OFFSET, 0x1000);
48
- machine->initrd_filename);
54
create_unimp(s, &s->sdramc, "bcm2835-sdramc", SDRAMC_OFFSET, 0x100);
49
-
55
}
50
exynos4_boards_init_ram(s, get_system_memory(),
51
exynos4_board_ram_size[board_type]);
52
56
53
--
57
--
54
2.20.1
58
2.20.1
55
59
56
60
diff view generated by jsdifflib
New patch
[PULL 10/18] hw/arm/raspi: Remove ignore_memory_transaction_failures on the raspi2
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
Commit 1c3db49d39 added the raspi3, which uses the same peripherals
4
than the raspi2 (but with different ARM cores). The raspi3 was
5
introduced without the ignore_memory_transaction_failures flag.
6
Almost 2 years later, the machine is usable running U-Boot and
7
Linux.
8
In commit 00cbd5bd74 we mapped a lot of unimplemented devices,
9
commit d442d95f added thermal block and commit 0e5bbd7406 the
10
system timer.
11
As we are happy with the raspi3, let's remove this flag on the
12
raspi2.
13
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
16
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Message-id: 20200921034729.432931-4-f4bug@amsat.org
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
hw/arm/raspi.c | 3 ---
21
1 file changed, 3 deletions(-)
22
23
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/arm/raspi.c
26
+++ b/hw/arm/raspi.c
27
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_class_init(ObjectClass *oc, void *data)
28
mc->default_cpus = mc->min_cpus = mc->max_cpus = cores_count(board_rev);
29
mc->default_ram_size = board_ram_size(board_rev);
30
mc->default_ram_id = "ram";
31
- if (board_version(board_rev) == 2) {
32
- mc->ignore_memory_transaction_failures = true;
33
- }
34
};
35
36
static const TypeInfo raspi_machine_types[] = {
37
--
38
2.20.1
39
40
diff view generated by jsdifflib
New patch
[PULL 11/18] hw/arm/raspi: Display the board revision in the machine description
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
Display the board revision in the machine description.
4
5
Before:
6
7
$ qemu-system-aarch64 -M help | fgrep raspi
8
raspi2 Raspberry Pi 2B
9
raspi3 Raspberry Pi 3B
10
11
After:
12
13
raspi2 Raspberry Pi 2B (revision 1.1)
14
raspi3 Raspberry Pi 3B (revision 1.2)
15
16
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
17
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Message-id: 20200924111808.77168-2-f4bug@amsat.org
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
21
hw/arm/raspi.c | 4 +++-
22
1 file changed, 3 insertions(+), 1 deletion(-)
23
24
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/hw/arm/raspi.c
27
+++ b/hw/arm/raspi.c
28
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_class_init(ObjectClass *oc, void *data)
29
uint32_t board_rev = (uint32_t)(uintptr_t)data;
30
31
rmc->board_rev = board_rev;
32
- mc->desc = g_strdup_printf("Raspberry Pi %s", board_type(board_rev));
33
+ mc->desc = g_strdup_printf("Raspberry Pi %s (revision 1.%u)",
34
+ board_type(board_rev),
35
+ FIELD_EX32(board_rev, REV_CODE, REVISION));
36
mc->init = raspi_machine_init;
37
mc->block_default_type = IF_SD;
38
mc->no_parallel = 1;
39
--
40
2.20.1
41
42
diff view generated by jsdifflib
New patch
[PULL 12/18] hw/arm/raspi: Load the firmware on the first core
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
The 'first_cpu' is more a QEMU accelerator-related concept
4
than a variable the machine requires to use.
5
Since the machine is aware of its CPUs, directly use the
6
first one to load the firmware.
7
8
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20200924111808.77168-3-f4bug@amsat.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/arm/raspi.c | 3 ++-
14
1 file changed, 2 insertions(+), 1 deletion(-)
15
16
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/raspi.c
19
+++ b/hw/arm/raspi.c
20
@@ -XXX,XX +XXX,XX @@ static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
21
22
static void setup_boot(MachineState *machine, int version, size_t ram_size)
23
{
24
+ RaspiMachineState *s = RASPI_MACHINE(machine);
25
static struct arm_boot_info binfo;
26
int r;
27
28
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
29
binfo.firmware_loaded = true;
30
}
31
32
- arm_load_kernel(ARM_CPU(first_cpu), machine, &binfo);
33
+ arm_load_kernel(&s->soc.cpu[0].core, machine, &binfo);
34
}
35
36
static void raspi_machine_init(MachineState *machine)
37
--
38
2.20.1
39
40
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/12] hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3
[PULL 13/18] hw/arm/raspi: Move arm_boot_info structure to RaspiMachineState
1
The ICC_CTLR_EL3 register includes some bits which are aliases
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
of bits in the ICC_CTLR_EL1(S) and (NS) registers. QEMU chooses
3
to keep those bits in the cs->icc_ctlr_el1[] struct fields.
4
Unfortunately a missing '~' in the code to update the bits
5
in those fields meant that writing to ICC_CTLR_EL3 would corrupt
6
the ICC_CLTR_EL1 register values.
7
2
3
The arm_boot_info structure belong to the machine,
4
move it to RaspiMachineState.
5
6
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
7
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20200924111808.77168-4-f4bug@amsat.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Message-id: 20190520162809.2677-5-peter.maydell@linaro.org
11
---
10
---
12
hw/intc/arm_gicv3_cpuif.c | 4 ++--
11
hw/arm/raspi.c | 30 +++++++++++++++---------------
13
1 file changed, 2 insertions(+), 2 deletions(-)
12
1 file changed, 15 insertions(+), 15 deletions(-)
14
13
15
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
14
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/intc/arm_gicv3_cpuif.c
16
--- a/hw/arm/raspi.c
18
+++ b/hw/intc/arm_gicv3_cpuif.c
17
+++ b/hw/arm/raspi.c
19
@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
18
@@ -XXX,XX +XXX,XX @@ struct RaspiMachineState {
20
trace_gicv3_icc_ctlr_el3_write(gicv3_redist_affid(cs), value);
19
MachineState parent_obj;
21
20
/*< public >*/
22
/* *_EL1NS and *_EL1S bits are aliases into the ICC_CTLR_EL1 bits. */
21
BCM283XState soc;
23
- cs->icc_ctlr_el1[GICV3_NS] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
22
+ struct arm_boot_info binfo;
24
+ cs->icc_ctlr_el1[GICV3_NS] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
23
};
25
if (value & ICC_CTLR_EL3_EOIMODE_EL1NS) {
24
typedef struct RaspiMachineState RaspiMachineState;
26
cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE;
25
26
@@ -XXX,XX +XXX,XX @@ static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
27
static void setup_boot(MachineState *machine, int version, size_t ram_size)
28
{
29
RaspiMachineState *s = RASPI_MACHINE(machine);
30
- static struct arm_boot_info binfo;
31
int r;
32
33
- binfo.board_id = MACH_TYPE_BCM2708;
34
- binfo.ram_size = ram_size;
35
- binfo.nb_cpus = machine->smp.cpus;
36
+ s->binfo.board_id = MACH_TYPE_BCM2708;
37
+ s->binfo.ram_size = ram_size;
38
+ s->binfo.nb_cpus = machine->smp.cpus;
39
40
if (version <= 2) {
41
/* The rpi1 and 2 require some custom setup code to run in Secure
42
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
43
* firmware for some cache maintenance operations.
44
* The rpi3 doesn't need this.
45
*/
46
- binfo.board_setup_addr = BOARDSETUP_ADDR;
47
- binfo.write_board_setup = write_board_setup;
48
- binfo.secure_board_setup = true;
49
- binfo.secure_boot = true;
50
+ s->binfo.board_setup_addr = BOARDSETUP_ADDR;
51
+ s->binfo.write_board_setup = write_board_setup;
52
+ s->binfo.secure_board_setup = true;
53
+ s->binfo.secure_boot = true;
27
}
54
}
28
@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
55
29
cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_CBPR;
56
/* Pi2 and Pi3 requires SMP setup */
57
if (version >= 2) {
58
- binfo.smp_loader_start = SMPBOOT_ADDR;
59
+ s->binfo.smp_loader_start = SMPBOOT_ADDR;
60
if (version == 2) {
61
- binfo.write_secondary_boot = write_smpboot;
62
+ s->binfo.write_secondary_boot = write_smpboot;
63
} else {
64
- binfo.write_secondary_boot = write_smpboot64;
65
+ s->binfo.write_secondary_boot = write_smpboot64;
66
}
67
- binfo.secondary_cpu_reset_hook = reset_secondary;
68
+ s->binfo.secondary_cpu_reset_hook = reset_secondary;
30
}
69
}
31
70
32
- cs->icc_ctlr_el1[GICV3_S] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
71
/* If the user specified a "firmware" image (e.g. UEFI), we bypass
33
+ cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
72
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
34
if (value & ICC_CTLR_EL3_EOIMODE_EL1S) {
73
exit(1);
35
cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_EOIMODE;
74
}
75
76
- binfo.entry = firmware_addr;
77
- binfo.firmware_loaded = true;
78
+ s->binfo.entry = firmware_addr;
79
+ s->binfo.firmware_loaded = true;
36
}
80
}
81
82
- arm_load_kernel(&s->soc.cpu[0].core, machine, &binfo);
83
+ arm_load_kernel(&s->soc.cpu[0].core, machine, &s->binfo);
84
}
85
86
static void raspi_machine_init(MachineState *machine)
37
--
87
--
38
2.20.1
88
2.20.1
39
89
40
90
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/12] hw/arm/exynos4: Use the IEC binary prefix definitions
[PULL 14/18] hw/arm/raspi: Avoid using TypeInfo::class_data pointer
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
It eases code review, unit is explicit.
3
Using class_data pointer to create a MachineClass is not
4
the recommended way anymore. The correct way is to open-code
5
the MachineClass::fields in the class_init() method.
4
6
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
We can not use TYPE_RASPI_MACHINE::class_base_init() because
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
it is called *before* each machine class_init(), therefore the
7
Message-id: 20190520214342.13709-3-philmd@redhat.com
9
board_rev field is not populated. We have to manually call
10
raspi_machine_class_common_init() for each machine.
11
12
This partly reverts commit a03bde3674e.
13
14
Suggested-by: Igor Mammedov <imammedo@redhat.com>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
17
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Message-id: 20200924111808.77168-5-f4bug@amsat.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
20
---
10
hw/arm/exynos4_boards.c | 5 +++--
21
hw/arm/raspi.c | 34 ++++++++++++++++++++++++----------
11
1 file changed, 3 insertions(+), 2 deletions(-)
22
1 file changed, 24 insertions(+), 10 deletions(-)
12
23
13
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
24
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
14
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/exynos4_boards.c
26
--- a/hw/arm/raspi.c
16
+++ b/hw/arm/exynos4_boards.c
27
+++ b/hw/arm/raspi.c
17
@@ -XXX,XX +XXX,XX @@
28
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_init(MachineState *machine)
18
*/
29
setup_boot(machine, version, machine->ram_size - vcram_size);
19
30
}
20
#include "qemu/osdep.h"
31
21
+#include "qemu/units.h"
32
-static void raspi_machine_class_init(ObjectClass *oc, void *data)
22
#include "qapi/error.h"
33
+static void raspi_machine_class_common_init(MachineClass *mc,
23
#include "qemu/error-report.h"
34
+ uint32_t board_rev)
24
#include "qemu-common.h"
35
{
25
@@ -XXX,XX +XXX,XX @@ static int exynos4_board_smp_bootreg_addr[EXYNOS4_NUM_OF_BOARDS] = {
36
- MachineClass *mc = MACHINE_CLASS(oc);
37
- RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
38
- uint32_t board_rev = (uint32_t)(uintptr_t)data;
39
-
40
- rmc->board_rev = board_rev;
41
mc->desc = g_strdup_printf("Raspberry Pi %s (revision 1.%u)",
42
board_type(board_rev),
43
FIELD_EX32(board_rev, REV_CODE, REVISION));
44
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_class_init(ObjectClass *oc, void *data)
45
mc->default_ram_id = "ram";
26
};
46
};
27
47
28
static unsigned long exynos4_board_ram_size[EXYNOS4_NUM_OF_BOARDS] = {
48
+static void raspi2b_machine_class_init(ObjectClass *oc, void *data)
29
- [EXYNOS4_BOARD_NURI] = 0x40000000,
49
+{
30
- [EXYNOS4_BOARD_SMDKC210] = 0x40000000,
50
+ MachineClass *mc = MACHINE_CLASS(oc);
31
+ [EXYNOS4_BOARD_NURI] = 1 * GiB,
51
+ RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
32
+ [EXYNOS4_BOARD_SMDKC210] = 1 * GiB,
52
+
33
};
53
+ rmc->board_rev = 0xa21041;
34
54
+ raspi_machine_class_common_init(mc, rmc->board_rev);
35
static struct arm_boot_info exynos4_board_binfo = {
55
+};
56
+
57
+#ifdef TARGET_AARCH64
58
+static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
59
+{
60
+ MachineClass *mc = MACHINE_CLASS(oc);
61
+ RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
62
+
63
+ rmc->board_rev = 0xa02082;
64
+ raspi_machine_class_common_init(mc, rmc->board_rev);
65
+};
66
+#endif /* TARGET_AARCH64 */
67
+
68
static const TypeInfo raspi_machine_types[] = {
69
{
70
.name = MACHINE_TYPE_NAME("raspi2"),
71
.parent = TYPE_RASPI_MACHINE,
72
- .class_init = raspi_machine_class_init,
73
- .class_data = (void *)0xa21041,
74
+ .class_init = raspi2b_machine_class_init,
75
#ifdef TARGET_AARCH64
76
}, {
77
.name = MACHINE_TYPE_NAME("raspi3"),
78
.parent = TYPE_RASPI_MACHINE,
79
- .class_init = raspi_machine_class_init,
80
- .class_data = (void *)0xa02082,
81
+ .class_init = raspi3b_machine_class_init,
82
#endif
83
}, {
84
.name = TYPE_RASPI_MACHINE,
36
--
85
--
37
2.20.1
86
2.20.1
38
87
39
88
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/12] arm: Move system_clock_scale to armv7m_systick.h
[PULL 15/18] hw/arm/raspi: Use more specific machine names
1
The system_clock_scale global is used only by the armv7m systick
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
device; move the extern declaration to the armv7m_systick.h header,
3
and expand the comment to explain what it is and that it should
4
ideally be replaced with a different approach.
5
2
3
Now that we can instantiate different machines based on their
4
board_rev register value, we can have various raspi2 and raspi3.
5
6
In commit fc78a990ec103 we corrected the machine description.
7
Correct the machine names too. For backward compatibility, add
8
an alias to the previous generic name.
9
10
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
11
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
12
Message-id: 20200924111808.77168-6-f4bug@amsat.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20190516163857.6430-2-peter.maydell@linaro.org
10
---
14
---
11
include/hw/arm/arm.h | 4 ----
15
hw/arm/raspi.c | 6 ++++--
12
include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++++++++
16
1 file changed, 4 insertions(+), 2 deletions(-)
13
2 files changed, 22 insertions(+), 4 deletions(-)
14
17
15
diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h
18
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
16
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/arm.h
20
--- a/hw/arm/raspi.c
18
+++ b/include/hw/arm/arm.h
21
+++ b/hw/arm/raspi.c
19
@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
22
@@ -XXX,XX +XXX,XX @@ static void raspi2b_machine_class_init(ObjectClass *oc, void *data)
20
const struct arm_boot_info *info,
23
MachineClass *mc = MACHINE_CLASS(oc);
21
hwaddr mvbar_addr);
24
RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
22
25
23
-/* Multiplication factor to convert from system clock ticks to qemu timer
26
+ mc->alias = "raspi2";
24
- ticks. */
27
rmc->board_rev = 0xa21041;
25
-extern int system_clock_scale;
28
raspi_machine_class_common_init(mc, rmc->board_rev);
26
-
29
};
27
#endif /* HW_ARM_H */
30
@@ -XXX,XX +XXX,XX @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
28
diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
31
MachineClass *mc = MACHINE_CLASS(oc);
29
index XXXXXXX..XXXXXXX 100644
32
RaspiMachineClass *rmc = RASPI_MACHINE_CLASS(oc);
30
--- a/include/hw/timer/armv7m_systick.h
33
31
+++ b/include/hw/timer/armv7m_systick.h
34
+ mc->alias = "raspi3";
32
@@ -XXX,XX +XXX,XX @@ typedef struct SysTickState {
35
rmc->board_rev = 0xa02082;
33
qemu_irq irq;
36
raspi_machine_class_common_init(mc, rmc->board_rev);
34
} SysTickState;
37
};
35
38
@@ -XXX,XX +XXX,XX @@ static void raspi3b_machine_class_init(ObjectClass *oc, void *data)
36
+/*
39
37
+ * Multiplication factor to convert from system clock ticks to qemu timer
40
static const TypeInfo raspi_machine_types[] = {
38
+ * ticks. This should be set (by board code, usually) to a value
41
{
39
+ * equal to NANOSECONDS_PER_SECOND / frq, where frq is the clock frequency
42
- .name = MACHINE_TYPE_NAME("raspi2"),
40
+ * in Hz of the CPU.
43
+ .name = MACHINE_TYPE_NAME("raspi2b"),
41
+ *
44
.parent = TYPE_RASPI_MACHINE,
42
+ * This value is used by the systick device when it is running in
45
.class_init = raspi2b_machine_class_init,
43
+ * its "use the CPU clock" mode (ie when SYST_CSR.CLKSOURCE == 1) to
46
#ifdef TARGET_AARCH64
44
+ * set how fast the timer should tick.
47
}, {
45
+ *
48
- .name = MACHINE_TYPE_NAME("raspi3"),
46
+ * TODO: we should refactor this so that rather than using a global
49
+ .name = MACHINE_TYPE_NAME("raspi3b"),
47
+ * we use a device property or something similar. This is complicated
50
.parent = TYPE_RASPI_MACHINE,
48
+ * because (a) the property would need to be plumbed through from the
51
.class_init = raspi3b_machine_class_init,
49
+ * board code down through various layers to the systick device
50
+ * and (b) the property needs to be modifiable after realize, because
51
+ * the stellaris board uses this to implement the behaviour where the
52
+ * guest can reprogram the PLL registers to downclock the CPU, and the
53
+ * systick device needs to react accordingly. Possibly this should
54
+ * be deferred until we have a good API for modelling clock trees.
55
+ */
56
+extern int system_clock_scale;
57
+
58
#endif
52
#endif
59
--
53
--
60
2.20.1
54
2.20.1
61
55
62
56
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/12] hw/arm/exynos4210: QOM'ify the Exynos4210 SoC
[PULL 16/18] hw/arm/raspi: Introduce RaspiProcessorId enum
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
3
As we only support a reduced set of the REV_CODE_PROCESSOR id
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
4
encoded in the board revision, define the PROCESSOR_ID values
5
Message-id: 20190520214342.13709-5-philmd@redhat.com
5
as an enum. We can simplify the board_soc_type and cores_count
6
methods.
7
8
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
9
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20200924111808.77168-7-f4bug@amsat.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
12
---
8
include/hw/arm/exynos4210.h | 9 +++++++--
13
hw/arm/raspi.c | 45 +++++++++++++++++++++------------------------
9
hw/arm/exynos4210.c | 28 ++++++++++++++++++++++++----
14
1 file changed, 21 insertions(+), 24 deletions(-)
10
hw/arm/exynos4_boards.c | 9 ++++++---
11
3 files changed, 37 insertions(+), 9 deletions(-)
12
15
13
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
16
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
14
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/arm/exynos4210.h
18
--- a/hw/arm/raspi.c
16
+++ b/include/hw/arm/exynos4210.h
19
+++ b/hw/arm/raspi.c
17
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210Irq {
20
@@ -XXX,XX +XXX,XX @@ FIELD(REV_CODE, MANUFACTURER, 16, 4);
18
} Exynos4210Irq;
21
FIELD(REV_CODE, MEMORY_SIZE, 20, 3);
19
22
FIELD(REV_CODE, STYLE, 23, 1);
20
typedef struct Exynos4210State {
23
21
+ /*< private >*/
24
+typedef enum RaspiProcessorId {
22
+ SysBusDevice parent_obj;
25
+ PROCESSOR_ID_BCM2836 = 1,
23
+ /*< public >*/
26
+ PROCESSOR_ID_BCM2837 = 2,
24
ARMCPU *cpu[EXYNOS4210_NCPUS];
27
+} RaspiProcessorId;
25
Exynos4210Irq irqs;
26
qemu_irq *irq_table;
27
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210State {
28
I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
29
} Exynos4210State;
30
31
+#define TYPE_EXYNOS4210_SOC "exynos4210"
32
+#define EXYNOS4210_SOC(obj) \
33
+ OBJECT_CHECK(Exynos4210State, obj, TYPE_EXYNOS4210_SOC)
34
+
28
+
35
void exynos4210_write_secondary(ARMCPU *cpu,
29
+static const struct {
36
const struct arm_boot_info *info);
30
+ const char *type;
37
31
+ int cores_count;
38
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem);
32
+} soc_property[] = {
39
-
33
+ [PROCESSOR_ID_BCM2836] = {TYPE_BCM2836, BCM283X_NCPUS},
40
/* Initialize exynos4210 IRQ subsystem stub */
34
+ [PROCESSOR_ID_BCM2837] = {TYPE_BCM2837, BCM283X_NCPUS},
41
qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
42
43
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/arm/exynos4210.c
46
+++ b/hw/arm/exynos4210.c
47
@@ -XXX,XX +XXX,XX @@ static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
48
sysbus_connect_irq(busdev, 0, irq);
49
}
50
51
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
52
+static void exynos4210_realize(DeviceState *socdev, Error **errp)
53
{
54
- Exynos4210State *s = g_new0(Exynos4210State, 1);
55
+ Exynos4210State *s = EXYNOS4210_SOC(socdev);
56
+ MemoryRegion *system_mem = get_system_memory();
57
qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
58
SysBusDevice *busdev;
59
DeviceState *dev;
60
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
61
qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
62
pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
63
qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
64
-
65
- return s;
66
}
67
+
68
+static void exynos4210_class_init(ObjectClass *klass, void *data)
69
+{
70
+ DeviceClass *dc = DEVICE_CLASS(klass);
71
+
72
+ dc->realize = exynos4210_realize;
73
+}
74
+
75
+static const TypeInfo exynos4210_info = {
76
+ .name = TYPE_EXYNOS4210_SOC,
77
+ .parent = TYPE_SYS_BUS_DEVICE,
78
+ .instance_size = sizeof(Exynos4210State),
79
+ .class_init = exynos4210_class_init,
80
+};
35
+};
81
+
36
+
82
+static void exynos4210_register_types(void)
37
static uint64_t board_ram_size(uint32_t board_rev)
83
+{
38
{
84
+ type_register_static(&exynos4210_info);
39
assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */
85
+}
40
return 256 * MiB << FIELD_EX32(board_rev, REV_CODE, MEMORY_SIZE);
41
}
42
43
-static int board_processor_id(uint32_t board_rev)
44
+static RaspiProcessorId board_processor_id(uint32_t board_rev)
45
{
46
+ int proc_id = FIELD_EX32(board_rev, REV_CODE, PROCESSOR);
86
+
47
+
87
+type_init(exynos4210_register_types)
48
assert(FIELD_EX32(board_rev, REV_CODE, STYLE)); /* Only new style */
88
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
49
- return FIELD_EX32(board_rev, REV_CODE, PROCESSOR);
89
index XXXXXXX..XXXXXXX 100644
50
+ assert(proc_id < ARRAY_SIZE(soc_property) && soc_property[proc_id].type);
90
--- a/hw/arm/exynos4_boards.c
51
+
91
+++ b/hw/arm/exynos4_boards.c
52
+ return proc_id;
92
@@ -XXX,XX +XXX,XX @@ typedef enum Exynos4BoardType {
93
} Exynos4BoardType;
94
95
typedef struct Exynos4BoardState {
96
- Exynos4210State *soc;
97
+ Exynos4210State soc;
98
MemoryRegion dram0_mem;
99
MemoryRegion dram1_mem;
100
} Exynos4BoardState;
101
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
102
exynos4_boards_init_ram(s, get_system_memory(),
103
exynos4_board_ram_size[board_type]);
104
105
- s->soc = exynos4210_init(get_system_memory());
106
+ object_initialize(&s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC);
107
+ qdev_set_parent_bus(DEVICE(&s->soc), sysbus_get_default());
108
+ object_property_set_bool(OBJECT(&s->soc), true, "realized",
109
+ &error_fatal);
110
111
return s;
112
}
53
}
113
@@ -XXX,XX +XXX,XX @@ static void smdkc210_init(MachineState *machine)
54
114
EXYNOS4_BOARD_SMDKC210);
55
static int board_version(uint32_t board_rev)
115
56
@@ -XXX,XX +XXX,XX @@ static int board_version(uint32_t board_rev)
116
lan9215_init(SMDK_LAN9118_BASE_ADDR,
57
117
- qemu_irq_invert(s->soc->irq_table[exynos4210_get_irq(37, 1)]));
58
static const char *board_soc_type(uint32_t board_rev)
118
+ qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)]));
59
{
119
arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo);
60
- static const char *soc_types[] = {
61
- NULL, TYPE_BCM2836, TYPE_BCM2837,
62
- };
63
- int proc_id = board_processor_id(board_rev);
64
-
65
- if (proc_id >= ARRAY_SIZE(soc_types) || !soc_types[proc_id]) {
66
- error_report("Unsupported processor id '%d' (board revision: 0x%x)",
67
- proc_id, board_rev);
68
- exit(1);
69
- }
70
- return soc_types[proc_id];
71
+ return soc_property[board_processor_id(board_rev)].type;
120
}
72
}
121
73
74
static int cores_count(uint32_t board_rev)
75
{
76
- static const int soc_cores_count[] = {
77
- 0, BCM283X_NCPUS, BCM283X_NCPUS,
78
- };
79
- int proc_id = board_processor_id(board_rev);
80
-
81
- if (proc_id >= ARRAY_SIZE(soc_cores_count) || !soc_cores_count[proc_id]) {
82
- error_report("Unsupported processor id '%d' (board revision: 0x%x)",
83
- proc_id, board_rev);
84
- exit(1);
85
- }
86
- return soc_cores_count[proc_id];
87
+ return soc_property[board_processor_id(board_rev)].cores_count;
88
}
89
90
static const char *board_type(uint32_t board_rev)
122
--
91
--
123
2.20.1
92
2.20.1
124
93
125
94
diff view generated by jsdifflib
New patch
[PULL 17/18] hw/arm/raspi: Use RaspiProcessorId to set the firmware load address
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
2
3
The firmware load address depends on the SoC ("processor id") used,
4
not on the version of the board.
5
6
Suggested-by: Luc Michel <luc.michel@greensocs.com>
7
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
8
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20200924111808.77168-8-f4bug@amsat.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/raspi.c | 3 ++-
13
1 file changed, 2 insertions(+), 1 deletion(-)
14
15
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/raspi.c
18
+++ b/hw/arm/raspi.c
19
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
20
* the normal Linux boot process
21
*/
22
if (machine->firmware) {
23
- hwaddr firmware_addr = version == 3 ? FIRMWARE_ADDR_3 : FIRMWARE_ADDR_2;
24
+ hwaddr firmware_addr = processor_id <= PROCESSOR_ID_BCM2836
25
+ ? FIRMWARE_ADDR_2 : FIRMWARE_ADDR_3;
26
/* load the firmware image (typically kernel.img) */
27
r = load_image_targphys(machine->firmware, firmware_addr,
28
ram_size - firmware_addr);
29
--
30
2.20.1
31
32
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/12] arm: Rename hw/arm/arm.h to hw/arm/boot.h
[PULL 18/18] hw/arm/raspi: Remove use of the 'version' value in the board code
1
The header file hw/arm/arm.h now includes only declarations
1
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
relating to hw/arm/boot.c functionality. Rename it accordingly,
3
and adjust its header comment.
4
2
5
The bulk of this commit was created via
3
We expected the 'version' ID to match the board processor ID,
6
perl -pi -e 's|hw/arm/arm.h|hw/arm/boot.h|' hw/arm/*.c include/hw/arm/*.h
4
but this is not always true (for example boards with revision
5
id 0xa02042/0xa22042 are Raspberry Pi 2 with a BCM2837 SoC).
6
This was not important because we were not modelling them, but
7
since the recent refactor now allow to model these boards, it
8
is safer to check the processor id directly. Remove the version
9
check.
7
10
8
In a few cases we can just delete the #include:
11
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
9
hw/arm/msf2-soc.c, include/hw/arm/aspeed_soc.h and
12
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
10
include/hw/arm/bcm2836.h did not require it.
13
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20200924111808.77168-9-f4bug@amsat.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/arm/raspi.c | 29 +++++++++++++----------------
18
1 file changed, 13 insertions(+), 16 deletions(-)
11
19
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Message-id: 20190516163857.6430-4-peter.maydell@linaro.org
16
---
17
include/hw/arm/allwinner-a10.h | 2 +-
18
include/hw/arm/aspeed_soc.h | 1 -
19
include/hw/arm/bcm2836.h | 1 -
20
include/hw/arm/{arm.h => boot.h} | 8 ++++----
21
include/hw/arm/fsl-imx25.h | 2 +-
22
include/hw/arm/fsl-imx31.h | 2 +-
23
include/hw/arm/fsl-imx6.h | 2 +-
24
include/hw/arm/fsl-imx6ul.h | 2 +-
25
include/hw/arm/fsl-imx7.h | 2 +-
26
include/hw/arm/virt.h | 2 +-
27
include/hw/arm/xlnx-versal.h | 2 +-
28
include/hw/arm/xlnx-zynqmp.h | 2 +-
29
hw/arm/armsse.c | 2 +-
30
hw/arm/armv7m.c | 2 +-
31
hw/arm/aspeed.c | 2 +-
32
hw/arm/boot.c | 2 +-
33
hw/arm/collie.c | 2 +-
34
hw/arm/exynos4210.c | 2 +-
35
hw/arm/exynos4_boards.c | 2 +-
36
hw/arm/highbank.c | 2 +-
37
hw/arm/integratorcp.c | 2 +-
38
hw/arm/mainstone.c | 2 +-
39
hw/arm/microbit.c | 2 +-
40
hw/arm/mps2-tz.c | 2 +-
41
hw/arm/mps2.c | 2 +-
42
hw/arm/msf2-soc.c | 1 -
43
hw/arm/msf2-som.c | 2 +-
44
hw/arm/musca.c | 2 +-
45
hw/arm/musicpal.c | 2 +-
46
hw/arm/netduino2.c | 2 +-
47
hw/arm/nrf51_soc.c | 2 +-
48
hw/arm/nseries.c | 2 +-
49
hw/arm/omap1.c | 2 +-
50
hw/arm/omap2.c | 2 +-
51
hw/arm/omap_sx1.c | 2 +-
52
hw/arm/palm.c | 2 +-
53
hw/arm/raspi.c | 2 +-
54
hw/arm/realview.c | 2 +-
55
hw/arm/spitz.c | 2 +-
56
hw/arm/stellaris.c | 2 +-
57
hw/arm/stm32f205_soc.c | 2 +-
58
hw/arm/strongarm.c | 2 +-
59
hw/arm/tosa.c | 2 +-
60
hw/arm/versatilepb.c | 2 +-
61
hw/arm/vexpress.c | 2 +-
62
hw/arm/virt.c | 2 +-
63
hw/arm/xilinx_zynq.c | 2 +-
64
hw/arm/xlnx-versal.c | 2 +-
65
hw/arm/z2.c | 2 +-
66
49 files changed, 49 insertions(+), 52 deletions(-)
67
rename include/hw/arm/{arm.h => boot.h} (98%)
68
69
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
70
index XXXXXXX..XXXXXXX 100644
71
--- a/include/hw/arm/allwinner-a10.h
72
+++ b/include/hw/arm/allwinner-a10.h
73
@@ -XXX,XX +XXX,XX @@
74
#include "qemu-common.h"
75
#include "qemu/error-report.h"
76
#include "hw/char/serial.h"
77
-#include "hw/arm/arm.h"
78
+#include "hw/arm/boot.h"
79
#include "hw/timer/allwinner-a10-pit.h"
80
#include "hw/intc/allwinner-a10-pic.h"
81
#include "hw/net/allwinner_emac.h"
82
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
83
index XXXXXXX..XXXXXXX 100644
84
--- a/include/hw/arm/aspeed_soc.h
85
+++ b/include/hw/arm/aspeed_soc.h
86
@@ -XXX,XX +XXX,XX @@
87
#ifndef ASPEED_SOC_H
88
#define ASPEED_SOC_H
89
90
-#include "hw/arm/arm.h"
91
#include "hw/intc/aspeed_vic.h"
92
#include "hw/misc/aspeed_scu.h"
93
#include "hw/misc/aspeed_sdmc.h"
94
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
95
index XXXXXXX..XXXXXXX 100644
96
--- a/include/hw/arm/bcm2836.h
97
+++ b/include/hw/arm/bcm2836.h
98
@@ -XXX,XX +XXX,XX @@
99
#ifndef BCM2836_H
100
#define BCM2836_H
101
102
-#include "hw/arm/arm.h"
103
#include "hw/arm/bcm2835_peripherals.h"
104
#include "hw/intc/bcm2836_control.h"
105
106
diff --git a/include/hw/arm/arm.h b/include/hw/arm/boot.h
107
similarity index 98%
108
rename from include/hw/arm/arm.h
109
rename to include/hw/arm/boot.h
110
index XXXXXXX..XXXXXXX 100644
111
--- a/include/hw/arm/arm.h
112
+++ b/include/hw/arm/boot.h
113
@@ -XXX,XX +XXX,XX @@
114
/*
115
- * Misc ARM declarations
116
+ * ARM kernel loader.
117
*
118
* Copyright (c) 2006 CodeSourcery.
119
* Written by Paul Brook
120
@@ -XXX,XX +XXX,XX @@
121
*
122
*/
123
124
-#ifndef HW_ARM_H
125
-#define HW_ARM_H
126
+#ifndef HW_ARM_BOOT_H
127
+#define HW_ARM_BOOT_H
128
129
#include "exec/memory.h"
130
#include "target/arm/cpu-qom.h"
131
@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
132
const struct arm_boot_info *info,
133
hwaddr mvbar_addr);
134
135
-#endif /* HW_ARM_H */
136
+#endif /* HW_ARM_BOOT_H */
137
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
138
index XXXXXXX..XXXXXXX 100644
139
--- a/include/hw/arm/fsl-imx25.h
140
+++ b/include/hw/arm/fsl-imx25.h
141
@@ -XXX,XX +XXX,XX @@
142
#ifndef FSL_IMX25_H
143
#define FSL_IMX25_H
144
145
-#include "hw/arm/arm.h"
146
+#include "hw/arm/boot.h"
147
#include "hw/intc/imx_avic.h"
148
#include "hw/misc/imx25_ccm.h"
149
#include "hw/char/imx_serial.h"
150
diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h
151
index XXXXXXX..XXXXXXX 100644
152
--- a/include/hw/arm/fsl-imx31.h
153
+++ b/include/hw/arm/fsl-imx31.h
154
@@ -XXX,XX +XXX,XX @@
155
#ifndef FSL_IMX31_H
156
#define FSL_IMX31_H
157
158
-#include "hw/arm/arm.h"
159
+#include "hw/arm/boot.h"
160
#include "hw/intc/imx_avic.h"
161
#include "hw/misc/imx31_ccm.h"
162
#include "hw/char/imx_serial.h"
163
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
164
index XXXXXXX..XXXXXXX 100644
165
--- a/include/hw/arm/fsl-imx6.h
166
+++ b/include/hw/arm/fsl-imx6.h
167
@@ -XXX,XX +XXX,XX @@
168
#ifndef FSL_IMX6_H
169
#define FSL_IMX6_H
170
171
-#include "hw/arm/arm.h"
172
+#include "hw/arm/boot.h"
173
#include "hw/cpu/a9mpcore.h"
174
#include "hw/misc/imx6_ccm.h"
175
#include "hw/misc/imx6_src.h"
176
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
177
index XXXXXXX..XXXXXXX 100644
178
--- a/include/hw/arm/fsl-imx6ul.h
179
+++ b/include/hw/arm/fsl-imx6ul.h
180
@@ -XXX,XX +XXX,XX @@
181
#ifndef FSL_IMX6UL_H
182
#define FSL_IMX6UL_H
183
184
-#include "hw/arm/arm.h"
185
+#include "hw/arm/boot.h"
186
#include "hw/cpu/a15mpcore.h"
187
#include "hw/misc/imx6ul_ccm.h"
188
#include "hw/misc/imx6_src.h"
189
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
190
index XXXXXXX..XXXXXXX 100644
191
--- a/include/hw/arm/fsl-imx7.h
192
+++ b/include/hw/arm/fsl-imx7.h
193
@@ -XXX,XX +XXX,XX @@
194
#ifndef FSL_IMX7_H
195
#define FSL_IMX7_H
196
197
-#include "hw/arm/arm.h"
198
+#include "hw/arm/boot.h"
199
#include "hw/cpu/a15mpcore.h"
200
#include "hw/intc/imx_gpcv2.h"
201
#include "hw/misc/imx7_ccm.h"
202
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
203
index XXXXXXX..XXXXXXX 100644
204
--- a/include/hw/arm/virt.h
205
+++ b/include/hw/arm/virt.h
206
@@ -XXX,XX +XXX,XX @@
207
#include "exec/hwaddr.h"
208
#include "qemu/notify.h"
209
#include "hw/boards.h"
210
-#include "hw/arm/arm.h"
211
+#include "hw/arm/boot.h"
212
#include "hw/block/flash.h"
213
#include "sysemu/kvm.h"
214
#include "hw/intc/arm_gicv3_common.h"
215
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
216
index XXXXXXX..XXXXXXX 100644
217
--- a/include/hw/arm/xlnx-versal.h
218
+++ b/include/hw/arm/xlnx-versal.h
219
@@ -XXX,XX +XXX,XX @@
220
#define XLNX_VERSAL_H
221
222
#include "hw/sysbus.h"
223
-#include "hw/arm/arm.h"
224
+#include "hw/arm/boot.h"
225
#include "hw/intc/arm_gicv3.h"
226
227
#define TYPE_XLNX_VERSAL "xlnx-versal"
228
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
229
index XXXXXXX..XXXXXXX 100644
230
--- a/include/hw/arm/xlnx-zynqmp.h
231
+++ b/include/hw/arm/xlnx-zynqmp.h
232
@@ -XXX,XX +XXX,XX @@
233
#ifndef XLNX_ZYNQMP_H
234
235
#include "qemu-common.h"
236
-#include "hw/arm/arm.h"
237
+#include "hw/arm/boot.h"
238
#include "hw/intc/arm_gic.h"
239
#include "hw/net/cadence_gem.h"
240
#include "hw/char/cadence_uart.h"
241
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
242
index XXXXXXX..XXXXXXX 100644
243
--- a/hw/arm/armsse.c
244
+++ b/hw/arm/armsse.c
245
@@ -XXX,XX +XXX,XX @@
246
#include "hw/sysbus.h"
247
#include "hw/registerfields.h"
248
#include "hw/arm/armsse.h"
249
-#include "hw/arm/arm.h"
250
+#include "hw/arm/boot.h"
251
252
/* Format of the System Information block SYS_CONFIG register */
253
typedef enum SysConfigFormat {
254
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
255
index XXXXXXX..XXXXXXX 100644
256
--- a/hw/arm/armv7m.c
257
+++ b/hw/arm/armv7m.c
258
@@ -XXX,XX +XXX,XX @@
259
#include "qemu-common.h"
260
#include "cpu.h"
261
#include "hw/sysbus.h"
262
-#include "hw/arm/arm.h"
263
+#include "hw/arm/boot.h"
264
#include "hw/loader.h"
265
#include "elf.h"
266
#include "sysemu/qtest.h"
267
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
268
index XXXXXXX..XXXXXXX 100644
269
--- a/hw/arm/aspeed.c
270
+++ b/hw/arm/aspeed.c
271
@@ -XXX,XX +XXX,XX @@
272
#include "qemu-common.h"
273
#include "cpu.h"
274
#include "exec/address-spaces.h"
275
-#include "hw/arm/arm.h"
276
+#include "hw/arm/boot.h"
277
#include "hw/arm/aspeed.h"
278
#include "hw/arm/aspeed_soc.h"
279
#include "hw/boards.h"
280
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
281
index XXXXXXX..XXXXXXX 100644
282
--- a/hw/arm/boot.c
283
+++ b/hw/arm/boot.c
284
@@ -XXX,XX +XXX,XX @@
285
#include "qapi/error.h"
286
#include <libfdt.h>
287
#include "hw/hw.h"
288
-#include "hw/arm/arm.h"
289
+#include "hw/arm/boot.h"
290
#include "hw/arm/linux-boot-if.h"
291
#include "sysemu/kvm.h"
292
#include "sysemu/sysemu.h"
293
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
294
index XXXXXXX..XXXXXXX 100644
295
--- a/hw/arm/collie.c
296
+++ b/hw/arm/collie.c
297
@@ -XXX,XX +XXX,XX @@
298
#include "hw/sysbus.h"
299
#include "hw/boards.h"
300
#include "strongarm.h"
301
-#include "hw/arm/arm.h"
302
+#include "hw/arm/boot.h"
303
#include "hw/block/flash.h"
304
#include "exec/address-spaces.h"
305
#include "cpu.h"
306
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
307
index XXXXXXX..XXXXXXX 100644
308
--- a/hw/arm/exynos4210.c
309
+++ b/hw/arm/exynos4210.c
310
@@ -XXX,XX +XXX,XX @@
311
#include "hw/boards.h"
312
#include "sysemu/sysemu.h"
313
#include "hw/sysbus.h"
314
-#include "hw/arm/arm.h"
315
+#include "hw/arm/boot.h"
316
#include "hw/loader.h"
317
#include "hw/arm/exynos4210.h"
318
#include "hw/sd/sdhci.h"
319
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
320
index XXXXXXX..XXXXXXX 100644
321
--- a/hw/arm/exynos4_boards.c
322
+++ b/hw/arm/exynos4_boards.c
323
@@ -XXX,XX +XXX,XX @@
324
#include "sysemu/sysemu.h"
325
#include "hw/sysbus.h"
326
#include "net/net.h"
327
-#include "hw/arm/arm.h"
328
+#include "hw/arm/boot.h"
329
#include "exec/address-spaces.h"
330
#include "hw/arm/exynos4210.h"
331
#include "hw/net/lan9118.h"
332
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
333
index XXXXXXX..XXXXXXX 100644
334
--- a/hw/arm/highbank.c
335
+++ b/hw/arm/highbank.c
336
@@ -XXX,XX +XXX,XX @@
337
#include "qemu/osdep.h"
338
#include "qapi/error.h"
339
#include "hw/sysbus.h"
340
-#include "hw/arm/arm.h"
341
+#include "hw/arm/boot.h"
342
#include "hw/loader.h"
343
#include "net/net.h"
344
#include "sysemu/kvm.h"
345
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
346
index XXXXXXX..XXXXXXX 100644
347
--- a/hw/arm/integratorcp.c
348
+++ b/hw/arm/integratorcp.c
349
@@ -XXX,XX +XXX,XX @@
350
#include "cpu.h"
351
#include "hw/sysbus.h"
352
#include "hw/boards.h"
353
-#include "hw/arm/arm.h"
354
+#include "hw/arm/boot.h"
355
#include "hw/misc/arm_integrator_debug.h"
356
#include "hw/net/smc91c111.h"
357
#include "net/net.h"
358
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
359
index XXXXXXX..XXXXXXX 100644
360
--- a/hw/arm/mainstone.c
361
+++ b/hw/arm/mainstone.c
362
@@ -XXX,XX +XXX,XX @@
363
#include "qapi/error.h"
364
#include "hw/hw.h"
365
#include "hw/arm/pxa.h"
366
-#include "hw/arm/arm.h"
367
+#include "hw/arm/boot.h"
368
#include "net/net.h"
369
#include "hw/net/smc91c111.h"
370
#include "hw/boards.h"
371
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
372
index XXXXXXX..XXXXXXX 100644
373
--- a/hw/arm/microbit.c
374
+++ b/hw/arm/microbit.c
375
@@ -XXX,XX +XXX,XX @@
376
#include "qemu/osdep.h"
377
#include "qapi/error.h"
378
#include "hw/boards.h"
379
-#include "hw/arm/arm.h"
380
+#include "hw/arm/boot.h"
381
#include "sysemu/sysemu.h"
382
#include "exec/address-spaces.h"
383
384
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
385
index XXXXXXX..XXXXXXX 100644
386
--- a/hw/arm/mps2-tz.c
387
+++ b/hw/arm/mps2-tz.c
388
@@ -XXX,XX +XXX,XX @@
389
#include "qemu/osdep.h"
390
#include "qapi/error.h"
391
#include "qemu/error-report.h"
392
-#include "hw/arm/arm.h"
393
+#include "hw/arm/boot.h"
394
#include "hw/arm/armv7m.h"
395
#include "hw/or-irq.h"
396
#include "hw/boards.h"
397
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
398
index XXXXXXX..XXXXXXX 100644
399
--- a/hw/arm/mps2.c
400
+++ b/hw/arm/mps2.c
401
@@ -XXX,XX +XXX,XX @@
402
#include "qemu/osdep.h"
403
#include "qapi/error.h"
404
#include "qemu/error-report.h"
405
-#include "hw/arm/arm.h"
406
+#include "hw/arm/boot.h"
407
#include "hw/arm/armv7m.h"
408
#include "hw/or-irq.h"
409
#include "hw/boards.h"
410
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
411
index XXXXXXX..XXXXXXX 100644
412
--- a/hw/arm/msf2-soc.c
413
+++ b/hw/arm/msf2-soc.c
414
@@ -XXX,XX +XXX,XX @@
415
#include "qemu/units.h"
416
#include "qapi/error.h"
417
#include "qemu-common.h"
418
-#include "hw/arm/arm.h"
419
#include "exec/address-spaces.h"
420
#include "hw/char/serial.h"
421
#include "hw/boards.h"
422
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
423
index XXXXXXX..XXXXXXX 100644
424
--- a/hw/arm/msf2-som.c
425
+++ b/hw/arm/msf2-som.c
426
@@ -XXX,XX +XXX,XX @@
427
#include "qapi/error.h"
428
#include "qemu/error-report.h"
429
#include "hw/boards.h"
430
-#include "hw/arm/arm.h"
431
+#include "hw/arm/boot.h"
432
#include "exec/address-spaces.h"
433
#include "hw/arm/msf2-soc.h"
434
#include "cpu.h"
435
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
436
index XXXXXXX..XXXXXXX 100644
437
--- a/hw/arm/musca.c
438
+++ b/hw/arm/musca.c
439
@@ -XXX,XX +XXX,XX @@
440
#include "qapi/error.h"
441
#include "exec/address-spaces.h"
442
#include "sysemu/sysemu.h"
443
-#include "hw/arm/arm.h"
444
+#include "hw/arm/boot.h"
445
#include "hw/arm/armsse.h"
446
#include "hw/boards.h"
447
#include "hw/char/pl011.h"
448
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
449
index XXXXXXX..XXXXXXX 100644
450
--- a/hw/arm/musicpal.c
451
+++ b/hw/arm/musicpal.c
452
@@ -XXX,XX +XXX,XX @@
453
#include "qemu-common.h"
454
#include "cpu.h"
455
#include "hw/sysbus.h"
456
-#include "hw/arm/arm.h"
457
+#include "hw/arm/boot.h"
458
#include "net/net.h"
459
#include "sysemu/sysemu.h"
460
#include "hw/boards.h"
461
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
462
index XXXXXXX..XXXXXXX 100644
463
--- a/hw/arm/netduino2.c
464
+++ b/hw/arm/netduino2.c
465
@@ -XXX,XX +XXX,XX @@
466
#include "hw/boards.h"
467
#include "qemu/error-report.h"
468
#include "hw/arm/stm32f205_soc.h"
469
-#include "hw/arm/arm.h"
470
+#include "hw/arm/boot.h"
471
472
static void netduino2_init(MachineState *machine)
473
{
474
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
475
index XXXXXXX..XXXXXXX 100644
476
--- a/hw/arm/nrf51_soc.c
477
+++ b/hw/arm/nrf51_soc.c
478
@@ -XXX,XX +XXX,XX @@
479
#include "qemu/osdep.h"
480
#include "qapi/error.h"
481
#include "qemu-common.h"
482
-#include "hw/arm/arm.h"
483
+#include "hw/arm/boot.h"
484
#include "hw/sysbus.h"
485
#include "hw/boards.h"
486
#include "hw/misc/unimp.h"
487
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
488
index XXXXXXX..XXXXXXX 100644
489
--- a/hw/arm/nseries.c
490
+++ b/hw/arm/nseries.c
491
@@ -XXX,XX +XXX,XX @@
492
#include "qemu/bswap.h"
493
#include "sysemu/sysemu.h"
494
#include "hw/arm/omap.h"
495
-#include "hw/arm/arm.h"
496
+#include "hw/arm/boot.h"
497
#include "hw/irq.h"
498
#include "ui/console.h"
499
#include "hw/boards.h"
500
diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
501
index XXXXXXX..XXXXXXX 100644
502
--- a/hw/arm/omap1.c
503
+++ b/hw/arm/omap1.c
504
@@ -XXX,XX +XXX,XX @@
505
#include "cpu.h"
506
#include "hw/boards.h"
507
#include "hw/hw.h"
508
-#include "hw/arm/arm.h"
509
+#include "hw/arm/boot.h"
510
#include "hw/arm/omap.h"
511
#include "sysemu/sysemu.h"
512
#include "hw/arm/soc_dma.h"
513
diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
514
index XXXXXXX..XXXXXXX 100644
515
--- a/hw/arm/omap2.c
516
+++ b/hw/arm/omap2.c
517
@@ -XXX,XX +XXX,XX @@
518
#include "sysemu/qtest.h"
519
#include "hw/boards.h"
520
#include "hw/hw.h"
521
-#include "hw/arm/arm.h"
522
+#include "hw/arm/boot.h"
523
#include "hw/arm/omap.h"
524
#include "sysemu/sysemu.h"
525
#include "qemu/timer.h"
526
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
527
index XXXXXXX..XXXXXXX 100644
528
--- a/hw/arm/omap_sx1.c
529
+++ b/hw/arm/omap_sx1.c
530
@@ -XXX,XX +XXX,XX @@
531
#include "ui/console.h"
532
#include "hw/arm/omap.h"
533
#include "hw/boards.h"
534
-#include "hw/arm/arm.h"
535
+#include "hw/arm/boot.h"
536
#include "hw/block/flash.h"
537
#include "sysemu/qtest.h"
538
#include "exec/address-spaces.h"
539
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
540
index XXXXXXX..XXXXXXX 100644
541
--- a/hw/arm/palm.c
542
+++ b/hw/arm/palm.c
543
@@ -XXX,XX +XXX,XX @@
544
#include "ui/console.h"
545
#include "hw/arm/omap.h"
546
#include "hw/boards.h"
547
-#include "hw/arm/arm.h"
548
+#include "hw/arm/boot.h"
549
#include "hw/input/tsc2xxx.h"
550
#include "hw/loader.h"
551
#include "exec/address-spaces.h"
552
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
20
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
553
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
554
--- a/hw/arm/raspi.c
22
--- a/hw/arm/raspi.c
555
+++ b/hw/arm/raspi.c
23
+++ b/hw/arm/raspi.c
556
@@ -XXX,XX +XXX,XX @@
24
@@ -XXX,XX +XXX,XX @@ static RaspiProcessorId board_processor_id(uint32_t board_rev)
557
#include "qemu/error-report.h"
25
return proc_id;
558
#include "hw/boards.h"
26
}
559
#include "hw/loader.h"
27
560
-#include "hw/arm/arm.h"
28
-static int board_version(uint32_t board_rev)
561
+#include "hw/arm/boot.h"
29
-{
562
#include "sysemu/sysemu.h"
30
- return board_processor_id(board_rev) + 1;
563
31
-}
564
#define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS */
32
-
565
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
33
static const char *board_soc_type(uint32_t board_rev)
566
index XXXXXXX..XXXXXXX 100644
34
{
567
--- a/hw/arm/realview.c
35
return soc_property[board_processor_id(board_rev)].type;
568
+++ b/hw/arm/realview.c
36
@@ -XXX,XX +XXX,XX @@ static void reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
569
@@ -XXX,XX +XXX,XX @@
37
cpu_set_pc(cs, info->smp_loader_start);
570
#include "qemu-common.h"
38
}
571
#include "cpu.h"
39
572
#include "hw/sysbus.h"
40
-static void setup_boot(MachineState *machine, int version, size_t ram_size)
573
-#include "hw/arm/arm.h"
41
+static void setup_boot(MachineState *machine, RaspiProcessorId processor_id,
574
+#include "hw/arm/boot.h"
42
+ size_t ram_size)
575
#include "hw/arm/primecell.h"
43
{
576
#include "hw/net/lan9118.h"
44
RaspiMachineState *s = RASPI_MACHINE(machine);
577
#include "hw/net/smc91c111.h"
45
int r;
578
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
46
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
579
index XXXXXXX..XXXXXXX 100644
47
s->binfo.ram_size = ram_size;
580
--- a/hw/arm/spitz.c
48
s->binfo.nb_cpus = machine->smp.cpus;
581
+++ b/hw/arm/spitz.c
49
582
@@ -XXX,XX +XXX,XX @@
50
- if (version <= 2) {
583
#include "qapi/error.h"
51
- /* The rpi1 and 2 require some custom setup code to run in Secure
584
#include "hw/hw.h"
52
- * mode before booting a kernel (to set up the SMC vectors so
585
#include "hw/arm/pxa.h"
53
- * that we get a no-op SMC; this is used by Linux to call the
586
-#include "hw/arm/arm.h"
54
+ if (processor_id <= PROCESSOR_ID_BCM2836) {
587
+#include "hw/arm/boot.h"
55
+ /*
588
#include "sysemu/sysemu.h"
56
+ * The BCM2835 and BCM2836 require some custom setup code to run
589
#include "hw/pcmcia.h"
57
+ * in Secure mode before booting a kernel (to set up the SMC vectors
590
#include "hw/i2c/i2c.h"
58
+ * so that we get a no-op SMC; this is used by Linux to call the
591
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
59
* firmware for some cache maintenance operations.
592
index XXXXXXX..XXXXXXX 100644
60
- * The rpi3 doesn't need this.
593
--- a/hw/arm/stellaris.c
61
+ * The BCM2837 doesn't need this.
594
+++ b/hw/arm/stellaris.c
62
*/
595
@@ -XXX,XX +XXX,XX @@
63
s->binfo.board_setup_addr = BOARDSETUP_ADDR;
596
#include "qapi/error.h"
64
s->binfo.write_board_setup = write_board_setup;
597
#include "hw/sysbus.h"
65
@@ -XXX,XX +XXX,XX @@ static void setup_boot(MachineState *machine, int version, size_t ram_size)
598
#include "hw/ssi/ssi.h"
66
s->binfo.secure_boot = true;
599
-#include "hw/arm/arm.h"
67
}
600
+#include "hw/arm/boot.h"
68
601
#include "qemu/timer.h"
69
- /* Pi2 and Pi3 requires SMP setup */
602
#include "hw/i2c/i2c.h"
70
- if (version >= 2) {
603
#include "net/net.h"
71
+ /* BCM2836 and BCM2837 requires SMP setup */
604
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
72
+ if (processor_id >= PROCESSOR_ID_BCM2836) {
605
index XXXXXXX..XXXXXXX 100644
73
s->binfo.smp_loader_start = SMPBOOT_ADDR;
606
--- a/hw/arm/stm32f205_soc.c
74
- if (version == 2) {
607
+++ b/hw/arm/stm32f205_soc.c
75
+ if (processor_id == PROCESSOR_ID_BCM2836) {
608
@@ -XXX,XX +XXX,XX @@
76
s->binfo.write_secondary_boot = write_smpboot;
609
#include "qemu/osdep.h"
77
} else {
610
#include "qapi/error.h"
78
s->binfo.write_secondary_boot = write_smpboot64;
611
#include "qemu-common.h"
79
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_init(MachineState *machine)
612
-#include "hw/arm/arm.h"
80
RaspiMachineClass *mc = RASPI_MACHINE_GET_CLASS(machine);
613
+#include "hw/arm/boot.h"
81
RaspiMachineState *s = RASPI_MACHINE(machine);
614
#include "exec/address-spaces.h"
82
uint32_t board_rev = mc->board_rev;
615
#include "hw/arm/stm32f205_soc.h"
83
- int version = board_version(board_rev);
616
84
uint64_t ram_size = board_ram_size(board_rev);
617
diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
85
uint32_t vcram_size;
618
index XXXXXXX..XXXXXXX 100644
86
DriveInfo *di;
619
--- a/hw/arm/strongarm.c
87
@@ -XXX,XX +XXX,XX @@ static void raspi_machine_init(MachineState *machine)
620
+++ b/hw/arm/strongarm.c
88
621
@@ -XXX,XX +XXX,XX @@
89
vcram_size = object_property_get_uint(OBJECT(&s->soc), "vcram-size",
622
#include "hw/sysbus.h"
90
&error_abort);
623
#include "strongarm.h"
91
- setup_boot(machine, version, machine->ram_size - vcram_size);
624
#include "qemu/error-report.h"
92
+ setup_boot(machine, board_processor_id(mc->board_rev),
625
-#include "hw/arm/arm.h"
93
+ machine->ram_size - vcram_size);
626
+#include "hw/arm/boot.h"
94
}
627
#include "chardev/char-fe.h"
95
628
#include "chardev/char-serial.h"
96
static void raspi_machine_class_common_init(MachineClass *mc,
629
#include "sysemu/sysemu.h"
630
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
631
index XXXXXXX..XXXXXXX 100644
632
--- a/hw/arm/tosa.c
633
+++ b/hw/arm/tosa.c
634
@@ -XXX,XX +XXX,XX @@
635
#include "qapi/error.h"
636
#include "hw/hw.h"
637
#include "hw/arm/pxa.h"
638
-#include "hw/arm/arm.h"
639
+#include "hw/arm/boot.h"
640
#include "hw/arm/sharpsl.h"
641
#include "hw/pcmcia.h"
642
#include "hw/boards.h"
643
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
644
index XXXXXXX..XXXXXXX 100644
645
--- a/hw/arm/versatilepb.c
646
+++ b/hw/arm/versatilepb.c
647
@@ -XXX,XX +XXX,XX @@
648
#include "qemu-common.h"
649
#include "cpu.h"
650
#include "hw/sysbus.h"
651
-#include "hw/arm/arm.h"
652
+#include "hw/arm/boot.h"
653
#include "hw/net/smc91c111.h"
654
#include "net/net.h"
655
#include "sysemu/sysemu.h"
656
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
657
index XXXXXXX..XXXXXXX 100644
658
--- a/hw/arm/vexpress.c
659
+++ b/hw/arm/vexpress.c
660
@@ -XXX,XX +XXX,XX @@
661
#include "qemu-common.h"
662
#include "cpu.h"
663
#include "hw/sysbus.h"
664
-#include "hw/arm/arm.h"
665
+#include "hw/arm/boot.h"
666
#include "hw/arm/primecell.h"
667
#include "hw/net/lan9118.h"
668
#include "hw/i2c/i2c.h"
669
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
670
index XXXXXXX..XXXXXXX 100644
671
--- a/hw/arm/virt.c
672
+++ b/hw/arm/virt.c
673
@@ -XXX,XX +XXX,XX @@
674
#include "qemu/option.h"
675
#include "qapi/error.h"
676
#include "hw/sysbus.h"
677
-#include "hw/arm/arm.h"
678
+#include "hw/arm/boot.h"
679
#include "hw/arm/primecell.h"
680
#include "hw/arm/virt.h"
681
#include "hw/block/flash.h"
682
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
683
index XXXXXXX..XXXXXXX 100644
684
--- a/hw/arm/xilinx_zynq.c
685
+++ b/hw/arm/xilinx_zynq.c
686
@@ -XXX,XX +XXX,XX @@
687
#include "qemu-common.h"
688
#include "cpu.h"
689
#include "hw/sysbus.h"
690
-#include "hw/arm/arm.h"
691
+#include "hw/arm/boot.h"
692
#include "net/net.h"
693
#include "exec/address-spaces.h"
694
#include "sysemu/sysemu.h"
695
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
696
index XXXXXXX..XXXXXXX 100644
697
--- a/hw/arm/xlnx-versal.c
698
+++ b/hw/arm/xlnx-versal.c
699
@@ -XXX,XX +XXX,XX @@
700
#include "net/net.h"
701
#include "sysemu/sysemu.h"
702
#include "sysemu/kvm.h"
703
-#include "hw/arm/arm.h"
704
+#include "hw/arm/boot.h"
705
#include "kvm_arm.h"
706
#include "hw/misc/unimp.h"
707
#include "hw/intc/arm_gicv3_common.h"
708
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
709
index XXXXXXX..XXXXXXX 100644
710
--- a/hw/arm/z2.c
711
+++ b/hw/arm/z2.c
712
@@ -XXX,XX +XXX,XX @@
713
#include "qemu/osdep.h"
714
#include "hw/hw.h"
715
#include "hw/arm/pxa.h"
716
-#include "hw/arm/arm.h"
717
+#include "hw/arm/boot.h"
718
#include "hw/i2c/i2c.h"
719
#include "hw/ssi/ssi.h"
720
#include "hw/boards.h"
721
--
97
--
722
2.20.1
98
2.20.1
723
99
724
100
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.