1
Not very much here, but several people have fallen over
1
Not much here, mostly documentation, but a few bug fixes.
2
the vector operation segfault bug, so let's get the fix
3
into master.
4
2
5
thanks
3
thanks
6
-- PMM
4
-- PMM
7
5
8
The following changes since commit d418238dca7b4e0b124135827ead3076233052b1:
6
The following changes since commit 873ec69aeb12e24eec7fb317fd0cd8494e8489dd:
9
7
10
Merge remote-tracking branch 'remotes/rth/tags/pull-rng-20190522' into staging (2019-05-23 12:57:17 +0100)
8
Merge remote-tracking branch 'remotes/cminyard/tags/for-qemu-i2c-5' into staging (2020-07-20 11:03:09 +0100)
11
9
12
are available in the Git repository at:
10
are available in the Git repository at:
13
11
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190523
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200720
15
13
16
for you to fetch changes up to 98e4f4fdb8ea05d840f51f47125924c2bb9df2df:
14
for you to fetch changes up to 6a0b7505f1fd6769c3f1558fda76464d51e4118a:
17
15
18
hw/arm/exynos4210: QOM'ify the Exynos4210 SoC (2019-05-23 14:47:44 +0100)
16
docs/system: Document the arm virt board (2020-07-20 11:35:17 +0100)
19
17
20
----------------------------------------------------------------
18
----------------------------------------------------------------
21
target-arm queue:
19
target-arm queue:
22
* exynos4210: QOM'ify the Exynos4210 SoC
20
* virt: Don't enable MTE emulation by default
23
* exynos4210: Add DMA support for the Exynos4210
21
* virt: Diagnose attempts to use MTE with memory-hotplug or KVM
24
* arm_gicv3: Fix writes to ICC_CTLR_EL3
22
(rather than silently not working correctly)
25
* arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
23
* util: Implement qemu_get_thread_id() for OpenBSD
26
* target/arm: Fix vector operation segfault
24
* qdev: Add doc comments for qdev_unrealize and GPIO functions,
27
* target/arm: Minor improvements to BFXIL, EXTR
25
and standardize on doc-comments-in-header-file
26
* hw/arm/armsse: Assert info->num_cpus is in-bounds in armsse_realize()
27
* docs/system: Document canon-a1100, collie, gumstix, virt boards
28
28
29
----------------------------------------------------------------
29
----------------------------------------------------------------
30
Alistair Francis (1):
30
David CARLIER (1):
31
target/arm: Fix vector operation segfault
31
util: Implement qemu_get_thread_id() for OpenBSD
32
32
33
Guenter Roeck (1):
33
Peter Maydell (8):
34
hw/arm/exynos4210: Add DMA support for the Exynos4210
34
qdev: Move doc comments from qdev.c to qdev-core.h
35
qdev: Document qdev_unrealize()
36
qdev: Document GPIO related functions
37
hw/arm/armsse: Assert info->num_cpus is in-bounds in armsse_realize()
38
docs/system: Briefly document canon-a1100 board
39
docs/system: Briefly document collie board
40
docs/system: Briefly document gumstix boards
41
docs/system: Document the arm virt board
35
42
36
Peter Maydell (5):
43
Richard Henderson (3):
37
arm: Move system_clock_scale to armv7m_systick.h
44
hw/arm/virt: Enable MTE via a machine property
38
arm: Remove unnecessary includes of hw/arm/arm.h
45
hw/arm/virt: Error for MTE enabled with KVM
39
arm: Rename hw/arm/arm.h to hw/arm/boot.h
46
hw/arm/virt: Disable memory hotplug when MTE is enabled
40
hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
41
hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3
42
47
43
Philippe Mathieu-Daudé (3):
48
docs/system/arm/collie.rst | 16 +++
44
hw/arm/exynos4: Remove unuseful debug code
49
docs/system/arm/digic.rst | 11 ++
45
hw/arm/exynos4: Use the IEC binary prefix definitions
50
docs/system/arm/gumstix.rst | 21 ++++
46
hw/arm/exynos4210: QOM'ify the Exynos4210 SoC
51
docs/system/arm/virt.rst | 161 ++++++++++++++++++++++++++
52
docs/system/target-arm.rst | 4 +
53
include/hw/arm/virt.h | 1 +
54
include/hw/qdev-core.h | 267 ++++++++++++++++++++++++++++++++++++++++++-
55
include/hw/qdev-properties.h | 13 +++
56
hw/arm/armsse.c | 2 +
57
hw/arm/virt.c | 50 +++++++-
58
hw/core/qdev.c | 33 ------
59
target/arm/cpu.c | 19 +--
60
target/arm/cpu64.c | 5 +-
61
util/oslib-posix.c | 2 +
62
MAINTAINERS | 4 +
63
15 files changed, 559 insertions(+), 50 deletions(-)
64
create mode 100644 docs/system/arm/collie.rst
65
create mode 100644 docs/system/arm/digic.rst
66
create mode 100644 docs/system/arm/gumstix.rst
67
create mode 100644 docs/system/arm/virt.rst
47
68
48
Richard Henderson (2):
49
target/arm: Use extract2 for EXTR
50
target/arm: Simplify BFXIL expansion
51
52
include/hw/arm/allwinner-a10.h | 2 +-
53
include/hw/arm/aspeed_soc.h | 1 -
54
include/hw/arm/bcm2836.h | 1 -
55
include/hw/arm/{arm.h => boot.h} | 12 +++------
56
include/hw/arm/exynos4210.h | 9 +++++--
57
include/hw/arm/fsl-imx25.h | 2 +-
58
include/hw/arm/fsl-imx31.h | 2 +-
59
include/hw/arm/fsl-imx6.h | 2 +-
60
include/hw/arm/fsl-imx6ul.h | 2 +-
61
include/hw/arm/fsl-imx7.h | 2 +-
62
include/hw/arm/virt.h | 2 +-
63
include/hw/arm/xlnx-versal.h | 2 +-
64
include/hw/arm/xlnx-zynqmp.h | 2 +-
65
include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++
66
hw/arm/armsse.c | 2 +-
67
hw/arm/armv7m.c | 2 +-
68
hw/arm/aspeed.c | 2 +-
69
hw/arm/boot.c | 2 +-
70
hw/arm/collie.c | 2 +-
71
hw/arm/exynos4210.c | 54 ++++++++++++++++++++++++++++++++++++---
72
hw/arm/exynos4_boards.c | 40 ++++++++---------------------
73
hw/arm/highbank.c | 2 +-
74
hw/arm/integratorcp.c | 2 +-
75
hw/arm/mainstone.c | 2 +-
76
hw/arm/microbit.c | 2 +-
77
hw/arm/mps2-tz.c | 2 +-
78
hw/arm/mps2.c | 2 +-
79
hw/arm/msf2-soc.c | 1 -
80
hw/arm/msf2-som.c | 2 +-
81
hw/arm/musca.c | 2 +-
82
hw/arm/musicpal.c | 2 +-
83
hw/arm/netduino2.c | 2 +-
84
hw/arm/nrf51_soc.c | 2 +-
85
hw/arm/nseries.c | 2 +-
86
hw/arm/omap1.c | 2 +-
87
hw/arm/omap2.c | 2 +-
88
hw/arm/omap_sx1.c | 2 +-
89
hw/arm/palm.c | 2 +-
90
hw/arm/raspi.c | 2 +-
91
hw/arm/realview.c | 2 +-
92
hw/arm/spitz.c | 2 +-
93
hw/arm/stellaris.c | 2 +-
94
hw/arm/stm32f205_soc.c | 2 +-
95
hw/arm/strongarm.c | 2 +-
96
hw/arm/tosa.c | 2 +-
97
hw/arm/versatilepb.c | 2 +-
98
hw/arm/vexpress.c | 2 +-
99
hw/arm/virt.c | 2 +-
100
hw/arm/xilinx_zynq.c | 2 +-
101
hw/arm/xlnx-versal.c | 2 +-
102
hw/arm/z2.c | 2 +-
103
hw/intc/arm_gicv3_cpuif.c | 6 ++---
104
hw/intc/armv7m_nvic.c | 1 -
105
target/arm/arm-semi.c | 1 -
106
target/arm/cpu.c | 1 -
107
target/arm/cpu64.c | 1 -
108
target/arm/kvm.c | 1 -
109
target/arm/kvm32.c | 1 -
110
target/arm/kvm64.c | 1 -
111
target/arm/translate-a64.c | 44 ++++++++++++++++---------------
112
target/arm/translate.c | 4 +--
113
61 files changed, 164 insertions(+), 123 deletions(-)
114
rename include/hw/arm/{arm.h => boot.h} (96%)
115
diff view generated by jsdifflib
1
The hw/arm/arm.h header now only includes declarations relating
1
From: Richard Henderson <richard.henderson@linaro.org>
2
to boot.c code, so it is only needed by Arm board or SoC code.
3
Remove some unnecessary inclusions of it from target/arm files
4
and from hw/intc/armv7m_nvic.c.
5
2
3
Control this cpu feature via a machine property, much as we do
4
with secure=on, since both require specialized support in the
5
machine setup to be functional.
6
7
Default MTE to off, since this feature implies extra overhead.
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200713213341.590275-2-richard.henderson@linaro.org
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20190516163857.6430-3-peter.maydell@linaro.org
10
---
13
---
11
hw/intc/armv7m_nvic.c | 1 -
14
include/hw/arm/virt.h | 1 +
12
target/arm/arm-semi.c | 1 -
15
hw/arm/virt.c | 39 ++++++++++++++++++++++++++++++++++-----
13
target/arm/cpu.c | 1 -
16
target/arm/cpu.c | 19 +++++++++++--------
14
target/arm/cpu64.c | 1 -
17
target/arm/cpu64.c | 5 +++--
15
target/arm/kvm.c | 1 -
18
4 files changed, 49 insertions(+), 15 deletions(-)
16
target/arm/kvm32.c | 1 -
17
target/arm/kvm64.c | 1 -
18
7 files changed, 7 deletions(-)
19
19
20
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
20
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
21
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/intc/armv7m_nvic.c
22
--- a/include/hw/arm/virt.h
23
+++ b/hw/intc/armv7m_nvic.c
23
+++ b/include/hw/arm/virt.h
24
@@ -XXX,XX +XXX,XX @@
24
@@ -XXX,XX +XXX,XX @@ typedef struct {
25
#include "cpu.h"
25
bool its;
26
#include "hw/sysbus.h"
26
bool virt;
27
#include "qemu/timer.h"
27
bool ras;
28
-#include "hw/arm/arm.h"
28
+ bool mte;
29
#include "hw/intc/armv7m_nvic.h"
29
OnOffAuto acpi;
30
#include "target/arm/cpu.h"
30
VirtGICType gic_version;
31
#include "exec/exec-all.h"
31
VirtIOMMUType iommu;
32
diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
32
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
33
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/arm-semi.c
34
--- a/hw/arm/virt.c
35
+++ b/target/arm/arm-semi.c
35
+++ b/hw/arm/virt.c
36
@@ -XXX,XX +XXX,XX @@
36
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
37
#else
37
OBJECT(secure_sysmem), &error_abort);
38
#include "qemu-common.h"
38
}
39
#include "exec/gdbstub.h"
39
40
-#include "hw/arm/arm.h"
40
- /*
41
#include "qemu/cutils.h"
41
- * The cpu adds the property if and only if MemTag is supported.
42
#endif
42
- * If it is, we must allocate the ram to back that up.
43
43
- */
44
- if (object_property_find(cpuobj, "tag-memory", NULL)) {
45
+ if (vms->mte) {
46
+ /* Create the memory region only once, but link to all cpus. */
47
if (!tag_sysmem) {
48
+ /*
49
+ * The property exists only if MemTag is supported.
50
+ * If it is, we must allocate the ram to back that up.
51
+ */
52
+ if (!object_property_find(cpuobj, "tag-memory", NULL)) {
53
+ error_report("MTE requested, but not supported "
54
+ "by the guest CPU");
55
+ exit(1);
56
+ }
57
+
58
tag_sysmem = g_new(MemoryRegion, 1);
59
memory_region_init(tag_sysmem, OBJECT(machine),
60
"tag-memory", UINT64_MAX / 32);
61
@@ -XXX,XX +XXX,XX @@ static void virt_set_ras(Object *obj, bool value, Error **errp)
62
vms->ras = value;
63
}
64
65
+static bool virt_get_mte(Object *obj, Error **errp)
66
+{
67
+ VirtMachineState *vms = VIRT_MACHINE(obj);
68
+
69
+ return vms->mte;
70
+}
71
+
72
+static void virt_set_mte(Object *obj, bool value, Error **errp)
73
+{
74
+ VirtMachineState *vms = VIRT_MACHINE(obj);
75
+
76
+ vms->mte = value;
77
+}
78
+
79
static char *virt_get_gic_version(Object *obj, Error **errp)
80
{
81
VirtMachineState *vms = VIRT_MACHINE(obj);
82
@@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj)
83
"Set on/off to enable/disable reporting host memory errors "
84
"to a KVM guest using ACPI and guest external abort exceptions");
85
86
+ /* MTE is disabled by default. */
87
+ vms->mte = false;
88
+ object_property_add_bool(obj, "mte", virt_get_mte, virt_set_mte);
89
+ object_property_set_description(obj, "mte",
90
+ "Set on/off to enable/disable emulating a "
91
+ "guest CPU which implements the ARM "
92
+ "Memory Tagging Extension");
93
+
94
vms->irqmap = a15irqmap;
95
96
virt_flash_create(vms);
44
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
97
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
45
index XXXXXXX..XXXXXXX 100644
98
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/cpu.c
99
--- a/target/arm/cpu.c
47
+++ b/target/arm/cpu.c
100
+++ b/target/arm/cpu.c
48
@@ -XXX,XX +XXX,XX @@
101
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
49
#if !defined(CONFIG_USER_ONLY)
102
cpu->id_pfr1 &= ~0xf000;
50
#include "hw/loader.h"
103
}
51
#endif
104
52
-#include "hw/arm/arm.h"
105
+#ifndef CONFIG_USER_ONLY
53
#include "sysemu/sysemu.h"
106
+ if (cpu->tag_memory == NULL && cpu_isar_feature(aa64_mte, cpu)) {
54
#include "sysemu/hw_accel.h"
107
+ /*
55
#include "kvm_arm.h"
108
+ * Disable the MTE feature bits if we do not have tag-memory
109
+ * provided by the machine.
110
+ */
111
+ cpu->isar.id_aa64pfr1 =
112
+ FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 0);
113
+ }
114
+#endif
115
+
116
/* MPU can be configured out of a PMSA CPU either by setting has-mpu
117
* to false or by setting pmsav7-dregion to 0.
118
*/
119
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
120
cpu_address_space_init(cs, ARMASIdx_TagS, "cpu-tag-memory",
121
cpu->secure_tag_memory);
122
}
123
- } else if (cpu_isar_feature(aa64_mte, cpu)) {
124
- /*
125
- * Since there is no tag memory, we can't meaningfully support MTE
126
- * to its fullest. To avoid problems later, when we would come to
127
- * use the tag memory, downgrade support to insns only.
128
- */
129
- cpu->isar.id_aa64pfr1 =
130
- FIELD_DP64(cpu->isar.id_aa64pfr1, ID_AA64PFR1, MTE, 1);
131
}
132
133
cpu_address_space_init(cs, ARMASIdx_NS, "cpu-memory", cs->memory);
56
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
134
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
57
index XXXXXXX..XXXXXXX 100644
135
index XXXXXXX..XXXXXXX 100644
58
--- a/target/arm/cpu64.c
136
--- a/target/arm/cpu64.c
59
+++ b/target/arm/cpu64.c
137
+++ b/target/arm/cpu64.c
60
@@ -XXX,XX +XXX,XX @@
138
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
61
#if !defined(CONFIG_USER_ONLY)
139
t = cpu->isar.id_aa64pfr1;
62
#include "hw/loader.h"
140
t = FIELD_DP64(t, ID_AA64PFR1, BT, 1);
63
#endif
141
/*
64
-#include "hw/arm/arm.h"
142
- * Begin with full support for MTE; will be downgraded to MTE=1
65
#include "sysemu/sysemu.h"
143
- * during realize if the board provides no tag memory.
66
#include "sysemu/kvm.h"
144
+ * Begin with full support for MTE. This will be downgraded to MTE=0
67
#include "kvm_arm.h"
145
+ * during realize if the board provides no tag memory, much like
68
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
146
+ * we do for EL2 with the virtualization=on property.
69
index XXXXXXX..XXXXXXX 100644
147
*/
70
--- a/target/arm/kvm.c
148
t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2);
71
+++ b/target/arm/kvm.c
149
cpu->isar.id_aa64pfr1 = t;
72
@@ -XXX,XX +XXX,XX @@
73
#include "cpu.h"
74
#include "trace.h"
75
#include "internals.h"
76
-#include "hw/arm/arm.h"
77
#include "hw/pci/pci.h"
78
#include "exec/memattrs.h"
79
#include "exec/address-spaces.h"
80
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
81
index XXXXXXX..XXXXXXX 100644
82
--- a/target/arm/kvm32.c
83
+++ b/target/arm/kvm32.c
84
@@ -XXX,XX +XXX,XX @@
85
#include "sysemu/kvm.h"
86
#include "kvm_arm.h"
87
#include "internals.h"
88
-#include "hw/arm/arm.h"
89
#include "qemu/log.h"
90
91
static inline void set_feature(uint64_t *features, int feature)
92
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
93
index XXXXXXX..XXXXXXX 100644
94
--- a/target/arm/kvm64.c
95
+++ b/target/arm/kvm64.c
96
@@ -XXX,XX +XXX,XX @@
97
#include "sysemu/kvm.h"
98
#include "kvm_arm.h"
99
#include "internals.h"
100
-#include "hw/arm/arm.h"
101
102
static bool have_guest_debug;
103
104
--
150
--
105
2.20.1
151
2.20.1
106
152
107
153
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The mask implied by the extract is redundant with the one
3
While we expect KVM to support MTE at some future point,
4
implied by the deposit. Also, fix spelling of BFXIL.
4
it certainly won't be ready in time for qemu 5.1.
5
5
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20190514011129.11330-3-richard.henderson@linaro.org
7
Message-id: 20200713213341.590275-3-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
target/arm/translate-a64.c | 6 +++---
11
hw/arm/virt.c | 6 ++++++
12
1 file changed, 3 insertions(+), 3 deletions(-)
12
1 file changed, 6 insertions(+)
13
13
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
16
--- a/hw/arm/virt.c
17
+++ b/target/arm/translate-a64.c
17
+++ b/hw/arm/virt.c
18
@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
18
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
19
tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len);
19
exit(1);
20
return;
21
}
22
- /* opc == 1, BXFIL fall through to deposit */
23
- tcg_gen_extract_i64(tcg_tmp, tcg_tmp, ri, len);
24
+ /* opc == 1, BFXIL fall through to deposit */
25
+ tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri);
26
pos = 0;
27
} else {
28
/* Handle the ri > si case with a deposit
29
@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
30
len = ri;
31
}
20
}
32
21
33
- if (opc == 1) { /* BFM, BXFIL */
22
+ if (vms->mte && kvm_enabled()) {
34
+ if (opc == 1) { /* BFM, BFXIL */
23
+ error_report("mach-virt: KVM does not support providing "
35
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len);
24
+ "MTE to the guest CPU");
36
} else {
25
+ exit(1);
37
/* SBFM or UBFM: We start with zero, and we haven't modified
26
+ }
27
+
28
create_fdt(vms);
29
30
possible_cpus = mc->possible_cpu_arch_ids(machine);
38
--
31
--
39
2.20.1
32
2.20.1
40
33
41
34
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This is, after all, how we implement extract2 in tcg/aarch64.
3
When MTE is enabled, tag memory must exist for all RAM.
4
4
5
It might be possible to simultaneously hot plug tag memory
6
alongside the corresponding normal memory, but for now just
7
disable hotplug.
8
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20200713213341.590275-4-richard.henderson@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20190514011129.11330-2-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
13
---
10
target/arm/translate-a64.c | 38 ++++++++++++++++++++------------------
14
hw/arm/virt.c | 5 +++++
11
1 file changed, 20 insertions(+), 18 deletions(-)
15
1 file changed, 5 insertions(+)
12
16
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
17
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
14
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
19
--- a/hw/arm/virt.c
16
+++ b/target/arm/translate-a64.c
20
+++ b/hw/arm/virt.c
17
@@ -XXX,XX +XXX,XX @@ static void disas_extract(DisasContext *s, uint32_t insn)
21
@@ -XXX,XX +XXX,XX @@ static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev,
18
} else {
22
return;
19
tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));
23
}
20
}
24
21
- } else if (rm == rn) { /* ROR */
25
+ if (vms->mte) {
22
- tcg_rm = cpu_reg(s, rm);
26
+ error_setg(errp, "memory hotplug is not enabled: MTE is enabled");
23
- if (sf) {
27
+ return;
24
- tcg_gen_rotri_i64(tcg_rd, tcg_rm, imm);
28
+ }
25
- } else {
26
- TCGv_i32 tmp = tcg_temp_new_i32();
27
- tcg_gen_extrl_i64_i32(tmp, tcg_rm);
28
- tcg_gen_rotri_i32(tmp, tmp, imm);
29
- tcg_gen_extu_i32_i64(tcg_rd, tmp);
30
- tcg_temp_free_i32(tmp);
31
- }
32
} else {
33
- tcg_rm = read_cpu_reg(s, rm, sf);
34
- tcg_rn = read_cpu_reg(s, rn, sf);
35
- tcg_gen_shri_i64(tcg_rm, tcg_rm, imm);
36
- tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm);
37
- tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn);
38
- if (!sf) {
39
- tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
40
+ tcg_rm = cpu_reg(s, rm);
41
+ tcg_rn = cpu_reg(s, rn);
42
+
29
+
43
+ if (sf) {
30
if (is_nvdimm && !ms->nvdimms_state->is_enabled) {
44
+ /* Specialization to ROR happens in EXTRACT2. */
31
error_setg(errp, "nvdimm is not enabled: add 'nvdimm=on' to '-M'");
45
+ tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, imm);
32
return;
46
+ } else {
47
+ TCGv_i32 t0 = tcg_temp_new_i32();
48
+
49
+ tcg_gen_extrl_i64_i32(t0, tcg_rm);
50
+ if (rm == rn) {
51
+ tcg_gen_rotri_i32(t0, t0, imm);
52
+ } else {
53
+ TCGv_i32 t1 = tcg_temp_new_i32();
54
+ tcg_gen_extrl_i64_i32(t1, tcg_rn);
55
+ tcg_gen_extract2_i32(t0, t0, t1, imm);
56
+ tcg_temp_free_i32(t1);
57
+ }
58
+ tcg_gen_extu_i32_i64(tcg_rd, t0);
59
+ tcg_temp_free_i32(t0);
60
}
61
}
62
}
63
--
33
--
64
2.20.1
34
2.20.1
65
35
66
36
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: David CARLIER <devnexen@gmail.com>
2
2
3
QEMU already supports pl330. Instantiate it for Exynos4210.
3
Implement qemu_get_thread_id() for OpenBSD hosts, using
4
getthrid().
4
5
5
Relevant part of Linux arch/arm/boot/dts/exynos4.dtsi:
6
Signed-off-by: David Carlier <devnexen@gmail.com>
6
7
Reviewed-by: Brad Smith <brad@comstyle.com>
7
/ {
8
Message-id: CA+XhMqxD6gQDBaj8tX0CMEj3si7qYKsM8u1km47e_-U7MC37Pg@mail.gmail.com
8
soc: soc {
9
amba {
10
pdma0: pdma@12680000 {
11
compatible = "arm,pl330", "arm,primecell";
12
reg = <0x12680000 0x1000>;
13
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
14
clocks = <&clock CLK_PDMA0>;
15
clock-names = "apb_pclk";
16
#dma-cells = <1>;
17
#dma-channels = <8>;
18
#dma-requests = <32>;
19
};
20
pdma1: pdma@12690000 {
21
compatible = "arm,pl330", "arm,primecell";
22
reg = <0x12690000 0x1000>;
23
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
24
clocks = <&clock CLK_PDMA1>;
25
clock-names = "apb_pclk";
26
#dma-cells = <1>;
27
#dma-channels = <8>;
28
#dma-requests = <32>;
29
};
30
mdma1: mdma@12850000 {
31
compatible = "arm,pl330", "arm,primecell";
32
reg = <0x12850000 0x1000>;
33
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
34
clocks = <&clock CLK_MDMA>;
35
clock-names = "apb_pclk";
36
#dma-cells = <1>;
37
#dma-channels = <8>;
38
#dma-requests = <1>;
39
};
40
};
41
};
42
};
43
44
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
45
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
46
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
47
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
48
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
[PMM: tidied up commit message]
49
Message-id: 20190520214342.13709-4-philmd@redhat.com
50
[PMD: Do not set default qdev properties, create the controllers in the SoC
51
rather than the board (Peter Maydell), add dtsi in commit message]
52
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
53
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
54
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
55
---
12
---
56
hw/arm/exynos4210.c | 26 ++++++++++++++++++++++++++
13
util/oslib-posix.c | 2 ++
57
1 file changed, 26 insertions(+)
14
1 file changed, 2 insertions(+)
58
15
59
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
16
diff --git a/util/oslib-posix.c b/util/oslib-posix.c
60
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
61
--- a/hw/arm/exynos4210.c
18
--- a/util/oslib-posix.c
62
+++ b/hw/arm/exynos4210.c
19
+++ b/util/oslib-posix.c
63
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ int qemu_get_thread_id(void)
64
/* EHCI */
21
return (int)tid;
65
#define EXYNOS4210_EHCI_BASE_ADDR 0x12580000
22
#elif defined(__NetBSD__)
66
23
return _lwp_self();
67
+/* DMA */
24
+#elif defined(__OpenBSD__)
68
+#define EXYNOS4210_PL330_BASE0_ADDR 0x12680000
25
+ return getthrid();
69
+#define EXYNOS4210_PL330_BASE1_ADDR 0x12690000
26
#else
70
+#define EXYNOS4210_PL330_BASE2_ADDR 0x12850000
27
return getpid();
71
+
28
#endif
72
static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
73
0x09, 0x00, 0x00, 0x00 };
74
75
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu)
76
return (0x9 << ARM_AFF1_SHIFT) | cpu;
77
}
78
79
+static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
80
+{
81
+ SysBusDevice *busdev;
82
+ DeviceState *dev;
83
+
84
+ dev = qdev_create(NULL, "pl330");
85
+ qdev_prop_set_uint8(dev, "num_periph_req", nreq);
86
+ qdev_init_nofail(dev);
87
+ busdev = SYS_BUS_DEVICE(dev);
88
+ sysbus_mmio_map(busdev, 0, base);
89
+ sysbus_connect_irq(busdev, 0, irq);
90
+}
91
+
92
Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
93
{
94
Exynos4210State *s = g_new0(Exynos4210State, 1);
95
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
96
sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
97
s->irq_table[exynos4210_get_irq(28, 3)]);
98
99
+ /*** DMA controllers ***/
100
+ pl330_create(EXYNOS4210_PL330_BASE0_ADDR,
101
+ qemu_irq_invert(s->irq_table[exynos4210_get_irq(35, 1)]), 32);
102
+ pl330_create(EXYNOS4210_PL330_BASE1_ADDR,
103
+ qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
104
+ pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
105
+ qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
106
+
107
return s;
108
}
109
--
29
--
110
2.20.1
30
2.20.1
111
31
112
32
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
The doc-comments which document the qdev API are split between the
2
header file and the C source files, because as a project we haven't
3
been consistent about where we put them.
2
4
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
Move all the doc-comments in qdev.c to the header files, so that
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
6
users of the APIs don't have to look at the implementation files for
5
Message-id: 20190520214342.13709-5-philmd@redhat.com
7
this information.
8
9
In the process, unify them into our doc-comment format and expand on
10
them in some cases to clarify expected use cases.
11
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20200711142425.16283-2-peter.maydell@linaro.org
7
---
15
---
8
include/hw/arm/exynos4210.h | 9 +++++++--
16
include/hw/qdev-core.h | 57 ++++++++++++++++++++++++++++++++++++
9
hw/arm/exynos4210.c | 28 ++++++++++++++++++++++++----
17
include/hw/qdev-properties.h | 13 ++++++++
10
hw/arm/exynos4_boards.c | 9 ++++++---
18
hw/core/qdev.c | 33 ---------------------
11
3 files changed, 37 insertions(+), 9 deletions(-)
19
3 files changed, 70 insertions(+), 33 deletions(-)
12
20
13
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
21
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
14
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/arm/exynos4210.h
23
--- a/include/hw/qdev-core.h
16
+++ b/include/hw/arm/exynos4210.h
24
+++ b/include/hw/qdev-core.h
17
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210Irq {
25
@@ -XXX,XX +XXX,XX @@ compat_props_add(GPtrArray *arr,
18
} Exynos4210Irq;
26
19
27
/*** Board API. This should go away once we have a machine config file. ***/
20
typedef struct Exynos4210State {
28
21
+ /*< private >*/
29
+/**
22
+ SysBusDevice parent_obj;
30
+ * qdev_new: Create a device on the heap
23
+ /*< public >*/
31
+ * @name: device type to create (we assert() that this type exists)
24
ARMCPU *cpu[EXYNOS4210_NCPUS];
32
+ *
25
Exynos4210Irq irqs;
33
+ * This only allocates the memory and initializes the device state
26
qemu_irq *irq_table;
34
+ * structure, ready for the caller to set properties if they wish.
27
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210State {
35
+ * The device still needs to be realized.
28
I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
36
+ * The returned object has a reference count of 1.
29
} Exynos4210State;
37
+ */
30
38
DeviceState *qdev_new(const char *name);
31
+#define TYPE_EXYNOS4210_SOC "exynos4210"
39
+/**
32
+#define EXYNOS4210_SOC(obj) \
40
+ * qdev_try_new: Try to create a device on the heap
33
+ OBJECT_CHECK(Exynos4210State, obj, TYPE_EXYNOS4210_SOC)
41
+ * @name: device type to create
34
+
42
+ *
35
void exynos4210_write_secondary(ARMCPU *cpu,
43
+ * This is like qdev_new(), except it returns %NULL when type @name
36
const struct arm_boot_info *info);
44
+ * does not exist, rather than asserting.
37
45
+ */
38
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem);
46
DeviceState *qdev_try_new(const char *name);
39
-
47
+/**
40
/* Initialize exynos4210 IRQ subsystem stub */
48
+ * qdev_realize: Realize @dev.
41
qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
49
+ * @dev: device to realize
42
50
+ * @bus: bus to plug it into (may be NULL)
43
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
51
+ * @errp: pointer to error object
52
+ *
53
+ * "Realize" the device, i.e. perform the second phase of device
54
+ * initialization.
55
+ * @dev must not be plugged into a bus already.
56
+ * If @bus, plug @dev into @bus. This takes a reference to @dev.
57
+ * If @dev has no QOM parent, make one up, taking another reference.
58
+ * On success, return true.
59
+ * On failure, store an error through @errp and return false.
60
+ *
61
+ * If you created @dev using qdev_new(), you probably want to use
62
+ * qdev_realize_and_unref() instead.
63
+ */
64
bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp);
65
+/**
66
+ * qdev_realize_and_unref: Realize @dev and drop a reference
67
+ * @dev: device to realize
68
+ * @bus: bus to plug it into (may be NULL)
69
+ * @errp: pointer to error object
70
+ *
71
+ * Realize @dev and drop a reference.
72
+ * This is like qdev_realize(), except the caller must hold a
73
+ * (private) reference, which is dropped on return regardless of
74
+ * success or failure. Intended use::
75
+ *
76
+ * dev = qdev_new();
77
+ * [...]
78
+ * qdev_realize_and_unref(dev, bus, errp);
79
+ *
80
+ * Now @dev can go away without further ado.
81
+ *
82
+ * If you are embedding the device into some other QOM device and
83
+ * initialized it via some variant on object_initialize_child() then
84
+ * do not use this function, because that family of functions arrange
85
+ * for the only reference to the child device to be held by the parent
86
+ * via the child<> property, and so the reference-count-drop done here
87
+ * would be incorrect. For that use case you want qdev_realize().
88
+ */
89
bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp);
90
void qdev_unrealize(DeviceState *dev);
91
void qdev_set_legacy_instance_id(DeviceState *dev, int alias_id,
92
diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h
44
index XXXXXXX..XXXXXXX 100644
93
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/arm/exynos4210.c
94
--- a/include/hw/qdev-properties.h
46
+++ b/hw/arm/exynos4210.c
95
+++ b/include/hw/qdev-properties.h
47
@@ -XXX,XX +XXX,XX @@ static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
96
@@ -XXX,XX +XXX,XX @@ void error_set_from_qdev_prop_error(Error **errp, int ret, DeviceState *dev,
48
sysbus_connect_irq(busdev, 0, irq);
97
*/
98
void qdev_property_add_static(DeviceState *dev, Property *prop);
99
100
+/**
101
+ * qdev_alias_all_properties: Create aliases on source for all target properties
102
+ * @target: Device which has properties to be aliased
103
+ * @source: Object to add alias properties to
104
+ *
105
+ * Add alias properties to the @source object for all qdev properties on
106
+ * the @target DeviceState.
107
+ *
108
+ * This is useful when @target is an internal implementation object
109
+ * owned by @source, and you want to expose all the properties of that
110
+ * implementation object as properties on the @source object so that users
111
+ * of @source can set them.
112
+ */
113
void qdev_alias_all_properties(DeviceState *target, Object *source);
114
115
/**
116
diff --git a/hw/core/qdev.c b/hw/core/qdev.c
117
index XXXXXXX..XXXXXXX 100644
118
--- a/hw/core/qdev.c
119
+++ b/hw/core/qdev.c
120
@@ -XXX,XX +XXX,XX @@ void qdev_set_parent_bus(DeviceState *dev, BusState *bus)
121
}
49
}
122
}
50
123
51
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
124
-/*
52
+static void exynos4210_realize(DeviceState *socdev, Error **errp)
125
- * Create a device on the heap.
126
- * A type @name must exist.
127
- * This only initializes the device state structure and allows
128
- * properties to be set. The device still needs to be realized. See
129
- * qdev-core.h.
130
- */
131
DeviceState *qdev_new(const char *name)
53
{
132
{
54
- Exynos4210State *s = g_new0(Exynos4210State, 1);
133
if (!object_class_by_name(name)) {
55
+ Exynos4210State *s = EXYNOS4210_SOC(socdev);
134
@@ -XXX,XX +XXX,XX @@ DeviceState *qdev_new(const char *name)
56
+ MemoryRegion *system_mem = get_system_memory();
135
return DEVICE(object_new(name));
57
qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
58
SysBusDevice *busdev;
59
DeviceState *dev;
60
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
61
qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
62
pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
63
qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
64
-
65
- return s;
66
}
136
}
67
+
137
68
+static void exynos4210_class_init(ObjectClass *klass, void *data)
138
-/*
69
+{
139
- * Try to create a device on the heap.
70
+ DeviceClass *dc = DEVICE_CLASS(klass);
140
- * This is like qdev_new(), except it returns %NULL when type @name
71
+
141
- * does not exist.
72
+ dc->realize = exynos4210_realize;
142
- */
73
+}
143
DeviceState *qdev_try_new(const char *name)
74
+
144
{
75
+static const TypeInfo exynos4210_info = {
145
if (!module_object_class_by_name(name)) {
76
+ .name = TYPE_EXYNOS4210_SOC,
146
@@ -XXX,XX +XXX,XX @@ void qdev_simple_device_unplug_cb(HotplugHandler *hotplug_dev,
77
+ .parent = TYPE_SYS_BUS_DEVICE,
147
qdev_unrealize(dev);
78
+ .instance_size = sizeof(Exynos4210State),
79
+ .class_init = exynos4210_class_init,
80
+};
81
+
82
+static void exynos4210_register_types(void)
83
+{
84
+ type_register_static(&exynos4210_info);
85
+}
86
+
87
+type_init(exynos4210_register_types)
88
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
89
index XXXXXXX..XXXXXXX 100644
90
--- a/hw/arm/exynos4_boards.c
91
+++ b/hw/arm/exynos4_boards.c
92
@@ -XXX,XX +XXX,XX @@ typedef enum Exynos4BoardType {
93
} Exynos4BoardType;
94
95
typedef struct Exynos4BoardState {
96
- Exynos4210State *soc;
97
+ Exynos4210State soc;
98
MemoryRegion dram0_mem;
99
MemoryRegion dram1_mem;
100
} Exynos4BoardState;
101
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
102
exynos4_boards_init_ram(s, get_system_memory(),
103
exynos4_board_ram_size[board_type]);
104
105
- s->soc = exynos4210_init(get_system_memory());
106
+ object_initialize(&s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC);
107
+ qdev_set_parent_bus(DEVICE(&s->soc), sysbus_get_default());
108
+ object_property_set_bool(OBJECT(&s->soc), true, "realized",
109
+ &error_fatal);
110
111
return s;
112
}
148
}
113
@@ -XXX,XX +XXX,XX @@ static void smdkc210_init(MachineState *machine)
149
114
EXYNOS4_BOARD_SMDKC210);
150
-/*
115
151
- * Realize @dev.
116
lan9215_init(SMDK_LAN9118_BASE_ADDR,
152
- * @dev must not be plugged into a bus.
117
- qemu_irq_invert(s->soc->irq_table[exynos4210_get_irq(37, 1)]));
153
- * If @bus, plug @dev into @bus. This takes a reference to @dev.
118
+ qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)]));
154
- * If @dev has no QOM parent, make one up, taking another reference.
119
arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo);
155
- * On success, return true.
156
- * On failure, store an error through @errp and return false.
157
- */
158
bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp)
159
{
160
assert(!dev->realized && !dev->parent_bus);
161
@@ -XXX,XX +XXX,XX @@ bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp)
162
return object_property_set_bool(OBJECT(dev), "realized", true, errp);
120
}
163
}
121
164
165
-/*
166
- * Realize @dev and drop a reference.
167
- * This is like qdev_realize(), except the caller must hold a
168
- * (private) reference, which is dropped on return regardless of
169
- * success or failure. Intended use:
170
- * dev = qdev_new();
171
- * [...]
172
- * qdev_realize_and_unref(dev, bus, errp);
173
- * Now @dev can go away without further ado.
174
- */
175
bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp)
176
{
177
bool ret;
178
@@ -XXX,XX +XXX,XX @@ static void qdev_class_add_property(DeviceClass *klass, Property *prop)
179
prop->info->description);
180
}
181
182
-/* @qdev_alias_all_properties - Add alias properties to the source object for
183
- * all qdev properties on the target DeviceState.
184
- */
185
void qdev_alias_all_properties(DeviceState *target, Object *source)
186
{
187
ObjectClass *class;
122
--
188
--
123
2.20.1
189
2.20.1
124
190
125
191
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Add a doc comment for qdev_unrealize(), to go with the new
2
documentation for the realize part of the qdev lifecycle.
2
3
3
It eases code review, unit is explicit.
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20200711142425.16283-3-peter.maydell@linaro.org
7
---
8
include/hw/qdev-core.h | 19 +++++++++++++++++++
9
1 file changed, 19 insertions(+)
4
10
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Message-id: 20190520214342.13709-3-philmd@redhat.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
hw/arm/exynos4_boards.c | 5 +++--
11
1 file changed, 3 insertions(+), 2 deletions(-)
12
13
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
14
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/exynos4_boards.c
13
--- a/include/hw/qdev-core.h
16
+++ b/hw/arm/exynos4_boards.c
14
+++ b/include/hw/qdev-core.h
17
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@ bool qdev_realize(DeviceState *dev, BusState *bus, Error **errp);
16
* would be incorrect. For that use case you want qdev_realize().
18
*/
17
*/
19
18
bool qdev_realize_and_unref(DeviceState *dev, BusState *bus, Error **errp);
20
#include "qemu/osdep.h"
19
+/**
21
+#include "qemu/units.h"
20
+ * qdev_unrealize: Unrealize a device
22
#include "qapi/error.h"
21
+ * @dev: device to unrealize
23
#include "qemu/error-report.h"
22
+ *
24
#include "qemu-common.h"
23
+ * This function will "unrealize" a device, which is the first phase
25
@@ -XXX,XX +XXX,XX @@ static int exynos4_board_smp_bootreg_addr[EXYNOS4_NUM_OF_BOARDS] = {
24
+ * of correctly destroying a device that has been realized. It will:
26
};
25
+ *
27
26
+ * - unrealize any child buses by calling qbus_unrealize()
28
static unsigned long exynos4_board_ram_size[EXYNOS4_NUM_OF_BOARDS] = {
27
+ * (this will recursively unrealize any devices on those buses)
29
- [EXYNOS4_BOARD_NURI] = 0x40000000,
28
+ * - call the the unrealize method of @dev
30
- [EXYNOS4_BOARD_SMDKC210] = 0x40000000,
29
+ *
31
+ [EXYNOS4_BOARD_NURI] = 1 * GiB,
30
+ * The device can then be freed by causing its reference count to go
32
+ [EXYNOS4_BOARD_SMDKC210] = 1 * GiB,
31
+ * to zero.
33
};
32
+ *
34
33
+ * Warning: most devices in QEMU do not expect to be unrealized. Only
35
static struct arm_boot_info exynos4_board_binfo = {
34
+ * devices which are hot-unpluggable should be unrealized (as part of
35
+ * the unplugging process); all other devices are expected to last for
36
+ * the life of the simulation and should not be unrealized and freed.
37
+ */
38
void qdev_unrealize(DeviceState *dev);
39
void qdev_set_legacy_instance_id(DeviceState *dev, int alias_id,
40
int required_for_version);
36
--
41
--
37
2.20.1
42
2.20.1
38
43
39
44
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Add documentation comments for the various qdev functions
2
2
related to creating and connecting GPIO lines.
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
3
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Message-id: 20190520214342.13709-2-philmd@redhat.com
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20200711142425.16283-4-peter.maydell@linaro.org
7
---
7
---
8
hw/arm/exynos4_boards.c | 24 ------------------------
8
include/hw/qdev-core.h | 191 ++++++++++++++++++++++++++++++++++++++++-
9
1 file changed, 24 deletions(-)
9
1 file changed, 189 insertions(+), 2 deletions(-)
10
10
11
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
11
diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h
12
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/arm/exynos4_boards.c
13
--- a/include/hw/qdev-core.h
14
+++ b/hw/arm/exynos4_boards.c
14
+++ b/include/hw/qdev-core.h
15
@@ -XXX,XX +XXX,XX @@
15
@@ -XXX,XX +XXX,XX @@ void qdev_simple_device_unplug_cb(HotplugHandler *hotplug_dev,
16
#include "hw/net/lan9118.h"
16
void qdev_machine_creation_done(void);
17
#include "hw/boards.h"
17
bool qdev_machine_modified(void);
18
18
19
-#undef DEBUG
19
+/**
20
-
20
+ * qdev_get_gpio_in: Get one of a device's anonymous input GPIO lines
21
-//#define DEBUG
21
+ * @dev: Device whose GPIO we want
22
-
22
+ * @n: Number of the anonymous GPIO line (which must be in range)
23
-#ifdef DEBUG
23
+ *
24
- #undef PRINT_DEBUG
24
+ * Returns the qemu_irq corresponding to an anonymous input GPIO line
25
- #define PRINT_DEBUG(fmt, args...) \
25
+ * (which the device has set up with qdev_init_gpio_in()). The index
26
- do { \
26
+ * @n of the GPIO line must be valid (i.e. be at least 0 and less than
27
- fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
27
+ * the total number of anonymous input GPIOs the device has); this
28
- } while (0)
28
+ * function will assert() if passed an invalid index.
29
-#else
29
+ *
30
- #define PRINT_DEBUG(fmt, args...) do {} while (0)
30
+ * This function is intended to be used by board code or SoC "container"
31
-#endif
31
+ * device models to wire up the GPIO lines; usually the return value
32
-
32
+ * will be passed to qdev_connect_gpio_out() or a similar function to
33
#define SMDK_LAN9118_BASE_ADDR 0x05000000
33
+ * connect another device's output GPIO line to this input.
34
34
+ *
35
typedef enum Exynos4BoardType {
35
+ * For named input GPIO lines, use qdev_get_gpio_in_named().
36
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
36
+ */
37
exynos4_board_binfo.gic_cpu_if_addr =
37
qemu_irq qdev_get_gpio_in(DeviceState *dev, int n);
38
EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100;
38
+/**
39
39
+ * qdev_get_gpio_in_named: Get one of a device's named input GPIO lines
40
- PRINT_DEBUG("\n ram_size: %luMiB [0x%08lx]\n"
40
+ * @dev: Device whose GPIO we want
41
- " kernel_filename: %s\n"
41
+ * @name: Name of the input GPIO array
42
- " kernel_cmdline: %s\n"
42
+ * @n: Number of the GPIO line in that array (which must be in range)
43
- " initrd_filename: %s\n",
43
+ *
44
- exynos4_board_ram_size[board_type] / 1048576,
44
+ * Returns the qemu_irq corresponding to a named input GPIO line
45
- exynos4_board_ram_size[board_type],
45
+ * (which the device has set up with qdev_init_gpio_in_named()).
46
- machine->kernel_filename,
46
+ * The @name string must correspond to an input GPIO array which exists on
47
- machine->kernel_cmdline,
47
+ * the device, and the index @n of the GPIO line must be valid (i.e.
48
- machine->initrd_filename);
48
+ * be at least 0 and less than the total number of input GPIOs in that
49
-
49
+ * array); this function will assert() if passed an invalid name or index.
50
exynos4_boards_init_ram(s, get_system_memory(),
50
+ *
51
exynos4_board_ram_size[board_type]);
51
+ * For anonymous input GPIO lines, use qdev_get_gpio_in().
52
+ */
53
qemu_irq qdev_get_gpio_in_named(DeviceState *dev, const char *name, int n);
54
55
+/**
56
+ * qdev_connect_gpio_out: Connect one of a device's anonymous output GPIO lines
57
+ * @dev: Device whose GPIO to connect
58
+ * @n: Number of the anonymous output GPIO line (which must be in range)
59
+ * @pin: qemu_irq to connect the output line to
60
+ *
61
+ * This function connects an anonymous output GPIO line on a device
62
+ * up to an arbitrary qemu_irq, so that when the device asserts that
63
+ * output GPIO line, the qemu_irq's callback is invoked.
64
+ * The index @n of the GPIO line must be valid (i.e. be at least 0 and
65
+ * less than the total number of anonymous output GPIOs the device has
66
+ * created with qdev_init_gpio_out()); otherwise this function will assert().
67
+ *
68
+ * Outbound GPIO lines can be connected to any qemu_irq, but the common
69
+ * case is connecting them to another device's inbound GPIO line, using
70
+ * the qemu_irq returned by qdev_get_gpio_in() or qdev_get_gpio_in_named().
71
+ *
72
+ * It is not valid to try to connect one outbound GPIO to multiple
73
+ * qemu_irqs at once, or to connect multiple outbound GPIOs to the
74
+ * same qemu_irq. (Warning: there is no assertion or other guard to
75
+ * catch this error: the model will just not do the right thing.)
76
+ * Instead, for fan-out you can use the TYPE_IRQ_SPLIT device: connect
77
+ * a device's outbound GPIO to the splitter's input, and connect each
78
+ * of the splitter's outputs to a different device. For fan-in you
79
+ * can use the TYPE_OR_IRQ device, which is a model of a logical OR
80
+ * gate with multiple inputs and one output.
81
+ *
82
+ * For named output GPIO lines, use qdev_connect_gpio_out_named().
83
+ */
84
void qdev_connect_gpio_out(DeviceState *dev, int n, qemu_irq pin);
85
+/**
86
+ * qdev_connect_gpio_out: Connect one of a device's anonymous output GPIO lines
87
+ * @dev: Device whose GPIO to connect
88
+ * @name: Name of the output GPIO array
89
+ * @n: Number of the anonymous output GPIO line (which must be in range)
90
+ * @pin: qemu_irq to connect the output line to
91
+ *
92
+ * This function connects an anonymous output GPIO line on a device
93
+ * up to an arbitrary qemu_irq, so that when the device asserts that
94
+ * output GPIO line, the qemu_irq's callback is invoked.
95
+ * The @name string must correspond to an output GPIO array which exists on
96
+ * the device, and the index @n of the GPIO line must be valid (i.e.
97
+ * be at least 0 and less than the total number of input GPIOs in that
98
+ * array); this function will assert() if passed an invalid name or index.
99
+ *
100
+ * Outbound GPIO lines can be connected to any qemu_irq, but the common
101
+ * case is connecting them to another device's inbound GPIO line, using
102
+ * the qemu_irq returned by qdev_get_gpio_in() or qdev_get_gpio_in_named().
103
+ *
104
+ * It is not valid to try to connect one outbound GPIO to multiple
105
+ * qemu_irqs at once, or to connect multiple outbound GPIOs to the
106
+ * same qemu_irq; see qdev_connect_gpio_out() for details.
107
+ *
108
+ * For named output GPIO lines, use qdev_connect_gpio_out_named().
109
+ */
110
void qdev_connect_gpio_out_named(DeviceState *dev, const char *name, int n,
111
qemu_irq pin);
112
+/**
113
+ * qdev_get_gpio_out_connector: Get the qemu_irq connected to an output GPIO
114
+ * @dev: Device whose output GPIO we are interested in
115
+ * @name: Name of the output GPIO array
116
+ * @n: Number of the output GPIO line within that array
117
+ *
118
+ * Returns whatever qemu_irq is currently connected to the specified
119
+ * output GPIO line of @dev. This will be NULL if the output GPIO line
120
+ * has never been wired up to the anything. Note that the qemu_irq
121
+ * returned does not belong to @dev -- it will be the input GPIO or
122
+ * IRQ of whichever device the board code has connected up to @dev's
123
+ * output GPIO.
124
+ *
125
+ * You probably don't need to use this function -- it is used only
126
+ * by the platform-bus subsystem.
127
+ */
128
qemu_irq qdev_get_gpio_out_connector(DeviceState *dev, const char *name, int n);
129
+/**
130
+ * qdev_intercept_gpio_out: Intercept an existing GPIO connection
131
+ * @dev: Device to intercept the outbound GPIO line from
132
+ * @icpt: New qemu_irq to connect instead
133
+ * @name: Name of the output GPIO array
134
+ * @n: Number of the GPIO line in the array
135
+ *
136
+ * This function is provided only for use by the qtest testing framework
137
+ * and is not suitable for use in non-testing parts of QEMU.
138
+ *
139
+ * This function breaks an existing connection of an outbound GPIO
140
+ * line from @dev, and replaces it with the new qemu_irq @icpt, as if
141
+ * ``qdev_connect_gpio_out_named(dev, icpt, name, n)`` had been called.
142
+ * The previously connected qemu_irq is returned, so it can be restored
143
+ * by a second call to qdev_intercept_gpio_out() if desired.
144
+ */
145
qemu_irq qdev_intercept_gpio_out(DeviceState *dev, qemu_irq icpt,
146
const char *name, int n);
147
148
@@ -XXX,XX +XXX,XX @@ BusState *qdev_get_child_bus(DeviceState *dev, const char *name);
149
150
/*** Device API. ***/
151
152
-/* Register device properties. */
153
-/* GPIO inputs also double as IRQ sinks. */
154
+/**
155
+ * qdev_init_gpio_in: create an array of anonymous input GPIO lines
156
+ * @dev: Device to create input GPIOs for
157
+ * @handler: Function to call when GPIO line value is set
158
+ * @n: Number of GPIO lines to create
159
+ *
160
+ * Devices should use functions in the qdev_init_gpio_in* family in
161
+ * their instance_init or realize methods to create any input GPIO
162
+ * lines they need. There is no functional difference between
163
+ * anonymous and named GPIO lines. Stylistically, named GPIOs are
164
+ * preferable (easier to understand at callsites) unless a device
165
+ * has exactly one uniform kind of GPIO input whose purpose is obvious.
166
+ * Note that input GPIO lines can serve as 'sinks' for IRQ lines.
167
+ *
168
+ * See qdev_get_gpio_in() for how code that uses such a device can get
169
+ * hold of an input GPIO line to manipulate it.
170
+ */
171
void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n);
172
+/**
173
+ * qdev_init_gpio_out: create an array of anonymous output GPIO lines
174
+ * @dev: Device to create output GPIOs for
175
+ * @pins: Pointer to qemu_irq or qemu_irq array for the GPIO lines
176
+ * @n: Number of GPIO lines to create
177
+ *
178
+ * Devices should use functions in the qdev_init_gpio_out* family
179
+ * in their instance_init or realize methods to create any output
180
+ * GPIO lines they need. There is no functional difference between
181
+ * anonymous and named GPIO lines. Stylistically, named GPIOs are
182
+ * preferable (easier to understand at callsites) unless a device
183
+ * has exactly one uniform kind of GPIO output whose purpose is obvious.
184
+ *
185
+ * The @pins argument should be a pointer to either a "qemu_irq"
186
+ * (if @n == 1) or a "qemu_irq []" array (if @n > 1) in the device's
187
+ * state structure. The device implementation can then raise and
188
+ * lower the GPIO line by calling qemu_set_irq(). (If anything is
189
+ * connected to the other end of the GPIO this will cause the handler
190
+ * function for that input GPIO to be called.)
191
+ *
192
+ * See qdev_connect_gpio_out() for how code that uses such a device
193
+ * can connect to one of its output GPIO lines.
194
+ */
195
void qdev_init_gpio_out(DeviceState *dev, qemu_irq *pins, int n);
196
+/**
197
+ * qdev_init_gpio_out: create an array of named output GPIO lines
198
+ * @dev: Device to create output GPIOs for
199
+ * @pins: Pointer to qemu_irq or qemu_irq array for the GPIO lines
200
+ * @name: Name to give this array of GPIO lines
201
+ * @n: Number of GPIO lines to create
202
+ *
203
+ * Like qdev_init_gpio_out(), but creates an array of GPIO output lines
204
+ * with a name. Code using the device can then connect these GPIO lines
205
+ * using qdev_connect_gpio_out_named().
206
+ */
207
void qdev_init_gpio_out_named(DeviceState *dev, qemu_irq *pins,
208
const char *name, int n);
209
/**
210
@@ -XXX,XX +XXX,XX @@ static inline void qdev_init_gpio_in_named(DeviceState *dev,
211
qdev_init_gpio_in_named_with_opaque(dev, handler, dev, name, n);
212
}
213
214
+/**
215
+ * qdev_pass_gpios: create GPIO lines on container which pass through to device
216
+ * @dev: Device which has GPIO lines
217
+ * @container: Container device which needs to expose them
218
+ * @name: Name of GPIO array to pass through (NULL for the anonymous GPIO array)
219
+ *
220
+ * In QEMU, complicated devices like SoCs are often modelled with a
221
+ * "container" QOM device which itself contains other QOM devices and
222
+ * which wires them up appropriately. This function allows the container
223
+ * to create GPIO arrays on itself which simply pass through to a GPIO
224
+ * array of one of its internal devices.
225
+ *
226
+ * If @dev has both input and output GPIOs named @name then both will
227
+ * be passed through. It is not possible to pass a subset of the array
228
+ * with this function.
229
+ *
230
+ * To users of the container device, the GPIO array created on @container
231
+ * behaves exactly like any other.
232
+ */
233
void qdev_pass_gpios(DeviceState *dev, DeviceState *container,
234
const char *name);
52
235
53
--
236
--
54
2.20.1
237
2.20.1
55
238
56
239
diff view generated by jsdifflib
1
The header file hw/arm/arm.h now includes only declarations
1
In armsse_realize() we have a loop over [0, info->num_cpus), which
2
relating to hw/arm/boot.c functionality. Rename it accordingly,
2
indexes into various fixed-size arrays in the ARMSSE struct. This
3
and adjust its header comment.
3
confuses Coverity, which warns that we might overrun those arrays
4
4
(CID 1430326, 1430337, 1430371, 1430414, 1430430). This can't
5
The bulk of this commit was created via
5
actually happen, because the info struct is always one of the entries
6
perl -pi -e 's|hw/arm/arm.h|hw/arm/boot.h|' hw/arm/*.c include/hw/arm/*.h
6
in the armsse_variants[] array and num_cpus is either 1 or 2; we also
7
7
already assert in armsse_init() that num_cpus is not too large.
8
In a few cases we can just delete the #include:
8
However, adding an assert to armsse_realize() like the one in
9
hw/arm/msf2-soc.c, include/hw/arm/aspeed_soc.h and
9
armsse_init() should help Coverity figure out that these code paths
10
include/hw/arm/bcm2836.h did not require it.
10
aren't possible.
11
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Message-id: 20200713143716.9881-1-peter.maydell@linaro.org
15
Message-id: 20190516163857.6430-4-peter.maydell@linaro.org
16
---
15
---
17
include/hw/arm/allwinner-a10.h | 2 +-
16
hw/arm/armsse.c | 2 ++
18
include/hw/arm/aspeed_soc.h | 1 -
17
1 file changed, 2 insertions(+)
19
include/hw/arm/bcm2836.h | 1 -
20
include/hw/arm/{arm.h => boot.h} | 8 ++++----
21
include/hw/arm/fsl-imx25.h | 2 +-
22
include/hw/arm/fsl-imx31.h | 2 +-
23
include/hw/arm/fsl-imx6.h | 2 +-
24
include/hw/arm/fsl-imx6ul.h | 2 +-
25
include/hw/arm/fsl-imx7.h | 2 +-
26
include/hw/arm/virt.h | 2 +-
27
include/hw/arm/xlnx-versal.h | 2 +-
28
include/hw/arm/xlnx-zynqmp.h | 2 +-
29
hw/arm/armsse.c | 2 +-
30
hw/arm/armv7m.c | 2 +-
31
hw/arm/aspeed.c | 2 +-
32
hw/arm/boot.c | 2 +-
33
hw/arm/collie.c | 2 +-
34
hw/arm/exynos4210.c | 2 +-
35
hw/arm/exynos4_boards.c | 2 +-
36
hw/arm/highbank.c | 2 +-
37
hw/arm/integratorcp.c | 2 +-
38
hw/arm/mainstone.c | 2 +-
39
hw/arm/microbit.c | 2 +-
40
hw/arm/mps2-tz.c | 2 +-
41
hw/arm/mps2.c | 2 +-
42
hw/arm/msf2-soc.c | 1 -
43
hw/arm/msf2-som.c | 2 +-
44
hw/arm/musca.c | 2 +-
45
hw/arm/musicpal.c | 2 +-
46
hw/arm/netduino2.c | 2 +-
47
hw/arm/nrf51_soc.c | 2 +-
48
hw/arm/nseries.c | 2 +-
49
hw/arm/omap1.c | 2 +-
50
hw/arm/omap2.c | 2 +-
51
hw/arm/omap_sx1.c | 2 +-
52
hw/arm/palm.c | 2 +-
53
hw/arm/raspi.c | 2 +-
54
hw/arm/realview.c | 2 +-
55
hw/arm/spitz.c | 2 +-
56
hw/arm/stellaris.c | 2 +-
57
hw/arm/stm32f205_soc.c | 2 +-
58
hw/arm/strongarm.c | 2 +-
59
hw/arm/tosa.c | 2 +-
60
hw/arm/versatilepb.c | 2 +-
61
hw/arm/vexpress.c | 2 +-
62
hw/arm/virt.c | 2 +-
63
hw/arm/xilinx_zynq.c | 2 +-
64
hw/arm/xlnx-versal.c | 2 +-
65
hw/arm/z2.c | 2 +-
66
49 files changed, 49 insertions(+), 52 deletions(-)
67
rename include/hw/arm/{arm.h => boot.h} (98%)
68
18
69
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
70
index XXXXXXX..XXXXXXX 100644
71
--- a/include/hw/arm/allwinner-a10.h
72
+++ b/include/hw/arm/allwinner-a10.h
73
@@ -XXX,XX +XXX,XX @@
74
#include "qemu-common.h"
75
#include "qemu/error-report.h"
76
#include "hw/char/serial.h"
77
-#include "hw/arm/arm.h"
78
+#include "hw/arm/boot.h"
79
#include "hw/timer/allwinner-a10-pit.h"
80
#include "hw/intc/allwinner-a10-pic.h"
81
#include "hw/net/allwinner_emac.h"
82
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
83
index XXXXXXX..XXXXXXX 100644
84
--- a/include/hw/arm/aspeed_soc.h
85
+++ b/include/hw/arm/aspeed_soc.h
86
@@ -XXX,XX +XXX,XX @@
87
#ifndef ASPEED_SOC_H
88
#define ASPEED_SOC_H
89
90
-#include "hw/arm/arm.h"
91
#include "hw/intc/aspeed_vic.h"
92
#include "hw/misc/aspeed_scu.h"
93
#include "hw/misc/aspeed_sdmc.h"
94
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
95
index XXXXXXX..XXXXXXX 100644
96
--- a/include/hw/arm/bcm2836.h
97
+++ b/include/hw/arm/bcm2836.h
98
@@ -XXX,XX +XXX,XX @@
99
#ifndef BCM2836_H
100
#define BCM2836_H
101
102
-#include "hw/arm/arm.h"
103
#include "hw/arm/bcm2835_peripherals.h"
104
#include "hw/intc/bcm2836_control.h"
105
106
diff --git a/include/hw/arm/arm.h b/include/hw/arm/boot.h
107
similarity index 98%
108
rename from include/hw/arm/arm.h
109
rename to include/hw/arm/boot.h
110
index XXXXXXX..XXXXXXX 100644
111
--- a/include/hw/arm/arm.h
112
+++ b/include/hw/arm/boot.h
113
@@ -XXX,XX +XXX,XX @@
114
/*
115
- * Misc ARM declarations
116
+ * ARM kernel loader.
117
*
118
* Copyright (c) 2006 CodeSourcery.
119
* Written by Paul Brook
120
@@ -XXX,XX +XXX,XX @@
121
*
122
*/
123
124
-#ifndef HW_ARM_H
125
-#define HW_ARM_H
126
+#ifndef HW_ARM_BOOT_H
127
+#define HW_ARM_BOOT_H
128
129
#include "exec/memory.h"
130
#include "target/arm/cpu-qom.h"
131
@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
132
const struct arm_boot_info *info,
133
hwaddr mvbar_addr);
134
135
-#endif /* HW_ARM_H */
136
+#endif /* HW_ARM_BOOT_H */
137
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
138
index XXXXXXX..XXXXXXX 100644
139
--- a/include/hw/arm/fsl-imx25.h
140
+++ b/include/hw/arm/fsl-imx25.h
141
@@ -XXX,XX +XXX,XX @@
142
#ifndef FSL_IMX25_H
143
#define FSL_IMX25_H
144
145
-#include "hw/arm/arm.h"
146
+#include "hw/arm/boot.h"
147
#include "hw/intc/imx_avic.h"
148
#include "hw/misc/imx25_ccm.h"
149
#include "hw/char/imx_serial.h"
150
diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h
151
index XXXXXXX..XXXXXXX 100644
152
--- a/include/hw/arm/fsl-imx31.h
153
+++ b/include/hw/arm/fsl-imx31.h
154
@@ -XXX,XX +XXX,XX @@
155
#ifndef FSL_IMX31_H
156
#define FSL_IMX31_H
157
158
-#include "hw/arm/arm.h"
159
+#include "hw/arm/boot.h"
160
#include "hw/intc/imx_avic.h"
161
#include "hw/misc/imx31_ccm.h"
162
#include "hw/char/imx_serial.h"
163
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
164
index XXXXXXX..XXXXXXX 100644
165
--- a/include/hw/arm/fsl-imx6.h
166
+++ b/include/hw/arm/fsl-imx6.h
167
@@ -XXX,XX +XXX,XX @@
168
#ifndef FSL_IMX6_H
169
#define FSL_IMX6_H
170
171
-#include "hw/arm/arm.h"
172
+#include "hw/arm/boot.h"
173
#include "hw/cpu/a9mpcore.h"
174
#include "hw/misc/imx6_ccm.h"
175
#include "hw/misc/imx6_src.h"
176
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
177
index XXXXXXX..XXXXXXX 100644
178
--- a/include/hw/arm/fsl-imx6ul.h
179
+++ b/include/hw/arm/fsl-imx6ul.h
180
@@ -XXX,XX +XXX,XX @@
181
#ifndef FSL_IMX6UL_H
182
#define FSL_IMX6UL_H
183
184
-#include "hw/arm/arm.h"
185
+#include "hw/arm/boot.h"
186
#include "hw/cpu/a15mpcore.h"
187
#include "hw/misc/imx6ul_ccm.h"
188
#include "hw/misc/imx6_src.h"
189
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
190
index XXXXXXX..XXXXXXX 100644
191
--- a/include/hw/arm/fsl-imx7.h
192
+++ b/include/hw/arm/fsl-imx7.h
193
@@ -XXX,XX +XXX,XX @@
194
#ifndef FSL_IMX7_H
195
#define FSL_IMX7_H
196
197
-#include "hw/arm/arm.h"
198
+#include "hw/arm/boot.h"
199
#include "hw/cpu/a15mpcore.h"
200
#include "hw/intc/imx_gpcv2.h"
201
#include "hw/misc/imx7_ccm.h"
202
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
203
index XXXXXXX..XXXXXXX 100644
204
--- a/include/hw/arm/virt.h
205
+++ b/include/hw/arm/virt.h
206
@@ -XXX,XX +XXX,XX @@
207
#include "exec/hwaddr.h"
208
#include "qemu/notify.h"
209
#include "hw/boards.h"
210
-#include "hw/arm/arm.h"
211
+#include "hw/arm/boot.h"
212
#include "hw/block/flash.h"
213
#include "sysemu/kvm.h"
214
#include "hw/intc/arm_gicv3_common.h"
215
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
216
index XXXXXXX..XXXXXXX 100644
217
--- a/include/hw/arm/xlnx-versal.h
218
+++ b/include/hw/arm/xlnx-versal.h
219
@@ -XXX,XX +XXX,XX @@
220
#define XLNX_VERSAL_H
221
222
#include "hw/sysbus.h"
223
-#include "hw/arm/arm.h"
224
+#include "hw/arm/boot.h"
225
#include "hw/intc/arm_gicv3.h"
226
227
#define TYPE_XLNX_VERSAL "xlnx-versal"
228
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
229
index XXXXXXX..XXXXXXX 100644
230
--- a/include/hw/arm/xlnx-zynqmp.h
231
+++ b/include/hw/arm/xlnx-zynqmp.h
232
@@ -XXX,XX +XXX,XX @@
233
#ifndef XLNX_ZYNQMP_H
234
235
#include "qemu-common.h"
236
-#include "hw/arm/arm.h"
237
+#include "hw/arm/boot.h"
238
#include "hw/intc/arm_gic.h"
239
#include "hw/net/cadence_gem.h"
240
#include "hw/char/cadence_uart.h"
241
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
19
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
242
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
243
--- a/hw/arm/armsse.c
21
--- a/hw/arm/armsse.c
244
+++ b/hw/arm/armsse.c
22
+++ b/hw/arm/armsse.c
245
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
246
#include "hw/sysbus.h"
24
return;
247
#include "hw/registerfields.h"
25
}
248
#include "hw/arm/armsse.h"
26
249
-#include "hw/arm/arm.h"
27
+ assert(info->num_cpus <= SSE_MAX_CPUS);
250
+#include "hw/arm/boot.h"
28
+
251
29
/* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */
252
/* Format of the System Information block SYS_CONFIG register */
30
assert(is_power_of_2(info->sram_banks));
253
typedef enum SysConfigFormat {
31
addr_width_max = 24 - ctz32(info->sram_banks);
254
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
255
index XXXXXXX..XXXXXXX 100644
256
--- a/hw/arm/armv7m.c
257
+++ b/hw/arm/armv7m.c
258
@@ -XXX,XX +XXX,XX @@
259
#include "qemu-common.h"
260
#include "cpu.h"
261
#include "hw/sysbus.h"
262
-#include "hw/arm/arm.h"
263
+#include "hw/arm/boot.h"
264
#include "hw/loader.h"
265
#include "elf.h"
266
#include "sysemu/qtest.h"
267
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
268
index XXXXXXX..XXXXXXX 100644
269
--- a/hw/arm/aspeed.c
270
+++ b/hw/arm/aspeed.c
271
@@ -XXX,XX +XXX,XX @@
272
#include "qemu-common.h"
273
#include "cpu.h"
274
#include "exec/address-spaces.h"
275
-#include "hw/arm/arm.h"
276
+#include "hw/arm/boot.h"
277
#include "hw/arm/aspeed.h"
278
#include "hw/arm/aspeed_soc.h"
279
#include "hw/boards.h"
280
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
281
index XXXXXXX..XXXXXXX 100644
282
--- a/hw/arm/boot.c
283
+++ b/hw/arm/boot.c
284
@@ -XXX,XX +XXX,XX @@
285
#include "qapi/error.h"
286
#include <libfdt.h>
287
#include "hw/hw.h"
288
-#include "hw/arm/arm.h"
289
+#include "hw/arm/boot.h"
290
#include "hw/arm/linux-boot-if.h"
291
#include "sysemu/kvm.h"
292
#include "sysemu/sysemu.h"
293
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
294
index XXXXXXX..XXXXXXX 100644
295
--- a/hw/arm/collie.c
296
+++ b/hw/arm/collie.c
297
@@ -XXX,XX +XXX,XX @@
298
#include "hw/sysbus.h"
299
#include "hw/boards.h"
300
#include "strongarm.h"
301
-#include "hw/arm/arm.h"
302
+#include "hw/arm/boot.h"
303
#include "hw/block/flash.h"
304
#include "exec/address-spaces.h"
305
#include "cpu.h"
306
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
307
index XXXXXXX..XXXXXXX 100644
308
--- a/hw/arm/exynos4210.c
309
+++ b/hw/arm/exynos4210.c
310
@@ -XXX,XX +XXX,XX @@
311
#include "hw/boards.h"
312
#include "sysemu/sysemu.h"
313
#include "hw/sysbus.h"
314
-#include "hw/arm/arm.h"
315
+#include "hw/arm/boot.h"
316
#include "hw/loader.h"
317
#include "hw/arm/exynos4210.h"
318
#include "hw/sd/sdhci.h"
319
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
320
index XXXXXXX..XXXXXXX 100644
321
--- a/hw/arm/exynos4_boards.c
322
+++ b/hw/arm/exynos4_boards.c
323
@@ -XXX,XX +XXX,XX @@
324
#include "sysemu/sysemu.h"
325
#include "hw/sysbus.h"
326
#include "net/net.h"
327
-#include "hw/arm/arm.h"
328
+#include "hw/arm/boot.h"
329
#include "exec/address-spaces.h"
330
#include "hw/arm/exynos4210.h"
331
#include "hw/net/lan9118.h"
332
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
333
index XXXXXXX..XXXXXXX 100644
334
--- a/hw/arm/highbank.c
335
+++ b/hw/arm/highbank.c
336
@@ -XXX,XX +XXX,XX @@
337
#include "qemu/osdep.h"
338
#include "qapi/error.h"
339
#include "hw/sysbus.h"
340
-#include "hw/arm/arm.h"
341
+#include "hw/arm/boot.h"
342
#include "hw/loader.h"
343
#include "net/net.h"
344
#include "sysemu/kvm.h"
345
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
346
index XXXXXXX..XXXXXXX 100644
347
--- a/hw/arm/integratorcp.c
348
+++ b/hw/arm/integratorcp.c
349
@@ -XXX,XX +XXX,XX @@
350
#include "cpu.h"
351
#include "hw/sysbus.h"
352
#include "hw/boards.h"
353
-#include "hw/arm/arm.h"
354
+#include "hw/arm/boot.h"
355
#include "hw/misc/arm_integrator_debug.h"
356
#include "hw/net/smc91c111.h"
357
#include "net/net.h"
358
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
359
index XXXXXXX..XXXXXXX 100644
360
--- a/hw/arm/mainstone.c
361
+++ b/hw/arm/mainstone.c
362
@@ -XXX,XX +XXX,XX @@
363
#include "qapi/error.h"
364
#include "hw/hw.h"
365
#include "hw/arm/pxa.h"
366
-#include "hw/arm/arm.h"
367
+#include "hw/arm/boot.h"
368
#include "net/net.h"
369
#include "hw/net/smc91c111.h"
370
#include "hw/boards.h"
371
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
372
index XXXXXXX..XXXXXXX 100644
373
--- a/hw/arm/microbit.c
374
+++ b/hw/arm/microbit.c
375
@@ -XXX,XX +XXX,XX @@
376
#include "qemu/osdep.h"
377
#include "qapi/error.h"
378
#include "hw/boards.h"
379
-#include "hw/arm/arm.h"
380
+#include "hw/arm/boot.h"
381
#include "sysemu/sysemu.h"
382
#include "exec/address-spaces.h"
383
384
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
385
index XXXXXXX..XXXXXXX 100644
386
--- a/hw/arm/mps2-tz.c
387
+++ b/hw/arm/mps2-tz.c
388
@@ -XXX,XX +XXX,XX @@
389
#include "qemu/osdep.h"
390
#include "qapi/error.h"
391
#include "qemu/error-report.h"
392
-#include "hw/arm/arm.h"
393
+#include "hw/arm/boot.h"
394
#include "hw/arm/armv7m.h"
395
#include "hw/or-irq.h"
396
#include "hw/boards.h"
397
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
398
index XXXXXXX..XXXXXXX 100644
399
--- a/hw/arm/mps2.c
400
+++ b/hw/arm/mps2.c
401
@@ -XXX,XX +XXX,XX @@
402
#include "qemu/osdep.h"
403
#include "qapi/error.h"
404
#include "qemu/error-report.h"
405
-#include "hw/arm/arm.h"
406
+#include "hw/arm/boot.h"
407
#include "hw/arm/armv7m.h"
408
#include "hw/or-irq.h"
409
#include "hw/boards.h"
410
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
411
index XXXXXXX..XXXXXXX 100644
412
--- a/hw/arm/msf2-soc.c
413
+++ b/hw/arm/msf2-soc.c
414
@@ -XXX,XX +XXX,XX @@
415
#include "qemu/units.h"
416
#include "qapi/error.h"
417
#include "qemu-common.h"
418
-#include "hw/arm/arm.h"
419
#include "exec/address-spaces.h"
420
#include "hw/char/serial.h"
421
#include "hw/boards.h"
422
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
423
index XXXXXXX..XXXXXXX 100644
424
--- a/hw/arm/msf2-som.c
425
+++ b/hw/arm/msf2-som.c
426
@@ -XXX,XX +XXX,XX @@
427
#include "qapi/error.h"
428
#include "qemu/error-report.h"
429
#include "hw/boards.h"
430
-#include "hw/arm/arm.h"
431
+#include "hw/arm/boot.h"
432
#include "exec/address-spaces.h"
433
#include "hw/arm/msf2-soc.h"
434
#include "cpu.h"
435
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
436
index XXXXXXX..XXXXXXX 100644
437
--- a/hw/arm/musca.c
438
+++ b/hw/arm/musca.c
439
@@ -XXX,XX +XXX,XX @@
440
#include "qapi/error.h"
441
#include "exec/address-spaces.h"
442
#include "sysemu/sysemu.h"
443
-#include "hw/arm/arm.h"
444
+#include "hw/arm/boot.h"
445
#include "hw/arm/armsse.h"
446
#include "hw/boards.h"
447
#include "hw/char/pl011.h"
448
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
449
index XXXXXXX..XXXXXXX 100644
450
--- a/hw/arm/musicpal.c
451
+++ b/hw/arm/musicpal.c
452
@@ -XXX,XX +XXX,XX @@
453
#include "qemu-common.h"
454
#include "cpu.h"
455
#include "hw/sysbus.h"
456
-#include "hw/arm/arm.h"
457
+#include "hw/arm/boot.h"
458
#include "net/net.h"
459
#include "sysemu/sysemu.h"
460
#include "hw/boards.h"
461
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
462
index XXXXXXX..XXXXXXX 100644
463
--- a/hw/arm/netduino2.c
464
+++ b/hw/arm/netduino2.c
465
@@ -XXX,XX +XXX,XX @@
466
#include "hw/boards.h"
467
#include "qemu/error-report.h"
468
#include "hw/arm/stm32f205_soc.h"
469
-#include "hw/arm/arm.h"
470
+#include "hw/arm/boot.h"
471
472
static void netduino2_init(MachineState *machine)
473
{
474
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
475
index XXXXXXX..XXXXXXX 100644
476
--- a/hw/arm/nrf51_soc.c
477
+++ b/hw/arm/nrf51_soc.c
478
@@ -XXX,XX +XXX,XX @@
479
#include "qemu/osdep.h"
480
#include "qapi/error.h"
481
#include "qemu-common.h"
482
-#include "hw/arm/arm.h"
483
+#include "hw/arm/boot.h"
484
#include "hw/sysbus.h"
485
#include "hw/boards.h"
486
#include "hw/misc/unimp.h"
487
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
488
index XXXXXXX..XXXXXXX 100644
489
--- a/hw/arm/nseries.c
490
+++ b/hw/arm/nseries.c
491
@@ -XXX,XX +XXX,XX @@
492
#include "qemu/bswap.h"
493
#include "sysemu/sysemu.h"
494
#include "hw/arm/omap.h"
495
-#include "hw/arm/arm.h"
496
+#include "hw/arm/boot.h"
497
#include "hw/irq.h"
498
#include "ui/console.h"
499
#include "hw/boards.h"
500
diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
501
index XXXXXXX..XXXXXXX 100644
502
--- a/hw/arm/omap1.c
503
+++ b/hw/arm/omap1.c
504
@@ -XXX,XX +XXX,XX @@
505
#include "cpu.h"
506
#include "hw/boards.h"
507
#include "hw/hw.h"
508
-#include "hw/arm/arm.h"
509
+#include "hw/arm/boot.h"
510
#include "hw/arm/omap.h"
511
#include "sysemu/sysemu.h"
512
#include "hw/arm/soc_dma.h"
513
diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
514
index XXXXXXX..XXXXXXX 100644
515
--- a/hw/arm/omap2.c
516
+++ b/hw/arm/omap2.c
517
@@ -XXX,XX +XXX,XX @@
518
#include "sysemu/qtest.h"
519
#include "hw/boards.h"
520
#include "hw/hw.h"
521
-#include "hw/arm/arm.h"
522
+#include "hw/arm/boot.h"
523
#include "hw/arm/omap.h"
524
#include "sysemu/sysemu.h"
525
#include "qemu/timer.h"
526
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
527
index XXXXXXX..XXXXXXX 100644
528
--- a/hw/arm/omap_sx1.c
529
+++ b/hw/arm/omap_sx1.c
530
@@ -XXX,XX +XXX,XX @@
531
#include "ui/console.h"
532
#include "hw/arm/omap.h"
533
#include "hw/boards.h"
534
-#include "hw/arm/arm.h"
535
+#include "hw/arm/boot.h"
536
#include "hw/block/flash.h"
537
#include "sysemu/qtest.h"
538
#include "exec/address-spaces.h"
539
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
540
index XXXXXXX..XXXXXXX 100644
541
--- a/hw/arm/palm.c
542
+++ b/hw/arm/palm.c
543
@@ -XXX,XX +XXX,XX @@
544
#include "ui/console.h"
545
#include "hw/arm/omap.h"
546
#include "hw/boards.h"
547
-#include "hw/arm/arm.h"
548
+#include "hw/arm/boot.h"
549
#include "hw/input/tsc2xxx.h"
550
#include "hw/loader.h"
551
#include "exec/address-spaces.h"
552
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
553
index XXXXXXX..XXXXXXX 100644
554
--- a/hw/arm/raspi.c
555
+++ b/hw/arm/raspi.c
556
@@ -XXX,XX +XXX,XX @@
557
#include "qemu/error-report.h"
558
#include "hw/boards.h"
559
#include "hw/loader.h"
560
-#include "hw/arm/arm.h"
561
+#include "hw/arm/boot.h"
562
#include "sysemu/sysemu.h"
563
564
#define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS */
565
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
566
index XXXXXXX..XXXXXXX 100644
567
--- a/hw/arm/realview.c
568
+++ b/hw/arm/realview.c
569
@@ -XXX,XX +XXX,XX @@
570
#include "qemu-common.h"
571
#include "cpu.h"
572
#include "hw/sysbus.h"
573
-#include "hw/arm/arm.h"
574
+#include "hw/arm/boot.h"
575
#include "hw/arm/primecell.h"
576
#include "hw/net/lan9118.h"
577
#include "hw/net/smc91c111.h"
578
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
579
index XXXXXXX..XXXXXXX 100644
580
--- a/hw/arm/spitz.c
581
+++ b/hw/arm/spitz.c
582
@@ -XXX,XX +XXX,XX @@
583
#include "qapi/error.h"
584
#include "hw/hw.h"
585
#include "hw/arm/pxa.h"
586
-#include "hw/arm/arm.h"
587
+#include "hw/arm/boot.h"
588
#include "sysemu/sysemu.h"
589
#include "hw/pcmcia.h"
590
#include "hw/i2c/i2c.h"
591
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
592
index XXXXXXX..XXXXXXX 100644
593
--- a/hw/arm/stellaris.c
594
+++ b/hw/arm/stellaris.c
595
@@ -XXX,XX +XXX,XX @@
596
#include "qapi/error.h"
597
#include "hw/sysbus.h"
598
#include "hw/ssi/ssi.h"
599
-#include "hw/arm/arm.h"
600
+#include "hw/arm/boot.h"
601
#include "qemu/timer.h"
602
#include "hw/i2c/i2c.h"
603
#include "net/net.h"
604
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
605
index XXXXXXX..XXXXXXX 100644
606
--- a/hw/arm/stm32f205_soc.c
607
+++ b/hw/arm/stm32f205_soc.c
608
@@ -XXX,XX +XXX,XX @@
609
#include "qemu/osdep.h"
610
#include "qapi/error.h"
611
#include "qemu-common.h"
612
-#include "hw/arm/arm.h"
613
+#include "hw/arm/boot.h"
614
#include "exec/address-spaces.h"
615
#include "hw/arm/stm32f205_soc.h"
616
617
diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
618
index XXXXXXX..XXXXXXX 100644
619
--- a/hw/arm/strongarm.c
620
+++ b/hw/arm/strongarm.c
621
@@ -XXX,XX +XXX,XX @@
622
#include "hw/sysbus.h"
623
#include "strongarm.h"
624
#include "qemu/error-report.h"
625
-#include "hw/arm/arm.h"
626
+#include "hw/arm/boot.h"
627
#include "chardev/char-fe.h"
628
#include "chardev/char-serial.h"
629
#include "sysemu/sysemu.h"
630
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
631
index XXXXXXX..XXXXXXX 100644
632
--- a/hw/arm/tosa.c
633
+++ b/hw/arm/tosa.c
634
@@ -XXX,XX +XXX,XX @@
635
#include "qapi/error.h"
636
#include "hw/hw.h"
637
#include "hw/arm/pxa.h"
638
-#include "hw/arm/arm.h"
639
+#include "hw/arm/boot.h"
640
#include "hw/arm/sharpsl.h"
641
#include "hw/pcmcia.h"
642
#include "hw/boards.h"
643
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
644
index XXXXXXX..XXXXXXX 100644
645
--- a/hw/arm/versatilepb.c
646
+++ b/hw/arm/versatilepb.c
647
@@ -XXX,XX +XXX,XX @@
648
#include "qemu-common.h"
649
#include "cpu.h"
650
#include "hw/sysbus.h"
651
-#include "hw/arm/arm.h"
652
+#include "hw/arm/boot.h"
653
#include "hw/net/smc91c111.h"
654
#include "net/net.h"
655
#include "sysemu/sysemu.h"
656
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
657
index XXXXXXX..XXXXXXX 100644
658
--- a/hw/arm/vexpress.c
659
+++ b/hw/arm/vexpress.c
660
@@ -XXX,XX +XXX,XX @@
661
#include "qemu-common.h"
662
#include "cpu.h"
663
#include "hw/sysbus.h"
664
-#include "hw/arm/arm.h"
665
+#include "hw/arm/boot.h"
666
#include "hw/arm/primecell.h"
667
#include "hw/net/lan9118.h"
668
#include "hw/i2c/i2c.h"
669
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
670
index XXXXXXX..XXXXXXX 100644
671
--- a/hw/arm/virt.c
672
+++ b/hw/arm/virt.c
673
@@ -XXX,XX +XXX,XX @@
674
#include "qemu/option.h"
675
#include "qapi/error.h"
676
#include "hw/sysbus.h"
677
-#include "hw/arm/arm.h"
678
+#include "hw/arm/boot.h"
679
#include "hw/arm/primecell.h"
680
#include "hw/arm/virt.h"
681
#include "hw/block/flash.h"
682
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
683
index XXXXXXX..XXXXXXX 100644
684
--- a/hw/arm/xilinx_zynq.c
685
+++ b/hw/arm/xilinx_zynq.c
686
@@ -XXX,XX +XXX,XX @@
687
#include "qemu-common.h"
688
#include "cpu.h"
689
#include "hw/sysbus.h"
690
-#include "hw/arm/arm.h"
691
+#include "hw/arm/boot.h"
692
#include "net/net.h"
693
#include "exec/address-spaces.h"
694
#include "sysemu/sysemu.h"
695
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
696
index XXXXXXX..XXXXXXX 100644
697
--- a/hw/arm/xlnx-versal.c
698
+++ b/hw/arm/xlnx-versal.c
699
@@ -XXX,XX +XXX,XX @@
700
#include "net/net.h"
701
#include "sysemu/sysemu.h"
702
#include "sysemu/kvm.h"
703
-#include "hw/arm/arm.h"
704
+#include "hw/arm/boot.h"
705
#include "kvm_arm.h"
706
#include "hw/misc/unimp.h"
707
#include "hw/intc/arm_gicv3_common.h"
708
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
709
index XXXXXXX..XXXXXXX 100644
710
--- a/hw/arm/z2.c
711
+++ b/hw/arm/z2.c
712
@@ -XXX,XX +XXX,XX @@
713
#include "qemu/osdep.h"
714
#include "hw/hw.h"
715
#include "hw/arm/pxa.h"
716
-#include "hw/arm/arm.h"
717
+#include "hw/arm/boot.h"
718
#include "hw/i2c/i2c.h"
719
#include "hw/ssi/ssi.h"
720
#include "hw/boards.h"
721
--
32
--
722
2.20.1
33
2.20.1
723
34
724
35
diff view generated by jsdifflib
1
The ICC_CTLR_EL3 register includes some bits which are aliases
1
Add skeletal documentation of the canon-a1100 board.
2
of bits in the ICC_CTLR_EL1(S) and (NS) registers. QEMU chooses
3
to keep those bits in the cs->icc_ctlr_el1[] struct fields.
4
Unfortunately a missing '~' in the code to update the bits
5
in those fields meant that writing to ICC_CTLR_EL3 would corrupt
6
the ICC_CLTR_EL1 register values.
7
2
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20190520162809.2677-5-peter.maydell@linaro.org
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Message-id: 20200713175746.5936-2-peter.maydell@linaro.org
11
---
7
---
12
hw/intc/arm_gicv3_cpuif.c | 4 ++--
8
docs/system/arm/digic.rst | 11 +++++++++++
13
1 file changed, 2 insertions(+), 2 deletions(-)
9
docs/system/target-arm.rst | 1 +
10
MAINTAINERS | 1 +
11
3 files changed, 13 insertions(+)
12
create mode 100644 docs/system/arm/digic.rst
14
13
15
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
14
diff --git a/docs/system/arm/digic.rst b/docs/system/arm/digic.rst
15
new file mode 100644
16
index XXXXXXX..XXXXXXX
17
--- /dev/null
18
+++ b/docs/system/arm/digic.rst
19
@@ -XXX,XX +XXX,XX @@
20
+Canon A1100 (``canon-a1100``)
21
+=============================
22
+
23
+This machine is a model of the Canon PowerShot A1100 camera, which
24
+uses the DIGIC SoC. This model is based on reverse engineering efforts
25
+by the contributors to the `CHDK <http://chdk.wikia.com/>`_ and
26
+`Magic Lantern <http://www.magiclantern.fm/>`_ projects.
27
+
28
+The emulation is incomplete. In particular it can't be used
29
+to run the original camera firmware, but it can successfully run
30
+an experimental version of the `barebox bootloader <http://www.barebox.org/>`_.
31
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
16
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/intc/arm_gicv3_cpuif.c
33
--- a/docs/system/target-arm.rst
18
+++ b/hw/intc/arm_gicv3_cpuif.c
34
+++ b/docs/system/target-arm.rst
19
@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
35
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
20
trace_gicv3_icc_ctlr_el3_write(gicv3_redist_affid(cs), value);
36
arm/versatile
21
37
arm/vexpress
22
/* *_EL1NS and *_EL1S bits are aliases into the ICC_CTLR_EL1 bits. */
38
arm/aspeed
23
- cs->icc_ctlr_el1[GICV3_NS] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
39
+ arm/digic
24
+ cs->icc_ctlr_el1[GICV3_NS] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
40
arm/musicpal
25
if (value & ICC_CTLR_EL3_EOIMODE_EL1NS) {
41
arm/nseries
26
cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE;
42
arm/orangepi
27
}
43
diff --git a/MAINTAINERS b/MAINTAINERS
28
@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
44
index XXXXXXX..XXXXXXX 100644
29
cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_CBPR;
45
--- a/MAINTAINERS
30
}
46
+++ b/MAINTAINERS
31
47
@@ -XXX,XX +XXX,XX @@ F: include/hw/arm/digic.h
32
- cs->icc_ctlr_el1[GICV3_S] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
48
F: hw/*/digic*
33
+ cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
49
F: include/hw/*/digic*
34
if (value & ICC_CTLR_EL3_EOIMODE_EL1S) {
50
F: tests/acceptance/machine_arm_canona1100.py
35
cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_EOIMODE;
51
+F: docs/system/arm/digic.rst
36
}
52
53
Goldfish RTC
54
M: Anup Patel <anup.patel@wdc.com>
37
--
55
--
38
2.20.1
56
2.20.1
39
57
40
58
diff view generated by jsdifflib
1
In ich_vmcr_write() we enforce "writes of BPR fields to less than
1
Add skeletal documentation of the collie board.
2
their minimum sets them to the minimum" by doing a "read vbpr and
3
write it back" operation. A typo here meant that we weren't handling
4
writes to these fields correctly, because we were reading from VBPR0
5
but writing to VBPR1.
6
2
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20190520162809.2677-4-peter.maydell@linaro.org
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Message-id: 20200713175746.5936-3-peter.maydell@linaro.org
10
---
7
---
11
hw/intc/arm_gicv3_cpuif.c | 2 +-
8
docs/system/arm/collie.rst | 16 ++++++++++++++++
12
1 file changed, 1 insertion(+), 1 deletion(-)
9
docs/system/target-arm.rst | 1 +
10
MAINTAINERS | 1 +
11
3 files changed, 18 insertions(+)
12
create mode 100644 docs/system/arm/collie.rst
13
13
14
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
14
diff --git a/docs/system/arm/collie.rst b/docs/system/arm/collie.rst
15
new file mode 100644
16
index XXXXXXX..XXXXXXX
17
--- /dev/null
18
+++ b/docs/system/arm/collie.rst
19
@@ -XXX,XX +XXX,XX @@
20
+Sharp Zaurus SL-5500 (``collie``)
21
+=================================
22
+
23
+This machine is a model of the Sharp Zaurus SL-5500, which was
24
+a 1990s PDA based on the StrongARM SA1110.
25
+
26
+Implemented devices:
27
+
28
+ * NOR flash
29
+ * Interrupt controller
30
+ * Timer
31
+ * RTC
32
+ * GPIO
33
+ * Peripheral Pin Controller (PPC)
34
+ * UARTs
35
+ * Synchronous Serial Ports (SSP)
36
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
15
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/arm_gicv3_cpuif.c
38
--- a/docs/system/target-arm.rst
17
+++ b/hw/intc/arm_gicv3_cpuif.c
39
+++ b/docs/system/target-arm.rst
18
@@ -XXX,XX +XXX,XX @@ static void ich_vmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
40
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
19
/* Enforce "writing BPRs to less than minimum sets them to the minimum"
41
arm/orangepi
20
* by reading and writing back the fields.
42
arm/palm
21
*/
43
arm/xscale
22
- write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G0));
44
+ arm/collie
23
+ write_vbpr(cs, GICV3_G0, read_vbpr(cs, GICV3_G0));
45
arm/sx1
24
write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G1));
46
arm/stellaris
25
47
26
gicv3_cpuif_virt_update(cs);
48
diff --git a/MAINTAINERS b/MAINTAINERS
49
index XXXXXXX..XXXXXXX 100644
50
--- a/MAINTAINERS
51
+++ b/MAINTAINERS
52
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
53
S: Odd Fixes
54
F: hw/arm/collie.c
55
F: hw/arm/strongarm*
56
+F: docs/system/arm/collie.rst
57
58
Stellaris
59
M: Peter Maydell <peter.maydell@linaro.org>
27
--
60
--
28
2.20.1
61
2.20.1
29
62
30
63
diff view generated by jsdifflib
1
The system_clock_scale global is used only by the armv7m systick
1
Add skeletal documentation of the gumstix boards
2
device; move the extern declaration to the armv7m_systick.h header,
2
('connex' and 'verdex').
3
and expand the comment to explain what it is and that it should
4
ideally be replaced with a different approach.
5
3
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
9
Message-id: 20190516163857.6430-2-peter.maydell@linaro.org
7
Message-id: 20200713175746.5936-4-peter.maydell@linaro.org
10
---
8
---
11
include/hw/arm/arm.h | 4 ----
9
docs/system/arm/gumstix.rst | 21 +++++++++++++++++++++
12
include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++++++++
10
docs/system/target-arm.rst | 1 +
13
2 files changed, 22 insertions(+), 4 deletions(-)
11
MAINTAINERS | 1 +
12
3 files changed, 23 insertions(+)
13
create mode 100644 docs/system/arm/gumstix.rst
14
14
15
diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h
15
diff --git a/docs/system/arm/gumstix.rst b/docs/system/arm/gumstix.rst
16
new file mode 100644
17
index XXXXXXX..XXXXXXX
18
--- /dev/null
19
+++ b/docs/system/arm/gumstix.rst
20
@@ -XXX,XX +XXX,XX @@
21
+Gumstix Connex and Verdex (``connex``, ``verdex``)
22
+==================================================
23
+
24
+These machines model the Gumstix Connex and Verdex boards.
25
+The Connex has a PXA255 CPU and the Verdex has a PXA270.
26
+
27
+Implemented devices:
28
+
29
+ * NOR flash
30
+ * SMC91C111 ethernet
31
+ * Interrupt controller
32
+ * DMA
33
+ * Timer
34
+ * GPIO
35
+ * MMC/SD card
36
+ * Fast infra-red communications port (FIR)
37
+ * LCD controller
38
+ * Synchronous serial ports (SPI)
39
+ * PCMCIA interface
40
+ * I2C
41
+ * I2S
42
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
16
index XXXXXXX..XXXXXXX 100644
43
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/arm.h
44
--- a/docs/system/target-arm.rst
18
+++ b/include/hw/arm/arm.h
45
+++ b/docs/system/target-arm.rst
19
@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
46
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
20
const struct arm_boot_info *info,
47
arm/aspeed
21
hwaddr mvbar_addr);
48
arm/digic
22
49
arm/musicpal
23
-/* Multiplication factor to convert from system clock ticks to qemu timer
50
+ arm/gumstix
24
- ticks. */
51
arm/nseries
25
-extern int system_clock_scale;
52
arm/orangepi
26
-
53
arm/palm
27
#endif /* HW_ARM_H */
54
diff --git a/MAINTAINERS b/MAINTAINERS
28
diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
29
index XXXXXXX..XXXXXXX 100644
55
index XXXXXXX..XXXXXXX 100644
30
--- a/include/hw/timer/armv7m_systick.h
56
--- a/MAINTAINERS
31
+++ b/include/hw/timer/armv7m_systick.h
57
+++ b/MAINTAINERS
32
@@ -XXX,XX +XXX,XX @@ typedef struct SysTickState {
58
@@ -XXX,XX +XXX,XX @@ R: Philippe Mathieu-Daudé <f4bug@amsat.org>
33
qemu_irq irq;
59
L: qemu-arm@nongnu.org
34
} SysTickState;
60
S: Odd Fixes
35
61
F: hw/arm/gumstix.c
36
+/*
62
+F: docs/system/arm/gumstix.rst
37
+ * Multiplication factor to convert from system clock ticks to qemu timer
63
38
+ * ticks. This should be set (by board code, usually) to a value
64
i.MX25 PDK
39
+ * equal to NANOSECONDS_PER_SECOND / frq, where frq is the clock frequency
65
M: Peter Maydell <peter.maydell@linaro.org>
40
+ * in Hz of the CPU.
41
+ *
42
+ * This value is used by the systick device when it is running in
43
+ * its "use the CPU clock" mode (ie when SYST_CSR.CLKSOURCE == 1) to
44
+ * set how fast the timer should tick.
45
+ *
46
+ * TODO: we should refactor this so that rather than using a global
47
+ * we use a device property or something similar. This is complicated
48
+ * because (a) the property would need to be plumbed through from the
49
+ * board code down through various layers to the systick device
50
+ * and (b) the property needs to be modifiable after realize, because
51
+ * the stellaris board uses this to implement the behaviour where the
52
+ * guest can reprogram the PLL registers to downclock the CPU, and the
53
+ * systick device needs to react accordingly. Possibly this should
54
+ * be deferred until we have a good API for modelling clock trees.
55
+ */
56
+extern int system_clock_scale;
57
+
58
#endif
59
--
66
--
60
2.20.1
67
2.20.1
61
68
62
69
diff view generated by jsdifflib
1
From: Alistair Francis <alistair.francis@wdc.com>
1
Document the arm 'virt' board, which has been undocumented
2
2
for far too long given that it is the main recommended board
3
Commit 89e68b575 "target/arm: Use vector operations for saturation"
3
type for arm guests.
4
causes this abort() when booting QEMU ARM with a Cortex-A15:
4
5
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
0 0x00007ffff4c2382f in raise () at /usr/lib/libc.so.6
7
1 0x00007ffff4c0e672 in abort () at /usr/lib/libc.so.6
8
2 0x00005555559c1839 in disas_neon_data_insn (insn=<optimized out>, s=<optimized out>) at ./target/arm/translate.c:6673
9
3 0x00005555559c1839 in disas_neon_data_insn (s=<optimized out>, insn=<optimized out>) at ./target/arm/translate.c:6386
10
4 0x00005555559cd8a4 in disas_arm_insn (insn=4081107068, s=0x7fffe59a9510) at ./target/arm/translate.c:9289
11
5 0x00005555559cd8a4 in arm_tr_translate_insn (dcbase=0x7fffe59a9510, cpu=<optimized out>) at ./target/arm/translate.c:13612
12
6 0x00005555558d1d39 in translator_loop (ops=0x5555561cc580 <arm_translator_ops>, db=0x7fffe59a9510, cpu=0x55555686a2f0, tb=<optimized out>, max_insns=<optimized out>) at ./accel/tcg/translator.c:96
13
7 0x00005555559d10d4 in gen_intermediate_code (cpu=cpu@entry=0x55555686a2f0, tb=tb@entry=0x7fffd7840080 <code_gen_buffer+126091347>, max_insns=max_insns@entry=512) at ./target/arm/translate.c:13901
14
8 0x00005555558d06b9 in tb_gen_code (cpu=cpu@entry=0x55555686a2f0, pc=3067096216, cs_base=0, flags=192, cflags=-16252928, cflags@entry=524288) at ./accel/tcg/translate-all.c:1736
15
9 0x00005555558ce467 in tb_find (cf_mask=524288, tb_exit=1, last_tb=0x7fffd783e640 <code_gen_buffer+126084627>, cpu=0x1) at ./accel/tcg/cpu-exec.c:407
16
10 0x00005555558ce467 in cpu_exec (cpu=cpu@entry=0x55555686a2f0) at ./accel/tcg/cpu-exec.c:728
17
11 0x000055555588b0cf in tcg_cpu_exec (cpu=0x55555686a2f0) at ./cpus.c:1431
18
12 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=0x55555686a2f0) at ./cpus.c:1735
19
13 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=arg@entry=0x55555686a2f0) at ./cpus.c:1709
20
14 0x0000555555d2629a in qemu_thread_start (args=<optimized out>) at ./util/qemu-thread-posix.c:502
21
15 0x00007ffff4db8a92 in start_thread () at /usr/lib/libpthread.
22
23
This patch ensures that we don't hit the abort() in the second switch
24
case in disas_neon_data_insn() as we will return from the first case.
25
26
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
27
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
28
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
29
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
30
Tested-by: Alex Bennée <alex.bennee@linaro.org>
7
Message-id: 20200713175746.5936-5-peter.maydell@linaro.org
31
Message-id: ad91b397f360b2fc7f4087e476f7df5b04d42ddb.1558021877.git.alistair.francis@wdc.com
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
---
8
---
34
target/arm/translate.c | 4 ++--
9
docs/system/arm/virt.rst | 161 +++++++++++++++++++++++++++++++++++++
35
1 file changed, 2 insertions(+), 2 deletions(-)
10
docs/system/target-arm.rst | 1 +
36
11
MAINTAINERS | 1 +
37
diff --git a/target/arm/translate.c b/target/arm/translate.c
12
3 files changed, 163 insertions(+)
13
create mode 100644 docs/system/arm/virt.rst
14
15
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
16
new file mode 100644
17
index XXXXXXX..XXXXXXX
18
--- /dev/null
19
+++ b/docs/system/arm/virt.rst
20
@@ -XXX,XX +XXX,XX @@
21
+'virt' generic virtual platform (``virt``)
22
+==========================================
23
+
24
+The `virt` board is a platform which does not correspond to any
25
+real hardware; it is designed for use in virtual machines.
26
+It is the recommended board type if you simply want to run
27
+a guest such as Linux and do not care about reproducing the
28
+idiosyncrasies and limitations of a particular bit of real-world
29
+hardware.
30
+
31
+This is a "versioned" board model, so as well as the ``virt`` machine
32
+type itself (which may have improvements, bugfixes and other minor
33
+changes between QEMU versions) a version is provided that guarantees
34
+to have the same behaviour as that of previous QEMU releases, so
35
+that VM migration will work between QEMU versions. For instance the
36
+``virt-5.0`` machine type will behave like the ``virt`` machine from
37
+the QEMU 5.0 release, and migration should work between ``virt-5.0``
38
+of the 5.0 release and ``virt-5.0`` of the 5.1 release. Migration
39
+is not guaranteed to work between different QEMU releases for
40
+the non-versioned ``virt`` machine type.
41
+
42
+Supported devices
43
+"""""""""""""""""
44
+
45
+The virt board supports:
46
+
47
+- PCI/PCIe devices
48
+- Flash memory
49
+- One PL011 UART
50
+- An RTC
51
+- The fw_cfg device that allows a guest to obtain data from QEMU
52
+- A PL061 GPIO controller
53
+- An optional SMMUv3 IOMMU
54
+- hotpluggable DIMMs
55
+- hotpluggable NVDIMMs
56
+- An MSI controller (GICv2M or ITS). GICv2M is selected by default along
57
+ with GICv2. ITS is selected by default with GICv3 (>= virt-2.7). Note
58
+ that ITS is not modeled in TCG mode.
59
+- 32 virtio-mmio transport devices
60
+- running guests using the KVM accelerator on aarch64 hardware
61
+- large amounts of RAM (at least 255GB, and more if using highmem)
62
+- many CPUs (up to 512 if using a GICv3 and highmem)
63
+- Secure-World-only devices if the CPU has TrustZone:
64
+
65
+ - A second PL011 UART
66
+ - A secure flash memory
67
+ - 16MB of secure RAM
68
+
69
+Supported guest CPU types:
70
+
71
+- ``cortex-a7`` (32-bit)
72
+- ``cortex-a15`` (32-bit; the default)
73
+- ``cortex-a53`` (64-bit)
74
+- ``cortex-a57`` (64-bit)
75
+- ``cortex-a72`` (64-bit)
76
+- ``host`` (with KVM only)
77
+- ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
78
+
79
+Note that the default is ``cortex-a15``, so for an AArch64 guest you must
80
+specify a CPU type.
81
+
82
+Graphics output is available, but unlike the x86 PC machine types
83
+there is no default display device enabled: you should select one from
84
+the Display devices section of "-device help". The recommended option
85
+is ``virtio-gpu-pci``; this is the only one which will work correctly
86
+with KVM. You may also need to ensure your guest kernel is configured
87
+with support for this; see below.
88
+
89
+Machine-specific options
90
+""""""""""""""""""""""""
91
+
92
+The following machine-specific options are supported:
93
+
94
+secure
95
+ Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the
96
+ Arm Security Extensions (TrustZone). The default is ``off``.
97
+
98
+virtualization
99
+ Set ``on``/``off`` to enable/disable emulating a guest CPU which implements the
100
+ Arm Virtualization Extensions. The default is ``off``.
101
+
102
+highmem
103
+ Set ``on``/``off`` to enable/disable placing devices and RAM in physical
104
+ address space above 32 bits. The default is ``on`` for machine types
105
+ later than ``virt-2.12``.
106
+
107
+gic-version
108
+ Specify the version of the Generic Interrupt Controller (GIC) to provide.
109
+ Valid values are:
110
+
111
+ ``2``
112
+ GICv2
113
+ ``3``
114
+ GICv3
115
+ ``host``
116
+ Use the same GIC version the host provides, when using KVM
117
+ ``max``
118
+ Use the best GIC version possible (same as host when using KVM;
119
+ currently same as ``3``` for TCG, but this may change in future)
120
+
121
+its
122
+ Set ``on``/``off`` to enable/disable ITS instantiation. The default is ``on``
123
+ for machine types later than ``virt-2.7``.
124
+
125
+iommu
126
+ Set the IOMMU type to create for the guest. Valid values are:
127
+
128
+ ``none``
129
+ Don't create an IOMMU (the default)
130
+ ``smmuv3``
131
+ Create an SMMUv3
132
+
133
+ras
134
+ Set ``on``/``off`` to enable/disable reporting host memory errors to a guest
135
+ using ACPI and guest external abort exceptions. The default is off.
136
+
137
+Linux guest kernel configuration
138
+""""""""""""""""""""""""""""""""
139
+
140
+The 'defconfig' for Linux arm and arm64 kernels should include the
141
+right device drivers for virtio and the PCI controller; however some older
142
+kernel versions, especially for 32-bit Arm, did not have everything
143
+enabled by default. If you're not seeing PCI devices that you expect,
144
+then check that your guest config has::
145
+
146
+ CONFIG_PCI=y
147
+ CONFIG_VIRTIO_PCI=y
148
+ CONFIG_PCI_HOST_GENERIC=y
149
+
150
+If you want to use the ``virtio-gpu-pci`` graphics device you will also
151
+need::
152
+
153
+ CONFIG_DRM=y
154
+ CONFIG_DRM_VIRTIO_GPU=y
155
+
156
+Hardware configuration information for bare-metal programming
157
+"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""
158
+
159
+The ``virt`` board automatically generates a device tree blob ("dtb")
160
+which it passes to the guest. This provides information about the
161
+addresses, interrupt lines and other configuration of the various devices
162
+in the system. Guest code can rely on and hard-code the following
163
+addresses:
164
+
165
+- Flash memory starts at address 0x0000_0000
166
+
167
+- RAM starts at 0x4000_0000
168
+
169
+All other information about device locations may change between
170
+QEMU versions, so guest code must look in the DTB.
171
+
172
+QEMU supports two types of guest image boot for ``virt``, and
173
+the way for the guest code to locate the dtb binary differs:
174
+
175
+- For guests using the Linux kernel boot protocol (this means any
176
+ non-ELF file passed to the QEMU ``-kernel`` option) the address
177
+ of the DTB is passed in a register (``r2`` for 32-bit guests,
178
+ or ``x0`` for 64-bit guests)
179
+
180
+- For guests booting as "bare-metal" (any other kind of boot),
181
+ the DTB is at the start of RAM (0x4000_0000)
182
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
38
index XXXXXXX..XXXXXXX 100644
183
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/translate.c
184
--- a/docs/system/target-arm.rst
40
+++ b/target/arm/translate.c
185
+++ b/docs/system/target-arm.rst
41
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
186
@@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running
42
tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
187
arm/collie
43
rn_ofs, rm_ofs, vec_size, vec_size,
188
arm/sx1
44
(u ? uqadd_op : sqadd_op) + size);
189
arm/stellaris
45
- break;
190
+ arm/virt
46
+ return 0;
191
47
192
Arm CPU features
48
case NEON_3R_VQSUB:
193
================
49
tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
194
diff --git a/MAINTAINERS b/MAINTAINERS
50
rn_ofs, rm_ofs, vec_size, vec_size,
195
index XXXXXXX..XXXXXXX 100644
51
(u ? uqsub_op : sqsub_op) + size);
196
--- a/MAINTAINERS
52
- break;
197
+++ b/MAINTAINERS
53
+ return 0;
198
@@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org
54
199
S: Maintained
55
case NEON_3R_VMUL: /* VMUL */
200
F: hw/arm/virt*
56
if (u) {
201
F: include/hw/arm/virt.h
202
+F: docs/system/arm/virt.rst
203
204
Xilinx Zynq
205
M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
57
--
206
--
58
2.20.1
207
2.20.1
59
208
60
209
diff view generated by jsdifflib