1
Not very much here, but several people have fallen over
1
I might squeeze in another pullreq before softfreeze, but the
2
the vector operation segfault bug, so let's get the fix
2
queue was already big enough that I wanted to send this lot out now.
3
into master.
4
3
5
thanks
6
-- PMM
4
-- PMM
7
5
8
The following changes since commit d418238dca7b4e0b124135827ead3076233052b1:
6
The following changes since commit 4abf70a661a5df3886ac9d7c19c3617fa92b922a:
9
7
10
Merge remote-tracking branch 'remotes/rth/tags/pull-rng-20190522' into staging (2019-05-23 12:57:17 +0100)
8
Merge remote-tracking branch 'remotes/maxreitz/tags/pull-block-2020-06-24' into staging (2020-07-03 15:34:45 +0100)
11
9
12
are available in the Git repository at:
10
are available in the Git repository at:
13
11
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190523
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200703
15
13
16
for you to fetch changes up to 98e4f4fdb8ea05d840f51f47125924c2bb9df2df:
14
for you to fetch changes up to 0f10bf84a9d489259a5b11c6aa1b05c1175b76ea:
17
15
18
hw/arm/exynos4210: QOM'ify the Exynos4210 SoC (2019-05-23 14:47:44 +0100)
16
Deprecate TileGX port (2020-07-03 16:59:46 +0100)
19
17
20
----------------------------------------------------------------
18
----------------------------------------------------------------
21
target-arm queue:
19
target-arm queue:
22
* exynos4210: QOM'ify the Exynos4210 SoC
20
* i.MX6UL EVK board: put PHYs in the correct places
23
* exynos4210: Add DMA support for the Exynos4210
21
* hw/arm/virt: Let the virtio-iommu bypass MSIs
24
* arm_gicv3: Fix writes to ICC_CTLR_EL3
22
* target/arm: kvm: Handle DABT with no valid ISS
25
* arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
23
* hw/arm/virt-acpi-build: Only expose flash on older machine types
26
* target/arm: Fix vector operation segfault
24
* target/arm: Fix temp double-free in sve ldr/str
27
* target/arm: Minor improvements to BFXIL, EXTR
25
* hw/display/bcm2835_fb.c: Initialize all fields of struct
26
* hw/arm/spitz: Code cleanup to fix Coverity-detected memory leak
27
* Deprecate TileGX port
28
28
29
----------------------------------------------------------------
29
----------------------------------------------------------------
30
Alistair Francis (1):
30
Andrew Jones (4):
31
target/arm: Fix vector operation segfault
31
tests/acpi: remove stale allowed tables
32
tests/acpi: virt: allow DSDT acpi table changes
33
hw/arm/virt-acpi-build: Only expose flash on older machine types
34
tests/acpi: virt: update golden masters for DSDT
32
35
33
Guenter Roeck (1):
36
Beata Michalska (2):
34
hw/arm/exynos4210: Add DMA support for the Exynos4210
37
target/arm: kvm: Handle DABT with no valid ISS
38
target/arm: kvm: Handle misconfigured dabt injection
35
39
36
Peter Maydell (5):
40
Eric Auger (5):
37
arm: Move system_clock_scale to armv7m_systick.h
41
qdev: Introduce DEFINE_PROP_RESERVED_REGION
38
arm: Remove unnecessary includes of hw/arm/arm.h
42
virtio-iommu: Implement RESV_MEM probe request
39
arm: Rename hw/arm/arm.h to hw/arm/boot.h
43
virtio-iommu: Handle reserved regions in the translation process
40
hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
44
virtio-iommu-pci: Add array of Interval properties
41
hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3
45
hw/arm/virt: Let the virtio-iommu bypass MSIs
42
46
43
Philippe Mathieu-Daudé (3):
47
Jean-Christophe Dubois (3):
44
hw/arm/exynos4: Remove unuseful debug code
48
Add a phy-num property to the i.MX FEC emulator
45
hw/arm/exynos4: Use the IEC binary prefix definitions
49
Add the ability to select a different PHY for each i.MX6UL FEC interface
46
hw/arm/exynos4210: QOM'ify the Exynos4210 SoC
50
Select MDIO device 2 and 1 as PHY devices for i.MX6UL EVK board.
47
51
48
Richard Henderson (2):
52
Peter Maydell (19):
49
target/arm: Use extract2 for EXTR
53
hw/display/bcm2835_fb.c: Initialize all fields of struct
50
target/arm: Simplify BFXIL expansion
54
hw/arm/spitz: Detabify
55
hw/arm/spitz: Create SpitzMachineClass abstract base class
56
hw/arm/spitz: Keep pointers to MPU and SSI devices in SpitzMachineState
57
hw/arm/spitz: Keep pointers to scp0, scp1 in SpitzMachineState
58
hw/arm/spitz: Implement inbound GPIO lines for bit5 and power signals
59
hw/misc/max111x: provide QOM properties for setting initial values
60
hw/misc/max111x: Don't use vmstate_register()
61
ssi: Add ssi_realize_and_unref()
62
hw/arm/spitz: Use max111x properties to set initial values
63
hw/misc/max111x: Use GPIO lines rather than max111x_set_input()
64
hw/misc/max111x: Create header file for documentation, TYPE_ macros
65
hw/arm/spitz: Encapsulate misc GPIO handling in a device
66
hw/gpio/zaurus.c: Use LOG_GUEST_ERROR for bad guest register accesses
67
hw/arm/spitz: Use LOG_GUEST_ERROR for bad guest register accesses
68
hw/arm/pxa2xx_pic: Use LOG_GUEST_ERROR for bad guest register accesses
69
hw/arm/spitz: Provide usual QOM macros for corgi-ssp and spitz-lcdtg
70
Replace uses of FROM_SSI_SLAVE() macro with QOM casts
71
Deprecate TileGX port
51
72
52
include/hw/arm/allwinner-a10.h | 2 +-
73
Richard Henderson (1):
53
include/hw/arm/aspeed_soc.h | 1 -
74
target/arm: Fix temp double-free in sve ldr/str
54
include/hw/arm/bcm2836.h | 1 -
55
include/hw/arm/{arm.h => boot.h} | 12 +++------
56
include/hw/arm/exynos4210.h | 9 +++++--
57
include/hw/arm/fsl-imx25.h | 2 +-
58
include/hw/arm/fsl-imx31.h | 2 +-
59
include/hw/arm/fsl-imx6.h | 2 +-
60
include/hw/arm/fsl-imx6ul.h | 2 +-
61
include/hw/arm/fsl-imx7.h | 2 +-
62
include/hw/arm/virt.h | 2 +-
63
include/hw/arm/xlnx-versal.h | 2 +-
64
include/hw/arm/xlnx-zynqmp.h | 2 +-
65
include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++
66
hw/arm/armsse.c | 2 +-
67
hw/arm/armv7m.c | 2 +-
68
hw/arm/aspeed.c | 2 +-
69
hw/arm/boot.c | 2 +-
70
hw/arm/collie.c | 2 +-
71
hw/arm/exynos4210.c | 54 ++++++++++++++++++++++++++++++++++++---
72
hw/arm/exynos4_boards.c | 40 ++++++++---------------------
73
hw/arm/highbank.c | 2 +-
74
hw/arm/integratorcp.c | 2 +-
75
hw/arm/mainstone.c | 2 +-
76
hw/arm/microbit.c | 2 +-
77
hw/arm/mps2-tz.c | 2 +-
78
hw/arm/mps2.c | 2 +-
79
hw/arm/msf2-soc.c | 1 -
80
hw/arm/msf2-som.c | 2 +-
81
hw/arm/musca.c | 2 +-
82
hw/arm/musicpal.c | 2 +-
83
hw/arm/netduino2.c | 2 +-
84
hw/arm/nrf51_soc.c | 2 +-
85
hw/arm/nseries.c | 2 +-
86
hw/arm/omap1.c | 2 +-
87
hw/arm/omap2.c | 2 +-
88
hw/arm/omap_sx1.c | 2 +-
89
hw/arm/palm.c | 2 +-
90
hw/arm/raspi.c | 2 +-
91
hw/arm/realview.c | 2 +-
92
hw/arm/spitz.c | 2 +-
93
hw/arm/stellaris.c | 2 +-
94
hw/arm/stm32f205_soc.c | 2 +-
95
hw/arm/strongarm.c | 2 +-
96
hw/arm/tosa.c | 2 +-
97
hw/arm/versatilepb.c | 2 +-
98
hw/arm/vexpress.c | 2 +-
99
hw/arm/virt.c | 2 +-
100
hw/arm/xilinx_zynq.c | 2 +-
101
hw/arm/xlnx-versal.c | 2 +-
102
hw/arm/z2.c | 2 +-
103
hw/intc/arm_gicv3_cpuif.c | 6 ++---
104
hw/intc/armv7m_nvic.c | 1 -
105
target/arm/arm-semi.c | 1 -
106
target/arm/cpu.c | 1 -
107
target/arm/cpu64.c | 1 -
108
target/arm/kvm.c | 1 -
109
target/arm/kvm32.c | 1 -
110
target/arm/kvm64.c | 1 -
111
target/arm/translate-a64.c | 44 ++++++++++++++++---------------
112
target/arm/translate.c | 4 +--
113
61 files changed, 164 insertions(+), 123 deletions(-)
114
rename include/hw/arm/{arm.h => boot.h} (96%)
115
75
76
docs/system/deprecated.rst | 11 +
77
include/exec/memory.h | 6 +
78
include/hw/arm/fsl-imx6ul.h | 2 +
79
include/hw/arm/pxa.h | 1 -
80
include/hw/arm/sharpsl.h | 3 -
81
include/hw/arm/virt.h | 8 +
82
include/hw/misc/max111x.h | 56 +++
83
include/hw/net/imx_fec.h | 1 +
84
include/hw/qdev-properties.h | 3 +
85
include/hw/ssi/ssi.h | 31 +-
86
include/hw/virtio/virtio-iommu.h | 2 +
87
include/qemu/typedefs.h | 1 +
88
target/arm/cpu.h | 2 +
89
target/arm/kvm_arm.h | 10 +
90
target/arm/translate-a64.h | 1 +
91
tests/qtest/bios-tables-test-allowed-diff.h | 18 -
92
hw/arm/fsl-imx6ul.c | 10 +
93
hw/arm/mcimx6ul-evk.c | 2 +
94
hw/arm/pxa2xx_pic.c | 9 +-
95
hw/arm/spitz.c | 507 ++++++++++++++++------------
96
hw/arm/virt-acpi-build.c | 5 +-
97
hw/arm/virt.c | 33 ++
98
hw/arm/z2.c | 11 +-
99
hw/core/qdev-properties.c | 89 +++++
100
hw/display/ads7846.c | 9 +-
101
hw/display/bcm2835_fb.c | 4 +
102
hw/display/ssd0323.c | 10 +-
103
hw/gpio/zaurus.c | 12 +-
104
hw/misc/max111x.c | 86 +++--
105
hw/net/imx_fec.c | 24 +-
106
hw/sd/ssi-sd.c | 4 +-
107
hw/ssi/ssi.c | 7 +-
108
hw/virtio/virtio-iommu-pci.c | 11 +
109
hw/virtio/virtio-iommu.c | 114 ++++++-
110
target/arm/kvm.c | 80 +++++
111
target/arm/kvm32.c | 34 ++
112
target/arm/kvm64.c | 49 +++
113
target/arm/translate-a64.c | 6 +
114
target/arm/translate-sve.c | 8 +-
115
MAINTAINERS | 1 +
116
hw/net/trace-events | 4 +-
117
hw/virtio/trace-events | 1 +
118
tests/data/acpi/virt/DSDT | Bin 5307 -> 5205 bytes
119
tests/data/acpi/virt/DSDT.memhp | Bin 6668 -> 6566 bytes
120
tests/data/acpi/virt/DSDT.numamem | Bin 5307 -> 5205 bytes
121
45 files changed, 974 insertions(+), 312 deletions(-)
122
create mode 100644 include/hw/misc/max111x.h
123
diff view generated by jsdifflib
New patch
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
1
2
3
We need a solution to use an Ethernet PHY that is not the first device
4
on the MDIO bus (device 0 on MDIO bus).
5
6
As an example with the i.MX6UL the NXP SOC has 2 Ethernet devices but
7
only one MDIO bus on which the 2 related PHY are connected but at unique
8
addresses.
9
10
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
11
Message-id: a1a5c0e139d1c763194b8020573dcb6025daeefa.1593296112.git.jcd@tribudubois.net
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
include/hw/net/imx_fec.h | 1 +
16
hw/net/imx_fec.c | 24 +++++++++++++++++-------
17
hw/net/trace-events | 4 ++--
18
3 files changed, 20 insertions(+), 9 deletions(-)
19
20
diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/net/imx_fec.h
23
+++ b/include/hw/net/imx_fec.h
24
@@ -XXX,XX +XXX,XX @@ typedef struct IMXFECState {
25
uint32_t phy_advertise;
26
uint32_t phy_int;
27
uint32_t phy_int_mask;
28
+ uint32_t phy_num;
29
30
bool is_fec;
31
32
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/net/imx_fec.c
35
+++ b/hw/net/imx_fec.c
36
@@ -XXX,XX +XXX,XX @@ static void imx_phy_reset(IMXFECState *s)
37
static uint32_t imx_phy_read(IMXFECState *s, int reg)
38
{
39
uint32_t val;
40
+ uint32_t phy = reg / 32;
41
42
- if (reg > 31) {
43
- /* we only advertise one phy */
44
+ if (phy != s->phy_num) {
45
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad phy num %u\n",
46
+ TYPE_IMX_FEC, __func__, phy);
47
return 0;
48
}
49
50
+ reg %= 32;
51
+
52
switch (reg) {
53
case 0: /* Basic Control */
54
val = s->phy_control;
55
@@ -XXX,XX +XXX,XX @@ static uint32_t imx_phy_read(IMXFECState *s, int reg)
56
break;
57
}
58
59
- trace_imx_phy_read(val, reg);
60
+ trace_imx_phy_read(val, phy, reg);
61
62
return val;
63
}
64
65
static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
66
{
67
- trace_imx_phy_write(val, reg);
68
+ uint32_t phy = reg / 32;
69
70
- if (reg > 31) {
71
- /* we only advertise one phy */
72
+ if (phy != s->phy_num) {
73
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad phy num %u\n",
74
+ TYPE_IMX_FEC, __func__, phy);
75
return;
76
}
77
78
+ reg %= 32;
79
+
80
+ trace_imx_phy_write(val, phy, reg);
81
+
82
switch (reg) {
83
case 0: /* Basic Control */
84
if (val & 0x8000) {
85
@@ -XXX,XX +XXX,XX @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value,
86
extract32(value,
87
18, 10)));
88
} else {
89
- /* This a write operation */
90
+ /* This is a write operation */
91
imx_phy_write(s, extract32(value, 18, 10), extract32(value, 0, 16));
92
}
93
/* raise the interrupt as the PHY operation is done */
94
@@ -XXX,XX +XXX,XX @@ static void imx_eth_realize(DeviceState *dev, Error **errp)
95
static Property imx_eth_properties[] = {
96
DEFINE_NIC_PROPERTIES(IMXFECState, conf),
97
DEFINE_PROP_UINT32("tx-ring-num", IMXFECState, tx_ring_num, 1),
98
+ DEFINE_PROP_UINT32("phy-num", IMXFECState, phy_num, 0),
99
DEFINE_PROP_END_OF_LIST(),
100
};
101
102
diff --git a/hw/net/trace-events b/hw/net/trace-events
103
index XXXXXXX..XXXXXXX 100644
104
--- a/hw/net/trace-events
105
+++ b/hw/net/trace-events
106
@@ -XXX,XX +XXX,XX @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries"
107
i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION"
108
109
# imx_fec.c
110
-imx_phy_read(uint32_t val, int reg) "0x%04"PRIx32" <= reg[%d]"
111
-imx_phy_write(uint32_t val, int reg) "0x%04"PRIx32" => reg[%d]"
112
+imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]"
113
+imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]"
114
imx_phy_update_link(const char *s) "%s"
115
imx_phy_reset(void) ""
116
imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x"
117
--
118
2.20.1
119
120
diff view generated by jsdifflib
New patch
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
1
2
3
Add properties to the i.MX6UL processor to be able to select a
4
particular PHY on the MDIO bus for each FEC device.
5
6
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
7
Message-id: ea1d604198b6b73ea6521676e45bacfc597aba53.1593296112.git.jcd@tribudubois.net
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/fsl-imx6ul.h | 2 ++
12
hw/arm/fsl-imx6ul.c | 10 ++++++++++
13
2 files changed, 12 insertions(+)
14
15
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/fsl-imx6ul.h
18
+++ b/include/hw/arm/fsl-imx6ul.h
19
@@ -XXX,XX +XXX,XX @@ typedef struct FslIMX6ULState {
20
MemoryRegion caam;
21
MemoryRegion ocram;
22
MemoryRegion ocram_alias;
23
+
24
+ uint32_t phy_num[FSL_IMX6UL_NUM_ETHS];
25
} FslIMX6ULState;
26
27
enum FslIMX6ULMemoryMap {
28
diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/arm/fsl-imx6ul.c
31
+++ b/hw/arm/fsl-imx6ul.c
32
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
33
FSL_IMX6UL_ENET2_TIMER_IRQ,
34
};
35
36
+ object_property_set_uint(OBJECT(&s->eth[i]),
37
+ s->phy_num[i],
38
+ "phy-num", &error_abort);
39
object_property_set_uint(OBJECT(&s->eth[i]),
40
FSL_IMX6UL_ETH_NUM_TX_RINGS,
41
"tx-ring-num", &error_abort);
42
@@ -XXX,XX +XXX,XX @@ static void fsl_imx6ul_realize(DeviceState *dev, Error **errp)
43
FSL_IMX6UL_OCRAM_ALIAS_ADDR, &s->ocram_alias);
44
}
45
46
+static Property fsl_imx6ul_properties[] = {
47
+ DEFINE_PROP_UINT32("fec1-phy-num", FslIMX6ULState, phy_num[0], 0),
48
+ DEFINE_PROP_UINT32("fec2-phy-num", FslIMX6ULState, phy_num[1], 1),
49
+ DEFINE_PROP_END_OF_LIST(),
50
+};
51
+
52
static void fsl_imx6ul_class_init(ObjectClass *oc, void *data)
53
{
54
DeviceClass *dc = DEVICE_CLASS(oc);
55
56
+ device_class_set_props(dc, fsl_imx6ul_properties);
57
dc->realize = fsl_imx6ul_realize;
58
dc->desc = "i.MX6UL SOC";
59
/* Reason: Uses serial_hds and nd_table in realize() directly */
60
--
61
2.20.1
62
63
diff view generated by jsdifflib
New patch
1
From: Jean-Christophe Dubois <jcd@tribudubois.net>
1
2
3
The i.MX6UL EVK 14x14 board uses:
4
- PHY 2 for FEC 1
5
- PHY 1 for FEC 2
6
7
Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
8
Message-id: fb41992126c091a71d76ab3d1898959091f60583.1593296112.git.jcd@tribudubois.net
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/mcimx6ul-evk.c | 2 ++
13
1 file changed, 2 insertions(+)
14
15
diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/mcimx6ul-evk.c
18
+++ b/hw/arm/mcimx6ul-evk.c
19
@@ -XXX,XX +XXX,XX @@ static void mcimx6ul_evk_init(MachineState *machine)
20
21
s = FSL_IMX6UL(object_new(TYPE_FSL_IMX6UL));
22
object_property_add_child(OBJECT(machine), "soc", OBJECT(s));
23
+ object_property_set_uint(OBJECT(s), 2, "fec1-phy-num", &error_fatal);
24
+ object_property_set_uint(OBJECT(s), 1, "fec2-phy-num", &error_fatal);
25
qdev_realize(DEVICE(s), NULL, &error_fatal);
26
27
memory_region_add_subregion(get_system_memory(), FSL_IMX6UL_MMDC_ADDR,
28
--
29
2.20.1
30
31
diff view generated by jsdifflib
New patch
1
From: Eric Auger <eric.auger@redhat.com>
1
2
3
Introduce a new property defining a reserved region:
4
<low address>:<high address>:<type>.
5
6
This will be used to encode reserved IOVA regions.
7
8
For instance, in virtio-iommu use case, reserved IOVA regions
9
will be passed by the machine code to the virtio-iommu-pci
10
device (an array of those). The type of the reserved region
11
will match the virtio_iommu_probe_resv_mem subtype value:
12
- VIRTIO_IOMMU_RESV_MEM_T_RESERVED (0)
13
- VIRTIO_IOMMU_RESV_MEM_T_MSI (1)
14
15
on PC/Q35 machine, this will be used to inform the
16
virtio-iommu-pci device it should bypass the MSI region.
17
The reserved region will be: 0xfee00000:0xfeefffff:1.
18
19
On ARM, we can declare the ITS MSI doorbell as an MSI
20
region to prevent MSIs from being mapped on guest side.
21
22
Signed-off-by: Eric Auger <eric.auger@redhat.com>
23
Reviewed-by: Markus Armbruster <armbru@redhat.com>
24
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
25
Message-id: 20200629070404.10969-2-eric.auger@redhat.com
26
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
27
---
28
include/exec/memory.h | 6 +++
29
include/hw/qdev-properties.h | 3 ++
30
include/qemu/typedefs.h | 1 +
31
hw/core/qdev-properties.c | 89 ++++++++++++++++++++++++++++++++++++
32
4 files changed, 99 insertions(+)
33
34
diff --git a/include/exec/memory.h b/include/exec/memory.h
35
index XXXXXXX..XXXXXXX 100644
36
--- a/include/exec/memory.h
37
+++ b/include/exec/memory.h
38
@@ -XXX,XX +XXX,XX @@ extern bool global_dirty_log;
39
40
typedef struct MemoryRegionOps MemoryRegionOps;
41
42
+struct ReservedRegion {
43
+ hwaddr low;
44
+ hwaddr high;
45
+ unsigned type;
46
+};
47
+
48
typedef struct IOMMUTLBEntry IOMMUTLBEntry;
49
50
/* See address_space_translate: bit 0 is read, bit 1 is write. */
51
diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h
52
index XXXXXXX..XXXXXXX 100644
53
--- a/include/hw/qdev-properties.h
54
+++ b/include/hw/qdev-properties.h
55
@@ -XXX,XX +XXX,XX @@ extern const PropertyInfo qdev_prop_string;
56
extern const PropertyInfo qdev_prop_chr;
57
extern const PropertyInfo qdev_prop_tpm;
58
extern const PropertyInfo qdev_prop_macaddr;
59
+extern const PropertyInfo qdev_prop_reserved_region;
60
extern const PropertyInfo qdev_prop_on_off_auto;
61
extern const PropertyInfo qdev_prop_multifd_compression;
62
extern const PropertyInfo qdev_prop_losttickpolicy;
63
@@ -XXX,XX +XXX,XX @@ extern const PropertyInfo qdev_prop_pcie_link_width;
64
DEFINE_PROP(_n, _s, _f, qdev_prop_drive_iothread, BlockBackend *)
65
#define DEFINE_PROP_MACADDR(_n, _s, _f) \
66
DEFINE_PROP(_n, _s, _f, qdev_prop_macaddr, MACAddr)
67
+#define DEFINE_PROP_RESERVED_REGION(_n, _s, _f) \
68
+ DEFINE_PROP(_n, _s, _f, qdev_prop_reserved_region, ReservedRegion)
69
#define DEFINE_PROP_ON_OFF_AUTO(_n, _s, _f, _d) \
70
DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_on_off_auto, OnOffAuto)
71
#define DEFINE_PROP_MULTIFD_COMPRESSION(_n, _s, _f, _d) \
72
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
73
index XXXXXXX..XXXXXXX 100644
74
--- a/include/qemu/typedefs.h
75
+++ b/include/qemu/typedefs.h
76
@@ -XXX,XX +XXX,XX @@ typedef struct ISABus ISABus;
77
typedef struct ISADevice ISADevice;
78
typedef struct IsaDma IsaDma;
79
typedef struct MACAddr MACAddr;
80
+typedef struct ReservedRegion ReservedRegion;
81
typedef struct MachineClass MachineClass;
82
typedef struct MachineState MachineState;
83
typedef struct MemoryListener MemoryListener;
84
diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c
85
index XXXXXXX..XXXXXXX 100644
86
--- a/hw/core/qdev-properties.c
87
+++ b/hw/core/qdev-properties.c
88
@@ -XXX,XX +XXX,XX @@
89
#include "chardev/char.h"
90
#include "qemu/uuid.h"
91
#include "qemu/units.h"
92
+#include "qemu/cutils.h"
93
94
void qdev_prop_set_after_realize(DeviceState *dev, const char *name,
95
Error **errp)
96
@@ -XXX,XX +XXX,XX @@ const PropertyInfo qdev_prop_macaddr = {
97
.set = set_mac,
98
};
99
100
+/* --- Reserved Region --- */
101
+
102
+/*
103
+ * Accepted syntax:
104
+ * <low address>:<high address>:<type>
105
+ * where low/high addresses are uint64_t in hexadecimal
106
+ * and type is a non-negative decimal integer
107
+ */
108
+static void get_reserved_region(Object *obj, Visitor *v, const char *name,
109
+ void *opaque, Error **errp)
110
+{
111
+ DeviceState *dev = DEVICE(obj);
112
+ Property *prop = opaque;
113
+ ReservedRegion *rr = qdev_get_prop_ptr(dev, prop);
114
+ char buffer[64];
115
+ char *p = buffer;
116
+ int rc;
117
+
118
+ rc = snprintf(buffer, sizeof(buffer), "0x%"PRIx64":0x%"PRIx64":%u",
119
+ rr->low, rr->high, rr->type);
120
+ assert(rc < sizeof(buffer));
121
+
122
+ visit_type_str(v, name, &p, errp);
123
+}
124
+
125
+static void set_reserved_region(Object *obj, Visitor *v, const char *name,
126
+ void *opaque, Error **errp)
127
+{
128
+ DeviceState *dev = DEVICE(obj);
129
+ Property *prop = opaque;
130
+ ReservedRegion *rr = qdev_get_prop_ptr(dev, prop);
131
+ Error *local_err = NULL;
132
+ const char *endptr;
133
+ char *str;
134
+ int ret;
135
+
136
+ if (dev->realized) {
137
+ qdev_prop_set_after_realize(dev, name, errp);
138
+ return;
139
+ }
140
+
141
+ visit_type_str(v, name, &str, &local_err);
142
+ if (local_err) {
143
+ error_propagate(errp, local_err);
144
+ return;
145
+ }
146
+
147
+ ret = qemu_strtou64(str, &endptr, 16, &rr->low);
148
+ if (ret) {
149
+ error_setg(errp, "start address of '%s'"
150
+ " must be a hexadecimal integer", name);
151
+ goto out;
152
+ }
153
+ if (*endptr != ':') {
154
+ goto separator_error;
155
+ }
156
+
157
+ ret = qemu_strtou64(endptr + 1, &endptr, 16, &rr->high);
158
+ if (ret) {
159
+ error_setg(errp, "end address of '%s'"
160
+ " must be a hexadecimal integer", name);
161
+ goto out;
162
+ }
163
+ if (*endptr != ':') {
164
+ goto separator_error;
165
+ }
166
+
167
+ ret = qemu_strtoui(endptr + 1, &endptr, 10, &rr->type);
168
+ if (ret) {
169
+ error_setg(errp, "type of '%s'"
170
+ " must be a non-negative decimal integer", name);
171
+ }
172
+ goto out;
173
+
174
+separator_error:
175
+ error_setg(errp, "reserved region fields must be separated with ':'");
176
+out:
177
+ g_free(str);
178
+ return;
179
+}
180
+
181
+const PropertyInfo qdev_prop_reserved_region = {
182
+ .name = "reserved_region",
183
+ .description = "Reserved Region, example: 0xFEE00000:0xFEEFFFFF:0",
184
+ .get = get_reserved_region,
185
+ .set = set_reserved_region,
186
+};
187
+
188
/* --- on/off/auto --- */
189
190
const PropertyInfo qdev_prop_on_off_auto = {
191
--
192
2.20.1
193
194
diff view generated by jsdifflib
New patch
1
1
From: Eric Auger <eric.auger@redhat.com>
2
3
This patch implements the PROBE request. At the moment,
4
only THE RESV_MEM property is handled. The first goal is
5
to report iommu wide reserved regions such as the MSI regions
6
set by the machine code. On x86 this will be the IOAPIC MSI
7
region, [0xFEE00000 - 0xFEEFFFFF], on ARM this may be the ITS
8
doorbell.
9
10
In the future we may introduce per device reserved regions.
11
This will be useful when protecting host assigned devices
12
which may expose their own reserved regions
13
14
Signed-off-by: Eric Auger <eric.auger@redhat.com>
15
Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
16
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
17
Message-id: 20200629070404.10969-3-eric.auger@redhat.com
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
20
include/hw/virtio/virtio-iommu.h | 2 +
21
hw/virtio/virtio-iommu.c | 94 ++++++++++++++++++++++++++++++--
22
hw/virtio/trace-events | 1 +
23
3 files changed, 93 insertions(+), 4 deletions(-)
24
25
diff --git a/include/hw/virtio/virtio-iommu.h b/include/hw/virtio/virtio-iommu.h
26
index XXXXXXX..XXXXXXX 100644
27
--- a/include/hw/virtio/virtio-iommu.h
28
+++ b/include/hw/virtio/virtio-iommu.h
29
@@ -XXX,XX +XXX,XX @@ typedef struct VirtIOIOMMU {
30
GHashTable *as_by_busptr;
31
IOMMUPciBus *iommu_pcibus_by_bus_num[PCI_BUS_MAX];
32
PCIBus *primary_bus;
33
+ ReservedRegion *reserved_regions;
34
+ uint32_t nb_reserved_regions;
35
GTree *domains;
36
QemuMutex mutex;
37
GTree *endpoints;
38
diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/virtio/virtio-iommu.c
41
+++ b/hw/virtio/virtio-iommu.c
42
@@ -XXX,XX +XXX,XX @@
43
44
/* Max size */
45
#define VIOMMU_DEFAULT_QUEUE_SIZE 256
46
+#define VIOMMU_PROBE_SIZE 512
47
48
typedef struct VirtIOIOMMUDomain {
49
uint32_t id;
50
@@ -XXX,XX +XXX,XX @@ static int virtio_iommu_unmap(VirtIOIOMMU *s,
51
return ret;
52
}
53
54
+static ssize_t virtio_iommu_fill_resv_mem_prop(VirtIOIOMMU *s, uint32_t ep,
55
+ uint8_t *buf, size_t free)
56
+{
57
+ struct virtio_iommu_probe_resv_mem prop = {};
58
+ size_t size = sizeof(prop), length = size - sizeof(prop.head), total;
59
+ int i;
60
+
61
+ total = size * s->nb_reserved_regions;
62
+
63
+ if (total > free) {
64
+ return -ENOSPC;
65
+ }
66
+
67
+ for (i = 0; i < s->nb_reserved_regions; i++) {
68
+ unsigned subtype = s->reserved_regions[i].type;
69
+
70
+ assert(subtype == VIRTIO_IOMMU_RESV_MEM_T_RESERVED ||
71
+ subtype == VIRTIO_IOMMU_RESV_MEM_T_MSI);
72
+ prop.head.type = cpu_to_le16(VIRTIO_IOMMU_PROBE_T_RESV_MEM);
73
+ prop.head.length = cpu_to_le16(length);
74
+ prop.subtype = subtype;
75
+ prop.start = cpu_to_le64(s->reserved_regions[i].low);
76
+ prop.end = cpu_to_le64(s->reserved_regions[i].high);
77
+
78
+ memcpy(buf, &prop, size);
79
+
80
+ trace_virtio_iommu_fill_resv_property(ep, prop.subtype,
81
+ prop.start, prop.end);
82
+ buf += size;
83
+ }
84
+ return total;
85
+}
86
+
87
+/**
88
+ * virtio_iommu_probe - Fill the probe request buffer with
89
+ * the properties the device is able to return
90
+ */
91
+static int virtio_iommu_probe(VirtIOIOMMU *s,
92
+ struct virtio_iommu_req_probe *req,
93
+ uint8_t *buf)
94
+{
95
+ uint32_t ep_id = le32_to_cpu(req->endpoint);
96
+ size_t free = VIOMMU_PROBE_SIZE;
97
+ ssize_t count;
98
+
99
+ if (!virtio_iommu_mr(s, ep_id)) {
100
+ return VIRTIO_IOMMU_S_NOENT;
101
+ }
102
+
103
+ count = virtio_iommu_fill_resv_mem_prop(s, ep_id, buf, free);
104
+ if (count < 0) {
105
+ return VIRTIO_IOMMU_S_INVAL;
106
+ }
107
+ buf += count;
108
+ free -= count;
109
+
110
+ return VIRTIO_IOMMU_S_OK;
111
+}
112
+
113
static int virtio_iommu_iov_to_req(struct iovec *iov,
114
unsigned int iov_cnt,
115
void *req, size_t req_sz)
116
@@ -XXX,XX +XXX,XX @@ virtio_iommu_handle_req(detach)
117
virtio_iommu_handle_req(map)
118
virtio_iommu_handle_req(unmap)
119
120
+static int virtio_iommu_handle_probe(VirtIOIOMMU *s,
121
+ struct iovec *iov,
122
+ unsigned int iov_cnt,
123
+ uint8_t *buf)
124
+{
125
+ struct virtio_iommu_req_probe req;
126
+ int ret = virtio_iommu_iov_to_req(iov, iov_cnt, &req, sizeof(req));
127
+
128
+ return ret ? ret : virtio_iommu_probe(s, &req, buf);
129
+}
130
+
131
static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq)
132
{
133
VirtIOIOMMU *s = VIRTIO_IOMMU(vdev);
134
struct virtio_iommu_req_head head;
135
struct virtio_iommu_req_tail tail = {};
136
+ size_t output_size = sizeof(tail), sz;
137
VirtQueueElement *elem;
138
unsigned int iov_cnt;
139
struct iovec *iov;
140
- size_t sz;
141
+ void *buf = NULL;
142
143
for (;;) {
144
elem = virtqueue_pop(vq, sizeof(VirtQueueElement));
145
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq)
146
case VIRTIO_IOMMU_T_UNMAP:
147
tail.status = virtio_iommu_handle_unmap(s, iov, iov_cnt);
148
break;
149
+ case VIRTIO_IOMMU_T_PROBE:
150
+ {
151
+ struct virtio_iommu_req_tail *ptail;
152
+
153
+ output_size = s->config.probe_size + sizeof(tail);
154
+ buf = g_malloc0(output_size);
155
+
156
+ ptail = (struct virtio_iommu_req_tail *)
157
+ (buf + s->config.probe_size);
158
+ ptail->status = virtio_iommu_handle_probe(s, iov, iov_cnt, buf);
159
+ }
160
default:
161
tail.status = VIRTIO_IOMMU_S_UNSUPP;
162
}
163
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_handle_command(VirtIODevice *vdev, VirtQueue *vq)
164
165
out:
166
sz = iov_from_buf(elem->in_sg, elem->in_num, 0,
167
- &tail, sizeof(tail));
168
- assert(sz == sizeof(tail));
169
+ buf ? buf : &tail, output_size);
170
+ assert(sz == output_size);
171
172
- virtqueue_push(vq, elem, sizeof(tail));
173
+ virtqueue_push(vq, elem, sz);
174
virtio_notify(vdev, vq);
175
g_free(elem);
176
+ g_free(buf);
177
}
178
}
179
180
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_device_realize(DeviceState *dev, Error **errp)
181
s->config.page_size_mask = TARGET_PAGE_MASK;
182
s->config.input_range.end = -1UL;
183
s->config.domain_range.end = 32;
184
+ s->config.probe_size = VIOMMU_PROBE_SIZE;
185
186
virtio_add_feature(&s->features, VIRTIO_RING_F_EVENT_IDX);
187
virtio_add_feature(&s->features, VIRTIO_RING_F_INDIRECT_DESC);
188
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_device_realize(DeviceState *dev, Error **errp)
189
virtio_add_feature(&s->features, VIRTIO_IOMMU_F_MAP_UNMAP);
190
virtio_add_feature(&s->features, VIRTIO_IOMMU_F_BYPASS);
191
virtio_add_feature(&s->features, VIRTIO_IOMMU_F_MMIO);
192
+ virtio_add_feature(&s->features, VIRTIO_IOMMU_F_PROBE);
193
194
qemu_mutex_init(&s->mutex);
195
196
diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events
197
index XXXXXXX..XXXXXXX 100644
198
--- a/hw/virtio/trace-events
199
+++ b/hw/virtio/trace-events
200
@@ -XXX,XX +XXX,XX @@ virtio_iommu_get_domain(uint32_t domain_id) "Alloc domain=%d"
201
virtio_iommu_put_domain(uint32_t domain_id) "Free domain=%d"
202
virtio_iommu_translate_out(uint64_t virt_addr, uint64_t phys_addr, uint32_t sid) "0x%"PRIx64" -> 0x%"PRIx64 " for sid=%d"
203
virtio_iommu_report_fault(uint8_t reason, uint32_t flags, uint32_t endpoint, uint64_t addr) "FAULT reason=%d flags=%d endpoint=%d address =0x%"PRIx64
204
+virtio_iommu_fill_resv_property(uint32_t devid, uint8_t subtype, uint64_t start, uint64_t end) "dev= %d, type=%d start=0x%"PRIx64" end=0x%"PRIx64
205
--
206
2.20.1
207
208
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Eric Auger <eric.auger@redhat.com>
2
2
3
The mask implied by the extract is redundant with the one
3
When translating an address we need to check if it belongs to
4
implied by the deposit. Also, fix spelling of BFXIL.
4
a reserved virtual address range. If it does, there are 2 cases:
5
5
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
- it belongs to a RESERVED region: the guest should neither use
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
this address in a MAP not instruct the end-point to DMA on
8
Message-id: 20190514011129.11330-3-richard.henderson@linaro.org
8
them. We report an error
9
10
- It belongs to an MSI region: we bypass the translation.
11
12
Signed-off-by: Eric Auger <eric.auger@redhat.com>
13
Reviewed-by: Peter Xu <peterx@redhat.com>
14
Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
15
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
16
Message-id: 20200629070404.10969-4-eric.auger@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
18
---
11
target/arm/translate-a64.c | 6 +++---
19
hw/virtio/virtio-iommu.c | 20 ++++++++++++++++++++
12
1 file changed, 3 insertions(+), 3 deletions(-)
20
1 file changed, 20 insertions(+)
13
21
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
22
diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c
15
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
24
--- a/hw/virtio/virtio-iommu.c
17
+++ b/target/arm/translate-a64.c
25
+++ b/hw/virtio/virtio-iommu.c
18
@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
26
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr,
19
tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len);
27
uint32_t sid, flags;
20
return;
28
bool bypass_allowed;
21
}
29
bool found;
22
- /* opc == 1, BXFIL fall through to deposit */
30
+ int i;
23
- tcg_gen_extract_i64(tcg_tmp, tcg_tmp, ri, len);
31
24
+ /* opc == 1, BFXIL fall through to deposit */
32
interval.low = addr;
25
+ tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri);
33
interval.high = addr + 1;
26
pos = 0;
34
@@ -XXX,XX +XXX,XX @@ static IOMMUTLBEntry virtio_iommu_translate(IOMMUMemoryRegion *mr, hwaddr addr,
27
} else {
35
goto unlock;
28
/* Handle the ri > si case with a deposit
29
@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
30
len = ri;
31
}
36
}
32
37
33
- if (opc == 1) { /* BFM, BXFIL */
38
+ for (i = 0; i < s->nb_reserved_regions; i++) {
34
+ if (opc == 1) { /* BFM, BFXIL */
39
+ ReservedRegion *reg = &s->reserved_regions[i];
35
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len);
40
+
36
} else {
41
+ if (addr >= reg->low && addr <= reg->high) {
37
/* SBFM or UBFM: We start with zero, and we haven't modified
42
+ switch (reg->type) {
43
+ case VIRTIO_IOMMU_RESV_MEM_T_MSI:
44
+ entry.perm = flag;
45
+ break;
46
+ case VIRTIO_IOMMU_RESV_MEM_T_RESERVED:
47
+ default:
48
+ virtio_iommu_report_fault(s, VIRTIO_IOMMU_FAULT_R_MAPPING,
49
+ VIRTIO_IOMMU_FAULT_F_ADDRESS,
50
+ sid, addr);
51
+ break;
52
+ }
53
+ goto unlock;
54
+ }
55
+ }
56
+
57
if (!ep->domain) {
58
if (!bypass_allowed) {
59
error_report_once("%s %02x:%02x.%01x not attached to any domain",
38
--
60
--
39
2.20.1
61
2.20.1
40
62
41
63
diff view generated by jsdifflib
New patch
1
From: Eric Auger <eric.auger@redhat.com>
1
2
3
The machine may need to pass reserved regions to the
4
virtio-iommu-pci device (such as the MSI window on x86
5
or the MSI doorbells on ARM).
6
7
So let's add an array of Interval properties.
8
9
Note: if some reserved regions are already set by the
10
machine code - which should be the case in general -,
11
the length of the property array is already set and
12
prevents the end-user from modifying them. For example,
13
attempting to use:
14
15
-device virtio-iommu-pci,\
16
len-reserved-regions=1,reserved-regions[0]=0xfee00000:0xfeefffff:1
17
18
would result in the following error message:
19
20
qemu-system-aarch64: -device virtio-iommu-pci,addr=0xa,
21
len-reserved-regions=1,reserved-regions[0]=0xfee00000:0xfeefffff:1:
22
array size property len-reserved-regions may not be set more than once
23
24
Otherwise, for example, adding two reserved regions is achieved
25
using the following options:
26
27
-device virtio-iommu-pci,addr=0xa,len-reserved-regions=2,\
28
reserved-regions[0]=0xfee00000:0xfeefffff:1,\
29
reserved-regions[1]=0x1000000:100ffff:1
30
31
Signed-off-by: Eric Auger <eric.auger@redhat.com>
32
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
33
Reviewed-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
34
Reviewed-by: Peter Xu <peterx@redhat.com>
35
Message-id: 20200629070404.10969-5-eric.auger@redhat.com
36
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
37
---
38
hw/virtio/virtio-iommu-pci.c | 11 +++++++++++
39
1 file changed, 11 insertions(+)
40
41
diff --git a/hw/virtio/virtio-iommu-pci.c b/hw/virtio/virtio-iommu-pci.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/hw/virtio/virtio-iommu-pci.c
44
+++ b/hw/virtio/virtio-iommu-pci.c
45
@@ -XXX,XX +XXX,XX @@ struct VirtIOIOMMUPCI {
46
47
static Property virtio_iommu_pci_properties[] = {
48
DEFINE_PROP_UINT32("class", VirtIOPCIProxy, class_code, 0),
49
+ DEFINE_PROP_ARRAY("reserved-regions", VirtIOIOMMUPCI,
50
+ vdev.nb_reserved_regions, vdev.reserved_regions,
51
+ qdev_prop_reserved_region, ReservedRegion),
52
DEFINE_PROP_END_OF_LIST(),
53
};
54
55
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
56
{
57
VirtIOIOMMUPCI *dev = VIRTIO_IOMMU_PCI(vpci_dev);
58
DeviceState *vdev = DEVICE(&dev->vdev);
59
+ VirtIOIOMMU *s = VIRTIO_IOMMU(vdev);
60
61
if (!qdev_get_machine_hotplug_handler(DEVICE(vpci_dev))) {
62
MachineClass *mc = MACHINE_GET_CLASS(qdev_get_machine());
63
@@ -XXX,XX +XXX,XX @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp)
64
"-no-acpi\n");
65
return;
66
}
67
+ for (int i = 0; i < s->nb_reserved_regions; i++) {
68
+ if (s->reserved_regions[i].type != VIRTIO_IOMMU_RESV_MEM_T_RESERVED &&
69
+ s->reserved_regions[i].type != VIRTIO_IOMMU_RESV_MEM_T_MSI) {
70
+ error_setg(errp, "reserved region %d has an invalid type", i);
71
+ error_append_hint(errp, "Valid values are 0 and 1\n");
72
+ }
73
+ }
74
object_property_set_link(OBJECT(dev),
75
OBJECT(pci_get_bus(&vpci_dev->pci_dev)),
76
"primary-bus", &error_abort);
77
--
78
2.20.1
79
80
diff view generated by jsdifflib
1
The header file hw/arm/arm.h now includes only declarations
1
From: Eric Auger <eric.auger@redhat.com>
2
relating to hw/arm/boot.c functionality. Rename it accordingly,
3
and adjust its header comment.
4
2
5
The bulk of this commit was created via
3
At the moment the virtio-iommu translates MSI transactions.
6
perl -pi -e 's|hw/arm/arm.h|hw/arm/boot.h|' hw/arm/*.c include/hw/arm/*.h
4
This behavior is inherited from ARM SMMU. The virt machine
5
code knows where the guest MSI doorbells are so we can easily
6
declare those regions as VIRTIO_IOMMU_RESV_MEM_T_MSI. With that
7
setting the guest will not map MSIs through the IOMMU and those
8
transactions will be simply bypassed.
7
9
8
In a few cases we can just delete the #include:
10
Depending on which MSI controller is in use (ITS or GICV2M),
9
hw/arm/msf2-soc.c, include/hw/arm/aspeed_soc.h and
11
we declare either:
10
include/hw/arm/bcm2836.h did not require it.
12
- the ITS interrupt translation space (ITS_base + 0x10000),
13
containing the GITS_TRANSLATOR or
14
- The GICV2M single frame, containing the MSI_SETSP_NS register.
11
15
16
Signed-off-by: Eric Auger <eric.auger@redhat.com>
17
Message-id: 20200629070404.10969-6-eric.auger@redhat.com
18
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Message-id: 20190516163857.6430-4-peter.maydell@linaro.org
16
---
20
---
17
include/hw/arm/allwinner-a10.h | 2 +-
21
include/hw/arm/virt.h | 7 +++++++
18
include/hw/arm/aspeed_soc.h | 1 -
22
hw/arm/virt.c | 30 ++++++++++++++++++++++++++++++
19
include/hw/arm/bcm2836.h | 1 -
23
2 files changed, 37 insertions(+)
20
include/hw/arm/{arm.h => boot.h} | 8 ++++----
21
include/hw/arm/fsl-imx25.h | 2 +-
22
include/hw/arm/fsl-imx31.h | 2 +-
23
include/hw/arm/fsl-imx6.h | 2 +-
24
include/hw/arm/fsl-imx6ul.h | 2 +-
25
include/hw/arm/fsl-imx7.h | 2 +-
26
include/hw/arm/virt.h | 2 +-
27
include/hw/arm/xlnx-versal.h | 2 +-
28
include/hw/arm/xlnx-zynqmp.h | 2 +-
29
hw/arm/armsse.c | 2 +-
30
hw/arm/armv7m.c | 2 +-
31
hw/arm/aspeed.c | 2 +-
32
hw/arm/boot.c | 2 +-
33
hw/arm/collie.c | 2 +-
34
hw/arm/exynos4210.c | 2 +-
35
hw/arm/exynos4_boards.c | 2 +-
36
hw/arm/highbank.c | 2 +-
37
hw/arm/integratorcp.c | 2 +-
38
hw/arm/mainstone.c | 2 +-
39
hw/arm/microbit.c | 2 +-
40
hw/arm/mps2-tz.c | 2 +-
41
hw/arm/mps2.c | 2 +-
42
hw/arm/msf2-soc.c | 1 -
43
hw/arm/msf2-som.c | 2 +-
44
hw/arm/musca.c | 2 +-
45
hw/arm/musicpal.c | 2 +-
46
hw/arm/netduino2.c | 2 +-
47
hw/arm/nrf51_soc.c | 2 +-
48
hw/arm/nseries.c | 2 +-
49
hw/arm/omap1.c | 2 +-
50
hw/arm/omap2.c | 2 +-
51
hw/arm/omap_sx1.c | 2 +-
52
hw/arm/palm.c | 2 +-
53
hw/arm/raspi.c | 2 +-
54
hw/arm/realview.c | 2 +-
55
hw/arm/spitz.c | 2 +-
56
hw/arm/stellaris.c | 2 +-
57
hw/arm/stm32f205_soc.c | 2 +-
58
hw/arm/strongarm.c | 2 +-
59
hw/arm/tosa.c | 2 +-
60
hw/arm/versatilepb.c | 2 +-
61
hw/arm/vexpress.c | 2 +-
62
hw/arm/virt.c | 2 +-
63
hw/arm/xilinx_zynq.c | 2 +-
64
hw/arm/xlnx-versal.c | 2 +-
65
hw/arm/z2.c | 2 +-
66
49 files changed, 49 insertions(+), 52 deletions(-)
67
rename include/hw/arm/{arm.h => boot.h} (98%)
68
24
69
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
70
index XXXXXXX..XXXXXXX 100644
71
--- a/include/hw/arm/allwinner-a10.h
72
+++ b/include/hw/arm/allwinner-a10.h
73
@@ -XXX,XX +XXX,XX @@
74
#include "qemu-common.h"
75
#include "qemu/error-report.h"
76
#include "hw/char/serial.h"
77
-#include "hw/arm/arm.h"
78
+#include "hw/arm/boot.h"
79
#include "hw/timer/allwinner-a10-pit.h"
80
#include "hw/intc/allwinner-a10-pic.h"
81
#include "hw/net/allwinner_emac.h"
82
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
83
index XXXXXXX..XXXXXXX 100644
84
--- a/include/hw/arm/aspeed_soc.h
85
+++ b/include/hw/arm/aspeed_soc.h
86
@@ -XXX,XX +XXX,XX @@
87
#ifndef ASPEED_SOC_H
88
#define ASPEED_SOC_H
89
90
-#include "hw/arm/arm.h"
91
#include "hw/intc/aspeed_vic.h"
92
#include "hw/misc/aspeed_scu.h"
93
#include "hw/misc/aspeed_sdmc.h"
94
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
95
index XXXXXXX..XXXXXXX 100644
96
--- a/include/hw/arm/bcm2836.h
97
+++ b/include/hw/arm/bcm2836.h
98
@@ -XXX,XX +XXX,XX @@
99
#ifndef BCM2836_H
100
#define BCM2836_H
101
102
-#include "hw/arm/arm.h"
103
#include "hw/arm/bcm2835_peripherals.h"
104
#include "hw/intc/bcm2836_control.h"
105
106
diff --git a/include/hw/arm/arm.h b/include/hw/arm/boot.h
107
similarity index 98%
108
rename from include/hw/arm/arm.h
109
rename to include/hw/arm/boot.h
110
index XXXXXXX..XXXXXXX 100644
111
--- a/include/hw/arm/arm.h
112
+++ b/include/hw/arm/boot.h
113
@@ -XXX,XX +XXX,XX @@
114
/*
115
- * Misc ARM declarations
116
+ * ARM kernel loader.
117
*
118
* Copyright (c) 2006 CodeSourcery.
119
* Written by Paul Brook
120
@@ -XXX,XX +XXX,XX @@
121
*
122
*/
123
124
-#ifndef HW_ARM_H
125
-#define HW_ARM_H
126
+#ifndef HW_ARM_BOOT_H
127
+#define HW_ARM_BOOT_H
128
129
#include "exec/memory.h"
130
#include "target/arm/cpu-qom.h"
131
@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
132
const struct arm_boot_info *info,
133
hwaddr mvbar_addr);
134
135
-#endif /* HW_ARM_H */
136
+#endif /* HW_ARM_BOOT_H */
137
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
138
index XXXXXXX..XXXXXXX 100644
139
--- a/include/hw/arm/fsl-imx25.h
140
+++ b/include/hw/arm/fsl-imx25.h
141
@@ -XXX,XX +XXX,XX @@
142
#ifndef FSL_IMX25_H
143
#define FSL_IMX25_H
144
145
-#include "hw/arm/arm.h"
146
+#include "hw/arm/boot.h"
147
#include "hw/intc/imx_avic.h"
148
#include "hw/misc/imx25_ccm.h"
149
#include "hw/char/imx_serial.h"
150
diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h
151
index XXXXXXX..XXXXXXX 100644
152
--- a/include/hw/arm/fsl-imx31.h
153
+++ b/include/hw/arm/fsl-imx31.h
154
@@ -XXX,XX +XXX,XX @@
155
#ifndef FSL_IMX31_H
156
#define FSL_IMX31_H
157
158
-#include "hw/arm/arm.h"
159
+#include "hw/arm/boot.h"
160
#include "hw/intc/imx_avic.h"
161
#include "hw/misc/imx31_ccm.h"
162
#include "hw/char/imx_serial.h"
163
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
164
index XXXXXXX..XXXXXXX 100644
165
--- a/include/hw/arm/fsl-imx6.h
166
+++ b/include/hw/arm/fsl-imx6.h
167
@@ -XXX,XX +XXX,XX @@
168
#ifndef FSL_IMX6_H
169
#define FSL_IMX6_H
170
171
-#include "hw/arm/arm.h"
172
+#include "hw/arm/boot.h"
173
#include "hw/cpu/a9mpcore.h"
174
#include "hw/misc/imx6_ccm.h"
175
#include "hw/misc/imx6_src.h"
176
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
177
index XXXXXXX..XXXXXXX 100644
178
--- a/include/hw/arm/fsl-imx6ul.h
179
+++ b/include/hw/arm/fsl-imx6ul.h
180
@@ -XXX,XX +XXX,XX @@
181
#ifndef FSL_IMX6UL_H
182
#define FSL_IMX6UL_H
183
184
-#include "hw/arm/arm.h"
185
+#include "hw/arm/boot.h"
186
#include "hw/cpu/a15mpcore.h"
187
#include "hw/misc/imx6ul_ccm.h"
188
#include "hw/misc/imx6_src.h"
189
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
190
index XXXXXXX..XXXXXXX 100644
191
--- a/include/hw/arm/fsl-imx7.h
192
+++ b/include/hw/arm/fsl-imx7.h
193
@@ -XXX,XX +XXX,XX @@
194
#ifndef FSL_IMX7_H
195
#define FSL_IMX7_H
196
197
-#include "hw/arm/arm.h"
198
+#include "hw/arm/boot.h"
199
#include "hw/cpu/a15mpcore.h"
200
#include "hw/intc/imx_gpcv2.h"
201
#include "hw/misc/imx7_ccm.h"
202
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
25
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
203
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
204
--- a/include/hw/arm/virt.h
27
--- a/include/hw/arm/virt.h
205
+++ b/include/hw/arm/virt.h
28
+++ b/include/hw/arm/virt.h
206
@@ -XXX,XX +XXX,XX @@
29
@@ -XXX,XX +XXX,XX @@ typedef enum VirtIOMMUType {
207
#include "exec/hwaddr.h"
30
VIRT_IOMMU_VIRTIO,
208
#include "qemu/notify.h"
31
} VirtIOMMUType;
209
#include "hw/boards.h"
32
210
-#include "hw/arm/arm.h"
33
+typedef enum VirtMSIControllerType {
211
+#include "hw/arm/boot.h"
34
+ VIRT_MSI_CTRL_NONE,
212
#include "hw/block/flash.h"
35
+ VIRT_MSI_CTRL_GICV2M,
213
#include "sysemu/kvm.h"
36
+ VIRT_MSI_CTRL_ITS,
214
#include "hw/intc/arm_gicv3_common.h"
37
+} VirtMSIControllerType;
215
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
38
+
216
index XXXXXXX..XXXXXXX 100644
39
typedef enum VirtGICType {
217
--- a/include/hw/arm/xlnx-versal.h
40
VIRT_GIC_VERSION_MAX,
218
+++ b/include/hw/arm/xlnx-versal.h
41
VIRT_GIC_VERSION_HOST,
219
@@ -XXX,XX +XXX,XX @@
42
@@ -XXX,XX +XXX,XX @@ typedef struct {
220
#define XLNX_VERSAL_H
43
OnOffAuto acpi;
221
44
VirtGICType gic_version;
222
#include "hw/sysbus.h"
45
VirtIOMMUType iommu;
223
-#include "hw/arm/arm.h"
46
+ VirtMSIControllerType msi_controller;
224
+#include "hw/arm/boot.h"
47
uint16_t virtio_iommu_bdf;
225
#include "hw/intc/arm_gicv3.h"
48
struct arm_boot_info bootinfo;
226
49
MemMapEntry *memmap;
227
#define TYPE_XLNX_VERSAL "xlnx-versal"
228
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
229
index XXXXXXX..XXXXXXX 100644
230
--- a/include/hw/arm/xlnx-zynqmp.h
231
+++ b/include/hw/arm/xlnx-zynqmp.h
232
@@ -XXX,XX +XXX,XX @@
233
#ifndef XLNX_ZYNQMP_H
234
235
#include "qemu-common.h"
236
-#include "hw/arm/arm.h"
237
+#include "hw/arm/boot.h"
238
#include "hw/intc/arm_gic.h"
239
#include "hw/net/cadence_gem.h"
240
#include "hw/char/cadence_uart.h"
241
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
242
index XXXXXXX..XXXXXXX 100644
243
--- a/hw/arm/armsse.c
244
+++ b/hw/arm/armsse.c
245
@@ -XXX,XX +XXX,XX @@
246
#include "hw/sysbus.h"
247
#include "hw/registerfields.h"
248
#include "hw/arm/armsse.h"
249
-#include "hw/arm/arm.h"
250
+#include "hw/arm/boot.h"
251
252
/* Format of the System Information block SYS_CONFIG register */
253
typedef enum SysConfigFormat {
254
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
255
index XXXXXXX..XXXXXXX 100644
256
--- a/hw/arm/armv7m.c
257
+++ b/hw/arm/armv7m.c
258
@@ -XXX,XX +XXX,XX @@
259
#include "qemu-common.h"
260
#include "cpu.h"
261
#include "hw/sysbus.h"
262
-#include "hw/arm/arm.h"
263
+#include "hw/arm/boot.h"
264
#include "hw/loader.h"
265
#include "elf.h"
266
#include "sysemu/qtest.h"
267
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
268
index XXXXXXX..XXXXXXX 100644
269
--- a/hw/arm/aspeed.c
270
+++ b/hw/arm/aspeed.c
271
@@ -XXX,XX +XXX,XX @@
272
#include "qemu-common.h"
273
#include "cpu.h"
274
#include "exec/address-spaces.h"
275
-#include "hw/arm/arm.h"
276
+#include "hw/arm/boot.h"
277
#include "hw/arm/aspeed.h"
278
#include "hw/arm/aspeed_soc.h"
279
#include "hw/boards.h"
280
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
281
index XXXXXXX..XXXXXXX 100644
282
--- a/hw/arm/boot.c
283
+++ b/hw/arm/boot.c
284
@@ -XXX,XX +XXX,XX @@
285
#include "qapi/error.h"
286
#include <libfdt.h>
287
#include "hw/hw.h"
288
-#include "hw/arm/arm.h"
289
+#include "hw/arm/boot.h"
290
#include "hw/arm/linux-boot-if.h"
291
#include "sysemu/kvm.h"
292
#include "sysemu/sysemu.h"
293
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
294
index XXXXXXX..XXXXXXX 100644
295
--- a/hw/arm/collie.c
296
+++ b/hw/arm/collie.c
297
@@ -XXX,XX +XXX,XX @@
298
#include "hw/sysbus.h"
299
#include "hw/boards.h"
300
#include "strongarm.h"
301
-#include "hw/arm/arm.h"
302
+#include "hw/arm/boot.h"
303
#include "hw/block/flash.h"
304
#include "exec/address-spaces.h"
305
#include "cpu.h"
306
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
307
index XXXXXXX..XXXXXXX 100644
308
--- a/hw/arm/exynos4210.c
309
+++ b/hw/arm/exynos4210.c
310
@@ -XXX,XX +XXX,XX @@
311
#include "hw/boards.h"
312
#include "sysemu/sysemu.h"
313
#include "hw/sysbus.h"
314
-#include "hw/arm/arm.h"
315
+#include "hw/arm/boot.h"
316
#include "hw/loader.h"
317
#include "hw/arm/exynos4210.h"
318
#include "hw/sd/sdhci.h"
319
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
320
index XXXXXXX..XXXXXXX 100644
321
--- a/hw/arm/exynos4_boards.c
322
+++ b/hw/arm/exynos4_boards.c
323
@@ -XXX,XX +XXX,XX @@
324
#include "sysemu/sysemu.h"
325
#include "hw/sysbus.h"
326
#include "net/net.h"
327
-#include "hw/arm/arm.h"
328
+#include "hw/arm/boot.h"
329
#include "exec/address-spaces.h"
330
#include "hw/arm/exynos4210.h"
331
#include "hw/net/lan9118.h"
332
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
333
index XXXXXXX..XXXXXXX 100644
334
--- a/hw/arm/highbank.c
335
+++ b/hw/arm/highbank.c
336
@@ -XXX,XX +XXX,XX @@
337
#include "qemu/osdep.h"
338
#include "qapi/error.h"
339
#include "hw/sysbus.h"
340
-#include "hw/arm/arm.h"
341
+#include "hw/arm/boot.h"
342
#include "hw/loader.h"
343
#include "net/net.h"
344
#include "sysemu/kvm.h"
345
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
346
index XXXXXXX..XXXXXXX 100644
347
--- a/hw/arm/integratorcp.c
348
+++ b/hw/arm/integratorcp.c
349
@@ -XXX,XX +XXX,XX @@
350
#include "cpu.h"
351
#include "hw/sysbus.h"
352
#include "hw/boards.h"
353
-#include "hw/arm/arm.h"
354
+#include "hw/arm/boot.h"
355
#include "hw/misc/arm_integrator_debug.h"
356
#include "hw/net/smc91c111.h"
357
#include "net/net.h"
358
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
359
index XXXXXXX..XXXXXXX 100644
360
--- a/hw/arm/mainstone.c
361
+++ b/hw/arm/mainstone.c
362
@@ -XXX,XX +XXX,XX @@
363
#include "qapi/error.h"
364
#include "hw/hw.h"
365
#include "hw/arm/pxa.h"
366
-#include "hw/arm/arm.h"
367
+#include "hw/arm/boot.h"
368
#include "net/net.h"
369
#include "hw/net/smc91c111.h"
370
#include "hw/boards.h"
371
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
372
index XXXXXXX..XXXXXXX 100644
373
--- a/hw/arm/microbit.c
374
+++ b/hw/arm/microbit.c
375
@@ -XXX,XX +XXX,XX @@
376
#include "qemu/osdep.h"
377
#include "qapi/error.h"
378
#include "hw/boards.h"
379
-#include "hw/arm/arm.h"
380
+#include "hw/arm/boot.h"
381
#include "sysemu/sysemu.h"
382
#include "exec/address-spaces.h"
383
384
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
385
index XXXXXXX..XXXXXXX 100644
386
--- a/hw/arm/mps2-tz.c
387
+++ b/hw/arm/mps2-tz.c
388
@@ -XXX,XX +XXX,XX @@
389
#include "qemu/osdep.h"
390
#include "qapi/error.h"
391
#include "qemu/error-report.h"
392
-#include "hw/arm/arm.h"
393
+#include "hw/arm/boot.h"
394
#include "hw/arm/armv7m.h"
395
#include "hw/or-irq.h"
396
#include "hw/boards.h"
397
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
398
index XXXXXXX..XXXXXXX 100644
399
--- a/hw/arm/mps2.c
400
+++ b/hw/arm/mps2.c
401
@@ -XXX,XX +XXX,XX @@
402
#include "qemu/osdep.h"
403
#include "qapi/error.h"
404
#include "qemu/error-report.h"
405
-#include "hw/arm/arm.h"
406
+#include "hw/arm/boot.h"
407
#include "hw/arm/armv7m.h"
408
#include "hw/or-irq.h"
409
#include "hw/boards.h"
410
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
411
index XXXXXXX..XXXXXXX 100644
412
--- a/hw/arm/msf2-soc.c
413
+++ b/hw/arm/msf2-soc.c
414
@@ -XXX,XX +XXX,XX @@
415
#include "qemu/units.h"
416
#include "qapi/error.h"
417
#include "qemu-common.h"
418
-#include "hw/arm/arm.h"
419
#include "exec/address-spaces.h"
420
#include "hw/char/serial.h"
421
#include "hw/boards.h"
422
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
423
index XXXXXXX..XXXXXXX 100644
424
--- a/hw/arm/msf2-som.c
425
+++ b/hw/arm/msf2-som.c
426
@@ -XXX,XX +XXX,XX @@
427
#include "qapi/error.h"
428
#include "qemu/error-report.h"
429
#include "hw/boards.h"
430
-#include "hw/arm/arm.h"
431
+#include "hw/arm/boot.h"
432
#include "exec/address-spaces.h"
433
#include "hw/arm/msf2-soc.h"
434
#include "cpu.h"
435
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
436
index XXXXXXX..XXXXXXX 100644
437
--- a/hw/arm/musca.c
438
+++ b/hw/arm/musca.c
439
@@ -XXX,XX +XXX,XX @@
440
#include "qapi/error.h"
441
#include "exec/address-spaces.h"
442
#include "sysemu/sysemu.h"
443
-#include "hw/arm/arm.h"
444
+#include "hw/arm/boot.h"
445
#include "hw/arm/armsse.h"
446
#include "hw/boards.h"
447
#include "hw/char/pl011.h"
448
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
449
index XXXXXXX..XXXXXXX 100644
450
--- a/hw/arm/musicpal.c
451
+++ b/hw/arm/musicpal.c
452
@@ -XXX,XX +XXX,XX @@
453
#include "qemu-common.h"
454
#include "cpu.h"
455
#include "hw/sysbus.h"
456
-#include "hw/arm/arm.h"
457
+#include "hw/arm/boot.h"
458
#include "net/net.h"
459
#include "sysemu/sysemu.h"
460
#include "hw/boards.h"
461
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
462
index XXXXXXX..XXXXXXX 100644
463
--- a/hw/arm/netduino2.c
464
+++ b/hw/arm/netduino2.c
465
@@ -XXX,XX +XXX,XX @@
466
#include "hw/boards.h"
467
#include "qemu/error-report.h"
468
#include "hw/arm/stm32f205_soc.h"
469
-#include "hw/arm/arm.h"
470
+#include "hw/arm/boot.h"
471
472
static void netduino2_init(MachineState *machine)
473
{
474
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
475
index XXXXXXX..XXXXXXX 100644
476
--- a/hw/arm/nrf51_soc.c
477
+++ b/hw/arm/nrf51_soc.c
478
@@ -XXX,XX +XXX,XX @@
479
#include "qemu/osdep.h"
480
#include "qapi/error.h"
481
#include "qemu-common.h"
482
-#include "hw/arm/arm.h"
483
+#include "hw/arm/boot.h"
484
#include "hw/sysbus.h"
485
#include "hw/boards.h"
486
#include "hw/misc/unimp.h"
487
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
488
index XXXXXXX..XXXXXXX 100644
489
--- a/hw/arm/nseries.c
490
+++ b/hw/arm/nseries.c
491
@@ -XXX,XX +XXX,XX @@
492
#include "qemu/bswap.h"
493
#include "sysemu/sysemu.h"
494
#include "hw/arm/omap.h"
495
-#include "hw/arm/arm.h"
496
+#include "hw/arm/boot.h"
497
#include "hw/irq.h"
498
#include "ui/console.h"
499
#include "hw/boards.h"
500
diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
501
index XXXXXXX..XXXXXXX 100644
502
--- a/hw/arm/omap1.c
503
+++ b/hw/arm/omap1.c
504
@@ -XXX,XX +XXX,XX @@
505
#include "cpu.h"
506
#include "hw/boards.h"
507
#include "hw/hw.h"
508
-#include "hw/arm/arm.h"
509
+#include "hw/arm/boot.h"
510
#include "hw/arm/omap.h"
511
#include "sysemu/sysemu.h"
512
#include "hw/arm/soc_dma.h"
513
diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
514
index XXXXXXX..XXXXXXX 100644
515
--- a/hw/arm/omap2.c
516
+++ b/hw/arm/omap2.c
517
@@ -XXX,XX +XXX,XX @@
518
#include "sysemu/qtest.h"
519
#include "hw/boards.h"
520
#include "hw/hw.h"
521
-#include "hw/arm/arm.h"
522
+#include "hw/arm/boot.h"
523
#include "hw/arm/omap.h"
524
#include "sysemu/sysemu.h"
525
#include "qemu/timer.h"
526
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
527
index XXXXXXX..XXXXXXX 100644
528
--- a/hw/arm/omap_sx1.c
529
+++ b/hw/arm/omap_sx1.c
530
@@ -XXX,XX +XXX,XX @@
531
#include "ui/console.h"
532
#include "hw/arm/omap.h"
533
#include "hw/boards.h"
534
-#include "hw/arm/arm.h"
535
+#include "hw/arm/boot.h"
536
#include "hw/block/flash.h"
537
#include "sysemu/qtest.h"
538
#include "exec/address-spaces.h"
539
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
540
index XXXXXXX..XXXXXXX 100644
541
--- a/hw/arm/palm.c
542
+++ b/hw/arm/palm.c
543
@@ -XXX,XX +XXX,XX @@
544
#include "ui/console.h"
545
#include "hw/arm/omap.h"
546
#include "hw/boards.h"
547
-#include "hw/arm/arm.h"
548
+#include "hw/arm/boot.h"
549
#include "hw/input/tsc2xxx.h"
550
#include "hw/loader.h"
551
#include "exec/address-spaces.h"
552
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
553
index XXXXXXX..XXXXXXX 100644
554
--- a/hw/arm/raspi.c
555
+++ b/hw/arm/raspi.c
556
@@ -XXX,XX +XXX,XX @@
557
#include "qemu/error-report.h"
558
#include "hw/boards.h"
559
#include "hw/loader.h"
560
-#include "hw/arm/arm.h"
561
+#include "hw/arm/boot.h"
562
#include "sysemu/sysemu.h"
563
564
#define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS */
565
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
566
index XXXXXXX..XXXXXXX 100644
567
--- a/hw/arm/realview.c
568
+++ b/hw/arm/realview.c
569
@@ -XXX,XX +XXX,XX @@
570
#include "qemu-common.h"
571
#include "cpu.h"
572
#include "hw/sysbus.h"
573
-#include "hw/arm/arm.h"
574
+#include "hw/arm/boot.h"
575
#include "hw/arm/primecell.h"
576
#include "hw/net/lan9118.h"
577
#include "hw/net/smc91c111.h"
578
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
579
index XXXXXXX..XXXXXXX 100644
580
--- a/hw/arm/spitz.c
581
+++ b/hw/arm/spitz.c
582
@@ -XXX,XX +XXX,XX @@
583
#include "qapi/error.h"
584
#include "hw/hw.h"
585
#include "hw/arm/pxa.h"
586
-#include "hw/arm/arm.h"
587
+#include "hw/arm/boot.h"
588
#include "sysemu/sysemu.h"
589
#include "hw/pcmcia.h"
590
#include "hw/i2c/i2c.h"
591
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
592
index XXXXXXX..XXXXXXX 100644
593
--- a/hw/arm/stellaris.c
594
+++ b/hw/arm/stellaris.c
595
@@ -XXX,XX +XXX,XX @@
596
#include "qapi/error.h"
597
#include "hw/sysbus.h"
598
#include "hw/ssi/ssi.h"
599
-#include "hw/arm/arm.h"
600
+#include "hw/arm/boot.h"
601
#include "qemu/timer.h"
602
#include "hw/i2c/i2c.h"
603
#include "net/net.h"
604
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
605
index XXXXXXX..XXXXXXX 100644
606
--- a/hw/arm/stm32f205_soc.c
607
+++ b/hw/arm/stm32f205_soc.c
608
@@ -XXX,XX +XXX,XX @@
609
#include "qemu/osdep.h"
610
#include "qapi/error.h"
611
#include "qemu-common.h"
612
-#include "hw/arm/arm.h"
613
+#include "hw/arm/boot.h"
614
#include "exec/address-spaces.h"
615
#include "hw/arm/stm32f205_soc.h"
616
617
diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
618
index XXXXXXX..XXXXXXX 100644
619
--- a/hw/arm/strongarm.c
620
+++ b/hw/arm/strongarm.c
621
@@ -XXX,XX +XXX,XX @@
622
#include "hw/sysbus.h"
623
#include "strongarm.h"
624
#include "qemu/error-report.h"
625
-#include "hw/arm/arm.h"
626
+#include "hw/arm/boot.h"
627
#include "chardev/char-fe.h"
628
#include "chardev/char-serial.h"
629
#include "sysemu/sysemu.h"
630
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
631
index XXXXXXX..XXXXXXX 100644
632
--- a/hw/arm/tosa.c
633
+++ b/hw/arm/tosa.c
634
@@ -XXX,XX +XXX,XX @@
635
#include "qapi/error.h"
636
#include "hw/hw.h"
637
#include "hw/arm/pxa.h"
638
-#include "hw/arm/arm.h"
639
+#include "hw/arm/boot.h"
640
#include "hw/arm/sharpsl.h"
641
#include "hw/pcmcia.h"
642
#include "hw/boards.h"
643
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
644
index XXXXXXX..XXXXXXX 100644
645
--- a/hw/arm/versatilepb.c
646
+++ b/hw/arm/versatilepb.c
647
@@ -XXX,XX +XXX,XX @@
648
#include "qemu-common.h"
649
#include "cpu.h"
650
#include "hw/sysbus.h"
651
-#include "hw/arm/arm.h"
652
+#include "hw/arm/boot.h"
653
#include "hw/net/smc91c111.h"
654
#include "net/net.h"
655
#include "sysemu/sysemu.h"
656
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
657
index XXXXXXX..XXXXXXX 100644
658
--- a/hw/arm/vexpress.c
659
+++ b/hw/arm/vexpress.c
660
@@ -XXX,XX +XXX,XX @@
661
#include "qemu-common.h"
662
#include "cpu.h"
663
#include "hw/sysbus.h"
664
-#include "hw/arm/arm.h"
665
+#include "hw/arm/boot.h"
666
#include "hw/arm/primecell.h"
667
#include "hw/net/lan9118.h"
668
#include "hw/i2c/i2c.h"
669
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
50
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
670
index XXXXXXX..XXXXXXX 100644
51
index XXXXXXX..XXXXXXX 100644
671
--- a/hw/arm/virt.c
52
--- a/hw/arm/virt.c
672
+++ b/hw/arm/virt.c
53
+++ b/hw/arm/virt.c
673
@@ -XXX,XX +XXX,XX @@
54
@@ -XXX,XX +XXX,XX @@ static void create_its(VirtMachineState *vms)
674
#include "qemu/option.h"
55
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base);
675
#include "qapi/error.h"
56
676
#include "hw/sysbus.h"
57
fdt_add_its_gic_node(vms);
677
-#include "hw/arm/arm.h"
58
+ vms->msi_controller = VIRT_MSI_CTRL_ITS;
678
+#include "hw/arm/boot.h"
59
}
679
#include "hw/arm/primecell.h"
60
680
#include "hw/arm/virt.h"
61
static void create_v2m(VirtMachineState *vms)
681
#include "hw/block/flash.h"
62
@@ -XXX,XX +XXX,XX @@ static void create_v2m(VirtMachineState *vms)
682
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
63
}
683
index XXXXXXX..XXXXXXX 100644
64
684
--- a/hw/arm/xilinx_zynq.c
65
fdt_add_v2m_gic_node(vms);
685
+++ b/hw/arm/xilinx_zynq.c
66
+ vms->msi_controller = VIRT_MSI_CTRL_GICV2M;
686
@@ -XXX,XX +XXX,XX @@
67
}
687
#include "qemu-common.h"
68
688
#include "cpu.h"
69
static void create_gic(VirtMachineState *vms)
689
#include "hw/sysbus.h"
70
@@ -XXX,XX +XXX,XX @@ out:
690
-#include "hw/arm/arm.h"
71
static void virt_machine_device_pre_plug_cb(HotplugHandler *hotplug_dev,
691
+#include "hw/arm/boot.h"
72
DeviceState *dev, Error **errp)
692
#include "net/net.h"
73
{
693
#include "exec/address-spaces.h"
74
+ VirtMachineState *vms = VIRT_MACHINE(hotplug_dev);
694
#include "sysemu/sysemu.h"
75
+
695
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
76
if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM)) {
696
index XXXXXXX..XXXXXXX 100644
77
virt_memory_pre_plug(hotplug_dev, dev, errp);
697
--- a/hw/arm/xlnx-versal.c
78
+ } else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
698
+++ b/hw/arm/xlnx-versal.c
79
+ hwaddr db_start = 0, db_end = 0;
699
@@ -XXX,XX +XXX,XX @@
80
+ char *resv_prop_str;
700
#include "net/net.h"
81
+
701
#include "sysemu/sysemu.h"
82
+ switch (vms->msi_controller) {
702
#include "sysemu/kvm.h"
83
+ case VIRT_MSI_CTRL_NONE:
703
-#include "hw/arm/arm.h"
84
+ return;
704
+#include "hw/arm/boot.h"
85
+ case VIRT_MSI_CTRL_ITS:
705
#include "kvm_arm.h"
86
+ /* GITS_TRANSLATER page */
706
#include "hw/misc/unimp.h"
87
+ db_start = base_memmap[VIRT_GIC_ITS].base + 0x10000;
707
#include "hw/intc/arm_gicv3_common.h"
88
+ db_end = base_memmap[VIRT_GIC_ITS].base +
708
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
89
+ base_memmap[VIRT_GIC_ITS].size - 1;
709
index XXXXXXX..XXXXXXX 100644
90
+ break;
710
--- a/hw/arm/z2.c
91
+ case VIRT_MSI_CTRL_GICV2M:
711
+++ b/hw/arm/z2.c
92
+ /* MSI_SETSPI_NS page */
712
@@ -XXX,XX +XXX,XX @@
93
+ db_start = base_memmap[VIRT_GIC_V2M].base;
713
#include "qemu/osdep.h"
94
+ db_end = db_start + base_memmap[VIRT_GIC_V2M].size - 1;
714
#include "hw/hw.h"
95
+ break;
715
#include "hw/arm/pxa.h"
96
+ }
716
-#include "hw/arm/arm.h"
97
+ resv_prop_str = g_strdup_printf("0x%"PRIx64":0x%"PRIx64":%u",
717
+#include "hw/arm/boot.h"
98
+ db_start, db_end,
718
#include "hw/i2c/i2c.h"
99
+ VIRTIO_IOMMU_RESV_MEM_T_MSI);
719
#include "hw/ssi/ssi.h"
100
+
720
#include "hw/boards.h"
101
+ qdev_prop_set_uint32(dev, "len-reserved-regions", 1);
102
+ qdev_prop_set_string(dev, "reserved-regions[0]", resv_prop_str);
103
+ g_free(resv_prop_str);
104
}
105
}
106
721
--
107
--
722
2.20.1
108
2.20.1
723
109
724
110
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Beata Michalska <beata.michalska@linaro.org>
2
2
3
QEMU already supports pl330. Instantiate it for Exynos4210.
3
On ARMv7 & ARMv8 some load/store instructions might trigger a data abort
4
exception with no valid ISS info to be decoded. The lack of decode info
5
makes it at least tricky to emulate those instruction which is one of the
6
(many) reasons why KVM will not even try to do so.
4
7
5
Relevant part of Linux arch/arm/boot/dts/exynos4.dtsi:
8
Add support for handling those by requesting KVM to inject external
9
dabt into the quest.
6
10
7
/ {
11
Signed-off-by: Beata Michalska <beata.michalska@linaro.org>
8
soc: soc {
12
Reviewed-by: Andrew Jones <drjones@redhat.com>
9
amba {
13
Message-id: 20200629114110.30723-2-beata.michalska@linaro.org
10
pdma0: pdma@12680000 {
11
compatible = "arm,pl330", "arm,primecell";
12
reg = <0x12680000 0x1000>;
13
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
14
clocks = <&clock CLK_PDMA0>;
15
clock-names = "apb_pclk";
16
#dma-cells = <1>;
17
#dma-channels = <8>;
18
#dma-requests = <32>;
19
};
20
pdma1: pdma@12690000 {
21
compatible = "arm,pl330", "arm,primecell";
22
reg = <0x12690000 0x1000>;
23
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
24
clocks = <&clock CLK_PDMA1>;
25
clock-names = "apb_pclk";
26
#dma-cells = <1>;
27
#dma-channels = <8>;
28
#dma-requests = <32>;
29
};
30
mdma1: mdma@12850000 {
31
compatible = "arm,pl330", "arm,primecell";
32
reg = <0x12850000 0x1000>;
33
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
34
clocks = <&clock CLK_MDMA>;
35
clock-names = "apb_pclk";
36
#dma-cells = <1>;
37
#dma-channels = <8>;
38
#dma-requests = <1>;
39
};
40
};
41
};
42
};
43
44
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
45
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
46
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
47
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
48
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
49
Message-id: 20190520214342.13709-4-philmd@redhat.com
50
[PMD: Do not set default qdev properties, create the controllers in the SoC
51
rather than the board (Peter Maydell), add dtsi in commit message]
52
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
53
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
54
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
55
---
15
---
56
hw/arm/exynos4210.c | 26 ++++++++++++++++++++++++++
16
target/arm/kvm.c | 52 ++++++++++++++++++++++++++++++++++++++++++++++++
57
1 file changed, 26 insertions(+)
17
1 file changed, 52 insertions(+)
58
18
59
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
19
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
60
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
61
--- a/hw/arm/exynos4210.c
21
--- a/target/arm/kvm.c
62
+++ b/hw/arm/exynos4210.c
22
+++ b/target/arm/kvm.c
63
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@ const KVMCapabilityInfo kvm_arch_required_capabilities[] = {
64
/* EHCI */
24
65
#define EXYNOS4210_EHCI_BASE_ADDR 0x12580000
25
static bool cap_has_mp_state;
66
26
static bool cap_has_inject_serror_esr;
67
+/* DMA */
27
+static bool cap_has_inject_ext_dabt;
68
+#define EXYNOS4210_PL330_BASE0_ADDR 0x12680000
28
69
+#define EXYNOS4210_PL330_BASE1_ADDR 0x12690000
29
static ARMHostCPUFeatures arm_host_cpu_features;
70
+#define EXYNOS4210_PL330_BASE2_ADDR 0x12850000
30
31
@@ -XXX,XX +XXX,XX @@ int kvm_arch_init(MachineState *ms, KVMState *s)
32
ret = -EINVAL;
33
}
34
35
+ if (kvm_check_extension(s, KVM_CAP_ARM_NISV_TO_USER)) {
36
+ if (kvm_vm_enable_cap(s, KVM_CAP_ARM_NISV_TO_USER, 0)) {
37
+ error_report("Failed to enable KVM_CAP_ARM_NISV_TO_USER cap");
38
+ } else {
39
+ /* Set status for supporting the external dabt injection */
40
+ cap_has_inject_ext_dabt = kvm_check_extension(s,
41
+ KVM_CAP_ARM_INJECT_EXT_DABT);
42
+ }
43
+ }
71
+
44
+
72
static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
45
return ret;
73
0x09, 0x00, 0x00, 0x00 };
74
75
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu)
76
return (0x9 << ARM_AFF1_SHIFT) | cpu;
77
}
46
}
78
47
79
+static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
48
@@ -XXX,XX +XXX,XX @@ void kvm_arm_vm_state_change(void *opaque, int running, RunState state)
49
}
50
}
51
52
+/**
53
+ * kvm_arm_handle_dabt_nisv:
54
+ * @cs: CPUState
55
+ * @esr_iss: ISS encoding (limited) for the exception from Data Abort
56
+ * ISV bit set to '0b0' -> no valid instruction syndrome
57
+ * @fault_ipa: faulting address for the synchronous data abort
58
+ *
59
+ * Returns: 0 if the exception has been handled, < 0 otherwise
60
+ */
61
+static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss,
62
+ uint64_t fault_ipa)
80
+{
63
+{
81
+ SysBusDevice *busdev;
64
+ /*
82
+ DeviceState *dev;
65
+ * Request KVM to inject the external data abort into the guest
83
+
66
+ */
84
+ dev = qdev_create(NULL, "pl330");
67
+ if (cap_has_inject_ext_dabt) {
85
+ qdev_prop_set_uint8(dev, "num_periph_req", nreq);
68
+ struct kvm_vcpu_events events = { };
86
+ qdev_init_nofail(dev);
69
+ /*
87
+ busdev = SYS_BUS_DEVICE(dev);
70
+ * The external data abort event will be handled immediately by KVM
88
+ sysbus_mmio_map(busdev, 0, base);
71
+ * using the address fault that triggered the exit on given VCPU.
89
+ sysbus_connect_irq(busdev, 0, irq);
72
+ * Requesting injection of the external data abort does not rely
73
+ * on any other VCPU state. Therefore, in this particular case, the VCPU
74
+ * synchronization can be exceptionally skipped.
75
+ */
76
+ events.exception.ext_dabt_pending = 1;
77
+ /* KVM_CAP_ARM_INJECT_EXT_DABT implies KVM_CAP_VCPU_EVENTS */
78
+ return kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events);
79
+ } else {
80
+ error_report("Data abort exception triggered by guest memory access "
81
+ "at physical address: 0x" TARGET_FMT_lx,
82
+ (target_ulong)fault_ipa);
83
+ error_printf("KVM unable to emulate faulting instruction.\n");
84
+ }
85
+ return -1;
90
+}
86
+}
91
+
87
+
92
Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
88
int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
93
{
89
{
94
Exynos4210State *s = g_new0(Exynos4210State, 1);
90
int ret = 0;
95
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
91
@@ -XXX,XX +XXX,XX @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run)
96
sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
92
ret = EXCP_DEBUG;
97
s->irq_table[exynos4210_get_irq(28, 3)]);
93
} /* otherwise return to guest */
98
94
break;
99
+ /*** DMA controllers ***/
95
+ case KVM_EXIT_ARM_NISV:
100
+ pl330_create(EXYNOS4210_PL330_BASE0_ADDR,
96
+ /* External DABT with no valid iss to decode */
101
+ qemu_irq_invert(s->irq_table[exynos4210_get_irq(35, 1)]), 32);
97
+ ret = kvm_arm_handle_dabt_nisv(cs, run->arm_nisv.esr_iss,
102
+ pl330_create(EXYNOS4210_PL330_BASE1_ADDR,
98
+ run->arm_nisv.fault_ipa);
103
+ qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
99
+ break;
104
+ pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
100
default:
105
+ qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
101
qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n",
106
+
102
__func__, run->exit_reason);
107
return s;
108
}
109
--
103
--
110
2.20.1
104
2.20.1
111
105
112
106
diff view generated by jsdifflib
1
The hw/arm/arm.h header now only includes declarations relating
1
From: Beata Michalska <beata.michalska@linaro.org>
2
to boot.c code, so it is only needed by Arm board or SoC code.
2
3
Remove some unnecessary inclusions of it from target/arm files
3
Injecting external data abort through KVM might trigger
4
and from hw/intc/armv7m_nvic.c.
4
an issue on kernels that do not get updated to include the KVM fix.
5
5
For those and aarch32 guests, the injected abort gets misconfigured
6
to be an implementation defined exception. This leads to the guest
7
repeatedly re-running the faulting instruction.
8
9
Add support for handling that case.
10
11
[
12
Fixed-by: 018f22f95e8a
13
    ('KVM: arm: Fix DFSR setting for non-LPAE aarch32 guests')
14
Fixed-by: 21aecdbd7f3a
15
    ('KVM: arm: Make inject_abt32() inject an external abort instead')
16
]
17
18
Signed-off-by: Beata Michalska <beata.michalska@linaro.org>
19
Acked-by: Andrew Jones <drjones@redhat.com>
20
Message-id: 20200629114110.30723-3-beata.michalska@linaro.org
21
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20190516163857.6430-3-peter.maydell@linaro.org
10
---
23
---
11
hw/intc/armv7m_nvic.c | 1 -
24
target/arm/cpu.h | 2 ++
12
target/arm/arm-semi.c | 1 -
25
target/arm/kvm_arm.h | 10 +++++++++
13
target/arm/cpu.c | 1 -
26
target/arm/kvm.c | 30 ++++++++++++++++++++++++++-
14
target/arm/cpu64.c | 1 -
27
target/arm/kvm32.c | 34 ++++++++++++++++++++++++++++++
15
target/arm/kvm.c | 1 -
28
target/arm/kvm64.c | 49 ++++++++++++++++++++++++++++++++++++++++++++
16
target/arm/kvm32.c | 1 -
29
5 files changed, 124 insertions(+), 1 deletion(-)
17
target/arm/kvm64.c | 1 -
30
18
7 files changed, 7 deletions(-)
31
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
19
32
index XXXXXXX..XXXXXXX 100644
20
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
33
--- a/target/arm/cpu.h
21
index XXXXXXX..XXXXXXX 100644
34
+++ b/target/arm/cpu.h
22
--- a/hw/intc/armv7m_nvic.c
35
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
23
+++ b/hw/intc/armv7m_nvic.c
36
uint64_t esr;
24
@@ -XXX,XX +XXX,XX @@
37
} serror;
25
#include "cpu.h"
38
26
#include "hw/sysbus.h"
39
+ uint8_t ext_dabt_raised; /* Tracking/verifying injection of ext DABT */
27
#include "qemu/timer.h"
40
+
28
-#include "hw/arm/arm.h"
41
/* State of our input IRQ/FIQ/VIRQ/VFIQ lines */
29
#include "hw/intc/armv7m_nvic.h"
42
uint32_t irq_line_state;
30
#include "target/arm/cpu.h"
43
31
#include "exec/exec-all.h"
44
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
32
diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
45
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/kvm_arm.h
34
--- a/target/arm/arm-semi.c
47
+++ b/target/arm/kvm_arm.h
35
+++ b/target/arm/arm-semi.c
48
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_hw_debug_active(CPUState *cs);
36
@@ -XXX,XX +XXX,XX @@
49
struct kvm_guest_debug_arch;
37
#else
50
void kvm_arm_copy_hw_debug_data(struct kvm_guest_debug_arch *ptr);
38
#include "qemu-common.h"
51
39
#include "exec/gdbstub.h"
52
+/**
40
-#include "hw/arm/arm.h"
53
+ * kvm_arm_verify_ext_dabt_pending:
41
#include "qemu/cutils.h"
54
+ * @cs: CPUState
42
#endif
55
+ *
43
56
+ * Verify the fault status code wrt the Ext DABT injection
44
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
57
+ *
45
index XXXXXXX..XXXXXXX 100644
58
+ * Returns: true if the fault status code is as expected, false otherwise
46
--- a/target/arm/cpu.c
59
+ */
47
+++ b/target/arm/cpu.c
60
+bool kvm_arm_verify_ext_dabt_pending(CPUState *cs);
48
@@ -XXX,XX +XXX,XX @@
61
+
49
#if !defined(CONFIG_USER_ONLY)
62
/**
50
#include "hw/loader.h"
63
* its_class_name:
51
#endif
64
*
52
-#include "hw/arm/arm.h"
53
#include "sysemu/sysemu.h"
54
#include "sysemu/hw_accel.h"
55
#include "kvm_arm.h"
56
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/target/arm/cpu64.c
59
+++ b/target/arm/cpu64.c
60
@@ -XXX,XX +XXX,XX @@
61
#if !defined(CONFIG_USER_ONLY)
62
#include "hw/loader.h"
63
#endif
64
-#include "hw/arm/arm.h"
65
#include "sysemu/sysemu.h"
66
#include "sysemu/kvm.h"
67
#include "kvm_arm.h"
68
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
65
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
69
index XXXXXXX..XXXXXXX 100644
66
index XXXXXXX..XXXXXXX 100644
70
--- a/target/arm/kvm.c
67
--- a/target/arm/kvm.c
71
+++ b/target/arm/kvm.c
68
+++ b/target/arm/kvm.c
72
@@ -XXX,XX +XXX,XX @@
69
@@ -XXX,XX +XXX,XX @@ int kvm_get_vcpu_events(ARMCPU *cpu)
73
#include "cpu.h"
70
74
#include "trace.h"
71
void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run)
75
#include "internals.h"
72
{
76
-#include "hw/arm/arm.h"
73
+ ARMCPU *cpu = ARM_CPU(cs);
77
#include "hw/pci/pci.h"
74
+ CPUARMState *env = &cpu->env;
78
#include "exec/memattrs.h"
75
+
79
#include "exec/address-spaces.h"
76
+ if (unlikely(env->ext_dabt_raised)) {
77
+ /*
78
+ * Verifying that the ext DABT has been properly injected,
79
+ * otherwise risking indefinitely re-running the faulting instruction
80
+ * Covering a very narrow case for kernels 5.5..5.5.4
81
+ * when injected abort was misconfigured to be
82
+ * an IMPLEMENTATION DEFINED exception (for 32-bit EL1)
83
+ */
84
+ if (!arm_feature(env, ARM_FEATURE_AARCH64) &&
85
+ unlikely(!kvm_arm_verify_ext_dabt_pending(cs))) {
86
+
87
+ error_report("Data abort exception with no valid ISS generated by "
88
+ "guest memory access. KVM unable to emulate faulting "
89
+ "instruction. Failed to inject an external data abort "
90
+ "into the guest.");
91
+ abort();
92
+ }
93
+ /* Clear the status */
94
+ env->ext_dabt_raised = 0;
95
+ }
96
}
97
98
MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run)
99
@@ -XXX,XX +XXX,XX @@ void kvm_arm_vm_state_change(void *opaque, int running, RunState state)
100
static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss,
101
uint64_t fault_ipa)
102
{
103
+ ARMCPU *cpu = ARM_CPU(cs);
104
+ CPUARMState *env = &cpu->env;
105
/*
106
* Request KVM to inject the external data abort into the guest
107
*/
108
@@ -XXX,XX +XXX,XX @@ static int kvm_arm_handle_dabt_nisv(CPUState *cs, uint64_t esr_iss,
109
*/
110
events.exception.ext_dabt_pending = 1;
111
/* KVM_CAP_ARM_INJECT_EXT_DABT implies KVM_CAP_VCPU_EVENTS */
112
- return kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events);
113
+ if (!kvm_vcpu_ioctl(cs, KVM_SET_VCPU_EVENTS, &events)) {
114
+ env->ext_dabt_raised = 1;
115
+ return 0;
116
+ }
117
} else {
118
error_report("Data abort exception triggered by guest memory access "
119
"at physical address: 0x" TARGET_FMT_lx,
80
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
120
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
81
index XXXXXXX..XXXXXXX 100644
121
index XXXXXXX..XXXXXXX 100644
82
--- a/target/arm/kvm32.c
122
--- a/target/arm/kvm32.c
83
+++ b/target/arm/kvm32.c
123
+++ b/target/arm/kvm32.c
84
@@ -XXX,XX +XXX,XX @@
124
@@ -XXX,XX +XXX,XX @@ void kvm_arm_pmu_init(CPUState *cs)
85
#include "sysemu/kvm.h"
125
{
86
#include "kvm_arm.h"
126
qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__);
87
#include "internals.h"
127
}
88
-#include "hw/arm/arm.h"
128
+
89
#include "qemu/log.h"
129
+#define ARM_REG_DFSR ARM_CP15_REG32(0, 5, 0, 0)
90
130
+#define ARM_REG_TTBCR ARM_CP15_REG32(0, 2, 0, 2)
91
static inline void set_feature(uint64_t *features, int feature)
131
+/*
132
+ *DFSR:
133
+ * TTBCR.EAE == 0
134
+ * FS[4] - DFSR[10]
135
+ * FS[3:0] - DFSR[3:0]
136
+ * TTBCR.EAE == 1
137
+ * FS, bits [5:0]
138
+ */
139
+#define DFSR_FSC(lpae, v) \
140
+ ((lpae) ? ((v) & 0x3F) : (((v) >> 6) | ((v) & 0x1F)))
141
+
142
+#define DFSC_EXTABT(lpae) ((lpae) ? 0x10 : 0x08)
143
+
144
+bool kvm_arm_verify_ext_dabt_pending(CPUState *cs)
145
+{
146
+ uint32_t dfsr_val;
147
+
148
+ if (!kvm_get_one_reg(cs, ARM_REG_DFSR, &dfsr_val)) {
149
+ ARMCPU *cpu = ARM_CPU(cs);
150
+ CPUARMState *env = &cpu->env;
151
+ uint32_t ttbcr;
152
+ int lpae = 0;
153
+
154
+ if (!kvm_get_one_reg(cs, ARM_REG_TTBCR, &ttbcr)) {
155
+ lpae = arm_feature(env, ARM_FEATURE_LPAE) && (ttbcr & TTBCR_EAE);
156
+ }
157
+ /* The verification is based on FS filed of the DFSR reg only*/
158
+ return (DFSR_FSC(lpae, dfsr_val) == DFSC_EXTABT(lpae));
159
+ }
160
+ return false;
161
+}
92
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
162
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
93
index XXXXXXX..XXXXXXX 100644
163
index XXXXXXX..XXXXXXX 100644
94
--- a/target/arm/kvm64.c
164
--- a/target/arm/kvm64.c
95
+++ b/target/arm/kvm64.c
165
+++ b/target/arm/kvm64.c
96
@@ -XXX,XX +XXX,XX @@
166
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_handle_debug(CPUState *cs, struct kvm_debug_exit_arch *debug_exit)
97
#include "sysemu/kvm.h"
167
98
#include "kvm_arm.h"
168
return false;
99
#include "internals.h"
169
}
100
-#include "hw/arm/arm.h"
170
+
101
171
+#define ARM64_REG_ESR_EL1 ARM64_SYS_REG(3, 0, 5, 2, 0)
102
static bool have_guest_debug;
172
+#define ARM64_REG_TCR_EL1 ARM64_SYS_REG(3, 0, 2, 0, 2)
103
173
+
174
+/*
175
+ * ESR_EL1
176
+ * ISS encoding
177
+ * AARCH64: DFSC, bits [5:0]
178
+ * AARCH32:
179
+ * TTBCR.EAE == 0
180
+ * FS[4] - DFSR[10]
181
+ * FS[3:0] - DFSR[3:0]
182
+ * TTBCR.EAE == 1
183
+ * FS, bits [5:0]
184
+ */
185
+#define ESR_DFSC(aarch64, lpae, v) \
186
+ ((aarch64 || (lpae)) ? ((v) & 0x3F) \
187
+ : (((v) >> 6) | ((v) & 0x1F)))
188
+
189
+#define ESR_DFSC_EXTABT(aarch64, lpae) \
190
+ ((aarch64) ? 0x10 : (lpae) ? 0x10 : 0x8)
191
+
192
+bool kvm_arm_verify_ext_dabt_pending(CPUState *cs)
193
+{
194
+ uint64_t dfsr_val;
195
+
196
+ if (!kvm_get_one_reg(cs, ARM64_REG_ESR_EL1, &dfsr_val)) {
197
+ ARMCPU *cpu = ARM_CPU(cs);
198
+ CPUARMState *env = &cpu->env;
199
+ int aarch64_mode = arm_feature(env, ARM_FEATURE_AARCH64);
200
+ int lpae = 0;
201
+
202
+ if (!aarch64_mode) {
203
+ uint64_t ttbcr;
204
+
205
+ if (!kvm_get_one_reg(cs, ARM64_REG_TCR_EL1, &ttbcr)) {
206
+ lpae = arm_feature(env, ARM_FEATURE_LPAE)
207
+ && (ttbcr & TTBCR_EAE);
208
+ }
209
+ }
210
+ /*
211
+ * The verification here is based on the DFSC bits
212
+ * of the ESR_EL1 reg only
213
+ */
214
+ return (ESR_DFSC(aarch64_mode, lpae, dfsr_val) ==
215
+ ESR_DFSC_EXTABT(aarch64_mode, lpae));
216
+ }
217
+ return false;
218
+}
104
--
219
--
105
2.20.1
220
2.20.1
106
221
107
222
diff view generated by jsdifflib
New patch
1
From: Andrew Jones <drjones@redhat.com>
1
2
3
Fixes: 93dd625f8bf7 ("tests/acpi: update expected data files")
4
Signed-off-by: Andrew Jones <drjones@redhat.com>
5
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
6
Reviewed-by: Eric Auger <eric.auger@redhat.com>
7
Message-id: 20200629140938.17566-2-drjones@redhat.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
tests/qtest/bios-tables-test-allowed-diff.h | 18 ------------------
11
1 file changed, 18 deletions(-)
12
13
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/tests/qtest/bios-tables-test-allowed-diff.h
16
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
17
@@ -1,19 +1 @@
18
/* List of comma-separated changed AML files to ignore */
19
-"tests/data/acpi/pc/DSDT",
20
-"tests/data/acpi/pc/DSDT.acpihmat",
21
-"tests/data/acpi/pc/DSDT.bridge",
22
-"tests/data/acpi/pc/DSDT.cphp",
23
-"tests/data/acpi/pc/DSDT.dimmpxm",
24
-"tests/data/acpi/pc/DSDT.ipmikcs",
25
-"tests/data/acpi/pc/DSDT.memhp",
26
-"tests/data/acpi/pc/DSDT.numamem",
27
-"tests/data/acpi/q35/DSDT",
28
-"tests/data/acpi/q35/DSDT.acpihmat",
29
-"tests/data/acpi/q35/DSDT.bridge",
30
-"tests/data/acpi/q35/DSDT.cphp",
31
-"tests/data/acpi/q35/DSDT.dimmpxm",
32
-"tests/data/acpi/q35/DSDT.ipmibt",
33
-"tests/data/acpi/q35/DSDT.memhp",
34
-"tests/data/acpi/q35/DSDT.mmio64",
35
-"tests/data/acpi/q35/DSDT.numamem",
36
-"tests/data/acpi/q35/DSDT.tis",
37
--
38
2.20.1
39
40
diff view generated by jsdifflib
New patch
1
From: Andrew Jones <drjones@redhat.com>
1
2
3
Signed-off-by: Andrew Jones <drjones@redhat.com>
4
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
5
Reviewed-by: Eric Auger <eric.auger@redhat.com>
6
Message-id: 20200629140938.17566-3-drjones@redhat.com
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
10
1 file changed, 3 insertions(+)
11
12
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
13
index XXXXXXX..XXXXXXX 100644
14
--- a/tests/qtest/bios-tables-test-allowed-diff.h
15
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
16
@@ -1 +1,4 @@
17
/* List of comma-separated changed AML files to ignore */
18
+"tests/data/acpi/virt/DSDT",
19
+"tests/data/acpi/virt/DSDT.memhp",
20
+"tests/data/acpi/virt/DSDT.numamem",
21
--
22
2.20.1
23
24
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Andrew Jones <drjones@redhat.com>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
3
The flash device is exclusively for the host-controlled firmware, so
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
4
we should not expose it to the OS. Exposing it risks the OS messing
5
Message-id: 20190520214342.13709-2-philmd@redhat.com
5
with it, which could break firmware runtime services and surprise the
6
OS when all its changes disappear after reboot.
7
8
As firmware needs the device and uses DT, we leave the device exposed
9
there. It's up to firmware to remove the nodes from DT before sending
10
it on to the OS. However, there's no need to force firmware to remove
11
tables from ACPI (which it doesn't know how to do anyway), so we
12
simply don't add the tables in the first place. But, as we've been
13
adding the tables for quite some time and don't want to change the
14
default hardware exposed to versioned machines, then we only stop
15
exposing the flash device tables for 5.1 and later machine types.
16
17
Suggested-by: Ard Biesheuvel <ard.biesheuvel@arm.com>
18
Suggested-by: Laszlo Ersek <lersek@redhat.com>
19
Signed-off-by: Andrew Jones <drjones@redhat.com>
20
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
21
Reviewed-by: Eric Auger <eric.auger@redhat.com>
22
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
23
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
24
Message-id: 20200629140938.17566-4-drjones@redhat.com
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
26
---
8
hw/arm/exynos4_boards.c | 24 ------------------------
27
include/hw/arm/virt.h | 1 +
9
1 file changed, 24 deletions(-)
28
hw/arm/virt-acpi-build.c | 5 ++++-
29
hw/arm/virt.c | 3 +++
30
3 files changed, 8 insertions(+), 1 deletion(-)
10
31
11
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
32
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
12
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/arm/exynos4_boards.c
34
--- a/include/hw/arm/virt.h
14
+++ b/hw/arm/exynos4_boards.c
35
+++ b/include/hw/arm/virt.h
15
@@ -XXX,XX +XXX,XX @@
36
@@ -XXX,XX +XXX,XX @@ typedef struct {
16
#include "hw/net/lan9118.h"
37
bool no_highmem_ecam;
17
#include "hw/boards.h"
38
bool no_ged; /* Machines < 4.2 has no support for ACPI GED device */
18
39
bool kvm_no_adjvtime;
19
-#undef DEBUG
40
+ bool acpi_expose_flash;
20
-
41
} VirtMachineClass;
21
-//#define DEBUG
42
22
-
43
typedef struct {
23
-#ifdef DEBUG
44
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
24
- #undef PRINT_DEBUG
45
index XXXXXXX..XXXXXXX 100644
25
- #define PRINT_DEBUG(fmt, args...) \
46
--- a/hw/arm/virt-acpi-build.c
26
- do { \
47
+++ b/hw/arm/virt-acpi-build.c
27
- fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
48
@@ -XXX,XX +XXX,XX @@ static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker,
28
- } while (0)
49
static void
29
-#else
50
build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
30
- #define PRINT_DEBUG(fmt, args...) do {} while (0)
51
{
31
-#endif
52
+ VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(vms);
32
-
53
Aml *scope, *dsdt;
33
#define SMDK_LAN9118_BASE_ADDR 0x05000000
54
MachineState *ms = MACHINE(vms);
34
55
const MemMapEntry *memmap = vms->memmap;
35
typedef enum Exynos4BoardType {
56
@@ -XXX,XX +XXX,XX @@ build_dsdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
36
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
57
acpi_dsdt_add_cpus(scope, vms->smp_cpus);
37
exynos4_board_binfo.gic_cpu_if_addr =
58
acpi_dsdt_add_uart(scope, &memmap[VIRT_UART],
38
EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100;
59
(irqmap[VIRT_UART] + ARM_SPI_BASE));
39
60
- acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
40
- PRINT_DEBUG("\n ram_size: %luMiB [0x%08lx]\n"
61
+ if (vmc->acpi_expose_flash) {
41
- " kernel_filename: %s\n"
62
+ acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]);
42
- " kernel_cmdline: %s\n"
63
+ }
43
- " initrd_filename: %s\n",
64
acpi_dsdt_add_fw_cfg(scope, &memmap[VIRT_FW_CFG]);
44
- exynos4_board_ram_size[board_type] / 1048576,
65
acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO],
45
- exynos4_board_ram_size[board_type],
66
(irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPORTS);
46
- machine->kernel_filename,
67
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
47
- machine->kernel_cmdline,
68
index XXXXXXX..XXXXXXX 100644
48
- machine->initrd_filename);
69
--- a/hw/arm/virt.c
49
-
70
+++ b/hw/arm/virt.c
50
exynos4_boards_init_ram(s, get_system_memory(),
71
@@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(5, 1)
51
exynos4_board_ram_size[board_type]);
72
73
static void virt_machine_5_0_options(MachineClass *mc)
74
{
75
+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
76
+
77
virt_machine_5_1_options(mc);
78
compat_props_add(mc->compat_props, hw_compat_5_0, hw_compat_5_0_len);
79
mc->numa_mem_supported = true;
80
+ vmc->acpi_expose_flash = true;
81
}
82
DEFINE_VIRT_MACHINE(5, 0)
52
83
53
--
84
--
54
2.20.1
85
2.20.1
55
86
56
87
diff view generated by jsdifflib
1
From: Alistair Francis <alistair.francis@wdc.com>
1
From: Andrew Jones <drjones@redhat.com>
2
2
3
Commit 89e68b575 "target/arm: Use vector operations for saturation"
3
Differences between disassembled ASL files for DSDT:
4
causes this abort() when booting QEMU ARM with a Cortex-A15:
5
4
6
0 0x00007ffff4c2382f in raise () at /usr/lib/libc.so.6
5
@@ -XXX,XX +XXX,XX @@
7
1 0x00007ffff4c0e672 in abort () at /usr/lib/libc.so.6
6
*
8
2 0x00005555559c1839 in disas_neon_data_insn (insn=<optimized out>, s=<optimized out>) at ./target/arm/translate.c:6673
7
* Disassembling to symbolic ASL+ operators
9
3 0x00005555559c1839 in disas_neon_data_insn (s=<optimized out>, insn=<optimized out>) at ./target/arm/translate.c:6386
8
*
10
4 0x00005555559cd8a4 in disas_arm_insn (insn=4081107068, s=0x7fffe59a9510) at ./target/arm/translate.c:9289
9
- * Disassembly of a, Mon Jun 29 09:50:01 2020
11
5 0x00005555559cd8a4 in arm_tr_translate_insn (dcbase=0x7fffe59a9510, cpu=<optimized out>) at ./target/arm/translate.c:13612
10
+ * Disassembly of b, Mon Jun 29 09:50:03 2020
12
6 0x00005555558d1d39 in translator_loop (ops=0x5555561cc580 <arm_translator_ops>, db=0x7fffe59a9510, cpu=0x55555686a2f0, tb=<optimized out>, max_insns=<optimized out>) at ./accel/tcg/translator.c:96
11
*
13
7 0x00005555559d10d4 in gen_intermediate_code (cpu=cpu@entry=0x55555686a2f0, tb=tb@entry=0x7fffd7840080 <code_gen_buffer+126091347>, max_insns=max_insns@entry=512) at ./target/arm/translate.c:13901
12
* Original Table Header:
14
8 0x00005555558d06b9 in tb_gen_code (cpu=cpu@entry=0x55555686a2f0, pc=3067096216, cs_base=0, flags=192, cflags=-16252928, cflags@entry=524288) at ./accel/tcg/translate-all.c:1736
13
* Signature "DSDT"
15
9 0x00005555558ce467 in tb_find (cf_mask=524288, tb_exit=1, last_tb=0x7fffd783e640 <code_gen_buffer+126084627>, cpu=0x1) at ./accel/tcg/cpu-exec.c:407
14
- * Length 0x000014BB (5307)
16
10 0x00005555558ce467 in cpu_exec (cpu=cpu@entry=0x55555686a2f0) at ./accel/tcg/cpu-exec.c:728
15
+ * Length 0x00001455 (5205)
17
11 0x000055555588b0cf in tcg_cpu_exec (cpu=0x55555686a2f0) at ./cpus.c:1431
16
* Revision 0x02
18
12 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=0x55555686a2f0) at ./cpus.c:1735
17
- * Checksum 0xD1
19
13 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=arg@entry=0x55555686a2f0) at ./cpus.c:1709
18
+ * Checksum 0xE1
20
14 0x0000555555d2629a in qemu_thread_start (args=<optimized out>) at ./util/qemu-thread-posix.c:502
19
* OEM ID "BOCHS "
21
15 0x00007ffff4db8a92 in start_thread () at /usr/lib/libpthread.
20
* OEM Table ID "BXPCDSDT"
21
* OEM Revision 0x00000001 (1)
22
@@ -XXX,XX +XXX,XX @@
23
})
24
}
22
25
23
This patch ensures that we don't hit the abort() in the second switch
26
- Device (FLS0)
24
case in disas_neon_data_insn() as we will return from the first case.
27
- {
28
- Name (_HID, "LNRO0015") // _HID: Hardware ID
29
- Name (_UID, Zero) // _UID: Unique ID
30
- Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
31
- {
32
- Memory32Fixed (ReadWrite,
33
- 0x00000000, // Address Base
34
- 0x04000000, // Address Length
35
- )
36
- })
37
- }
38
-
39
- Device (FLS1)
40
- {
41
- Name (_HID, "LNRO0015") // _HID: Hardware ID
42
- Name (_UID, One) // _UID: Unique ID
43
- Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
44
- {
45
- Memory32Fixed (ReadWrite,
46
- 0x04000000, // Address Base
47
- 0x04000000, // Address Length
48
- )
49
- })
50
- }
51
-
52
Device (FWCF)
53
{
54
Name (_HID, "QEMU0002") // _HID: Hardware ID
25
55
26
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
56
The other two binaries have the same changes (the removal of the
27
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
57
flash devices).
58
59
Signed-off-by: Andrew Jones <drjones@redhat.com>
60
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
61
Reviewed-by: Eric Auger <eric.auger@redhat.com>
28
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
62
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
29
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
63
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
30
Tested-by: Alex Bennée <alex.bennee@linaro.org>
64
Message-id: 20200629140938.17566-5-drjones@redhat.com
31
Message-id: ad91b397f360b2fc7f4087e476f7df5b04d42ddb.1558021877.git.alistair.francis@wdc.com
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
65
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
---
66
---
34
target/arm/translate.c | 4 ++--
67
tests/qtest/bios-tables-test-allowed-diff.h | 3 ---
35
1 file changed, 2 insertions(+), 2 deletions(-)
68
tests/data/acpi/virt/DSDT | Bin 5307 -> 5205 bytes
69
tests/data/acpi/virt/DSDT.memhp | Bin 6668 -> 6566 bytes
70
tests/data/acpi/virt/DSDT.numamem | Bin 5307 -> 5205 bytes
71
4 files changed, 3 deletions(-)
36
72
37
diff --git a/target/arm/translate.c b/target/arm/translate.c
73
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h
38
index XXXXXXX..XXXXXXX 100644
74
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/translate.c
75
--- a/tests/qtest/bios-tables-test-allowed-diff.h
40
+++ b/target/arm/translate.c
76
+++ b/tests/qtest/bios-tables-test-allowed-diff.h
41
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
77
@@ -1,4 +1 @@
42
tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
78
/* List of comma-separated changed AML files to ignore */
43
rn_ofs, rm_ofs, vec_size, vec_size,
79
-"tests/data/acpi/virt/DSDT",
44
(u ? uqadd_op : sqadd_op) + size);
80
-"tests/data/acpi/virt/DSDT.memhp",
45
- break;
81
-"tests/data/acpi/virt/DSDT.numamem",
46
+ return 0;
82
diff --git a/tests/data/acpi/virt/DSDT b/tests/data/acpi/virt/DSDT
47
83
index XXXXXXX..XXXXXXX 100644
48
case NEON_3R_VQSUB:
84
GIT binary patch
49
tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
85
delta 28
50
rn_ofs, rm_ofs, vec_size, vec_size,
86
kcmdn3c~yhUCD<h-RD^+n>ET2!X{H9}iRuX(-<}f&0DgxFc>n+a
51
(u ? uqsub_op : sqsub_op) + size);
87
52
- break;
88
delta 156
53
+ return 0;
89
zcmcbrv0IbNCD<iow+I6R)5VEg(oAih6V(&y4c&Z#4LIUGJY9Hw{DS-q3=B;fIO0P+
54
90
zU4W!>P_UpN7hfAE10w?juv9WcH-WSmV$;Hiu7w4t3#`S$E!^1+q9xGPH`KtuzzAr5
55
case NEON_3R_VMUL: /* VMUL */
91
LaERl^1zUvy_;n(J
56
if (u) {
92
93
diff --git a/tests/data/acpi/virt/DSDT.memhp b/tests/data/acpi/virt/DSDT.memhp
94
index XXXXXXX..XXXXXXX 100644
95
GIT binary patch
96
delta 28
97
kcmeA%S!T@T66_MPOp<|tiD@F2G*jb@iRuX(-^xn@0CHUjRR910
98
99
delta 156
100
zcmZ2x++)J!66_MfBgMeL^l>7WG*kP$iRuaUhHgH=1|0Doo-VvTenI{Q28N~#9Py!^
101
zE<n;bC|FRCi?5B7fsp|MSSlH!n?PC&v1wsM*TMqS1=eEW7Vhi@(GuwD8){%+U<5Qj
102
LIK*+|0yaqism~!^
103
104
diff --git a/tests/data/acpi/virt/DSDT.numamem b/tests/data/acpi/virt/DSDT.numamem
105
index XXXXXXX..XXXXXXX 100644
106
GIT binary patch
107
delta 28
108
kcmdn3c~yhUCD<h-RD^+n>ET2!X{H9}iRuX(-<}f&0DgxFc>n+a
109
110
delta 156
111
zcmcbrv0IbNCD<iow+I6R)5VEg(oAih6V(&y4c&Z#4LIUGJY9Hw{DS-q3=B;fIO0P+
112
zU4W!>P_UpN7hfAE10w?juv9WcH-WSmV$;Hiu7w4t3#`S$E!^1+q9xGPH`KtuzzAr5
113
LaERl^1zUvy_;n(J
114
57
--
115
--
58
2.20.1
116
2.20.1
59
117
60
118
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This is, after all, how we implement extract2 in tcg/aarch64.
3
The temp that gets assigned to clean_addr has been allocated with
4
new_tmp_a64, which means that it will be freed at the end of the
5
instruction. Freeing it earlier leads to assertion failure.
4
6
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
The loop creates a complication, in which we allocate a new local
8
temp, which does need freeing, and the final code path is shared
9
between the loop and non-loop.
10
11
Fix this complication by adding new_tmp_a64_local so that the new
12
local temp is freed at the end, and can be treated exactly like
13
the non-loop path.
14
15
Fixes: bba87d0a0f4
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20190514011129.11330-2-richard.henderson@linaro.org
17
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
18
Message-id: 20200702175605.1987125-1-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
20
---
10
target/arm/translate-a64.c | 38 ++++++++++++++++++++------------------
21
target/arm/translate-a64.h | 1 +
11
1 file changed, 20 insertions(+), 18 deletions(-)
22
target/arm/translate-a64.c | 6 ++++++
23
target/arm/translate-sve.c | 8 ++------
24
3 files changed, 9 insertions(+), 6 deletions(-)
12
25
26
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
27
index XXXXXXX..XXXXXXX 100644
28
--- a/target/arm/translate-a64.h
29
+++ b/target/arm/translate-a64.h
30
@@ -XXX,XX +XXX,XX @@ void unallocated_encoding(DisasContext *s);
31
} while (0)
32
33
TCGv_i64 new_tmp_a64(DisasContext *s);
34
+TCGv_i64 new_tmp_a64_local(DisasContext *s);
35
TCGv_i64 new_tmp_a64_zero(DisasContext *s);
36
TCGv_i64 cpu_reg(DisasContext *s, int reg);
37
TCGv_i64 cpu_reg_sp(DisasContext *s, int reg);
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
38
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
40
--- a/target/arm/translate-a64.c
16
+++ b/target/arm/translate-a64.c
41
+++ b/target/arm/translate-a64.c
17
@@ -XXX,XX +XXX,XX @@ static void disas_extract(DisasContext *s, uint32_t insn)
42
@@ -XXX,XX +XXX,XX @@ TCGv_i64 new_tmp_a64(DisasContext *s)
18
} else {
43
return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64();
19
tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));
44
}
20
}
45
21
- } else if (rm == rn) { /* ROR */
46
+TCGv_i64 new_tmp_a64_local(DisasContext *s)
22
- tcg_rm = cpu_reg(s, rm);
47
+{
23
- if (sf) {
48
+ assert(s->tmp_a64_count < TMP_A64_MAX);
24
- tcg_gen_rotri_i64(tcg_rd, tcg_rm, imm);
49
+ return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_local_new_i64();
25
- } else {
50
+}
26
- TCGv_i32 tmp = tcg_temp_new_i32();
27
- tcg_gen_extrl_i64_i32(tmp, tcg_rm);
28
- tcg_gen_rotri_i32(tmp, tmp, imm);
29
- tcg_gen_extu_i32_i64(tcg_rd, tmp);
30
- tcg_temp_free_i32(tmp);
31
- }
32
} else {
33
- tcg_rm = read_cpu_reg(s, rm, sf);
34
- tcg_rn = read_cpu_reg(s, rn, sf);
35
- tcg_gen_shri_i64(tcg_rm, tcg_rm, imm);
36
- tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm);
37
- tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn);
38
- if (!sf) {
39
- tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
40
+ tcg_rm = cpu_reg(s, rm);
41
+ tcg_rn = cpu_reg(s, rn);
42
+
51
+
43
+ if (sf) {
52
TCGv_i64 new_tmp_a64_zero(DisasContext *s)
44
+ /* Specialization to ROR happens in EXTRACT2. */
53
{
45
+ tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, imm);
54
TCGv_i64 t = new_tmp_a64(s);
46
+ } else {
55
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
47
+ TCGv_i32 t0 = tcg_temp_new_i32();
56
index XXXXXXX..XXXXXXX 100644
48
+
57
--- a/target/arm/translate-sve.c
49
+ tcg_gen_extrl_i64_i32(t0, tcg_rm);
58
+++ b/target/arm/translate-sve.c
50
+ if (rm == rn) {
59
@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
51
+ tcg_gen_rotri_i32(t0, t0, imm);
60
52
+ } else {
61
/* Copy the clean address into a local temp, live across the loop. */
53
+ TCGv_i32 t1 = tcg_temp_new_i32();
62
t0 = clean_addr;
54
+ tcg_gen_extrl_i64_i32(t1, tcg_rn);
63
- clean_addr = tcg_temp_local_new_i64();
55
+ tcg_gen_extract2_i32(t0, t0, t1, imm);
64
+ clean_addr = new_tmp_a64_local(s);
56
+ tcg_temp_free_i32(t1);
65
tcg_gen_mov_i64(clean_addr, t0);
57
+ }
66
- tcg_temp_free_i64(t0);
58
+ tcg_gen_extu_i32_i64(tcg_rd, t0);
67
59
+ tcg_temp_free_i32(t0);
68
gen_set_label(loop);
60
}
69
70
@@ -XXX,XX +XXX,XX @@ static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
71
tcg_gen_st_i64(t0, cpu_env, vofs + len_align);
72
tcg_temp_free_i64(t0);
73
}
74
- tcg_temp_free_i64(clean_addr);
75
}
76
77
/* Similarly for stores. */
78
@@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
79
80
/* Copy the clean address into a local temp, live across the loop. */
81
t0 = clean_addr;
82
- clean_addr = tcg_temp_local_new_i64();
83
+ clean_addr = new_tmp_a64_local(s);
84
tcg_gen_mov_i64(clean_addr, t0);
85
- tcg_temp_free_i64(t0);
86
87
gen_set_label(loop);
88
89
@@ -XXX,XX +XXX,XX @@ static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int imm)
61
}
90
}
91
tcg_temp_free_i64(t0);
62
}
92
}
93
- tcg_temp_free_i64(clean_addr);
94
}
95
96
static bool trans_LDR_zri(DisasContext *s, arg_rri *a)
63
--
97
--
64
2.20.1
98
2.20.1
65
99
66
100
diff view generated by jsdifflib
New patch
1
In bcm2835_fb_mbox_push(), Coverity complains (CID 1429989) that we
2
pass a pointer to a local struct to another function without
3
initializing all its fields. This is a real bug:
4
bcm2835_fb_reconfigure() copies the whole of our new BCM2385FBConfig
5
struct into s->config, so any fields we don't initialize will corrupt
6
the state of the device.
1
7
8
Copy the two fields which we don't want to update (pixo and alpha)
9
from the existing config so we don't accidentally change them.
10
11
Fixes: cfb7ba983857e40e88
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
14
Message-id: 20200628195436.27582-1-peter.maydell@linaro.org
15
---
16
hw/display/bcm2835_fb.c | 4 ++++
17
1 file changed, 4 insertions(+)
18
19
diff --git a/hw/display/bcm2835_fb.c b/hw/display/bcm2835_fb.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/display/bcm2835_fb.c
22
+++ b/hw/display/bcm2835_fb.c
23
@@ -XXX,XX +XXX,XX @@ static void bcm2835_fb_mbox_push(BCM2835FBState *s, uint32_t value)
24
newconf.base = s->vcram_base | (value & 0xc0000000);
25
newconf.base += BCM2835_FB_OFFSET;
26
27
+ /* Copy fields which we don't want to change from the existing config */
28
+ newconf.pixo = s->config.pixo;
29
+ newconf.alpha = s->config.alpha;
30
+
31
bcm2835_fb_validate_config(&newconf);
32
33
pitch = bcm2835_fb_get_pitch(&newconf);
34
--
35
2.20.1
36
37
diff view generated by jsdifflib
New patch
1
1
The spitz board has been around a long time, and still has a fair number
2
of hard-coded tab characters in it. We're about to do some work on
3
this source file, so start out by expanding out the tabs.
4
5
This commit is a pure whitespace only change.
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-id: 20200628142429.17111-2-peter.maydell@linaro.org
11
---
12
hw/arm/spitz.c | 156 ++++++++++++++++++++++++-------------------------
13
1 file changed, 78 insertions(+), 78 deletions(-)
14
15
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/spitz.c
18
+++ b/hw/arm/spitz.c
19
@@ -XXX,XX +XXX,XX @@
20
#include "cpu.h"
21
22
#undef REG_FMT
23
-#define REG_FMT            "0x%02lx"
24
+#define REG_FMT "0x%02lx"
25
26
/* Spitz Flash */
27
-#define FLASH_BASE        0x0c000000
28
-#define FLASH_ECCLPLB        0x00    /* Line parity 7 - 0 bit */
29
-#define FLASH_ECCLPUB        0x04    /* Line parity 15 - 8 bit */
30
-#define FLASH_ECCCP        0x08    /* Column parity 5 - 0 bit */
31
-#define FLASH_ECCCNTR        0x0c    /* ECC byte counter */
32
-#define FLASH_ECCCLRR        0x10    /* Clear ECC */
33
-#define FLASH_FLASHIO        0x14    /* Flash I/O */
34
-#define FLASH_FLASHCTL        0x18    /* Flash Control */
35
+#define FLASH_BASE 0x0c000000
36
+#define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */
37
+#define FLASH_ECCLPUB 0x04 /* Line parity 15 - 8 bit */
38
+#define FLASH_ECCCP 0x08 /* Column parity 5 - 0 bit */
39
+#define FLASH_ECCCNTR 0x0c /* ECC byte counter */
40
+#define FLASH_ECCCLRR 0x10 /* Clear ECC */
41
+#define FLASH_FLASHIO 0x14 /* Flash I/O */
42
+#define FLASH_FLASHCTL 0x18 /* Flash Control */
43
44
-#define FLASHCTL_CE0        (1 << 0)
45
-#define FLASHCTL_CLE        (1 << 1)
46
-#define FLASHCTL_ALE        (1 << 2)
47
-#define FLASHCTL_WP        (1 << 3)
48
-#define FLASHCTL_CE1        (1 << 4)
49
-#define FLASHCTL_RYBY        (1 << 5)
50
-#define FLASHCTL_NCE        (FLASHCTL_CE0 | FLASHCTL_CE1)
51
+#define FLASHCTL_CE0 (1 << 0)
52
+#define FLASHCTL_CLE (1 << 1)
53
+#define FLASHCTL_ALE (1 << 2)
54
+#define FLASHCTL_WP (1 << 3)
55
+#define FLASHCTL_CE1 (1 << 4)
56
+#define FLASHCTL_RYBY (1 << 5)
57
+#define FLASHCTL_NCE (FLASHCTL_CE0 | FLASHCTL_CE1)
58
59
#define TYPE_SL_NAND "sl-nand"
60
#define SL_NAND(obj) OBJECT_CHECK(SLNANDState, (obj), TYPE_SL_NAND)
61
@@ -XXX,XX +XXX,XX @@ static uint64_t sl_read(void *opaque, hwaddr addr, unsigned size)
62
int ryby;
63
64
switch (addr) {
65
-#define BSHR(byte, from, to)    ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
66
+#define BSHR(byte, from, to) ((s->ecc.lp[byte] >> (from - to)) & (1 << to))
67
case FLASH_ECCLPLB:
68
return BSHR(0, 4, 0) | BSHR(0, 5, 2) | BSHR(0, 6, 4) | BSHR(0, 7, 6) |
69
BSHR(1, 4, 1) | BSHR(1, 5, 3) | BSHR(1, 6, 5) | BSHR(1, 7, 7);
70
71
-#define BSHL(byte, from, to)    ((s->ecc.lp[byte] << (to - from)) & (1 << to))
72
+#define BSHL(byte, from, to) ((s->ecc.lp[byte] << (to - from)) & (1 << to))
73
case FLASH_ECCLPUB:
74
return BSHL(0, 0, 0) | BSHL(0, 1, 2) | BSHL(0, 2, 4) | BSHL(0, 3, 6) |
75
BSHL(1, 0, 1) | BSHL(1, 1, 3) | BSHL(1, 2, 5) | BSHL(1, 3, 7);
76
@@ -XXX,XX +XXX,XX @@ static void sl_nand_realize(DeviceState *dev, Error **errp)
77
78
/* Spitz Keyboard */
79
80
-#define SPITZ_KEY_STROBE_NUM    11
81
-#define SPITZ_KEY_SENSE_NUM    7
82
+#define SPITZ_KEY_STROBE_NUM 11
83
+#define SPITZ_KEY_SENSE_NUM 7
84
85
static const int spitz_gpio_key_sense[SPITZ_KEY_SENSE_NUM] = {
86
12, 17, 91, 34, 36, 38, 39
87
@@ -XXX,XX +XXX,XX @@ static int spitz_keymap[SPITZ_KEY_SENSE_NUM + 1][SPITZ_KEY_STROBE_NUM] = {
88
{ 0x52, 0x43, 0x01, 0x47, 0x49, -1 , -1 , -1 , -1 , -1 , -1 },
89
};
90
91
-#define SPITZ_GPIO_AK_INT    13    /* Remote control */
92
-#define SPITZ_GPIO_SYNC        16    /* Sync button */
93
-#define SPITZ_GPIO_ON_KEY    95    /* Power button */
94
-#define SPITZ_GPIO_SWA        97    /* Lid */
95
-#define SPITZ_GPIO_SWB        96    /* Tablet mode */
96
+#define SPITZ_GPIO_AK_INT 13 /* Remote control */
97
+#define SPITZ_GPIO_SYNC 16 /* Sync button */
98
+#define SPITZ_GPIO_ON_KEY 95 /* Power button */
99
+#define SPITZ_GPIO_SWA 97 /* Lid */
100
+#define SPITZ_GPIO_SWB 96 /* Tablet mode */
101
102
/* The special buttons are mapped to unused keys */
103
static const int spitz_gpiomap[5] = {
104
@@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_keydown(SpitzKeyboardState *s, int keycode)
105
#define SPITZ_MOD_CTRL (1 << 8)
106
#define SPITZ_MOD_FN (1 << 9)
107
108
-#define QUEUE_KEY(c)    s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
109
+#define QUEUE_KEY(c) s->fifo[(s->fifopos + s->fifolen ++) & 0xf] = c
110
111
static void spitz_keyboard_handler(void *opaque, int keycode)
112
{
113
@@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_handler(void *opaque, int keycode)
114
uint16_t code;
115
int mapcode;
116
switch (keycode) {
117
- case 0x2a:    /* Left Shift */
118
+ case 0x2a: /* Left Shift */
119
s->modifiers |= 1;
120
break;
121
case 0xaa:
122
s->modifiers &= ~1;
123
break;
124
- case 0x36:    /* Right Shift */
125
+ case 0x36: /* Right Shift */
126
s->modifiers |= 2;
127
break;
128
case 0xb6:
129
s->modifiers &= ~2;
130
break;
131
- case 0x1d:    /* Control */
132
+ case 0x1d: /* Control */
133
s->modifiers |= 4;
134
break;
135
case 0x9d:
136
s->modifiers &= ~4;
137
break;
138
- case 0x38:    /* Alt */
139
+ case 0x38: /* Alt */
140
s->modifiers |= 8;
141
break;
142
case 0xb8:
143
@@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_realize(DeviceState *dev, Error **errp)
144
145
/* LCD backlight controller */
146
147
-#define LCDTG_RESCTL    0x00
148
-#define LCDTG_PHACTRL    0x01
149
-#define LCDTG_DUTYCTRL    0x02
150
-#define LCDTG_POWERREG0    0x03
151
-#define LCDTG_POWERREG1    0x04
152
-#define LCDTG_GPOR3    0x05
153
-#define LCDTG_PICTRL    0x06
154
-#define LCDTG_POLCTRL    0x07
155
+#define LCDTG_RESCTL 0x00
156
+#define LCDTG_PHACTRL 0x01
157
+#define LCDTG_DUTYCTRL 0x02
158
+#define LCDTG_POWERREG0 0x03
159
+#define LCDTG_POWERREG1 0x04
160
+#define LCDTG_GPOR3 0x05
161
+#define LCDTG_PICTRL 0x06
162
+#define LCDTG_POLCTRL 0x07
163
164
typedef struct {
165
SSISlave ssidev;
166
@@ -XXX,XX +XXX,XX @@ static void spitz_lcdtg_realize(SSISlave *dev, Error **errp)
167
168
/* SSP devices */
169
170
-#define CORGI_SSP_PORT        2
171
+#define CORGI_SSP_PORT 2
172
173
-#define SPITZ_GPIO_LCDCON_CS    53
174
-#define SPITZ_GPIO_ADS7846_CS    14
175
-#define SPITZ_GPIO_MAX1111_CS    20
176
-#define SPITZ_GPIO_TP_INT    11
177
+#define SPITZ_GPIO_LCDCON_CS 53
178
+#define SPITZ_GPIO_ADS7846_CS 14
179
+#define SPITZ_GPIO_MAX1111_CS 20
180
+#define SPITZ_GPIO_TP_INT 11
181
182
static DeviceState *max1111;
183
184
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
185
s->enable[line] = !level;
186
}
187
188
-#define MAX1111_BATT_VOLT    1
189
-#define MAX1111_BATT_TEMP    2
190
-#define MAX1111_ACIN_VOLT    3
191
+#define MAX1111_BATT_VOLT 1
192
+#define MAX1111_BATT_TEMP 2
193
+#define MAX1111_ACIN_VOLT 3
194
195
-#define SPITZ_BATTERY_TEMP    0xe0    /* About 2.9V */
196
-#define SPITZ_BATTERY_VOLT    0xd0    /* About 4.0V */
197
-#define SPITZ_CHARGEON_ACIN    0x80    /* About 5.0V */
198
+#define SPITZ_BATTERY_TEMP 0xe0 /* About 2.9V */
199
+#define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */
200
+#define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */
201
202
static void spitz_adc_temp_on(void *opaque, int line, int level)
203
{
204
@@ -XXX,XX +XXX,XX @@ static void spitz_microdrive_attach(PXA2xxState *cpu, int slot)
205
206
/* Wm8750 and Max7310 on I2C */
207
208
-#define AKITA_MAX_ADDR    0x18
209
-#define SPITZ_WM_ADDRL    0x1b
210
-#define SPITZ_WM_ADDRH    0x1a
211
+#define AKITA_MAX_ADDR 0x18
212
+#define SPITZ_WM_ADDRL 0x1b
213
+#define SPITZ_WM_ADDRH 0x1a
214
215
-#define SPITZ_GPIO_WM    5
216
+#define SPITZ_GPIO_WM 5
217
218
static void spitz_wm8750_addr(void *opaque, int line, int level)
219
{
220
@@ -XXX,XX +XXX,XX @@ static void spitz_out_switch(void *opaque, int line, int level)
221
}
222
}
223
224
-#define SPITZ_SCP_LED_GREEN        1
225
-#define SPITZ_SCP_JK_B            2
226
-#define SPITZ_SCP_CHRG_ON        3
227
-#define SPITZ_SCP_MUTE_L        4
228
-#define SPITZ_SCP_MUTE_R        5
229
-#define SPITZ_SCP_CF_POWER        6
230
-#define SPITZ_SCP_LED_ORANGE        7
231
-#define SPITZ_SCP_JK_A            8
232
-#define SPITZ_SCP_ADC_TEMP_ON        9
233
-#define SPITZ_SCP2_IR_ON        1
234
-#define SPITZ_SCP2_AKIN_PULLUP        2
235
-#define SPITZ_SCP2_BACKLIGHT_CONT    7
236
-#define SPITZ_SCP2_BACKLIGHT_ON        8
237
-#define SPITZ_SCP2_MIC_BIAS        9
238
+#define SPITZ_SCP_LED_GREEN 1
239
+#define SPITZ_SCP_JK_B 2
240
+#define SPITZ_SCP_CHRG_ON 3
241
+#define SPITZ_SCP_MUTE_L 4
242
+#define SPITZ_SCP_MUTE_R 5
243
+#define SPITZ_SCP_CF_POWER 6
244
+#define SPITZ_SCP_LED_ORANGE 7
245
+#define SPITZ_SCP_JK_A 8
246
+#define SPITZ_SCP_ADC_TEMP_ON 9
247
+#define SPITZ_SCP2_IR_ON 1
248
+#define SPITZ_SCP2_AKIN_PULLUP 2
249
+#define SPITZ_SCP2_BACKLIGHT_CONT 7
250
+#define SPITZ_SCP2_BACKLIGHT_ON 8
251
+#define SPITZ_SCP2_MIC_BIAS 9
252
253
static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
254
DeviceState *scp0, DeviceState *scp1)
255
@@ -XXX,XX +XXX,XX @@ static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
256
qdev_connect_gpio_out(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
257
}
258
259
-#define SPITZ_GPIO_HSYNC        22
260
-#define SPITZ_GPIO_SD_DETECT        9
261
-#define SPITZ_GPIO_SD_WP        81
262
-#define SPITZ_GPIO_ON_RESET        89
263
-#define SPITZ_GPIO_BAT_COVER        90
264
-#define SPITZ_GPIO_CF1_IRQ        105
265
-#define SPITZ_GPIO_CF1_CD        94
266
-#define SPITZ_GPIO_CF2_IRQ        106
267
-#define SPITZ_GPIO_CF2_CD        93
268
+#define SPITZ_GPIO_HSYNC 22
269
+#define SPITZ_GPIO_SD_DETECT 9
270
+#define SPITZ_GPIO_SD_WP 81
271
+#define SPITZ_GPIO_ON_RESET 89
272
+#define SPITZ_GPIO_BAT_COVER 90
273
+#define SPITZ_GPIO_CF1_IRQ 105
274
+#define SPITZ_GPIO_CF1_CD 94
275
+#define SPITZ_GPIO_CF2_IRQ 106
276
+#define SPITZ_GPIO_CF2_CD 93
277
278
static int spitz_hsync;
279
280
@@ -XXX,XX +XXX,XX @@ static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
281
/* Board init. */
282
enum spitz_model_e { spitz, akita, borzoi, terrier };
283
284
-#define SPITZ_RAM    0x04000000
285
-#define SPITZ_ROM    0x00800000
286
+#define SPITZ_RAM 0x04000000
287
+#define SPITZ_ROM 0x00800000
288
289
static struct arm_boot_info spitz_binfo = {
290
.loader_start = PXA2XX_SDRAM_BASE,
291
--
292
2.20.1
293
294
diff view generated by jsdifflib
New patch
1
1
For the four Spitz-family machines (akita, borzoi, spitz, terrier)
2
create a proper abstract class SpitzMachineClass which encapsulates
3
the common behaviour, rather than having them all derive directly
4
from TYPE_MACHINE:
5
* instead of each machine class setting mc->init to a wrapper
6
function which calls spitz_common_init() with parameters,
7
put that data in the SpitzMachineClass and make spitz_common_init
8
the SpitzMachineClass machine-init function
9
* move the settings of mc->block_default_type and
10
mc->ignore_memory_transaction_failures into the SpitzMachineClass
11
class init rather than repeating them in each machine's class init
12
13
(The motivation is that we're going to want to keep some state in
14
the SpitzMachineState so we can connect GPIOs between devices created
15
in one sub-function of the machine init to devices created in a
16
different sub-function.)
17
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
20
Message-id: 20200628142429.17111-3-peter.maydell@linaro.org
21
---
22
hw/arm/spitz.c | 91 ++++++++++++++++++++++++++++++--------------------
23
1 file changed, 55 insertions(+), 36 deletions(-)
24
25
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/hw/arm/spitz.c
28
+++ b/hw/arm/spitz.c
29
@@ -XXX,XX +XXX,XX @@
30
#include "exec/address-spaces.h"
31
#include "cpu.h"
32
33
+enum spitz_model_e { spitz, akita, borzoi, terrier };
34
+
35
+typedef struct {
36
+ MachineClass parent;
37
+ enum spitz_model_e model;
38
+ int arm_id;
39
+} SpitzMachineClass;
40
+
41
+typedef struct {
42
+ MachineState parent;
43
+} SpitzMachineState;
44
+
45
+#define TYPE_SPITZ_MACHINE "spitz-common"
46
+#define SPITZ_MACHINE(obj) \
47
+ OBJECT_CHECK(SpitzMachineState, obj, TYPE_SPITZ_MACHINE)
48
+#define SPITZ_MACHINE_GET_CLASS(obj) \
49
+ OBJECT_GET_CLASS(SpitzMachineClass, obj, TYPE_SPITZ_MACHINE)
50
+#define SPITZ_MACHINE_CLASS(klass) \
51
+ OBJECT_CLASS_CHECK(SpitzMachineClass, klass, TYPE_SPITZ_MACHINE)
52
+
53
#undef REG_FMT
54
#define REG_FMT "0x%02lx"
55
56
@@ -XXX,XX +XXX,XX @@ static void spitz_gpio_setup(PXA2xxState *cpu, int slots)
57
}
58
59
/* Board init. */
60
-enum spitz_model_e { spitz, akita, borzoi, terrier };
61
-
62
#define SPITZ_RAM 0x04000000
63
#define SPITZ_ROM 0x00800000
64
65
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info spitz_binfo = {
66
.ram_size = 0x04000000,
67
};
68
69
-static void spitz_common_init(MachineState *machine,
70
- enum spitz_model_e model, int arm_id)
71
+static void spitz_common_init(MachineState *machine)
72
{
73
+ SpitzMachineClass *smc = SPITZ_MACHINE_GET_CLASS(machine);
74
+ enum spitz_model_e model = smc->model;
75
PXA2xxState *mpu;
76
DeviceState *scp0, *scp1 = NULL;
77
MemoryRegion *address_space_mem = get_system_memory();
78
@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine,
79
/* A 4.0 GB microdrive is permanently sitting in CF slot 0. */
80
spitz_microdrive_attach(mpu, 0);
81
82
- spitz_binfo.board_id = arm_id;
83
+ spitz_binfo.board_id = smc->arm_id;
84
arm_load_kernel(mpu->cpu, machine, &spitz_binfo);
85
sl_bootparam_write(SL_PXA_PARAM_BASE);
86
}
87
88
-static void spitz_init(MachineState *machine)
89
+static void spitz_common_class_init(ObjectClass *oc, void *data)
90
{
91
- spitz_common_init(machine, spitz, 0x2c9);
92
+ MachineClass *mc = MACHINE_CLASS(oc);
93
+
94
+ mc->block_default_type = IF_IDE;
95
+ mc->ignore_memory_transaction_failures = true;
96
+ mc->init = spitz_common_init;
97
}
98
99
-static void borzoi_init(MachineState *machine)
100
-{
101
- spitz_common_init(machine, borzoi, 0x33f);
102
-}
103
-
104
-static void akita_init(MachineState *machine)
105
-{
106
- spitz_common_init(machine, akita, 0x2e8);
107
-}
108
-
109
-static void terrier_init(MachineState *machine)
110
-{
111
- spitz_common_init(machine, terrier, 0x33f);
112
-}
113
+static const TypeInfo spitz_common_info = {
114
+ .name = TYPE_SPITZ_MACHINE,
115
+ .parent = TYPE_MACHINE,
116
+ .abstract = true,
117
+ .instance_size = sizeof(SpitzMachineState),
118
+ .class_size = sizeof(SpitzMachineClass),
119
+ .class_init = spitz_common_class_init,
120
+};
121
122
static void akitapda_class_init(ObjectClass *oc, void *data)
123
{
124
MachineClass *mc = MACHINE_CLASS(oc);
125
+ SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
126
127
mc->desc = "Sharp SL-C1000 (Akita) PDA (PXA270)";
128
- mc->init = akita_init;
129
- mc->ignore_memory_transaction_failures = true;
130
mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
131
+ smc->model = akita;
132
+ smc->arm_id = 0x2e8;
133
}
134
135
static const TypeInfo akitapda_type = {
136
.name = MACHINE_TYPE_NAME("akita"),
137
- .parent = TYPE_MACHINE,
138
+ .parent = TYPE_SPITZ_MACHINE,
139
.class_init = akitapda_class_init,
140
};
141
142
static void spitzpda_class_init(ObjectClass *oc, void *data)
143
{
144
MachineClass *mc = MACHINE_CLASS(oc);
145
+ SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
146
147
mc->desc = "Sharp SL-C3000 (Spitz) PDA (PXA270)";
148
- mc->init = spitz_init;
149
- mc->block_default_type = IF_IDE;
150
- mc->ignore_memory_transaction_failures = true;
151
mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
152
+ smc->model = spitz;
153
+ smc->arm_id = 0x2c9;
154
}
155
156
static const TypeInfo spitzpda_type = {
157
.name = MACHINE_TYPE_NAME("spitz"),
158
- .parent = TYPE_MACHINE,
159
+ .parent = TYPE_SPITZ_MACHINE,
160
.class_init = spitzpda_class_init,
161
};
162
163
static void borzoipda_class_init(ObjectClass *oc, void *data)
164
{
165
MachineClass *mc = MACHINE_CLASS(oc);
166
+ SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
167
168
mc->desc = "Sharp SL-C3100 (Borzoi) PDA (PXA270)";
169
- mc->init = borzoi_init;
170
- mc->block_default_type = IF_IDE;
171
- mc->ignore_memory_transaction_failures = true;
172
mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c0");
173
+ smc->model = borzoi;
174
+ smc->arm_id = 0x33f;
175
}
176
177
static const TypeInfo borzoipda_type = {
178
.name = MACHINE_TYPE_NAME("borzoi"),
179
- .parent = TYPE_MACHINE,
180
+ .parent = TYPE_SPITZ_MACHINE,
181
.class_init = borzoipda_class_init,
182
};
183
184
static void terrierpda_class_init(ObjectClass *oc, void *data)
185
{
186
MachineClass *mc = MACHINE_CLASS(oc);
187
+ SpitzMachineClass *smc = SPITZ_MACHINE_CLASS(oc);
188
189
mc->desc = "Sharp SL-C3200 (Terrier) PDA (PXA270)";
190
- mc->init = terrier_init;
191
- mc->block_default_type = IF_IDE;
192
- mc->ignore_memory_transaction_failures = true;
193
mc->default_cpu_type = ARM_CPU_TYPE_NAME("pxa270-c5");
194
+ smc->model = terrier;
195
+ smc->arm_id = 0x33f;
196
}
197
198
static const TypeInfo terrierpda_type = {
199
.name = MACHINE_TYPE_NAME("terrier"),
200
- .parent = TYPE_MACHINE,
201
+ .parent = TYPE_SPITZ_MACHINE,
202
.class_init = terrierpda_class_init,
203
};
204
205
static void spitz_machine_init(void)
206
{
207
+ type_register_static(&spitz_common_info);
208
type_register_static(&akitapda_type);
209
type_register_static(&spitzpda_type);
210
type_register_static(&borzoipda_type);
211
--
212
2.20.1
213
214
diff view generated by jsdifflib
New patch
1
Keep pointers to the MPU and the SSI devices in SpitzMachineState.
2
We're going to want to make GPIO connections between some of the
3
SSI devices and the SCPs, so we want to keep hold of a pointer to
4
those; putting the MPU into the struct allows us to pass just
5
one thing to spitz_ssp_attach() rather than two.
1
6
7
We have to retain the setting of the global "max1111" variable
8
for the moment as it is used in spitz_adc_temp_on(); later in
9
this series of commits we will be able to remove it.
10
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
13
Message-id: 20200628142429.17111-4-peter.maydell@linaro.org
14
---
15
hw/arm/spitz.c | 50 ++++++++++++++++++++++++++++----------------------
16
1 file changed, 28 insertions(+), 22 deletions(-)
17
18
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/arm/spitz.c
21
+++ b/hw/arm/spitz.c
22
@@ -XXX,XX +XXX,XX @@ typedef struct {
23
24
typedef struct {
25
MachineState parent;
26
+ PXA2xxState *mpu;
27
+ DeviceState *mux;
28
+ DeviceState *lcdtg;
29
+ DeviceState *ads7846;
30
+ DeviceState *max1111;
31
} SpitzMachineState;
32
33
#define TYPE_SPITZ_MACHINE "spitz-common"
34
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_realize(SSISlave *d, Error **errp)
35
s->bus[2] = ssi_create_bus(dev, "ssi2");
36
}
37
38
-static void spitz_ssp_attach(PXA2xxState *cpu)
39
+static void spitz_ssp_attach(SpitzMachineState *sms)
40
{
41
- DeviceState *mux;
42
- DeviceState *dev;
43
void *bus;
44
45
- mux = ssi_create_slave(cpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
46
+ sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
47
48
- bus = qdev_get_child_bus(mux, "ssi0");
49
- ssi_create_slave(bus, "spitz-lcdtg");
50
+ bus = qdev_get_child_bus(sms->mux, "ssi0");
51
+ sms->lcdtg = ssi_create_slave(bus, "spitz-lcdtg");
52
53
- bus = qdev_get_child_bus(mux, "ssi1");
54
- dev = ssi_create_slave(bus, "ads7846");
55
- qdev_connect_gpio_out(dev, 0,
56
- qdev_get_gpio_in(cpu->gpio, SPITZ_GPIO_TP_INT));
57
+ bus = qdev_get_child_bus(sms->mux, "ssi1");
58
+ sms->ads7846 = ssi_create_slave(bus, "ads7846");
59
+ qdev_connect_gpio_out(sms->ads7846, 0,
60
+ qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT));
61
62
- bus = qdev_get_child_bus(mux, "ssi2");
63
- max1111 = ssi_create_slave(bus, "max1111");
64
- max111x_set_input(max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
65
- max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
66
- max111x_set_input(max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
67
+ bus = qdev_get_child_bus(sms->mux, "ssi2");
68
+ sms->max1111 = ssi_create_slave(bus, "max1111");
69
+ max1111 = sms->max1111;
70
+ max111x_set_input(sms->max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
71
+ max111x_set_input(sms->max1111, MAX1111_BATT_TEMP, 0);
72
+ max111x_set_input(sms->max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
73
74
- qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_LCDCON_CS,
75
- qdev_get_gpio_in(mux, 0));
76
- qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_ADS7846_CS,
77
- qdev_get_gpio_in(mux, 1));
78
- qdev_connect_gpio_out(cpu->gpio, SPITZ_GPIO_MAX1111_CS,
79
- qdev_get_gpio_in(mux, 2));
80
+ qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_LCDCON_CS,
81
+ qdev_get_gpio_in(sms->mux, 0));
82
+ qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_ADS7846_CS,
83
+ qdev_get_gpio_in(sms->mux, 1));
84
+ qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_MAX1111_CS,
85
+ qdev_get_gpio_in(sms->mux, 2));
86
}
87
88
/* CF Microdrive */
89
@@ -XXX,XX +XXX,XX @@ static struct arm_boot_info spitz_binfo = {
90
static void spitz_common_init(MachineState *machine)
91
{
92
SpitzMachineClass *smc = SPITZ_MACHINE_GET_CLASS(machine);
93
+ SpitzMachineState *sms = SPITZ_MACHINE(machine);
94
enum spitz_model_e model = smc->model;
95
PXA2xxState *mpu;
96
DeviceState *scp0, *scp1 = NULL;
97
@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine)
98
/* Setup CPU & memory */
99
mpu = pxa270_init(address_space_mem, spitz_binfo.ram_size,
100
machine->cpu_type);
101
+ sms->mpu = mpu;
102
103
sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M);
104
105
@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine)
106
/* Setup peripherals */
107
spitz_keyboard_register(mpu);
108
109
- spitz_ssp_attach(mpu);
110
+ spitz_ssp_attach(sms);
111
112
scp0 = sysbus_create_simple("scoop", 0x10800000, NULL);
113
if (model != akita) {
114
--
115
2.20.1
116
117
diff view generated by jsdifflib
New patch
1
Keep pointers to scp0, scp1 in SpitzMachineState, and just pass
2
that to spitz_scoop_gpio_setup().
1
3
4
(We'll want to use some of the other fields in SpitzMachineState
5
in that function in the next commit.)
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
Message-id: 20200628142429.17111-5-peter.maydell@linaro.org
10
---
11
hw/arm/spitz.c | 34 +++++++++++++++++++---------------
12
1 file changed, 19 insertions(+), 15 deletions(-)
13
14
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/spitz.c
17
+++ b/hw/arm/spitz.c
18
@@ -XXX,XX +XXX,XX @@ typedef struct {
19
DeviceState *lcdtg;
20
DeviceState *ads7846;
21
DeviceState *max1111;
22
+ DeviceState *scp0;
23
+ DeviceState *scp1;
24
} SpitzMachineState;
25
26
#define TYPE_SPITZ_MACHINE "spitz-common"
27
@@ -XXX,XX +XXX,XX @@ static void spitz_out_switch(void *opaque, int line, int level)
28
#define SPITZ_SCP2_BACKLIGHT_ON 8
29
#define SPITZ_SCP2_MIC_BIAS 9
30
31
-static void spitz_scoop_gpio_setup(PXA2xxState *cpu,
32
- DeviceState *scp0, DeviceState *scp1)
33
+static void spitz_scoop_gpio_setup(SpitzMachineState *sms)
34
{
35
- qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, cpu, 8);
36
+ qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, sms->mpu, 8);
37
38
- qdev_connect_gpio_out(scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
39
- qdev_connect_gpio_out(scp0, SPITZ_SCP_JK_B, outsignals[1]);
40
- qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
41
- qdev_connect_gpio_out(scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
42
+ qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
43
+ qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_JK_B, outsignals[1]);
44
+ qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
45
+ qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
46
47
- if (scp1) {
48
- qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_CONT, outsignals[4]);
49
- qdev_connect_gpio_out(scp1, SPITZ_SCP2_BACKLIGHT_ON, outsignals[5]);
50
+ if (sms->scp1) {
51
+ qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_CONT,
52
+ outsignals[4]);
53
+ qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_ON,
54
+ outsignals[5]);
55
}
56
57
- qdev_connect_gpio_out(scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
58
+ qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
59
}
60
61
#define SPITZ_GPIO_HSYNC 22
62
@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine)
63
SpitzMachineState *sms = SPITZ_MACHINE(machine);
64
enum spitz_model_e model = smc->model;
65
PXA2xxState *mpu;
66
- DeviceState *scp0, *scp1 = NULL;
67
MemoryRegion *address_space_mem = get_system_memory();
68
MemoryRegion *rom = g_new(MemoryRegion, 1);
69
70
@@ -XXX,XX +XXX,XX @@ static void spitz_common_init(MachineState *machine)
71
72
spitz_ssp_attach(sms);
73
74
- scp0 = sysbus_create_simple("scoop", 0x10800000, NULL);
75
+ sms->scp0 = sysbus_create_simple("scoop", 0x10800000, NULL);
76
if (model != akita) {
77
- scp1 = sysbus_create_simple("scoop", 0x08800040, NULL);
78
+ sms->scp1 = sysbus_create_simple("scoop", 0x08800040, NULL);
79
+ } else {
80
+ sms->scp1 = NULL;
81
}
82
83
- spitz_scoop_gpio_setup(mpu, scp0, scp1);
84
+ spitz_scoop_gpio_setup(sms);
85
86
spitz_gpio_setup(mpu, (model == akita) ? 1 : 2);
87
88
--
89
2.20.1
90
91
diff view generated by jsdifflib
1
The ICC_CTLR_EL3 register includes some bits which are aliases
1
Currently the Spitz board uses a nasty hack for the GPIO lines
2
of bits in the ICC_CTLR_EL1(S) and (NS) registers. QEMU chooses
2
that pass "bit5" and "power" information to the LCD controller:
3
to keep those bits in the cs->icc_ctlr_el1[] struct fields.
3
the lcdtg realize function sets a global variable to point to
4
Unfortunately a missing '~' in the code to update the bits
4
the instance it just realized, and then the functions spitz_bl_power()
5
in those fields meant that writing to ICC_CTLR_EL3 would corrupt
5
and spitz_bl_bit5() use that to find the device they are changing
6
the ICC_CLTR_EL1 register values.
6
the internal state of. There is a comment reading:
7
FIXME: Implement GPIO properly and remove this hack.
8
which was added in 2009.
9
10
Implement GPIO properly and remove this hack.
7
11
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
10
Message-id: 20190520162809.2677-5-peter.maydell@linaro.org
14
Message-id: 20200628142429.17111-6-peter.maydell@linaro.org
11
---
15
---
12
hw/intc/arm_gicv3_cpuif.c | 4 ++--
16
hw/arm/spitz.c | 28 ++++++++++++----------------
13
1 file changed, 2 insertions(+), 2 deletions(-)
17
1 file changed, 12 insertions(+), 16 deletions(-)
14
18
15
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
19
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
16
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/intc/arm_gicv3_cpuif.c
21
--- a/hw/arm/spitz.c
18
+++ b/hw/intc/arm_gicv3_cpuif.c
22
+++ b/hw/arm/spitz.c
19
@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
23
@@ -XXX,XX +XXX,XX @@ static void spitz_bl_update(SpitzLCDTG *s)
20
trace_gicv3_icc_ctlr_el3_write(gicv3_redist_affid(cs), value);
24
zaurus_printf("LCD Backlight now off\n");
21
25
}
22
/* *_EL1NS and *_EL1S bits are aliases into the ICC_CTLR_EL1 bits. */
26
23
- cs->icc_ctlr_el1[GICV3_NS] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
27
-/* FIXME: Implement GPIO properly and remove this hack. */
24
+ cs->icc_ctlr_el1[GICV3_NS] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
28
-static SpitzLCDTG *spitz_lcdtg;
25
if (value & ICC_CTLR_EL3_EOIMODE_EL1NS) {
29
-
26
cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE;
30
static inline void spitz_bl_bit5(void *opaque, int line, int level)
31
{
32
- SpitzLCDTG *s = spitz_lcdtg;
33
+ SpitzLCDTG *s = opaque;
34
int prev = s->bl_intensity;
35
36
if (level)
37
@@ -XXX,XX +XXX,XX @@ static inline void spitz_bl_bit5(void *opaque, int line, int level)
38
39
static inline void spitz_bl_power(void *opaque, int line, int level)
40
{
41
- SpitzLCDTG *s = spitz_lcdtg;
42
+ SpitzLCDTG *s = opaque;
43
s->bl_power = !!level;
44
spitz_bl_update(s);
45
}
46
@@ -XXX,XX +XXX,XX @@ static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
47
return 0;
48
}
49
50
-static void spitz_lcdtg_realize(SSISlave *dev, Error **errp)
51
+static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp)
52
{
53
- SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
54
+ SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, ssi);
55
+ DeviceState *dev = DEVICE(s);
56
57
- spitz_lcdtg = s;
58
s->bl_power = 0;
59
s->bl_intensity = 0x20;
60
+
61
+ qdev_init_gpio_in_named(dev, spitz_bl_bit5, "bl_bit5", 1);
62
+ qdev_init_gpio_in_named(dev, spitz_bl_power, "bl_power", 1);
63
}
64
65
/* SSP devices */
66
@@ -XXX,XX +XXX,XX @@ static void spitz_out_switch(void *opaque, int line, int level)
67
case 3:
68
zaurus_printf("Orange LED %s.\n", level ? "on" : "off");
69
break;
70
- case 4:
71
- spitz_bl_bit5(opaque, line, level);
72
- break;
73
- case 5:
74
- spitz_bl_power(opaque, line, level);
75
- break;
76
case 6:
77
spitz_adc_temp_on(opaque, line, level);
78
break;
79
+ default:
80
+ g_assert_not_reached();
27
}
81
}
28
@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
82
}
29
cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_CBPR;
83
84
@@ -XXX,XX +XXX,XX @@ static void spitz_scoop_gpio_setup(SpitzMachineState *sms)
85
86
if (sms->scp1) {
87
qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_CONT,
88
- outsignals[4]);
89
+ qdev_get_gpio_in_named(sms->lcdtg, "bl_bit5", 0));
90
qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_ON,
91
- outsignals[5]);
92
+ qdev_get_gpio_in_named(sms->lcdtg, "bl_power", 0));
30
}
93
}
31
94
32
- cs->icc_ctlr_el1[GICV3_S] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
95
qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
33
+ cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
34
if (value & ICC_CTLR_EL3_EOIMODE_EL1S) {
35
cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_EOIMODE;
36
}
37
--
96
--
38
2.20.1
97
2.20.1
39
98
40
99
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Add some QOM properties to the max111x ADC device to allow the
2
initial values to be configured. Currently this is done by
3
board code calling max111x_set_input() after it creates the
4
device, which doesn't work on system reset.
2
5
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
This requires us to implement a reset method for this device,
7
so while we're doing that make sure we reset the other parts
8
of the device state.
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Message-id: 20190520214342.13709-5-philmd@redhat.com
13
Message-id: 20200628142429.17111-7-peter.maydell@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
14
---
8
include/hw/arm/exynos4210.h | 9 +++++++--
15
hw/misc/max111x.c | 57 ++++++++++++++++++++++++++++++++++++++---------
9
hw/arm/exynos4210.c | 28 ++++++++++++++++++++++++----
16
1 file changed, 47 insertions(+), 10 deletions(-)
10
hw/arm/exynos4_boards.c | 9 ++++++---
11
3 files changed, 37 insertions(+), 9 deletions(-)
12
17
13
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
18
diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c
14
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/arm/exynos4210.h
20
--- a/hw/misc/max111x.c
16
+++ b/include/hw/arm/exynos4210.h
21
+++ b/hw/misc/max111x.c
17
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210Irq {
22
@@ -XXX,XX +XXX,XX @@
18
} Exynos4210Irq;
23
#include "hw/ssi/ssi.h"
19
24
#include "migration/vmstate.h"
20
typedef struct Exynos4210State {
25
#include "qemu/module.h"
21
+ /*< private >*/
26
+#include "hw/qdev-properties.h"
22
+ SysBusDevice parent_obj;
27
23
+ /*< public >*/
28
typedef struct {
24
ARMCPU *cpu[EXYNOS4210_NCPUS];
29
SSISlave parent_obj;
25
Exynos4210Irq irqs;
30
26
qemu_irq *irq_table;
31
qemu_irq interrupt;
27
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210State {
32
+ /* Values of inputs at system reset (settable by QOM property) */
28
I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
33
+ uint8_t reset_input[8];
29
} Exynos4210State;
30
31
+#define TYPE_EXYNOS4210_SOC "exynos4210"
32
+#define EXYNOS4210_SOC(obj) \
33
+ OBJECT_CHECK(Exynos4210State, obj, TYPE_EXYNOS4210_SOC)
34
+
34
+
35
void exynos4210_write_secondary(ARMCPU *cpu,
35
uint8_t tb1, rb2, rb3;
36
const struct arm_boot_info *info);
36
int cycle;
37
37
38
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem);
38
@@ -XXX,XX +XXX,XX @@ static int max111x_init(SSISlave *d, int inputs)
39
-
39
qdev_init_gpio_out(dev, &s->interrupt, 1);
40
/* Initialize exynos4210 IRQ subsystem stub */
40
41
qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
41
s->inputs = inputs;
42
42
- /* TODO: add a user interface for setting these */
43
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
43
- s->input[0] = 0xf0;
44
index XXXXXXX..XXXXXXX 100644
44
- s->input[1] = 0xe0;
45
--- a/hw/arm/exynos4210.c
45
- s->input[2] = 0xd0;
46
+++ b/hw/arm/exynos4210.c
46
- s->input[3] = 0xc0;
47
@@ -XXX,XX +XXX,XX @@ static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
47
- s->input[4] = 0xb0;
48
sysbus_connect_irq(busdev, 0, irq);
48
- s->input[5] = 0xa0;
49
- s->input[6] = 0x90;
50
- s->input[7] = 0x80;
51
- s->com = 0;
52
53
vmstate_register(VMSTATE_IF(dev), VMSTATE_INSTANCE_ID_ANY,
54
&vmstate_max111x, s);
55
@@ -XXX,XX +XXX,XX @@ void max111x_set_input(DeviceState *dev, int line, uint8_t value)
56
s->input[line] = value;
49
}
57
}
50
58
51
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
59
+static void max111x_reset(DeviceState *dev)
52
+static void exynos4210_realize(DeviceState *socdev, Error **errp)
60
+{
53
{
61
+ MAX111xState *s = MAX_111X(dev);
54
- Exynos4210State *s = g_new0(Exynos4210State, 1);
62
+ int i;
55
+ Exynos4210State *s = EXYNOS4210_SOC(socdev);
56
+ MemoryRegion *system_mem = get_system_memory();
57
qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
58
SysBusDevice *busdev;
59
DeviceState *dev;
60
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
61
qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
62
pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
63
qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
64
-
65
- return s;
66
}
67
+
63
+
68
+static void exynos4210_class_init(ObjectClass *klass, void *data)
64
+ for (i = 0; i < s->inputs; i++) {
69
+{
65
+ s->input[i] = s->reset_input[i];
70
+ DeviceClass *dc = DEVICE_CLASS(klass);
66
+ }
71
+
67
+ s->com = 0;
72
+ dc->realize = exynos4210_realize;
68
+ s->tb1 = 0;
69
+ s->rb2 = 0;
70
+ s->rb3 = 0;
71
+ s->cycle = 0;
73
+}
72
+}
74
+
73
+
75
+static const TypeInfo exynos4210_info = {
74
+static Property max1110_properties[] = {
76
+ .name = TYPE_EXYNOS4210_SOC,
75
+ /* Reset values for ADC inputs */
77
+ .parent = TYPE_SYS_BUS_DEVICE,
76
+ DEFINE_PROP_UINT8("input0", MAX111xState, reset_input[0], 0xf0),
78
+ .instance_size = sizeof(Exynos4210State),
77
+ DEFINE_PROP_UINT8("input1", MAX111xState, reset_input[1], 0xe0),
79
+ .class_init = exynos4210_class_init,
78
+ DEFINE_PROP_UINT8("input2", MAX111xState, reset_input[2], 0xd0),
79
+ DEFINE_PROP_UINT8("input3", MAX111xState, reset_input[3], 0xc0),
80
+ DEFINE_PROP_END_OF_LIST(),
80
+};
81
+};
81
+
82
+
82
+static void exynos4210_register_types(void)
83
+static Property max1111_properties[] = {
83
+{
84
+ /* Reset values for ADC inputs */
84
+ type_register_static(&exynos4210_info);
85
+ DEFINE_PROP_UINT8("input0", MAX111xState, reset_input[0], 0xf0),
85
+}
86
+ DEFINE_PROP_UINT8("input1", MAX111xState, reset_input[1], 0xe0),
87
+ DEFINE_PROP_UINT8("input2", MAX111xState, reset_input[2], 0xd0),
88
+ DEFINE_PROP_UINT8("input3", MAX111xState, reset_input[3], 0xc0),
89
+ DEFINE_PROP_UINT8("input4", MAX111xState, reset_input[4], 0xb0),
90
+ DEFINE_PROP_UINT8("input5", MAX111xState, reset_input[5], 0xa0),
91
+ DEFINE_PROP_UINT8("input6", MAX111xState, reset_input[6], 0x90),
92
+ DEFINE_PROP_UINT8("input7", MAX111xState, reset_input[7], 0x80),
93
+ DEFINE_PROP_END_OF_LIST(),
94
+};
86
+
95
+
87
+type_init(exynos4210_register_types)
96
static void max111x_class_init(ObjectClass *klass, void *data)
88
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
97
{
89
index XXXXXXX..XXXXXXX 100644
98
SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
90
--- a/hw/arm/exynos4_boards.c
99
+ DeviceClass *dc = DEVICE_CLASS(klass);
91
+++ b/hw/arm/exynos4_boards.c
100
92
@@ -XXX,XX +XXX,XX @@ typedef enum Exynos4BoardType {
101
k->transfer = max111x_transfer;
93
} Exynos4BoardType;
102
+ dc->reset = max111x_reset;
94
95
typedef struct Exynos4BoardState {
96
- Exynos4210State *soc;
97
+ Exynos4210State soc;
98
MemoryRegion dram0_mem;
99
MemoryRegion dram1_mem;
100
} Exynos4BoardState;
101
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
102
exynos4_boards_init_ram(s, get_system_memory(),
103
exynos4_board_ram_size[board_type]);
104
105
- s->soc = exynos4210_init(get_system_memory());
106
+ object_initialize(&s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC);
107
+ qdev_set_parent_bus(DEVICE(&s->soc), sysbus_get_default());
108
+ object_property_set_bool(OBJECT(&s->soc), true, "realized",
109
+ &error_fatal);
110
111
return s;
112
}
103
}
113
@@ -XXX,XX +XXX,XX @@ static void smdkc210_init(MachineState *machine)
104
114
EXYNOS4_BOARD_SMDKC210);
105
static const TypeInfo max111x_info = {
115
106
@@ -XXX,XX +XXX,XX @@ static const TypeInfo max111x_info = {
116
lan9215_init(SMDK_LAN9118_BASE_ADDR,
107
static void max1110_class_init(ObjectClass *klass, void *data)
117
- qemu_irq_invert(s->soc->irq_table[exynos4210_get_irq(37, 1)]));
108
{
118
+ qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)]));
109
SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
119
arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo);
110
+ DeviceClass *dc = DEVICE_CLASS(klass);
111
112
k->realize = max1110_realize;
113
+ device_class_set_props(dc, max1110_properties);
120
}
114
}
121
115
116
static const TypeInfo max1110_info = {
117
@@ -XXX,XX +XXX,XX @@ static const TypeInfo max1110_info = {
118
static void max1111_class_init(ObjectClass *klass, void *data)
119
{
120
SSISlaveClass *k = SSI_SLAVE_CLASS(klass);
121
+ DeviceClass *dc = DEVICE_CLASS(klass);
122
123
k->realize = max1111_realize;
124
+ device_class_set_props(dc, max1111_properties);
125
}
126
127
static const TypeInfo max1111_info = {
122
--
128
--
123
2.20.1
129
2.20.1
124
130
125
131
diff view generated by jsdifflib
New patch
1
The max111x is a proper qdev device; we can use dc->vmsd rather than
2
directly calling vmstate_register().
1
3
4
It's possible that this is a migration compat break, but the only
5
boards that use this device are the spitz-family ('akita', 'borzoi',
6
'spitz', 'terrier').
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-id: 20200628142429.17111-8-peter.maydell@linaro.org
12
---
13
hw/misc/max111x.c | 3 +--
14
1 file changed, 1 insertion(+), 2 deletions(-)
15
16
diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/misc/max111x.c
19
+++ b/hw/misc/max111x.c
20
@@ -XXX,XX +XXX,XX @@ static int max111x_init(SSISlave *d, int inputs)
21
22
s->inputs = inputs;
23
24
- vmstate_register(VMSTATE_IF(dev), VMSTATE_INSTANCE_ID_ANY,
25
- &vmstate_max111x, s);
26
return 0;
27
}
28
29
@@ -XXX,XX +XXX,XX @@ static void max111x_class_init(ObjectClass *klass, void *data)
30
31
k->transfer = max111x_transfer;
32
dc->reset = max111x_reset;
33
+ dc->vmsd = &vmstate_max111x;
34
}
35
36
static const TypeInfo max111x_info = {
37
--
38
2.20.1
39
40
diff view generated by jsdifflib
New patch
1
Add an ssi_realize_and_unref(), for the benefit of callers
2
who want to be able to create an SSI device, set QOM properties
3
on it, and then do the realize-and-unref afterwards.
1
4
5
The API works on the same principle as the recently added
6
qdev_realize_and_undef(), sysbus_realize_and_undef(), etc.
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-id: 20200628142429.17111-9-peter.maydell@linaro.org
12
---
13
include/hw/ssi/ssi.h | 26 ++++++++++++++++++++++++++
14
hw/ssi/ssi.c | 7 ++++++-
15
2 files changed, 32 insertions(+), 1 deletion(-)
16
17
diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/ssi/ssi.h
20
+++ b/include/hw/ssi/ssi.h
21
@@ -XXX,XX +XXX,XX @@ extern const VMStateDescription vmstate_ssi_slave;
22
}
23
24
DeviceState *ssi_create_slave(SSIBus *bus, const char *name);
25
+/**
26
+ * ssi_realize_and_unref: realize and unref an SSI slave device
27
+ * @dev: SSI slave device to realize
28
+ * @bus: SSI bus to put it on
29
+ * @errp: error pointer
30
+ *
31
+ * Call 'realize' on @dev, put it on the specified @bus, and drop the
32
+ * reference to it. Errors are reported via @errp and by returning
33
+ * false.
34
+ *
35
+ * This function is useful if you have created @dev via qdev_new()
36
+ * (which takes a reference to the device it returns to you), so that
37
+ * you can set properties on it before realizing it. If you don't need
38
+ * to set properties then ssi_create_slave() is probably better (as it
39
+ * does the create, init and realize in one step).
40
+ *
41
+ * If you are embedding the SSI slave into another QOM device and
42
+ * initialized it via some variant on object_initialize_child() then
43
+ * do not use this function, because that family of functions arrange
44
+ * for the only reference to the child device to be held by the parent
45
+ * via the child<> property, and so the reference-count-drop done here
46
+ * would be incorrect. (Instead you would want ssi_realize(), which
47
+ * doesn't currently exist but would be trivial to create if we had
48
+ * any code that wanted it.)
49
+ */
50
+bool ssi_realize_and_unref(DeviceState *dev, SSIBus *bus, Error **errp);
51
52
/* Master interface. */
53
SSIBus *ssi_create_bus(DeviceState *parent, const char *name);
54
diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/hw/ssi/ssi.c
57
+++ b/hw/ssi/ssi.c
58
@@ -XXX,XX +XXX,XX @@ static const TypeInfo ssi_slave_info = {
59
.abstract = true,
60
};
61
62
+bool ssi_realize_and_unref(DeviceState *dev, SSIBus *bus, Error **errp)
63
+{
64
+ return qdev_realize_and_unref(dev, &bus->parent_obj, errp);
65
+}
66
+
67
DeviceState *ssi_create_slave(SSIBus *bus, const char *name)
68
{
69
DeviceState *dev = qdev_new(name);
70
71
- qdev_realize_and_unref(dev, &bus->parent_obj, &error_fatal);
72
+ ssi_realize_and_unref(dev, bus, &error_fatal);
73
return dev;
74
}
75
76
--
77
2.20.1
78
79
diff view generated by jsdifflib
New patch
1
Use the new max111x qdev properties to set the initial input
2
values rather than calling max111x_set_input(); this means that
3
on system reset the inputs will correctly return to their initial
4
values.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Message-id: 20200628142429.17111-10-peter.maydell@linaro.org
9
---
10
hw/arm/spitz.c | 11 +++++++----
11
1 file changed, 7 insertions(+), 4 deletions(-)
12
13
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/spitz.c
16
+++ b/hw/arm/spitz.c
17
@@ -XXX,XX +XXX,XX @@ static void spitz_ssp_attach(SpitzMachineState *sms)
18
qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT));
19
20
bus = qdev_get_child_bus(sms->mux, "ssi2");
21
- sms->max1111 = ssi_create_slave(bus, "max1111");
22
+ sms->max1111 = qdev_new("max1111");
23
max1111 = sms->max1111;
24
- max111x_set_input(sms->max1111, MAX1111_BATT_VOLT, SPITZ_BATTERY_VOLT);
25
- max111x_set_input(sms->max1111, MAX1111_BATT_TEMP, 0);
26
- max111x_set_input(sms->max1111, MAX1111_ACIN_VOLT, SPITZ_CHARGEON_ACIN);
27
+ qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */,
28
+ SPITZ_BATTERY_VOLT);
29
+ qdev_prop_set_uint8(sms->max1111, "input2" /* BATT_TEMP */, 0);
30
+ qdev_prop_set_uint8(sms->max1111, "input3" /* ACIN_VOLT */,
31
+ SPITZ_CHARGEON_ACIN);
32
+ ssi_realize_and_unref(sms->max1111, bus, &error_fatal);
33
34
qdev_connect_gpio_out(sms->mpu->gpio, SPITZ_GPIO_LCDCON_CS,
35
qdev_get_gpio_in(sms->mux, 0));
36
--
37
2.20.1
38
39
diff view generated by jsdifflib
New patch
1
The max111x ADC device model allows other code to set the level on
2
the 8 ADC inputs using the max111x_set_input() function. Replace
3
this with generic qdev GPIO inputs, which also allow inputs to be set
4
to arbitrary values.
1
5
6
Using GPIO lines will make it easier for board code to wire things
7
up, so that if device A wants to set the ADC input it doesn't need to
8
have a direct pointer to the max111x but can just set that value on
9
its output GPIO, which is then wired up by the board to the
10
appropriate max111x input.
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Message-id: 20200628142429.17111-11-peter.maydell@linaro.org
15
---
16
include/hw/ssi/ssi.h | 3 ---
17
hw/arm/spitz.c | 9 +++++----
18
hw/misc/max111x.c | 16 +++++++++-------
19
3 files changed, 14 insertions(+), 14 deletions(-)
20
21
diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/ssi/ssi.h
24
+++ b/include/hw/ssi/ssi.h
25
@@ -XXX,XX +XXX,XX @@ SSIBus *ssi_create_bus(DeviceState *parent, const char *name);
26
27
uint32_t ssi_transfer(SSIBus *bus, uint32_t val);
28
29
-/* max111x.c */
30
-void max111x_set_input(DeviceState *dev, int line, uint8_t value);
31
-
32
#endif
33
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/hw/arm/spitz.c
36
+++ b/hw/arm/spitz.c
37
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
38
39
static void spitz_adc_temp_on(void *opaque, int line, int level)
40
{
41
+ int batt_temp;
42
+
43
if (!max1111)
44
return;
45
46
- if (level)
47
- max111x_set_input(max1111, MAX1111_BATT_TEMP, SPITZ_BATTERY_TEMP);
48
- else
49
- max111x_set_input(max1111, MAX1111_BATT_TEMP, 0);
50
+ batt_temp = level ? SPITZ_BATTERY_TEMP : 0;
51
+
52
+ qemu_set_irq(qdev_get_gpio_in(max1111, MAX1111_BATT_TEMP), batt_temp);
53
}
54
55
static void corgi_ssp_realize(SSISlave *d, Error **errp)
56
diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/hw/misc/max111x.c
59
+++ b/hw/misc/max111x.c
60
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_max111x = {
61
}
62
};
63
64
+static void max111x_input_set(void *opaque, int line, int value)
65
+{
66
+ MAX111xState *s = MAX_111X(opaque);
67
+
68
+ assert(line >= 0 && line < s->inputs);
69
+ s->input[line] = value;
70
+}
71
+
72
static int max111x_init(SSISlave *d, int inputs)
73
{
74
DeviceState *dev = DEVICE(d);
75
MAX111xState *s = MAX_111X(dev);
76
77
qdev_init_gpio_out(dev, &s->interrupt, 1);
78
+ qdev_init_gpio_in(dev, max111x_input_set, inputs);
79
80
s->inputs = inputs;
81
82
@@ -XXX,XX +XXX,XX @@ static void max1111_realize(SSISlave *dev, Error **errp)
83
max111x_init(dev, 4);
84
}
85
86
-void max111x_set_input(DeviceState *dev, int line, uint8_t value)
87
-{
88
- MAX111xState *s = MAX_111X(dev);
89
- assert(line >= 0 && line < s->inputs);
90
- s->input[line] = value;
91
-}
92
-
93
static void max111x_reset(DeviceState *dev)
94
{
95
MAX111xState *s = MAX_111X(dev);
96
--
97
2.20.1
98
99
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
Create a header file for the hw/misc/max111x device, in the
2
usual modern style for QOM devices:
3
* definition of the TYPE_ constants and macros
4
* definition of the device's state struct so that it can
5
be embedded in other structs if desired
6
* documentation of the interface
2
7
3
It eases code review, unit is explicit.
8
This allows us to use TYPE_MAX_1111 in the spitz.c code rather
9
than the string "max1111".
4
10
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Message-id: 20190520214342.13709-3-philmd@redhat.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
13
Message-id: 20200628142429.17111-12-peter.maydell@linaro.org
9
---
14
---
10
hw/arm/exynos4_boards.c | 5 +++--
15
include/hw/misc/max111x.h | 56 +++++++++++++++++++++++++++++++++++++++
11
1 file changed, 3 insertions(+), 2 deletions(-)
16
hw/arm/spitz.c | 3 ++-
17
hw/misc/max111x.c | 24 +----------------
18
MAINTAINERS | 1 +
19
4 files changed, 60 insertions(+), 24 deletions(-)
20
create mode 100644 include/hw/misc/max111x.h
12
21
13
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
22
diff --git a/include/hw/misc/max111x.h b/include/hw/misc/max111x.h
23
new file mode 100644
24
index XXXXXXX..XXXXXXX
25
--- /dev/null
26
+++ b/include/hw/misc/max111x.h
27
@@ -XXX,XX +XXX,XX @@
28
+/*
29
+ * Maxim MAX1110/1111 ADC chip emulation.
30
+ *
31
+ * Copyright (c) 2006 Openedhand Ltd.
32
+ * Written by Andrzej Zaborowski <balrog@zabor.org>
33
+ *
34
+ * This code is licensed under the GNU GPLv2.
35
+ *
36
+ * Contributions after 2012-01-13 are licensed under the terms of the
37
+ * GNU GPL, version 2 or (at your option) any later version.
38
+ */
39
+
40
+#ifndef HW_MISC_MAX111X_H
41
+#define HW_MISC_MAX111X_H
42
+
43
+#include "hw/ssi/ssi.h"
44
+
45
+/*
46
+ * This is a model of the Maxim MAX1110/1111 ADC chip, which for QEMU
47
+ * is an SSI slave device. It has either 4 (max1110) or 8 (max1111)
48
+ * 8-bit ADC channels.
49
+ *
50
+ * QEMU interface:
51
+ * + GPIO inputs 0..3 (for max1110) or 0..7 (for max1111): set the value
52
+ * of each ADC input, as an unsigned 8-bit value
53
+ * + GPIO output 0: interrupt line
54
+ * + Properties "input0" to "input3" (max1110) or "input0" to "input7"
55
+ * (max1111): initial reset values for ADC inputs.
56
+ *
57
+ * Known bugs:
58
+ * + the interrupt line is not correctly implemented, and will never
59
+ * be lowered once it has been asserted.
60
+ */
61
+typedef struct {
62
+ SSISlave parent_obj;
63
+
64
+ qemu_irq interrupt;
65
+ /* Values of inputs at system reset (settable by QOM property) */
66
+ uint8_t reset_input[8];
67
+
68
+ uint8_t tb1, rb2, rb3;
69
+ int cycle;
70
+
71
+ uint8_t input[8];
72
+ int inputs, com;
73
+} MAX111xState;
74
+
75
+#define TYPE_MAX_111X "max111x"
76
+
77
+#define MAX_111X(obj) \
78
+ OBJECT_CHECK(MAX111xState, (obj), TYPE_MAX_111X)
79
+
80
+#define TYPE_MAX_1110 "max1110"
81
+#define TYPE_MAX_1111 "max1111"
82
+
83
+#endif
84
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
14
index XXXXXXX..XXXXXXX 100644
85
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/exynos4_boards.c
86
--- a/hw/arm/spitz.c
16
+++ b/hw/arm/exynos4_boards.c
87
+++ b/hw/arm/spitz.c
88
@@ -XXX,XX +XXX,XX @@
89
#include "audio/audio.h"
90
#include "hw/boards.h"
91
#include "hw/sysbus.h"
92
+#include "hw/misc/max111x.h"
93
#include "migration/vmstate.h"
94
#include "exec/address-spaces.h"
95
#include "cpu.h"
96
@@ -XXX,XX +XXX,XX @@ static void spitz_ssp_attach(SpitzMachineState *sms)
97
qdev_get_gpio_in(sms->mpu->gpio, SPITZ_GPIO_TP_INT));
98
99
bus = qdev_get_child_bus(sms->mux, "ssi2");
100
- sms->max1111 = qdev_new("max1111");
101
+ sms->max1111 = qdev_new(TYPE_MAX_1111);
102
max1111 = sms->max1111;
103
qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */,
104
SPITZ_BATTERY_VOLT);
105
diff --git a/hw/misc/max111x.c b/hw/misc/max111x.c
106
index XXXXXXX..XXXXXXX 100644
107
--- a/hw/misc/max111x.c
108
+++ b/hw/misc/max111x.c
17
@@ -XXX,XX +XXX,XX @@
109
@@ -XXX,XX +XXX,XX @@
18
*/
110
*/
19
111
20
#include "qemu/osdep.h"
112
#include "qemu/osdep.h"
21
+#include "qemu/units.h"
113
+#include "hw/misc/max111x.h"
22
#include "qapi/error.h"
114
#include "hw/irq.h"
23
#include "qemu/error-report.h"
115
-#include "hw/ssi/ssi.h"
24
#include "qemu-common.h"
116
#include "migration/vmstate.h"
25
@@ -XXX,XX +XXX,XX @@ static int exynos4_board_smp_bootreg_addr[EXYNOS4_NUM_OF_BOARDS] = {
117
#include "qemu/module.h"
26
};
118
#include "hw/qdev-properties.h"
27
119
28
static unsigned long exynos4_board_ram_size[EXYNOS4_NUM_OF_BOARDS] = {
120
-typedef struct {
29
- [EXYNOS4_BOARD_NURI] = 0x40000000,
121
- SSISlave parent_obj;
30
- [EXYNOS4_BOARD_SMDKC210] = 0x40000000,
122
-
31
+ [EXYNOS4_BOARD_NURI] = 1 * GiB,
123
- qemu_irq interrupt;
32
+ [EXYNOS4_BOARD_SMDKC210] = 1 * GiB,
124
- /* Values of inputs at system reset (settable by QOM property) */
33
};
125
- uint8_t reset_input[8];
34
126
-
35
static struct arm_boot_info exynos4_board_binfo = {
127
- uint8_t tb1, rb2, rb3;
128
- int cycle;
129
-
130
- uint8_t input[8];
131
- int inputs, com;
132
-} MAX111xState;
133
-
134
-#define TYPE_MAX_111X "max111x"
135
-
136
-#define MAX_111X(obj) \
137
- OBJECT_CHECK(MAX111xState, (obj), TYPE_MAX_111X)
138
-
139
-#define TYPE_MAX_1110 "max1110"
140
-#define TYPE_MAX_1111 "max1111"
141
-
142
/* Control-byte bitfields */
143
#define CB_PD0        (1 << 0)
144
#define CB_PD1        (1 << 1)
145
diff --git a/MAINTAINERS b/MAINTAINERS
146
index XXXXXXX..XXXXXXX 100644
147
--- a/MAINTAINERS
148
+++ b/MAINTAINERS
149
@@ -XXX,XX +XXX,XX @@ F: hw/gpio/max7310.c
150
F: hw/gpio/zaurus.c
151
F: hw/misc/mst_fpga.c
152
F: hw/misc/max111x.c
153
+F: include/hw/misc/max111x.h
154
F: include/hw/arm/pxa.h
155
F: include/hw/arm/sharpsl.h
156
F: include/hw/display/tc6393xb.h
36
--
157
--
37
2.20.1
158
2.20.1
38
159
39
160
diff view generated by jsdifflib
New patch
1
1
Currently we have a free-floating set of IRQs and a function
2
spitz_out_switch() which handle some miscellaneous GPIO lines for the
3
spitz board. Encapsulate this behaviour in a simple QOM device.
4
5
At this point we can finally remove the 'max1111' global, because the
6
ADC battery-temperature value is now handled by the misc-gpio device
7
writing the value to its outbound "adc-temp" GPIO, which the board
8
code wires up to the appropriate inbound GPIO line on the max1111.
9
10
This commit also fixes Coverity issue CID 1421913 (which pointed out
11
that the 'outsignals' in spitz_scoop_gpio_setup() were leaked),
12
because it removes the use of the qemu_allocate_irqs() API from this
13
code entirely.
14
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
18
Message-id: 20200628142429.17111-13-peter.maydell@linaro.org
19
---
20
hw/arm/spitz.c | 129 +++++++++++++++++++++++++++++++++----------------
21
1 file changed, 87 insertions(+), 42 deletions(-)
22
23
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/arm/spitz.c
26
+++ b/hw/arm/spitz.c
27
@@ -XXX,XX +XXX,XX @@ typedef struct {
28
DeviceState *max1111;
29
DeviceState *scp0;
30
DeviceState *scp1;
31
+ DeviceState *misc_gpio;
32
} SpitzMachineState;
33
34
#define TYPE_SPITZ_MACHINE "spitz-common"
35
@@ -XXX,XX +XXX,XX @@ static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp)
36
#define SPITZ_GPIO_MAX1111_CS 20
37
#define SPITZ_GPIO_TP_INT 11
38
39
-static DeviceState *max1111;
40
-
41
/* "Demux" the signal based on current chipselect */
42
typedef struct {
43
SSISlave ssidev;
44
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
45
#define SPITZ_BATTERY_VOLT 0xd0 /* About 4.0V */
46
#define SPITZ_CHARGEON_ACIN 0x80 /* About 5.0V */
47
48
-static void spitz_adc_temp_on(void *opaque, int line, int level)
49
-{
50
- int batt_temp;
51
-
52
- if (!max1111)
53
- return;
54
-
55
- batt_temp = level ? SPITZ_BATTERY_TEMP : 0;
56
-
57
- qemu_set_irq(qdev_get_gpio_in(max1111, MAX1111_BATT_TEMP), batt_temp);
58
-}
59
-
60
static void corgi_ssp_realize(SSISlave *d, Error **errp)
61
{
62
DeviceState *dev = DEVICE(d);
63
@@ -XXX,XX +XXX,XX @@ static void spitz_ssp_attach(SpitzMachineState *sms)
64
65
bus = qdev_get_child_bus(sms->mux, "ssi2");
66
sms->max1111 = qdev_new(TYPE_MAX_1111);
67
- max1111 = sms->max1111;
68
qdev_prop_set_uint8(sms->max1111, "input1" /* BATT_VOLT */,
69
SPITZ_BATTERY_VOLT);
70
qdev_prop_set_uint8(sms->max1111, "input2" /* BATT_TEMP */, 0);
71
@@ -XXX,XX +XXX,XX @@ static void spitz_akita_i2c_setup(PXA2xxState *cpu)
72
73
/* Other peripherals */
74
75
-static void spitz_out_switch(void *opaque, int line, int level)
76
+/*
77
+ * Encapsulation of some miscellaneous GPIO line behaviour for the Spitz boards.
78
+ *
79
+ * QEMU interface:
80
+ * + named GPIO inputs "green-led", "orange-led", "charging", "discharging":
81
+ * these currently just print messages that the line has been signalled
82
+ * + named GPIO input "adc-temp-on": set to cause the battery-temperature
83
+ * value to be passed to the max111x ADC
84
+ * + named GPIO output "adc-temp": the ADC value, to be wired up to the max111x
85
+ */
86
+#define TYPE_SPITZ_MISC_GPIO "spitz-misc-gpio"
87
+#define SPITZ_MISC_GPIO(obj) \
88
+ OBJECT_CHECK(SpitzMiscGPIOState, (obj), TYPE_SPITZ_MISC_GPIO)
89
+
90
+typedef struct SpitzMiscGPIOState {
91
+ SysBusDevice parent_obj;
92
+
93
+ qemu_irq adc_value;
94
+} SpitzMiscGPIOState;
95
+
96
+static void spitz_misc_charging(void *opaque, int n, int level)
97
{
98
- switch (line) {
99
- case 0:
100
- zaurus_printf("Charging %s.\n", level ? "off" : "on");
101
- break;
102
- case 1:
103
- zaurus_printf("Discharging %s.\n", level ? "on" : "off");
104
- break;
105
- case 2:
106
- zaurus_printf("Green LED %s.\n", level ? "on" : "off");
107
- break;
108
- case 3:
109
- zaurus_printf("Orange LED %s.\n", level ? "on" : "off");
110
- break;
111
- case 6:
112
- spitz_adc_temp_on(opaque, line, level);
113
- break;
114
- default:
115
- g_assert_not_reached();
116
- }
117
+ zaurus_printf("Charging %s.\n", level ? "off" : "on");
118
+}
119
+
120
+static void spitz_misc_discharging(void *opaque, int n, int level)
121
+{
122
+ zaurus_printf("Discharging %s.\n", level ? "off" : "on");
123
+}
124
+
125
+static void spitz_misc_green_led(void *opaque, int n, int level)
126
+{
127
+ zaurus_printf("Green LED %s.\n", level ? "off" : "on");
128
+}
129
+
130
+static void spitz_misc_orange_led(void *opaque, int n, int level)
131
+{
132
+ zaurus_printf("Orange LED %s.\n", level ? "off" : "on");
133
+}
134
+
135
+static void spitz_misc_adc_temp(void *opaque, int n, int level)
136
+{
137
+ SpitzMiscGPIOState *s = SPITZ_MISC_GPIO(opaque);
138
+ int batt_temp = level ? SPITZ_BATTERY_TEMP : 0;
139
+
140
+ qemu_set_irq(s->adc_value, batt_temp);
141
+}
142
+
143
+static void spitz_misc_gpio_init(Object *obj)
144
+{
145
+ SpitzMiscGPIOState *s = SPITZ_MISC_GPIO(obj);
146
+ DeviceState *dev = DEVICE(obj);
147
+
148
+ qdev_init_gpio_in_named(dev, spitz_misc_charging, "charging", 1);
149
+ qdev_init_gpio_in_named(dev, spitz_misc_discharging, "discharging", 1);
150
+ qdev_init_gpio_in_named(dev, spitz_misc_green_led, "green-led", 1);
151
+ qdev_init_gpio_in_named(dev, spitz_misc_orange_led, "orange-led", 1);
152
+ qdev_init_gpio_in_named(dev, spitz_misc_adc_temp, "adc-temp-on", 1);
153
+
154
+ qdev_init_gpio_out_named(dev, &s->adc_value, "adc-temp", 1);
155
}
156
157
#define SPITZ_SCP_LED_GREEN 1
158
@@ -XXX,XX +XXX,XX @@ static void spitz_out_switch(void *opaque, int line, int level)
159
160
static void spitz_scoop_gpio_setup(SpitzMachineState *sms)
161
{
162
- qemu_irq *outsignals = qemu_allocate_irqs(spitz_out_switch, sms->mpu, 8);
163
+ DeviceState *miscdev = sysbus_create_simple(TYPE_SPITZ_MISC_GPIO, -1, NULL);
164
165
- qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_CHRG_ON, outsignals[0]);
166
- qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_JK_B, outsignals[1]);
167
- qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_GREEN, outsignals[2]);
168
- qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_ORANGE, outsignals[3]);
169
+ sms->misc_gpio = miscdev;
170
+
171
+ qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_CHRG_ON,
172
+ qdev_get_gpio_in_named(miscdev, "charging", 0));
173
+ qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_JK_B,
174
+ qdev_get_gpio_in_named(miscdev, "discharging", 0));
175
+ qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_GREEN,
176
+ qdev_get_gpio_in_named(miscdev, "green-led", 0));
177
+ qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_LED_ORANGE,
178
+ qdev_get_gpio_in_named(miscdev, "orange-led", 0));
179
+ qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON,
180
+ qdev_get_gpio_in_named(miscdev, "adc-temp-on", 0));
181
+ qdev_connect_gpio_out_named(miscdev, "adc-temp", 0,
182
+ qdev_get_gpio_in(sms->max1111, MAX1111_BATT_TEMP));
183
184
if (sms->scp1) {
185
qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_CONT,
186
@@ -XXX,XX +XXX,XX @@ static void spitz_scoop_gpio_setup(SpitzMachineState *sms)
187
qdev_connect_gpio_out(sms->scp1, SPITZ_SCP2_BACKLIGHT_ON,
188
qdev_get_gpio_in_named(sms->lcdtg, "bl_power", 0));
189
}
190
-
191
- qdev_connect_gpio_out(sms->scp0, SPITZ_SCP_ADC_TEMP_ON, outsignals[6]);
192
}
193
194
#define SPITZ_GPIO_HSYNC 22
195
@@ -XXX,XX +XXX,XX @@ static const TypeInfo spitz_lcdtg_info = {
196
.class_init = spitz_lcdtg_class_init,
197
};
198
199
+static const TypeInfo spitz_misc_gpio_info = {
200
+ .name = TYPE_SPITZ_MISC_GPIO,
201
+ .parent = TYPE_SYS_BUS_DEVICE,
202
+ .instance_size = sizeof(SpitzMiscGPIOState),
203
+ .instance_init = spitz_misc_gpio_init,
204
+ /*
205
+ * No class_init required: device has no internal state so does not
206
+ * need to set up reset or vmstate, and does not have a realize method.
207
+ */
208
+};
209
+
210
static void spitz_register_types(void)
211
{
212
type_register_static(&corgi_ssp_info);
213
type_register_static(&spitz_lcdtg_info);
214
type_register_static(&spitz_keyboard_info);
215
type_register_static(&sl_nand_info);
216
+ type_register_static(&spitz_misc_gpio_info);
217
}
218
219
type_init(spitz_register_types)
220
--
221
2.20.1
222
223
diff view generated by jsdifflib
New patch
1
Instead of logging guest accesses to invalid register offsets in this
2
device using zaurus_printf() (which just prints to stderr), use the
3
usual qemu_log_mask(LOG_GUEST_ERROR,...).
1
4
5
Since this was the only use of the zaurus_printf() macro outside
6
spitz.c, we can move the definition of that macro from sharpsl.h
7
to spitz.c.
8
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
12
Message-id: 20200628142429.17111-14-peter.maydell@linaro.org
13
---
14
include/hw/arm/sharpsl.h | 3 ---
15
hw/arm/spitz.c | 3 +++
16
hw/gpio/zaurus.c | 12 +++++++-----
17
3 files changed, 10 insertions(+), 8 deletions(-)
18
19
diff --git a/include/hw/arm/sharpsl.h b/include/hw/arm/sharpsl.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/arm/sharpsl.h
22
+++ b/include/hw/arm/sharpsl.h
23
@@ -XXX,XX +XXX,XX @@
24
25
#include "exec/hwaddr.h"
26
27
-#define zaurus_printf(format, ...)    \
28
- fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__)
29
-
30
/* zaurus.c */
31
32
#define SL_PXA_PARAM_BASE    0xa0000a00
33
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/hw/arm/spitz.c
36
+++ b/hw/arm/spitz.c
37
@@ -XXX,XX +XXX,XX @@ typedef struct {
38
#define SPITZ_MACHINE_CLASS(klass) \
39
OBJECT_CLASS_CHECK(SpitzMachineClass, klass, TYPE_SPITZ_MACHINE)
40
41
+#define zaurus_printf(format, ...) \
42
+ fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__)
43
+
44
#undef REG_FMT
45
#define REG_FMT "0x%02lx"
46
47
diff --git a/hw/gpio/zaurus.c b/hw/gpio/zaurus.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/hw/gpio/zaurus.c
50
+++ b/hw/gpio/zaurus.c
51
@@ -XXX,XX +XXX,XX @@
52
#include "hw/sysbus.h"
53
#include "migration/vmstate.h"
54
#include "qemu/module.h"
55
-
56
-#undef REG_FMT
57
-#define REG_FMT            "0x%02lx"
58
+#include "qemu/log.h"
59
60
/* SCOOP devices */
61
62
@@ -XXX,XX +XXX,XX @@ static uint64_t scoop_read(void *opaque, hwaddr addr,
63
case SCOOP_GPRR:
64
return s->gpio_level;
65
default:
66
- zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
67
+ qemu_log_mask(LOG_GUEST_ERROR,
68
+ "scoop_read: bad register offset 0x%02" HWADDR_PRIx "\n",
69
+ addr);
70
}
71
72
return 0;
73
@@ -XXX,XX +XXX,XX @@ static void scoop_write(void *opaque, hwaddr addr,
74
scoop_gpio_handler_update(s);
75
break;
76
default:
77
- zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
78
+ qemu_log_mask(LOG_GUEST_ERROR,
79
+ "scoop_write: bad register offset 0x%02" HWADDR_PRIx "\n",
80
+ addr);
81
}
82
}
83
84
--
85
2.20.1
86
87
diff view generated by jsdifflib
New patch
1
Instead of logging guest accesses to invalid register offsets in the
2
Spitz flash device with zaurus_printf() (which just prints to stderr),
3
use the usual qemu_log_mask(LOG_GUEST_ERROR,...).
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20200628142429.17111-15-peter.maydell@linaro.org
9
---
10
hw/arm/spitz.c | 12 +++++++-----
11
1 file changed, 7 insertions(+), 5 deletions(-)
12
13
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/spitz.c
16
+++ b/hw/arm/spitz.c
17
@@ -XXX,XX +XXX,XX @@
18
#include "hw/ssi/ssi.h"
19
#include "hw/block/flash.h"
20
#include "qemu/timer.h"
21
+#include "qemu/log.h"
22
#include "hw/arm/sharpsl.h"
23
#include "ui/console.h"
24
#include "hw/audio/wm8750.h"
25
@@ -XXX,XX +XXX,XX @@ typedef struct {
26
#define zaurus_printf(format, ...) \
27
fprintf(stderr, "%s: " format, __func__, ##__VA_ARGS__)
28
29
-#undef REG_FMT
30
-#define REG_FMT "0x%02lx"
31
-
32
/* Spitz Flash */
33
#define FLASH_BASE 0x0c000000
34
#define FLASH_ECCLPLB 0x00 /* Line parity 7 - 0 bit */
35
@@ -XXX,XX +XXX,XX @@ static uint64_t sl_read(void *opaque, hwaddr addr, unsigned size)
36
return ecc_digest(&s->ecc, nand_getio(s->nand));
37
38
default:
39
- zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
40
+ qemu_log_mask(LOG_GUEST_ERROR,
41
+ "sl_read: bad register offset 0x%02" HWADDR_PRIx "\n",
42
+ addr);
43
}
44
return 0;
45
}
46
@@ -XXX,XX +XXX,XX @@ static void sl_write(void *opaque, hwaddr addr,
47
break;
48
49
default:
50
- zaurus_printf("Bad register offset " REG_FMT "\n", (unsigned long)addr);
51
+ qemu_log_mask(LOG_GUEST_ERROR,
52
+ "sl_write: bad register offset 0x%02" HWADDR_PRIx "\n",
53
+ addr);
54
}
55
}
56
57
--
58
2.20.1
59
60
diff view generated by jsdifflib
New patch
1
Instead of using printf() for logging guest accesses to invalid
2
register offsets in the pxa2xx PIC device, use the usual
3
qemu_log_mask(LOG_GUEST_ERROR,...).
1
4
5
This was the only user of the REG_FMT macro in pxa.h, so we can
6
remove that.
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-id: 20200628142429.17111-16-peter.maydell@linaro.org
12
---
13
include/hw/arm/pxa.h | 1 -
14
hw/arm/pxa2xx_pic.c | 9 +++++++--
15
2 files changed, 7 insertions(+), 3 deletions(-)
16
17
diff --git a/include/hw/arm/pxa.h b/include/hw/arm/pxa.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/arm/pxa.h
20
+++ b/include/hw/arm/pxa.h
21
@@ -XXX,XX +XXX,XX @@ struct PXA2xxI2SState {
22
};
23
24
# define PA_FMT            "0x%08lx"
25
-# define REG_FMT        "0x" TARGET_FMT_plx
26
27
PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size,
28
const char *revision);
29
diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/arm/pxa2xx_pic.c
32
+++ b/hw/arm/pxa2xx_pic.c
33
@@ -XXX,XX +XXX,XX @@
34
#include "qemu/osdep.h"
35
#include "qapi/error.h"
36
#include "qemu/module.h"
37
+#include "qemu/log.h"
38
#include "cpu.h"
39
#include "hw/arm/pxa.h"
40
#include "hw/sysbus.h"
41
@@ -XXX,XX +XXX,XX @@ static uint64_t pxa2xx_pic_mem_read(void *opaque, hwaddr offset,
42
case ICHP:    /* Highest Priority register */
43
return pxa2xx_pic_highest(s);
44
default:
45
- printf("%s: Bad register offset " REG_FMT "\n", __func__, offset);
46
+ qemu_log_mask(LOG_GUEST_ERROR,
47
+ "pxa2xx_pic_mem_read: bad register offset 0x%" HWADDR_PRIx
48
+ "\n", offset);
49
return 0;
50
}
51
}
52
@@ -XXX,XX +XXX,XX @@ static void pxa2xx_pic_mem_write(void *opaque, hwaddr offset,
53
s->priority[32 + ((offset - IPR32) >> 2)] = value & 0x8000003f;
54
break;
55
default:
56
- printf("%s: Bad register offset " REG_FMT "\n", __func__, offset);
57
+ qemu_log_mask(LOG_GUEST_ERROR,
58
+ "pxa2xx_pic_mem_write: bad register offset 0x%"
59
+ HWADDR_PRIx "\n", offset);
60
return;
61
}
62
pxa2xx_pic_update(opaque);
63
--
64
2.20.1
65
66
diff view generated by jsdifflib
New patch
1
The QOM types "spitz-lcdtg" and "corgi-ssp" are missing the
2
usual QOM TYPE and casting macros; provide and use them.
1
3
4
In particular, we can safely use the QOM cast macros instead of
5
FROM_SSI_SLAVE() because in both cases the 'ssidev' field of
6
the instance state struct is the first field in it.
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
11
Message-id: 20200628142429.17111-17-peter.maydell@linaro.org
12
---
13
hw/arm/spitz.c | 23 +++++++++++++++--------
14
1 file changed, 15 insertions(+), 8 deletions(-)
15
16
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/spitz.c
19
+++ b/hw/arm/spitz.c
20
@@ -XXX,XX +XXX,XX @@ static void spitz_keyboard_realize(DeviceState *dev, Error **errp)
21
#define LCDTG_PICTRL 0x06
22
#define LCDTG_POLCTRL 0x07
23
24
+#define TYPE_SPITZ_LCDTG "spitz-lcdtg"
25
+#define SPITZ_LCDTG(obj) OBJECT_CHECK(SpitzLCDTG, (obj), TYPE_SPITZ_LCDTG)
26
+
27
typedef struct {
28
SSISlave ssidev;
29
uint32_t bl_intensity;
30
@@ -XXX,XX +XXX,XX @@ static inline void spitz_bl_power(void *opaque, int line, int level)
31
32
static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
33
{
34
- SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, dev);
35
+ SpitzLCDTG *s = SPITZ_LCDTG(dev);
36
int addr;
37
addr = value >> 5;
38
value &= 0x1f;
39
@@ -XXX,XX +XXX,XX @@ static uint32_t spitz_lcdtg_transfer(SSISlave *dev, uint32_t value)
40
41
static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp)
42
{
43
- SpitzLCDTG *s = FROM_SSI_SLAVE(SpitzLCDTG, ssi);
44
+ SpitzLCDTG *s = SPITZ_LCDTG(ssi);
45
DeviceState *dev = DEVICE(s);
46
47
s->bl_power = 0;
48
@@ -XXX,XX +XXX,XX @@ static void spitz_lcdtg_realize(SSISlave *ssi, Error **errp)
49
#define SPITZ_GPIO_MAX1111_CS 20
50
#define SPITZ_GPIO_TP_INT 11
51
52
+#define TYPE_CORGI_SSP "corgi-ssp"
53
+#define CORGI_SSP(obj) OBJECT_CHECK(CorgiSSPState, (obj), TYPE_CORGI_SSP)
54
+
55
/* "Demux" the signal based on current chipselect */
56
typedef struct {
57
SSISlave ssidev;
58
@@ -XXX,XX +XXX,XX @@ typedef struct {
59
60
static uint32_t corgi_ssp_transfer(SSISlave *dev, uint32_t value)
61
{
62
- CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, dev);
63
+ CorgiSSPState *s = CORGI_SSP(dev);
64
int i;
65
66
for (i = 0; i < 3; i++) {
67
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_gpio_cs(void *opaque, int line, int level)
68
static void corgi_ssp_realize(SSISlave *d, Error **errp)
69
{
70
DeviceState *dev = DEVICE(d);
71
- CorgiSSPState *s = FROM_SSI_SLAVE(CorgiSSPState, d);
72
+ CorgiSSPState *s = CORGI_SSP(d);
73
74
qdev_init_gpio_in(dev, corgi_ssp_gpio_cs, 3);
75
s->bus[0] = ssi_create_bus(dev, "ssi0");
76
@@ -XXX,XX +XXX,XX @@ static void spitz_ssp_attach(SpitzMachineState *sms)
77
{
78
void *bus;
79
80
- sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1], "corgi-ssp");
81
+ sms->mux = ssi_create_slave(sms->mpu->ssp[CORGI_SSP_PORT - 1],
82
+ TYPE_CORGI_SSP);
83
84
bus = qdev_get_child_bus(sms->mux, "ssi0");
85
- sms->lcdtg = ssi_create_slave(bus, "spitz-lcdtg");
86
+ sms->lcdtg = ssi_create_slave(bus, TYPE_SPITZ_LCDTG);
87
88
bus = qdev_get_child_bus(sms->mux, "ssi1");
89
sms->ads7846 = ssi_create_slave(bus, "ads7846");
90
@@ -XXX,XX +XXX,XX @@ static void corgi_ssp_class_init(ObjectClass *klass, void *data)
91
}
92
93
static const TypeInfo corgi_ssp_info = {
94
- .name = "corgi-ssp",
95
+ .name = TYPE_CORGI_SSP,
96
.parent = TYPE_SSI_SLAVE,
97
.instance_size = sizeof(CorgiSSPState),
98
.class_init = corgi_ssp_class_init,
99
@@ -XXX,XX +XXX,XX @@ static void spitz_lcdtg_class_init(ObjectClass *klass, void *data)
100
}
101
102
static const TypeInfo spitz_lcdtg_info = {
103
- .name = "spitz-lcdtg",
104
+ .name = TYPE_SPITZ_LCDTG,
105
.parent = TYPE_SSI_SLAVE,
106
.instance_size = sizeof(SpitzLCDTG),
107
.class_init = spitz_lcdtg_class_init,
108
--
109
2.20.1
110
111
diff view generated by jsdifflib
1
In ich_vmcr_write() we enforce "writes of BPR fields to less than
1
The FROM_SSI_SLAVE() macro predates QOM and is used as a typesafe way
2
their minimum sets them to the minimum" by doing a "read vbpr and
2
to cast from an SSISlave* to the instance struct of a subtype of
3
write it back" operation. A typo here meant that we weren't handling
3
TYPE_SSI_SLAVE. Switch to using the QOM cast macros instead, which
4
writes to these fields correctly, because we were reading from VBPR0
4
have the same effect (by writing the QOM macros if the types were
5
but writing to VBPR1.
5
previously missing them.)
6
7
(The FROM_SSI_SLAVE() macro allows the SSISlave member of the
8
subtype's struct to be anywhere as long as it is named "ssidev",
9
whereas a QOM cast macro insists that it is the first thing in the
10
subtype's struct. This is true for all the types we convert here.)
11
12
This removes all the uses of FROM_SSI_SLAVE() so we can delete the
13
definition.
6
14
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
16
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20190520162809.2677-4-peter.maydell@linaro.org
17
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
18
Message-id: 20200628142429.17111-18-peter.maydell@linaro.org
10
---
19
---
11
hw/intc/arm_gicv3_cpuif.c | 2 +-
20
include/hw/ssi/ssi.h | 2 --
12
1 file changed, 1 insertion(+), 1 deletion(-)
21
hw/arm/z2.c | 11 +++++++----
22
hw/display/ads7846.c | 9 ++++++---
23
hw/display/ssd0323.c | 10 +++++++---
24
hw/sd/ssi-sd.c | 4 ++--
25
5 files changed, 22 insertions(+), 14 deletions(-)
13
26
14
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
27
diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h
15
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/arm_gicv3_cpuif.c
29
--- a/include/hw/ssi/ssi.h
17
+++ b/hw/intc/arm_gicv3_cpuif.c
30
+++ b/include/hw/ssi/ssi.h
18
@@ -XXX,XX +XXX,XX @@ static void ich_vmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
31
@@ -XXX,XX +XXX,XX @@ struct SSISlave {
19
/* Enforce "writing BPRs to less than minimum sets them to the minimum"
32
bool cs;
20
* by reading and writing back the fields.
33
};
21
*/
34
22
- write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G0));
35
-#define FROM_SSI_SLAVE(type, dev) DO_UPCAST(type, ssidev, dev)
23
+ write_vbpr(cs, GICV3_G0, read_vbpr(cs, GICV3_G0));
36
-
24
write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G1));
37
extern const VMStateDescription vmstate_ssi_slave;
25
38
26
gicv3_cpuif_virt_update(cs);
39
#define VMSTATE_SSI_SLAVE(_field, _state) { \
40
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/hw/arm/z2.c
43
+++ b/hw/arm/z2.c
44
@@ -XXX,XX +XXX,XX @@ typedef struct {
45
int pos;
46
} ZipitLCD;
47
48
+#define TYPE_ZIPIT_LCD "zipit-lcd"
49
+#define ZIPIT_LCD(obj) OBJECT_CHECK(ZipitLCD, (obj), TYPE_ZIPIT_LCD)
50
+
51
static uint32_t zipit_lcd_transfer(SSISlave *dev, uint32_t value)
52
{
53
- ZipitLCD *z = FROM_SSI_SLAVE(ZipitLCD, dev);
54
+ ZipitLCD *z = ZIPIT_LCD(dev);
55
uint16_t val;
56
if (z->selected) {
57
z->buf[z->pos] = value & 0xff;
58
@@ -XXX,XX +XXX,XX @@ static void z2_lcd_cs(void *opaque, int line, int level)
59
60
static void zipit_lcd_realize(SSISlave *dev, Error **errp)
61
{
62
- ZipitLCD *z = FROM_SSI_SLAVE(ZipitLCD, dev);
63
+ ZipitLCD *z = ZIPIT_LCD(dev);
64
z->selected = 0;
65
z->enabled = 0;
66
z->pos = 0;
67
@@ -XXX,XX +XXX,XX @@ static void zipit_lcd_class_init(ObjectClass *klass, void *data)
68
}
69
70
static const TypeInfo zipit_lcd_info = {
71
- .name = "zipit-lcd",
72
+ .name = TYPE_ZIPIT_LCD,
73
.parent = TYPE_SSI_SLAVE,
74
.instance_size = sizeof(ZipitLCD),
75
.class_init = zipit_lcd_class_init,
76
@@ -XXX,XX +XXX,XX @@ static void z2_init(MachineState *machine)
77
78
type_register_static(&zipit_lcd_info);
79
type_register_static(&aer915_info);
80
- z2_lcd = ssi_create_slave(mpu->ssp[1], "zipit-lcd");
81
+ z2_lcd = ssi_create_slave(mpu->ssp[1], TYPE_ZIPIT_LCD);
82
bus = pxa2xx_i2c_bus(mpu->i2c[0]);
83
i2c_create_slave(bus, TYPE_AER915, 0x55);
84
wm = i2c_create_slave(bus, TYPE_WM8750, 0x1b);
85
diff --git a/hw/display/ads7846.c b/hw/display/ads7846.c
86
index XXXXXXX..XXXXXXX 100644
87
--- a/hw/display/ads7846.c
88
+++ b/hw/display/ads7846.c
89
@@ -XXX,XX +XXX,XX @@ typedef struct {
90
int output;
91
} ADS7846State;
92
93
+#define TYPE_ADS7846 "ads7846"
94
+#define ADS7846(obj) OBJECT_CHECK(ADS7846State, (obj), TYPE_ADS7846)
95
+
96
/* Control-byte bitfields */
97
#define CB_PD0        (1 << 0)
98
#define CB_PD1        (1 << 1)
99
@@ -XXX,XX +XXX,XX @@ static void ads7846_int_update(ADS7846State *s)
100
101
static uint32_t ads7846_transfer(SSISlave *dev, uint32_t value)
102
{
103
- ADS7846State *s = FROM_SSI_SLAVE(ADS7846State, dev);
104
+ ADS7846State *s = ADS7846(dev);
105
106
switch (s->cycle ++) {
107
case 0:
108
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_ads7846 = {
109
static void ads7846_realize(SSISlave *d, Error **errp)
110
{
111
DeviceState *dev = DEVICE(d);
112
- ADS7846State *s = FROM_SSI_SLAVE(ADS7846State, d);
113
+ ADS7846State *s = ADS7846(d);
114
115
qdev_init_gpio_out(dev, &s->interrupt, 1);
116
117
@@ -XXX,XX +XXX,XX @@ static void ads7846_class_init(ObjectClass *klass, void *data)
118
}
119
120
static const TypeInfo ads7846_info = {
121
- .name = "ads7846",
122
+ .name = TYPE_ADS7846,
123
.parent = TYPE_SSI_SLAVE,
124
.instance_size = sizeof(ADS7846State),
125
.class_init = ads7846_class_init,
126
diff --git a/hw/display/ssd0323.c b/hw/display/ssd0323.c
127
index XXXXXXX..XXXXXXX 100644
128
--- a/hw/display/ssd0323.c
129
+++ b/hw/display/ssd0323.c
130
@@ -XXX,XX +XXX,XX @@ typedef struct {
131
uint8_t framebuffer[128 * 80 / 2];
132
} ssd0323_state;
133
134
+#define TYPE_SSD0323 "ssd0323"
135
+#define SSD0323(obj) OBJECT_CHECK(ssd0323_state, (obj), TYPE_SSD0323)
136
+
137
+
138
static uint32_t ssd0323_transfer(SSISlave *dev, uint32_t data)
139
{
140
- ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, dev);
141
+ ssd0323_state *s = SSD0323(dev);
142
143
switch (s->mode) {
144
case SSD0323_DATA:
145
@@ -XXX,XX +XXX,XX @@ static const GraphicHwOps ssd0323_ops = {
146
static void ssd0323_realize(SSISlave *d, Error **errp)
147
{
148
DeviceState *dev = DEVICE(d);
149
- ssd0323_state *s = FROM_SSI_SLAVE(ssd0323_state, d);
150
+ ssd0323_state *s = SSD0323(d);
151
152
s->col_end = 63;
153
s->row_end = 79;
154
@@ -XXX,XX +XXX,XX @@ static void ssd0323_class_init(ObjectClass *klass, void *data)
155
}
156
157
static const TypeInfo ssd0323_info = {
158
- .name = "ssd0323",
159
+ .name = TYPE_SSD0323,
160
.parent = TYPE_SSI_SLAVE,
161
.instance_size = sizeof(ssd0323_state),
162
.class_init = ssd0323_class_init,
163
diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c
164
index XXXXXXX..XXXXXXX 100644
165
--- a/hw/sd/ssi-sd.c
166
+++ b/hw/sd/ssi-sd.c
167
@@ -XXX,XX +XXX,XX @@ typedef struct {
168
169
static uint32_t ssi_sd_transfer(SSISlave *dev, uint32_t val)
170
{
171
- ssi_sd_state *s = FROM_SSI_SLAVE(ssi_sd_state, dev);
172
+ ssi_sd_state *s = SSI_SD(dev);
173
174
/* Special case: allow CMD12 (STOP TRANSMISSION) while reading data. */
175
if (s->mode == SSI_SD_DATA_READ && val == 0x4d) {
176
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_ssi_sd = {
177
178
static void ssi_sd_realize(SSISlave *d, Error **errp)
179
{
180
- ssi_sd_state *s = FROM_SSI_SLAVE(ssi_sd_state, d);
181
+ ssi_sd_state *s = SSI_SD(d);
182
DeviceState *carddev;
183
DriveInfo *dinfo;
184
Error *err = NULL;
27
--
185
--
28
2.20.1
186
2.20.1
29
187
30
188
diff view generated by jsdifflib
1
The system_clock_scale global is used only by the armv7m systick
1
Deprecate our TileGX target support:
2
device; move the extern declaration to the armv7m_systick.h header,
2
* we have no active maintainer for it
3
and expand the comment to explain what it is and that it should
3
* it has had essentially no contributions (other than tree-wide cleanups
4
ideally be replaced with a different approach.
4
and similar) since it was first added
5
* the Linux kernel dropped support in 2018, as has glibc
6
7
Note the deprecation in the manual, but don't try to print a warning
8
when QEMU runs -- printing unsuppressable messages is more obtrusive
9
for linux-user mode than it would be for system-emulation mode, and
10
it doesn't seem worth trying to invent a new suppressible-error
11
system for linux-user just for this.
5
12
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
8
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20190516163857.6430-2-peter.maydell@linaro.org
16
Reviewed-by: Thomas Huth <thuth@redhat.com>
17
Message-id: 20200619154831.26319-1-peter.maydell@linaro.org
10
---
18
---
11
include/hw/arm/arm.h | 4 ----
19
docs/system/deprecated.rst | 11 +++++++++++
12
include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++++++++
20
1 file changed, 11 insertions(+)
13
2 files changed, 22 insertions(+), 4 deletions(-)
14
21
15
diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h
22
diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst
16
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/arm.h
24
--- a/docs/system/deprecated.rst
18
+++ b/include/hw/arm/arm.h
25
+++ b/docs/system/deprecated.rst
19
@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
26
@@ -XXX,XX +XXX,XX @@ The above, converted to the current supported format::
20
const struct arm_boot_info *info,
27
21
hwaddr mvbar_addr);
28
json:{"file.driver":"rbd", "file.pool":"rbd", "file.image":"name"}
22
29
23
-/* Multiplication factor to convert from system clock ticks to qemu timer
30
+linux-user mode CPUs
24
- ticks. */
31
+--------------------
25
-extern int system_clock_scale;
26
-
27
#endif /* HW_ARM_H */
28
diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
29
index XXXXXXX..XXXXXXX 100644
30
--- a/include/hw/timer/armv7m_systick.h
31
+++ b/include/hw/timer/armv7m_systick.h
32
@@ -XXX,XX +XXX,XX @@ typedef struct SysTickState {
33
qemu_irq irq;
34
} SysTickState;
35
36
+/*
37
+ * Multiplication factor to convert from system clock ticks to qemu timer
38
+ * ticks. This should be set (by board code, usually) to a value
39
+ * equal to NANOSECONDS_PER_SECOND / frq, where frq is the clock frequency
40
+ * in Hz of the CPU.
41
+ *
42
+ * This value is used by the systick device when it is running in
43
+ * its "use the CPU clock" mode (ie when SYST_CSR.CLKSOURCE == 1) to
44
+ * set how fast the timer should tick.
45
+ *
46
+ * TODO: we should refactor this so that rather than using a global
47
+ * we use a device property or something similar. This is complicated
48
+ * because (a) the property would need to be plumbed through from the
49
+ * board code down through various layers to the systick device
50
+ * and (b) the property needs to be modifiable after realize, because
51
+ * the stellaris board uses this to implement the behaviour where the
52
+ * guest can reprogram the PLL registers to downclock the CPU, and the
53
+ * systick device needs to react accordingly. Possibly this should
54
+ * be deferred until we have a good API for modelling clock trees.
55
+ */
56
+extern int system_clock_scale;
57
+
32
+
58
#endif
33
+``tilegx`` CPUs (since 5.1.0)
34
+'''''''''''''''''''''''''''''
35
+
36
+The ``tilegx`` guest CPU support (which was only implemented in
37
+linux-user mode) is deprecated and will be removed in a future version
38
+of QEMU. Support for this CPU was removed from the upstream Linux
39
+kernel in 2018, and has also been dropped from glibc.
40
+
41
Related binaries
42
----------------
43
59
--
44
--
60
2.20.1
45
2.20.1
61
46
62
47
diff view generated by jsdifflib