Thomas Huth (2):

tests/acceptance: Add a test for the N800 and N810 arm machines

tests/acceptance: Add a test for the integratorcp arm machine

include/hw/intc/arm_gic.h | 2 +

include/hw/intc/arm_gic_common.h | 1 +

target/arm/cpu.h | 88 +++++-

hw/arm/integratorcp.c | 1 +

hw/arm/sbsa-ref.c | 3 +-

hw/arm/virt.c | 3 +-

hw/arm/xilinx_zynq.c | 5 +-

hw/arm/xlnx-versal.c | 3 +-

hw/cpu/a9mpcore.c | 4 +

hw/cpu/arm11mpcore.c | 5 +

hw/intc/arm_gic.c | 33 +-

hw/intc/arm_gic_common.c | 1 +

hw/intc/arm_gic_kvm.c | 9 +

hw/intc/armv7m_nvic.c | 20 +-

hw/usb/hcd-ehci-sysbus.c | 17 -

linux-user/arm/signal.c | 4 +-

linux-user/elfload.c | 25 +-

target/arm/arch_dump.c | 11 +-

target/arm/cpu.c | 44 +--

target/arm/cpu64.c | 5 +-

target/arm/helper.c | 23 +-

target/arm/kvm32.c | 5 -

target/arm/kvm64.c | 1 -

target/arm/m_helper.c | 11 +-

target/arm/machine.c | 5 +-

target/arm/translate-a64.c | 114 +++++++

target/arm/translate-vfp.inc.c | 448 +++++++++++++++++----------

target/arm/translate.c | 122 ++------

MAINTAINERS | 2 +

hw/arm/Kconfig | 1 +

target/arm/vfp-uncond.decode | 12 +-

target/arm/vfp.decode | 153 ++++-----

tests/acceptance/machine_arm_integratorcp.py | 99 ++++++

tests/acceptance/machine_arm_n8x0.py | 49 +++

34 files changed, 865 insertions(+), 464 deletions(-)

create mode 100644 tests/acceptance/machine_arm_integratorcp.py

create mode 100644 tests/acceptance/machine_arm_n8x0.py

From: Richard Henderson <richard.henderson@linaro.org>

We had set this for aarch32-only in arm_max_initfn, but

failed to set the same bit for aarch64.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20200218190958.745-2-richard.henderson@linaro.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/cpu64.c | 1 +

1 file changed, 1 insertion(+)

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu64.c

+++ b/target/arm/cpu64.c

@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)

cpu->isar.id_mmfr3 = u;

u = cpu->isar.id_mmfr4;

+ u = FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */

u = FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */

cpu->isar.id_mmfr4 = u;

--

2.20.1

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

The Linux kernel displays errors why trying to detect the PL041

audio interface:

Linux version 4.16.0 (linus@genomnajs) (gcc version 7.2.1 20171011 (Linaro GCC 7.2-2017.11)) #142 PREEMPT Wed May 9 13:24:55 CEST 2018

CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=00093177

CPU: VIVT data cache, VIVT instruction cache

OF: fdt: Machine model: ARM Integrator/CP

...

OF: amba_device_add() failed (-19) for /fpga/aaci@1d000000

Since we have it already modelled, simply plug it.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20200223233033.15371-2-f4bug@amsat.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/arm/integratorcp.c | 1 +

hw/arm/Kconfig | 1 +

2 files changed, 2 insertions(+)

diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/integratorcp.c

+++ b/hw/arm/integratorcp.c

@@ -XXX,XX +XXX,XX @@ static void integratorcp_init(MachineState *machine)

qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, 0));

qdev_connect_gpio_out(dev, 1,

qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN, 0));

+ sysbus_create_varargs("pl041", 0x1d000000, pic[25], NULL);

if (nd_table[0].used)

smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);

diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/Kconfig

+++ b/hw/arm/Kconfig

@@ -XXX,XX +XXX,XX @@ config INTEGRATOR

select INTEGRATOR_DEBUG

select PL011 # UART

select PL031 # RTC

+ select PL041 # audio

select PL050 # keyboard/mouse

select PL110 # pl111 LCD controller

select PL181 # display

--

2.20.1

From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>

The GICv2 allows the implementation to implement a variable number

of priority bits; unimplemented bits in the priority registers

are read as zeros, writes ignored. We were previously always

implementing a full 8 bits of priority, which is allowed but not

what the real hardware typically does (which is usually to have

4 or 5 bits of priority).

Add a new device property to allow the number of implemented

property bits to be specified.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>

Message-id: 1582537164-764-2-git-send-email-sai.pavan.boddu@xilinx.com

Suggested-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

[PMM: improved commit message]

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

include/hw/intc/arm_gic.h | 2 ++

include/hw/intc/arm_gic_common.h | 1 +

hw/intc/arm_gic.c | 33 ++++++++++++++++++++++++++++++--

hw/intc/arm_gic_common.c | 1 +

4 files changed, 35 insertions(+), 2 deletions(-)

diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/intc/arm_gic.h

+++ b/include/hw/intc/arm_gic.h

@@ -XXX,XX +XXX,XX @@

/* Number of SGI target-list bits */

#define GIC_TARGETLIST_BITS 8

+#define GIC_MAX_PRIORITY_BITS 8

+#define GIC_MIN_PRIORITY_BITS 4

#define TYPE_ARM_GIC "arm_gic"

#define ARM_GIC(obj) \

diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h

index XXXXXXX..XXXXXXX 100644

--- a/include/hw/intc/arm_gic_common.h

+++ b/include/hw/intc/arm_gic_common.h

@@ -XXX,XX +XXX,XX @@ typedef struct GICState {

uint16_t priority_mask[GIC_NCPU_VCPU];

uint16_t running_priority[GIC_NCPU_VCPU];

uint16_t current_pending[GIC_NCPU_VCPU];

+ uint32_t n_prio_bits;

/* If we present the GICv2 without security extensions to a guest,

* the guest can configure the GICC_CTLR to configure group 1 binary point

diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/intc/arm_gic.c

+++ b/hw/intc/arm_gic.c

@@ -XXX,XX +XXX,XX @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs)

return ret;

}

+static uint32_t gic_fullprio_mask(GICState *s, int cpu)

+{

+ /*

+ * Return a mask word which clears the unimplemented priority

+ * bits from a priority value for an interrupt. (Not to be

+ * confused with the group priority, whose mask depends on BPR.)

+ */

+ int priBits;

+

+ if (gic_is_vcpu(cpu)) {

+ priBits = GIC_VIRT_MAX_GROUP_PRIO_BITS;

+ } else {

+ priBits = s->n_prio_bits;

+ }

+ return ~0U << (8 - priBits);

+}

+

void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val,

MemTxAttrs attrs)

{

@@ -XXX,XX +XXX,XX @@ void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val,

val = 0x80 | (val >> 1); /* Non-secure view */

}

+ val &= gic_fullprio_mask(s, cpu);

+

if (irq < GIC_INTERNAL) {

s->priority1[irq][cpu] = val;

} else {

@@ -XXX,XX +XXX,XX @@ static uint32_t gic_dist_get_priority(GICState *s, int cpu, int irq,

}

prio = (prio << 1) & 0xff; /* Non-secure view */

}

- return prio;

+ return prio & gic_fullprio_mask(s, cpu);

}

static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask,

@@ -XXX,XX +XXX,XX @@ static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask,

return;

}

}

- s->priority_mask[cpu] = pmask;

+ s->priority_mask[cpu] = pmask & gic_fullprio_mask(s, cpu);

}

static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs)

@@ -XXX,XX +XXX,XX @@ static void arm_gic_realize(DeviceState *dev, Error **errp)

return;

}

+ if (s->n_prio_bits > GIC_MAX_PRIORITY_BITS ||

+ (s->virt_extn ? s->n_prio_bits < GIC_VIRT_MAX_GROUP_PRIO_BITS :

+ s->n_prio_bits < GIC_MIN_PRIORITY_BITS)) {

+ error_setg(errp, "num-priority-bits cannot be greater than %d"

+ " or less than %d", GIC_MAX_PRIORITY_BITS,

+ s->virt_extn ? GIC_VIRT_MAX_GROUP_PRIO_BITS :

+ GIC_MIN_PRIORITY_BITS);

+ return;

+ }

+

/* This creates distributor, main CPU interface (s->cpuiomem[0]) and if

* enabled, virtualization extensions related interfaces (main virtual

* interface (s->vifaceiomem[0]) and virtual CPU interface).

diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/intc/arm_gic_common.c

+++ b/hw/intc/arm_gic_common.c

@@ -XXX,XX +XXX,XX @@ static Property arm_gic_common_properties[] = {

DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0),

/* True if the GIC should implement the virtualization extensions */

DEFINE_PROP_BOOL("has-virtualization-extensions", GICState, virt_extn, 0),

+ DEFINE_PROP_UINT32("num-priority-bits", GICState, n_prio_bits, 8),

DEFINE_PROP_END_OF_LIST(),

};

--

2.20.1

From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>

All A9 CPUs have a GIC with 5 bits of priority.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Message-id: 1582537164-764-3-git-send-email-sai.pavan.boddu@xilinx.com

Suggested-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/cpu/a9mpcore.c | 4 ++++

1 file changed, 4 insertions(+)

diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/cpu/a9mpcore.c

+++ b/hw/cpu/a9mpcore.c

@@ -XXX,XX +XXX,XX @@

#include "hw/qdev-properties.h"

#include "hw/core/cpu.h"

+#define A9_GIC_NUM_PRIORITY_BITS 5

+

static void a9mp_priv_set_irq(void *opaque, int irq, int level)

{

A9MPPrivState *s = (A9MPPrivState *)opaque;

@@ -XXX,XX +XXX,XX @@ static void a9mp_priv_realize(DeviceState *dev, Error **errp)

gicdev = DEVICE(&s->gic);

qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);

qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);

+ qdev_prop_set_uint32(gicdev, "num-priority-bits",

+ A9_GIC_NUM_PRIORITY_BITS);

/* Make the GIC's TZ support match the CPUs. We assume that

* either all the CPUs have TZ, or none do.

--

2.20.1

From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>

The GIC built into the ARM11MPCore is always implemented with 4

priority bits; set the GIC property accordingly.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Message-id: 1582537164-764-4-git-send-email-sai.pavan.boddu@xilinx.com

Suggested-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

[PMM: tweaked commit message]

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/cpu/arm11mpcore.c | 5 +++++

1 file changed, 5 insertions(+)

diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/cpu/arm11mpcore.c

+++ b/hw/cpu/arm11mpcore.c

@@ -XXX,XX +XXX,XX @@

#include "hw/irq.h"

#include "hw/qdev-properties.h"

+#define ARM11MPCORE_NUM_GIC_PRIORITY_BITS 4

static void mpcore_priv_set_irq(void *opaque, int irq, int level)

{

@@ -XXX,XX +XXX,XX @@ static void mpcore_priv_realize(DeviceState *dev, Error **errp)

qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);

qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);

+ qdev_prop_set_uint32(gicdev, "num-priority-bits",

+ ARM11MPCORE_NUM_GIC_PRIORITY_BITS);

+

+

object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);

if (err != NULL) {

error_propagate(errp, err);

--

2.20.1