1
Not very much here, but several people have fallen over
1
Target-arm queue for rc2 -- just some minor bugfixes.
2
the vector operation segfault bug, so let's get the fix
3
into master.
4
2
5
thanks
3
thanks
6
-- PMM
4
-- PMM
7
5
8
The following changes since commit d418238dca7b4e0b124135827ead3076233052b1:
6
The following changes since commit 6e5d4999c761ffa082f60d72a14e5c953515b417:
9
7
10
Merge remote-tracking branch 'remotes/rth/tags/pull-rng-20190522' into staging (2019-05-23 12:57:17 +0100)
8
Merge remote-tracking branch 'remotes/armbru/tags/pull-monitor-2019-11-19' into staging (2019-11-19 11:29:01 +0000)
11
9
12
are available in the Git repository at:
10
are available in the Git repository at:
13
11
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190523
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20191119
15
13
16
for you to fetch changes up to 98e4f4fdb8ea05d840f51f47125924c2bb9df2df:
14
for you to fetch changes up to 04c9c81b8fa2ee33f59a26265700fae6fc646062:
17
15
18
hw/arm/exynos4210: QOM'ify the Exynos4210 SoC (2019-05-23 14:47:44 +0100)
16
target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY (2019-11-19 13:20:28 +0000)
19
17
20
----------------------------------------------------------------
18
----------------------------------------------------------------
21
target-arm queue:
19
target-arm queue:
22
* exynos4210: QOM'ify the Exynos4210 SoC
20
* Support EL0 v7m msr/mrs for CONFIG_USER_ONLY
23
* exynos4210: Add DMA support for the Exynos4210
21
* Relax r13 restriction for ldrex/strex for v8.0
24
* arm_gicv3: Fix writes to ICC_CTLR_EL3
22
* Do not reject rt == rt2 for strexd
25
* arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
23
* net/cadence_gem: Set PHY autonegotiation restart status
26
* target/arm: Fix vector operation segfault
24
* ssi: xilinx_spips: Skip spi bus update for a few register writes
27
* target/arm: Minor improvements to BFXIL, EXTR
25
* pl031: Expose RTCICR as proper WC register
28
26
29
----------------------------------------------------------------
27
----------------------------------------------------------------
30
Alistair Francis (1):
28
Alexander Graf (1):
31
target/arm: Fix vector operation segfault
29
pl031: Expose RTCICR as proper WC register
32
30
33
Guenter Roeck (1):
31
Linus Ziegert (1):
34
hw/arm/exynos4210: Add DMA support for the Exynos4210
32
net/cadence_gem: Set PHY autonegotiation restart status
35
33
36
Peter Maydell (5):
34
Richard Henderson (4):
37
arm: Move system_clock_scale to armv7m_systick.h
35
target/arm: Merge arm_cpu_vq_map_next_smaller into sole caller
38
arm: Remove unnecessary includes of hw/arm/arm.h
36
target/arm: Do not reject rt == rt2 for strexd
39
arm: Rename hw/arm/arm.h to hw/arm/boot.h
37
target/arm: Relax r13 restriction for ldrex/strex for v8.0
40
hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
38
target/arm: Support EL0 v7m msr/mrs for CONFIG_USER_ONLY
41
hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3
42
39
43
Philippe Mathieu-Daudé (3):
40
Sai Pavan Boddu (1):
44
hw/arm/exynos4: Remove unuseful debug code
41
ssi: xilinx_spips: Skip spi bus update for a few register writes
45
hw/arm/exynos4: Use the IEC binary prefix definitions
46
hw/arm/exynos4210: QOM'ify the Exynos4210 SoC
47
42
48
Richard Henderson (2):
43
target/arm/cpu.h | 5 +--
49
target/arm: Use extract2 for EXTR
44
hw/net/cadence_gem.c | 9 ++--
50
target/arm: Simplify BFXIL expansion
45
hw/rtc/pl031.c | 6 +--
46
hw/ssi/xilinx_spips.c | 22 ++++++++--
47
target/arm/cpu64.c | 15 -------
48
target/arm/helper.c | 9 +++-
49
target/arm/m_helper.c | 114 ++++++++++++++++++++++++++++++-------------------
50
target/arm/translate.c | 14 +++---
51
8 files changed, 113 insertions(+), 81 deletions(-)
51
52
52
include/hw/arm/allwinner-a10.h | 2 +-
53
include/hw/arm/aspeed_soc.h | 1 -
54
include/hw/arm/bcm2836.h | 1 -
55
include/hw/arm/{arm.h => boot.h} | 12 +++------
56
include/hw/arm/exynos4210.h | 9 +++++--
57
include/hw/arm/fsl-imx25.h | 2 +-
58
include/hw/arm/fsl-imx31.h | 2 +-
59
include/hw/arm/fsl-imx6.h | 2 +-
60
include/hw/arm/fsl-imx6ul.h | 2 +-
61
include/hw/arm/fsl-imx7.h | 2 +-
62
include/hw/arm/virt.h | 2 +-
63
include/hw/arm/xlnx-versal.h | 2 +-
64
include/hw/arm/xlnx-zynqmp.h | 2 +-
65
include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++
66
hw/arm/armsse.c | 2 +-
67
hw/arm/armv7m.c | 2 +-
68
hw/arm/aspeed.c | 2 +-
69
hw/arm/boot.c | 2 +-
70
hw/arm/collie.c | 2 +-
71
hw/arm/exynos4210.c | 54 ++++++++++++++++++++++++++++++++++++---
72
hw/arm/exynos4_boards.c | 40 ++++++++---------------------
73
hw/arm/highbank.c | 2 +-
74
hw/arm/integratorcp.c | 2 +-
75
hw/arm/mainstone.c | 2 +-
76
hw/arm/microbit.c | 2 +-
77
hw/arm/mps2-tz.c | 2 +-
78
hw/arm/mps2.c | 2 +-
79
hw/arm/msf2-soc.c | 1 -
80
hw/arm/msf2-som.c | 2 +-
81
hw/arm/musca.c | 2 +-
82
hw/arm/musicpal.c | 2 +-
83
hw/arm/netduino2.c | 2 +-
84
hw/arm/nrf51_soc.c | 2 +-
85
hw/arm/nseries.c | 2 +-
86
hw/arm/omap1.c | 2 +-
87
hw/arm/omap2.c | 2 +-
88
hw/arm/omap_sx1.c | 2 +-
89
hw/arm/palm.c | 2 +-
90
hw/arm/raspi.c | 2 +-
91
hw/arm/realview.c | 2 +-
92
hw/arm/spitz.c | 2 +-
93
hw/arm/stellaris.c | 2 +-
94
hw/arm/stm32f205_soc.c | 2 +-
95
hw/arm/strongarm.c | 2 +-
96
hw/arm/tosa.c | 2 +-
97
hw/arm/versatilepb.c | 2 +-
98
hw/arm/vexpress.c | 2 +-
99
hw/arm/virt.c | 2 +-
100
hw/arm/xilinx_zynq.c | 2 +-
101
hw/arm/xlnx-versal.c | 2 +-
102
hw/arm/z2.c | 2 +-
103
hw/intc/arm_gicv3_cpuif.c | 6 ++---
104
hw/intc/armv7m_nvic.c | 1 -
105
target/arm/arm-semi.c | 1 -
106
target/arm/cpu.c | 1 -
107
target/arm/cpu64.c | 1 -
108
target/arm/kvm.c | 1 -
109
target/arm/kvm32.c | 1 -
110
target/arm/kvm64.c | 1 -
111
target/arm/translate-a64.c | 44 ++++++++++++++++---------------
112
target/arm/translate.c | 4 +--
113
61 files changed, 164 insertions(+), 123 deletions(-)
114
rename include/hw/arm/{arm.h => boot.h} (96%)
115
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Alexander Graf <graf@amazon.com>
2
2
3
It eases code review, unit is explicit.
3
The current PL031 RTCICR register implementation always clears the
4
IRQ pending status on a register write, regardless of the value the
5
guest writes.
4
6
5
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
To justify that behavior, it references the ARM926EJ-S Development
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Chip Reference Manual (DDI0287B) and indicates that said document
7
Message-id: 20190520214342.13709-3-philmd@redhat.com
9
states that any write clears the internal IRQ state. It is indeed
10
true that in section 11.1 this document says:
11
12
"The interrupt is cleared by writing any data value to the
13
interrupt clear register RTCICR".
14
15
However, later in section 11.2.2 it contradicts itself by saying:
16
17
"Writing 1 to bit 0 of RTCICR clears the RTCINTR flag."
18
19
The latter statement matches the PL031 TRM (DDI0224C), which says:
20
21
"Writing 1 to bit position 0 clears the corresponding interrupt.
22
Writing 0 has no effect."
23
24
Let's assume that the self-contradictory DDI0287B is in error, and
25
follow the reference manual for the device itself, by making the
26
register write-one-to-clear.
27
28
Reported-by: Hendrik Borghorst <hborghor@amazon.de>
29
Signed-off-by: Alexander Graf <graf@amazon.com>
30
Message-id: 20191104115228.30745-1-graf@amazon.com
31
[PMM: updated commit message to note that DDI0287B says two
32
conflicting things]
33
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
35
---
10
hw/arm/exynos4_boards.c | 5 +++--
36
hw/rtc/pl031.c | 6 +-----
11
1 file changed, 3 insertions(+), 2 deletions(-)
37
1 file changed, 1 insertion(+), 5 deletions(-)
12
38
13
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
39
diff --git a/hw/rtc/pl031.c b/hw/rtc/pl031.c
14
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
15
--- a/hw/arm/exynos4_boards.c
41
--- a/hw/rtc/pl031.c
16
+++ b/hw/arm/exynos4_boards.c
42
+++ b/hw/rtc/pl031.c
17
@@ -XXX,XX +XXX,XX @@
43
@@ -XXX,XX +XXX,XX @@ static void pl031_write(void * opaque, hwaddr offset,
18
*/
44
pl031_update(s);
19
45
break;
20
#include "qemu/osdep.h"
46
case RTC_ICR:
21
+#include "qemu/units.h"
47
- /* The PL031 documentation (DDI0224B) states that the interrupt is
22
#include "qapi/error.h"
48
- cleared when bit 0 of the written value is set. However the
23
#include "qemu/error-report.h"
49
- arm926e documentation (DDI0287B) states that the interrupt is
24
#include "qemu-common.h"
50
- cleared when any value is written. */
25
@@ -XXX,XX +XXX,XX @@ static int exynos4_board_smp_bootreg_addr[EXYNOS4_NUM_OF_BOARDS] = {
51
- s->is = 0;
26
};
52
+ s->is &= ~value;
27
53
pl031_update(s);
28
static unsigned long exynos4_board_ram_size[EXYNOS4_NUM_OF_BOARDS] = {
54
break;
29
- [EXYNOS4_BOARD_NURI] = 0x40000000,
55
case RTC_CR:
30
- [EXYNOS4_BOARD_SMDKC210] = 0x40000000,
31
+ [EXYNOS4_BOARD_NURI] = 1 * GiB,
32
+ [EXYNOS4_BOARD_SMDKC210] = 1 * GiB,
33
};
34
35
static struct arm_boot_info exynos4_board_binfo = {
36
--
56
--
37
2.20.1
57
2.20.1
38
58
39
59
diff view generated by jsdifflib
1
The hw/arm/arm.h header now only includes declarations relating
1
From: Richard Henderson <richard.henderson@linaro.org>
2
to boot.c code, so it is only needed by Arm board or SoC code.
3
Remove some unnecessary inclusions of it from target/arm files
4
and from hw/intc/armv7m_nvic.c.
5
2
3
Coverity reports, in sve_zcr_get_valid_len,
4
5
"Subtract operation overflows on operands
6
arm_cpu_vq_map_next_smaller(cpu, start_vq + 1U) and 1U"
7
8
First, the aarch32 stub version of arm_cpu_vq_map_next_smaller,
9
returning 0, does exactly what Coverity reports. Remove it.
10
11
Second, the aarch64 version of arm_cpu_vq_map_next_smaller has
12
a set of asserts, but they don't cover the case in question.
13
Further, there is a fair amount of extra arithmetic needed to
14
convert from the 0-based zcr register, to the 1-base vq form,
15
to the 0-based bitmap, and back again. This can be simplified
16
by leaving the value in the 0-based form.
17
18
Finally, use test_bit to simplify the common case, where the
19
length in the zcr registers is in fact a supported length.
20
21
Reported-by: Coverity (CID 1407217)
22
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
23
Reviewed-by: Andrew Jones <drjones@redhat.com>
24
Message-id: 20191118091414.19440-1-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20190516163857.6430-3-peter.maydell@linaro.org
10
---
26
---
11
hw/intc/armv7m_nvic.c | 1 -
27
target/arm/cpu.h | 3 ---
12
target/arm/arm-semi.c | 1 -
28
target/arm/cpu64.c | 15 ---------------
13
target/arm/cpu.c | 1 -
29
target/arm/helper.c | 9 +++++++--
14
target/arm/cpu64.c | 1 -
30
3 files changed, 7 insertions(+), 20 deletions(-)
15
target/arm/kvm.c | 1 -
16
target/arm/kvm32.c | 1 -
17
target/arm/kvm64.c | 1 -
18
7 files changed, 7 deletions(-)
19
31
20
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
32
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
21
index XXXXXXX..XXXXXXX 100644
33
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/intc/armv7m_nvic.c
34
--- a/target/arm/cpu.h
23
+++ b/hw/intc/armv7m_nvic.c
35
+++ b/target/arm/cpu.h
24
@@ -XXX,XX +XXX,XX @@
36
@@ -XXX,XX +XXX,XX @@ typedef struct {
25
#include "cpu.h"
37
#ifdef TARGET_AARCH64
26
#include "hw/sysbus.h"
38
# define ARM_MAX_VQ 16
27
#include "qemu/timer.h"
39
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);
28
-#include "hw/arm/arm.h"
40
-uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq);
29
#include "hw/intc/armv7m_nvic.h"
30
#include "target/arm/cpu.h"
31
#include "exec/exec-all.h"
32
diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/arm-semi.c
35
+++ b/target/arm/arm-semi.c
36
@@ -XXX,XX +XXX,XX @@
37
#else
41
#else
38
#include "qemu-common.h"
42
# define ARM_MAX_VQ 1
39
#include "exec/gdbstub.h"
43
static inline void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { }
40
-#include "hw/arm/arm.h"
44
-static inline uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq)
41
#include "qemu/cutils.h"
45
-{ return 0; }
42
#endif
46
#endif
43
47
44
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
48
typedef struct ARMVectorReg {
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/cpu.c
47
+++ b/target/arm/cpu.c
48
@@ -XXX,XX +XXX,XX @@
49
#if !defined(CONFIG_USER_ONLY)
50
#include "hw/loader.h"
51
#endif
52
-#include "hw/arm/arm.h"
53
#include "sysemu/sysemu.h"
54
#include "sysemu/hw_accel.h"
55
#include "kvm_arm.h"
56
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
49
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
57
index XXXXXXX..XXXXXXX 100644
50
index XXXXXXX..XXXXXXX 100644
58
--- a/target/arm/cpu64.c
51
--- a/target/arm/cpu64.c
59
+++ b/target/arm/cpu64.c
52
+++ b/target/arm/cpu64.c
60
@@ -XXX,XX +XXX,XX @@
53
@@ -XXX,XX +XXX,XX @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
61
#if !defined(CONFIG_USER_ONLY)
54
cpu->sve_max_vq = max_vq;
62
#include "hw/loader.h"
55
}
63
#endif
56
64
-#include "hw/arm/arm.h"
57
-uint32_t arm_cpu_vq_map_next_smaller(ARMCPU *cpu, uint32_t vq)
65
#include "sysemu/sysemu.h"
58
-{
66
#include "sysemu/kvm.h"
59
- uint32_t bitnum;
67
#include "kvm_arm.h"
60
-
68
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
61
- /*
62
- * We allow vq == ARM_MAX_VQ + 1 to be input because the caller may want
63
- * to find the maximum vq enabled, which may be ARM_MAX_VQ, but this
64
- * function always returns the next smaller than the input.
65
- */
66
- assert(vq && vq <= ARM_MAX_VQ + 1);
67
-
68
- bitnum = find_last_bit(cpu->sve_vq_map, vq - 1);
69
- return bitnum == vq - 1 ? 0 : bitnum + 1;
70
-}
71
-
72
static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *name,
73
void *opaque, Error **errp)
74
{
75
diff --git a/target/arm/helper.c b/target/arm/helper.c
69
index XXXXXXX..XXXXXXX 100644
76
index XXXXXXX..XXXXXXX 100644
70
--- a/target/arm/kvm.c
77
--- a/target/arm/helper.c
71
+++ b/target/arm/kvm.c
78
+++ b/target/arm/helper.c
72
@@ -XXX,XX +XXX,XX @@
79
@@ -XXX,XX +XXX,XX @@ int sve_exception_el(CPUARMState *env, int el)
73
#include "cpu.h"
80
74
#include "trace.h"
81
static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len)
75
#include "internals.h"
82
{
76
-#include "hw/arm/arm.h"
83
- uint32_t start_vq = (start_len & 0xf) + 1;
77
#include "hw/pci/pci.h"
84
+ uint32_t end_len;
78
#include "exec/memattrs.h"
85
79
#include "exec/address-spaces.h"
86
- return arm_cpu_vq_map_next_smaller(cpu, start_vq + 1) - 1;
80
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
87
+ end_len = start_len &= 0xf;
81
index XXXXXXX..XXXXXXX 100644
88
+ if (!test_bit(start_len, cpu->sve_vq_map)) {
82
--- a/target/arm/kvm32.c
89
+ end_len = find_last_bit(cpu->sve_vq_map, start_len);
83
+++ b/target/arm/kvm32.c
90
+ assert(end_len < start_len);
84
@@ -XXX,XX +XXX,XX @@
91
+ }
85
#include "sysemu/kvm.h"
92
+ return end_len;
86
#include "kvm_arm.h"
93
}
87
#include "internals.h"
94
88
-#include "hw/arm/arm.h"
95
/*
89
#include "qemu/log.h"
90
91
static inline void set_feature(uint64_t *features, int feature)
92
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
93
index XXXXXXX..XXXXXXX 100644
94
--- a/target/arm/kvm64.c
95
+++ b/target/arm/kvm64.c
96
@@ -XXX,XX +XXX,XX @@
97
#include "sysemu/kvm.h"
98
#include "kvm_arm.h"
99
#include "internals.h"
100
-#include "hw/arm/arm.h"
101
102
static bool have_guest_debug;
103
104
--
96
--
105
2.20.1
97
2.20.1
106
98
107
99
diff view generated by jsdifflib
1
From: Guenter Roeck <linux@roeck-us.net>
1
From: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
2
2
3
QEMU already supports pl330. Instantiate it for Exynos4210.
3
A few configuration register writes need not update the spi bus state, so just
4
return after the register write.
4
5
5
Relevant part of Linux arch/arm/boot/dts/exynos4.dtsi:
6
Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
6
7
/ {
8
soc: soc {
9
amba {
10
pdma0: pdma@12680000 {
11
compatible = "arm,pl330", "arm,primecell";
12
reg = <0x12680000 0x1000>;
13
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
14
clocks = <&clock CLK_PDMA0>;
15
clock-names = "apb_pclk";
16
#dma-cells = <1>;
17
#dma-channels = <8>;
18
#dma-requests = <32>;
19
};
20
pdma1: pdma@12690000 {
21
compatible = "arm,pl330", "arm,primecell";
22
reg = <0x12690000 0x1000>;
23
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
24
clocks = <&clock CLK_PDMA1>;
25
clock-names = "apb_pclk";
26
#dma-cells = <1>;
27
#dma-channels = <8>;
28
#dma-requests = <32>;
29
};
30
mdma1: mdma@12850000 {
31
compatible = "arm,pl330", "arm,primecell";
32
reg = <0x12850000 0x1000>;
33
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
34
clocks = <&clock CLK_MDMA>;
35
clock-names = "apb_pclk";
36
#dma-cells = <1>;
37
#dma-channels = <8>;
38
#dma-requests = <1>;
39
};
40
};
41
};
42
};
43
44
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
45
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
46
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
47
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
48
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Tested-by: Francisco Iglesias <frasse.iglesias@gmail.com>
49
Message-id: 20190520214342.13709-4-philmd@redhat.com
10
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
50
[PMD: Do not set default qdev properties, create the controllers in the SoC
11
Message-id: 1573830705-14579-1-git-send-email-sai.pavan.boddu@xilinx.com
51
rather than the board (Peter Maydell), add dtsi in commit message]
52
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
53
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
54
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
55
---
13
---
56
hw/arm/exynos4210.c | 26 ++++++++++++++++++++++++++
14
hw/ssi/xilinx_spips.c | 22 ++++++++++++++++++----
57
1 file changed, 26 insertions(+)
15
1 file changed, 18 insertions(+), 4 deletions(-)
58
16
59
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
17
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
60
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
61
--- a/hw/arm/exynos4210.c
19
--- a/hw/ssi/xilinx_spips.c
62
+++ b/hw/arm/exynos4210.c
20
+++ b/hw/ssi/xilinx_spips.c
63
@@ -XXX,XX +XXX,XX @@
21
@@ -XXX,XX +XXX,XX @@
64
/* EHCI */
22
#define R_GPIO (0x30 / 4)
65
#define EXYNOS4210_EHCI_BASE_ADDR 0x12580000
23
#define R_LPBK_DLY_ADJ (0x38 / 4)
66
24
#define R_LPBK_DLY_ADJ_RESET (0x33)
67
+/* DMA */
25
+#define R_IOU_TAPDLY_BYPASS (0x3C / 4)
68
+#define EXYNOS4210_PL330_BASE0_ADDR 0x12680000
26
#define R_TXD1 (0x80 / 4)
69
+#define EXYNOS4210_PL330_BASE1_ADDR 0x12690000
27
#define R_TXD2 (0x84 / 4)
70
+#define EXYNOS4210_PL330_BASE2_ADDR 0x12850000
28
#define R_TXD3 (0x88 / 4)
71
+
29
@@ -XXX,XX +XXX,XX @@
72
static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
30
#define R_LQSPI_STS (0xA4 / 4)
73
0x09, 0x00, 0x00, 0x00 };
31
#define LQSPI_STS_WR_RECVD (1 << 1)
74
32
75
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu)
33
+#define R_DUMMY_CYCLE_EN (0xC8 / 4)
76
return (0x9 << ARM_AFF1_SHIFT) | cpu;
34
+#define R_ECO (0xF8 / 4)
35
#define R_MOD_ID (0xFC / 4)
36
37
#define R_GQSPI_SELECT (0x144 / 4)
38
@@ -XXX,XX +XXX,XX @@ static void xilinx_spips_write(void *opaque, hwaddr addr,
39
{
40
int mask = ~0;
41
XilinxSPIPS *s = opaque;
42
+ bool try_flush = true;
43
44
DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);
45
addr >>= 2;
46
@@ -XXX,XX +XXX,XX @@ static void xilinx_spips_write(void *opaque, hwaddr addr,
47
tx_data_bytes(&s->tx_fifo, (uint32_t)value, 3,
48
s->regs[R_CONFIG] & R_CONFIG_ENDIAN);
49
goto no_reg_update;
50
+ /* Skip SPI bus update for below registers writes */
51
+ case R_GPIO:
52
+ case R_LPBK_DLY_ADJ:
53
+ case R_IOU_TAPDLY_BYPASS:
54
+ case R_DUMMY_CYCLE_EN:
55
+ case R_ECO:
56
+ try_flush = false;
57
+ break;
58
}
59
s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask);
60
no_reg_update:
61
- xilinx_spips_update_cs_lines(s);
62
- xilinx_spips_check_flush(s);
63
- xilinx_spips_update_cs_lines(s);
64
- xilinx_spips_update_ixr(s);
65
+ if (try_flush) {
66
+ xilinx_spips_update_cs_lines(s);
67
+ xilinx_spips_check_flush(s);
68
+ xilinx_spips_update_cs_lines(s);
69
+ xilinx_spips_update_ixr(s);
70
+ }
77
}
71
}
78
72
79
+static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
73
static const MemoryRegionOps spips_ops = {
80
+{
81
+ SysBusDevice *busdev;
82
+ DeviceState *dev;
83
+
84
+ dev = qdev_create(NULL, "pl330");
85
+ qdev_prop_set_uint8(dev, "num_periph_req", nreq);
86
+ qdev_init_nofail(dev);
87
+ busdev = SYS_BUS_DEVICE(dev);
88
+ sysbus_mmio_map(busdev, 0, base);
89
+ sysbus_connect_irq(busdev, 0, irq);
90
+}
91
+
92
Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
93
{
94
Exynos4210State *s = g_new0(Exynos4210State, 1);
95
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
96
sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
97
s->irq_table[exynos4210_get_irq(28, 3)]);
98
99
+ /*** DMA controllers ***/
100
+ pl330_create(EXYNOS4210_PL330_BASE0_ADDR,
101
+ qemu_irq_invert(s->irq_table[exynos4210_get_irq(35, 1)]), 32);
102
+ pl330_create(EXYNOS4210_PL330_BASE1_ADDR,
103
+ qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
104
+ pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
105
+ qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
106
+
107
return s;
108
}
109
--
74
--
110
2.20.1
75
2.20.1
111
76
112
77
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Linus Ziegert <linus.ziegert+qemu@holoplot.com>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
3
The Linux kernel PHY driver sets AN_RESTART in the BMCR of the
4
PHY when autonegotiation is started.
5
Recently the kernel started to read back the PHY's AN_RESTART
6
bit and now checks whether the autonegotiation is complete and
7
the bit was cleared [1]. Otherwise the link status is down.
8
9
The emulated PHY needs to clear AN_RESTART immediately to inform
10
the kernel driver about the completion of autonegotiation phase.
11
12
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=c36757eb9dee
13
14
Signed-off-by: Linus Ziegert <linus.ziegert+qemu@holoplot.com>
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
15
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Message-id: 20190520214342.13709-2-philmd@redhat.com
16
Message-id: 20191104181604.21943-1-linus.ziegert+qemu@holoplot.com
17
Cc: qemu-stable@nongnu.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
19
---
8
hw/arm/exynos4_boards.c | 24 ------------------------
20
hw/net/cadence_gem.c | 9 +++++----
9
1 file changed, 24 deletions(-)
21
1 file changed, 5 insertions(+), 4 deletions(-)
10
22
11
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
23
diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c
12
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/arm/exynos4_boards.c
25
--- a/hw/net/cadence_gem.c
14
+++ b/hw/arm/exynos4_boards.c
26
+++ b/hw/net/cadence_gem.c
15
@@ -XXX,XX +XXX,XX @@
27
@@ -XXX,XX +XXX,XX @@
16
#include "hw/net/lan9118.h"
28
#define PHY_REG_EXT_PHYSPCFC_ST 27
17
#include "hw/boards.h"
29
#define PHY_REG_CABLE_DIAG 28
18
30
19
-#undef DEBUG
31
-#define PHY_REG_CONTROL_RST 0x8000
20
-
32
-#define PHY_REG_CONTROL_LOOP 0x4000
21
-//#define DEBUG
33
-#define PHY_REG_CONTROL_ANEG 0x1000
22
-
34
+#define PHY_REG_CONTROL_RST 0x8000
23
-#ifdef DEBUG
35
+#define PHY_REG_CONTROL_LOOP 0x4000
24
- #undef PRINT_DEBUG
36
+#define PHY_REG_CONTROL_ANEG 0x1000
25
- #define PRINT_DEBUG(fmt, args...) \
37
+#define PHY_REG_CONTROL_ANRESTART 0x0200
26
- do { \
38
27
- fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \
39
#define PHY_REG_STATUS_LINK 0x0004
28
- } while (0)
40
#define PHY_REG_STATUS_ANEGCMPL 0x0020
29
-#else
41
@@ -XXX,XX +XXX,XX @@ static void gem_phy_write(CadenceGEMState *s, unsigned reg_num, uint16_t val)
30
- #define PRINT_DEBUG(fmt, args...) do {} while (0)
42
}
31
-#endif
43
if (val & PHY_REG_CONTROL_ANEG) {
32
-
44
/* Complete autonegotiation immediately */
33
#define SMDK_LAN9118_BASE_ADDR 0x05000000
45
- val &= ~PHY_REG_CONTROL_ANEG;
34
46
+ val &= ~(PHY_REG_CONTROL_ANEG | PHY_REG_CONTROL_ANRESTART);
35
typedef enum Exynos4BoardType {
47
s->phy_regs[PHY_REG_STATUS] |= PHY_REG_STATUS_ANEGCMPL;
36
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
48
}
37
exynos4_board_binfo.gic_cpu_if_addr =
49
if (val & PHY_REG_CONTROL_LOOP) {
38
EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100;
39
40
- PRINT_DEBUG("\n ram_size: %luMiB [0x%08lx]\n"
41
- " kernel_filename: %s\n"
42
- " kernel_cmdline: %s\n"
43
- " initrd_filename: %s\n",
44
- exynos4_board_ram_size[board_type] / 1048576,
45
- exynos4_board_ram_size[board_type],
46
- machine->kernel_filename,
47
- machine->kernel_cmdline,
48
- machine->initrd_filename);
49
-
50
exynos4_boards_init_ram(s, get_system_memory(),
51
exynos4_board_ram_size[board_type]);
52
53
--
50
--
54
2.20.1
51
2.20.1
55
52
56
53
diff view generated by jsdifflib
1
From: Alistair Francis <alistair.francis@wdc.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Commit 89e68b575 "target/arm: Use vector operations for saturation"
3
There was too much cut and paste between ldrexd and strexd,
4
causes this abort() when booting QEMU ARM with a Cortex-A15:
4
as ldrexd does prohibit two output registers the same.
5
5
6
0 0x00007ffff4c2382f in raise () at /usr/lib/libc.so.6
6
Fixes: af288228995
7
1 0x00007ffff4c0e672 in abort () at /usr/lib/libc.so.6
7
Reported-by: Michael Goffioul <michael.goffioul@gmail.com>
8
2 0x00005555559c1839 in disas_neon_data_insn (insn=<optimized out>, s=<optimized out>) at ./target/arm/translate.c:6673
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
3 0x00005555559c1839 in disas_neon_data_insn (s=<optimized out>, insn=<optimized out>) at ./target/arm/translate.c:6386
9
Message-id: 20191117090621.32425-2-richard.henderson@linaro.org
10
4 0x00005555559cd8a4 in disas_arm_insn (insn=4081107068, s=0x7fffe59a9510) at ./target/arm/translate.c:9289
10
Reviewed-by: Robert Foley <robert.foley@linaro.org>
11
5 0x00005555559cd8a4 in arm_tr_translate_insn (dcbase=0x7fffe59a9510, cpu=<optimized out>) at ./target/arm/translate.c:13612
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
6 0x00005555558d1d39 in translator_loop (ops=0x5555561cc580 <arm_translator_ops>, db=0x7fffe59a9510, cpu=0x55555686a2f0, tb=<optimized out>, max_insns=<optimized out>) at ./accel/tcg/translator.c:96
13
7 0x00005555559d10d4 in gen_intermediate_code (cpu=cpu@entry=0x55555686a2f0, tb=tb@entry=0x7fffd7840080 <code_gen_buffer+126091347>, max_insns=max_insns@entry=512) at ./target/arm/translate.c:13901
14
8 0x00005555558d06b9 in tb_gen_code (cpu=cpu@entry=0x55555686a2f0, pc=3067096216, cs_base=0, flags=192, cflags=-16252928, cflags@entry=524288) at ./accel/tcg/translate-all.c:1736
15
9 0x00005555558ce467 in tb_find (cf_mask=524288, tb_exit=1, last_tb=0x7fffd783e640 <code_gen_buffer+126084627>, cpu=0x1) at ./accel/tcg/cpu-exec.c:407
16
10 0x00005555558ce467 in cpu_exec (cpu=cpu@entry=0x55555686a2f0) at ./accel/tcg/cpu-exec.c:728
17
11 0x000055555588b0cf in tcg_cpu_exec (cpu=0x55555686a2f0) at ./cpus.c:1431
18
12 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=0x55555686a2f0) at ./cpus.c:1735
19
13 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=arg@entry=0x55555686a2f0) at ./cpus.c:1709
20
14 0x0000555555d2629a in qemu_thread_start (args=<optimized out>) at ./util/qemu-thread-posix.c:502
21
15 0x00007ffff4db8a92 in start_thread () at /usr/lib/libpthread.
22
23
This patch ensures that we don't hit the abort() in the second switch
24
case in disas_neon_data_insn() as we will return from the first case.
25
26
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
27
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
28
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
29
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
30
Tested-by: Alex Bennée <alex.bennee@linaro.org>
31
Message-id: ad91b397f360b2fc7f4087e476f7df5b04d42ddb.1558021877.git.alistair.francis@wdc.com
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
---
13
---
34
target/arm/translate.c | 4 ++--
14
target/arm/translate.c | 2 +-
35
1 file changed, 2 insertions(+), 2 deletions(-)
15
1 file changed, 1 insertion(+), 1 deletion(-)
36
16
37
diff --git a/target/arm/translate.c b/target/arm/translate.c
17
diff --git a/target/arm/translate.c b/target/arm/translate.c
38
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/translate.c
19
--- a/target/arm/translate.c
40
+++ b/target/arm/translate.c
20
+++ b/target/arm/translate.c
41
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
21
@@ -XXX,XX +XXX,XX @@ static bool op_strex(DisasContext *s, arg_STREX *a, MemOp mop, bool rel)
42
tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
22
|| (s->thumb && (a->rd == 13 || a->rt == 13))
43
rn_ofs, rm_ofs, vec_size, vec_size,
23
|| (mop == MO_64
44
(u ? uqadd_op : sqadd_op) + size);
24
&& (a->rt2 == 15
45
- break;
25
- || a->rd == a->rt2 || a->rt == a->rt2
46
+ return 0;
26
+ || a->rd == a->rt2
47
27
|| (s->thumb && a->rt2 == 13)))) {
48
case NEON_3R_VQSUB:
28
unallocated_encoding(s);
49
tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
29
return true;
50
rn_ofs, rm_ofs, vec_size, vec_size,
51
(u ? uqsub_op : sqsub_op) + size);
52
- break;
53
+ return 0;
54
55
case NEON_3R_VMUL: /* VMUL */
56
if (u) {
57
--
30
--
58
2.20.1
31
2.20.1
59
32
60
33
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This is, after all, how we implement extract2 in tcg/aarch64.
3
Armv8-A removes UNPREDICTABLE for R13 for these cases.
4
4
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20191117090621.32425-3-richard.henderson@linaro.org
7
[PMM: changed ENABLE_ARCH_8 checks to check a new bool 'v8a',
8
since these cases are still UNPREDICTABLE for v8M]
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20190514011129.11330-2-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
11
---
10
target/arm/translate-a64.c | 38 ++++++++++++++++++++------------------
12
target/arm/translate.c | 12 ++++++++----
11
1 file changed, 20 insertions(+), 18 deletions(-)
13
1 file changed, 8 insertions(+), 4 deletions(-)
12
14
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
17
--- a/target/arm/translate.c
16
+++ b/target/arm/translate-a64.c
18
+++ b/target/arm/translate.c
17
@@ -XXX,XX +XXX,XX @@ static void disas_extract(DisasContext *s, uint32_t insn)
19
@@ -XXX,XX +XXX,XX @@ static bool trans_SWPB(DisasContext *s, arg_SWP *a)
18
} else {
20
static bool op_strex(DisasContext *s, arg_STREX *a, MemOp mop, bool rel)
19
tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));
21
{
20
}
22
TCGv_i32 addr;
21
- } else if (rm == rn) { /* ROR */
23
+ /* Some cases stopped being UNPREDICTABLE in v8A (but not v8M) */
22
- tcg_rm = cpu_reg(s, rm);
24
+ bool v8a = ENABLE_ARCH_8 && !arm_dc_feature(s, ARM_FEATURE_M);
23
- if (sf) {
25
24
- tcg_gen_rotri_i64(tcg_rd, tcg_rm, imm);
26
/* We UNDEF for these UNPREDICTABLE cases. */
25
- } else {
27
if (a->rd == 15 || a->rn == 15 || a->rt == 15
26
- TCGv_i32 tmp = tcg_temp_new_i32();
28
|| a->rd == a->rn || a->rd == a->rt
27
- tcg_gen_extrl_i64_i32(tmp, tcg_rm);
29
- || (s->thumb && (a->rd == 13 || a->rt == 13))
28
- tcg_gen_rotri_i32(tmp, tmp, imm);
30
+ || (!v8a && s->thumb && (a->rd == 13 || a->rt == 13))
29
- tcg_gen_extu_i32_i64(tcg_rd, tmp);
31
|| (mop == MO_64
30
- tcg_temp_free_i32(tmp);
32
&& (a->rt2 == 15
31
- }
33
|| a->rd == a->rt2
32
} else {
34
- || (s->thumb && a->rt2 == 13)))) {
33
- tcg_rm = read_cpu_reg(s, rm, sf);
35
+ || (!v8a && s->thumb && a->rt2 == 13)))) {
34
- tcg_rn = read_cpu_reg(s, rn, sf);
36
unallocated_encoding(s);
35
- tcg_gen_shri_i64(tcg_rm, tcg_rm, imm);
37
return true;
36
- tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm);
38
}
37
- tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn);
39
@@ -XXX,XX +XXX,XX @@ static bool trans_STLH(DisasContext *s, arg_STL *a)
38
- if (!sf) {
40
static bool op_ldrex(DisasContext *s, arg_LDREX *a, MemOp mop, bool acq)
39
- tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
41
{
40
+ tcg_rm = cpu_reg(s, rm);
42
TCGv_i32 addr;
41
+ tcg_rn = cpu_reg(s, rn);
43
+ /* Some cases stopped being UNPREDICTABLE in v8A (but not v8M) */
42
+
44
+ bool v8a = ENABLE_ARCH_8 && !arm_dc_feature(s, ARM_FEATURE_M);
43
+ if (sf) {
45
44
+ /* Specialization to ROR happens in EXTRACT2. */
46
/* We UNDEF for these UNPREDICTABLE cases. */
45
+ tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, imm);
47
if (a->rn == 15 || a->rt == 15
46
+ } else {
48
- || (s->thumb && a->rt == 13)
47
+ TCGv_i32 t0 = tcg_temp_new_i32();
49
+ || (!v8a && s->thumb && a->rt == 13)
48
+
50
|| (mop == MO_64
49
+ tcg_gen_extrl_i64_i32(t0, tcg_rm);
51
&& (a->rt2 == 15 || a->rt == a->rt2
50
+ if (rm == rn) {
52
- || (s->thumb && a->rt2 == 13)))) {
51
+ tcg_gen_rotri_i32(t0, t0, imm);
53
+ || (!v8a && s->thumb && a->rt2 == 13)))) {
52
+ } else {
54
unallocated_encoding(s);
53
+ TCGv_i32 t1 = tcg_temp_new_i32();
55
return true;
54
+ tcg_gen_extrl_i64_i32(t1, tcg_rn);
55
+ tcg_gen_extract2_i32(t0, t0, t1, imm);
56
+ tcg_temp_free_i32(t1);
57
+ }
58
+ tcg_gen_extu_i32_i64(tcg_rd, t0);
59
+ tcg_temp_free_i32(t0);
60
}
61
}
62
}
56
}
63
--
57
--
64
2.20.1
58
2.20.1
65
59
66
60
diff view generated by jsdifflib
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
The mask implied by the extract is redundant with the one
4
implied by the deposit. Also, fix spelling of BFXIL.
5
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20190514011129.11330-3-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-a64.c | 6 +++---
12
1 file changed, 3 insertions(+), 3 deletions(-)
13
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
17
+++ b/target/arm/translate-a64.c
18
@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
19
tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len);
20
return;
21
}
22
- /* opc == 1, BXFIL fall through to deposit */
23
- tcg_gen_extract_i64(tcg_tmp, tcg_tmp, ri, len);
24
+ /* opc == 1, BFXIL fall through to deposit */
25
+ tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri);
26
pos = 0;
27
} else {
28
/* Handle the ri > si case with a deposit
29
@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
30
len = ri;
31
}
32
33
- if (opc == 1) { /* BFM, BXFIL */
34
+ if (opc == 1) { /* BFM, BFXIL */
35
tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len);
36
} else {
37
/* SBFM or UBFM: We start with zero, and we haven't modified
38
--
39
2.20.1
40
41
diff view generated by jsdifflib
Deleted patch
1
The system_clock_scale global is used only by the armv7m systick
2
device; move the extern declaration to the armv7m_systick.h header,
3
and expand the comment to explain what it is and that it should
4
ideally be replaced with a different approach.
5
1
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20190516163857.6430-2-peter.maydell@linaro.org
10
---
11
include/hw/arm/arm.h | 4 ----
12
include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++++++++
13
2 files changed, 22 insertions(+), 4 deletions(-)
14
15
diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/arm.h
18
+++ b/include/hw/arm/arm.h
19
@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
20
const struct arm_boot_info *info,
21
hwaddr mvbar_addr);
22
23
-/* Multiplication factor to convert from system clock ticks to qemu timer
24
- ticks. */
25
-extern int system_clock_scale;
26
-
27
#endif /* HW_ARM_H */
28
diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
29
index XXXXXXX..XXXXXXX 100644
30
--- a/include/hw/timer/armv7m_systick.h
31
+++ b/include/hw/timer/armv7m_systick.h
32
@@ -XXX,XX +XXX,XX @@ typedef struct SysTickState {
33
qemu_irq irq;
34
} SysTickState;
35
36
+/*
37
+ * Multiplication factor to convert from system clock ticks to qemu timer
38
+ * ticks. This should be set (by board code, usually) to a value
39
+ * equal to NANOSECONDS_PER_SECOND / frq, where frq is the clock frequency
40
+ * in Hz of the CPU.
41
+ *
42
+ * This value is used by the systick device when it is running in
43
+ * its "use the CPU clock" mode (ie when SYST_CSR.CLKSOURCE == 1) to
44
+ * set how fast the timer should tick.
45
+ *
46
+ * TODO: we should refactor this so that rather than using a global
47
+ * we use a device property or something similar. This is complicated
48
+ * because (a) the property would need to be plumbed through from the
49
+ * board code down through various layers to the systick device
50
+ * and (b) the property needs to be modifiable after realize, because
51
+ * the stellaris board uses this to implement the behaviour where the
52
+ * guest can reprogram the PLL registers to downclock the CPU, and the
53
+ * systick device needs to react accordingly. Possibly this should
54
+ * be deferred until we have a good API for modelling clock trees.
55
+ */
56
+extern int system_clock_scale;
57
+
58
#endif
59
--
60
2.20.1
61
62
diff view generated by jsdifflib
Deleted patch
1
The header file hw/arm/arm.h now includes only declarations
2
relating to hw/arm/boot.c functionality. Rename it accordingly,
3
and adjust its header comment.
4
1
5
The bulk of this commit was created via
6
perl -pi -e 's|hw/arm/arm.h|hw/arm/boot.h|' hw/arm/*.c include/hw/arm/*.h
7
8
In a few cases we can just delete the #include:
9
hw/arm/msf2-soc.c, include/hw/arm/aspeed_soc.h and
10
include/hw/arm/bcm2836.h did not require it.
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Message-id: 20190516163857.6430-4-peter.maydell@linaro.org
16
---
17
include/hw/arm/allwinner-a10.h | 2 +-
18
include/hw/arm/aspeed_soc.h | 1 -
19
include/hw/arm/bcm2836.h | 1 -
20
include/hw/arm/{arm.h => boot.h} | 8 ++++----
21
include/hw/arm/fsl-imx25.h | 2 +-
22
include/hw/arm/fsl-imx31.h | 2 +-
23
include/hw/arm/fsl-imx6.h | 2 +-
24
include/hw/arm/fsl-imx6ul.h | 2 +-
25
include/hw/arm/fsl-imx7.h | 2 +-
26
include/hw/arm/virt.h | 2 +-
27
include/hw/arm/xlnx-versal.h | 2 +-
28
include/hw/arm/xlnx-zynqmp.h | 2 +-
29
hw/arm/armsse.c | 2 +-
30
hw/arm/armv7m.c | 2 +-
31
hw/arm/aspeed.c | 2 +-
32
hw/arm/boot.c | 2 +-
33
hw/arm/collie.c | 2 +-
34
hw/arm/exynos4210.c | 2 +-
35
hw/arm/exynos4_boards.c | 2 +-
36
hw/arm/highbank.c | 2 +-
37
hw/arm/integratorcp.c | 2 +-
38
hw/arm/mainstone.c | 2 +-
39
hw/arm/microbit.c | 2 +-
40
hw/arm/mps2-tz.c | 2 +-
41
hw/arm/mps2.c | 2 +-
42
hw/arm/msf2-soc.c | 1 -
43
hw/arm/msf2-som.c | 2 +-
44
hw/arm/musca.c | 2 +-
45
hw/arm/musicpal.c | 2 +-
46
hw/arm/netduino2.c | 2 +-
47
hw/arm/nrf51_soc.c | 2 +-
48
hw/arm/nseries.c | 2 +-
49
hw/arm/omap1.c | 2 +-
50
hw/arm/omap2.c | 2 +-
51
hw/arm/omap_sx1.c | 2 +-
52
hw/arm/palm.c | 2 +-
53
hw/arm/raspi.c | 2 +-
54
hw/arm/realview.c | 2 +-
55
hw/arm/spitz.c | 2 +-
56
hw/arm/stellaris.c | 2 +-
57
hw/arm/stm32f205_soc.c | 2 +-
58
hw/arm/strongarm.c | 2 +-
59
hw/arm/tosa.c | 2 +-
60
hw/arm/versatilepb.c | 2 +-
61
hw/arm/vexpress.c | 2 +-
62
hw/arm/virt.c | 2 +-
63
hw/arm/xilinx_zynq.c | 2 +-
64
hw/arm/xlnx-versal.c | 2 +-
65
hw/arm/z2.c | 2 +-
66
49 files changed, 49 insertions(+), 52 deletions(-)
67
rename include/hw/arm/{arm.h => boot.h} (98%)
68
69
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
70
index XXXXXXX..XXXXXXX 100644
71
--- a/include/hw/arm/allwinner-a10.h
72
+++ b/include/hw/arm/allwinner-a10.h
73
@@ -XXX,XX +XXX,XX @@
74
#include "qemu-common.h"
75
#include "qemu/error-report.h"
76
#include "hw/char/serial.h"
77
-#include "hw/arm/arm.h"
78
+#include "hw/arm/boot.h"
79
#include "hw/timer/allwinner-a10-pit.h"
80
#include "hw/intc/allwinner-a10-pic.h"
81
#include "hw/net/allwinner_emac.h"
82
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
83
index XXXXXXX..XXXXXXX 100644
84
--- a/include/hw/arm/aspeed_soc.h
85
+++ b/include/hw/arm/aspeed_soc.h
86
@@ -XXX,XX +XXX,XX @@
87
#ifndef ASPEED_SOC_H
88
#define ASPEED_SOC_H
89
90
-#include "hw/arm/arm.h"
91
#include "hw/intc/aspeed_vic.h"
92
#include "hw/misc/aspeed_scu.h"
93
#include "hw/misc/aspeed_sdmc.h"
94
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
95
index XXXXXXX..XXXXXXX 100644
96
--- a/include/hw/arm/bcm2836.h
97
+++ b/include/hw/arm/bcm2836.h
98
@@ -XXX,XX +XXX,XX @@
99
#ifndef BCM2836_H
100
#define BCM2836_H
101
102
-#include "hw/arm/arm.h"
103
#include "hw/arm/bcm2835_peripherals.h"
104
#include "hw/intc/bcm2836_control.h"
105
106
diff --git a/include/hw/arm/arm.h b/include/hw/arm/boot.h
107
similarity index 98%
108
rename from include/hw/arm/arm.h
109
rename to include/hw/arm/boot.h
110
index XXXXXXX..XXXXXXX 100644
111
--- a/include/hw/arm/arm.h
112
+++ b/include/hw/arm/boot.h
113
@@ -XXX,XX +XXX,XX @@
114
/*
115
- * Misc ARM declarations
116
+ * ARM kernel loader.
117
*
118
* Copyright (c) 2006 CodeSourcery.
119
* Written by Paul Brook
120
@@ -XXX,XX +XXX,XX @@
121
*
122
*/
123
124
-#ifndef HW_ARM_H
125
-#define HW_ARM_H
126
+#ifndef HW_ARM_BOOT_H
127
+#define HW_ARM_BOOT_H
128
129
#include "exec/memory.h"
130
#include "target/arm/cpu-qom.h"
131
@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
132
const struct arm_boot_info *info,
133
hwaddr mvbar_addr);
134
135
-#endif /* HW_ARM_H */
136
+#endif /* HW_ARM_BOOT_H */
137
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
138
index XXXXXXX..XXXXXXX 100644
139
--- a/include/hw/arm/fsl-imx25.h
140
+++ b/include/hw/arm/fsl-imx25.h
141
@@ -XXX,XX +XXX,XX @@
142
#ifndef FSL_IMX25_H
143
#define FSL_IMX25_H
144
145
-#include "hw/arm/arm.h"
146
+#include "hw/arm/boot.h"
147
#include "hw/intc/imx_avic.h"
148
#include "hw/misc/imx25_ccm.h"
149
#include "hw/char/imx_serial.h"
150
diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h
151
index XXXXXXX..XXXXXXX 100644
152
--- a/include/hw/arm/fsl-imx31.h
153
+++ b/include/hw/arm/fsl-imx31.h
154
@@ -XXX,XX +XXX,XX @@
155
#ifndef FSL_IMX31_H
156
#define FSL_IMX31_H
157
158
-#include "hw/arm/arm.h"
159
+#include "hw/arm/boot.h"
160
#include "hw/intc/imx_avic.h"
161
#include "hw/misc/imx31_ccm.h"
162
#include "hw/char/imx_serial.h"
163
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
164
index XXXXXXX..XXXXXXX 100644
165
--- a/include/hw/arm/fsl-imx6.h
166
+++ b/include/hw/arm/fsl-imx6.h
167
@@ -XXX,XX +XXX,XX @@
168
#ifndef FSL_IMX6_H
169
#define FSL_IMX6_H
170
171
-#include "hw/arm/arm.h"
172
+#include "hw/arm/boot.h"
173
#include "hw/cpu/a9mpcore.h"
174
#include "hw/misc/imx6_ccm.h"
175
#include "hw/misc/imx6_src.h"
176
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
177
index XXXXXXX..XXXXXXX 100644
178
--- a/include/hw/arm/fsl-imx6ul.h
179
+++ b/include/hw/arm/fsl-imx6ul.h
180
@@ -XXX,XX +XXX,XX @@
181
#ifndef FSL_IMX6UL_H
182
#define FSL_IMX6UL_H
183
184
-#include "hw/arm/arm.h"
185
+#include "hw/arm/boot.h"
186
#include "hw/cpu/a15mpcore.h"
187
#include "hw/misc/imx6ul_ccm.h"
188
#include "hw/misc/imx6_src.h"
189
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
190
index XXXXXXX..XXXXXXX 100644
191
--- a/include/hw/arm/fsl-imx7.h
192
+++ b/include/hw/arm/fsl-imx7.h
193
@@ -XXX,XX +XXX,XX @@
194
#ifndef FSL_IMX7_H
195
#define FSL_IMX7_H
196
197
-#include "hw/arm/arm.h"
198
+#include "hw/arm/boot.h"
199
#include "hw/cpu/a15mpcore.h"
200
#include "hw/intc/imx_gpcv2.h"
201
#include "hw/misc/imx7_ccm.h"
202
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
203
index XXXXXXX..XXXXXXX 100644
204
--- a/include/hw/arm/virt.h
205
+++ b/include/hw/arm/virt.h
206
@@ -XXX,XX +XXX,XX @@
207
#include "exec/hwaddr.h"
208
#include "qemu/notify.h"
209
#include "hw/boards.h"
210
-#include "hw/arm/arm.h"
211
+#include "hw/arm/boot.h"
212
#include "hw/block/flash.h"
213
#include "sysemu/kvm.h"
214
#include "hw/intc/arm_gicv3_common.h"
215
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
216
index XXXXXXX..XXXXXXX 100644
217
--- a/include/hw/arm/xlnx-versal.h
218
+++ b/include/hw/arm/xlnx-versal.h
219
@@ -XXX,XX +XXX,XX @@
220
#define XLNX_VERSAL_H
221
222
#include "hw/sysbus.h"
223
-#include "hw/arm/arm.h"
224
+#include "hw/arm/boot.h"
225
#include "hw/intc/arm_gicv3.h"
226
227
#define TYPE_XLNX_VERSAL "xlnx-versal"
228
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
229
index XXXXXXX..XXXXXXX 100644
230
--- a/include/hw/arm/xlnx-zynqmp.h
231
+++ b/include/hw/arm/xlnx-zynqmp.h
232
@@ -XXX,XX +XXX,XX @@
233
#ifndef XLNX_ZYNQMP_H
234
235
#include "qemu-common.h"
236
-#include "hw/arm/arm.h"
237
+#include "hw/arm/boot.h"
238
#include "hw/intc/arm_gic.h"
239
#include "hw/net/cadence_gem.h"
240
#include "hw/char/cadence_uart.h"
241
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
242
index XXXXXXX..XXXXXXX 100644
243
--- a/hw/arm/armsse.c
244
+++ b/hw/arm/armsse.c
245
@@ -XXX,XX +XXX,XX @@
246
#include "hw/sysbus.h"
247
#include "hw/registerfields.h"
248
#include "hw/arm/armsse.h"
249
-#include "hw/arm/arm.h"
250
+#include "hw/arm/boot.h"
251
252
/* Format of the System Information block SYS_CONFIG register */
253
typedef enum SysConfigFormat {
254
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
255
index XXXXXXX..XXXXXXX 100644
256
--- a/hw/arm/armv7m.c
257
+++ b/hw/arm/armv7m.c
258
@@ -XXX,XX +XXX,XX @@
259
#include "qemu-common.h"
260
#include "cpu.h"
261
#include "hw/sysbus.h"
262
-#include "hw/arm/arm.h"
263
+#include "hw/arm/boot.h"
264
#include "hw/loader.h"
265
#include "elf.h"
266
#include "sysemu/qtest.h"
267
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
268
index XXXXXXX..XXXXXXX 100644
269
--- a/hw/arm/aspeed.c
270
+++ b/hw/arm/aspeed.c
271
@@ -XXX,XX +XXX,XX @@
272
#include "qemu-common.h"
273
#include "cpu.h"
274
#include "exec/address-spaces.h"
275
-#include "hw/arm/arm.h"
276
+#include "hw/arm/boot.h"
277
#include "hw/arm/aspeed.h"
278
#include "hw/arm/aspeed_soc.h"
279
#include "hw/boards.h"
280
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
281
index XXXXXXX..XXXXXXX 100644
282
--- a/hw/arm/boot.c
283
+++ b/hw/arm/boot.c
284
@@ -XXX,XX +XXX,XX @@
285
#include "qapi/error.h"
286
#include <libfdt.h>
287
#include "hw/hw.h"
288
-#include "hw/arm/arm.h"
289
+#include "hw/arm/boot.h"
290
#include "hw/arm/linux-boot-if.h"
291
#include "sysemu/kvm.h"
292
#include "sysemu/sysemu.h"
293
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
294
index XXXXXXX..XXXXXXX 100644
295
--- a/hw/arm/collie.c
296
+++ b/hw/arm/collie.c
297
@@ -XXX,XX +XXX,XX @@
298
#include "hw/sysbus.h"
299
#include "hw/boards.h"
300
#include "strongarm.h"
301
-#include "hw/arm/arm.h"
302
+#include "hw/arm/boot.h"
303
#include "hw/block/flash.h"
304
#include "exec/address-spaces.h"
305
#include "cpu.h"
306
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
307
index XXXXXXX..XXXXXXX 100644
308
--- a/hw/arm/exynos4210.c
309
+++ b/hw/arm/exynos4210.c
310
@@ -XXX,XX +XXX,XX @@
311
#include "hw/boards.h"
312
#include "sysemu/sysemu.h"
313
#include "hw/sysbus.h"
314
-#include "hw/arm/arm.h"
315
+#include "hw/arm/boot.h"
316
#include "hw/loader.h"
317
#include "hw/arm/exynos4210.h"
318
#include "hw/sd/sdhci.h"
319
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
320
index XXXXXXX..XXXXXXX 100644
321
--- a/hw/arm/exynos4_boards.c
322
+++ b/hw/arm/exynos4_boards.c
323
@@ -XXX,XX +XXX,XX @@
324
#include "sysemu/sysemu.h"
325
#include "hw/sysbus.h"
326
#include "net/net.h"
327
-#include "hw/arm/arm.h"
328
+#include "hw/arm/boot.h"
329
#include "exec/address-spaces.h"
330
#include "hw/arm/exynos4210.h"
331
#include "hw/net/lan9118.h"
332
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
333
index XXXXXXX..XXXXXXX 100644
334
--- a/hw/arm/highbank.c
335
+++ b/hw/arm/highbank.c
336
@@ -XXX,XX +XXX,XX @@
337
#include "qemu/osdep.h"
338
#include "qapi/error.h"
339
#include "hw/sysbus.h"
340
-#include "hw/arm/arm.h"
341
+#include "hw/arm/boot.h"
342
#include "hw/loader.h"
343
#include "net/net.h"
344
#include "sysemu/kvm.h"
345
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
346
index XXXXXXX..XXXXXXX 100644
347
--- a/hw/arm/integratorcp.c
348
+++ b/hw/arm/integratorcp.c
349
@@ -XXX,XX +XXX,XX @@
350
#include "cpu.h"
351
#include "hw/sysbus.h"
352
#include "hw/boards.h"
353
-#include "hw/arm/arm.h"
354
+#include "hw/arm/boot.h"
355
#include "hw/misc/arm_integrator_debug.h"
356
#include "hw/net/smc91c111.h"
357
#include "net/net.h"
358
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
359
index XXXXXXX..XXXXXXX 100644
360
--- a/hw/arm/mainstone.c
361
+++ b/hw/arm/mainstone.c
362
@@ -XXX,XX +XXX,XX @@
363
#include "qapi/error.h"
364
#include "hw/hw.h"
365
#include "hw/arm/pxa.h"
366
-#include "hw/arm/arm.h"
367
+#include "hw/arm/boot.h"
368
#include "net/net.h"
369
#include "hw/net/smc91c111.h"
370
#include "hw/boards.h"
371
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
372
index XXXXXXX..XXXXXXX 100644
373
--- a/hw/arm/microbit.c
374
+++ b/hw/arm/microbit.c
375
@@ -XXX,XX +XXX,XX @@
376
#include "qemu/osdep.h"
377
#include "qapi/error.h"
378
#include "hw/boards.h"
379
-#include "hw/arm/arm.h"
380
+#include "hw/arm/boot.h"
381
#include "sysemu/sysemu.h"
382
#include "exec/address-spaces.h"
383
384
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
385
index XXXXXXX..XXXXXXX 100644
386
--- a/hw/arm/mps2-tz.c
387
+++ b/hw/arm/mps2-tz.c
388
@@ -XXX,XX +XXX,XX @@
389
#include "qemu/osdep.h"
390
#include "qapi/error.h"
391
#include "qemu/error-report.h"
392
-#include "hw/arm/arm.h"
393
+#include "hw/arm/boot.h"
394
#include "hw/arm/armv7m.h"
395
#include "hw/or-irq.h"
396
#include "hw/boards.h"
397
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
398
index XXXXXXX..XXXXXXX 100644
399
--- a/hw/arm/mps2.c
400
+++ b/hw/arm/mps2.c
401
@@ -XXX,XX +XXX,XX @@
402
#include "qemu/osdep.h"
403
#include "qapi/error.h"
404
#include "qemu/error-report.h"
405
-#include "hw/arm/arm.h"
406
+#include "hw/arm/boot.h"
407
#include "hw/arm/armv7m.h"
408
#include "hw/or-irq.h"
409
#include "hw/boards.h"
410
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
411
index XXXXXXX..XXXXXXX 100644
412
--- a/hw/arm/msf2-soc.c
413
+++ b/hw/arm/msf2-soc.c
414
@@ -XXX,XX +XXX,XX @@
415
#include "qemu/units.h"
416
#include "qapi/error.h"
417
#include "qemu-common.h"
418
-#include "hw/arm/arm.h"
419
#include "exec/address-spaces.h"
420
#include "hw/char/serial.h"
421
#include "hw/boards.h"
422
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
423
index XXXXXXX..XXXXXXX 100644
424
--- a/hw/arm/msf2-som.c
425
+++ b/hw/arm/msf2-som.c
426
@@ -XXX,XX +XXX,XX @@
427
#include "qapi/error.h"
428
#include "qemu/error-report.h"
429
#include "hw/boards.h"
430
-#include "hw/arm/arm.h"
431
+#include "hw/arm/boot.h"
432
#include "exec/address-spaces.h"
433
#include "hw/arm/msf2-soc.h"
434
#include "cpu.h"
435
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
436
index XXXXXXX..XXXXXXX 100644
437
--- a/hw/arm/musca.c
438
+++ b/hw/arm/musca.c
439
@@ -XXX,XX +XXX,XX @@
440
#include "qapi/error.h"
441
#include "exec/address-spaces.h"
442
#include "sysemu/sysemu.h"
443
-#include "hw/arm/arm.h"
444
+#include "hw/arm/boot.h"
445
#include "hw/arm/armsse.h"
446
#include "hw/boards.h"
447
#include "hw/char/pl011.h"
448
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
449
index XXXXXXX..XXXXXXX 100644
450
--- a/hw/arm/musicpal.c
451
+++ b/hw/arm/musicpal.c
452
@@ -XXX,XX +XXX,XX @@
453
#include "qemu-common.h"
454
#include "cpu.h"
455
#include "hw/sysbus.h"
456
-#include "hw/arm/arm.h"
457
+#include "hw/arm/boot.h"
458
#include "net/net.h"
459
#include "sysemu/sysemu.h"
460
#include "hw/boards.h"
461
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
462
index XXXXXXX..XXXXXXX 100644
463
--- a/hw/arm/netduino2.c
464
+++ b/hw/arm/netduino2.c
465
@@ -XXX,XX +XXX,XX @@
466
#include "hw/boards.h"
467
#include "qemu/error-report.h"
468
#include "hw/arm/stm32f205_soc.h"
469
-#include "hw/arm/arm.h"
470
+#include "hw/arm/boot.h"
471
472
static void netduino2_init(MachineState *machine)
473
{
474
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
475
index XXXXXXX..XXXXXXX 100644
476
--- a/hw/arm/nrf51_soc.c
477
+++ b/hw/arm/nrf51_soc.c
478
@@ -XXX,XX +XXX,XX @@
479
#include "qemu/osdep.h"
480
#include "qapi/error.h"
481
#include "qemu-common.h"
482
-#include "hw/arm/arm.h"
483
+#include "hw/arm/boot.h"
484
#include "hw/sysbus.h"
485
#include "hw/boards.h"
486
#include "hw/misc/unimp.h"
487
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
488
index XXXXXXX..XXXXXXX 100644
489
--- a/hw/arm/nseries.c
490
+++ b/hw/arm/nseries.c
491
@@ -XXX,XX +XXX,XX @@
492
#include "qemu/bswap.h"
493
#include "sysemu/sysemu.h"
494
#include "hw/arm/omap.h"
495
-#include "hw/arm/arm.h"
496
+#include "hw/arm/boot.h"
497
#include "hw/irq.h"
498
#include "ui/console.h"
499
#include "hw/boards.h"
500
diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
501
index XXXXXXX..XXXXXXX 100644
502
--- a/hw/arm/omap1.c
503
+++ b/hw/arm/omap1.c
504
@@ -XXX,XX +XXX,XX @@
505
#include "cpu.h"
506
#include "hw/boards.h"
507
#include "hw/hw.h"
508
-#include "hw/arm/arm.h"
509
+#include "hw/arm/boot.h"
510
#include "hw/arm/omap.h"
511
#include "sysemu/sysemu.h"
512
#include "hw/arm/soc_dma.h"
513
diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
514
index XXXXXXX..XXXXXXX 100644
515
--- a/hw/arm/omap2.c
516
+++ b/hw/arm/omap2.c
517
@@ -XXX,XX +XXX,XX @@
518
#include "sysemu/qtest.h"
519
#include "hw/boards.h"
520
#include "hw/hw.h"
521
-#include "hw/arm/arm.h"
522
+#include "hw/arm/boot.h"
523
#include "hw/arm/omap.h"
524
#include "sysemu/sysemu.h"
525
#include "qemu/timer.h"
526
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
527
index XXXXXXX..XXXXXXX 100644
528
--- a/hw/arm/omap_sx1.c
529
+++ b/hw/arm/omap_sx1.c
530
@@ -XXX,XX +XXX,XX @@
531
#include "ui/console.h"
532
#include "hw/arm/omap.h"
533
#include "hw/boards.h"
534
-#include "hw/arm/arm.h"
535
+#include "hw/arm/boot.h"
536
#include "hw/block/flash.h"
537
#include "sysemu/qtest.h"
538
#include "exec/address-spaces.h"
539
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
540
index XXXXXXX..XXXXXXX 100644
541
--- a/hw/arm/palm.c
542
+++ b/hw/arm/palm.c
543
@@ -XXX,XX +XXX,XX @@
544
#include "ui/console.h"
545
#include "hw/arm/omap.h"
546
#include "hw/boards.h"
547
-#include "hw/arm/arm.h"
548
+#include "hw/arm/boot.h"
549
#include "hw/input/tsc2xxx.h"
550
#include "hw/loader.h"
551
#include "exec/address-spaces.h"
552
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
553
index XXXXXXX..XXXXXXX 100644
554
--- a/hw/arm/raspi.c
555
+++ b/hw/arm/raspi.c
556
@@ -XXX,XX +XXX,XX @@
557
#include "qemu/error-report.h"
558
#include "hw/boards.h"
559
#include "hw/loader.h"
560
-#include "hw/arm/arm.h"
561
+#include "hw/arm/boot.h"
562
#include "sysemu/sysemu.h"
563
564
#define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS */
565
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
566
index XXXXXXX..XXXXXXX 100644
567
--- a/hw/arm/realview.c
568
+++ b/hw/arm/realview.c
569
@@ -XXX,XX +XXX,XX @@
570
#include "qemu-common.h"
571
#include "cpu.h"
572
#include "hw/sysbus.h"
573
-#include "hw/arm/arm.h"
574
+#include "hw/arm/boot.h"
575
#include "hw/arm/primecell.h"
576
#include "hw/net/lan9118.h"
577
#include "hw/net/smc91c111.h"
578
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
579
index XXXXXXX..XXXXXXX 100644
580
--- a/hw/arm/spitz.c
581
+++ b/hw/arm/spitz.c
582
@@ -XXX,XX +XXX,XX @@
583
#include "qapi/error.h"
584
#include "hw/hw.h"
585
#include "hw/arm/pxa.h"
586
-#include "hw/arm/arm.h"
587
+#include "hw/arm/boot.h"
588
#include "sysemu/sysemu.h"
589
#include "hw/pcmcia.h"
590
#include "hw/i2c/i2c.h"
591
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
592
index XXXXXXX..XXXXXXX 100644
593
--- a/hw/arm/stellaris.c
594
+++ b/hw/arm/stellaris.c
595
@@ -XXX,XX +XXX,XX @@
596
#include "qapi/error.h"
597
#include "hw/sysbus.h"
598
#include "hw/ssi/ssi.h"
599
-#include "hw/arm/arm.h"
600
+#include "hw/arm/boot.h"
601
#include "qemu/timer.h"
602
#include "hw/i2c/i2c.h"
603
#include "net/net.h"
604
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
605
index XXXXXXX..XXXXXXX 100644
606
--- a/hw/arm/stm32f205_soc.c
607
+++ b/hw/arm/stm32f205_soc.c
608
@@ -XXX,XX +XXX,XX @@
609
#include "qemu/osdep.h"
610
#include "qapi/error.h"
611
#include "qemu-common.h"
612
-#include "hw/arm/arm.h"
613
+#include "hw/arm/boot.h"
614
#include "exec/address-spaces.h"
615
#include "hw/arm/stm32f205_soc.h"
616
617
diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
618
index XXXXXXX..XXXXXXX 100644
619
--- a/hw/arm/strongarm.c
620
+++ b/hw/arm/strongarm.c
621
@@ -XXX,XX +XXX,XX @@
622
#include "hw/sysbus.h"
623
#include "strongarm.h"
624
#include "qemu/error-report.h"
625
-#include "hw/arm/arm.h"
626
+#include "hw/arm/boot.h"
627
#include "chardev/char-fe.h"
628
#include "chardev/char-serial.h"
629
#include "sysemu/sysemu.h"
630
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
631
index XXXXXXX..XXXXXXX 100644
632
--- a/hw/arm/tosa.c
633
+++ b/hw/arm/tosa.c
634
@@ -XXX,XX +XXX,XX @@
635
#include "qapi/error.h"
636
#include "hw/hw.h"
637
#include "hw/arm/pxa.h"
638
-#include "hw/arm/arm.h"
639
+#include "hw/arm/boot.h"
640
#include "hw/arm/sharpsl.h"
641
#include "hw/pcmcia.h"
642
#include "hw/boards.h"
643
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
644
index XXXXXXX..XXXXXXX 100644
645
--- a/hw/arm/versatilepb.c
646
+++ b/hw/arm/versatilepb.c
647
@@ -XXX,XX +XXX,XX @@
648
#include "qemu-common.h"
649
#include "cpu.h"
650
#include "hw/sysbus.h"
651
-#include "hw/arm/arm.h"
652
+#include "hw/arm/boot.h"
653
#include "hw/net/smc91c111.h"
654
#include "net/net.h"
655
#include "sysemu/sysemu.h"
656
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
657
index XXXXXXX..XXXXXXX 100644
658
--- a/hw/arm/vexpress.c
659
+++ b/hw/arm/vexpress.c
660
@@ -XXX,XX +XXX,XX @@
661
#include "qemu-common.h"
662
#include "cpu.h"
663
#include "hw/sysbus.h"
664
-#include "hw/arm/arm.h"
665
+#include "hw/arm/boot.h"
666
#include "hw/arm/primecell.h"
667
#include "hw/net/lan9118.h"
668
#include "hw/i2c/i2c.h"
669
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
670
index XXXXXXX..XXXXXXX 100644
671
--- a/hw/arm/virt.c
672
+++ b/hw/arm/virt.c
673
@@ -XXX,XX +XXX,XX @@
674
#include "qemu/option.h"
675
#include "qapi/error.h"
676
#include "hw/sysbus.h"
677
-#include "hw/arm/arm.h"
678
+#include "hw/arm/boot.h"
679
#include "hw/arm/primecell.h"
680
#include "hw/arm/virt.h"
681
#include "hw/block/flash.h"
682
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
683
index XXXXXXX..XXXXXXX 100644
684
--- a/hw/arm/xilinx_zynq.c
685
+++ b/hw/arm/xilinx_zynq.c
686
@@ -XXX,XX +XXX,XX @@
687
#include "qemu-common.h"
688
#include "cpu.h"
689
#include "hw/sysbus.h"
690
-#include "hw/arm/arm.h"
691
+#include "hw/arm/boot.h"
692
#include "net/net.h"
693
#include "exec/address-spaces.h"
694
#include "sysemu/sysemu.h"
695
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
696
index XXXXXXX..XXXXXXX 100644
697
--- a/hw/arm/xlnx-versal.c
698
+++ b/hw/arm/xlnx-versal.c
699
@@ -XXX,XX +XXX,XX @@
700
#include "net/net.h"
701
#include "sysemu/sysemu.h"
702
#include "sysemu/kvm.h"
703
-#include "hw/arm/arm.h"
704
+#include "hw/arm/boot.h"
705
#include "kvm_arm.h"
706
#include "hw/misc/unimp.h"
707
#include "hw/intc/arm_gicv3_common.h"
708
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
709
index XXXXXXX..XXXXXXX 100644
710
--- a/hw/arm/z2.c
711
+++ b/hw/arm/z2.c
712
@@ -XXX,XX +XXX,XX @@
713
#include "qemu/osdep.h"
714
#include "hw/hw.h"
715
#include "hw/arm/pxa.h"
716
-#include "hw/arm/arm.h"
717
+#include "hw/arm/boot.h"
718
#include "hw/i2c/i2c.h"
719
#include "hw/ssi/ssi.h"
720
#include "hw/boards.h"
721
--
722
2.20.1
723
724
diff view generated by jsdifflib
Deleted patch
1
In ich_vmcr_write() we enforce "writes of BPR fields to less than
2
their minimum sets them to the minimum" by doing a "read vbpr and
3
write it back" operation. A typo here meant that we weren't handling
4
writes to these fields correctly, because we were reading from VBPR0
5
but writing to VBPR1.
6
1
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20190520162809.2677-4-peter.maydell@linaro.org
10
---
11
hw/intc/arm_gicv3_cpuif.c | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
13
14
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/intc/arm_gicv3_cpuif.c
17
+++ b/hw/intc/arm_gicv3_cpuif.c
18
@@ -XXX,XX +XXX,XX @@ static void ich_vmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
19
/* Enforce "writing BPRs to less than minimum sets them to the minimum"
20
* by reading and writing back the fields.
21
*/
22
- write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G0));
23
+ write_vbpr(cs, GICV3_G0, read_vbpr(cs, GICV3_G0));
24
write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G1));
25
26
gicv3_cpuif_virt_update(cs);
27
--
28
2.20.1
29
30
diff view generated by jsdifflib
Deleted patch
1
The ICC_CTLR_EL3 register includes some bits which are aliases
2
of bits in the ICC_CTLR_EL1(S) and (NS) registers. QEMU chooses
3
to keep those bits in the cs->icc_ctlr_el1[] struct fields.
4
Unfortunately a missing '~' in the code to update the bits
5
in those fields meant that writing to ICC_CTLR_EL3 would corrupt
6
the ICC_CLTR_EL1 register values.
7
1
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Message-id: 20190520162809.2677-5-peter.maydell@linaro.org
11
---
12
hw/intc/arm_gicv3_cpuif.c | 4 ++--
13
1 file changed, 2 insertions(+), 2 deletions(-)
14
15
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/intc/arm_gicv3_cpuif.c
18
+++ b/hw/intc/arm_gicv3_cpuif.c
19
@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
20
trace_gicv3_icc_ctlr_el3_write(gicv3_redist_affid(cs), value);
21
22
/* *_EL1NS and *_EL1S bits are aliases into the ICC_CTLR_EL1 bits. */
23
- cs->icc_ctlr_el1[GICV3_NS] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
24
+ cs->icc_ctlr_el1[GICV3_NS] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
25
if (value & ICC_CTLR_EL3_EOIMODE_EL1NS) {
26
cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE;
27
}
28
@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
29
cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_CBPR;
30
}
31
32
- cs->icc_ctlr_el1[GICV3_S] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
33
+ cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
34
if (value & ICC_CTLR_EL3_EOIMODE_EL1S) {
35
cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_EOIMODE;
36
}
37
--
38
2.20.1
39
40
diff view generated by jsdifflib
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
3
Simply moving the non-stub helper_v7m_mrs/msr outside of
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
4
!CONFIG_USER_ONLY is not an option, because of all of the
5
Message-id: 20190520214342.13709-5-philmd@redhat.com
5
other system-mode helpers that are called.
6
7
But we can split out a few subroutines to handle the few
8
EL0 accessible registers without duplicating code.
9
10
Reported-by: Christophe Lyon <christophe.lyon@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20191118194916.3670-1-richard.henderson@linaro.org
13
[PMM: deleted now-redundant comment; added a default case
14
to switch in v7m_msr helper]
15
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
17
---
8
include/hw/arm/exynos4210.h | 9 +++++++--
18
target/arm/cpu.h | 2 +
9
hw/arm/exynos4210.c | 28 ++++++++++++++++++++++++----
19
target/arm/m_helper.c | 114 ++++++++++++++++++++++++++----------------
10
hw/arm/exynos4_boards.c | 9 ++++++---
20
2 files changed, 73 insertions(+), 43 deletions(-)
11
3 files changed, 37 insertions(+), 9 deletions(-)
12
21
13
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
22
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
15
--- a/include/hw/arm/exynos4210.h
24
--- a/target/arm/cpu.h
16
+++ b/include/hw/arm/exynos4210.h
25
+++ b/target/arm/cpu.h
17
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210Irq {
26
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
18
} Exynos4210Irq;
27
if (mask & XPSR_GE) {
19
28
env->GE = (val & XPSR_GE) >> 16;
20
typedef struct Exynos4210State {
29
}
21
+ /*< private >*/
30
+#ifndef CONFIG_USER_ONLY
22
+ SysBusDevice parent_obj;
31
if (mask & XPSR_T) {
23
+ /*< public >*/
32
env->thumb = ((val & XPSR_T) != 0);
24
ARMCPU *cpu[EXYNOS4210_NCPUS];
33
}
25
Exynos4210Irq irqs;
34
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
26
qemu_irq *irq_table;
35
/* Note that this only happens on exception exit */
27
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210State {
36
write_v7m_exception(env, val & XPSR_EXCP);
28
I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
37
}
29
} Exynos4210State;
38
+#endif
30
39
}
31
+#define TYPE_EXYNOS4210_SOC "exynos4210"
40
32
+#define EXYNOS4210_SOC(obj) \
41
#define HCR_VM (1ULL << 0)
33
+ OBJECT_CHECK(Exynos4210State, obj, TYPE_EXYNOS4210_SOC)
42
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/target/arm/m_helper.c
45
+++ b/target/arm/m_helper.c
46
@@ -XXX,XX +XXX,XX @@
47
#include "exec/cpu_ldst.h"
48
#endif
49
50
+static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask,
51
+ uint32_t reg, uint32_t val)
52
+{
53
+ /* Only APSR is actually writable */
54
+ if (!(reg & 4)) {
55
+ uint32_t apsrmask = 0;
34
+
56
+
35
void exynos4210_write_secondary(ARMCPU *cpu,
57
+ if (mask & 8) {
36
const struct arm_boot_info *info);
58
+ apsrmask |= XPSR_NZCV | XPSR_Q;
37
59
+ }
38
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem);
60
+ if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) {
39
-
61
+ apsrmask |= XPSR_GE;
40
/* Initialize exynos4210 IRQ subsystem stub */
62
+ }
41
qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
63
+ xpsr_write(env, val, apsrmask);
42
64
+ }
43
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/hw/arm/exynos4210.c
46
+++ b/hw/arm/exynos4210.c
47
@@ -XXX,XX +XXX,XX @@ static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
48
sysbus_connect_irq(busdev, 0, irq);
49
}
50
51
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
52
+static void exynos4210_realize(DeviceState *socdev, Error **errp)
53
{
54
- Exynos4210State *s = g_new0(Exynos4210State, 1);
55
+ Exynos4210State *s = EXYNOS4210_SOC(socdev);
56
+ MemoryRegion *system_mem = get_system_memory();
57
qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
58
SysBusDevice *busdev;
59
DeviceState *dev;
60
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
61
qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
62
pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
63
qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
64
-
65
- return s;
66
}
67
+
68
+static void exynos4210_class_init(ObjectClass *klass, void *data)
69
+{
70
+ DeviceClass *dc = DEVICE_CLASS(klass);
71
+
72
+ dc->realize = exynos4210_realize;
73
+}
65
+}
74
+
66
+
75
+static const TypeInfo exynos4210_info = {
67
+static uint32_t v7m_mrs_xpsr(CPUARMState *env, uint32_t reg, unsigned el)
76
+ .name = TYPE_EXYNOS4210_SOC,
68
+{
77
+ .parent = TYPE_SYS_BUS_DEVICE,
69
+ uint32_t mask = 0;
78
+ .instance_size = sizeof(Exynos4210State),
79
+ .class_init = exynos4210_class_init,
80
+};
81
+
70
+
82
+static void exynos4210_register_types(void)
71
+ if ((reg & 1) && el) {
83
+{
72
+ mask |= XPSR_EXCP; /* IPSR (unpriv. reads as zero) */
84
+ type_register_static(&exynos4210_info);
73
+ }
74
+ if (!(reg & 4)) {
75
+ mask |= XPSR_NZCV | XPSR_Q; /* APSR */
76
+ if (arm_feature(env, ARM_FEATURE_THUMB_DSP)) {
77
+ mask |= XPSR_GE;
78
+ }
79
+ }
80
+ /* EPSR reads as zero */
81
+ return xpsr_read(env) & mask;
85
+}
82
+}
86
+
83
+
87
+type_init(exynos4210_register_types)
84
+static uint32_t v7m_mrs_control(CPUARMState *env, uint32_t secure)
88
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
85
+{
89
index XXXXXXX..XXXXXXX 100644
86
+ uint32_t value = env->v7m.control[secure];
90
--- a/hw/arm/exynos4_boards.c
87
+
91
+++ b/hw/arm/exynos4_boards.c
88
+ if (!secure) {
92
@@ -XXX,XX +XXX,XX @@ typedef enum Exynos4BoardType {
89
+ /* SFPA is RAZ/WI from NS; FPCA is stored in the M_REG_S bank */
93
} Exynos4BoardType;
90
+ value |= env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK;
94
91
+ }
95
typedef struct Exynos4BoardState {
92
+ return value;
96
- Exynos4210State *soc;
93
+}
97
+ Exynos4210State soc;
94
+
98
MemoryRegion dram0_mem;
95
#ifdef CONFIG_USER_ONLY
99
MemoryRegion dram1_mem;
96
100
} Exynos4BoardState;
97
-/* These should probably raise undefined insn exceptions. */
101
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
98
-void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
102
exynos4_boards_init_ram(s, get_system_memory(),
99
+void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
103
exynos4_board_ram_size[board_type]);
100
{
104
101
- ARMCPU *cpu = env_archcpu(env);
105
- s->soc = exynos4210_init(get_system_memory());
102
+ uint32_t mask = extract32(maskreg, 8, 4);
106
+ object_initialize(&s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC);
103
+ uint32_t reg = extract32(maskreg, 0, 8);
107
+ qdev_set_parent_bus(DEVICE(&s->soc), sysbus_get_default());
104
108
+ object_property_set_bool(OBJECT(&s->soc), true, "realized",
105
- cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
109
+ &error_fatal);
106
+ switch (reg) {
110
107
+ case 0 ... 7: /* xPSR sub-fields */
111
return s;
108
+ v7m_msr_xpsr(env, mask, reg, val);
109
+ break;
110
+ case 20: /* CONTROL */
111
+ /* There are no sub-fields that are actually writable from EL0. */
112
+ break;
113
+ default:
114
+ /* Unprivileged writes to other registers are ignored */
115
+ break;
116
+ }
112
}
117
}
113
@@ -XXX,XX +XXX,XX @@ static void smdkc210_init(MachineState *machine)
118
114
EXYNOS4_BOARD_SMDKC210);
119
uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
115
120
{
116
lan9215_init(SMDK_LAN9118_BASE_ADDR,
121
- ARMCPU *cpu = env_archcpu(env);
117
- qemu_irq_invert(s->soc->irq_table[exynos4210_get_irq(37, 1)]));
122
-
118
+ qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)]));
123
- cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
119
arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo);
124
- return 0;
125
+ switch (reg) {
126
+ case 0 ... 7: /* xPSR sub-fields */
127
+ return v7m_mrs_xpsr(env, reg, 0);
128
+ case 20: /* CONTROL */
129
+ return v7m_mrs_control(env, 0);
130
+ default:
131
+ /* Unprivileged reads others as zero. */
132
+ return 0;
133
+ }
120
}
134
}
121
135
136
void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest)
137
@@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
138
139
uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
140
{
141
- uint32_t mask;
142
unsigned el = arm_current_el(env);
143
144
/* First handle registers which unprivileged can read */
145
-
146
switch (reg) {
147
case 0 ... 7: /* xPSR sub-fields */
148
- mask = 0;
149
- if ((reg & 1) && el) {
150
- mask |= XPSR_EXCP; /* IPSR (unpriv. reads as zero) */
151
- }
152
- if (!(reg & 4)) {
153
- mask |= XPSR_NZCV | XPSR_Q; /* APSR */
154
- if (arm_feature(env, ARM_FEATURE_THUMB_DSP)) {
155
- mask |= XPSR_GE;
156
- }
157
- }
158
- /* EPSR reads as zero */
159
- return xpsr_read(env) & mask;
160
- break;
161
+ return v7m_mrs_xpsr(env, reg, el);
162
case 20: /* CONTROL */
163
- {
164
- uint32_t value = env->v7m.control[env->v7m.secure];
165
- if (!env->v7m.secure) {
166
- /* SFPA is RAZ/WI from NS; FPCA is stored in the M_REG_S bank */
167
- value |= env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK;
168
- }
169
- return value;
170
- }
171
+ return v7m_mrs_control(env, env->v7m.secure);
172
case 0x94: /* CONTROL_NS */
173
/*
174
* We have to handle this here because unprivileged Secure code
175
@@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val)
176
177
switch (reg) {
178
case 0 ... 7: /* xPSR sub-fields */
179
- /* only APSR is actually writable */
180
- if (!(reg & 4)) {
181
- uint32_t apsrmask = 0;
182
-
183
- if (mask & 8) {
184
- apsrmask |= XPSR_NZCV | XPSR_Q;
185
- }
186
- if ((mask & 4) && arm_feature(env, ARM_FEATURE_THUMB_DSP)) {
187
- apsrmask |= XPSR_GE;
188
- }
189
- xpsr_write(env, val, apsrmask);
190
- }
191
+ v7m_msr_xpsr(env, mask, reg, val);
192
break;
193
case 8: /* MSP */
194
if (v7m_using_psp(env)) {
122
--
195
--
123
2.20.1
196
2.20.1
124
197
125
198
diff view generated by jsdifflib