1 | Not very much here, but several people have fallen over | 1 | target-arm queue: nothing major here, but no point |
---|---|---|---|
2 | the vector operation segfault bug, so let's get the fix | 2 | sitting on them waiting for more stuff to come along. |
3 | into master. | ||
4 | 3 | ||
5 | thanks | 4 | thanks |
6 | -- PMM | 5 | -- PMM |
7 | 6 | ||
8 | The following changes since commit d418238dca7b4e0b124135827ead3076233052b1: | 7 | The following changes since commit 1329132d28bf14b9508f7a1f04a2c63422bc3f99: |
9 | 8 | ||
10 | Merge remote-tracking branch 'remotes/rth/tags/pull-rng-20190522' into staging (2019-05-23 12:57:17 +0100) | 9 | Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2019-09-26 16:14:03 +0100) |
11 | 10 | ||
12 | are available in the Git repository at: | 11 | are available in the Git repository at: |
13 | 12 | ||
14 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190523 | 13 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190927 |
15 | 14 | ||
16 | for you to fetch changes up to 98e4f4fdb8ea05d840f51f47125924c2bb9df2df: | 15 | for you to fetch changes up to e4e34855e658b78ecac50a651cc847662ff02cfd: |
17 | 16 | ||
18 | hw/arm/exynos4210: QOM'ify the Exynos4210 SoC (2019-05-23 14:47:44 +0100) | 17 | hw/arm/boot: Use the IEC binary prefix definitions (2019-09-27 11:44:39 +0100) |
19 | 18 | ||
20 | ---------------------------------------------------------------- | 19 | ---------------------------------------------------------------- |
21 | target-arm queue: | 20 | target-arm queue: |
22 | * exynos4210: QOM'ify the Exynos4210 SoC | 21 | * Fix the CBAR register implementation for Cortex-A53, |
23 | * exynos4210: Add DMA support for the Exynos4210 | 22 | Cortex-A57, Cortex-A72 |
24 | * arm_gicv3: Fix writes to ICC_CTLR_EL3 | 23 | * Fix direct booting of Linux kernels on emulated CPUs |
25 | * arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1} | 24 | which have an AArch32 EL3 (incorrect NSACR settings |
26 | * target/arm: Fix vector operation segfault | 25 | meant they could not access the FPU) |
27 | * target/arm: Minor improvements to BFXIL, EXTR | 26 | * semihosting cleanup: do more work at translate time |
27 | and less work at runtime | ||
28 | 28 | ||
29 | ---------------------------------------------------------------- | 29 | ---------------------------------------------------------------- |
30 | Alistair Francis (1): | 30 | Alex Bennée (6): |
31 | target/arm: Fix vector operation segfault | 31 | tests/tcg: clean-up some comments after the de-tangling |
32 | target/arm: handle M-profile semihosting at translate time | ||
33 | target/arm: handle A-profile semihosting at translate time | ||
34 | target/arm: remove run time semihosting checks | ||
35 | target/arm: remove run-time semihosting checks for linux-user | ||
36 | tests/tcg: add linux-user semihosting smoke test for ARM | ||
32 | 37 | ||
33 | Guenter Roeck (1): | 38 | Luc Michel (1): |
34 | hw/arm/exynos4210: Add DMA support for the Exynos4210 | 39 | target/arm: fix CBAR register for AArch64 CPUs |
35 | 40 | ||
36 | Peter Maydell (5): | 41 | Peter Maydell (1): |
37 | arm: Move system_clock_scale to armv7m_systick.h | 42 | hw/arm/boot.c: Set NSACR.{CP11,CP10} for NS kernel boots |
38 | arm: Remove unnecessary includes of hw/arm/arm.h | ||
39 | arm: Rename hw/arm/arm.h to hw/arm/boot.h | ||
40 | hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1} | ||
41 | hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3 | ||
42 | 43 | ||
43 | Philippe Mathieu-Daudé (3): | 44 | Philippe Mathieu-Daudé (1): |
44 | hw/arm/exynos4: Remove unuseful debug code | 45 | hw/arm/boot: Use the IEC binary prefix definitions |
45 | hw/arm/exynos4: Use the IEC binary prefix definitions | ||
46 | hw/arm/exynos4210: QOM'ify the Exynos4210 SoC | ||
47 | 46 | ||
48 | Richard Henderson (2): | 47 | tests/tcg/Makefile.target | 7 ++- |
49 | target/arm: Use extract2 for EXTR | 48 | tests/tcg/aarch64/Makefile.target | 8 ++- |
50 | target/arm: Simplify BFXIL expansion | 49 | tests/tcg/arm/Makefile.target | 20 ++++--- |
50 | linux-user/arm/target_syscall.h | 3 - | ||
51 | hw/arm/boot.c | 12 ++-- | ||
52 | linux-user/arm/cpu_loop.c | 3 - | ||
53 | target/arm/helper.c | 115 +++++++++++++------------------------- | ||
54 | target/arm/m_helper.c | 18 ++---- | ||
55 | target/arm/translate.c | 30 ++++++++-- | ||
56 | tests/tcg/arm/semihosting.c | 45 +++++++++++++++ | ||
57 | 10 files changed, 146 insertions(+), 115 deletions(-) | ||
58 | create mode 100644 tests/tcg/arm/semihosting.c | ||
51 | 59 | ||
52 | include/hw/arm/allwinner-a10.h | 2 +- | ||
53 | include/hw/arm/aspeed_soc.h | 1 - | ||
54 | include/hw/arm/bcm2836.h | 1 - | ||
55 | include/hw/arm/{arm.h => boot.h} | 12 +++------ | ||
56 | include/hw/arm/exynos4210.h | 9 +++++-- | ||
57 | include/hw/arm/fsl-imx25.h | 2 +- | ||
58 | include/hw/arm/fsl-imx31.h | 2 +- | ||
59 | include/hw/arm/fsl-imx6.h | 2 +- | ||
60 | include/hw/arm/fsl-imx6ul.h | 2 +- | ||
61 | include/hw/arm/fsl-imx7.h | 2 +- | ||
62 | include/hw/arm/virt.h | 2 +- | ||
63 | include/hw/arm/xlnx-versal.h | 2 +- | ||
64 | include/hw/arm/xlnx-zynqmp.h | 2 +- | ||
65 | include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++ | ||
66 | hw/arm/armsse.c | 2 +- | ||
67 | hw/arm/armv7m.c | 2 +- | ||
68 | hw/arm/aspeed.c | 2 +- | ||
69 | hw/arm/boot.c | 2 +- | ||
70 | hw/arm/collie.c | 2 +- | ||
71 | hw/arm/exynos4210.c | 54 ++++++++++++++++++++++++++++++++++++--- | ||
72 | hw/arm/exynos4_boards.c | 40 ++++++++--------------------- | ||
73 | hw/arm/highbank.c | 2 +- | ||
74 | hw/arm/integratorcp.c | 2 +- | ||
75 | hw/arm/mainstone.c | 2 +- | ||
76 | hw/arm/microbit.c | 2 +- | ||
77 | hw/arm/mps2-tz.c | 2 +- | ||
78 | hw/arm/mps2.c | 2 +- | ||
79 | hw/arm/msf2-soc.c | 1 - | ||
80 | hw/arm/msf2-som.c | 2 +- | ||
81 | hw/arm/musca.c | 2 +- | ||
82 | hw/arm/musicpal.c | 2 +- | ||
83 | hw/arm/netduino2.c | 2 +- | ||
84 | hw/arm/nrf51_soc.c | 2 +- | ||
85 | hw/arm/nseries.c | 2 +- | ||
86 | hw/arm/omap1.c | 2 +- | ||
87 | hw/arm/omap2.c | 2 +- | ||
88 | hw/arm/omap_sx1.c | 2 +- | ||
89 | hw/arm/palm.c | 2 +- | ||
90 | hw/arm/raspi.c | 2 +- | ||
91 | hw/arm/realview.c | 2 +- | ||
92 | hw/arm/spitz.c | 2 +- | ||
93 | hw/arm/stellaris.c | 2 +- | ||
94 | hw/arm/stm32f205_soc.c | 2 +- | ||
95 | hw/arm/strongarm.c | 2 +- | ||
96 | hw/arm/tosa.c | 2 +- | ||
97 | hw/arm/versatilepb.c | 2 +- | ||
98 | hw/arm/vexpress.c | 2 +- | ||
99 | hw/arm/virt.c | 2 +- | ||
100 | hw/arm/xilinx_zynq.c | 2 +- | ||
101 | hw/arm/xlnx-versal.c | 2 +- | ||
102 | hw/arm/z2.c | 2 +- | ||
103 | hw/intc/arm_gicv3_cpuif.c | 6 ++--- | ||
104 | hw/intc/armv7m_nvic.c | 1 - | ||
105 | target/arm/arm-semi.c | 1 - | ||
106 | target/arm/cpu.c | 1 - | ||
107 | target/arm/cpu64.c | 1 - | ||
108 | target/arm/kvm.c | 1 - | ||
109 | target/arm/kvm32.c | 1 - | ||
110 | target/arm/kvm64.c | 1 - | ||
111 | target/arm/translate-a64.c | 44 ++++++++++++++++--------------- | ||
112 | target/arm/translate.c | 4 +-- | ||
113 | 61 files changed, 164 insertions(+), 123 deletions(-) | ||
114 | rename include/hw/arm/{arm.h => boot.h} (96%) | ||
115 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Luc Michel <luc.michel@greensocs.com> |
---|---|---|---|
2 | 2 | ||
3 | The mask implied by the extract is redundant with the one | 3 | For AArch64 CPUs with a CBAR register, we have two views for it: |
4 | implied by the deposit. Also, fix spelling of BFXIL. | 4 | - in AArch64 state, the CBAR_EL1 register (S3_1_C15_C3_0), returns the |
5 | full 64 bits CBAR value | ||
6 | - in AArch32 state, the CBAR register (cp15, opc1=1, CRn=15, CRm=3, opc2=0) | ||
7 | returns a 32 bits view such that: | ||
8 | CBAR = CBAR_EL1[31:18] 0..0 CBAR_EL1[43:32] | ||
5 | 9 | ||
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 10 | This commit fixes the current implementation where: |
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 11 | - CBAR_EL1 was returning the 32 bits view instead of the full 64 bits |
8 | Message-id: 20190514011129.11330-3-richard.henderson@linaro.org | 12 | value, |
13 | - CBAR was returning a truncated 32 bits version of the full 64 bits | ||
14 | one, instead of the 32 bits view | ||
15 | - CBAR was declared as cp15, opc1=4, CRn=15, CRm=0, opc2=0, which is | ||
16 | the CBAR register found in the ARMv7 Cortex-Ax CPUs, but not in | ||
17 | ARMv8 CPUs. | ||
18 | |||
19 | Signed-off-by: Luc Michel <luc.michel@greensocs.com> | ||
20 | Message-id: 20190912110103.1417887-1-luc.michel@greensocs.com | ||
21 | [PMM: Added a comment about the two different kinds of CBAR] | ||
22 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 23 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 24 | --- |
11 | target/arm/translate-a64.c | 6 +++--- | 25 | target/arm/helper.c | 19 ++++++++++++++++--- |
12 | 1 file changed, 3 insertions(+), 3 deletions(-) | 26 | 1 file changed, 16 insertions(+), 3 deletions(-) |
13 | 27 | ||
14 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 28 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
15 | index XXXXXXX..XXXXXXX 100644 | 29 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/translate-a64.c | 30 | --- a/target/arm/helper.c |
17 | +++ b/target/arm/translate-a64.c | 31 | +++ b/target/arm/helper.c |
18 | @@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn) | 32 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) |
19 | tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len); | ||
20 | return; | ||
21 | } | ||
22 | - /* opc == 1, BXFIL fall through to deposit */ | ||
23 | - tcg_gen_extract_i64(tcg_tmp, tcg_tmp, ri, len); | ||
24 | + /* opc == 1, BFXIL fall through to deposit */ | ||
25 | + tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri); | ||
26 | pos = 0; | ||
27 | } else { | ||
28 | /* Handle the ri > si case with a deposit | ||
29 | @@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn) | ||
30 | len = ri; | ||
31 | } | 33 | } |
32 | 34 | ||
33 | - if (opc == 1) { /* BFM, BXFIL */ | 35 | if (arm_feature(env, ARM_FEATURE_CBAR)) { |
34 | + if (opc == 1) { /* BFM, BFXIL */ | 36 | + /* |
35 | tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len); | 37 | + * CBAR is IMPDEF, but common on Arm Cortex-A implementations. |
36 | } else { | 38 | + * There are two flavours: |
37 | /* SBFM or UBFM: We start with zero, and we haven't modified | 39 | + * (1) older 32-bit only cores have a simple 32-bit CBAR |
40 | + * (2) 64-bit cores have a 64-bit CBAR visible to AArch64, plus a | ||
41 | + * 32-bit register visible to AArch32 at a different encoding | ||
42 | + * to the "flavour 1" register and with the bits rearranged to | ||
43 | + * be able to squash a 64-bit address into the 32-bit view. | ||
44 | + * We distinguish the two via the ARM_FEATURE_AARCH64 flag, but | ||
45 | + * in future if we support AArch32-only configs of some of the | ||
46 | + * AArch64 cores we might need to add a specific feature flag | ||
47 | + * to indicate cores with "flavour 2" CBAR. | ||
48 | + */ | ||
49 | if (arm_feature(env, ARM_FEATURE_AARCH64)) { | ||
50 | /* 32 bit view is [31:18] 0...0 [43:32]. */ | ||
51 | uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) | ||
52 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
53 | ARMCPRegInfo cbar_reginfo[] = { | ||
54 | { .name = "CBAR", | ||
55 | .type = ARM_CP_CONST, | ||
56 | - .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0, | ||
57 | - .access = PL1_R, .resetvalue = cpu->reset_cbar }, | ||
58 | + .cp = 15, .crn = 15, .crm = 3, .opc1 = 1, .opc2 = 0, | ||
59 | + .access = PL1_R, .resetvalue = cbar32 }, | ||
60 | { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64, | ||
61 | .type = ARM_CP_CONST, | ||
62 | .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0, | ||
63 | - .access = PL1_R, .resetvalue = cbar32 }, | ||
64 | + .access = PL1_R, .resetvalue = cpu->reset_cbar }, | ||
65 | REGINFO_SENTINEL | ||
66 | }; | ||
67 | /* We don't implement a r/w 64 bit CBAR currently */ | ||
38 | -- | 68 | -- |
39 | 2.20.1 | 69 | 2.20.1 |
40 | 70 | ||
41 | 71 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | 1 | From: Alex Bennée <alex.bennee@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 3 | These were missed in the recent de-tangling so have been updated to be |
4 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 4 | more actuate. I've also built up ARM_TESTS in a manner similar to |
5 | Message-id: 20190520214342.13709-5-philmd@redhat.com | 5 | AARCH64_TESTS for better consistency. |
6 | |||
7 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Message-id: 20190913151845.12582-2-alex.bennee@linaro.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 11 | --- |
8 | include/hw/arm/exynos4210.h | 9 +++++++-- | 12 | tests/tcg/Makefile.target | 7 +++++-- |
9 | hw/arm/exynos4210.c | 28 ++++++++++++++++++++++++---- | 13 | tests/tcg/aarch64/Makefile.target | 3 ++- |
10 | hw/arm/exynos4_boards.c | 9 ++++++--- | 14 | tests/tcg/arm/Makefile.target | 15 ++++++++------- |
11 | 3 files changed, 37 insertions(+), 9 deletions(-) | 15 | 3 files changed, 15 insertions(+), 10 deletions(-) |
12 | 16 | ||
13 | diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h | 17 | diff --git a/tests/tcg/Makefile.target b/tests/tcg/Makefile.target |
14 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/include/hw/arm/exynos4210.h | 19 | --- a/tests/tcg/Makefile.target |
16 | +++ b/include/hw/arm/exynos4210.h | 20 | +++ b/tests/tcg/Makefile.target |
17 | @@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210Irq { | 21 | @@ -XXX,XX +XXX,XX @@ TIMEOUT=15 |
18 | } Exynos4210Irq; | 22 | endif |
19 | 23 | ||
20 | typedef struct Exynos4210State { | 24 | ifdef CONFIG_USER_ONLY |
21 | + /*< private >*/ | 25 | -# The order we include is important. We include multiarch, base arch |
22 | + SysBusDevice parent_obj; | 26 | -# and finally arch if it's not the same as base arch. |
23 | + /*< public >*/ | 27 | +# The order we include is important. We include multiarch first and |
24 | ARMCPU *cpu[EXYNOS4210_NCPUS]; | 28 | +# then the target. If there are common tests shared between |
25 | Exynos4210Irq irqs; | 29 | +# sub-targets (e.g. ARM & AArch64) then it is up to |
26 | qemu_irq *irq_table; | 30 | +# $(TARGET_NAME)/Makefile.target to include the common parent |
27 | @@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210State { | 31 | +# architecture in its VPATH. |
28 | I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; | 32 | -include $(SRC_PATH)/tests/tcg/multiarch/Makefile.target |
29 | } Exynos4210State; | 33 | -include $(SRC_PATH)/tests/tcg/$(TARGET_NAME)/Makefile.target |
30 | 34 | ||
31 | +#define TYPE_EXYNOS4210_SOC "exynos4210" | 35 | diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target |
32 | +#define EXYNOS4210_SOC(obj) \ | 36 | index XXXXXXX..XXXXXXX 100644 |
33 | + OBJECT_CHECK(Exynos4210State, obj, TYPE_EXYNOS4210_SOC) | 37 | --- a/tests/tcg/aarch64/Makefile.target |
38 | +++ b/tests/tcg/aarch64/Makefile.target | ||
39 | @@ -XXX,XX +XXX,XX @@ VPATH += $(ARM_SRC) | ||
40 | AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64 | ||
41 | VPATH += $(AARCH64_SRC) | ||
42 | |||
43 | -# we don't build any other ARM test | ||
44 | +# Float-convert Tests | ||
45 | AARCH64_TESTS=fcvt | ||
46 | |||
47 | fcvt: LDFLAGS+=-lm | ||
48 | @@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt | ||
49 | $(call run-test,$<,$(QEMU) $<, "$< on $(TARGET_NAME)") | ||
50 | $(call diff-out,$<,$(AARCH64_SRC)/fcvt.ref) | ||
51 | |||
52 | +# Pauth Tests | ||
53 | AARCH64_TESTS += pauth-1 pauth-2 | ||
54 | run-pauth-%: QEMU_OPTS += -cpu max | ||
55 | |||
56 | diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target | ||
57 | index XXXXXXX..XXXXXXX 100644 | ||
58 | --- a/tests/tcg/arm/Makefile.target | ||
59 | +++ b/tests/tcg/arm/Makefile.target | ||
60 | @@ -XXX,XX +XXX,XX @@ ARM_SRC=$(SRC_PATH)/tests/tcg/arm | ||
61 | # Set search path for all sources | ||
62 | VPATH += $(ARM_SRC) | ||
63 | |||
64 | -ARM_TESTS=hello-arm test-arm-iwmmxt | ||
65 | - | ||
66 | -TESTS += $(ARM_TESTS) fcvt | ||
67 | - | ||
68 | +# Basic Hello World | ||
69 | +ARM_TESTS = hello-arm | ||
70 | hello-arm: CFLAGS+=-marm -ffreestanding | ||
71 | hello-arm: LDFLAGS+=-nostdlib | ||
72 | |||
73 | +# IWMXT floating point extensions | ||
74 | +ARM_TESTS += test-arm-iwmmxt | ||
75 | test-arm-iwmmxt: CFLAGS+=-marm -march=iwmmxt -mabi=aapcs -mfpu=fpv4-sp-d16 | ||
76 | test-arm-iwmmxt: test-arm-iwmmxt.S | ||
77 | $(CC) $(CFLAGS) $< -o $@ $(LDFLAGS) | ||
78 | |||
79 | -ifeq ($(TARGET_NAME), arm) | ||
80 | +# Float-convert Tests | ||
81 | +ARM_TESTS += fcvt | ||
82 | fcvt: LDFLAGS+=-lm | ||
83 | # fcvt: CFLAGS+=-march=armv8.2-a+fp16 -mfpu=neon-fp-armv8 | ||
84 | - | ||
85 | run-fcvt: fcvt | ||
86 | $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)") | ||
87 | $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref) | ||
88 | -endif | ||
34 | + | 89 | + |
35 | void exynos4210_write_secondary(ARMCPU *cpu, | 90 | +TESTS += $(ARM_TESTS) |
36 | const struct arm_boot_info *info); | 91 | |
37 | 92 | # On ARM Linux only supports 4k pages | |
38 | -Exynos4210State *exynos4210_init(MemoryRegion *system_mem); | 93 | EXTRA_RUNS+=run-test-mmap-4096 |
39 | - | ||
40 | /* Initialize exynos4210 IRQ subsystem stub */ | ||
41 | qemu_irq *exynos4210_init_irq(Exynos4210Irq *env); | ||
42 | |||
43 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/hw/arm/exynos4210.c | ||
46 | +++ b/hw/arm/exynos4210.c | ||
47 | @@ -XXX,XX +XXX,XX @@ static void pl330_create(uint32_t base, qemu_irq irq, int nreq) | ||
48 | sysbus_connect_irq(busdev, 0, irq); | ||
49 | } | ||
50 | |||
51 | -Exynos4210State *exynos4210_init(MemoryRegion *system_mem) | ||
52 | +static void exynos4210_realize(DeviceState *socdev, Error **errp) | ||
53 | { | ||
54 | - Exynos4210State *s = g_new0(Exynos4210State, 1); | ||
55 | + Exynos4210State *s = EXYNOS4210_SOC(socdev); | ||
56 | + MemoryRegion *system_mem = get_system_memory(); | ||
57 | qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; | ||
58 | SysBusDevice *busdev; | ||
59 | DeviceState *dev; | ||
60 | @@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem) | ||
61 | qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32); | ||
62 | pl330_create(EXYNOS4210_PL330_BASE2_ADDR, | ||
63 | qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1); | ||
64 | - | ||
65 | - return s; | ||
66 | } | ||
67 | + | ||
68 | +static void exynos4210_class_init(ObjectClass *klass, void *data) | ||
69 | +{ | ||
70 | + DeviceClass *dc = DEVICE_CLASS(klass); | ||
71 | + | ||
72 | + dc->realize = exynos4210_realize; | ||
73 | +} | ||
74 | + | ||
75 | +static const TypeInfo exynos4210_info = { | ||
76 | + .name = TYPE_EXYNOS4210_SOC, | ||
77 | + .parent = TYPE_SYS_BUS_DEVICE, | ||
78 | + .instance_size = sizeof(Exynos4210State), | ||
79 | + .class_init = exynos4210_class_init, | ||
80 | +}; | ||
81 | + | ||
82 | +static void exynos4210_register_types(void) | ||
83 | +{ | ||
84 | + type_register_static(&exynos4210_info); | ||
85 | +} | ||
86 | + | ||
87 | +type_init(exynos4210_register_types) | ||
88 | diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c | ||
89 | index XXXXXXX..XXXXXXX 100644 | ||
90 | --- a/hw/arm/exynos4_boards.c | ||
91 | +++ b/hw/arm/exynos4_boards.c | ||
92 | @@ -XXX,XX +XXX,XX @@ typedef enum Exynos4BoardType { | ||
93 | } Exynos4BoardType; | ||
94 | |||
95 | typedef struct Exynos4BoardState { | ||
96 | - Exynos4210State *soc; | ||
97 | + Exynos4210State soc; | ||
98 | MemoryRegion dram0_mem; | ||
99 | MemoryRegion dram1_mem; | ||
100 | } Exynos4BoardState; | ||
101 | @@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine, | ||
102 | exynos4_boards_init_ram(s, get_system_memory(), | ||
103 | exynos4_board_ram_size[board_type]); | ||
104 | |||
105 | - s->soc = exynos4210_init(get_system_memory()); | ||
106 | + object_initialize(&s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC); | ||
107 | + qdev_set_parent_bus(DEVICE(&s->soc), sysbus_get_default()); | ||
108 | + object_property_set_bool(OBJECT(&s->soc), true, "realized", | ||
109 | + &error_fatal); | ||
110 | |||
111 | return s; | ||
112 | } | ||
113 | @@ -XXX,XX +XXX,XX @@ static void smdkc210_init(MachineState *machine) | ||
114 | EXYNOS4_BOARD_SMDKC210); | ||
115 | |||
116 | lan9215_init(SMDK_LAN9118_BASE_ADDR, | ||
117 | - qemu_irq_invert(s->soc->irq_table[exynos4210_get_irq(37, 1)])); | ||
118 | + qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)])); | ||
119 | arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo); | ||
120 | } | ||
121 | |||
122 | -- | 94 | -- |
123 | 2.20.1 | 95 | 2.20.1 |
124 | 96 | ||
125 | 97 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | 1 | From: Alex Bennée <alex.bennee@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 3 | We do this for other semihosting calls so we might as well do it for |
4 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 4 | M-profile as well. |
5 | Message-id: 20190520214342.13709-2-philmd@redhat.com | 5 | |
6 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20190913151845.12582-3-alex.bennee@linaro.org | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 11 | --- |
8 | hw/arm/exynos4_boards.c | 24 ------------------------ | 12 | target/arm/m_helper.c | 18 ++++++------------ |
9 | 1 file changed, 24 deletions(-) | 13 | target/arm/translate.c | 11 ++++++++++- |
14 | 2 files changed, 16 insertions(+), 13 deletions(-) | ||
10 | 15 | ||
11 | diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c | 16 | diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c |
12 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/hw/arm/exynos4_boards.c | 18 | --- a/target/arm/m_helper.c |
14 | +++ b/hw/arm/exynos4_boards.c | 19 | +++ b/target/arm/m_helper.c |
15 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) |
16 | #include "hw/net/lan9118.h" | 21 | break; |
17 | #include "hw/boards.h" | 22 | } |
18 | 23 | break; | |
19 | -#undef DEBUG | 24 | + case EXCP_SEMIHOST: |
20 | - | 25 | + qemu_log_mask(CPU_LOG_INT, |
21 | -//#define DEBUG | 26 | + "...handling as semihosting call 0x%x\n", |
22 | - | 27 | + env->regs[0]); |
23 | -#ifdef DEBUG | 28 | + env->regs[0] = do_arm_semihosting(env); |
24 | - #undef PRINT_DEBUG | 29 | + return; |
25 | - #define PRINT_DEBUG(fmt, args...) \ | 30 | case EXCP_BKPT: |
26 | - do { \ | 31 | - if (semihosting_enabled()) { |
27 | - fprintf(stderr, " [%s:%d] "fmt, __func__, __LINE__, ##args); \ | 32 | - int nr; |
28 | - } while (0) | 33 | - nr = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) & 0xff; |
29 | -#else | 34 | - if (nr == 0xab) { |
30 | - #define PRINT_DEBUG(fmt, args...) do {} while (0) | 35 | - env->regs[15] += 2; |
31 | -#endif | 36 | - qemu_log_mask(CPU_LOG_INT, |
32 | - | 37 | - "...handling as semihosting call 0x%x\n", |
33 | #define SMDK_LAN9118_BASE_ADDR 0x05000000 | 38 | - env->regs[0]); |
34 | 39 | - env->regs[0] = do_arm_semihosting(env); | |
35 | typedef enum Exynos4BoardType { | 40 | - return; |
36 | @@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine, | 41 | - } |
37 | exynos4_board_binfo.gic_cpu_if_addr = | 42 | - } |
38 | EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100; | 43 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG, false); |
39 | 44 | break; | |
40 | - PRINT_DEBUG("\n ram_size: %luMiB [0x%08lx]\n" | 45 | case EXCP_IRQ: |
41 | - " kernel_filename: %s\n" | 46 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
42 | - " kernel_cmdline: %s\n" | 47 | index XXXXXXX..XXXXXXX 100644 |
43 | - " initrd_filename: %s\n", | 48 | --- a/target/arm/translate.c |
44 | - exynos4_board_ram_size[board_type] / 1048576, | 49 | +++ b/target/arm/translate.c |
45 | - exynos4_board_ram_size[board_type], | 50 | @@ -XXX,XX +XXX,XX @@ static bool trans_BKPT(DisasContext *s, arg_BKPT *a) |
46 | - machine->kernel_filename, | 51 | if (!ENABLE_ARCH_5) { |
47 | - machine->kernel_cmdline, | 52 | return false; |
48 | - machine->initrd_filename); | 53 | } |
49 | - | 54 | - gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false)); |
50 | exynos4_boards_init_ram(s, get_system_memory(), | 55 | + if (arm_dc_feature(s, ARM_FEATURE_M) && |
51 | exynos4_board_ram_size[board_type]); | 56 | + semihosting_enabled() && |
57 | +#ifndef CONFIG_USER_ONLY | ||
58 | + !IS_USER(s) && | ||
59 | +#endif | ||
60 | + (a->imm == 0xab)) { | ||
61 | + gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST); | ||
62 | + } else { | ||
63 | + gen_exception_bkpt_insn(s, syn_aa32_bkpt(a->imm, false)); | ||
64 | + } | ||
65 | return true; | ||
66 | } | ||
52 | 67 | ||
53 | -- | 68 | -- |
54 | 2.20.1 | 69 | 2.20.1 |
55 | 70 | ||
56 | 71 | diff view generated by jsdifflib |
1 | From: Alistair Francis <alistair.francis@wdc.com> | 1 | From: Alex Bennée <alex.bennee@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Commit 89e68b575 "target/arm: Use vector operations for saturation" | 3 | As for the other semihosting calls we can resolve this at translate |
4 | causes this abort() when booting QEMU ARM with a Cortex-A15: | 4 | time. |
5 | 5 | ||
6 | 0 0x00007ffff4c2382f in raise () at /usr/lib/libc.so.6 | 6 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> |
7 | 1 0x00007ffff4c0e672 in abort () at /usr/lib/libc.so.6 | 7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
8 | 2 0x00005555559c1839 in disas_neon_data_insn (insn=<optimized out>, s=<optimized out>) at ./target/arm/translate.c:6673 | 8 | Message-id: 20190913151845.12582-4-alex.bennee@linaro.org |
9 | 3 0x00005555559c1839 in disas_neon_data_insn (s=<optimized out>, insn=<optimized out>) at ./target/arm/translate.c:6386 | ||
10 | 4 0x00005555559cd8a4 in disas_arm_insn (insn=4081107068, s=0x7fffe59a9510) at ./target/arm/translate.c:9289 | ||
11 | 5 0x00005555559cd8a4 in arm_tr_translate_insn (dcbase=0x7fffe59a9510, cpu=<optimized out>) at ./target/arm/translate.c:13612 | ||
12 | 6 0x00005555558d1d39 in translator_loop (ops=0x5555561cc580 <arm_translator_ops>, db=0x7fffe59a9510, cpu=0x55555686a2f0, tb=<optimized out>, max_insns=<optimized out>) at ./accel/tcg/translator.c:96 | ||
13 | 7 0x00005555559d10d4 in gen_intermediate_code (cpu=cpu@entry=0x55555686a2f0, tb=tb@entry=0x7fffd7840080 <code_gen_buffer+126091347>, max_insns=max_insns@entry=512) at ./target/arm/translate.c:13901 | ||
14 | 8 0x00005555558d06b9 in tb_gen_code (cpu=cpu@entry=0x55555686a2f0, pc=3067096216, cs_base=0, flags=192, cflags=-16252928, cflags@entry=524288) at ./accel/tcg/translate-all.c:1736 | ||
15 | 9 0x00005555558ce467 in tb_find (cf_mask=524288, tb_exit=1, last_tb=0x7fffd783e640 <code_gen_buffer+126084627>, cpu=0x1) at ./accel/tcg/cpu-exec.c:407 | ||
16 | 10 0x00005555558ce467 in cpu_exec (cpu=cpu@entry=0x55555686a2f0) at ./accel/tcg/cpu-exec.c:728 | ||
17 | 11 0x000055555588b0cf in tcg_cpu_exec (cpu=0x55555686a2f0) at ./cpus.c:1431 | ||
18 | 12 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=0x55555686a2f0) at ./cpus.c:1735 | ||
19 | 13 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=arg@entry=0x55555686a2f0) at ./cpus.c:1709 | ||
20 | 14 0x0000555555d2629a in qemu_thread_start (args=<optimized out>) at ./util/qemu-thread-posix.c:502 | ||
21 | 15 0x00007ffff4db8a92 in start_thread () at /usr/lib/libpthread. | ||
22 | |||
23 | This patch ensures that we don't hit the abort() in the second switch | ||
24 | case in disas_neon_data_insn() as we will return from the first case. | ||
25 | |||
26 | Signed-off-by: Alistair Francis <alistair.francis@wdc.com> | ||
27 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
28 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
29 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
30 | Tested-by: Alex Bennée <alex.bennee@linaro.org> | ||
31 | Message-id: ad91b397f360b2fc7f4087e476f7df5b04d42ddb.1558021877.git.alistair.francis@wdc.com | ||
32 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
33 | --- | 10 | --- |
34 | target/arm/translate.c | 4 ++-- | 11 | target/arm/translate.c | 19 +++++++++++++++---- |
35 | 1 file changed, 2 insertions(+), 2 deletions(-) | 12 | 1 file changed, 15 insertions(+), 4 deletions(-) |
36 | 13 | ||
37 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 14 | diff --git a/target/arm/translate.c b/target/arm/translate.c |
38 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
39 | --- a/target/arm/translate.c | 16 | --- a/target/arm/translate.c |
40 | +++ b/target/arm/translate.c | 17 | +++ b/target/arm/translate.c |
41 | @@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) | 18 | @@ -XXX,XX +XXX,XX @@ static bool trans_CBZ(DisasContext *s, arg_CBZ *a) |
42 | tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc), | 19 | } |
43 | rn_ofs, rm_ofs, vec_size, vec_size, | 20 | |
44 | (u ? uqadd_op : sqadd_op) + size); | 21 | /* |
45 | - break; | 22 | - * Supervisor call |
46 | + return 0; | 23 | + * Supervisor call - both T32 & A32 come here so we need to check |
47 | 24 | + * which mode we are in when checking for semihosting. | |
48 | case NEON_3R_VQSUB: | 25 | */ |
49 | tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc), | 26 | |
50 | rn_ofs, rm_ofs, vec_size, vec_size, | 27 | static bool trans_SVC(DisasContext *s, arg_SVC *a) |
51 | (u ? uqsub_op : sqsub_op) + size); | 28 | { |
52 | - break; | 29 | - gen_set_pc_im(s, s->base.pc_next); |
53 | + return 0; | 30 | - s->svc_imm = a->imm; |
54 | 31 | - s->base.is_jmp = DISAS_SWI; | |
55 | case NEON_3R_VMUL: /* VMUL */ | 32 | + const uint32_t semihost_imm = s->thumb ? 0xab : 0x123456; |
56 | if (u) { | 33 | + |
34 | + if (!arm_dc_feature(s, ARM_FEATURE_M) && semihosting_enabled() && | ||
35 | +#ifndef CONFIG_USER_ONLY | ||
36 | + !IS_USER(s) && | ||
37 | +#endif | ||
38 | + (a->imm == semihost_imm)) { | ||
39 | + gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST); | ||
40 | + } else { | ||
41 | + gen_set_pc_im(s, s->base.pc_next); | ||
42 | + s->svc_imm = a->imm; | ||
43 | + s->base.is_jmp = DISAS_SWI; | ||
44 | + } | ||
45 | return true; | ||
46 | } | ||
47 | |||
57 | -- | 48 | -- |
58 | 2.20.1 | 49 | 2.20.1 |
59 | 50 | ||
60 | 51 | diff view generated by jsdifflib |
1 | The ICC_CTLR_EL3 register includes some bits which are aliases | 1 | From: Alex Bennée <alex.bennee@linaro.org> |
---|---|---|---|
2 | of bits in the ICC_CTLR_EL1(S) and (NS) registers. QEMU chooses | ||
3 | to keep those bits in the cs->icc_ctlr_el1[] struct fields. | ||
4 | Unfortunately a missing '~' in the code to update the bits | ||
5 | in those fields meant that writing to ICC_CTLR_EL3 would corrupt | ||
6 | the ICC_CLTR_EL1 register values. | ||
7 | 2 | ||
3 | Now we do all our checking and use a common EXCP_SEMIHOST for | ||
4 | semihosting operations we can make helper code a lot simpler. | ||
5 | |||
6 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20190913151845.12582-5-alex.bennee@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
10 | Message-id: 20190520162809.2677-5-peter.maydell@linaro.org | ||
11 | --- | 10 | --- |
12 | hw/intc/arm_gicv3_cpuif.c | 4 ++-- | 11 | target/arm/helper.c | 96 +++++++++++---------------------------------- |
13 | 1 file changed, 2 insertions(+), 2 deletions(-) | 12 | 1 file changed, 22 insertions(+), 74 deletions(-) |
14 | 13 | ||
15 | diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c | 14 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
16 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/intc/arm_gicv3_cpuif.c | 16 | --- a/target/arm/helper.c |
18 | +++ b/hw/intc/arm_gicv3_cpuif.c | 17 | +++ b/target/arm/helper.c |
19 | @@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri, | 18 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) |
20 | trace_gicv3_icc_ctlr_el3_write(gicv3_redist_affid(cs), value); | 19 | new_el, env->pc, pstate_read(env)); |
21 | 20 | } | |
22 | /* *_EL1NS and *_EL1S bits are aliases into the ICC_CTLR_EL1 bits. */ | 21 | |
23 | - cs->icc_ctlr_el1[GICV3_NS] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); | 22 | -static inline bool check_for_semihosting(CPUState *cs) |
24 | + cs->icc_ctlr_el1[GICV3_NS] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); | 23 | -{ |
25 | if (value & ICC_CTLR_EL3_EOIMODE_EL1NS) { | 24 | +/* |
26 | cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE; | 25 | + * Do semihosting call and set the appropriate return value. All the |
26 | + * permission and validity checks have been done at translate time. | ||
27 | + * | ||
28 | + * We only see semihosting exceptions in TCG only as they are not | ||
29 | + * trapped to the hypervisor in KVM. | ||
30 | + */ | ||
31 | #ifdef CONFIG_TCG | ||
32 | - /* Check whether this exception is a semihosting call; if so | ||
33 | - * then handle it and return true; otherwise return false. | ||
34 | - */ | ||
35 | +static void handle_semihosting(CPUState *cs) | ||
36 | +{ | ||
37 | ARMCPU *cpu = ARM_CPU(cs); | ||
38 | CPUARMState *env = &cpu->env; | ||
39 | |||
40 | if (is_a64(env)) { | ||
41 | - if (cs->exception_index == EXCP_SEMIHOST) { | ||
42 | - /* This is always the 64-bit semihosting exception. | ||
43 | - * The "is this usermode" and "is semihosting enabled" | ||
44 | - * checks have been done at translate time. | ||
45 | - */ | ||
46 | - qemu_log_mask(CPU_LOG_INT, | ||
47 | - "...handling as semihosting call 0x%" PRIx64 "\n", | ||
48 | - env->xregs[0]); | ||
49 | - env->xregs[0] = do_arm_semihosting(env); | ||
50 | - return true; | ||
51 | - } | ||
52 | - return false; | ||
53 | + qemu_log_mask(CPU_LOG_INT, | ||
54 | + "...handling as semihosting call 0x%" PRIx64 "\n", | ||
55 | + env->xregs[0]); | ||
56 | + env->xregs[0] = do_arm_semihosting(env); | ||
57 | } else { | ||
58 | - uint32_t imm; | ||
59 | - | ||
60 | - /* Only intercept calls from privileged modes, to provide some | ||
61 | - * semblance of security. | ||
62 | - */ | ||
63 | - if (cs->exception_index != EXCP_SEMIHOST && | ||
64 | - (!semihosting_enabled() || | ||
65 | - ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR))) { | ||
66 | - return false; | ||
67 | - } | ||
68 | - | ||
69 | - switch (cs->exception_index) { | ||
70 | - case EXCP_SEMIHOST: | ||
71 | - /* This is always a semihosting call; the "is this usermode" | ||
72 | - * and "is semihosting enabled" checks have been done at | ||
73 | - * translate time. | ||
74 | - */ | ||
75 | - break; | ||
76 | - case EXCP_SWI: | ||
77 | - /* Check for semihosting interrupt. */ | ||
78 | - if (env->thumb) { | ||
79 | - imm = arm_lduw_code(env, env->regs[15] - 2, arm_sctlr_b(env)) | ||
80 | - & 0xff; | ||
81 | - if (imm == 0xab) { | ||
82 | - break; | ||
83 | - } | ||
84 | - } else { | ||
85 | - imm = arm_ldl_code(env, env->regs[15] - 4, arm_sctlr_b(env)) | ||
86 | - & 0xffffff; | ||
87 | - if (imm == 0x123456) { | ||
88 | - break; | ||
89 | - } | ||
90 | - } | ||
91 | - return false; | ||
92 | - case EXCP_BKPT: | ||
93 | - /* See if this is a semihosting syscall. */ | ||
94 | - if (env->thumb) { | ||
95 | - imm = arm_lduw_code(env, env->regs[15], arm_sctlr_b(env)) | ||
96 | - & 0xff; | ||
97 | - if (imm == 0xab) { | ||
98 | - env->regs[15] += 2; | ||
99 | - break; | ||
100 | - } | ||
101 | - } | ||
102 | - return false; | ||
103 | - default: | ||
104 | - return false; | ||
105 | - } | ||
106 | - | ||
107 | qemu_log_mask(CPU_LOG_INT, | ||
108 | "...handling as semihosting call 0x%x\n", | ||
109 | env->regs[0]); | ||
110 | env->regs[0] = do_arm_semihosting(env); | ||
111 | - return true; | ||
27 | } | 112 | } |
28 | @@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri, | 113 | -#else |
29 | cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_CBPR; | 114 | - return false; |
115 | -#endif | ||
116 | } | ||
117 | +#endif | ||
118 | |||
119 | /* Handle a CPU exception for A and R profile CPUs. | ||
120 | * Do any appropriate logging, handle PSCI calls, and then hand off | ||
121 | @@ -XXX,XX +XXX,XX @@ void arm_cpu_do_interrupt(CPUState *cs) | ||
122 | return; | ||
30 | } | 123 | } |
31 | 124 | ||
32 | - cs->icc_ctlr_el1[GICV3_S] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); | 125 | - /* Semihosting semantics depend on the register width of the |
33 | + cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE); | 126 | - * code that caused the exception, not the target exception level, |
34 | if (value & ICC_CTLR_EL3_EOIMODE_EL1S) { | 127 | - * so must be handled here. |
35 | cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_EOIMODE; | 128 | + /* |
129 | + * Semihosting semantics depend on the register width of the code | ||
130 | + * that caused the exception, not the target exception level, so | ||
131 | + * must be handled here. | ||
132 | */ | ||
133 | - if (check_for_semihosting(cs)) { | ||
134 | +#ifdef CONFIG_TCG | ||
135 | + if (cs->exception_index == EXCP_SEMIHOST) { | ||
136 | + handle_semihosting(cs); | ||
137 | return; | ||
36 | } | 138 | } |
139 | +#endif | ||
140 | |||
141 | /* Hooks may change global state so BQL should be held, also the | ||
142 | * BQL needs to be held for any modification of | ||
37 | -- | 143 | -- |
38 | 2.20.1 | 144 | 2.20.1 |
39 | 145 | ||
40 | 146 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Alex Bennée <alex.bennee@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This is, after all, how we implement extract2 in tcg/aarch64. | 3 | Now we do all our checking at translate time we can make cpu_loop a |
4 | little bit simpler. We also introduce a simple linux-user semihosting | ||
5 | test case to defend the functionality. The out-of-tree softmmu based | ||
6 | semihosting tests are still more comprehensive. | ||
4 | 7 | ||
8 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> | ||
9 | Message-id: 20190913151845.12582-6-alex.bennee@linaro.org | ||
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20190514011129.11330-2-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 12 | --- |
10 | target/arm/translate-a64.c | 38 ++++++++++++++++++++------------------ | 13 | linux-user/arm/target_syscall.h | 3 --- |
11 | 1 file changed, 20 insertions(+), 18 deletions(-) | 14 | linux-user/arm/cpu_loop.c | 3 --- |
15 | 2 files changed, 6 deletions(-) | ||
12 | 16 | ||
13 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 17 | diff --git a/linux-user/arm/target_syscall.h b/linux-user/arm/target_syscall.h |
14 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/translate-a64.c | 19 | --- a/linux-user/arm/target_syscall.h |
16 | +++ b/target/arm/translate-a64.c | 20 | +++ b/linux-user/arm/target_syscall.h |
17 | @@ -XXX,XX +XXX,XX @@ static void disas_extract(DisasContext *s, uint32_t insn) | 21 | @@ -XXX,XX +XXX,XX @@ struct target_pt_regs { |
18 | } else { | 22 | #define ARM_NR_set_tls (ARM_NR_BASE + 5) |
19 | tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm)); | 23 | #define ARM_NR_get_tls (ARM_NR_BASE + 6) |
20 | } | 24 | |
21 | - } else if (rm == rn) { /* ROR */ | 25 | -#define ARM_NR_semihosting 0x123456 |
22 | - tcg_rm = cpu_reg(s, rm); | 26 | -#define ARM_NR_thumb_semihosting 0xAB |
23 | - if (sf) { | 27 | - |
24 | - tcg_gen_rotri_i64(tcg_rd, tcg_rm, imm); | 28 | #if defined(TARGET_WORDS_BIGENDIAN) |
25 | - } else { | 29 | #define UNAME_MACHINE "armv5teb" |
26 | - TCGv_i32 tmp = tcg_temp_new_i32(); | 30 | #else |
27 | - tcg_gen_extrl_i64_i32(tmp, tcg_rm); | 31 | diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c |
28 | - tcg_gen_rotri_i32(tmp, tmp, imm); | 32 | index XXXXXXX..XXXXXXX 100644 |
29 | - tcg_gen_extu_i32_i64(tcg_rd, tmp); | 33 | --- a/linux-user/arm/cpu_loop.c |
30 | - tcg_temp_free_i32(tmp); | 34 | +++ b/linux-user/arm/cpu_loop.c |
31 | - } | 35 | @@ -XXX,XX +XXX,XX @@ void cpu_loop(CPUARMState *env) |
32 | } else { | 36 | |
33 | - tcg_rm = read_cpu_reg(s, rm, sf); | 37 | if (n == ARM_NR_cacheflush) { |
34 | - tcg_rn = read_cpu_reg(s, rn, sf); | 38 | /* nop */ |
35 | - tcg_gen_shri_i64(tcg_rm, tcg_rm, imm); | 39 | - } else if (n == ARM_NR_semihosting |
36 | - tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm); | 40 | - || n == ARM_NR_thumb_semihosting) { |
37 | - tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn); | 41 | - env->regs[0] = do_arm_semihosting (env); |
38 | - if (!sf) { | 42 | } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) { |
39 | - tcg_gen_ext32u_i64(tcg_rd, tcg_rd); | 43 | /* linux syscall */ |
40 | + tcg_rm = cpu_reg(s, rm); | 44 | if (env->thumb || n == 0) { |
41 | + tcg_rn = cpu_reg(s, rn); | ||
42 | + | ||
43 | + if (sf) { | ||
44 | + /* Specialization to ROR happens in EXTRACT2. */ | ||
45 | + tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, imm); | ||
46 | + } else { | ||
47 | + TCGv_i32 t0 = tcg_temp_new_i32(); | ||
48 | + | ||
49 | + tcg_gen_extrl_i64_i32(t0, tcg_rm); | ||
50 | + if (rm == rn) { | ||
51 | + tcg_gen_rotri_i32(t0, t0, imm); | ||
52 | + } else { | ||
53 | + TCGv_i32 t1 = tcg_temp_new_i32(); | ||
54 | + tcg_gen_extrl_i64_i32(t1, tcg_rn); | ||
55 | + tcg_gen_extract2_i32(t0, t0, t1, imm); | ||
56 | + tcg_temp_free_i32(t1); | ||
57 | + } | ||
58 | + tcg_gen_extu_i32_i64(tcg_rd, t0); | ||
59 | + tcg_temp_free_i32(t0); | ||
60 | } | ||
61 | } | ||
62 | } | ||
63 | -- | 45 | -- |
64 | 2.20.1 | 46 | 2.20.1 |
65 | 47 | ||
66 | 48 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The system_clock_scale global is used only by the armv7m systick | ||
2 | device; move the extern declaration to the armv7m_systick.h header, | ||
3 | and expand the comment to explain what it is and that it should | ||
4 | ideally be replaced with a different approach. | ||
5 | 1 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
8 | Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
9 | Message-id: 20190516163857.6430-2-peter.maydell@linaro.org | ||
10 | --- | ||
11 | include/hw/arm/arm.h | 4 ---- | ||
12 | include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++++++++ | ||
13 | 2 files changed, 22 insertions(+), 4 deletions(-) | ||
14 | |||
15 | diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/include/hw/arm/arm.h | ||
18 | +++ b/include/hw/arm/arm.h | ||
19 | @@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, | ||
20 | const struct arm_boot_info *info, | ||
21 | hwaddr mvbar_addr); | ||
22 | |||
23 | -/* Multiplication factor to convert from system clock ticks to qemu timer | ||
24 | - ticks. */ | ||
25 | -extern int system_clock_scale; | ||
26 | - | ||
27 | #endif /* HW_ARM_H */ | ||
28 | diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/include/hw/timer/armv7m_systick.h | ||
31 | +++ b/include/hw/timer/armv7m_systick.h | ||
32 | @@ -XXX,XX +XXX,XX @@ typedef struct SysTickState { | ||
33 | qemu_irq irq; | ||
34 | } SysTickState; | ||
35 | |||
36 | +/* | ||
37 | + * Multiplication factor to convert from system clock ticks to qemu timer | ||
38 | + * ticks. This should be set (by board code, usually) to a value | ||
39 | + * equal to NANOSECONDS_PER_SECOND / frq, where frq is the clock frequency | ||
40 | + * in Hz of the CPU. | ||
41 | + * | ||
42 | + * This value is used by the systick device when it is running in | ||
43 | + * its "use the CPU clock" mode (ie when SYST_CSR.CLKSOURCE == 1) to | ||
44 | + * set how fast the timer should tick. | ||
45 | + * | ||
46 | + * TODO: we should refactor this so that rather than using a global | ||
47 | + * we use a device property or something similar. This is complicated | ||
48 | + * because (a) the property would need to be plumbed through from the | ||
49 | + * board code down through various layers to the systick device | ||
50 | + * and (b) the property needs to be modifiable after realize, because | ||
51 | + * the stellaris board uses this to implement the behaviour where the | ||
52 | + * guest can reprogram the PLL registers to downclock the CPU, and the | ||
53 | + * systick device needs to react accordingly. Possibly this should | ||
54 | + * be deferred until we have a good API for modelling clock trees. | ||
55 | + */ | ||
56 | +extern int system_clock_scale; | ||
57 | + | ||
58 | #endif | ||
59 | -- | ||
60 | 2.20.1 | ||
61 | |||
62 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | The hw/arm/arm.h header now only includes declarations relating | ||
2 | to boot.c code, so it is only needed by Arm board or SoC code. | ||
3 | Remove some unnecessary inclusions of it from target/arm files | ||
4 | and from hw/intc/armv7m_nvic.c. | ||
5 | 1 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
8 | Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
9 | Message-id: 20190516163857.6430-3-peter.maydell@linaro.org | ||
10 | --- | ||
11 | hw/intc/armv7m_nvic.c | 1 - | ||
12 | target/arm/arm-semi.c | 1 - | ||
13 | target/arm/cpu.c | 1 - | ||
14 | target/arm/cpu64.c | 1 - | ||
15 | target/arm/kvm.c | 1 - | ||
16 | target/arm/kvm32.c | 1 - | ||
17 | target/arm/kvm64.c | 1 - | ||
18 | 7 files changed, 7 deletions(-) | ||
19 | |||
20 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/hw/intc/armv7m_nvic.c | ||
23 | +++ b/hw/intc/armv7m_nvic.c | ||
24 | @@ -XXX,XX +XXX,XX @@ | ||
25 | #include "cpu.h" | ||
26 | #include "hw/sysbus.h" | ||
27 | #include "qemu/timer.h" | ||
28 | -#include "hw/arm/arm.h" | ||
29 | #include "hw/intc/armv7m_nvic.h" | ||
30 | #include "target/arm/cpu.h" | ||
31 | #include "exec/exec-all.h" | ||
32 | diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/target/arm/arm-semi.c | ||
35 | +++ b/target/arm/arm-semi.c | ||
36 | @@ -XXX,XX +XXX,XX @@ | ||
37 | #else | ||
38 | #include "qemu-common.h" | ||
39 | #include "exec/gdbstub.h" | ||
40 | -#include "hw/arm/arm.h" | ||
41 | #include "qemu/cutils.h" | ||
42 | #endif | ||
43 | |||
44 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/target/arm/cpu.c | ||
47 | +++ b/target/arm/cpu.c | ||
48 | @@ -XXX,XX +XXX,XX @@ | ||
49 | #if !defined(CONFIG_USER_ONLY) | ||
50 | #include "hw/loader.h" | ||
51 | #endif | ||
52 | -#include "hw/arm/arm.h" | ||
53 | #include "sysemu/sysemu.h" | ||
54 | #include "sysemu/hw_accel.h" | ||
55 | #include "kvm_arm.h" | ||
56 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
57 | index XXXXXXX..XXXXXXX 100644 | ||
58 | --- a/target/arm/cpu64.c | ||
59 | +++ b/target/arm/cpu64.c | ||
60 | @@ -XXX,XX +XXX,XX @@ | ||
61 | #if !defined(CONFIG_USER_ONLY) | ||
62 | #include "hw/loader.h" | ||
63 | #endif | ||
64 | -#include "hw/arm/arm.h" | ||
65 | #include "sysemu/sysemu.h" | ||
66 | #include "sysemu/kvm.h" | ||
67 | #include "kvm_arm.h" | ||
68 | diff --git a/target/arm/kvm.c b/target/arm/kvm.c | ||
69 | index XXXXXXX..XXXXXXX 100644 | ||
70 | --- a/target/arm/kvm.c | ||
71 | +++ b/target/arm/kvm.c | ||
72 | @@ -XXX,XX +XXX,XX @@ | ||
73 | #include "cpu.h" | ||
74 | #include "trace.h" | ||
75 | #include "internals.h" | ||
76 | -#include "hw/arm/arm.h" | ||
77 | #include "hw/pci/pci.h" | ||
78 | #include "exec/memattrs.h" | ||
79 | #include "exec/address-spaces.h" | ||
80 | diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c | ||
81 | index XXXXXXX..XXXXXXX 100644 | ||
82 | --- a/target/arm/kvm32.c | ||
83 | +++ b/target/arm/kvm32.c | ||
84 | @@ -XXX,XX +XXX,XX @@ | ||
85 | #include "sysemu/kvm.h" | ||
86 | #include "kvm_arm.h" | ||
87 | #include "internals.h" | ||
88 | -#include "hw/arm/arm.h" | ||
89 | #include "qemu/log.h" | ||
90 | |||
91 | static inline void set_feature(uint64_t *features, int feature) | ||
92 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
93 | index XXXXXXX..XXXXXXX 100644 | ||
94 | --- a/target/arm/kvm64.c | ||
95 | +++ b/target/arm/kvm64.c | ||
96 | @@ -XXX,XX +XXX,XX @@ | ||
97 | #include "sysemu/kvm.h" | ||
98 | #include "kvm_arm.h" | ||
99 | #include "internals.h" | ||
100 | -#include "hw/arm/arm.h" | ||
101 | |||
102 | static bool have_guest_debug; | ||
103 | |||
104 | -- | ||
105 | 2.20.1 | ||
106 | |||
107 | diff view generated by jsdifflib |
1 | From: Guenter Roeck <linux@roeck-us.net> | 1 | From: Alex Bennée <alex.bennee@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | QEMU already supports pl330. Instantiate it for Exynos4210. | 3 | We already use semihosting for the system stuff so this is a simple |
4 | smoke test to ensure we are working OK on linux-user. | ||
4 | 5 | ||
5 | Relevant part of Linux arch/arm/boot/dts/exynos4.dtsi: | 6 | Signed-off-by: Alex Bennée <alex.bennee@linaro.org> |
6 | 7 | Message-id: 20190913151845.12582-7-alex.bennee@linaro.org | |
7 | / { | ||
8 | soc: soc { | ||
9 | amba { | ||
10 | pdma0: pdma@12680000 { | ||
11 | compatible = "arm,pl330", "arm,primecell"; | ||
12 | reg = <0x12680000 0x1000>; | ||
13 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | ||
14 | clocks = <&clock CLK_PDMA0>; | ||
15 | clock-names = "apb_pclk"; | ||
16 | #dma-cells = <1>; | ||
17 | #dma-channels = <8>; | ||
18 | #dma-requests = <32>; | ||
19 | }; | ||
20 | pdma1: pdma@12690000 { | ||
21 | compatible = "arm,pl330", "arm,primecell"; | ||
22 | reg = <0x12690000 0x1000>; | ||
23 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | ||
24 | clocks = <&clock CLK_PDMA1>; | ||
25 | clock-names = "apb_pclk"; | ||
26 | #dma-cells = <1>; | ||
27 | #dma-channels = <8>; | ||
28 | #dma-requests = <32>; | ||
29 | }; | ||
30 | mdma1: mdma@12850000 { | ||
31 | compatible = "arm,pl330", "arm,primecell"; | ||
32 | reg = <0x12850000 0x1000>; | ||
33 | interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | ||
34 | clocks = <&clock CLK_MDMA>; | ||
35 | clock-names = "apb_pclk"; | ||
36 | #dma-cells = <1>; | ||
37 | #dma-channels = <8>; | ||
38 | #dma-requests = <1>; | ||
39 | }; | ||
40 | }; | ||
41 | }; | ||
42 | }; | ||
43 | |||
44 | Signed-off-by: Guenter Roeck <linux@roeck-us.net> | ||
45 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
46 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
47 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
48 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
49 | Message-id: 20190520214342.13709-4-philmd@redhat.com | ||
50 | [PMD: Do not set default qdev properties, create the controllers in the SoC | ||
51 | rather than the board (Peter Maydell), add dtsi in commit message] | ||
52 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
53 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
54 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
55 | --- | 10 | --- |
56 | hw/arm/exynos4210.c | 26 ++++++++++++++++++++++++++ | 11 | tests/tcg/aarch64/Makefile.target | 5 ++++ |
57 | 1 file changed, 26 insertions(+) | 12 | tests/tcg/arm/Makefile.target | 5 ++++ |
13 | tests/tcg/arm/semihosting.c | 45 +++++++++++++++++++++++++++++++ | ||
14 | 3 files changed, 55 insertions(+) | ||
15 | create mode 100644 tests/tcg/arm/semihosting.c | ||
58 | 16 | ||
59 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | 17 | diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target |
60 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
61 | --- a/hw/arm/exynos4210.c | 19 | --- a/tests/tcg/aarch64/Makefile.target |
62 | +++ b/hw/arm/exynos4210.c | 20 | +++ b/tests/tcg/aarch64/Makefile.target |
21 | @@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt | ||
22 | AARCH64_TESTS += pauth-1 pauth-2 | ||
23 | run-pauth-%: QEMU_OPTS += -cpu max | ||
24 | |||
25 | +# Semihosting smoke test for linux-user | ||
26 | +AARCH64_TESTS += semihosting | ||
27 | +run-semihosting: semihosting | ||
28 | + $(call run-test,$<,$(QEMU) $< 2> $<.err, "$< on $(TARGET_NAME)") | ||
29 | + | ||
30 | TESTS += $(AARCH64_TESTS) | ||
31 | diff --git a/tests/tcg/arm/Makefile.target b/tests/tcg/arm/Makefile.target | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/tests/tcg/arm/Makefile.target | ||
34 | +++ b/tests/tcg/arm/Makefile.target | ||
35 | @@ -XXX,XX +XXX,XX @@ run-fcvt: fcvt | ||
36 | $(call run-test,fcvt,$(QEMU) $<,"$< on $(TARGET_NAME)") | ||
37 | $(call diff-out,fcvt,$(ARM_SRC)/fcvt.ref) | ||
38 | |||
39 | +# Semihosting smoke test for linux-user | ||
40 | +ARM_TESTS += semihosting | ||
41 | +run-semihosting: semihosting | ||
42 | + $(call run-test,$<,$(QEMU) $< 2> $<.err, "$< on $(TARGET_NAME)") | ||
43 | + | ||
44 | TESTS += $(ARM_TESTS) | ||
45 | |||
46 | # On ARM Linux only supports 4k pages | ||
47 | diff --git a/tests/tcg/arm/semihosting.c b/tests/tcg/arm/semihosting.c | ||
48 | new file mode 100644 | ||
49 | index XXXXXXX..XXXXXXX | ||
50 | --- /dev/null | ||
51 | +++ b/tests/tcg/arm/semihosting.c | ||
63 | @@ -XXX,XX +XXX,XX @@ | 52 | @@ -XXX,XX +XXX,XX @@ |
64 | /* EHCI */ | 53 | +/* |
65 | #define EXYNOS4210_EHCI_BASE_ADDR 0x12580000 | 54 | + * linux-user semihosting checks |
66 | 55 | + * | |
67 | +/* DMA */ | 56 | + * Copyright (c) 2019 |
68 | +#define EXYNOS4210_PL330_BASE0_ADDR 0x12680000 | 57 | + * Written by Alex Bennée <alex.bennee@linaro.org> |
69 | +#define EXYNOS4210_PL330_BASE1_ADDR 0x12690000 | 58 | + * |
70 | +#define EXYNOS4210_PL330_BASE2_ADDR 0x12850000 | 59 | + * SPDX-License-Identifier: GPL-3.0-or-later |
60 | + */ | ||
71 | + | 61 | + |
72 | static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, | 62 | +#include <stdint.h> |
73 | 0x09, 0x00, 0x00, 0x00 }; | 63 | + |
74 | 64 | +#define SYS_WRITE0 0x04 | |
75 | @@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu) | 65 | +#define SYS_REPORTEXC 0x18 |
76 | return (0x9 << ARM_AFF1_SHIFT) | cpu; | 66 | + |
77 | } | 67 | +void __semi_call(uintptr_t type, uintptr_t arg0) |
78 | |||
79 | +static void pl330_create(uint32_t base, qemu_irq irq, int nreq) | ||
80 | +{ | 68 | +{ |
81 | + SysBusDevice *busdev; | 69 | +#if defined(__arm__) |
82 | + DeviceState *dev; | 70 | + register uintptr_t t asm("r0") = type; |
83 | + | 71 | + register uintptr_t a0 asm("r1") = arg0; |
84 | + dev = qdev_create(NULL, "pl330"); | 72 | + asm("svc 0xab" |
85 | + qdev_prop_set_uint8(dev, "num_periph_req", nreq); | 73 | + : /* no return */ |
86 | + qdev_init_nofail(dev); | 74 | + : "r" (t), "r" (a0)); |
87 | + busdev = SYS_BUS_DEVICE(dev); | 75 | +#else |
88 | + sysbus_mmio_map(busdev, 0, base); | 76 | + register uintptr_t t asm("x0") = type; |
89 | + sysbus_connect_irq(busdev, 0, irq); | 77 | + register uintptr_t a0 asm("x1") = arg0; |
78 | + asm("hlt 0xf000" | ||
79 | + : /* no return */ | ||
80 | + : "r" (t), "r" (a0)); | ||
81 | +#endif | ||
90 | +} | 82 | +} |
91 | + | 83 | + |
92 | Exynos4210State *exynos4210_init(MemoryRegion *system_mem) | 84 | +int main(int argc, char *argv[argc]) |
93 | { | 85 | +{ |
94 | Exynos4210State *s = g_new0(Exynos4210State, 1); | 86 | +#if defined(__arm__) |
95 | @@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem) | 87 | + uintptr_t exit_code = 0x20026; |
96 | sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR, | 88 | +#else |
97 | s->irq_table[exynos4210_get_irq(28, 3)]); | 89 | + uintptr_t exit_block[2] = {0x20026, 0}; |
98 | 90 | + uintptr_t exit_code = (uintptr_t) &exit_block; | |
99 | + /*** DMA controllers ***/ | 91 | +#endif |
100 | + pl330_create(EXYNOS4210_PL330_BASE0_ADDR, | ||
101 | + qemu_irq_invert(s->irq_table[exynos4210_get_irq(35, 1)]), 32); | ||
102 | + pl330_create(EXYNOS4210_PL330_BASE1_ADDR, | ||
103 | + qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32); | ||
104 | + pl330_create(EXYNOS4210_PL330_BASE2_ADDR, | ||
105 | + qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1); | ||
106 | + | 92 | + |
107 | return s; | 93 | + __semi_call(SYS_WRITE0, (uintptr_t) "Hello World"); |
108 | } | 94 | + __semi_call(SYS_REPORTEXC, exit_code); |
95 | + /* if we get here we failed */ | ||
96 | + return -1; | ||
97 | +} | ||
109 | -- | 98 | -- |
110 | 2.20.1 | 99 | 2.20.1 |
111 | 100 | ||
112 | 101 | diff view generated by jsdifflib |
1 | The header file hw/arm/arm.h now includes only declarations | 1 | If we're booting a Linux kernel directly into Non-Secure |
---|---|---|---|
2 | relating to hw/arm/boot.c functionality. Rename it accordingly, | 2 | state on a CPU which has Secure state, then make sure we |
3 | and adjust its header comment. | 3 | set the NSACR CP11 and CP10 bits, so that Non-Secure is allowed |
4 | to access the FPU. Otherwise an AArch32 kernel will UNDEF as | ||
5 | soon as it tries to use the FPU. | ||
4 | 6 | ||
5 | The bulk of this commit was created via | 7 | It used to not matter that we didn't do this until commit |
6 | perl -pi -e 's|hw/arm/arm.h|hw/arm/boot.h|' hw/arm/*.c include/hw/arm/*.h | 8 | fc1120a7f5f2d4b6, where we implemented actually honouring |
9 | these NSACR bits. | ||
7 | 10 | ||
8 | In a few cases we can just delete the #include: | 11 | The problem only exists for CPUs where EL3 is AArch32; the |
9 | hw/arm/msf2-soc.c, include/hw/arm/aspeed_soc.h and | 12 | equivalent AArch64 trap bits are in CPTR_EL3 and are "0 to |
10 | include/hw/arm/bcm2836.h did not require it. | 13 | not trap, 1 to trap", so the reset value of the register |
14 | permits NS access, unlike NSACR. | ||
11 | 15 | ||
16 | Fixes: fc1120a7f5 | ||
17 | Fixes: https://bugs.launchpad.net/qemu/+bug/1844597 | ||
18 | Cc: qemu-stable@nongnu.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 20 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
14 | Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 21 | Message-id: 20190920174039.3916-1-peter.maydell@linaro.org |
15 | Message-id: 20190516163857.6430-4-peter.maydell@linaro.org | ||
16 | --- | 22 | --- |
17 | include/hw/arm/allwinner-a10.h | 2 +- | 23 | hw/arm/boot.c | 2 ++ |
18 | include/hw/arm/aspeed_soc.h | 1 - | 24 | 1 file changed, 2 insertions(+) |
19 | include/hw/arm/bcm2836.h | 1 - | ||
20 | include/hw/arm/{arm.h => boot.h} | 8 ++++---- | ||
21 | include/hw/arm/fsl-imx25.h | 2 +- | ||
22 | include/hw/arm/fsl-imx31.h | 2 +- | ||
23 | include/hw/arm/fsl-imx6.h | 2 +- | ||
24 | include/hw/arm/fsl-imx6ul.h | 2 +- | ||
25 | include/hw/arm/fsl-imx7.h | 2 +- | ||
26 | include/hw/arm/virt.h | 2 +- | ||
27 | include/hw/arm/xlnx-versal.h | 2 +- | ||
28 | include/hw/arm/xlnx-zynqmp.h | 2 +- | ||
29 | hw/arm/armsse.c | 2 +- | ||
30 | hw/arm/armv7m.c | 2 +- | ||
31 | hw/arm/aspeed.c | 2 +- | ||
32 | hw/arm/boot.c | 2 +- | ||
33 | hw/arm/collie.c | 2 +- | ||
34 | hw/arm/exynos4210.c | 2 +- | ||
35 | hw/arm/exynos4_boards.c | 2 +- | ||
36 | hw/arm/highbank.c | 2 +- | ||
37 | hw/arm/integratorcp.c | 2 +- | ||
38 | hw/arm/mainstone.c | 2 +- | ||
39 | hw/arm/microbit.c | 2 +- | ||
40 | hw/arm/mps2-tz.c | 2 +- | ||
41 | hw/arm/mps2.c | 2 +- | ||
42 | hw/arm/msf2-soc.c | 1 - | ||
43 | hw/arm/msf2-som.c | 2 +- | ||
44 | hw/arm/musca.c | 2 +- | ||
45 | hw/arm/musicpal.c | 2 +- | ||
46 | hw/arm/netduino2.c | 2 +- | ||
47 | hw/arm/nrf51_soc.c | 2 +- | ||
48 | hw/arm/nseries.c | 2 +- | ||
49 | hw/arm/omap1.c | 2 +- | ||
50 | hw/arm/omap2.c | 2 +- | ||
51 | hw/arm/omap_sx1.c | 2 +- | ||
52 | hw/arm/palm.c | 2 +- | ||
53 | hw/arm/raspi.c | 2 +- | ||
54 | hw/arm/realview.c | 2 +- | ||
55 | hw/arm/spitz.c | 2 +- | ||
56 | hw/arm/stellaris.c | 2 +- | ||
57 | hw/arm/stm32f205_soc.c | 2 +- | ||
58 | hw/arm/strongarm.c | 2 +- | ||
59 | hw/arm/tosa.c | 2 +- | ||
60 | hw/arm/versatilepb.c | 2 +- | ||
61 | hw/arm/vexpress.c | 2 +- | ||
62 | hw/arm/virt.c | 2 +- | ||
63 | hw/arm/xilinx_zynq.c | 2 +- | ||
64 | hw/arm/xlnx-versal.c | 2 +- | ||
65 | hw/arm/z2.c | 2 +- | ||
66 | 49 files changed, 49 insertions(+), 52 deletions(-) | ||
67 | rename include/hw/arm/{arm.h => boot.h} (98%) | ||
68 | 25 | ||
69 | diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h | ||
70 | index XXXXXXX..XXXXXXX 100644 | ||
71 | --- a/include/hw/arm/allwinner-a10.h | ||
72 | +++ b/include/hw/arm/allwinner-a10.h | ||
73 | @@ -XXX,XX +XXX,XX @@ | ||
74 | #include "qemu-common.h" | ||
75 | #include "qemu/error-report.h" | ||
76 | #include "hw/char/serial.h" | ||
77 | -#include "hw/arm/arm.h" | ||
78 | +#include "hw/arm/boot.h" | ||
79 | #include "hw/timer/allwinner-a10-pit.h" | ||
80 | #include "hw/intc/allwinner-a10-pic.h" | ||
81 | #include "hw/net/allwinner_emac.h" | ||
82 | diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h | ||
83 | index XXXXXXX..XXXXXXX 100644 | ||
84 | --- a/include/hw/arm/aspeed_soc.h | ||
85 | +++ b/include/hw/arm/aspeed_soc.h | ||
86 | @@ -XXX,XX +XXX,XX @@ | ||
87 | #ifndef ASPEED_SOC_H | ||
88 | #define ASPEED_SOC_H | ||
89 | |||
90 | -#include "hw/arm/arm.h" | ||
91 | #include "hw/intc/aspeed_vic.h" | ||
92 | #include "hw/misc/aspeed_scu.h" | ||
93 | #include "hw/misc/aspeed_sdmc.h" | ||
94 | diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h | ||
95 | index XXXXXXX..XXXXXXX 100644 | ||
96 | --- a/include/hw/arm/bcm2836.h | ||
97 | +++ b/include/hw/arm/bcm2836.h | ||
98 | @@ -XXX,XX +XXX,XX @@ | ||
99 | #ifndef BCM2836_H | ||
100 | #define BCM2836_H | ||
101 | |||
102 | -#include "hw/arm/arm.h" | ||
103 | #include "hw/arm/bcm2835_peripherals.h" | ||
104 | #include "hw/intc/bcm2836_control.h" | ||
105 | |||
106 | diff --git a/include/hw/arm/arm.h b/include/hw/arm/boot.h | ||
107 | similarity index 98% | ||
108 | rename from include/hw/arm/arm.h | ||
109 | rename to include/hw/arm/boot.h | ||
110 | index XXXXXXX..XXXXXXX 100644 | ||
111 | --- a/include/hw/arm/arm.h | ||
112 | +++ b/include/hw/arm/boot.h | ||
113 | @@ -XXX,XX +XXX,XX @@ | ||
114 | /* | ||
115 | - * Misc ARM declarations | ||
116 | + * ARM kernel loader. | ||
117 | * | ||
118 | * Copyright (c) 2006 CodeSourcery. | ||
119 | * Written by Paul Brook | ||
120 | @@ -XXX,XX +XXX,XX @@ | ||
121 | * | ||
122 | */ | ||
123 | |||
124 | -#ifndef HW_ARM_H | ||
125 | -#define HW_ARM_H | ||
126 | +#ifndef HW_ARM_BOOT_H | ||
127 | +#define HW_ARM_BOOT_H | ||
128 | |||
129 | #include "exec/memory.h" | ||
130 | #include "target/arm/cpu-qom.h" | ||
131 | @@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu, | ||
132 | const struct arm_boot_info *info, | ||
133 | hwaddr mvbar_addr); | ||
134 | |||
135 | -#endif /* HW_ARM_H */ | ||
136 | +#endif /* HW_ARM_BOOT_H */ | ||
137 | diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h | ||
138 | index XXXXXXX..XXXXXXX 100644 | ||
139 | --- a/include/hw/arm/fsl-imx25.h | ||
140 | +++ b/include/hw/arm/fsl-imx25.h | ||
141 | @@ -XXX,XX +XXX,XX @@ | ||
142 | #ifndef FSL_IMX25_H | ||
143 | #define FSL_IMX25_H | ||
144 | |||
145 | -#include "hw/arm/arm.h" | ||
146 | +#include "hw/arm/boot.h" | ||
147 | #include "hw/intc/imx_avic.h" | ||
148 | #include "hw/misc/imx25_ccm.h" | ||
149 | #include "hw/char/imx_serial.h" | ||
150 | diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h | ||
151 | index XXXXXXX..XXXXXXX 100644 | ||
152 | --- a/include/hw/arm/fsl-imx31.h | ||
153 | +++ b/include/hw/arm/fsl-imx31.h | ||
154 | @@ -XXX,XX +XXX,XX @@ | ||
155 | #ifndef FSL_IMX31_H | ||
156 | #define FSL_IMX31_H | ||
157 | |||
158 | -#include "hw/arm/arm.h" | ||
159 | +#include "hw/arm/boot.h" | ||
160 | #include "hw/intc/imx_avic.h" | ||
161 | #include "hw/misc/imx31_ccm.h" | ||
162 | #include "hw/char/imx_serial.h" | ||
163 | diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h | ||
164 | index XXXXXXX..XXXXXXX 100644 | ||
165 | --- a/include/hw/arm/fsl-imx6.h | ||
166 | +++ b/include/hw/arm/fsl-imx6.h | ||
167 | @@ -XXX,XX +XXX,XX @@ | ||
168 | #ifndef FSL_IMX6_H | ||
169 | #define FSL_IMX6_H | ||
170 | |||
171 | -#include "hw/arm/arm.h" | ||
172 | +#include "hw/arm/boot.h" | ||
173 | #include "hw/cpu/a9mpcore.h" | ||
174 | #include "hw/misc/imx6_ccm.h" | ||
175 | #include "hw/misc/imx6_src.h" | ||
176 | diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h | ||
177 | index XXXXXXX..XXXXXXX 100644 | ||
178 | --- a/include/hw/arm/fsl-imx6ul.h | ||
179 | +++ b/include/hw/arm/fsl-imx6ul.h | ||
180 | @@ -XXX,XX +XXX,XX @@ | ||
181 | #ifndef FSL_IMX6UL_H | ||
182 | #define FSL_IMX6UL_H | ||
183 | |||
184 | -#include "hw/arm/arm.h" | ||
185 | +#include "hw/arm/boot.h" | ||
186 | #include "hw/cpu/a15mpcore.h" | ||
187 | #include "hw/misc/imx6ul_ccm.h" | ||
188 | #include "hw/misc/imx6_src.h" | ||
189 | diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h | ||
190 | index XXXXXXX..XXXXXXX 100644 | ||
191 | --- a/include/hw/arm/fsl-imx7.h | ||
192 | +++ b/include/hw/arm/fsl-imx7.h | ||
193 | @@ -XXX,XX +XXX,XX @@ | ||
194 | #ifndef FSL_IMX7_H | ||
195 | #define FSL_IMX7_H | ||
196 | |||
197 | -#include "hw/arm/arm.h" | ||
198 | +#include "hw/arm/boot.h" | ||
199 | #include "hw/cpu/a15mpcore.h" | ||
200 | #include "hw/intc/imx_gpcv2.h" | ||
201 | #include "hw/misc/imx7_ccm.h" | ||
202 | diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h | ||
203 | index XXXXXXX..XXXXXXX 100644 | ||
204 | --- a/include/hw/arm/virt.h | ||
205 | +++ b/include/hw/arm/virt.h | ||
206 | @@ -XXX,XX +XXX,XX @@ | ||
207 | #include "exec/hwaddr.h" | ||
208 | #include "qemu/notify.h" | ||
209 | #include "hw/boards.h" | ||
210 | -#include "hw/arm/arm.h" | ||
211 | +#include "hw/arm/boot.h" | ||
212 | #include "hw/block/flash.h" | ||
213 | #include "sysemu/kvm.h" | ||
214 | #include "hw/intc/arm_gicv3_common.h" | ||
215 | diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h | ||
216 | index XXXXXXX..XXXXXXX 100644 | ||
217 | --- a/include/hw/arm/xlnx-versal.h | ||
218 | +++ b/include/hw/arm/xlnx-versal.h | ||
219 | @@ -XXX,XX +XXX,XX @@ | ||
220 | #define XLNX_VERSAL_H | ||
221 | |||
222 | #include "hw/sysbus.h" | ||
223 | -#include "hw/arm/arm.h" | ||
224 | +#include "hw/arm/boot.h" | ||
225 | #include "hw/intc/arm_gicv3.h" | ||
226 | |||
227 | #define TYPE_XLNX_VERSAL "xlnx-versal" | ||
228 | diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h | ||
229 | index XXXXXXX..XXXXXXX 100644 | ||
230 | --- a/include/hw/arm/xlnx-zynqmp.h | ||
231 | +++ b/include/hw/arm/xlnx-zynqmp.h | ||
232 | @@ -XXX,XX +XXX,XX @@ | ||
233 | #ifndef XLNX_ZYNQMP_H | ||
234 | |||
235 | #include "qemu-common.h" | ||
236 | -#include "hw/arm/arm.h" | ||
237 | +#include "hw/arm/boot.h" | ||
238 | #include "hw/intc/arm_gic.h" | ||
239 | #include "hw/net/cadence_gem.h" | ||
240 | #include "hw/char/cadence_uart.h" | ||
241 | diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c | ||
242 | index XXXXXXX..XXXXXXX 100644 | ||
243 | --- a/hw/arm/armsse.c | ||
244 | +++ b/hw/arm/armsse.c | ||
245 | @@ -XXX,XX +XXX,XX @@ | ||
246 | #include "hw/sysbus.h" | ||
247 | #include "hw/registerfields.h" | ||
248 | #include "hw/arm/armsse.h" | ||
249 | -#include "hw/arm/arm.h" | ||
250 | +#include "hw/arm/boot.h" | ||
251 | |||
252 | /* Format of the System Information block SYS_CONFIG register */ | ||
253 | typedef enum SysConfigFormat { | ||
254 | diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c | ||
255 | index XXXXXXX..XXXXXXX 100644 | ||
256 | --- a/hw/arm/armv7m.c | ||
257 | +++ b/hw/arm/armv7m.c | ||
258 | @@ -XXX,XX +XXX,XX @@ | ||
259 | #include "qemu-common.h" | ||
260 | #include "cpu.h" | ||
261 | #include "hw/sysbus.h" | ||
262 | -#include "hw/arm/arm.h" | ||
263 | +#include "hw/arm/boot.h" | ||
264 | #include "hw/loader.h" | ||
265 | #include "elf.h" | ||
266 | #include "sysemu/qtest.h" | ||
267 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c | ||
268 | index XXXXXXX..XXXXXXX 100644 | ||
269 | --- a/hw/arm/aspeed.c | ||
270 | +++ b/hw/arm/aspeed.c | ||
271 | @@ -XXX,XX +XXX,XX @@ | ||
272 | #include "qemu-common.h" | ||
273 | #include "cpu.h" | ||
274 | #include "exec/address-spaces.h" | ||
275 | -#include "hw/arm/arm.h" | ||
276 | +#include "hw/arm/boot.h" | ||
277 | #include "hw/arm/aspeed.h" | ||
278 | #include "hw/arm/aspeed_soc.h" | ||
279 | #include "hw/boards.h" | ||
280 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | 26 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c |
281 | index XXXXXXX..XXXXXXX 100644 | 27 | index XXXXXXX..XXXXXXX 100644 |
282 | --- a/hw/arm/boot.c | 28 | --- a/hw/arm/boot.c |
283 | +++ b/hw/arm/boot.c | 29 | +++ b/hw/arm/boot.c |
284 | @@ -XXX,XX +XXX,XX @@ | 30 | @@ -XXX,XX +XXX,XX @@ static void do_cpu_reset(void *opaque) |
285 | #include "qapi/error.h" | 31 | (cs != first_cpu || !info->secure_board_setup)) { |
286 | #include <libfdt.h> | 32 | /* Linux expects non-secure state */ |
287 | #include "hw/hw.h" | 33 | env->cp15.scr_el3 |= SCR_NS; |
288 | -#include "hw/arm/arm.h" | 34 | + /* Set NSACR.{CP11,CP10} so NS can access the FPU */ |
289 | +#include "hw/arm/boot.h" | 35 | + env->cp15.nsacr |= 3 << 10; |
290 | #include "hw/arm/linux-boot-if.h" | 36 | } |
291 | #include "sysemu/kvm.h" | 37 | } |
292 | #include "sysemu/sysemu.h" | 38 | |
293 | diff --git a/hw/arm/collie.c b/hw/arm/collie.c | ||
294 | index XXXXXXX..XXXXXXX 100644 | ||
295 | --- a/hw/arm/collie.c | ||
296 | +++ b/hw/arm/collie.c | ||
297 | @@ -XXX,XX +XXX,XX @@ | ||
298 | #include "hw/sysbus.h" | ||
299 | #include "hw/boards.h" | ||
300 | #include "strongarm.h" | ||
301 | -#include "hw/arm/arm.h" | ||
302 | +#include "hw/arm/boot.h" | ||
303 | #include "hw/block/flash.h" | ||
304 | #include "exec/address-spaces.h" | ||
305 | #include "cpu.h" | ||
306 | diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c | ||
307 | index XXXXXXX..XXXXXXX 100644 | ||
308 | --- a/hw/arm/exynos4210.c | ||
309 | +++ b/hw/arm/exynos4210.c | ||
310 | @@ -XXX,XX +XXX,XX @@ | ||
311 | #include "hw/boards.h" | ||
312 | #include "sysemu/sysemu.h" | ||
313 | #include "hw/sysbus.h" | ||
314 | -#include "hw/arm/arm.h" | ||
315 | +#include "hw/arm/boot.h" | ||
316 | #include "hw/loader.h" | ||
317 | #include "hw/arm/exynos4210.h" | ||
318 | #include "hw/sd/sdhci.h" | ||
319 | diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c | ||
320 | index XXXXXXX..XXXXXXX 100644 | ||
321 | --- a/hw/arm/exynos4_boards.c | ||
322 | +++ b/hw/arm/exynos4_boards.c | ||
323 | @@ -XXX,XX +XXX,XX @@ | ||
324 | #include "sysemu/sysemu.h" | ||
325 | #include "hw/sysbus.h" | ||
326 | #include "net/net.h" | ||
327 | -#include "hw/arm/arm.h" | ||
328 | +#include "hw/arm/boot.h" | ||
329 | #include "exec/address-spaces.h" | ||
330 | #include "hw/arm/exynos4210.h" | ||
331 | #include "hw/net/lan9118.h" | ||
332 | diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c | ||
333 | index XXXXXXX..XXXXXXX 100644 | ||
334 | --- a/hw/arm/highbank.c | ||
335 | +++ b/hw/arm/highbank.c | ||
336 | @@ -XXX,XX +XXX,XX @@ | ||
337 | #include "qemu/osdep.h" | ||
338 | #include "qapi/error.h" | ||
339 | #include "hw/sysbus.h" | ||
340 | -#include "hw/arm/arm.h" | ||
341 | +#include "hw/arm/boot.h" | ||
342 | #include "hw/loader.h" | ||
343 | #include "net/net.h" | ||
344 | #include "sysemu/kvm.h" | ||
345 | diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c | ||
346 | index XXXXXXX..XXXXXXX 100644 | ||
347 | --- a/hw/arm/integratorcp.c | ||
348 | +++ b/hw/arm/integratorcp.c | ||
349 | @@ -XXX,XX +XXX,XX @@ | ||
350 | #include "cpu.h" | ||
351 | #include "hw/sysbus.h" | ||
352 | #include "hw/boards.h" | ||
353 | -#include "hw/arm/arm.h" | ||
354 | +#include "hw/arm/boot.h" | ||
355 | #include "hw/misc/arm_integrator_debug.h" | ||
356 | #include "hw/net/smc91c111.h" | ||
357 | #include "net/net.h" | ||
358 | diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c | ||
359 | index XXXXXXX..XXXXXXX 100644 | ||
360 | --- a/hw/arm/mainstone.c | ||
361 | +++ b/hw/arm/mainstone.c | ||
362 | @@ -XXX,XX +XXX,XX @@ | ||
363 | #include "qapi/error.h" | ||
364 | #include "hw/hw.h" | ||
365 | #include "hw/arm/pxa.h" | ||
366 | -#include "hw/arm/arm.h" | ||
367 | +#include "hw/arm/boot.h" | ||
368 | #include "net/net.h" | ||
369 | #include "hw/net/smc91c111.h" | ||
370 | #include "hw/boards.h" | ||
371 | diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c | ||
372 | index XXXXXXX..XXXXXXX 100644 | ||
373 | --- a/hw/arm/microbit.c | ||
374 | +++ b/hw/arm/microbit.c | ||
375 | @@ -XXX,XX +XXX,XX @@ | ||
376 | #include "qemu/osdep.h" | ||
377 | #include "qapi/error.h" | ||
378 | #include "hw/boards.h" | ||
379 | -#include "hw/arm/arm.h" | ||
380 | +#include "hw/arm/boot.h" | ||
381 | #include "sysemu/sysemu.h" | ||
382 | #include "exec/address-spaces.h" | ||
383 | |||
384 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c | ||
385 | index XXXXXXX..XXXXXXX 100644 | ||
386 | --- a/hw/arm/mps2-tz.c | ||
387 | +++ b/hw/arm/mps2-tz.c | ||
388 | @@ -XXX,XX +XXX,XX @@ | ||
389 | #include "qemu/osdep.h" | ||
390 | #include "qapi/error.h" | ||
391 | #include "qemu/error-report.h" | ||
392 | -#include "hw/arm/arm.h" | ||
393 | +#include "hw/arm/boot.h" | ||
394 | #include "hw/arm/armv7m.h" | ||
395 | #include "hw/or-irq.h" | ||
396 | #include "hw/boards.h" | ||
397 | diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c | ||
398 | index XXXXXXX..XXXXXXX 100644 | ||
399 | --- a/hw/arm/mps2.c | ||
400 | +++ b/hw/arm/mps2.c | ||
401 | @@ -XXX,XX +XXX,XX @@ | ||
402 | #include "qemu/osdep.h" | ||
403 | #include "qapi/error.h" | ||
404 | #include "qemu/error-report.h" | ||
405 | -#include "hw/arm/arm.h" | ||
406 | +#include "hw/arm/boot.h" | ||
407 | #include "hw/arm/armv7m.h" | ||
408 | #include "hw/or-irq.h" | ||
409 | #include "hw/boards.h" | ||
410 | diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c | ||
411 | index XXXXXXX..XXXXXXX 100644 | ||
412 | --- a/hw/arm/msf2-soc.c | ||
413 | +++ b/hw/arm/msf2-soc.c | ||
414 | @@ -XXX,XX +XXX,XX @@ | ||
415 | #include "qemu/units.h" | ||
416 | #include "qapi/error.h" | ||
417 | #include "qemu-common.h" | ||
418 | -#include "hw/arm/arm.h" | ||
419 | #include "exec/address-spaces.h" | ||
420 | #include "hw/char/serial.h" | ||
421 | #include "hw/boards.h" | ||
422 | diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c | ||
423 | index XXXXXXX..XXXXXXX 100644 | ||
424 | --- a/hw/arm/msf2-som.c | ||
425 | +++ b/hw/arm/msf2-som.c | ||
426 | @@ -XXX,XX +XXX,XX @@ | ||
427 | #include "qapi/error.h" | ||
428 | #include "qemu/error-report.h" | ||
429 | #include "hw/boards.h" | ||
430 | -#include "hw/arm/arm.h" | ||
431 | +#include "hw/arm/boot.h" | ||
432 | #include "exec/address-spaces.h" | ||
433 | #include "hw/arm/msf2-soc.h" | ||
434 | #include "cpu.h" | ||
435 | diff --git a/hw/arm/musca.c b/hw/arm/musca.c | ||
436 | index XXXXXXX..XXXXXXX 100644 | ||
437 | --- a/hw/arm/musca.c | ||
438 | +++ b/hw/arm/musca.c | ||
439 | @@ -XXX,XX +XXX,XX @@ | ||
440 | #include "qapi/error.h" | ||
441 | #include "exec/address-spaces.h" | ||
442 | #include "sysemu/sysemu.h" | ||
443 | -#include "hw/arm/arm.h" | ||
444 | +#include "hw/arm/boot.h" | ||
445 | #include "hw/arm/armsse.h" | ||
446 | #include "hw/boards.h" | ||
447 | #include "hw/char/pl011.h" | ||
448 | diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c | ||
449 | index XXXXXXX..XXXXXXX 100644 | ||
450 | --- a/hw/arm/musicpal.c | ||
451 | +++ b/hw/arm/musicpal.c | ||
452 | @@ -XXX,XX +XXX,XX @@ | ||
453 | #include "qemu-common.h" | ||
454 | #include "cpu.h" | ||
455 | #include "hw/sysbus.h" | ||
456 | -#include "hw/arm/arm.h" | ||
457 | +#include "hw/arm/boot.h" | ||
458 | #include "net/net.h" | ||
459 | #include "sysemu/sysemu.h" | ||
460 | #include "hw/boards.h" | ||
461 | diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c | ||
462 | index XXXXXXX..XXXXXXX 100644 | ||
463 | --- a/hw/arm/netduino2.c | ||
464 | +++ b/hw/arm/netduino2.c | ||
465 | @@ -XXX,XX +XXX,XX @@ | ||
466 | #include "hw/boards.h" | ||
467 | #include "qemu/error-report.h" | ||
468 | #include "hw/arm/stm32f205_soc.h" | ||
469 | -#include "hw/arm/arm.h" | ||
470 | +#include "hw/arm/boot.h" | ||
471 | |||
472 | static void netduino2_init(MachineState *machine) | ||
473 | { | ||
474 | diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c | ||
475 | index XXXXXXX..XXXXXXX 100644 | ||
476 | --- a/hw/arm/nrf51_soc.c | ||
477 | +++ b/hw/arm/nrf51_soc.c | ||
478 | @@ -XXX,XX +XXX,XX @@ | ||
479 | #include "qemu/osdep.h" | ||
480 | #include "qapi/error.h" | ||
481 | #include "qemu-common.h" | ||
482 | -#include "hw/arm/arm.h" | ||
483 | +#include "hw/arm/boot.h" | ||
484 | #include "hw/sysbus.h" | ||
485 | #include "hw/boards.h" | ||
486 | #include "hw/misc/unimp.h" | ||
487 | diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c | ||
488 | index XXXXXXX..XXXXXXX 100644 | ||
489 | --- a/hw/arm/nseries.c | ||
490 | +++ b/hw/arm/nseries.c | ||
491 | @@ -XXX,XX +XXX,XX @@ | ||
492 | #include "qemu/bswap.h" | ||
493 | #include "sysemu/sysemu.h" | ||
494 | #include "hw/arm/omap.h" | ||
495 | -#include "hw/arm/arm.h" | ||
496 | +#include "hw/arm/boot.h" | ||
497 | #include "hw/irq.h" | ||
498 | #include "ui/console.h" | ||
499 | #include "hw/boards.h" | ||
500 | diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c | ||
501 | index XXXXXXX..XXXXXXX 100644 | ||
502 | --- a/hw/arm/omap1.c | ||
503 | +++ b/hw/arm/omap1.c | ||
504 | @@ -XXX,XX +XXX,XX @@ | ||
505 | #include "cpu.h" | ||
506 | #include "hw/boards.h" | ||
507 | #include "hw/hw.h" | ||
508 | -#include "hw/arm/arm.h" | ||
509 | +#include "hw/arm/boot.h" | ||
510 | #include "hw/arm/omap.h" | ||
511 | #include "sysemu/sysemu.h" | ||
512 | #include "hw/arm/soc_dma.h" | ||
513 | diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c | ||
514 | index XXXXXXX..XXXXXXX 100644 | ||
515 | --- a/hw/arm/omap2.c | ||
516 | +++ b/hw/arm/omap2.c | ||
517 | @@ -XXX,XX +XXX,XX @@ | ||
518 | #include "sysemu/qtest.h" | ||
519 | #include "hw/boards.h" | ||
520 | #include "hw/hw.h" | ||
521 | -#include "hw/arm/arm.h" | ||
522 | +#include "hw/arm/boot.h" | ||
523 | #include "hw/arm/omap.h" | ||
524 | #include "sysemu/sysemu.h" | ||
525 | #include "qemu/timer.h" | ||
526 | diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c | ||
527 | index XXXXXXX..XXXXXXX 100644 | ||
528 | --- a/hw/arm/omap_sx1.c | ||
529 | +++ b/hw/arm/omap_sx1.c | ||
530 | @@ -XXX,XX +XXX,XX @@ | ||
531 | #include "ui/console.h" | ||
532 | #include "hw/arm/omap.h" | ||
533 | #include "hw/boards.h" | ||
534 | -#include "hw/arm/arm.h" | ||
535 | +#include "hw/arm/boot.h" | ||
536 | #include "hw/block/flash.h" | ||
537 | #include "sysemu/qtest.h" | ||
538 | #include "exec/address-spaces.h" | ||
539 | diff --git a/hw/arm/palm.c b/hw/arm/palm.c | ||
540 | index XXXXXXX..XXXXXXX 100644 | ||
541 | --- a/hw/arm/palm.c | ||
542 | +++ b/hw/arm/palm.c | ||
543 | @@ -XXX,XX +XXX,XX @@ | ||
544 | #include "ui/console.h" | ||
545 | #include "hw/arm/omap.h" | ||
546 | #include "hw/boards.h" | ||
547 | -#include "hw/arm/arm.h" | ||
548 | +#include "hw/arm/boot.h" | ||
549 | #include "hw/input/tsc2xxx.h" | ||
550 | #include "hw/loader.h" | ||
551 | #include "exec/address-spaces.h" | ||
552 | diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c | ||
553 | index XXXXXXX..XXXXXXX 100644 | ||
554 | --- a/hw/arm/raspi.c | ||
555 | +++ b/hw/arm/raspi.c | ||
556 | @@ -XXX,XX +XXX,XX @@ | ||
557 | #include "qemu/error-report.h" | ||
558 | #include "hw/boards.h" | ||
559 | #include "hw/loader.h" | ||
560 | -#include "hw/arm/arm.h" | ||
561 | +#include "hw/arm/boot.h" | ||
562 | #include "sysemu/sysemu.h" | ||
563 | |||
564 | #define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS */ | ||
565 | diff --git a/hw/arm/realview.c b/hw/arm/realview.c | ||
566 | index XXXXXXX..XXXXXXX 100644 | ||
567 | --- a/hw/arm/realview.c | ||
568 | +++ b/hw/arm/realview.c | ||
569 | @@ -XXX,XX +XXX,XX @@ | ||
570 | #include "qemu-common.h" | ||
571 | #include "cpu.h" | ||
572 | #include "hw/sysbus.h" | ||
573 | -#include "hw/arm/arm.h" | ||
574 | +#include "hw/arm/boot.h" | ||
575 | #include "hw/arm/primecell.h" | ||
576 | #include "hw/net/lan9118.h" | ||
577 | #include "hw/net/smc91c111.h" | ||
578 | diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c | ||
579 | index XXXXXXX..XXXXXXX 100644 | ||
580 | --- a/hw/arm/spitz.c | ||
581 | +++ b/hw/arm/spitz.c | ||
582 | @@ -XXX,XX +XXX,XX @@ | ||
583 | #include "qapi/error.h" | ||
584 | #include "hw/hw.h" | ||
585 | #include "hw/arm/pxa.h" | ||
586 | -#include "hw/arm/arm.h" | ||
587 | +#include "hw/arm/boot.h" | ||
588 | #include "sysemu/sysemu.h" | ||
589 | #include "hw/pcmcia.h" | ||
590 | #include "hw/i2c/i2c.h" | ||
591 | diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c | ||
592 | index XXXXXXX..XXXXXXX 100644 | ||
593 | --- a/hw/arm/stellaris.c | ||
594 | +++ b/hw/arm/stellaris.c | ||
595 | @@ -XXX,XX +XXX,XX @@ | ||
596 | #include "qapi/error.h" | ||
597 | #include "hw/sysbus.h" | ||
598 | #include "hw/ssi/ssi.h" | ||
599 | -#include "hw/arm/arm.h" | ||
600 | +#include "hw/arm/boot.h" | ||
601 | #include "qemu/timer.h" | ||
602 | #include "hw/i2c/i2c.h" | ||
603 | #include "net/net.h" | ||
604 | diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c | ||
605 | index XXXXXXX..XXXXXXX 100644 | ||
606 | --- a/hw/arm/stm32f205_soc.c | ||
607 | +++ b/hw/arm/stm32f205_soc.c | ||
608 | @@ -XXX,XX +XXX,XX @@ | ||
609 | #include "qemu/osdep.h" | ||
610 | #include "qapi/error.h" | ||
611 | #include "qemu-common.h" | ||
612 | -#include "hw/arm/arm.h" | ||
613 | +#include "hw/arm/boot.h" | ||
614 | #include "exec/address-spaces.h" | ||
615 | #include "hw/arm/stm32f205_soc.h" | ||
616 | |||
617 | diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c | ||
618 | index XXXXXXX..XXXXXXX 100644 | ||
619 | --- a/hw/arm/strongarm.c | ||
620 | +++ b/hw/arm/strongarm.c | ||
621 | @@ -XXX,XX +XXX,XX @@ | ||
622 | #include "hw/sysbus.h" | ||
623 | #include "strongarm.h" | ||
624 | #include "qemu/error-report.h" | ||
625 | -#include "hw/arm/arm.h" | ||
626 | +#include "hw/arm/boot.h" | ||
627 | #include "chardev/char-fe.h" | ||
628 | #include "chardev/char-serial.h" | ||
629 | #include "sysemu/sysemu.h" | ||
630 | diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c | ||
631 | index XXXXXXX..XXXXXXX 100644 | ||
632 | --- a/hw/arm/tosa.c | ||
633 | +++ b/hw/arm/tosa.c | ||
634 | @@ -XXX,XX +XXX,XX @@ | ||
635 | #include "qapi/error.h" | ||
636 | #include "hw/hw.h" | ||
637 | #include "hw/arm/pxa.h" | ||
638 | -#include "hw/arm/arm.h" | ||
639 | +#include "hw/arm/boot.h" | ||
640 | #include "hw/arm/sharpsl.h" | ||
641 | #include "hw/pcmcia.h" | ||
642 | #include "hw/boards.h" | ||
643 | diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c | ||
644 | index XXXXXXX..XXXXXXX 100644 | ||
645 | --- a/hw/arm/versatilepb.c | ||
646 | +++ b/hw/arm/versatilepb.c | ||
647 | @@ -XXX,XX +XXX,XX @@ | ||
648 | #include "qemu-common.h" | ||
649 | #include "cpu.h" | ||
650 | #include "hw/sysbus.h" | ||
651 | -#include "hw/arm/arm.h" | ||
652 | +#include "hw/arm/boot.h" | ||
653 | #include "hw/net/smc91c111.h" | ||
654 | #include "net/net.h" | ||
655 | #include "sysemu/sysemu.h" | ||
656 | diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c | ||
657 | index XXXXXXX..XXXXXXX 100644 | ||
658 | --- a/hw/arm/vexpress.c | ||
659 | +++ b/hw/arm/vexpress.c | ||
660 | @@ -XXX,XX +XXX,XX @@ | ||
661 | #include "qemu-common.h" | ||
662 | #include "cpu.h" | ||
663 | #include "hw/sysbus.h" | ||
664 | -#include "hw/arm/arm.h" | ||
665 | +#include "hw/arm/boot.h" | ||
666 | #include "hw/arm/primecell.h" | ||
667 | #include "hw/net/lan9118.h" | ||
668 | #include "hw/i2c/i2c.h" | ||
669 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
670 | index XXXXXXX..XXXXXXX 100644 | ||
671 | --- a/hw/arm/virt.c | ||
672 | +++ b/hw/arm/virt.c | ||
673 | @@ -XXX,XX +XXX,XX @@ | ||
674 | #include "qemu/option.h" | ||
675 | #include "qapi/error.h" | ||
676 | #include "hw/sysbus.h" | ||
677 | -#include "hw/arm/arm.h" | ||
678 | +#include "hw/arm/boot.h" | ||
679 | #include "hw/arm/primecell.h" | ||
680 | #include "hw/arm/virt.h" | ||
681 | #include "hw/block/flash.h" | ||
682 | diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c | ||
683 | index XXXXXXX..XXXXXXX 100644 | ||
684 | --- a/hw/arm/xilinx_zynq.c | ||
685 | +++ b/hw/arm/xilinx_zynq.c | ||
686 | @@ -XXX,XX +XXX,XX @@ | ||
687 | #include "qemu-common.h" | ||
688 | #include "cpu.h" | ||
689 | #include "hw/sysbus.h" | ||
690 | -#include "hw/arm/arm.h" | ||
691 | +#include "hw/arm/boot.h" | ||
692 | #include "net/net.h" | ||
693 | #include "exec/address-spaces.h" | ||
694 | #include "sysemu/sysemu.h" | ||
695 | diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c | ||
696 | index XXXXXXX..XXXXXXX 100644 | ||
697 | --- a/hw/arm/xlnx-versal.c | ||
698 | +++ b/hw/arm/xlnx-versal.c | ||
699 | @@ -XXX,XX +XXX,XX @@ | ||
700 | #include "net/net.h" | ||
701 | #include "sysemu/sysemu.h" | ||
702 | #include "sysemu/kvm.h" | ||
703 | -#include "hw/arm/arm.h" | ||
704 | +#include "hw/arm/boot.h" | ||
705 | #include "kvm_arm.h" | ||
706 | #include "hw/misc/unimp.h" | ||
707 | #include "hw/intc/arm_gicv3_common.h" | ||
708 | diff --git a/hw/arm/z2.c b/hw/arm/z2.c | ||
709 | index XXXXXXX..XXXXXXX 100644 | ||
710 | --- a/hw/arm/z2.c | ||
711 | +++ b/hw/arm/z2.c | ||
712 | @@ -XXX,XX +XXX,XX @@ | ||
713 | #include "qemu/osdep.h" | ||
714 | #include "hw/hw.h" | ||
715 | #include "hw/arm/pxa.h" | ||
716 | -#include "hw/arm/arm.h" | ||
717 | +#include "hw/arm/boot.h" | ||
718 | #include "hw/i2c/i2c.h" | ||
719 | #include "hw/ssi/ssi.h" | ||
720 | #include "hw/boards.h" | ||
721 | -- | 39 | -- |
722 | 2.20.1 | 40 | 2.20.1 |
723 | 41 | ||
724 | 42 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | In ich_vmcr_write() we enforce "writes of BPR fields to less than | ||
2 | their minimum sets them to the minimum" by doing a "read vbpr and | ||
3 | write it back" operation. A typo here meant that we weren't handling | ||
4 | writes to these fields correctly, because we were reading from VBPR0 | ||
5 | but writing to VBPR1. | ||
6 | 1 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
9 | Message-id: 20190520162809.2677-4-peter.maydell@linaro.org | ||
10 | --- | ||
11 | hw/intc/arm_gicv3_cpuif.c | 2 +- | ||
12 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
13 | |||
14 | diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/hw/intc/arm_gicv3_cpuif.c | ||
17 | +++ b/hw/intc/arm_gicv3_cpuif.c | ||
18 | @@ -XXX,XX +XXX,XX @@ static void ich_vmcr_write(CPUARMState *env, const ARMCPRegInfo *ri, | ||
19 | /* Enforce "writing BPRs to less than minimum sets them to the minimum" | ||
20 | * by reading and writing back the fields. | ||
21 | */ | ||
22 | - write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G0)); | ||
23 | + write_vbpr(cs, GICV3_G0, read_vbpr(cs, GICV3_G0)); | ||
24 | write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G1)); | ||
25 | |||
26 | gicv3_cpuif_virt_update(cs); | ||
27 | -- | ||
28 | 2.20.1 | ||
29 | |||
30 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | 1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> |
---|---|---|---|
2 | 2 | ||
3 | It eases code review, unit is explicit. | 3 | IEC binary prefixes ease code review: the unit is explicit. |
4 | 4 | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> | ||
7 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
5 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 8 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> |
6 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | 9 | Message-id: 20190923131108.21459-1-philmd@redhat.com |
7 | Message-id: 20190520214342.13709-3-philmd@redhat.com | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 11 | --- |
10 | hw/arm/exynos4_boards.c | 5 +++-- | 12 | hw/arm/boot.c | 10 +++++----- |
11 | 1 file changed, 3 insertions(+), 2 deletions(-) | 13 | 1 file changed, 5 insertions(+), 5 deletions(-) |
12 | 14 | ||
13 | diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c | 15 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c |
14 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/arm/exynos4_boards.c | 17 | --- a/hw/arm/boot.c |
16 | +++ b/hw/arm/exynos4_boards.c | 18 | +++ b/hw/arm/boot.c |
17 | @@ -XXX,XX +XXX,XX @@ | 19 | @@ -XXX,XX +XXX,XX @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, |
18 | */ | 20 | goto fail; |
19 | 21 | } | |
20 | #include "qemu/osdep.h" | 22 | |
21 | +#include "qemu/units.h" | 23 | - if (scells < 2 && binfo->ram_size >= (1ULL << 32)) { |
22 | #include "qapi/error.h" | 24 | + if (scells < 2 && binfo->ram_size >= 4 * GiB) { |
23 | #include "qemu/error-report.h" | 25 | /* This is user error so deserves a friendlier error message |
24 | #include "qemu-common.h" | 26 | * than the failure of setprop_sized_cells would provide |
25 | @@ -XXX,XX +XXX,XX @@ static int exynos4_board_smp_bootreg_addr[EXYNOS4_NUM_OF_BOARDS] = { | 27 | */ |
26 | }; | 28 | @@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, |
27 | 29 | * we might still make a bad choice here. | |
28 | static unsigned long exynos4_board_ram_size[EXYNOS4_NUM_OF_BOARDS] = { | 30 | */ |
29 | - [EXYNOS4_BOARD_NURI] = 0x40000000, | 31 | info->initrd_start = info->loader_start + |
30 | - [EXYNOS4_BOARD_SMDKC210] = 0x40000000, | 32 | - MIN(info->ram_size / 2, 128 * 1024 * 1024); |
31 | + [EXYNOS4_BOARD_NURI] = 1 * GiB, | 33 | + MIN(info->ram_size / 2, 128 * MiB); |
32 | + [EXYNOS4_BOARD_SMDKC210] = 1 * GiB, | 34 | if (image_high_addr) { |
33 | }; | 35 | info->initrd_start = MAX(info->initrd_start, image_high_addr); |
34 | 36 | } | |
35 | static struct arm_boot_info exynos4_board_binfo = { | 37 | @@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, |
38 | * | ||
39 | * Let's play safe and prealign it to 2MB to give us some space. | ||
40 | */ | ||
41 | - align = 2 * 1024 * 1024; | ||
42 | + align = 2 * MiB; | ||
43 | } else { | ||
44 | /* | ||
45 | * Some 32bit kernels will trash anything in the 4K page the | ||
46 | * initrd ends in, so make sure the DTB isn't caught up in that. | ||
47 | */ | ||
48 | - align = 4096; | ||
49 | + align = 4 * KiB; | ||
50 | } | ||
51 | |||
52 | /* Place the DTB after the initrd in memory with alignment. */ | ||
53 | @@ -XXX,XX +XXX,XX @@ static void arm_setup_direct_kernel_boot(ARMCPU *cpu, | ||
54 | info->loader_start + KERNEL_ARGS_ADDR; | ||
55 | fixupcontext[FIXUP_ARGPTR_HI] = | ||
56 | (info->loader_start + KERNEL_ARGS_ADDR) >> 32; | ||
57 | - if (info->ram_size >= (1ULL << 32)) { | ||
58 | + if (info->ram_size >= 4 * GiB) { | ||
59 | error_report("RAM size must be less than 4GB to boot" | ||
60 | " Linux kernel using ATAGS (try passing a device tree" | ||
61 | " using -dtb)"); | ||
36 | -- | 62 | -- |
37 | 2.20.1 | 63 | 2.20.1 |
38 | 64 | ||
39 | 65 | diff view generated by jsdifflib |