target/arm/cpu.h | 13 +-

target/arm/helper.h | 1 -

target/arm/kvm_arm.h | 28 ++

target/arm/translate-a64.h | 4 +-

target/arm/translate.h | 39 ++-

hw/misc/zynq_slcr.c | 450 ++++++++++++++++----------------

hw/net/imx_fec.c | 4 +

target/arm/cpu.c | 30 ++-

target/arm/cpu64.c | 31 ++-

target/arm/helper.c | 7 +

target/arm/kvm.c | 7 +

target/arm/kvm64.c | 161 +++++++-----

target/arm/op_helper.c | 15 --

target/arm/translate-a64.c | 130 ++++------

target/arm/translate-vfp.inc.c | 45 +---

target/arm/translate.c | 572 +++++++++++++++++------------------------

16 files changed, 771 insertions(+), 766 deletions(-)

From: Alex Bennée <alex.bennee@linaro.org>

While most features are now detected by probing the ID_* registers

kernels can (and do) use MIDR_EL1 for working out of they have to

apply errata. This can trip up warnings in the kernel as it tries to

work out if it should apply workarounds to features that don't

actually exist in the reported CPU type.

Avoid this problem by synthesising our own MIDR value.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20190726113950.7499-1-alex.bennee@linaro.org

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

target/arm/cpu.h | 6 ++++++

target/arm/cpu64.c | 19 +++++++++++++++++++

2 files changed, 25 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)

/*

* System register ID fields.

*/

+FIELD(MIDR_EL1, REVISION, 0, 4)

+FIELD(MIDR_EL1, PARTNUM, 4, 12)

+FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)

+FIELD(MIDR_EL1, VARIANT, 20, 4)

+FIELD(MIDR_EL1, IMPLEMENTER, 24, 8)

+

FIELD(ID_ISAR0, SWAP, 0, 4)

FIELD(ID_ISAR0, BITCOUNT, 4, 4)

FIELD(ID_ISAR0, BITFIELD, 8, 4)

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu64.c

+++ b/target/arm/cpu64.c

@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)

uint32_t u;

aarch64_a57_initfn(obj);

+ /*

+ * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real

+ * one and try to apply errata workarounds or use impdef features we

+ * don't provide.

+ * An IMPLEMENTER field of 0 means "reserved for software use";

+ * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers

+ * to see which features are present";

+ * the VARIANT, PARTNUM and REVISION fields are all implementation

+ * defined and we choose to define PARTNUM just in case guest

+ * code needs to distinguish this QEMU CPU from other software

+ * implementations, though this shouldn't be needed.

+ */

+ t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);

+ t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);

+ t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');

+ t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);

+ t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);

+ cpu->midr = t;

+

t = cpu->isar.id_aa64isar0;

t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */

t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);

--

2.20.1

From: Damien Hedde <damien.hedde@greensocs.com>

Replace the zynq_slcr registers enum and macros using the

hw/registerfields.h macros.

Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Message-id: 20190729145654.14644-30-damien.hedde@greensocs.com

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/misc/zynq_slcr.c | 450 ++++++++++++++++++++++----------------------

1 file changed, 225 insertions(+), 225 deletions(-)

diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/misc/zynq_slcr.c

+++ b/hw/misc/zynq_slcr.c

@@ -XXX,XX +XXX,XX @@

#include "sysemu/sysemu.h"

#include "qemu/log.h"

#include "qemu/module.h"

+#include "hw/registerfields.h"

#ifndef ZYNQ_SLCR_ERR_DEBUG

#define ZYNQ_SLCR_ERR_DEBUG 0

@@ -XXX,XX +XXX,XX @@

#define XILINX_LOCK_KEY 0x767b

#define XILINX_UNLOCK_KEY 0xdf0d

-#define R_PSS_RST_CTRL_SOFT_RST 0x1

+REG32(SCL, 0x000)

+REG32(LOCK, 0x004)

+REG32(UNLOCK, 0x008)

+REG32(LOCKSTA, 0x00c)

-enum {

- SCL = 0x000 / 4,

- LOCK,

- UNLOCK,

- LOCKSTA,

+REG32(ARM_PLL_CTRL, 0x100)

+REG32(DDR_PLL_CTRL, 0x104)

+REG32(IO_PLL_CTRL, 0x108)

+REG32(PLL_STATUS, 0x10c)

+REG32(ARM_PLL_CFG, 0x110)

+REG32(DDR_PLL_CFG, 0x114)

+REG32(IO_PLL_CFG, 0x118)

- ARM_PLL_CTRL = 0x100 / 4,

- DDR_PLL_CTRL,

- IO_PLL_CTRL,

- PLL_STATUS,

- ARM_PLL_CFG,

- DDR_PLL_CFG,

- IO_PLL_CFG,

-

- ARM_CLK_CTRL = 0x120 / 4,

- DDR_CLK_CTRL,

- DCI_CLK_CTRL,

- APER_CLK_CTRL,

- USB0_CLK_CTRL,

- USB1_CLK_CTRL,

- GEM0_RCLK_CTRL,

- GEM1_RCLK_CTRL,

- GEM0_CLK_CTRL,

- GEM1_CLK_CTRL,

- SMC_CLK_CTRL,

- LQSPI_CLK_CTRL,

- SDIO_CLK_CTRL,

- UART_CLK_CTRL,

- SPI_CLK_CTRL,

- CAN_CLK_CTRL,

- CAN_MIOCLK_CTRL,

- DBG_CLK_CTRL,

- PCAP_CLK_CTRL,

- TOPSW_CLK_CTRL,

+REG32(ARM_CLK_CTRL, 0x120)

+REG32(DDR_CLK_CTRL, 0x124)

+REG32(DCI_CLK_CTRL, 0x128)

+REG32(APER_CLK_CTRL, 0x12c)

+REG32(USB0_CLK_CTRL, 0x130)

+REG32(USB1_CLK_CTRL, 0x134)

+REG32(GEM0_RCLK_CTRL, 0x138)

+REG32(GEM1_RCLK_CTRL, 0x13c)

+REG32(GEM0_CLK_CTRL, 0x140)

+REG32(GEM1_CLK_CTRL, 0x144)

+REG32(SMC_CLK_CTRL, 0x148)

+REG32(LQSPI_CLK_CTRL, 0x14c)

+REG32(SDIO_CLK_CTRL, 0x150)

+REG32(UART_CLK_CTRL, 0x154)

+REG32(SPI_CLK_CTRL, 0x158)

+REG32(CAN_CLK_CTRL, 0x15c)

+REG32(CAN_MIOCLK_CTRL, 0x160)

+REG32(DBG_CLK_CTRL, 0x164)

+REG32(PCAP_CLK_CTRL, 0x168)

+REG32(TOPSW_CLK_CTRL, 0x16c)

#define FPGA_CTRL_REGS(n, start) \

- FPGA ## n ## _CLK_CTRL = (start) / 4, \

- FPGA ## n ## _THR_CTRL, \

- FPGA ## n ## _THR_CNT, \

- FPGA ## n ## _THR_STA,

- FPGA_CTRL_REGS(0, 0x170)

- FPGA_CTRL_REGS(1, 0x180)

- FPGA_CTRL_REGS(2, 0x190)

- FPGA_CTRL_REGS(3, 0x1a0)

+ REG32(FPGA ## n ## _CLK_CTRL, (start)) \

+ REG32(FPGA ## n ## _THR_CTRL, (start) + 0x4)\

+ REG32(FPGA ## n ## _THR_CNT, (start) + 0x8)\

+ REG32(FPGA ## n ## _THR_STA, (start) + 0xc)

+FPGA_CTRL_REGS(0, 0x170)

+FPGA_CTRL_REGS(1, 0x180)

+FPGA_CTRL_REGS(2, 0x190)

+FPGA_CTRL_REGS(3, 0x1a0)

- BANDGAP_TRIP = 0x1b8 / 4,

- PLL_PREDIVISOR = 0x1c0 / 4,

- CLK_621_TRUE,

+REG32(BANDGAP_TRIP, 0x1b8)

+REG32(PLL_PREDIVISOR, 0x1c0)

+REG32(CLK_621_TRUE, 0x1c4)

- PSS_RST_CTRL = 0x200 / 4,

- DDR_RST_CTRL,

- TOPSW_RESET_CTRL,

- DMAC_RST_CTRL,

- USB_RST_CTRL,

- GEM_RST_CTRL,

- SDIO_RST_CTRL,

- SPI_RST_CTRL,

- CAN_RST_CTRL,

- I2C_RST_CTRL,

- UART_RST_CTRL,

- GPIO_RST_CTRL,

- LQSPI_RST_CTRL,

- SMC_RST_CTRL,

- OCM_RST_CTRL,

- FPGA_RST_CTRL = 0x240 / 4,

- A9_CPU_RST_CTRL,

+REG32(PSS_RST_CTRL, 0x200)

+ FIELD(PSS_RST_CTRL, SOFT_RST, 0, 1)

+REG32(DDR_RST_CTRL, 0x204)

+REG32(TOPSW_RESET_CTRL, 0x208)

+REG32(DMAC_RST_CTRL, 0x20c)

+REG32(USB_RST_CTRL, 0x210)

+REG32(GEM_RST_CTRL, 0x214)

+REG32(SDIO_RST_CTRL, 0x218)

+REG32(SPI_RST_CTRL, 0x21c)

+REG32(CAN_RST_CTRL, 0x220)

+REG32(I2C_RST_CTRL, 0x224)

+REG32(UART_RST_CTRL, 0x228)

+REG32(GPIO_RST_CTRL, 0x22c)

+REG32(LQSPI_RST_CTRL, 0x230)

+REG32(SMC_RST_CTRL, 0x234)

+REG32(OCM_RST_CTRL, 0x238)

+REG32(FPGA_RST_CTRL, 0x240)

+REG32(A9_CPU_RST_CTRL, 0x244)

- RS_AWDT_CTRL = 0x24c / 4,

- RST_REASON,

+REG32(RS_AWDT_CTRL, 0x24c)

+REG32(RST_REASON, 0x250)

- REBOOT_STATUS = 0x258 / 4,

- BOOT_MODE,

+REG32(REBOOT_STATUS, 0x258)

+REG32(BOOT_MODE, 0x25c)

- APU_CTRL = 0x300 / 4,

- WDT_CLK_SEL,

+REG32(APU_CTRL, 0x300)

+REG32(WDT_CLK_SEL, 0x304)

- TZ_DMA_NS = 0x440 / 4,

- TZ_DMA_IRQ_NS,

- TZ_DMA_PERIPH_NS,

+REG32(TZ_DMA_NS, 0x440)

+REG32(TZ_DMA_IRQ_NS, 0x444)

+REG32(TZ_DMA_PERIPH_NS, 0x448)

- PSS_IDCODE = 0x530 / 4,

+REG32(PSS_IDCODE, 0x530)

- DDR_URGENT = 0x600 / 4,

- DDR_CAL_START = 0x60c / 4,

- DDR_REF_START = 0x614 / 4,

- DDR_CMD_STA,

- DDR_URGENT_SEL,

- DDR_DFI_STATUS,

+REG32(DDR_URGENT, 0x600)

+REG32(DDR_CAL_START, 0x60c)

+REG32(DDR_REF_START, 0x614)

+REG32(DDR_CMD_STA, 0x618)

+REG32(DDR_URGENT_SEL, 0x61c)

+REG32(DDR_DFI_STATUS, 0x620)

- MIO = 0x700 / 4,

+REG32(MIO, 0x700)

#define MIO_LENGTH 54

- MIO_LOOPBACK = 0x804 / 4,

- MIO_MST_TRI0,

- MIO_MST_TRI1,

+REG32(MIO_LOOPBACK, 0x804)

+REG32(MIO_MST_TRI0, 0x808)

+REG32(MIO_MST_TRI1, 0x80c)

- SD0_WP_CD_SEL = 0x830 / 4,

- SD1_WP_CD_SEL,

+REG32(SD0_WP_CD_SEL, 0x830)

+REG32(SD1_WP_CD_SEL, 0x834)

- LVL_SHFTR_EN = 0x900 / 4,

- OCM_CFG = 0x910 / 4,

+REG32(LVL_SHFTR_EN, 0x900)

+REG32(OCM_CFG, 0x910)

- CPU_RAM = 0xa00 / 4,

+REG32(CPU_RAM, 0xa00)

- IOU = 0xa30 / 4,

+REG32(IOU, 0xa30)

- DMAC_RAM = 0xa50 / 4,

+REG32(DMAC_RAM, 0xa50)

- AFI0 = 0xa60 / 4,

- AFI1 = AFI0 + 3,

- AFI2 = AFI1 + 3,

- AFI3 = AFI2 + 3,

+REG32(AFI0, 0xa60)

+REG32(AFI1, 0xa6c)

+REG32(AFI2, 0xa78)

+REG32(AFI3, 0xa84)

#define AFI_LENGTH 3

- OCM = 0xa90 / 4,

+REG32(OCM, 0xa90)

- DEVCI_RAM = 0xaa0 / 4,

+REG32(DEVCI_RAM, 0xaa0)

- CSG_RAM = 0xab0 / 4,

+REG32(CSG_RAM, 0xab0)

- GPIOB_CTRL = 0xb00 / 4,

- GPIOB_CFG_CMOS18,

- GPIOB_CFG_CMOS25,

- GPIOB_CFG_CMOS33,

- GPIOB_CFG_HSTL = 0xb14 / 4,

- GPIOB_DRVR_BIAS_CTRL,

+REG32(GPIOB_CTRL, 0xb00)

+REG32(GPIOB_CFG_CMOS18, 0xb04)

+REG32(GPIOB_CFG_CMOS25, 0xb08)

+REG32(GPIOB_CFG_CMOS33, 0xb0c)

+REG32(GPIOB_CFG_HSTL, 0xb14)

+REG32(GPIOB_DRVR_BIAS_CTRL, 0xb18)

- DDRIOB = 0xb40 / 4,

+REG32(DDRIOB, 0xb40)

#define DDRIOB_LENGTH 14

-};

#define ZYNQ_SLCR_MMIO_SIZE 0x1000

#define ZYNQ_SLCR_NUM_REGS (ZYNQ_SLCR_MMIO_SIZE / 4)

@@ -XXX,XX +XXX,XX @@ static void zynq_slcr_reset(DeviceState *d)

DB_PRINT("RESET\n");

- s->regs[LOCKSTA] = 1;

+ s->regs[R_LOCKSTA] = 1;

/* 0x100 - 0x11C */

- s->regs[ARM_PLL_CTRL] = 0x0001A008;

- s->regs[DDR_PLL_CTRL] = 0x0001A008;

- s->regs[IO_PLL_CTRL] = 0x0001A008;

- s->regs[PLL_STATUS] = 0x0000003F;

- s->regs[ARM_PLL_CFG] = 0x00014000;

- s->regs[DDR_PLL_CFG] = 0x00014000;

- s->regs[IO_PLL_CFG] = 0x00014000;

+ s->regs[R_ARM_PLL_CTRL] = 0x0001A008;

+ s->regs[R_DDR_PLL_CTRL] = 0x0001A008;

+ s->regs[R_IO_PLL_CTRL] = 0x0001A008;

+ s->regs[R_PLL_STATUS] = 0x0000003F;

+ s->regs[R_ARM_PLL_CFG] = 0x00014000;

+ s->regs[R_DDR_PLL_CFG] = 0x00014000;

+ s->regs[R_IO_PLL_CFG] = 0x00014000;

/* 0x120 - 0x16C */

- s->regs[ARM_CLK_CTRL] = 0x1F000400;

- s->regs[DDR_CLK_CTRL] = 0x18400003;

- s->regs[DCI_CLK_CTRL] = 0x01E03201;

- s->regs[APER_CLK_CTRL] = 0x01FFCCCD;

- s->regs[USB0_CLK_CTRL] = s->regs[USB1_CLK_CTRL] = 0x00101941;

- s->regs[GEM0_RCLK_CTRL] = s->regs[GEM1_RCLK_CTRL] = 0x00000001;

- s->regs[GEM0_CLK_CTRL] = s->regs[GEM1_CLK_CTRL] = 0x00003C01;

- s->regs[SMC_CLK_CTRL] = 0x00003C01;

- s->regs[LQSPI_CLK_CTRL] = 0x00002821;

- s->regs[SDIO_CLK_CTRL] = 0x00001E03;

- s->regs[UART_CLK_CTRL] = 0x00003F03;

- s->regs[SPI_CLK_CTRL] = 0x00003F03;

- s->regs[CAN_CLK_CTRL] = 0x00501903;

- s->regs[DBG_CLK_CTRL] = 0x00000F03;

- s->regs[PCAP_CLK_CTRL] = 0x00000F01;

+ s->regs[R_ARM_CLK_CTRL] = 0x1F000400;

+ s->regs[R_DDR_CLK_CTRL] = 0x18400003;

+ s->regs[R_DCI_CLK_CTRL] = 0x01E03201;

+ s->regs[R_APER_CLK_CTRL] = 0x01FFCCCD;

+ s->regs[R_USB0_CLK_CTRL] = s->regs[R_USB1_CLK_CTRL] = 0x00101941;

+ s->regs[R_GEM0_RCLK_CTRL] = s->regs[R_GEM1_RCLK_CTRL] = 0x00000001;

+ s->regs[R_GEM0_CLK_CTRL] = s->regs[R_GEM1_CLK_CTRL] = 0x00003C01;

+ s->regs[R_SMC_CLK_CTRL] = 0x00003C01;

+ s->regs[R_LQSPI_CLK_CTRL] = 0x00002821;

+ s->regs[R_SDIO_CLK_CTRL] = 0x00001E03;

+ s->regs[R_UART_CLK_CTRL] = 0x00003F03;

+ s->regs[R_SPI_CLK_CTRL] = 0x00003F03;

+ s->regs[R_CAN_CLK_CTRL] = 0x00501903;

+ s->regs[R_DBG_CLK_CTRL] = 0x00000F03;

+ s->regs[R_PCAP_CLK_CTRL] = 0x00000F01;

/* 0x170 - 0x1AC */

- s->regs[FPGA0_CLK_CTRL] = s->regs[FPGA1_CLK_CTRL] = s->regs[FPGA2_CLK_CTRL]

- = s->regs[FPGA3_CLK_CTRL] = 0x00101800;

- s->regs[FPGA0_THR_STA] = s->regs[FPGA1_THR_STA] = s->regs[FPGA2_THR_STA]

- = s->regs[FPGA3_THR_STA] = 0x00010000;

+ s->regs[R_FPGA0_CLK_CTRL] = s->regs[R_FPGA1_CLK_CTRL]

+ = s->regs[R_FPGA2_CLK_CTRL]

+ = s->regs[R_FPGA3_CLK_CTRL] = 0x00101800;

+ s->regs[R_FPGA0_THR_STA] = s->regs[R_FPGA1_THR_STA]

+ = s->regs[R_FPGA2_THR_STA]

+ = s->regs[R_FPGA3_THR_STA] = 0x00010000;

/* 0x1B0 - 0x1D8 */

- s->regs[BANDGAP_TRIP] = 0x0000001F;

- s->regs[PLL_PREDIVISOR] = 0x00000001;

- s->regs[CLK_621_TRUE] = 0x00000001;

+ s->regs[R_BANDGAP_TRIP] = 0x0000001F;

+ s->regs[R_PLL_PREDIVISOR] = 0x00000001;

+ s->regs[R_CLK_621_TRUE] = 0x00000001;

/* 0x200 - 0x25C */

- s->regs[FPGA_RST_CTRL] = 0x01F33F0F;

- s->regs[RST_REASON] = 0x00000040;

+ s->regs[R_FPGA_RST_CTRL] = 0x01F33F0F;

+ s->regs[R_RST_REASON] = 0x00000040;

- s->regs[BOOT_MODE] = 0x00000001;

+ s->regs[R_BOOT_MODE] = 0x00000001;

/* 0x700 - 0x7D4 */

for (i = 0; i < 54; i++) {

- s->regs[MIO + i] = 0x00001601;

+ s->regs[R_MIO + i] = 0x00001601;

}

for (i = 2; i <= 8; i++) {

- s->regs[MIO + i] = 0x00000601;

+ s->regs[R_MIO + i] = 0x00000601;

}

- s->regs[MIO_MST_TRI0] = s->regs[MIO_MST_TRI1] = 0xFFFFFFFF;

+ s->regs[R_MIO_MST_TRI0] = s->regs[R_MIO_MST_TRI1] = 0xFFFFFFFF;

- s->regs[CPU_RAM + 0] = s->regs[CPU_RAM + 1] = s->regs[CPU_RAM + 3]

- = s->regs[CPU_RAM + 4] = s->regs[CPU_RAM + 7]

- = 0x00010101;

- s->regs[CPU_RAM + 2] = s->regs[CPU_RAM + 5] = 0x01010101;

- s->regs[CPU_RAM + 6] = 0x00000001;

+ s->regs[R_CPU_RAM + 0] = s->regs[R_CPU_RAM + 1] = s->regs[R_CPU_RAM + 3]

+ = s->regs[R_CPU_RAM + 4] = s->regs[R_CPU_RAM + 7]

+ = 0x00010101;

+ s->regs[R_CPU_RAM + 2] = s->regs[R_CPU_RAM + 5] = 0x01010101;

+ s->regs[R_CPU_RAM + 6] = 0x00000001;

- s->regs[IOU + 0] = s->regs[IOU + 1] = s->regs[IOU + 2] = s->regs[IOU + 3]

- = 0x09090909;

- s->regs[IOU + 4] = s->regs[IOU + 5] = 0x00090909;

- s->regs[IOU + 6] = 0x00000909;

+ s->regs[R_IOU + 0] = s->regs[R_IOU + 1] = s->regs[R_IOU + 2]

+ = s->regs[R_IOU + 3] = 0x09090909;

+ s->regs[R_IOU + 4] = s->regs[R_IOU + 5] = 0x00090909;

+ s->regs[R_IOU + 6] = 0x00000909;

- s->regs[DMAC_RAM] = 0x00000009;

+ s->regs[R_DMAC_RAM] = 0x00000009;

- s->regs[AFI0 + 0] = s->regs[AFI0 + 1] = 0x09090909;

- s->regs[AFI1 + 0] = s->regs[AFI1 + 1] = 0x09090909;

- s->regs[AFI2 + 0] = s->regs[AFI2 + 1] = 0x09090909;

- s->regs[AFI3 + 0] = s->regs[AFI3 + 1] = 0x09090909;

- s->regs[AFI0 + 2] = s->regs[AFI1 + 2] = s->regs[AFI2 + 2]

- = s->regs[AFI3 + 2] = 0x00000909;

+ s->regs[R_AFI0 + 0] = s->regs[R_AFI0 + 1] = 0x09090909;

+ s->regs[R_AFI1 + 0] = s->regs[R_AFI1 + 1] = 0x09090909;

+ s->regs[R_AFI2 + 0] = s->regs[R_AFI2 + 1] = 0x09090909;

+ s->regs[R_AFI3 + 0] = s->regs[R_AFI3 + 1] = 0x09090909;

+ s->regs[R_AFI0 + 2] = s->regs[R_AFI1 + 2] = s->regs[R_AFI2 + 2]

+ = s->regs[R_AFI3 + 2] = 0x00000909;

- s->regs[OCM + 0] = 0x01010101;

- s->regs[OCM + 1] = s->regs[OCM + 2] = 0x09090909;

+ s->regs[R_OCM + 0] = 0x01010101;

+ s->regs[R_OCM + 1] = s->regs[R_OCM + 2] = 0x09090909;

- s->regs[DEVCI_RAM] = 0x00000909;

- s->regs[CSG_RAM] = 0x00000001;

+ s->regs[R_DEVCI_RAM] = 0x00000909;

+ s->regs[R_CSG_RAM] = 0x00000001;

- s->regs[DDRIOB + 0] = s->regs[DDRIOB + 1] = s->regs[DDRIOB + 2]

- = s->regs[DDRIOB + 3] = 0x00000e00;

- s->regs[DDRIOB + 4] = s->regs[DDRIOB + 5] = s->regs[DDRIOB + 6]

- = 0x00000e00;

- s->regs[DDRIOB + 12] = 0x00000021;

+ s->regs[R_DDRIOB + 0] = s->regs[R_DDRIOB + 1] = s->regs[R_DDRIOB + 2]

+ = s->regs[R_DDRIOB + 3] = 0x00000e00;

+ s->regs[R_DDRIOB + 4] = s->regs[R_DDRIOB + 5] = s->regs[R_DDRIOB + 6]

+ = 0x00000e00;

+ s->regs[R_DDRIOB + 12] = 0x00000021;

}

static bool zynq_slcr_check_offset(hwaddr offset, bool rnw)

{

switch (offset) {

- case LOCK:

- case UNLOCK:

- case DDR_CAL_START:

- case DDR_REF_START:

+ case R_LOCK:

+ case R_UNLOCK:

+ case R_DDR_CAL_START:

+ case R_DDR_REF_START:

return !rnw; /* Write only */

- case LOCKSTA:

- case FPGA0_THR_STA:

- case FPGA1_THR_STA:

- case FPGA2_THR_STA:

- case FPGA3_THR_STA:

- case BOOT_MODE:

- case PSS_IDCODE:

- case DDR_CMD_STA:

- case DDR_DFI_STATUS:

- case PLL_STATUS:

+ case R_LOCKSTA:

+ case R_FPGA0_THR_STA:

+ case R_FPGA1_THR_STA:

+ case R_FPGA2_THR_STA:

+ case R_FPGA3_THR_STA:

+ case R_BOOT_MODE:

+ case R_PSS_IDCODE:

+ case R_DDR_CMD_STA:

+ case R_DDR_DFI_STATUS:

+ case R_PLL_STATUS:

return rnw;/* read only */

- case SCL:

- case ARM_PLL_CTRL ... IO_PLL_CTRL:

- case ARM_PLL_CFG ... IO_PLL_CFG:

- case ARM_CLK_CTRL ... TOPSW_CLK_CTRL:

- case FPGA0_CLK_CTRL ... FPGA0_THR_CNT:

- case FPGA1_CLK_CTRL ... FPGA1_THR_CNT:

- case FPGA2_CLK_CTRL ... FPGA2_THR_CNT:

- case FPGA3_CLK_CTRL ... FPGA3_THR_CNT:

- case BANDGAP_TRIP:

- case PLL_PREDIVISOR:

- case CLK_621_TRUE:

- case PSS_RST_CTRL ... A9_CPU_RST_CTRL:

- case RS_AWDT_CTRL:

- case RST_REASON:

- case REBOOT_STATUS:

- case APU_CTRL:

- case WDT_CLK_SEL:

- case TZ_DMA_NS ... TZ_DMA_PERIPH_NS:

- case DDR_URGENT:

- case DDR_URGENT_SEL:

- case MIO ... MIO + MIO_LENGTH - 1:

- case MIO_LOOPBACK ... MIO_MST_TRI1:

- case SD0_WP_CD_SEL:

- case SD1_WP_CD_SEL:

- case LVL_SHFTR_EN:

- case OCM_CFG:

- case CPU_RAM:

- case IOU:

- case DMAC_RAM:

- case AFI0 ... AFI3 + AFI_LENGTH - 1:

- case OCM:

- case DEVCI_RAM:

- case CSG_RAM:

- case GPIOB_CTRL ... GPIOB_CFG_CMOS33:

- case GPIOB_CFG_HSTL:

- case GPIOB_DRVR_BIAS_CTRL:

- case DDRIOB ... DDRIOB + DDRIOB_LENGTH - 1:

+ case R_SCL:

+ case R_ARM_PLL_CTRL ... R_IO_PLL_CTRL:

+ case R_ARM_PLL_CFG ... R_IO_PLL_CFG:

+ case R_ARM_CLK_CTRL ... R_TOPSW_CLK_CTRL:

+ case R_FPGA0_CLK_CTRL ... R_FPGA0_THR_CNT:

+ case R_FPGA1_CLK_CTRL ... R_FPGA1_THR_CNT:

+ case R_FPGA2_CLK_CTRL ... R_FPGA2_THR_CNT:

+ case R_FPGA3_CLK_CTRL ... R_FPGA3_THR_CNT:

+ case R_BANDGAP_TRIP:

+ case R_PLL_PREDIVISOR:

+ case R_CLK_621_TRUE:

+ case R_PSS_RST_CTRL ... R_A9_CPU_RST_CTRL:

+ case R_RS_AWDT_CTRL:

+ case R_RST_REASON:

+ case R_REBOOT_STATUS:

+ case R_APU_CTRL:

+ case R_WDT_CLK_SEL:

+ case R_TZ_DMA_NS ... R_TZ_DMA_PERIPH_NS:

+ case R_DDR_URGENT:

+ case R_DDR_URGENT_SEL:

+ case R_MIO ... R_MIO + MIO_LENGTH - 1:

+ case R_MIO_LOOPBACK ... R_MIO_MST_TRI1:

+ case R_SD0_WP_CD_SEL:

+ case R_SD1_WP_CD_SEL:

+ case R_LVL_SHFTR_EN:

+ case R_OCM_CFG:

+ case R_CPU_RAM:

+ case R_IOU:

+ case R_DMAC_RAM:

+ case R_AFI0 ... R_AFI3 + AFI_LENGTH - 1:

+ case R_OCM:

+ case R_DEVCI_RAM:

+ case R_CSG_RAM:

+ case R_GPIOB_CTRL ... R_GPIOB_CFG_CMOS33:

+ case R_GPIOB_CFG_HSTL:

+ case R_GPIOB_DRVR_BIAS_CTRL:

+ case R_DDRIOB ... R_DDRIOB + DDRIOB_LENGTH - 1:

return true;

default:

return false;

@@ -XXX,XX +XXX,XX @@ static void zynq_slcr_write(void *opaque, hwaddr offset,

}

switch (offset) {

- case SCL:

- s->regs[SCL] = val & 0x1;

+ case R_SCL:

+ s->regs[R_SCL] = val & 0x1;

return;

- case LOCK:

+ case R_LOCK:

if ((val & 0xFFFF) == XILINX_LOCK_KEY) {

DB_PRINT("XILINX LOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,

(unsigned)val & 0xFFFF);

- s->regs[LOCKSTA] = 1;

+ s->regs[R_LOCKSTA] = 1;

} else {

DB_PRINT("WRONG XILINX LOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",

(int)offset, (unsigned)val & 0xFFFF);

}

return;

- case UNLOCK:

+ case R_UNLOCK:

if ((val & 0xFFFF) == XILINX_UNLOCK_KEY) {

DB_PRINT("XILINX UNLOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,

(unsigned)val & 0xFFFF);

- s->regs[LOCKSTA] = 0;

+ s->regs[R_LOCKSTA] = 0;

} else {

DB_PRINT("WRONG XILINX UNLOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",

(int)offset, (unsigned)val & 0xFFFF);

@@ -XXX,XX +XXX,XX @@ static void zynq_slcr_write(void *opaque, hwaddr offset,

return;

}

- if (s->regs[LOCKSTA]) {

+ if (s->regs[R_LOCKSTA]) {

qemu_log_mask(LOG_GUEST_ERROR,

"SCLR registers are locked. Unlock them first\n");

return;

@@ -XXX,XX +XXX,XX @@ static void zynq_slcr_write(void *opaque, hwaddr offset,

s->regs[offset] = val;

switch (offset) {

- case PSS_RST_CTRL:

- if (val & R_PSS_RST_CTRL_SOFT_RST) {

+ case R_PSS_RST_CTRL:

+ if (FIELD_EX32(val, PSS_RST_CTRL, SOFT_RST)) {

qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);

}

break;

--

2.20.1

From: Aaron Hill <aa1ronham@gmail.com>

This commit properly sets the ENET_BD_BDU flag once the emulated FEC controller

has finished processing the last descriptor. This is done for both transmit

and receive descriptors.

This allows the QNX 7.0.0 BSP for the Sabrelite board (which can be

found at http://blackberry.qnx.com/en/developers/bsp) to properly

control the FEC. Without this patch, the BSP ethernet driver will never

re-use FEC descriptors, as the unset ENET_BD_BDU flag will cause

it to believe that the descriptors are still in use by the NIC.

Note that Linux does not appear to use this field at all, and is

unaffected by this patch.

Without this patch, QNX will think that the NIC is still processing its

transaction descriptors, and won't send any more data over the network.

For reference:

On page 1192 of the I.MX 6DQ reference manual revision (Rev. 5, 06/2018),

which can be found at https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-6-processors/i.mx-6quad-processors-high-performance-3d-graphics-hd-video-arm-cortex-a9-core:i.MX6Q?&tab=Documentation_Tab&linkline=Application-Note

the 'BDU' field is described as follows for the 'Enhanced transmit

buffer descriptor':

'Last buffer descriptor update done. Indicates that the last BD data has been updated by

uDMA. This field is written by the user (=0) and uDMA (=1).'

The same description is used for the receive buffer descriptor.

Signed-off-by: Aaron Hill <aa1ronham@gmail.com>

Message-id: 20190805142417.10433-1-aaron.hill@alertinnovation.com

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/net/imx_fec.c | 4 ++++

1 file changed, 4 insertions(+)

diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/net/imx_fec.c

+++ b/hw/net/imx_fec.c

@@ -XXX,XX +XXX,XX @@ static void imx_enet_do_tx(IMXFECState *s, uint32_t index)

if (bd.option & ENET_BD_TX_INT) {

s->regs[ENET_EIR] |= int_txf;

}

+ /* Indicate that we've updated the last buffer descriptor. */

+ bd.last_buffer = ENET_BD_BDU;

}

if (bd.option & ENET_BD_TX_INT) {

s->regs[ENET_EIR] |= int_txb;

@@ -XXX,XX +XXX,XX @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf,

/* Last buffer in frame. */

bd.flags |= flags | ENET_BD_L;

FEC_PRINTF("rx frame flags %04x\n", bd.flags);

+ /* Indicate that we've updated the last buffer descriptor. */

+ bd.last_buffer = ENET_BD_BDU;

if (bd.option & ENET_BD_RX_INT) {

s->regs[ENET_EIR] |= ENET_INT_RXF;

}

--

2.20.1