[v3] tcg: Add CPUClass::tlb_fill

[Qemu-devel] [PATCH v3 10/27] target/mips: Pass a valid error to raise_mmu_exception for user-only

Richard Henderson posted 27 patches 6 years, 9 months ago

Diff against v1 v1 v2 v2
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Maintainers: Paolo Bonzini <pbonzini@redhat.com>, Peter Maydell <peter.maydell@linaro.org>, Marek Vasut <marex@denx.de>, Stafford Horne <shorne@gmail.com>, Anthony Green <green@moxielogic.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Cornelia Huck <cohuck@redhat.com>, Aleksandar Rikalo <arikalo@wavecomp.com>, Artyom Tarasenko <atar4qemu@gmail.com>, Laurent Vivier <laurent@vivier.eu>, Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>, Aleksandar Markovic <amarkovic@wavecomp.com>, Chris Wulff <crwulff@gmail.com>, Palmer Dabbelt <palmer@sifive.com>, David Gibson <david@gibson.dropbear.id.au>, Alistair Francis <Alistair.Francis@wdc.com>, Richard Henderson <rth@twiddle.net>, David Hildenbrand <david@redhat.com>, Max Filippov <jcmvbkbc@gmail.com>, Michael Walle <michael@walle.cc>, Eduardo Habkost <ehabkost@redhat.com>, "Edgar E. Iglesias" <edgar.iglesias@gmail.com>, Aurelien Jarno <aurelien@aurel32.net>, Guan Xuetao <gxt@mprc.pku.edu.cn>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

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[Qemu-devel] [PATCH v3 10/27] target/mips: Pass a valid error to raise_mmu_exception for user-only

Posted by Richard Henderson 6 years, 9 months ago

At present we give ret = 0, or TLBRET_MATCH.  This gets matched
by the default case, which falls through to TLBRET_BADADDR.
However, it makes more sense to use a proper value.  All of the
tlb-related exceptions are handled identically in cpu_loop.c,
so TLBRET_BADADDR is as good as any other.  Retain it.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/mips/helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/mips/helper.c b/target/mips/helper.c
index c44cdca3b5..cc7be7703a 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -884,7 +884,7 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
     int prot;
     int access_type;
 #endif
-    int ret = 0;
+    int ret = TLBRET_BADADDR;
 
 #if 0
     log_cpu_state(cs, 0);
-- 
2.17.1