[Qemu-devel] [PULL 00/15] target-arm queue
[PULL v2 00/29] target-arm queue
1
A mixed bag, all bug fixes or similar small stuff.
1
v2: drop pvpanic-pci patches.
2
2
3
thanks
3
The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c:
4
-- PMM
5
4
6
5
Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000)
7
The following changes since commit 19eb2d4e736dc895f31fbd6b520e514f10cc08e0:
8
9
Merge remote-tracking branch 'remotes/thibault/tags/samuel-thibault' into staging (2019-05-07 10:43:32 +0100)
10
6
11
are available in the Git repository at:
7
are available in the Git repository at:
12
8
13
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190507
9
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119-1
14
10
15
for you to fetch changes up to 63159601fb3e396b28da14cbb71e50ed3f5a0331:
11
for you to fetch changes up to b93f4fbdc48283a39089469c44a5529d79dc40a8:
16
12
17
target/arm: Stop using variable length array in dc_zva (2019-05-07 12:55:04 +0100)
13
docs: Build and install all the docs in a single manual (2021-01-19 15:45:14 +0000)
18
14
19
----------------------------------------------------------------
15
----------------------------------------------------------------
20
target-arm queue:
16
target-arm queue:
21
* Stop using variable length array in dc_zva
17
* Implement IMPDEF pauth algorithm
22
* Implement M-profile XPSR GE bits
18
* Support ARMv8.4-SEL2
23
* Don't enable ARMV7M_EXCP_DEBUG from reset
19
* Fix bug where we were truncating predicate vector lengths in SVE insns
24
* armv7m_nvic: NS BFAR and BFSR are RAZ/WI if BFHFNMINS == 0
20
* npcm7xx_adc-test: Fix memleak in adc_qom_set
25
* armv7m_nvic: Check subpriority in nvic_recompute_state_secure()
21
* target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
26
* fix various minor issues to allow building for Windows-on-ARM64
22
* docs: Build and install all the docs in a single manual
27
* aspeed: Set SDRAM size
28
* Allow system registers for KVM guests to be changed by QEMU code
29
* raspi: Diagnose requests for too much RAM
30
* virt: Support firmware configuration with -blockdev
31
23
32
----------------------------------------------------------------
24
----------------------------------------------------------------
33
Cao Jiaxi (4):
25
Gan Qixin (1):
34
QEMU_PACKED: Remove gcc_struct attribute in Windows non x86 targets
26
npcm7xx_adc-test: Fix memleak in adc_qom_set
35
qga: Fix mingw compilation warnings on enum conversion
36
util/cacheinfo: Use uint64_t on LLP64 model to satisfy Windows ARM64
37
osdep: Fix mingw compilation regarding stdio formats
38
27
39
Joel Stanley (1):
28
Peter Maydell (1):
40
arm: aspeed: Set SDRAM size
29
docs: Build and install all the docs in a single manual
41
30
42
Markus Armbruster (3):
31
Philippe Mathieu-Daudé (1):
43
pc: Rearrange pc_system_firmware_init()'s legacy -drive loop
32
target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
44
pflash_cfi01: New pflash_cfi01_legacy_drive()
45
hw/arm/virt: Support firmware configuration with -blockdev
46
33
47
Peter Maydell (7):
34
Richard Henderson (7):
48
hw/arm/raspi: Diagnose requests for too much RAM
35
target/arm: Implement an IMPDEF pauth algorithm
49
arm: Allow system registers for KVM guests to be changed by QEMU code
36
target/arm: Add cpu properties to control pauth
50
hw/arm/armv7m_nvic: Check subpriority in nvic_recompute_state_secure()
37
target/arm: Use object_property_add_bool for "sve" property
51
hw/intc/armv7m_nvic: NS BFAR and BFSR are RAZ/WI if BFHFNMINS == 0
38
target/arm: Introduce PREDDESC field definitions
52
hw/intc/armv7m_nvic: Don't enable ARMV7M_EXCP_DEBUG from reset
39
target/arm: Update PFIRST, PNEXT for pred_desc
53
target/arm: Implement XPSR GE bits
40
target/arm: Update ZIP, UZP, TRN for pred_desc
54
target/arm: Stop using variable length array in dc_zva
41
target/arm: Update REV, PUNPK for pred_desc
55
42
56
contrib/libvhost-user/libvhost-user.h | 2 +-
43
Rémi Denis-Courmont (19):
57
include/hw/arm/aspeed.h | 1 +
44
target/arm: remove redundant tests
58
include/hw/arm/virt.h | 2 +
45
target/arm: add arm_is_el2_enabled() helper
59
include/hw/block/flash.h | 1 +
46
target/arm: use arm_is_el2_enabled() where applicable
60
include/qemu/compiler.h | 2 +-
47
target/arm: use arm_hcr_el2_eff() where applicable
61
include/qemu/osdep.h | 10 +-
48
target/arm: factor MDCR_EL2 common handling
62
scripts/cocci-macro-file.h | 7 +-
49
target/arm: Define isar_feature function to test for presence of SEL2
63
target/arm/cpu.h | 13 ++-
50
target/arm: add 64-bit S-EL2 to EL exception table
64
hw/arm/aspeed.c | 8 ++
51
target/arm: add MMU stage 1 for Secure EL2
65
hw/arm/raspi.c | 7 ++
52
target/arm: add ARMv8.4-SEL2 system registers
66
hw/arm/virt.c | 202 ++++++++++++++++++++++------------
53
target/arm: handle VMID change in secure state
67
hw/block/pflash_cfi01.c | 28 +++++
54
target/arm: do S1_ptw_translate() before address space lookup
68
hw/i386/pc_sysfw.c | 18 +--
55
target/arm: translate NS bit in page-walks
69
hw/intc/armv7m_nvic.c | 40 ++++++-
56
target/arm: generalize 2-stage page-walk condition
70
qga/commands-win32.c | 2 +-
57
target/arm: secure stage 2 translation regime
71
target/arm/helper.c | 47 +++++++-
58
target/arm: set HPFAR_EL2.NS on secure stage 2 faults
72
target/arm/kvm.c | 8 ++
59
target/arm: revector to run-time pick target EL
73
target/arm/kvm32.c | 20 +---
60
target/arm: Implement SCR_EL2.EEL2
74
target/arm/kvm64.c | 2 +
61
target/arm: enable Secure EL2 in max CPU
75
target/arm/machine.c | 2 +-
62
target/arm: refactor vae1_tlbmask()
76
util/cacheinfo.c | 2 +-
77
21 files changed, 294 insertions(+), 130 deletions(-)
78
63
64
docs/conf.py | 46 ++++-
65
docs/devel/conf.py | 15 --
66
docs/index.html.in | 17 --
67
docs/interop/conf.py | 28 ---
68
docs/meson.build | 64 +++---
69
docs/specs/conf.py | 16 --
70
docs/system/arm/cpu-features.rst | 21 ++
71
docs/system/conf.py | 28 ---
72
docs/tools/conf.py | 37 ----
73
docs/user/conf.py | 15 --
74
include/qemu/xxhash.h | 98 +++++++++
75
target/arm/cpu-param.h | 2 +-
76
target/arm/cpu.h | 107 ++++++++--
77
target/arm/internals.h | 45 +++++
78
target/arm/cpu.c | 23 ++-
79
target/arm/cpu64.c | 65 ++++--
80
target/arm/helper-a64.c | 8 +-
81
target/arm/helper.c | 414 ++++++++++++++++++++++++++-------------
82
target/arm/m_helper.c | 2 +-
83
target/arm/monitor.c | 1 +
84
target/arm/op_helper.c | 4 +-
85
target/arm/pauth_helper.c | 27 ++-
86
target/arm/sve_helper.c | 33 ++--
87
target/arm/tlb_helper.c | 3 +
88
target/arm/translate-a64.c | 4 +
89
target/arm/translate-sve.c | 31 ++-
90
target/arm/translate.c | 36 +++-
91
tests/qtest/arm-cpu-features.c | 13 ++
92
tests/qtest/npcm7xx_adc-test.c | 1 +
93
.gitlab-ci.yml | 4 +-
94
30 files changed, 770 insertions(+), 438 deletions(-)
95
delete mode 100644 docs/devel/conf.py
96
delete mode 100644 docs/index.html.in
97
delete mode 100644 docs/interop/conf.py
98
delete mode 100644 docs/specs/conf.py
99
delete mode 100644 docs/system/conf.py
100
delete mode 100644 docs/tools/conf.py
101
delete mode 100644 docs/user/conf.py
102
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/15] pc: Rearrange pc_system_firmware_init()'s legacy -drive loop
Deleted patch
1
From: Markus Armbruster <armbru@redhat.com>
2
1
3
The loop does two things: map legacy -drive to properties, and collect
4
all the backends for use after the loop. The next patch will factor
5
out the former for reuse in hw/arm/virt.c. To make that easier,
6
rearrange the loop so it does the first thing first, and the second
7
thing second.
8
9
Signed-off-by: Markus Armbruster <armbru@redhat.com>
10
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Message-id: 20190416091348.26075-2-armbru@redhat.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/i386/pc_sysfw.c | 24 +++++++++++-------------
16
1 file changed, 11 insertions(+), 13 deletions(-)
17
18
diff --git a/hw/i386/pc_sysfw.c b/hw/i386/pc_sysfw.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/i386/pc_sysfw.c
21
+++ b/hw/i386/pc_sysfw.c
22
@@ -XXX,XX +XXX,XX @@ void pc_system_firmware_init(PCMachineState *pcms,
23
24
/* Map legacy -drive if=pflash to machine properties */
25
for (i = 0; i < ARRAY_SIZE(pcms->flash); i++) {
26
- pflash_blk[i] = pflash_cfi01_get_blk(pcms->flash[i]);
27
pflash_drv = drive_get(IF_PFLASH, 0, i);
28
- if (!pflash_drv) {
29
- continue;
30
+ if (pflash_drv) {
31
+ loc_push_none(&loc);
32
+ qemu_opts_loc_restore(pflash_drv->opts);
33
+ if (pflash_cfi01_get_blk(pcms->flash[i])) {
34
+ error_report("clashes with -machine");
35
+ exit(1);
36
+ }
37
+ qdev_prop_set_drive(DEVICE(pcms->flash[i]), "drive",
38
+ blk_by_legacy_dinfo(pflash_drv), &error_fatal);
39
+ loc_pop(&loc);
40
}
41
- loc_push_none(&loc);
42
- qemu_opts_loc_restore(pflash_drv->opts);
43
- if (pflash_blk[i]) {
44
- error_report("clashes with -machine");
45
- exit(1);
46
- }
47
- pflash_blk[i] = blk_by_legacy_dinfo(pflash_drv);
48
- qdev_prop_set_drive(DEVICE(pcms->flash[i]),
49
- "drive", pflash_blk[i], &error_fatal);
50
- loc_pop(&loc);
51
+ pflash_blk[i] = pflash_cfi01_get_blk(pcms->flash[i]);
52
}
53
54
/* Reject gaps */
55
--
56
2.20.1
57
58
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/15] pflash_cfi01: New pflash_cfi01_legacy_drive()
Deleted patch
1
From: Markus Armbruster <armbru@redhat.com>
2
1
3
Factored out of pc_system_firmware_init() so the next commit can reuse
4
it in hw/arm/virt.c.
5
6
Signed-off-by: Markus Armbruster <armbru@redhat.com>
7
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20190416091348.26075-3-armbru@redhat.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
include/hw/block/flash.h | 1 +
13
hw/block/pflash_cfi01.c | 28 ++++++++++++++++++++++++++++
14
hw/i386/pc_sysfw.c | 16 ++--------------
15
3 files changed, 31 insertions(+), 14 deletions(-)
16
17
diff --git a/include/hw/block/flash.h b/include/hw/block/flash.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/hw/block/flash.h
20
+++ b/include/hw/block/flash.h
21
@@ -XXX,XX +XXX,XX @@ PFlashCFI01 *pflash_cfi01_register(hwaddr base,
22
int be);
23
BlockBackend *pflash_cfi01_get_blk(PFlashCFI01 *fl);
24
MemoryRegion *pflash_cfi01_get_memory(PFlashCFI01 *fl);
25
+void pflash_cfi01_legacy_drive(PFlashCFI01 *dev, DriveInfo *dinfo);
26
27
/* pflash_cfi02.c */
28
29
diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c
30
index XXXXXXX..XXXXXXX 100644
31
--- a/hw/block/pflash_cfi01.c
32
+++ b/hw/block/pflash_cfi01.c
33
@@ -XXX,XX +XXX,XX @@
34
#include "qapi/error.h"
35
#include "qemu/timer.h"
36
#include "qemu/bitops.h"
37
+#include "qemu/error-report.h"
38
#include "qemu/host-utils.h"
39
#include "qemu/log.h"
40
+#include "qemu/option.h"
41
#include "hw/sysbus.h"
42
+#include "sysemu/blockdev.h"
43
#include "sysemu/sysemu.h"
44
#include "trace.h"
45
46
@@ -XXX,XX +XXX,XX @@ MemoryRegion *pflash_cfi01_get_memory(PFlashCFI01 *fl)
47
return &fl->mem;
48
}
49
50
+/*
51
+ * Handle -drive if=pflash for machines that use properties.
52
+ * If @dinfo is null, do nothing.
53
+ * Else if @fl's property "drive" is already set, fatal error.
54
+ * Else set it to the BlockBackend with @dinfo.
55
+ */
56
+void pflash_cfi01_legacy_drive(PFlashCFI01 *fl, DriveInfo *dinfo)
57
+{
58
+ Location loc;
59
+
60
+ if (!dinfo) {
61
+ return;
62
+ }
63
+
64
+ loc_push_none(&loc);
65
+ qemu_opts_loc_restore(dinfo->opts);
66
+ if (fl->blk) {
67
+ error_report("clashes with -machine");
68
+ exit(1);
69
+ }
70
+ qdev_prop_set_drive(DEVICE(fl), "drive",
71
+ blk_by_legacy_dinfo(dinfo), &error_fatal);
72
+ loc_pop(&loc);
73
+}
74
+
75
static void postload_update_cb(void *opaque, int running, RunState state)
76
{
77
PFlashCFI01 *pfl = opaque;
78
diff --git a/hw/i386/pc_sysfw.c b/hw/i386/pc_sysfw.c
79
index XXXXXXX..XXXXXXX 100644
80
--- a/hw/i386/pc_sysfw.c
81
+++ b/hw/i386/pc_sysfw.c
82
@@ -XXX,XX +XXX,XX @@ void pc_system_firmware_init(PCMachineState *pcms,
83
{
84
PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms);
85
int i;
86
- DriveInfo *pflash_drv;
87
BlockBackend *pflash_blk[ARRAY_SIZE(pcms->flash)];
88
- Location loc;
89
90
if (!pcmc->pci_enabled) {
91
old_pc_system_rom_init(rom_memory, true);
92
@@ -XXX,XX +XXX,XX @@ void pc_system_firmware_init(PCMachineState *pcms,
93
94
/* Map legacy -drive if=pflash to machine properties */
95
for (i = 0; i < ARRAY_SIZE(pcms->flash); i++) {
96
- pflash_drv = drive_get(IF_PFLASH, 0, i);
97
- if (pflash_drv) {
98
- loc_push_none(&loc);
99
- qemu_opts_loc_restore(pflash_drv->opts);
100
- if (pflash_cfi01_get_blk(pcms->flash[i])) {
101
- error_report("clashes with -machine");
102
- exit(1);
103
- }
104
- qdev_prop_set_drive(DEVICE(pcms->flash[i]), "drive",
105
- blk_by_legacy_dinfo(pflash_drv), &error_fatal);
106
- loc_pop(&loc);
107
- }
108
+ pflash_cfi01_legacy_drive(pcms->flash[i],
109
+ drive_get(IF_PFLASH, 0, i));
110
pflash_blk[i] = pflash_cfi01_get_blk(pcms->flash[i]);
111
}
112
113
--
114
2.20.1
115
116
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/15] hw/arm/virt: Support firmware configuration with -blockdev
Deleted patch
1
From: Markus Armbruster <armbru@redhat.com>
2
1
3
The ARM virt machines put firmware in flash memory. To configure it,
4
you use -drive if=pflash,unit=0,... and optionally -drive
5
if=pflash,unit=1,...
6
7
Why two -drive? This permits setting up one part of the flash memory
8
read-only, and the other part read/write. It also makes upgrading
9
firmware on the host easier. Below the hood, we get two separate
10
flash devices, because we were too lazy to improve our flash device
11
models to support sector protection.
12
13
The problem at hand is to do the same with -blockdev somehow, as one
14
more step towards deprecating -drive.
15
16
We recently solved this problem for x86 PC machines, in commit
17
ebc29e1beab. See the commit message for design rationale.
18
19
This commit solves it for ARM virt basically the same way: new machine
20
properties pflash0, pflash1 forward to the onboard flash devices'
21
properties. Requires creating the onboard devices in the
22
.instance_init() method virt_instance_init(). The existing code to
23
pick up drives defined with -drive if=pflash is replaced by code to
24
desugar into the machine properties.
25
26
There are a few behavioral differences, though:
27
28
* The flash devices are always present (x86: only present if
29
configured)
30
31
* Flash base addresses and sizes are fixed (x86: sizes depend on
32
images, mapped back to back below a fixed address)
33
34
* -bios configures contents of first pflash (x86: -bios configures ROM
35
contents)
36
37
* -bios is rejected when first pflash is also configured with -machine
38
pflash0=... (x86: bios is silently ignored then)
39
40
* -machine pflash1=... does not require -machine pflash0=... (x86: it
41
does).
42
43
The actual code is a bit simpler than for x86 mostly due to the first
44
two differences.
45
46
Before the patch, all the action is in create_flash(), called from the
47
machine's .init() method machvirt_init():
48
49
main()
50
machine_run_board_init()
51
machvirt_init()
52
create_flash()
53
create_one_flash() for flash[0]
54
create
55
configure
56
includes obeying -drive if=pflash,unit=0
57
realize
58
map
59
fall back to -bios
60
create_one_flash() for flash[1]
61
create
62
configure
63
includes obeying -drive if=pflash,unit=1
64
realize
65
map
66
update FDT
67
68
To make the machine properties work, we need to move device creation
69
to its .instance_init() method virt_instance_init().
70
71
Another complication is machvirt_init()'s computation of
72
@firmware_loaded: it predicts what create_flash() will do. Instead of
73
predicting what create_flash()'s replacement virt_firmware_init() will
74
do, I decided to have virt_firmware_init() return what it did.
75
Requires calling it a bit earlier.
76
77
Resulting call tree:
78
79
main()
80
current_machine = object_new()
81
...
82
virt_instance_init()
83
virt_flash_create()
84
virt_flash_create1() for flash[0]
85
create
86
configure: set defaults
87
become child of machine [NEW]
88
add machine prop pflash0 as alias for drive [NEW]
89
virt_flash_create1() for flash[1]
90
create
91
configure: set defaults
92
become child of machine [NEW]
93
add machine prop pflash1 as alias for drive [NEW]
94
for all machine props from the command line: machine_set_property()
95
...
96
property_set_alias() for machine props pflash0, pflash1
97
...
98
set_drive() for cfi.pflash01 prop drive
99
this is how -machine pflash0=... etc set
100
machine_run_board_init(current_machine);
101
virt_firmware_init()
102
pflash_cfi01_legacy_drive()
103
legacy -drive if=pflash,unit=0 and =1 [NEW]
104
virt_flash_map()
105
virt_flash_map1() for flash[0]
106
configure: num-blocks
107
realize
108
map
109
virt_flash_map1() for flash[1]
110
configure: num-blocks
111
realize
112
map
113
fall back to -bios
114
virt_flash_fdt()
115
update FDT
116
117
You have László to thank for making me explain this in detail.
118
119
Signed-off-by: Markus Armbruster <armbru@redhat.com>
120
Acked-by: Laszlo Ersek <lersek@redhat.com>
121
Message-id: 20190416091348.26075-4-armbru@redhat.com
122
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
123
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
124
---
125
include/hw/arm/virt.h | 2 +
126
hw/arm/virt.c | 202 +++++++++++++++++++++++++++---------------
127
2 files changed, 132 insertions(+), 72 deletions(-)
128
129
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
130
index XXXXXXX..XXXXXXX 100644
131
--- a/include/hw/arm/virt.h
132
+++ b/include/hw/arm/virt.h
133
@@ -XXX,XX +XXX,XX @@
134
#include "qemu/notify.h"
135
#include "hw/boards.h"
136
#include "hw/arm/arm.h"
137
+#include "hw/block/flash.h"
138
#include "sysemu/kvm.h"
139
#include "hw/intc/arm_gicv3_common.h"
140
141
@@ -XXX,XX +XXX,XX @@ typedef struct {
142
Notifier machine_done;
143
DeviceState *platform_bus_dev;
144
FWCfgState *fw_cfg;
145
+ PFlashCFI01 *flash[2];
146
bool secure;
147
bool highmem;
148
bool highmem_ecam;
149
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
150
index XXXXXXX..XXXXXXX 100644
151
--- a/hw/arm/virt.c
152
+++ b/hw/arm/virt.c
153
@@ -XXX,XX +XXX,XX @@
154
155
#include "qemu/osdep.h"
156
#include "qemu/units.h"
157
+#include "qemu/option.h"
158
#include "qapi/error.h"
159
#include "hw/sysbus.h"
160
#include "hw/arm/arm.h"
161
@@ -XXX,XX +XXX,XX @@ static void create_virtio_devices(const VirtMachineState *vms, qemu_irq *pic)
162
}
163
}
164
165
-static void create_one_flash(const char *name, hwaddr flashbase,
166
- hwaddr flashsize, const char *file,
167
- MemoryRegion *sysmem)
168
+#define VIRT_FLASH_SECTOR_SIZE (256 * KiB)
169
+
170
+static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms,
171
+ const char *name,
172
+ const char *alias_prop_name)
173
{
174
- /* Create and map a single flash device. We use the same
175
- * parameters as the flash devices on the Versatile Express board.
176
+ /*
177
+ * Create a single flash device. We use the same parameters as
178
+ * the flash devices on the Versatile Express board.
179
*/
180
- DriveInfo *dinfo = drive_get_next(IF_PFLASH);
181
DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01);
182
- SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
183
- const uint64_t sectorlength = 256 * 1024;
184
185
- if (dinfo) {
186
- qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
187
- &error_abort);
188
- }
189
-
190
- qdev_prop_set_uint32(dev, "num-blocks", flashsize / sectorlength);
191
- qdev_prop_set_uint64(dev, "sector-length", sectorlength);
192
+ qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE);
193
qdev_prop_set_uint8(dev, "width", 4);
194
qdev_prop_set_uint8(dev, "device-width", 2);
195
qdev_prop_set_bit(dev, "big-endian", false);
196
@@ -XXX,XX +XXX,XX @@ static void create_one_flash(const char *name, hwaddr flashbase,
197
qdev_prop_set_uint16(dev, "id2", 0x00);
198
qdev_prop_set_uint16(dev, "id3", 0x00);
199
qdev_prop_set_string(dev, "name", name);
200
- qdev_init_nofail(dev);
201
-
202
- memory_region_add_subregion(sysmem, flashbase,
203
- sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0));
204
-
205
- if (file) {
206
- char *fn;
207
- int image_size;
208
-
209
- if (drive_get(IF_PFLASH, 0, 0)) {
210
- error_report("The contents of the first flash device may be "
211
- "specified with -bios or with -drive if=pflash... "
212
- "but you cannot use both options at once");
213
- exit(1);
214
- }
215
- fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, file);
216
- if (!fn) {
217
- error_report("Could not find ROM image '%s'", file);
218
- exit(1);
219
- }
220
- image_size = load_image_mr(fn, sysbus_mmio_get_region(sbd, 0));
221
- g_free(fn);
222
- if (image_size < 0) {
223
- error_report("Could not load ROM image '%s'", file);
224
- exit(1);
225
- }
226
- }
227
+ object_property_add_child(OBJECT(vms), name, OBJECT(dev),
228
+ &error_abort);
229
+ object_property_add_alias(OBJECT(vms), alias_prop_name,
230
+ OBJECT(dev), "drive", &error_abort);
231
+ return PFLASH_CFI01(dev);
232
}
233
234
-static void create_flash(const VirtMachineState *vms,
235
- MemoryRegion *sysmem,
236
- MemoryRegion *secure_sysmem)
237
+static void virt_flash_create(VirtMachineState *vms)
238
{
239
- /* Create two flash devices to fill the VIRT_FLASH space in the memmap.
240
- * Any file passed via -bios goes in the first of these.
241
+ vms->flash[0] = virt_flash_create1(vms, "virt.flash0", "pflash0");
242
+ vms->flash[1] = virt_flash_create1(vms, "virt.flash1", "pflash1");
243
+}
244
+
245
+static void virt_flash_map1(PFlashCFI01 *flash,
246
+ hwaddr base, hwaddr size,
247
+ MemoryRegion *sysmem)
248
+{
249
+ DeviceState *dev = DEVICE(flash);
250
+
251
+ assert(size % VIRT_FLASH_SECTOR_SIZE == 0);
252
+ assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX);
253
+ qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE);
254
+ qdev_init_nofail(dev);
255
+
256
+ memory_region_add_subregion(sysmem, base,
257
+ sysbus_mmio_get_region(SYS_BUS_DEVICE(dev),
258
+ 0));
259
+}
260
+
261
+static void virt_flash_map(VirtMachineState *vms,
262
+ MemoryRegion *sysmem,
263
+ MemoryRegion *secure_sysmem)
264
+{
265
+ /*
266
+ * Map two flash devices to fill the VIRT_FLASH space in the memmap.
267
* sysmem is the system memory space. secure_sysmem is the secure view
268
* of the system, and the first flash device should be made visible only
269
* there. The second flash device is visible to both secure and nonsecure.
270
@@ -XXX,XX +XXX,XX @@ static void create_flash(const VirtMachineState *vms,
271
*/
272
hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
273
hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
274
- char *nodename;
275
276
- create_one_flash("virt.flash0", flashbase, flashsize,
277
- bios_name, secure_sysmem);
278
- create_one_flash("virt.flash1", flashbase + flashsize, flashsize,
279
- NULL, sysmem);
280
+ virt_flash_map1(vms->flash[0], flashbase, flashsize,
281
+ secure_sysmem);
282
+ virt_flash_map1(vms->flash[1], flashbase + flashsize, flashsize,
283
+ sysmem);
284
+}
285
+
286
+static void virt_flash_fdt(VirtMachineState *vms,
287
+ MemoryRegion *sysmem,
288
+ MemoryRegion *secure_sysmem)
289
+{
290
+ hwaddr flashsize = vms->memmap[VIRT_FLASH].size / 2;
291
+ hwaddr flashbase = vms->memmap[VIRT_FLASH].base;
292
+ char *nodename;
293
294
if (sysmem == secure_sysmem) {
295
/* Report both flash devices as a single node in the DT */
296
@@ -XXX,XX +XXX,XX @@ static void create_flash(const VirtMachineState *vms,
297
qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4);
298
g_free(nodename);
299
} else {
300
- /* Report the devices as separate nodes so we can mark one as
301
+ /*
302
+ * Report the devices as separate nodes so we can mark one as
303
* only visible to the secure world.
304
*/
305
nodename = g_strdup_printf("/secflash@%" PRIx64, flashbase);
306
@@ -XXX,XX +XXX,XX @@ static void create_flash(const VirtMachineState *vms,
307
}
308
}
309
310
+static bool virt_firmware_init(VirtMachineState *vms,
311
+ MemoryRegion *sysmem,
312
+ MemoryRegion *secure_sysmem)
313
+{
314
+ int i;
315
+ BlockBackend *pflash_blk0;
316
+
317
+ /* Map legacy -drive if=pflash to machine properties */
318
+ for (i = 0; i < ARRAY_SIZE(vms->flash); i++) {
319
+ pflash_cfi01_legacy_drive(vms->flash[i],
320
+ drive_get(IF_PFLASH, 0, i));
321
+ }
322
+
323
+ virt_flash_map(vms, sysmem, secure_sysmem);
324
+
325
+ pflash_blk0 = pflash_cfi01_get_blk(vms->flash[0]);
326
+
327
+ if (bios_name) {
328
+ char *fname;
329
+ MemoryRegion *mr;
330
+ int image_size;
331
+
332
+ if (pflash_blk0) {
333
+ error_report("The contents of the first flash device may be "
334
+ "specified with -bios or with -drive if=pflash... "
335
+ "but you cannot use both options at once");
336
+ exit(1);
337
+ }
338
+
339
+ /* Fall back to -bios */
340
+
341
+ fname = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
342
+ if (!fname) {
343
+ error_report("Could not find ROM image '%s'", bios_name);
344
+ exit(1);
345
+ }
346
+ mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(vms->flash[0]), 0);
347
+ image_size = load_image_mr(fname, mr);
348
+ g_free(fname);
349
+ if (image_size < 0) {
350
+ error_report("Could not load ROM image '%s'", bios_name);
351
+ exit(1);
352
+ }
353
+ }
354
+
355
+ return pflash_blk0 || bios_name;
356
+}
357
+
358
static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace *as)
359
{
360
hwaddr base = vms->memmap[VIRT_FW_CFG].base;
361
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
362
MemoryRegion *secure_sysmem = NULL;
363
int n, virt_max_cpus;
364
MemoryRegion *ram = g_new(MemoryRegion, 1);
365
- bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0);
366
+ bool firmware_loaded;
367
bool aarch64 = true;
368
369
/*
370
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
371
exit(1);
372
}
373
374
+ if (vms->secure) {
375
+ if (kvm_enabled()) {
376
+ error_report("mach-virt: KVM does not support Security extensions");
377
+ exit(1);
378
+ }
379
+
380
+ /*
381
+ * The Secure view of the world is the same as the NonSecure,
382
+ * but with a few extra devices. Create it as a container region
383
+ * containing the system memory at low priority; any secure-only
384
+ * devices go in at higher priority and take precedence.
385
+ */
386
+ secure_sysmem = g_new(MemoryRegion, 1);
387
+ memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
388
+ UINT64_MAX);
389
+ memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
390
+ }
391
+
392
+ firmware_loaded = virt_firmware_init(vms, sysmem,
393
+ secure_sysmem ?: sysmem);
394
+
395
/* If we have an EL3 boot ROM then the assumption is that it will
396
* implement PSCI itself, so disable QEMU's internal implementation
397
* so it doesn't get in the way. Instead of starting secondary
398
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
399
exit(1);
400
}
401
402
- if (vms->secure) {
403
- if (kvm_enabled()) {
404
- error_report("mach-virt: KVM does not support Security extensions");
405
- exit(1);
406
- }
407
-
408
- /* The Secure view of the world is the same as the NonSecure,
409
- * but with a few extra devices. Create it as a container region
410
- * containing the system memory at low priority; any secure-only
411
- * devices go in at higher priority and take precedence.
412
- */
413
- secure_sysmem = g_new(MemoryRegion, 1);
414
- memory_region_init(secure_sysmem, OBJECT(machine), "secure-memory",
415
- UINT64_MAX);
416
- memory_region_add_subregion_overlap(secure_sysmem, 0, sysmem, -1);
417
- }
418
-
419
create_fdt(vms);
420
421
possible_cpus = mc->possible_cpu_arch_ids(machine);
422
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
423
&machine->device_memory->mr);
424
}
425
426
- create_flash(vms, sysmem, secure_sysmem ? secure_sysmem : sysmem);
427
+ virt_flash_fdt(vms, sysmem, secure_sysmem);
428
429
create_gic(vms, pic);
430
431
@@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj)
432
NULL);
433
434
vms->irqmap = a15irqmap;
435
+
436
+ virt_flash_create(vms);
437
}
438
439
static const TypeInfo virt_machine_info = {
440
--
441
2.20.1
442
443
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/15] hw/arm/raspi: Diagnose requests for too much RAM
Deleted patch
1
The Raspberry Pi boards have a physical memory map which does
2
not allow for more than 1GB of RAM. Currently if the user tries
3
to ask for more then we fail in a confusing way:
4
1
5
$ qemu-system-aarch64 --machine raspi3 -m 8G
6
Unexpected error in visit_type_uintN() at qapi/qapi-visit-core.c:164:
7
qemu-system-aarch64: Parameter 'vcram-base' expects uint32_t
8
Aborted (core dumped)
9
10
Catch this earlier and diagnose it with a more friendly message:
11
$ qemu-system-aarch64 --machine raspi3 -m 8G
12
qemu-system-aarch64: Requested ram size is too large for this machine: maximum is 1GB
13
14
Fixes: https://bugs.launchpad.net/qemu/+bug/1794187
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com>
19
---
20
hw/arm/raspi.c | 7 +++++++
21
1 file changed, 7 insertions(+)
22
23
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
24
index XXXXXXX..XXXXXXX 100644
25
--- a/hw/arm/raspi.c
26
+++ b/hw/arm/raspi.c
27
@@ -XXX,XX +XXX,XX @@
28
*/
29
30
#include "qemu/osdep.h"
31
+#include "qemu/units.h"
32
#include "qapi/error.h"
33
#include "qemu-common.h"
34
#include "cpu.h"
35
@@ -XXX,XX +XXX,XX @@ static void raspi_init(MachineState *machine, int version)
36
BusState *bus;
37
DeviceState *carddev;
38
39
+ if (machine->ram_size > 1 * GiB) {
40
+ error_report("Requested ram size is too large for this machine: "
41
+ "maximum is 1GB");
42
+ exit(1);
43
+ }
44
+
45
object_initialize(&s->soc, sizeof(s->soc),
46
version == 3 ? TYPE_BCM2837 : TYPE_BCM2836);
47
object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc),
48
--
49
2.20.1
50
51
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/15] arm: Allow system registers for KVM guests to be changed by QEMU code
Deleted patch
1
At the moment the Arm implementations of kvm_arch_{get,put}_registers()
2
don't support having QEMU change the values of system registers
3
(aka coprocessor registers for AArch32). This is because although
4
kvm_arch_get_registers() calls write_list_to_cpustate() to
5
update the CPU state struct fields (so QEMU code can read the
6
values in the usual way), kvm_arch_put_registers() does not
7
call write_cpustate_to_list(), meaning that any changes to
8
the CPU state struct fields will not be passed back to KVM.
9
1
10
The rationale for this design is documented in a comment in the
11
AArch32 kvm_arch_put_registers() -- writing the values in the
12
cpregs list into the CPU state struct is "lossy" because the
13
write of a register might not succeed, and so if we blindly
14
copy the CPU state values back again we will incorrectly
15
change register values for the guest. The assumption was that
16
no QEMU code would need to write to the registers.
17
18
However, when we implemented debug support for KVM guests, we
19
broke that assumption: the code to handle "set the guest up
20
to take a breakpoint exception" does so by updating various
21
guest registers including ESR_EL1.
22
23
Support this by making kvm_arch_put_registers() synchronize
24
CPU state back into the list. We sync only those registers
25
where the initial write succeeds, which should be sufficient.
26
27
This commit is the same as commit 823e1b3818f9b10b824ddc which we
28
had to revert in commit 942f99c825fc94c8b1a4, except that the bug
29
which was preventing EDK2 guest firmware running has been fixed:
30
kvm_arm_reset_vcpu() now calls write_list_to_cpustate().
31
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
34
Tested-by: Eric Auger <eric.auger@redhat.com>
35
---
36
target/arm/cpu.h | 9 ++++++++-
37
target/arm/helper.c | 27 +++++++++++++++++++++++++--
38
target/arm/kvm.c | 8 ++++++++
39
target/arm/kvm32.c | 20 ++------------------
40
target/arm/kvm64.c | 2 ++
41
target/arm/machine.c | 2 +-
42
6 files changed, 46 insertions(+), 22 deletions(-)
43
44
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/cpu.h
47
+++ b/target/arm/cpu.h
48
@@ -XXX,XX +XXX,XX @@ bool write_list_to_cpustate(ARMCPU *cpu);
49
/**
50
* write_cpustate_to_list:
51
* @cpu: ARMCPU
52
+ * @kvm_sync: true if this is for syncing back to KVM
53
*
54
* For each register listed in the ARMCPU cpreg_indexes list, write
55
* its value from the ARMCPUState structure into the cpreg_values list.
56
* This is used to copy info from TCG's working data structures into
57
* KVM or for outbound migration.
58
*
59
+ * @kvm_sync is true if we are doing this in order to sync the
60
+ * register state back to KVM. In this case we will only update
61
+ * values in the list if the previous list->cpustate sync actually
62
+ * successfully wrote the CPU state. Otherwise we will keep the value
63
+ * that is in the list.
64
+ *
65
* Returns: true if all register values were read correctly,
66
* false if some register was unknown or could not be read.
67
* Note that we do not stop early on failure -- we will attempt
68
* reading all registers in the list.
69
*/
70
-bool write_cpustate_to_list(ARMCPU *cpu);
71
+bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
72
73
#define ARM_CPUID_TI915T 0x54029152
74
#define ARM_CPUID_TI925T 0x54029252
75
diff --git a/target/arm/helper.c b/target/arm/helper.c
76
index XXXXXXX..XXXXXXX 100644
77
--- a/target/arm/helper.c
78
+++ b/target/arm/helper.c
79
@@ -XXX,XX +XXX,XX @@ static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
80
return true;
81
}
82
83
-bool write_cpustate_to_list(ARMCPU *cpu)
84
+bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync)
85
{
86
/* Write the coprocessor state from cpu->env to the (index,value) list. */
87
int i;
88
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu)
89
for (i = 0; i < cpu->cpreg_array_len; i++) {
90
uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
91
const ARMCPRegInfo *ri;
92
+ uint64_t newval;
93
94
ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
95
if (!ri) {
96
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu)
97
if (ri->type & ARM_CP_NO_RAW) {
98
continue;
99
}
100
- cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
101
+
102
+ newval = read_raw_cp_reg(&cpu->env, ri);
103
+ if (kvm_sync) {
104
+ /*
105
+ * Only sync if the previous list->cpustate sync succeeded.
106
+ * Rather than tracking the success/failure state for every
107
+ * item in the list, we just recheck "does the raw write we must
108
+ * have made in write_list_to_cpustate() read back OK" here.
109
+ */
110
+ uint64_t oldval = cpu->cpreg_values[i];
111
+
112
+ if (oldval == newval) {
113
+ continue;
114
+ }
115
+
116
+ write_raw_cp_reg(&cpu->env, ri, oldval);
117
+ if (read_raw_cp_reg(&cpu->env, ri) != oldval) {
118
+ continue;
119
+ }
120
+
121
+ write_raw_cp_reg(&cpu->env, ri, newval);
122
+ }
123
+ cpu->cpreg_values[i] = newval;
124
}
125
return ok;
126
}
127
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
128
index XXXXXXX..XXXXXXX 100644
129
--- a/target/arm/kvm.c
130
+++ b/target/arm/kvm.c
131
@@ -XXX,XX +XXX,XX @@ void kvm_arm_reset_vcpu(ARMCPU *cpu)
132
fprintf(stderr, "write_kvmstate_to_list failed\n");
133
abort();
134
}
135
+ /*
136
+ * Sync the reset values also into the CPUState. This is necessary
137
+ * because the next thing we do will be a kvm_arch_put_registers()
138
+ * which will update the list values from the CPUState before copying
139
+ * the list values back to KVM. It's OK to ignore failure returns here
140
+ * for the same reason we do so in kvm_arch_get_registers().
141
+ */
142
+ write_list_to_cpustate(cpu);
143
}
144
145
/*
146
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
147
index XXXXXXX..XXXXXXX 100644
148
--- a/target/arm/kvm32.c
149
+++ b/target/arm/kvm32.c
150
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
151
return ret;
152
}
153
154
- /* Note that we do not call write_cpustate_to_list()
155
- * here, so we are only writing the tuple list back to
156
- * KVM. This is safe because nothing can change the
157
- * CPUARMState cp15 fields (in particular gdb accesses cannot)
158
- * and so there are no changes to sync. In fact syncing would
159
- * be wrong at this point: for a constant register where TCG and
160
- * KVM disagree about its value, the preceding write_list_to_cpustate()
161
- * would not have had any effect on the CPUARMState value (since the
162
- * register is read-only), and a write_cpustate_to_list() here would
163
- * then try to write the TCG value back into KVM -- this would either
164
- * fail or incorrectly change the value the guest sees.
165
- *
166
- * If we ever want to allow the user to modify cp15 registers via
167
- * the gdb stub, we would need to be more clever here (for instance
168
- * tracking the set of registers kvm_arch_get_registers() successfully
169
- * managed to update the CPUARMState with, and only allowing those
170
- * to be written back up into the kernel).
171
- */
172
+ write_cpustate_to_list(cpu, true);
173
+
174
if (!write_list_to_kvmstate(cpu, level)) {
175
return EINVAL;
176
}
177
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
178
index XXXXXXX..XXXXXXX 100644
179
--- a/target/arm/kvm64.c
180
+++ b/target/arm/kvm64.c
181
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
182
return ret;
183
}
184
185
+ write_cpustate_to_list(cpu, true);
186
+
187
if (!write_list_to_kvmstate(cpu, level)) {
188
return EINVAL;
189
}
190
diff --git a/target/arm/machine.c b/target/arm/machine.c
191
index XXXXXXX..XXXXXXX 100644
192
--- a/target/arm/machine.c
193
+++ b/target/arm/machine.c
194
@@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque)
195
abort();
196
}
197
} else {
198
- if (!write_cpustate_to_list(cpu)) {
199
+ if (!write_cpustate_to_list(cpu, false)) {
200
/* This should never fail. */
201
abort();
202
}
203
--
204
2.20.1
205
206
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/15] arm: aspeed: Set SDRAM size
Deleted patch
1
From: Joel Stanley <joel@jms.id.au>
2
1
3
We currently use Qemu's default of 128MB. As we know how much ram each
4
machine ships with, make it easier on users by setting a default.
5
6
It can still be overridden with -m on the command line.
7
8
Signed-off-by: Joel Stanley <joel@jms.id.au>
9
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20190503022958.1394-1-joel@jms.id.au
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
include/hw/arm/aspeed.h | 1 +
16
hw/arm/aspeed.c | 8 ++++++++
17
2 files changed, 9 insertions(+)
18
19
diff --git a/include/hw/arm/aspeed.h b/include/hw/arm/aspeed.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/arm/aspeed.h
22
+++ b/include/hw/arm/aspeed.h
23
@@ -XXX,XX +XXX,XX @@ typedef struct AspeedBoardConfig {
24
const char *spi_model;
25
uint32_t num_cs;
26
void (*i2c_init)(AspeedBoardState *bmc);
27
+ uint32_t ram;
28
} AspeedBoardConfig;
29
30
#define TYPE_ASPEED_MACHINE MACHINE_TYPE_NAME("aspeed")
31
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/hw/arm/aspeed.c
34
+++ b/hw/arm/aspeed.c
35
@@ -XXX,XX +XXX,XX @@
36
#include "sysemu/block-backend.h"
37
#include "hw/loader.h"
38
#include "qemu/error-report.h"
39
+#include "qemu/units.h"
40
41
static struct arm_boot_info aspeed_board_binfo = {
42
.board_id = -1, /* device-tree-only board */
43
@@ -XXX,XX +XXX,XX @@ static void aspeed_machine_class_init(ObjectClass *oc, void *data)
44
mc->no_floppy = 1;
45
mc->no_cdrom = 1;
46
mc->no_parallel = 1;
47
+ if (board->ram) {
48
+ mc->default_ram_size = board->ram;
49
+ }
50
amc->board = board;
51
}
52
53
@@ -XXX,XX +XXX,XX @@ static const AspeedBoardConfig aspeed_boards[] = {
54
.spi_model = "mx25l25635e",
55
.num_cs = 1,
56
.i2c_init = palmetto_bmc_i2c_init,
57
+ .ram = 256 * MiB,
58
}, {
59
.name = MACHINE_TYPE_NAME("ast2500-evb"),
60
.desc = "Aspeed AST2500 EVB (ARM1176)",
61
@@ -XXX,XX +XXX,XX @@ static const AspeedBoardConfig aspeed_boards[] = {
62
.spi_model = "mx25l25635e",
63
.num_cs = 1,
64
.i2c_init = ast2500_evb_i2c_init,
65
+ .ram = 512 * MiB,
66
}, {
67
.name = MACHINE_TYPE_NAME("romulus-bmc"),
68
.desc = "OpenPOWER Romulus BMC (ARM1176)",
69
@@ -XXX,XX +XXX,XX @@ static const AspeedBoardConfig aspeed_boards[] = {
70
.spi_model = "mx66l1g45g",
71
.num_cs = 2,
72
.i2c_init = romulus_bmc_i2c_init,
73
+ .ram = 512 * MiB,
74
}, {
75
.name = MACHINE_TYPE_NAME("witherspoon-bmc"),
76
.desc = "OpenPOWER Witherspoon BMC (ARM1176)",
77
@@ -XXX,XX +XXX,XX @@ static const AspeedBoardConfig aspeed_boards[] = {
78
.spi_model = "mx66l1g45g",
79
.num_cs = 2,
80
.i2c_init = witherspoon_bmc_i2c_init,
81
+ .ram = 512 * MiB,
82
},
83
};
84
85
--
86
2.20.1
87
88
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/15] QEMU_PACKED: Remove gcc_struct attribute in Windows non x86 targets
Deleted patch
1
From: Cao Jiaxi <driver1998@foxmail.com>
2
1
3
gcc_struct is for x86 only, and it generates an warning on ARM64 Clang/MinGW targets.
4
5
Signed-off-by: Cao Jiaxi <driver1998@foxmail.com>
6
Reviewed-by: Thomas Huth <thuth@redhat.com>
7
Message-id: 20190503003618.10089-1-driver1998@foxmail.com
8
[PMM: dropped the slirp change as slirp is now a submodule]
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
contrib/libvhost-user/libvhost-user.h | 2 +-
12
include/qemu/compiler.h | 2 +-
13
scripts/cocci-macro-file.h | 7 ++++++-
14
3 files changed, 8 insertions(+), 3 deletions(-)
15
16
diff --git a/contrib/libvhost-user/libvhost-user.h b/contrib/libvhost-user/libvhost-user.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/contrib/libvhost-user/libvhost-user.h
19
+++ b/contrib/libvhost-user/libvhost-user.h
20
@@ -XXX,XX +XXX,XX @@ typedef struct VhostUserInflight {
21
uint16_t queue_size;
22
} VhostUserInflight;
23
24
-#if defined(_WIN32)
25
+#if defined(_WIN32) && (defined(__x86_64__) || defined(__i386__))
26
# define VU_PACKED __attribute__((gcc_struct, packed))
27
#else
28
# define VU_PACKED __attribute__((packed))
29
diff --git a/include/qemu/compiler.h b/include/qemu/compiler.h
30
index XXXXXXX..XXXXXXX 100644
31
--- a/include/qemu/compiler.h
32
+++ b/include/qemu/compiler.h
33
@@ -XXX,XX +XXX,XX @@
34
35
#define QEMU_SENTINEL __attribute__((sentinel))
36
37
-#if defined(_WIN32)
38
+#if defined(_WIN32) && (defined(__x86_64__) || defined(__i386__))
39
# define QEMU_PACKED __attribute__((gcc_struct, packed))
40
#else
41
# define QEMU_PACKED __attribute__((packed))
42
diff --git a/scripts/cocci-macro-file.h b/scripts/cocci-macro-file.h
43
index XXXXXXX..XXXXXXX 100644
44
--- a/scripts/cocci-macro-file.h
45
+++ b/scripts/cocci-macro-file.h
46
@@ -XXX,XX +XXX,XX @@
47
#define QEMU_NORETURN __attribute__ ((__noreturn__))
48
#define QEMU_WARN_UNUSED_RESULT __attribute__((warn_unused_result))
49
#define QEMU_SENTINEL __attribute__((sentinel))
50
-#define QEMU_PACKED __attribute__((gcc_struct, packed))
51
+
52
+#if defined(_WIN32) && (defined(__x86_64__) || defined(__i386__))
53
+# define QEMU_PACKED __attribute__((gcc_struct, packed))
54
+#else
55
+# define QEMU_PACKED __attribute__((packed))
56
+#endif
57
58
#define cat(x,y) x ## y
59
#define cat2(x,y) cat(x,y)
60
--
61
2.20.1
62
63
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/15] qga: Fix mingw compilation warnings on enum conversion
Deleted patch
1
From: Cao Jiaxi <driver1998@foxmail.com>
2
1
3
The win2qemu[] is supposed to be the conversion table to convert between
4
STORAGE_BUS_TYPE in Windows SDK and GuestDiskBusType in qga.
5
6
But it was incorrectly written that it forces to set a GuestDiskBusType
7
value to STORAGE_BUS_TYPE, which generates an enum conversion warning in clang.
8
9
Suggested-by: Eric Blake <eblake@redhat.com>
10
Signed-off-by: Cao Jiaxi <driver1998@foxmail.com>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Thomas Huth <thuth@redhat.com>
13
Message-id: 20190503003650.10137-1-driver1998@foxmail.com
14
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
qga/commands-win32.c | 2 +-
19
1 file changed, 1 insertion(+), 1 deletion(-)
20
21
diff --git a/qga/commands-win32.c b/qga/commands-win32.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/qga/commands-win32.c
24
+++ b/qga/commands-win32.c
25
@@ -XXX,XX +XXX,XX @@ void qmp_guest_file_flush(int64_t handle, Error **errp)
26
27
#ifdef CONFIG_QGA_NTDDSCSI
28
29
-static STORAGE_BUS_TYPE win2qemu[] = {
30
+static GuestDiskBusType win2qemu[] = {
31
[BusTypeUnknown] = GUEST_DISK_BUS_TYPE_UNKNOWN,
32
[BusTypeScsi] = GUEST_DISK_BUS_TYPE_SCSI,
33
[BusTypeAtapi] = GUEST_DISK_BUS_TYPE_IDE,
34
--
35
2.20.1
36
37
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/15] util/cacheinfo: Use uint64_t on LLP64 model to satisfy Windows ARM64
Deleted patch
1
From: Cao Jiaxi <driver1998@foxmail.com>
2
1
3
Windows ARM64 uses LLP64 model, which breaks current assumptions.
4
5
Signed-off-by: Cao Jiaxi <driver1998@foxmail.com>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Thomas Huth <thuth@redhat.com>
8
Message-id: 20190503003707.10185-1-driver1998@foxmail.com
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
util/cacheinfo.c | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
16
diff --git a/util/cacheinfo.c b/util/cacheinfo.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/util/cacheinfo.c
19
+++ b/util/cacheinfo.c
20
@@ -XXX,XX +XXX,XX @@ static void sys_cache_info(int *isize, int *dsize)
21
static void arch_cache_info(int *isize, int *dsize)
22
{
23
if (*isize == 0 || *dsize == 0) {
24
- unsigned long ctr;
25
+ uint64_t ctr;
26
27
/* The real cache geometry is in CCSIDR_EL1/CLIDR_EL1/CSSELR_EL1,
28
but (at least under Linux) these are marked protected by the
29
--
30
2.20.1
31
32
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/15] osdep: Fix mingw compilation regarding stdio formats
Deleted patch
1
From: Cao Jiaxi <driver1998@foxmail.com>
2
1
3
I encountered the following compilation error on mingw:
4
5
/mnt/d/qemu/include/qemu/osdep.h:97:9: error: '__USE_MINGW_ANSI_STDIO' macro redefined [-Werror,-Wmacro-redefined]
6
#define __USE_MINGW_ANSI_STDIO 1
7
^
8
/mnt/d/llvm-mingw/aarch64-w64-mingw32/include/_mingw.h:433:9: note: previous definition is here
9
#define __USE_MINGW_ANSI_STDIO 0 /* was not defined so it should be 0 */
10
11
It turns out that __USE_MINGW_ANSI_STDIO must be set before any
12
system headers are included, not just before stdio.h.
13
14
Signed-off-by: Cao Jiaxi <driver1998@foxmail.com>
15
Reviewed-by: Thomas Huth <thuth@redhat.com>
16
Reviewed-by: Stefan Weil <sw@weilnetz.de>
17
Message-id: 20190503003719.10233-1-driver1998@foxmail.com
18
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
---
21
include/qemu/osdep.h | 10 +++++-----
22
1 file changed, 5 insertions(+), 5 deletions(-)
23
24
diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/include/qemu/osdep.h
27
+++ b/include/qemu/osdep.h
28
@@ -XXX,XX +XXX,XX @@ extern int daemon(int, int);
29
#endif
30
#endif
31
32
+/* enable C99/POSIX format strings (needs mingw32-runtime 3.15 or later) */
33
+#ifdef __MINGW32__
34
+#define __USE_MINGW_ANSI_STDIO 1
35
+#endif
36
+
37
#include <stdarg.h>
38
#include <stddef.h>
39
#include <stdbool.h>
40
#include <stdint.h>
41
#include <sys/types.h>
42
#include <stdlib.h>
43
-
44
-/* enable C99/POSIX format strings (needs mingw32-runtime 3.15 or later) */
45
-#ifdef __MINGW32__
46
-#define __USE_MINGW_ANSI_STDIO 1
47
-#endif
48
#include <stdio.h>
49
50
#include <string.h>
51
--
52
2.20.1
53
54
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/15] hw/arm/armv7m_nvic: Check subpriority in nvic_recompute_state_secure()
Deleted patch
1
Rule R_CQRV says that if two pending interrupts have the same
2
group priority then ties are broken by looking at the subpriority.
3
We had a comment describing this but had forgotten to actually
4
implement the subpriority comparison. Correct the omission.
5
1
6
(The further tie break rules of "lowest exception number" and
7
"secure before non-secure" are handled implicitly by the order
8
in which we iterate through the exceptions in the loops.)
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20190430131439.25251-2-peter.maydell@linaro.org
13
---
14
hw/intc/armv7m_nvic.c | 9 +++++++--
15
1 file changed, 7 insertions(+), 2 deletions(-)
16
17
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/intc/armv7m_nvic.c
20
+++ b/hw/intc/armv7m_nvic.c
21
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state_secure(NVICState *s)
22
int active_prio = NVIC_NOEXC_PRIO;
23
int pend_irq = 0;
24
bool pending_is_s_banked = false;
25
+ int pend_subprio = 0;
26
27
/* R_CQRV: precedence is by:
28
* - lowest group priority; if both the same then
29
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state_secure(NVICState *s)
30
for (i = 1; i < s->num_irq; i++) {
31
for (bank = M_REG_S; bank >= M_REG_NS; bank--) {
32
VecInfo *vec;
33
- int prio;
34
+ int prio, subprio;
35
bool targets_secure;
36
37
if (bank == M_REG_S) {
38
@@ -XXX,XX +XXX,XX @@ static void nvic_recompute_state_secure(NVICState *s)
39
}
40
41
prio = exc_group_prio(s, vec->prio, targets_secure);
42
- if (vec->enabled && vec->pending && prio < pend_prio) {
43
+ subprio = vec->prio & ~nvic_gprio_mask(s, targets_secure);
44
+ if (vec->enabled && vec->pending &&
45
+ ((prio < pend_prio) ||
46
+ (prio == pend_prio && prio >= 0 && subprio < pend_subprio))) {
47
pend_prio = prio;
48
+ pend_subprio = subprio;
49
pend_irq = i;
50
pending_is_s_banked = (bank == M_REG_S);
51
}
52
--
53
2.20.1
54
55
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/15] hw/intc/armv7m_nvic: NS BFAR and BFSR are RAZ/WI if BFHFNMINS == 0
Deleted patch
1
The non-secure versions of the BFAR and BFSR registers are
2
supposed to be RAZ/WI if AICR.BFHFNMINS == 0; we were
3
incorrectly allowing NS code to access the real values.
4
1
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20190430131439.25251-3-peter.maydell@linaro.org
8
---
9
hw/intc/armv7m_nvic.c | 27 ++++++++++++++++++++++++---
10
1 file changed, 24 insertions(+), 3 deletions(-)
11
12
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/intc/armv7m_nvic.c
15
+++ b/hw/intc/armv7m_nvic.c
16
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
17
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
18
goto bad_offset;
19
}
20
+ if (!attrs.secure &&
21
+ !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
22
+ return 0;
23
+ }
24
return cpu->env.v7m.bfar;
25
case 0xd3c: /* Aux Fault Status. */
26
/* TODO: Implement fault status registers. */
27
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
28
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
29
goto bad_offset;
30
}
31
+ if (!attrs.secure &&
32
+ !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
33
+ return;
34
+ }
35
cpu->env.v7m.bfar = value;
36
return;
37
case 0xd3c: /* Aux Fault Status. */
38
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_read(void *opaque, hwaddr addr,
39
val = 0;
40
break;
41
};
42
- /* The BFSR bits [15:8] are shared between security states
43
- * and we store them in the NS copy
44
+ /*
45
+ * The BFSR bits [15:8] are shared between security states
46
+ * and we store them in the NS copy. They are RAZ/WI for
47
+ * NS code if AIRCR.BFHFNMINS is 0.
48
*/
49
val = s->cpu->env.v7m.cfsr[attrs.secure];
50
- val |= s->cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK;
51
+ if (!attrs.secure &&
52
+ !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
53
+ val &= ~R_V7M_CFSR_BFSR_MASK;
54
+ } else {
55
+ val |= s->cpu->env.v7m.cfsr[M_REG_NS] & R_V7M_CFSR_BFSR_MASK;
56
+ }
57
val = extract32(val, (offset - 0xd28) * 8, size * 8);
58
break;
59
case 0xfe0 ... 0xfff: /* ID. */
60
@@ -XXX,XX +XXX,XX @@ static MemTxResult nvic_sysreg_write(void *opaque, hwaddr addr,
61
*/
62
value <<= ((offset - 0xd28) * 8);
63
64
+ if (!attrs.secure &&
65
+ !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
66
+ /* BFSR bits are RAZ/WI for NS if BFHFNMINS is set */
67
+ value &= ~R_V7M_CFSR_BFSR_MASK;
68
+ }
69
+
70
s->cpu->env.v7m.cfsr[attrs.secure] &= ~value;
71
if (attrs.secure) {
72
/* The BFSR bits [15:8] are shared between security states
73
--
74
2.20.1
75
76
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/15] hw/intc/armv7m_nvic: Don't enable ARMV7M_EXCP_DEBUG from reset
Deleted patch
1
The M-profile architecture specifies that the DebugMonitor exception
2
should be initially disabled, not enabled. It should be controlled
3
by the DEMCR register's MON_EN bit, but we don't implement that
4
register yet (like most of the debug architecture for M-profile).
5
1
6
Note that BKPT instructions will still work, because they
7
will be escalated to HardFault.
8
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20190430131439.25251-4-peter.maydell@linaro.org
12
---
13
hw/intc/armv7m_nvic.c | 4 +++-
14
1 file changed, 3 insertions(+), 1 deletion(-)
15
16
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/intc/armv7m_nvic.c
19
+++ b/hw/intc/armv7m_nvic.c
20
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_reset(DeviceState *dev)
21
* the System Handler Control register
22
*/
23
s->vectors[ARMV7M_EXCP_SVC].enabled = 1;
24
- s->vectors[ARMV7M_EXCP_DEBUG].enabled = 1;
25
s->vectors[ARMV7M_EXCP_PENDSV].enabled = 1;
26
s->vectors[ARMV7M_EXCP_SYSTICK].enabled = 1;
27
28
+ /* DebugMonitor is enabled via DEMCR.MON_EN */
29
+ s->vectors[ARMV7M_EXCP_DEBUG].enabled = 0;
30
+
31
resetprio = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? -4 : -3;
32
s->vectors[ARMV7M_EXCP_RESET].prio = resetprio;
33
s->vectors[ARMV7M_EXCP_NMI].prio = -2;
34
--
35
2.20.1
36
37
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/15] target/arm: Implement XPSR GE bits
Deleted patch
1
In the M-profile architecture, if the CPU implements the DSP extension
2
then the XPSR has GE bits, in the same way as the A-profile CPSR. When
3
we added DSP extension support we forgot to add support for reading
4
and writing the GE bits, which are stored in env->GE. We did put in
5
the code to add XPSR_GE to the mask of bits to update in the v7m_msr
6
helper, but forgot it in v7m_mrs. We also must not allow the XPSR we
7
pull off the stack on exception return to set the nonexistent GE bits.
8
Correct these errors:
9
* read and write env->GE in xpsr_read() and xpsr_write()
10
* only set GE bits on exception return if DSP present
11
* read GE bits for MRS if DSP present
12
1
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20190430131439.25251-5-peter.maydell@linaro.org
16
---
17
target/arm/cpu.h | 4 ++++
18
target/arm/helper.c | 12 ++++++++++--
19
2 files changed, 14 insertions(+), 2 deletions(-)
20
21
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
22
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/cpu.h
24
+++ b/target/arm/cpu.h
25
@@ -XXX,XX +XXX,XX @@ static inline uint32_t xpsr_read(CPUARMState *env)
26
| (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
27
| (env->thumb << 24) | ((env->condexec_bits & 3) << 25)
28
| ((env->condexec_bits & 0xfc) << 8)
29
+ | (env->GE << 16)
30
| env->v7m.exception;
31
}
32
33
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
34
if (mask & XPSR_Q) {
35
env->QF = ((val & XPSR_Q) != 0);
36
}
37
+ if (mask & XPSR_GE) {
38
+ env->GE = (val & XPSR_GE) >> 16;
39
+ }
40
if (mask & XPSR_T) {
41
env->thumb = ((val & XPSR_T) != 0);
42
}
43
diff --git a/target/arm/helper.c b/target/arm/helper.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/target/arm/helper.c
46
+++ b/target/arm/helper.c
47
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
48
{
49
CPUARMState *env = &cpu->env;
50
uint32_t excret;
51
- uint32_t xpsr;
52
+ uint32_t xpsr, xpsr_mask;
53
bool ufault = false;
54
bool sfault = false;
55
bool return_to_sp_process;
56
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
57
}
58
*frame_sp_p = frameptr;
59
}
60
+
61
+ xpsr_mask = ~(XPSR_SPREALIGN | XPSR_SFPA);
62
+ if (!arm_feature(env, ARM_FEATURE_THUMB_DSP)) {
63
+ xpsr_mask &= ~XPSR_GE;
64
+ }
65
/* This xpsr_write() will invalidate frame_sp_p as it may switch stack */
66
- xpsr_write(env, xpsr, ~(XPSR_SPREALIGN | XPSR_SFPA));
67
+ xpsr_write(env, xpsr, xpsr_mask);
68
69
if (env->v7m.secure) {
70
bool sfpa = xpsr & XPSR_SFPA;
71
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
72
}
73
if (!(reg & 4)) {
74
mask |= XPSR_NZCV | XPSR_Q; /* APSR */
75
+ if (arm_feature(env, ARM_FEATURE_THUMB_DSP)) {
76
+ mask |= XPSR_GE;
77
+ }
78
}
79
/* EPSR reads as zero */
80
return xpsr_read(env) & mask;
81
--
82
2.20.1
83
84
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/15] target/arm: Stop using variable length array in dc_zva
Deleted patch
1
Currently the dc_zva helper function uses a variable length
2
array. In fact we know (as the comment above remarks) that
3
the length of this array is bounded because the architecture
4
limits the block size and QEMU limits the target page size.
5
Use a fixed array size and assert that we don't run off it.
6
1
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Message-id: 20190503120448.13385-1-peter.maydell@linaro.org
12
---
13
target/arm/helper.c | 8 ++++++--
14
1 file changed, 6 insertions(+), 2 deletions(-)
15
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper.c
19
+++ b/target/arm/helper.c
20
@@ -XXX,XX +XXX,XX @@
21
#include "qemu/osdep.h"
22
+#include "qemu/units.h"
23
#include "target/arm/idau.h"
24
#include "trace.h"
25
#include "cpu.h"
26
@@ -XXX,XX +XXX,XX @@ void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
27
* We know that in fact for any v8 CPU the page size is at least 4K
28
* and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
29
* 1K as an artefact of legacy v5 subpage support being present in the
30
- * same QEMU executable.
31
+ * same QEMU executable. So in practice the hostaddr[] array has
32
+ * two entries, given the current setting of TARGET_PAGE_BITS_MIN.
33
*/
34
int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
35
- void *hostaddr[maxidx];
36
+ void *hostaddr[DIV_ROUND_UP(2 * KiB, 1 << TARGET_PAGE_BITS_MIN)];
37
int try, i;
38
unsigned mmu_idx = cpu_mmu_index(env, false);
39
TCGMemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
40
41
+ assert(maxidx <= ARRAY_SIZE(hostaddr));
42
+
43
for (try = 0; try < 2; try++) {
44
45
for (i = 0; i < maxidx; i++) {
46
--
47
2.20.1
48
49
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.