1 | First pullreq for arm of the 4.1 series, since I'm back from | 1 | The following changes since commit 53f306f316549d20c76886903181413d20842423: |
---|---|---|---|
2 | holiday now. This is mostly my M-profile FPU series and Philippe's | ||
3 | devices.h cleanup. I have a pile of other patchsets to work through | ||
4 | in my to-review folder, but 42 patches is definitely quite | ||
5 | big enough to send now... | ||
6 | 2 | ||
7 | thanks | 3 | Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-06-21 11:26:04 +0100) |
8 | -- PMM | ||
9 | |||
10 | The following changes since commit 413a99a92c13ec408dcf2adaa87918dc81e890c8: | ||
11 | |||
12 | Add Nios II semihosting support. (2019-04-29 16:09:51 +0100) | ||
13 | 4 | ||
14 | are available in the Git repository at: | 5 | are available in the Git repository at: |
15 | 6 | ||
16 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190429 | 7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210621 |
17 | 8 | ||
18 | for you to fetch changes up to 437cc27ddfded3bbab6afd5ac1761e0e195edba7: | 9 | for you to fetch changes up to a83f1d9263d281f938a3984cda7104d55affd43a: |
19 | 10 | ||
20 | hw/devices: Move SMSC 91C111 declaration into a new header (2019-04-29 17:57:21 +0100) | 11 | docs/system: arm: Add nRF boards description (2021-06-21 17:24:33 +0100) |
21 | 12 | ||
22 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
23 | target-arm queue: | 14 | target-arm queue: |
24 | * remove "bag of random stuff" hw/devices.h header | 15 | * Don't require 'virt' board to be compiled in for ACPI GHES code |
25 | * implement FPU for Cortex-M and enable it for Cortex-M4 and -M33 | 16 | * docs: Document which architecture extensions we emulate |
26 | * hw/dma: Compile the bcm2835_dma device as common object | 17 | * Fix bugs in M-profile FPCXT_NS accesses |
27 | * configure: Remove --source-path option | 18 | * First slice of MVE patches |
28 | * hw/ssi/xilinx_spips: Avoid variable length array | 19 | * Implement MTE3 |
29 | * hw/arm/smmuv3: Remove SMMUNotifierNode | 20 | * docs/system: arm: Add nRF boards description |
30 | 21 | ||
31 | ---------------------------------------------------------------- | 22 | ---------------------------------------------------------------- |
32 | Eric Auger (1): | 23 | Alexandre Iooss (1): |
33 | hw/arm/smmuv3: Remove SMMUNotifierNode | 24 | docs/system: arm: Add nRF boards description |
34 | 25 | ||
35 | Peter Maydell (28): | 26 | Peter Collingbourne (1): |
36 | hw/ssi/xilinx_spips: Avoid variable length array | 27 | target/arm: Implement MTE3 |
37 | configure: Remove --source-path option | ||
38 | target/arm: Make sure M-profile FPSCR RES0 bits are not settable | ||
39 | hw/intc/armv7m_nvic: Allow reading of M-profile MVFR* registers | ||
40 | target/arm: Implement dummy versions of M-profile FP-related registers | ||
41 | target/arm: Disable most VFP sysregs for M-profile | ||
42 | target/arm: Honour M-profile FP enable bits | ||
43 | target/arm: Decode FP instructions for M profile | ||
44 | target/arm: Clear CONTROL_S.SFPA in SG insn if FPU present | ||
45 | target/arm: Handle SFPA and FPCA bits in reads and writes of CONTROL | ||
46 | target/arm/helper: don't return early for STKOF faults during stacking | ||
47 | target/arm: Handle floating point registers in exception entry | ||
48 | target/arm: Implement v7m_update_fpccr() | ||
49 | target/arm: Clear CONTROL.SFPA in BXNS and BLXNS | ||
50 | target/arm: Clean excReturn bits when tail chaining | ||
51 | target/arm: Allow for floating point in callee stack integrity check | ||
52 | target/arm: Handle floating point registers in exception return | ||
53 | target/arm: Move NS TBFLAG from bit 19 to bit 6 | ||
54 | target/arm: Overlap VECSTRIDE and XSCALE_CPAR TB flags | ||
55 | target/arm: Set FPCCR.S when executing M-profile floating point insns | ||
56 | target/arm: Activate M-profile floating point context when FPCCR.ASPEN is set | ||
57 | target/arm: New helper function arm_v7m_mmu_idx_all() | ||
58 | target/arm: New function armv7m_nvic_set_pending_lazyfp() | ||
59 | target/arm: Add lazy-FP-stacking support to v7m_stack_write() | ||
60 | target/arm: Implement M-profile lazy FP state preservation | ||
61 | target/arm: Implement VLSTM for v7M CPUs with an FPU | ||
62 | target/arm: Implement VLLDM for v7M CPUs with an FPU | ||
63 | target/arm: Enable FPU for Cortex-M4 and Cortex-M33 | ||
64 | 28 | ||
65 | Philippe Mathieu-Daudé (13): | 29 | Peter Maydell (55): |
66 | hw/dma: Compile the bcm2835_dma device as common object | 30 | hw/acpi: Provide stub version of acpi_ghes_record_errors() |
67 | hw/arm/aspeed: Use TYPE_TMP105/TYPE_PCA9552 instead of hardcoded string | 31 | hw/acpi: Provide function acpi_ghes_present() |
68 | hw/arm/nseries: Use TYPE_TMP105 instead of hardcoded string | 32 | target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors |
69 | hw/display/tc6393xb: Remove unused functions | 33 | docs/system/arm: Document which architecture extensions we emulate |
70 | hw/devices: Move TC6393XB declarations into a new header | 34 | target/arm/translate-vfp.c: Whitespace fixes |
71 | hw/devices: Move Blizzard declarations into a new header | 35 | target/arm: Handle FPU being disabled in FPCXT_NS accesses |
72 | hw/devices: Move CBus declarations into a new header | 36 | target/arm: Don't NOCP fault for FPCXT_NS accesses |
73 | hw/devices: Move Gamepad declarations into a new header | 37 | target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access |
74 | hw/devices: Move TI touchscreen declarations into a new header | 38 | target/arm: Factor FP context update code out into helper function |
75 | hw/devices: Move LAN9118 declarations into a new header | 39 | target/arm: Split vfp_access_check() into A and M versions |
76 | hw/net/ne2000-isa: Add guards to the header | 40 | target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m() |
77 | hw/net/lan9118: Export TYPE_LAN9118 and use it instead of hardcoded string | 41 | target/arm: Implement MVE VLDR/VSTR (non-widening forms) |
78 | hw/devices: Move SMSC 91C111 declaration into a new header | 42 | target/arm: Implement widening/narrowing MVE VLDR/VSTR insns |
43 | target/arm: Implement MVE VCLZ | ||
44 | target/arm: Implement MVE VCLS | ||
45 | target/arm: Implement MVE VREV16, VREV32, VREV64 | ||
46 | target/arm: Implement MVE VMVN (register) | ||
47 | target/arm: Implement MVE VABS | ||
48 | target/arm: Implement MVE VNEG | ||
49 | tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64 | ||
50 | target/arm: Implement MVE VDUP | ||
51 | target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR | ||
52 | target/arm: Implement MVE VADD, VSUB, VMUL | ||
53 | target/arm: Implement MVE VMULH | ||
54 | target/arm: Implement MVE VRMULH | ||
55 | target/arm: Implement MVE VMAX, VMIN | ||
56 | target/arm: Implement MVE VABD | ||
57 | target/arm: Implement MVE VHADD, VHSUB | ||
58 | target/arm: Implement MVE VMULL | ||
59 | target/arm: Implement MVE VMLALDAV | ||
60 | target/arm: Implement MVE VMLSLDAV | ||
61 | target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH | ||
62 | target/arm: Implement MVE VADD (scalar) | ||
63 | target/arm: Implement MVE VSUB, VMUL (scalar) | ||
64 | target/arm: Implement MVE VHADD, VHSUB (scalar) | ||
65 | target/arm: Implement MVE VBRSR | ||
66 | target/arm: Implement MVE VPST | ||
67 | target/arm: Implement MVE VQADD and VQSUB | ||
68 | target/arm: Implement MVE VQDMULH and VQRDMULH (scalar) | ||
69 | target/arm: Implement MVE VQDMULL scalar | ||
70 | target/arm: Implement MVE VQDMULH, VQRDMULH (vector) | ||
71 | target/arm: Implement MVE VQADD, VQSUB (vector) | ||
72 | target/arm: Implement MVE VQSHL (vector) | ||
73 | target/arm: Implement MVE VQRSHL | ||
74 | target/arm: Implement MVE VSHL insn | ||
75 | target/arm: Implement MVE VRSHL | ||
76 | target/arm: Implement MVE VQDMLADH and VQRDMLADH | ||
77 | target/arm: Implement MVE VQDMLSDH and VQRDMLSDH | ||
78 | target/arm: Implement MVE VQDMULL (vector) | ||
79 | target/arm: Implement MVE VRHADD | ||
80 | target/arm: Implement MVE VADC, VSBC | ||
81 | target/arm: Implement MVE VCADD | ||
82 | target/arm: Implement MVE VHCADD | ||
83 | target/arm: Implement MVE VADDV | ||
84 | target/arm: Make VMOV scalar <-> gpreg beatwise for MVE | ||
79 | 85 | ||
80 | configure | 10 +- | 86 | docs/system/arm/emulation.rst | 103 ++++ |
81 | hw/dma/Makefile.objs | 2 +- | 87 | docs/system/arm/nrf.rst | 51 ++ |
82 | include/hw/arm/omap.h | 6 +- | 88 | docs/system/target-arm.rst | 7 + |
83 | include/hw/arm/smmu-common.h | 8 +- | 89 | include/hw/acpi/ghes.h | 9 + |
84 | include/hw/devices.h | 62 --- | 90 | include/tcg/tcg-op.h | 8 + |
85 | include/hw/display/blizzard.h | 22 ++ | 91 | include/tcg/tcg.h | 1 - |
86 | include/hw/display/tc6393xb.h | 24 ++ | 92 | target/arm/helper-mve.h | 357 +++++++++++++ |
87 | include/hw/input/gamepad.h | 19 + | 93 | target/arm/helper.h | 2 + |
88 | include/hw/input/tsc2xxx.h | 36 ++ | 94 | target/arm/internals.h | 11 + |
89 | include/hw/misc/cbus.h | 32 ++ | 95 | target/arm/translate-a32.h | 3 + |
90 | include/hw/net/lan9118.h | 21 + | 96 | target/arm/translate.h | 10 + |
91 | include/hw/net/ne2000-isa.h | 6 + | 97 | target/arm/m-nocp.decode | 24 + |
92 | include/hw/net/smc91c111.h | 19 + | 98 | target/arm/mve.decode | 240 +++++++++ |
93 | include/qemu/typedefs.h | 1 - | 99 | target/arm/vfp.decode | 14 - |
94 | target/arm/cpu.h | 95 ++++- | 100 | hw/acpi/ghes-stub.c | 22 + |
95 | target/arm/helper.h | 5 + | 101 | hw/acpi/ghes.c | 17 + |
96 | target/arm/translate.h | 3 + | 102 | target/arm/cpu64.c | 2 +- |
97 | hw/arm/aspeed.c | 13 +- | 103 | target/arm/kvm64.c | 6 +- |
98 | hw/arm/exynos4_boards.c | 3 +- | 104 | target/arm/mte_helper.c | 82 +-- |
99 | hw/arm/gumstix.c | 2 +- | 105 | target/arm/mve_helper.c | 1160 +++++++++++++++++++++++++++++++++++++++++ |
100 | hw/arm/integratorcp.c | 2 +- | 106 | target/arm/translate-m-nocp.c | 550 +++++++++++++++++++ |
101 | hw/arm/kzm.c | 2 +- | 107 | target/arm/translate-mve.c | 759 +++++++++++++++++++++++++++ |
102 | hw/arm/mainstone.c | 2 +- | 108 | target/arm/translate-vfp.c | 741 +++++++------------------- |
103 | hw/arm/mps2-tz.c | 3 +- | 109 | tcg/tcg-op-gvec.c | 20 +- |
104 | hw/arm/mps2.c | 2 +- | 110 | MAINTAINERS | 1 + |
105 | hw/arm/nseries.c | 7 +- | 111 | hw/acpi/meson.build | 6 +- |
106 | hw/arm/palm.c | 2 +- | 112 | target/arm/meson.build | 1 + |
107 | hw/arm/realview.c | 3 +- | 113 | 27 files changed, 3578 insertions(+), 629 deletions(-) |
108 | hw/arm/smmu-common.c | 6 +- | 114 | create mode 100644 docs/system/arm/emulation.rst |
109 | hw/arm/smmuv3.c | 28 +- | 115 | create mode 100644 docs/system/arm/nrf.rst |
110 | hw/arm/stellaris.c | 2 +- | 116 | create mode 100644 target/arm/helper-mve.h |
111 | hw/arm/tosa.c | 2 +- | 117 | create mode 100644 hw/acpi/ghes-stub.c |
112 | hw/arm/versatilepb.c | 2 +- | 118 | create mode 100644 target/arm/mve_helper.c |
113 | hw/arm/vexpress.c | 2 +- | ||
114 | hw/display/blizzard.c | 2 +- | ||
115 | hw/display/tc6393xb.c | 18 +- | ||
116 | hw/input/stellaris_input.c | 2 +- | ||
117 | hw/input/tsc2005.c | 2 +- | ||
118 | hw/input/tsc210x.c | 4 +- | ||
119 | hw/intc/armv7m_nvic.c | 261 +++++++++++++ | ||
120 | hw/misc/cbus.c | 2 +- | ||
121 | hw/net/lan9118.c | 3 +- | ||
122 | hw/net/smc91c111.c | 2 +- | ||
123 | hw/ssi/xilinx_spips.c | 6 +- | ||
124 | target/arm/cpu.c | 20 + | ||
125 | target/arm/helper.c | 873 +++++++++++++++++++++++++++++++++++++++--- | ||
126 | target/arm/machine.c | 16 + | ||
127 | target/arm/translate.c | 150 +++++++- | ||
128 | target/arm/vfp_helper.c | 8 + | ||
129 | MAINTAINERS | 7 + | ||
130 | 50 files changed, 1595 insertions(+), 235 deletions(-) | ||
131 | delete mode 100644 include/hw/devices.h | ||
132 | create mode 100644 include/hw/display/blizzard.h | ||
133 | create mode 100644 include/hw/display/tc6393xb.h | ||
134 | create mode 100644 include/hw/input/gamepad.h | ||
135 | create mode 100644 include/hw/input/tsc2xxx.h | ||
136 | create mode 100644 include/hw/misc/cbus.h | ||
137 | create mode 100644 include/hw/net/lan9118.h | ||
138 | create mode 100644 include/hw/net/smc91c111.h | ||
139 | 119 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | 1 | Generic code in target/arm wants to call acpi_ghes_record_errors(); |
---|---|---|---|
2 | provide a stub version so that we don't fail to link when | ||
3 | CONFIG_ACPI_APEI is not set. This requires us to add a new | ||
4 | ghes-stub.c file to contain it and the meson.build mechanics | ||
5 | to use it when appropriate. | ||
2 | 6 | ||
3 | This commit finally deletes "hw/devices.h". | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Reviewed-by: Dongjiu Geng <gengdongjiu1@gmail.com> | ||
10 | Message-id: 20210603171259.27962-2-peter.maydell@linaro.org | ||
11 | --- | ||
12 | hw/acpi/ghes-stub.c | 17 +++++++++++++++++ | ||
13 | hw/acpi/meson.build | 6 +++--- | ||
14 | 2 files changed, 20 insertions(+), 3 deletions(-) | ||
15 | create mode 100644 hw/acpi/ghes-stub.c | ||
4 | 16 | ||
5 | Reviewed-by: Markus Armbruster <armbru@redhat.com> | 17 | diff --git a/hw/acpi/ghes-stub.c b/hw/acpi/ghes-stub.c |
6 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
7 | Message-id: 20190412165416.7977-13-philmd@redhat.com | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | --- | ||
10 | include/hw/devices.h | 11 ----------- | ||
11 | include/hw/net/smc91c111.h | 19 +++++++++++++++++++ | ||
12 | hw/arm/gumstix.c | 2 +- | ||
13 | hw/arm/integratorcp.c | 2 +- | ||
14 | hw/arm/mainstone.c | 2 +- | ||
15 | hw/arm/realview.c | 2 +- | ||
16 | hw/arm/versatilepb.c | 2 +- | ||
17 | hw/net/smc91c111.c | 2 +- | ||
18 | 8 files changed, 25 insertions(+), 17 deletions(-) | ||
19 | delete mode 100644 include/hw/devices.h | ||
20 | create mode 100644 include/hw/net/smc91c111.h | ||
21 | |||
22 | diff --git a/include/hw/devices.h b/include/hw/devices.h | ||
23 | deleted file mode 100644 | ||
24 | index XXXXXXX..XXXXXXX | ||
25 | --- a/include/hw/devices.h | ||
26 | +++ /dev/null | ||
27 | @@ -XXX,XX +XXX,XX @@ | ||
28 | -#ifndef QEMU_DEVICES_H | ||
29 | -#define QEMU_DEVICES_H | ||
30 | - | ||
31 | -/* Devices that have nowhere better to go. */ | ||
32 | - | ||
33 | -#include "hw/hw.h" | ||
34 | - | ||
35 | -/* smc91c111.c */ | ||
36 | -void smc91c111_init(NICInfo *, uint32_t, qemu_irq); | ||
37 | - | ||
38 | -#endif | ||
39 | diff --git a/include/hw/net/smc91c111.h b/include/hw/net/smc91c111.h | ||
40 | new file mode 100644 | 18 | new file mode 100644 |
41 | index XXXXXXX..XXXXXXX | 19 | index XXXXXXX..XXXXXXX |
42 | --- /dev/null | 20 | --- /dev/null |
43 | +++ b/include/hw/net/smc91c111.h | 21 | +++ b/hw/acpi/ghes-stub.c |
44 | @@ -XXX,XX +XXX,XX @@ | 22 | @@ -XXX,XX +XXX,XX @@ |
45 | +/* | 23 | +/* |
46 | + * SMSC 91C111 Ethernet interface emulation | 24 | + * Support for generating APEI tables and recording CPER for Guests: |
25 | + * stub functions. | ||
47 | + * | 26 | + * |
48 | + * Copyright (c) 2005 CodeSourcery, LLC. | 27 | + * Copyright (c) 2021 Linaro, Ltd |
49 | + * Written by Paul Brook | ||
50 | + * | 28 | + * |
51 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | 29 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. |
52 | + * See the COPYING file in the top-level directory. | 30 | + * See the COPYING file in the top-level directory. |
53 | + */ | 31 | + */ |
54 | + | 32 | + |
55 | +#ifndef HW_NET_SMC91C111_H | 33 | +#include "qemu/osdep.h" |
56 | +#define HW_NET_SMC91C111_H | 34 | +#include "hw/acpi/ghes.h" |
57 | + | 35 | + |
58 | +#include "hw/irq.h" | 36 | +int acpi_ghes_record_errors(uint8_t source_id, uint64_t physical_address) |
59 | +#include "net/net.h" | 37 | +{ |
60 | + | 38 | + return -1; |
61 | +void smc91c111_init(NICInfo *, uint32_t, qemu_irq); | 39 | +} |
62 | + | 40 | diff --git a/hw/acpi/meson.build b/hw/acpi/meson.build |
63 | +#endif | ||
64 | diff --git a/hw/arm/gumstix.c b/hw/arm/gumstix.c | ||
65 | index XXXXXXX..XXXXXXX 100644 | 41 | index XXXXXXX..XXXXXXX 100644 |
66 | --- a/hw/arm/gumstix.c | 42 | --- a/hw/acpi/meson.build |
67 | +++ b/hw/arm/gumstix.c | 43 | +++ b/hw/acpi/meson.build |
68 | @@ -XXX,XX +XXX,XX @@ | 44 | @@ -XXX,XX +XXX,XX @@ acpi_ss.add(when: 'CONFIG_ACPI_PCI', if_true: files('pci.c')) |
69 | #include "hw/arm/pxa.h" | 45 | acpi_ss.add(when: 'CONFIG_ACPI_VMGENID', if_true: files('vmgenid.c')) |
70 | #include "net/net.h" | 46 | acpi_ss.add(when: 'CONFIG_ACPI_HW_REDUCED', if_true: files('generic_event_device.c')) |
71 | #include "hw/block/flash.h" | 47 | acpi_ss.add(when: 'CONFIG_ACPI_HMAT', if_true: files('hmat.c')) |
72 | -#include "hw/devices.h" | 48 | -acpi_ss.add(when: 'CONFIG_ACPI_APEI', if_true: files('ghes.c')) |
73 | +#include "hw/net/smc91c111.h" | 49 | +acpi_ss.add(when: 'CONFIG_ACPI_APEI', if_true: files('ghes.c'), if_false: files('ghes-stub.c')) |
74 | #include "hw/boards.h" | 50 | acpi_ss.add(when: 'CONFIG_ACPI_X86', if_true: files('core.c', 'piix4.c', 'pcihp.c'), if_false: files('acpi-stub.c')) |
75 | #include "exec/address-spaces.h" | 51 | acpi_ss.add(when: 'CONFIG_ACPI_X86_ICH', if_true: files('ich9.c', 'tco.c')) |
76 | #include "sysemu/qtest.h" | 52 | acpi_ss.add(when: 'CONFIG_IPMI', if_true: files('ipmi.c'), if_false: files('ipmi-stub.c')) |
77 | diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c | 53 | acpi_ss.add(when: 'CONFIG_PC', if_false: files('acpi-x86-stub.c')) |
78 | index XXXXXXX..XXXXXXX 100644 | 54 | acpi_ss.add(when: 'CONFIG_TPM', if_true: files('tpm.c')) |
79 | --- a/hw/arm/integratorcp.c | 55 | -softmmu_ss.add(when: 'CONFIG_ACPI', if_false: files('acpi-stub.c', 'aml-build-stub.c')) |
80 | +++ b/hw/arm/integratorcp.c | 56 | +softmmu_ss.add(when: 'CONFIG_ACPI', if_false: files('acpi-stub.c', 'aml-build-stub.c', 'ghes-stub.c')) |
81 | @@ -XXX,XX +XXX,XX @@ | 57 | softmmu_ss.add_all(when: 'CONFIG_ACPI', if_true: acpi_ss) |
82 | #include "qemu-common.h" | 58 | softmmu_ss.add(when: 'CONFIG_ALL', if_true: files('acpi-stub.c', 'aml-build-stub.c', |
83 | #include "cpu.h" | 59 | - 'acpi-x86-stub.c', 'ipmi-stub.c')) |
84 | #include "hw/sysbus.h" | 60 | + 'acpi-x86-stub.c', 'ipmi-stub.c', 'ghes-stub.c')) |
85 | -#include "hw/devices.h" | ||
86 | #include "hw/boards.h" | ||
87 | #include "hw/arm/arm.h" | ||
88 | #include "hw/misc/arm_integrator_debug.h" | ||
89 | +#include "hw/net/smc91c111.h" | ||
90 | #include "net/net.h" | ||
91 | #include "exec/address-spaces.h" | ||
92 | #include "sysemu/sysemu.h" | ||
93 | diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c | ||
94 | index XXXXXXX..XXXXXXX 100644 | ||
95 | --- a/hw/arm/mainstone.c | ||
96 | +++ b/hw/arm/mainstone.c | ||
97 | @@ -XXX,XX +XXX,XX @@ | ||
98 | #include "hw/arm/pxa.h" | ||
99 | #include "hw/arm/arm.h" | ||
100 | #include "net/net.h" | ||
101 | -#include "hw/devices.h" | ||
102 | +#include "hw/net/smc91c111.h" | ||
103 | #include "hw/boards.h" | ||
104 | #include "hw/block/flash.h" | ||
105 | #include "hw/sysbus.h" | ||
106 | diff --git a/hw/arm/realview.c b/hw/arm/realview.c | ||
107 | index XXXXXXX..XXXXXXX 100644 | ||
108 | --- a/hw/arm/realview.c | ||
109 | +++ b/hw/arm/realview.c | ||
110 | @@ -XXX,XX +XXX,XX @@ | ||
111 | #include "hw/sysbus.h" | ||
112 | #include "hw/arm/arm.h" | ||
113 | #include "hw/arm/primecell.h" | ||
114 | -#include "hw/devices.h" | ||
115 | #include "hw/net/lan9118.h" | ||
116 | +#include "hw/net/smc91c111.h" | ||
117 | #include "hw/pci/pci.h" | ||
118 | #include "net/net.h" | ||
119 | #include "sysemu/sysemu.h" | ||
120 | diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c | ||
121 | index XXXXXXX..XXXXXXX 100644 | ||
122 | --- a/hw/arm/versatilepb.c | ||
123 | +++ b/hw/arm/versatilepb.c | ||
124 | @@ -XXX,XX +XXX,XX @@ | ||
125 | #include "cpu.h" | ||
126 | #include "hw/sysbus.h" | ||
127 | #include "hw/arm/arm.h" | ||
128 | -#include "hw/devices.h" | ||
129 | +#include "hw/net/smc91c111.h" | ||
130 | #include "net/net.h" | ||
131 | #include "sysemu/sysemu.h" | ||
132 | #include "hw/pci/pci.h" | ||
133 | diff --git a/hw/net/smc91c111.c b/hw/net/smc91c111.c | ||
134 | index XXXXXXX..XXXXXXX 100644 | ||
135 | --- a/hw/net/smc91c111.c | ||
136 | +++ b/hw/net/smc91c111.c | ||
137 | @@ -XXX,XX +XXX,XX @@ | ||
138 | #include "qemu/osdep.h" | ||
139 | #include "hw/sysbus.h" | ||
140 | #include "net/net.h" | ||
141 | -#include "hw/devices.h" | ||
142 | +#include "hw/net/smc91c111.h" | ||
143 | #include "qemu/log.h" | ||
144 | /* For crc32 */ | ||
145 | #include <zlib.h> | ||
146 | -- | 61 | -- |
147 | 2.20.1 | 62 | 2.20.1 |
148 | 63 | ||
149 | 64 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Allow code elsewhere in the system to check whether the ACPI GHES | ||
2 | table is present, so it can determine whether it is OK to try to | ||
3 | record an error by calling acpi_ghes_record_errors(). | ||
1 | 4 | ||
5 | (We don't need to migrate the new 'present' field in AcpiGhesState, | ||
6 | because it is set once at system initialization and doesn't change.) | ||
7 | |||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Reviewed-by: Dongjiu Geng <gengdongjiu1@gmail.com> | ||
11 | Message-id: 20210603171259.27962-3-peter.maydell@linaro.org | ||
12 | --- | ||
13 | include/hw/acpi/ghes.h | 9 +++++++++ | ||
14 | hw/acpi/ghes-stub.c | 5 +++++ | ||
15 | hw/acpi/ghes.c | 17 +++++++++++++++++ | ||
16 | 3 files changed, 31 insertions(+) | ||
17 | |||
18 | diff --git a/include/hw/acpi/ghes.h b/include/hw/acpi/ghes.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/include/hw/acpi/ghes.h | ||
21 | +++ b/include/hw/acpi/ghes.h | ||
22 | @@ -XXX,XX +XXX,XX @@ enum { | ||
23 | |||
24 | typedef struct AcpiGhesState { | ||
25 | uint64_t ghes_addr_le; | ||
26 | + bool present; /* True if GHES is present at all on this board */ | ||
27 | } AcpiGhesState; | ||
28 | |||
29 | void build_ghes_error_table(GArray *hardware_errors, BIOSLinker *linker); | ||
30 | @@ -XXX,XX +XXX,XX @@ void acpi_build_hest(GArray *table_data, BIOSLinker *linker, | ||
31 | void acpi_ghes_add_fw_cfg(AcpiGhesState *vms, FWCfgState *s, | ||
32 | GArray *hardware_errors); | ||
33 | int acpi_ghes_record_errors(uint8_t notify, uint64_t error_physical_addr); | ||
34 | + | ||
35 | +/** | ||
36 | + * acpi_ghes_present: Report whether ACPI GHES table is present | ||
37 | + * | ||
38 | + * Returns: true if the system has an ACPI GHES table and it is | ||
39 | + * safe to call acpi_ghes_record_errors() to record a memory error. | ||
40 | + */ | ||
41 | +bool acpi_ghes_present(void); | ||
42 | #endif | ||
43 | diff --git a/hw/acpi/ghes-stub.c b/hw/acpi/ghes-stub.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/hw/acpi/ghes-stub.c | ||
46 | +++ b/hw/acpi/ghes-stub.c | ||
47 | @@ -XXX,XX +XXX,XX @@ int acpi_ghes_record_errors(uint8_t source_id, uint64_t physical_address) | ||
48 | { | ||
49 | return -1; | ||
50 | } | ||
51 | + | ||
52 | +bool acpi_ghes_present(void) | ||
53 | +{ | ||
54 | + return false; | ||
55 | +} | ||
56 | diff --git a/hw/acpi/ghes.c b/hw/acpi/ghes.c | ||
57 | index XXXXXXX..XXXXXXX 100644 | ||
58 | --- a/hw/acpi/ghes.c | ||
59 | +++ b/hw/acpi/ghes.c | ||
60 | @@ -XXX,XX +XXX,XX @@ void acpi_ghes_add_fw_cfg(AcpiGhesState *ags, FWCfgState *s, | ||
61 | /* Create a read-write fw_cfg file for Address */ | ||
62 | fw_cfg_add_file_callback(s, ACPI_GHES_DATA_ADDR_FW_CFG_FILE, NULL, NULL, | ||
63 | NULL, &(ags->ghes_addr_le), sizeof(ags->ghes_addr_le), false); | ||
64 | + | ||
65 | + ags->present = true; | ||
66 | } | ||
67 | |||
68 | int acpi_ghes_record_errors(uint8_t source_id, uint64_t physical_address) | ||
69 | @@ -XXX,XX +XXX,XX @@ int acpi_ghes_record_errors(uint8_t source_id, uint64_t physical_address) | ||
70 | |||
71 | return ret; | ||
72 | } | ||
73 | + | ||
74 | +bool acpi_ghes_present(void) | ||
75 | +{ | ||
76 | + AcpiGedState *acpi_ged_state; | ||
77 | + AcpiGhesState *ags; | ||
78 | + | ||
79 | + acpi_ged_state = ACPI_GED(object_resolve_path_type("", TYPE_ACPI_GED, | ||
80 | + NULL)); | ||
81 | + | ||
82 | + if (!acpi_ged_state) { | ||
83 | + return false; | ||
84 | + } | ||
85 | + ags = &acpi_ged_state->ghes_state; | ||
86 | + return ags->present; | ||
87 | +} | ||
88 | -- | ||
89 | 2.20.1 | ||
90 | |||
91 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The virt_is_acpi_enabled() function is specific to the virt board, as | ||
2 | is the check for its 'ras' property. Use the new acpi_ghes_present() | ||
3 | function to check whether we should report memory errors via | ||
4 | acpi_ghes_record_errors(). | ||
1 | 5 | ||
6 | This avoids a link error if QEMU was built without support for the | ||
7 | virt board, and provides a mechanism that can be used by any future | ||
8 | board models that want to add ACPI memory error reporting support | ||
9 | (they only need to call acpi_ghes_add_fw_cfg()). | ||
10 | |||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
13 | Reviewed-by: Dongjiu Geng <gengdongjiu1@gmail.com> | ||
14 | Message-id: 20210603171259.27962-4-peter.maydell@linaro.org | ||
15 | --- | ||
16 | target/arm/kvm64.c | 6 +----- | ||
17 | 1 file changed, 1 insertion(+), 5 deletions(-) | ||
18 | |||
19 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
20 | index XXXXXXX..XXXXXXX 100644 | ||
21 | --- a/target/arm/kvm64.c | ||
22 | +++ b/target/arm/kvm64.c | ||
23 | @@ -XXX,XX +XXX,XX @@ void kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr) | ||
24 | { | ||
25 | ram_addr_t ram_addr; | ||
26 | hwaddr paddr; | ||
27 | - Object *obj = qdev_get_machine(); | ||
28 | - VirtMachineState *vms = VIRT_MACHINE(obj); | ||
29 | - bool acpi_enabled = virt_is_acpi_enabled(vms); | ||
30 | |||
31 | assert(code == BUS_MCEERR_AR || code == BUS_MCEERR_AO); | ||
32 | |||
33 | - if (acpi_enabled && addr && | ||
34 | - object_property_get_bool(obj, "ras", NULL)) { | ||
35 | + if (acpi_ghes_present() && addr) { | ||
36 | ram_addr = qemu_ram_addr_from_host(addr); | ||
37 | if (ram_addr != RAM_ADDR_INVALID && | ||
38 | kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) { | ||
39 | -- | ||
40 | 2.20.1 | ||
41 | |||
42 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | 1 | These days the Arm architecture has a wide range of fine-grained |
---|---|---|---|
2 | optional extra architectural features. We implement quite a lot | ||
3 | of these but by no means all of them. Document what we do implement, | ||
4 | so that users can find out without having to dig through back-issues | ||
5 | of our Changelog on the wiki. | ||
2 | 6 | ||
3 | Reviewed-by: Markus Armbruster <armbru@redhat.com> | ||
4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
5 | Message-id: 20190412165416.7977-10-philmd@redhat.com | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | ||
9 | Message-id: 20210617140328.28622-1-peter.maydell@linaro.org | ||
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | --- | 11 | --- |
8 | include/hw/devices.h | 3 --- | 12 | docs/system/arm/emulation.rst | 102 ++++++++++++++++++++++++++++++++++ |
9 | include/hw/net/lan9118.h | 19 +++++++++++++++++++ | 13 | docs/system/target-arm.rst | 6 ++ |
10 | hw/arm/kzm.c | 2 +- | 14 | 2 files changed, 108 insertions(+) |
11 | hw/arm/mps2.c | 2 +- | 15 | create mode 100644 docs/system/arm/emulation.rst |
12 | hw/arm/realview.c | 1 + | ||
13 | hw/arm/vexpress.c | 2 +- | ||
14 | hw/net/lan9118.c | 2 +- | ||
15 | 7 files changed, 24 insertions(+), 7 deletions(-) | ||
16 | create mode 100644 include/hw/net/lan9118.h | ||
17 | 16 | ||
18 | diff --git a/include/hw/devices.h b/include/hw/devices.h | 17 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
19 | index XXXXXXX..XXXXXXX 100644 | ||
20 | --- a/include/hw/devices.h | ||
21 | +++ b/include/hw/devices.h | ||
22 | @@ -XXX,XX +XXX,XX @@ | ||
23 | /* smc91c111.c */ | ||
24 | void smc91c111_init(NICInfo *, uint32_t, qemu_irq); | ||
25 | |||
26 | -/* lan9118.c */ | ||
27 | -void lan9118_init(NICInfo *, uint32_t, qemu_irq); | ||
28 | - | ||
29 | #endif | ||
30 | diff --git a/include/hw/net/lan9118.h b/include/hw/net/lan9118.h | ||
31 | new file mode 100644 | 18 | new file mode 100644 |
32 | index XXXXXXX..XXXXXXX | 19 | index XXXXXXX..XXXXXXX |
33 | --- /dev/null | 20 | --- /dev/null |
34 | +++ b/include/hw/net/lan9118.h | 21 | +++ b/docs/system/arm/emulation.rst |
35 | @@ -XXX,XX +XXX,XX @@ | 22 | @@ -XXX,XX +XXX,XX @@ |
36 | +/* | 23 | +A-profile CPU architecture support |
37 | + * SMSC LAN9118 Ethernet interface emulation | 24 | +================================== |
38 | + * | ||
39 | + * Copyright (c) 2009 CodeSourcery, LLC. | ||
40 | + * Written by Paul Brook | ||
41 | + * | ||
42 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
43 | + * See the COPYING file in the top-level directory. | ||
44 | + */ | ||
45 | + | 25 | + |
46 | +#ifndef HW_NET_LAN9118_H | 26 | +QEMU's TCG emulation includes support for the Armv5, Armv6, Armv7 and |
47 | +#define HW_NET_LAN9118_H | 27 | +Armv8 versions of the A-profile architecture. It also has support for |
28 | +the following architecture extensions: | ||
48 | + | 29 | + |
49 | +#include "hw/irq.h" | 30 | +- FEAT_AA32BF16 (AArch32 BFloat16 instructions) |
50 | +#include "net/net.h" | 31 | +- FEAT_AA32HPD (AArch32 hierarchical permission disables) |
32 | +- FEAT_AA32I8MM (AArch32 Int8 matrix multiplication instructions) | ||
33 | +- FEAT_AES (AESD and AESE instructions) | ||
34 | +- FEAT_BF16 (AArch64 BFloat16 instructions) | ||
35 | +- FEAT_BTI (Branch Target Identification) | ||
36 | +- FEAT_DIT (Data Independent Timing instructions) | ||
37 | +- FEAT_DPB (DC CVAP instruction) | ||
38 | +- FEAT_DotProd (Advanced SIMD dot product instructions) | ||
39 | +- FEAT_FCMA (Floating-point complex number instructions) | ||
40 | +- FEAT_FHM (Floating-point half-precision multiplication instructions) | ||
41 | +- FEAT_FP16 (Half-precision floating-point data processing) | ||
42 | +- FEAT_FRINTTS (Floating-point to integer instructions) | ||
43 | +- FEAT_FlagM (Flag manipulation instructions v2) | ||
44 | +- FEAT_FlagM2 (Enhancements to flag manipulation instructions) | ||
45 | +- FEAT_HPDS (Hierarchical permission disables) | ||
46 | +- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) | ||
47 | +- FEAT_JSCVT (JavaScript conversion instructions) | ||
48 | +- FEAT_LOR (Limited ordering regions) | ||
49 | +- FEAT_LRCPC (Load-acquire RCpc instructions) | ||
50 | +- FEAT_LRCPC2 (Load-acquire RCpc instructions v2) | ||
51 | +- FEAT_LSE (Large System Extensions) | ||
52 | +- FEAT_MTE (Memory Tagging Extension) | ||
53 | +- FEAT_MTE2 (Memory Tagging Extension) | ||
54 | +- FEAT_PAN (Privileged access never) | ||
55 | +- FEAT_PAN2 (AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN) | ||
56 | +- FEAT_PAuth (Pointer authentication) | ||
57 | +- FEAT_PMULL (PMULL, PMULL2 instructions) | ||
58 | +- FEAT_PMUv3p1 (PMU Extensions v3.1) | ||
59 | +- FEAT_PMUv3p4 (PMU Extensions v3.4) | ||
60 | +- FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions) | ||
61 | +- FEAT_RNG (Random number generator) | ||
62 | +- FEAT_SB (Speculation Barrier) | ||
63 | +- FEAT_SEL2 (Secure EL2) | ||
64 | +- FEAT_SHA1 (SHA1 instructions) | ||
65 | +- FEAT_SHA256 (SHA256 instructions) | ||
66 | +- FEAT_SHA3 (Advanced SIMD SHA3 instructions) | ||
67 | +- FEAT_SHA512 (Advanced SIMD SHA512 instructions) | ||
68 | +- FEAT_SM3 (Advanced SIMD SM3 instructions) | ||
69 | +- FEAT_SM4 (Advanced SIMD SM4 instructions) | ||
70 | +- FEAT_SPECRES (Speculation restriction instructions) | ||
71 | +- FEAT_SSBS (Speculative Store Bypass Safe) | ||
72 | +- FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain) | ||
73 | +- FEAT_TLBIRANGE (TLB invalidate range instructions) | ||
74 | +- FEAT_TTCNP (Translation table Common not private translations) | ||
75 | +- FEAT_TTST (Small translation tables) | ||
76 | +- FEAT_UAO (Unprivileged Access Override control) | ||
77 | +- FEAT_VHE (Virtualization Host Extensions) | ||
78 | +- FEAT_VMID16 (16-bit VMID) | ||
79 | +- FEAT_XNX (Translation table stage 2 Unprivileged Execute-never) | ||
80 | +- SVE (The Scalable Vector Extension) | ||
81 | +- SVE2 (The Scalable Vector Extension v2) | ||
51 | + | 82 | + |
52 | +void lan9118_init(NICInfo *, uint32_t, qemu_irq); | 83 | +For information on the specifics of these extensions, please refer |
84 | +to the `Armv8-A Arm Architecture Reference Manual | ||
85 | +<https://developer.arm.com/documentation/ddi0487/latest>`_. | ||
53 | + | 86 | + |
54 | +#endif | 87 | +When a specific named CPU is being emulated, only those features which |
55 | diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c | 88 | +are present in hardware for that CPU are emulated. (If a feature is |
89 | +not in the list above then it is not supported, even if the real | ||
90 | +hardware should have it.) The ``max`` CPU enables all features. | ||
91 | + | ||
92 | +R-profile CPU architecture support | ||
93 | +================================== | ||
94 | + | ||
95 | +QEMU's TCG emulation support for R-profile CPUs is currently limited. | ||
96 | +We emulate only the Cortex-R5 and Cortex-R5F CPUs. | ||
97 | + | ||
98 | +M-profile CPU architecture support | ||
99 | +================================== | ||
100 | + | ||
101 | +QEMU's TCG emulation includes support for Armv6-M, Armv7-M, Armv8-M, and | ||
102 | +Armv8.1-M versions of the M-profile architucture. It also has support | ||
103 | +for the following architecture extensions: | ||
104 | + | ||
105 | +- FP (Floating-point Extension) | ||
106 | +- FPCXT (FPCXT access instructions) | ||
107 | +- HP (Half-precision floating-point instructions) | ||
108 | +- LOB (Low Overhead loops and Branch future) | ||
109 | +- M (Main Extension) | ||
110 | +- MPU (Memory Protection Unit Extension) | ||
111 | +- PXN (Privileged Execute Never) | ||
112 | +- RAS (Reliability, Serviceability and Availability): "minimum RAS Extension" only | ||
113 | +- S (Security Extension) | ||
114 | +- ST (System Timer Extension) | ||
115 | + | ||
116 | +For information on the specifics of these extensions, please refer | ||
117 | +to the `Armv8-M Arm Architecture Reference Manual | ||
118 | +<https://developer.arm.com/documentation/ddi0553/latest>`_. | ||
119 | + | ||
120 | +When a specific named CPU is being emulated, only those features which | ||
121 | +are present in hardware for that CPU are emulated. (If a feature is | ||
122 | +not in the list above then it is not supported, even if the real | ||
123 | +hardware should have it.) There is no equivalent of the ``max`` CPU for | ||
124 | +M-profile. | ||
125 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst | ||
56 | index XXXXXXX..XXXXXXX 100644 | 126 | index XXXXXXX..XXXXXXX 100644 |
57 | --- a/hw/arm/kzm.c | 127 | --- a/docs/system/target-arm.rst |
58 | +++ b/hw/arm/kzm.c | 128 | +++ b/docs/system/target-arm.rst |
59 | @@ -XXX,XX +XXX,XX @@ | 129 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running |
60 | #include "qemu/error-report.h" | 130 | arm/virt |
61 | #include "exec/address-spaces.h" | 131 | arm/xlnx-versal-virt |
62 | #include "net/net.h" | 132 | |
63 | -#include "hw/devices.h" | 133 | +Emulated CPU architecture support |
64 | +#include "hw/net/lan9118.h" | 134 | +================================= |
65 | #include "hw/char/serial.h" | 135 | + |
66 | #include "sysemu/qtest.h" | 136 | +.. toctree:: |
67 | 137 | + arm/emulation | |
68 | diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c | 138 | + |
69 | index XXXXXXX..XXXXXXX 100644 | 139 | Arm CPU features |
70 | --- a/hw/arm/mps2.c | 140 | ================ |
71 | +++ b/hw/arm/mps2.c | 141 | |
72 | @@ -XXX,XX +XXX,XX @@ | ||
73 | #include "hw/timer/cmsdk-apb-timer.h" | ||
74 | #include "hw/timer/cmsdk-apb-dualtimer.h" | ||
75 | #include "hw/misc/mps2-scc.h" | ||
76 | -#include "hw/devices.h" | ||
77 | +#include "hw/net/lan9118.h" | ||
78 | #include "net/net.h" | ||
79 | |||
80 | typedef enum MPS2FPGAType { | ||
81 | diff --git a/hw/arm/realview.c b/hw/arm/realview.c | ||
82 | index XXXXXXX..XXXXXXX 100644 | ||
83 | --- a/hw/arm/realview.c | ||
84 | +++ b/hw/arm/realview.c | ||
85 | @@ -XXX,XX +XXX,XX @@ | ||
86 | #include "hw/arm/arm.h" | ||
87 | #include "hw/arm/primecell.h" | ||
88 | #include "hw/devices.h" | ||
89 | +#include "hw/net/lan9118.h" | ||
90 | #include "hw/pci/pci.h" | ||
91 | #include "net/net.h" | ||
92 | #include "sysemu/sysemu.h" | ||
93 | diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c | ||
94 | index XXXXXXX..XXXXXXX 100644 | ||
95 | --- a/hw/arm/vexpress.c | ||
96 | +++ b/hw/arm/vexpress.c | ||
97 | @@ -XXX,XX +XXX,XX @@ | ||
98 | #include "hw/sysbus.h" | ||
99 | #include "hw/arm/arm.h" | ||
100 | #include "hw/arm/primecell.h" | ||
101 | -#include "hw/devices.h" | ||
102 | +#include "hw/net/lan9118.h" | ||
103 | #include "hw/i2c/i2c.h" | ||
104 | #include "net/net.h" | ||
105 | #include "sysemu/sysemu.h" | ||
106 | diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c | ||
107 | index XXXXXXX..XXXXXXX 100644 | ||
108 | --- a/hw/net/lan9118.c | ||
109 | +++ b/hw/net/lan9118.c | ||
110 | @@ -XXX,XX +XXX,XX @@ | ||
111 | #include "hw/sysbus.h" | ||
112 | #include "net/net.h" | ||
113 | #include "net/eth.h" | ||
114 | -#include "hw/devices.h" | ||
115 | +#include "hw/net/lan9118.h" | ||
116 | #include "sysemu/sysemu.h" | ||
117 | #include "hw/ptimer.h" | ||
118 | #include "qemu/log.h" | ||
119 | -- | 142 | -- |
120 | 2.20.1 | 143 | 2.20.1 |
121 | 144 | ||
122 | 145 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | In the code for handling VFP system register accesses there is some | ||
2 | stray whitespace after a unary '-' operator, and also some incorrect | ||
3 | indent in a couple of function prototypes. We're about to move this | ||
4 | code to another file, so fix the code style issues first so | ||
5 | checkpatch doesn't complain about the code-movement patch. | ||
1 | 6 | ||
7 | Cc: qemu-stable@nongnu.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20210618141019.10671-2-peter.maydell@linaro.org | ||
11 | --- | ||
12 | target/arm/translate-vfp.c | 11 +++++------ | ||
13 | 1 file changed, 5 insertions(+), 6 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/translate-vfp.c | ||
18 | +++ b/target/arm/translate-vfp.c | ||
19 | @@ -XXX,XX +XXX,XX @@ static void gen_branch_fpInactive(DisasContext *s, TCGCond cond, | ||
20 | } | ||
21 | |||
22 | static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, | ||
23 | - | ||
24 | fp_sysreg_loadfn *loadfn, | ||
25 | - void *opaque) | ||
26 | + void *opaque) | ||
27 | { | ||
28 | /* Do a write to an M-profile floating point system register */ | ||
29 | TCGv_i32 tmp; | ||
30 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, | ||
31 | } | ||
32 | |||
33 | static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, | ||
34 | - fp_sysreg_storefn *storefn, | ||
35 | - void *opaque) | ||
36 | + fp_sysreg_storefn *storefn, | ||
37 | + void *opaque) | ||
38 | { | ||
39 | /* Do a read from an M-profile floating point system register */ | ||
40 | TCGv_i32 tmp; | ||
41 | @@ -XXX,XX +XXX,XX @@ static void fp_sysreg_to_memory(DisasContext *s, void *opaque, TCGv_i32 value) | ||
42 | TCGv_i32 addr; | ||
43 | |||
44 | if (!a->a) { | ||
45 | - offset = - offset; | ||
46 | + offset = -offset; | ||
47 | } | ||
48 | |||
49 | addr = load_reg(s, a->rn); | ||
50 | @@ -XXX,XX +XXX,XX @@ static TCGv_i32 memory_to_fp_sysreg(DisasContext *s, void *opaque) | ||
51 | TCGv_i32 value = tcg_temp_new_i32(); | ||
52 | |||
53 | if (!a->a) { | ||
54 | - offset = - offset; | ||
55 | + offset = -offset; | ||
56 | } | ||
57 | |||
58 | addr = load_reg(s, a->rn); | ||
59 | -- | ||
60 | 2.20.1 | ||
61 | |||
62 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | If the guest makes an FPCXT_NS access when the FPU is disabled, | ||
2 | one of two things happens: | ||
3 | * if there is no active FP context, then the insn behaves the | ||
4 | same way as if the FPU was enabled: writes ignored, reads | ||
5 | same value as FPDSCR_NS | ||
6 | * if there is an active FP context, then we take a NOCP | ||
7 | exception | ||
1 | 8 | ||
9 | Add code to the sysreg read/write functions which emits | ||
10 | code to take the NOCP exception in the latter case. | ||
11 | |||
12 | At the moment this will never be used, because the NOCP checks in | ||
13 | m-nocp.decode happen first, and so the trans functions are never | ||
14 | called when the FPU is disabled. The code will be needed when we | ||
15 | move the sysreg access insns to before the NOCP patterns in the | ||
16 | following commit. | ||
17 | |||
18 | Cc: qemu-stable@nongnu.org | ||
19 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
20 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
21 | Message-id: 20210618141019.10671-3-peter.maydell@linaro.org | ||
22 | --- | ||
23 | target/arm/translate-vfp.c | 32 ++++++++++++++++++++++++++++++-- | ||
24 | 1 file changed, 30 insertions(+), 2 deletions(-) | ||
25 | |||
26 | diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c | ||
27 | index XXXXXXX..XXXXXXX 100644 | ||
28 | --- a/target/arm/translate-vfp.c | ||
29 | +++ b/target/arm/translate-vfp.c | ||
30 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, | ||
31 | lab_end = gen_new_label(); | ||
32 | /* fpInactive case: write is a NOP, so branch to end */ | ||
33 | gen_branch_fpInactive(s, TCG_COND_NE, lab_end); | ||
34 | - /* !fpInactive: PreserveFPState(), and reads same as FPCXT_S */ | ||
35 | + /* | ||
36 | + * !fpInactive: if FPU disabled, take NOCP exception; | ||
37 | + * otherwise PreserveFPState(), and then FPCXT_NS writes | ||
38 | + * behave the same as FPCXT_S writes. | ||
39 | + */ | ||
40 | + if (s->fp_excp_el) { | ||
41 | + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
42 | + syn_uncategorized(), s->fp_excp_el); | ||
43 | + /* | ||
44 | + * This was only a conditional exception, so override | ||
45 | + * gen_exception_insn()'s default to DISAS_NORETURN | ||
46 | + */ | ||
47 | + s->base.is_jmp = DISAS_NEXT; | ||
48 | + break; | ||
49 | + } | ||
50 | gen_preserve_fp_state(s); | ||
51 | /* fall through */ | ||
52 | case ARM_VFP_FPCXT_S: | ||
53 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, | ||
54 | tcg_gen_br(lab_end); | ||
55 | |||
56 | gen_set_label(lab_active); | ||
57 | - /* !fpInactive: Reads the same as FPCXT_S, but side effects differ */ | ||
58 | + /* | ||
59 | + * !fpInactive: if FPU disabled, take NOCP exception; | ||
60 | + * otherwise PreserveFPState(), and then FPCXT_NS | ||
61 | + * reads the same as FPCXT_S. | ||
62 | + */ | ||
63 | + if (s->fp_excp_el) { | ||
64 | + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
65 | + syn_uncategorized(), s->fp_excp_el); | ||
66 | + /* | ||
67 | + * This was only a conditional exception, so override | ||
68 | + * gen_exception_insn()'s default to DISAS_NORETURN | ||
69 | + */ | ||
70 | + s->base.is_jmp = DISAS_NEXT; | ||
71 | + break; | ||
72 | + } | ||
73 | gen_preserve_fp_state(s); | ||
74 | tmp = tcg_temp_new_i32(); | ||
75 | sfpa = tcg_temp_new_i32(); | ||
76 | -- | ||
77 | 2.20.1 | ||
78 | |||
79 | diff view generated by jsdifflib |
1 | In the v7M architecture, if an exception is generated in the process | 1 | The M-profile architecture requires that accesses to FPCXT_NS when |
---|---|---|---|
2 | of doing the lazy stacking of FP registers, the handling of | 2 | there is no active FP state must not take a NOCP fault even if the |
3 | possible escalation to HardFault is treated differently to the normal | 3 | FPU is disabled. We were not implementing this correctly, because |
4 | approach: it works based on the saved information about exception | 4 | in our decode we catch the NOCP faults early in m-nocp.decode. |
5 | readiness that was stored in the FPCCR when the stack frame was | ||
6 | created. Provide a new function armv7m_nvic_set_pending_lazyfp() | ||
7 | which pends exceptions during lazy stacking, and implements | ||
8 | this logic. | ||
9 | 5 | ||
10 | This corresponds to the pseudocode TakePreserveFPException(). | 6 | Fix this bug by moving all the handling of M-profile FP system |
7 | register accesses from vfp.decode into m-nocp.decode and putting | ||
8 | it above the NOCP blocks. This provides the correct behaviour: | ||
9 | * for accesses other than FPCXT_NS the trans functions call | ||
10 | vfp_access_check(), which will check for FPU disabled and | ||
11 | raise a NOCP exception if necessary | ||
12 | * for FPCXT_NS we have the special case code that doesn't | ||
13 | call vfp_access_check() | ||
14 | * when these trans functions want to raise an UNDEF they return | ||
15 | false, so the decoder will fall through into the NOCP blocks. | ||
16 | This means that NOCP correctly takes precedence over UNDEF | ||
17 | for these insns. (This is a difference from the other insns | ||
18 | handled by m-nocp.decode, where UNDEF takes precedence and | ||
19 | which we implement by having those trans functions call | ||
20 | unallocated_encoding() in the appropriate places.) | ||
11 | 21 | ||
22 | [Note for backport to stable: this commit has a semantic dependency | ||
23 | on commit 9a486856e9173af, which was not marked as cc-stable because | ||
24 | we didn't know we'd need it for a for-stable bugfix.] | ||
25 | |||
26 | Cc: qemu-stable@nongnu.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 27 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 28 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
14 | Message-id: 20190416125744.27770-22-peter.maydell@linaro.org | 29 | Message-id: 20210618141019.10671-4-peter.maydell@linaro.org |
15 | --- | 30 | --- |
16 | target/arm/cpu.h | 12 ++++++ | 31 | target/arm/translate-a32.h | 1 + |
17 | hw/intc/armv7m_nvic.c | 96 +++++++++++++++++++++++++++++++++++++++++++ | 32 | target/arm/m-nocp.decode | 24 ++ |
18 | 2 files changed, 108 insertions(+) | 33 | target/arm/vfp.decode | 14 - |
34 | target/arm/translate-m-nocp.c | 514 +++++++++++++++++++++++++++++++++ | ||
35 | target/arm/translate-vfp.c | 517 +--------------------------------- | ||
36 | 5 files changed, 542 insertions(+), 528 deletions(-) | ||
19 | 37 | ||
20 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 38 | diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h |
21 | index XXXXXXX..XXXXXXX 100644 | 39 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/target/arm/cpu.h | 40 | --- a/target/arm/translate-a32.h |
23 | +++ b/target/arm/cpu.h | 41 | +++ b/target/arm/translate-a32.h |
24 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending(void *opaque, int irq, bool secure); | 42 | @@ -XXX,XX +XXX,XX @@ bool disas_neon_shared(DisasContext *s, uint32_t insn); |
25 | * a different exception). | 43 | void load_reg_var(DisasContext *s, TCGv_i32 var, int reg); |
26 | */ | 44 | void arm_gen_condlabel(DisasContext *s); |
27 | void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure); | 45 | bool vfp_access_check(DisasContext *s); |
28 | +/** | 46 | +void gen_preserve_fp_state(DisasContext *s); |
29 | + * armv7m_nvic_set_pending_lazyfp: mark this lazy FP exception as pending | 47 | void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop); |
30 | + * @opaque: the NVIC | 48 | void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop); |
31 | + * @irq: the exception number to mark pending | 49 | void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop); |
32 | + * @secure: false for non-banked exceptions or for the nonsecure | 50 | diff --git a/target/arm/m-nocp.decode b/target/arm/m-nocp.decode |
33 | + * version of a banked exception, true for the secure version of a banked | 51 | index XXXXXXX..XXXXXXX 100644 |
34 | + * exception. | 52 | --- a/target/arm/m-nocp.decode |
35 | + * | 53 | +++ b/target/arm/m-nocp.decode |
36 | + * Similar to armv7m_nvic_set_pending(), but specifically for exceptions | 54 | @@ -XXX,XX +XXX,XX @@ |
37 | + * generated in the course of lazy stacking of FP registers. | 55 | |
56 | &nocp cp | ||
57 | |||
58 | +# M-profile VLDR/VSTR to sysreg | ||
59 | +%vldr_sysreg 22:1 13:3 | ||
60 | +%imm7_0x4 0:7 !function=times_4 | ||
61 | + | ||
62 | +&vldr_sysreg rn reg imm a w p | ||
63 | +@vldr_sysreg .... ... . a:1 . . . rn:4 ... . ... .. ....... \ | ||
64 | + reg=%vldr_sysreg imm=%imm7_0x4 &vldr_sysreg | ||
65 | + | ||
66 | { | ||
67 | # Special cases which do not take an early NOCP: VLLDM and VLSTM | ||
68 | VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 op:1 000 0000 | ||
69 | @@ -XXX,XX +XXX,XX @@ | ||
70 | VSCCLRM 1110 1100 1.01 1111 .... 1011 imm:7 0 vd=%vd_dp size=3 | ||
71 | VSCCLRM 1110 1100 1.01 1111 .... 1010 imm:8 vd=%vd_sp size=2 | ||
72 | |||
73 | + # FP system register accesses: these are a special case because accesses | ||
74 | + # to FPCXT_NS succeed even if the FPU is disabled. We therefore need | ||
75 | + # to handle them before the big NOCP blocks. Note that within these | ||
76 | + # insns NOCP still has higher priority than UNDEFs; this is implemented | ||
77 | + # by their returning 'false' for UNDEF so as to fall through into the | ||
78 | + # NOCP check (in contrast to VLLDM etc, which call unallocated_encoding() | ||
79 | + # for the UNDEFs there that must take precedence over NOCP.) | ||
80 | + | ||
81 | + VMSR_VMRS ---- 1110 111 l:1 reg:4 rt:4 1010 0001 0000 | ||
82 | + | ||
83 | + # P=0 W=0 is SEE "Related encodings", so split into two patterns | ||
84 | + VLDR_sysreg ---- 110 1 . . w:1 1 .... ... 0 111 11 ....... @vldr_sysreg p=1 | ||
85 | + VLDR_sysreg ---- 110 0 . . 1 1 .... ... 0 111 11 ....... @vldr_sysreg p=0 w=1 | ||
86 | + VSTR_sysreg ---- 110 1 . . w:1 0 .... ... 0 111 11 ....... @vldr_sysreg p=1 | ||
87 | + VSTR_sysreg ---- 110 0 . . 1 0 .... ... 0 111 11 ....... @vldr_sysreg p=0 w=1 | ||
88 | + | ||
89 | NOCP 111- 1110 ---- ---- ---- cp:4 ---- ---- &nocp | ||
90 | NOCP 111- 110- ---- ---- ---- cp:4 ---- ---- &nocp | ||
91 | # From v8.1M onwards this range will also NOCP: | ||
92 | diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode | ||
93 | index XXXXXXX..XXXXXXX 100644 | ||
94 | --- a/target/arm/vfp.decode | ||
95 | +++ b/target/arm/vfp.decode | ||
96 | @@ -XXX,XX +XXX,XX @@ VLDR_VSTR_hp ---- 1101 u:1 .0 l:1 rn:4 .... 1001 imm:8 vd=%vd_sp | ||
97 | VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 vd=%vd_sp | ||
98 | VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 vd=%vd_dp | ||
99 | |||
100 | -# M-profile VLDR/VSTR to sysreg | ||
101 | -%vldr_sysreg 22:1 13:3 | ||
102 | -%imm7_0x4 0:7 !function=times_4 | ||
103 | - | ||
104 | -&vldr_sysreg rn reg imm a w p | ||
105 | -@vldr_sysreg .... ... . a:1 . . . rn:4 ... . ... .. ....... \ | ||
106 | - reg=%vldr_sysreg imm=%imm7_0x4 &vldr_sysreg | ||
107 | - | ||
108 | -# P=0 W=0 is SEE "Related encodings", so split into two patterns | ||
109 | -VLDR_sysreg ---- 110 1 . . w:1 1 .... ... 0 111 11 ....... @vldr_sysreg p=1 | ||
110 | -VLDR_sysreg ---- 110 0 . . 1 1 .... ... 0 111 11 ....... @vldr_sysreg p=0 w=1 | ||
111 | -VSTR_sysreg ---- 110 1 . . w:1 0 .... ... 0 111 11 ....... @vldr_sysreg p=1 | ||
112 | -VSTR_sysreg ---- 110 0 . . 1 0 .... ... 0 111 11 ....... @vldr_sysreg p=0 w=1 | ||
113 | - | ||
114 | # We split the load/store multiple up into two patterns to avoid | ||
115 | # overlap with other insns in the "Advanced SIMD load/store and 64-bit move" | ||
116 | # grouping: | ||
117 | diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c | ||
118 | index XXXXXXX..XXXXXXX 100644 | ||
119 | --- a/target/arm/translate-m-nocp.c | ||
120 | +++ b/target/arm/translate-m-nocp.c | ||
121 | @@ -XXX,XX +XXX,XX @@ | ||
122 | |||
123 | #include "qemu/osdep.h" | ||
124 | #include "tcg/tcg-op.h" | ||
125 | +#include "tcg/tcg-op-gvec.h" | ||
126 | #include "translate.h" | ||
127 | #include "translate-a32.h" | ||
128 | |||
129 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a) | ||
130 | return true; | ||
131 | } | ||
132 | |||
133 | +/* | ||
134 | + * M-profile provides two different sets of instructions that can | ||
135 | + * access floating point system registers: VMSR/VMRS (which move | ||
136 | + * to/from a general purpose register) and VLDR/VSTR sysreg (which | ||
137 | + * move directly to/from memory). In some cases there are also side | ||
138 | + * effects which must happen after any write to memory (which could | ||
139 | + * cause an exception). So we implement the common logic for the | ||
140 | + * sysreg access in gen_M_fp_sysreg_write() and gen_M_fp_sysreg_read(), | ||
141 | + * which take pointers to callback functions which will perform the | ||
142 | + * actual "read/write general purpose register" and "read/write | ||
143 | + * memory" operations. | ||
38 | + */ | 144 | + */ |
39 | +void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure); | 145 | + |
40 | /** | 146 | +/* |
41 | * armv7m_nvic_get_pending_irq_info: return highest priority pending | 147 | + * Emit code to store the sysreg to its final destination; frees the |
42 | * exception, and whether it targets Secure state | 148 | + * TCG temp 'value' it is passed. |
43 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 149 | + */ |
44 | index XXXXXXX..XXXXXXX 100644 | 150 | +typedef void fp_sysreg_storefn(DisasContext *s, void *opaque, TCGv_i32 value); |
45 | --- a/hw/intc/armv7m_nvic.c | 151 | +/* |
46 | +++ b/hw/intc/armv7m_nvic.c | 152 | + * Emit code to load the value to be copied to the sysreg; returns |
47 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_set_pending_derived(void *opaque, int irq, bool secure) | 153 | + * a new TCG temporary |
48 | do_armv7m_nvic_set_pending(opaque, irq, secure, true); | 154 | + */ |
49 | } | 155 | +typedef TCGv_i32 fp_sysreg_loadfn(DisasContext *s, void *opaque); |
50 | 156 | + | |
51 | +void armv7m_nvic_set_pending_lazyfp(void *opaque, int irq, bool secure) | 157 | +/* Common decode/access checks for fp sysreg read/write */ |
158 | +typedef enum FPSysRegCheckResult { | ||
159 | + FPSysRegCheckFailed, /* caller should return false */ | ||
160 | + FPSysRegCheckDone, /* caller should return true */ | ||
161 | + FPSysRegCheckContinue, /* caller should continue generating code */ | ||
162 | +} FPSysRegCheckResult; | ||
163 | + | ||
164 | +static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno) | ||
165 | +{ | ||
166 | + if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)) { | ||
167 | + return FPSysRegCheckFailed; | ||
168 | + } | ||
169 | + | ||
170 | + switch (regno) { | ||
171 | + case ARM_VFP_FPSCR: | ||
172 | + case QEMU_VFP_FPSCR_NZCV: | ||
173 | + break; | ||
174 | + case ARM_VFP_FPSCR_NZCVQC: | ||
175 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
176 | + return FPSysRegCheckFailed; | ||
177 | + } | ||
178 | + break; | ||
179 | + case ARM_VFP_FPCXT_S: | ||
180 | + case ARM_VFP_FPCXT_NS: | ||
181 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
182 | + return FPSysRegCheckFailed; | ||
183 | + } | ||
184 | + if (!s->v8m_secure) { | ||
185 | + return FPSysRegCheckFailed; | ||
186 | + } | ||
187 | + break; | ||
188 | + case ARM_VFP_VPR: | ||
189 | + case ARM_VFP_P0: | ||
190 | + if (!dc_isar_feature(aa32_mve, s)) { | ||
191 | + return FPSysRegCheckFailed; | ||
192 | + } | ||
193 | + break; | ||
194 | + default: | ||
195 | + return FPSysRegCheckFailed; | ||
196 | + } | ||
197 | + | ||
198 | + /* | ||
199 | + * FPCXT_NS is a special case: it has specific handling for | ||
200 | + * "current FP state is inactive", and must do the PreserveFPState() | ||
201 | + * but not the usual full set of actions done by ExecuteFPCheck(). | ||
202 | + * So we don't call vfp_access_check() and the callers must handle this. | ||
203 | + */ | ||
204 | + if (regno != ARM_VFP_FPCXT_NS && !vfp_access_check(s)) { | ||
205 | + return FPSysRegCheckDone; | ||
206 | + } | ||
207 | + return FPSysRegCheckContinue; | ||
208 | +} | ||
209 | + | ||
210 | +static void gen_branch_fpInactive(DisasContext *s, TCGCond cond, | ||
211 | + TCGLabel *label) | ||
52 | +{ | 212 | +{ |
53 | + /* | 213 | + /* |
54 | + * Pend an exception during lazy FP stacking. This differs | 214 | + * FPCXT_NS is a special case: it has specific handling for |
55 | + * from the usual exception pending because the logic for | 215 | + * "current FP state is inactive", and must do the PreserveFPState() |
56 | + * whether we should escalate depends on the saved context | 216 | + * but not the usual full set of actions done by ExecuteFPCheck(). |
57 | + * in the FPCCR register, not on the current state of the CPU/NVIC. | 217 | + * We don't have a TB flag that matches the fpInactive check, so we |
218 | + * do it at runtime as we don't expect FPCXT_NS accesses to be frequent. | ||
219 | + * | ||
220 | + * Emit code that checks fpInactive and does a conditional | ||
221 | + * branch to label based on it: | ||
222 | + * if cond is TCG_COND_NE then branch if fpInactive != 0 (ie if inactive) | ||
223 | + * if cond is TCG_COND_EQ then branch if fpInactive == 0 (ie if active) | ||
58 | + */ | 224 | + */ |
59 | + NVICState *s = (NVICState *)opaque; | 225 | + assert(cond == TCG_COND_EQ || cond == TCG_COND_NE); |
60 | + bool banked = exc_is_banked(irq); | 226 | + |
61 | + VecInfo *vec; | 227 | + /* fpInactive = FPCCR_NS.ASPEN == 1 && CONTROL.FPCA == 0 */ |
62 | + bool targets_secure; | 228 | + TCGv_i32 aspen, fpca; |
63 | + bool escalate = false; | 229 | + aspen = load_cpu_field(v7m.fpccr[M_REG_NS]); |
64 | + /* | 230 | + fpca = load_cpu_field(v7m.control[M_REG_S]); |
65 | + * We will only look at bits in fpccr if this is a banked exception | 231 | + tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); |
66 | + * (in which case 'secure' tells us whether it is the S or NS version). | 232 | + tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); |
67 | + * All the bits for the non-banked exceptions are in fpccr_s. | 233 | + tcg_gen_andi_i32(fpca, fpca, R_V7M_CONTROL_FPCA_MASK); |
68 | + */ | 234 | + tcg_gen_or_i32(fpca, fpca, aspen); |
69 | + uint32_t fpccr_s = s->cpu->env.v7m.fpccr[M_REG_S]; | 235 | + tcg_gen_brcondi_i32(tcg_invert_cond(cond), fpca, 0, label); |
70 | + uint32_t fpccr = s->cpu->env.v7m.fpccr[secure]; | 236 | + tcg_temp_free_i32(aspen); |
71 | + | 237 | + tcg_temp_free_i32(fpca); |
72 | + assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); | 238 | +} |
73 | + assert(!secure || banked); | 239 | + |
74 | + | 240 | +static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, |
75 | + vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq]; | 241 | + fp_sysreg_loadfn *loadfn, |
76 | + | 242 | + void *opaque) |
77 | + targets_secure = banked ? secure : exc_targets_secure(s, irq); | 243 | +{ |
78 | + | 244 | + /* Do a write to an M-profile floating point system register */ |
79 | + switch (irq) { | 245 | + TCGv_i32 tmp; |
80 | + case ARMV7M_EXCP_DEBUG: | 246 | + TCGLabel *lab_end = NULL; |
81 | + if (!(fpccr_s & R_V7M_FPCCR_MONRDY_MASK)) { | 247 | + |
82 | + /* Ignore DebugMonitor exception */ | 248 | + switch (fp_sysreg_checks(s, regno)) { |
83 | + return; | 249 | + case FPSysRegCheckFailed: |
250 | + return false; | ||
251 | + case FPSysRegCheckDone: | ||
252 | + return true; | ||
253 | + case FPSysRegCheckContinue: | ||
254 | + break; | ||
255 | + } | ||
256 | + | ||
257 | + switch (regno) { | ||
258 | + case ARM_VFP_FPSCR: | ||
259 | + tmp = loadfn(s, opaque); | ||
260 | + gen_helper_vfp_set_fpscr(cpu_env, tmp); | ||
261 | + tcg_temp_free_i32(tmp); | ||
262 | + gen_lookup_tb(s); | ||
263 | + break; | ||
264 | + case ARM_VFP_FPSCR_NZCVQC: | ||
265 | + { | ||
266 | + TCGv_i32 fpscr; | ||
267 | + tmp = loadfn(s, opaque); | ||
268 | + if (dc_isar_feature(aa32_mve, s)) { | ||
269 | + /* QC is only present for MVE; otherwise RES0 */ | ||
270 | + TCGv_i32 qc = tcg_temp_new_i32(); | ||
271 | + tcg_gen_andi_i32(qc, tmp, FPCR_QC); | ||
272 | + /* | ||
273 | + * The 4 vfp.qc[] fields need only be "zero" vs "non-zero"; | ||
274 | + * here writing the same value into all elements is simplest. | ||
275 | + */ | ||
276 | + tcg_gen_gvec_dup_i32(MO_32, offsetof(CPUARMState, vfp.qc), | ||
277 | + 16, 16, qc); | ||
84 | + } | 278 | + } |
85 | + break; | 279 | + tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); |
86 | + case ARMV7M_EXCP_MEM: | 280 | + fpscr = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); |
87 | + escalate = !(fpccr & R_V7M_FPCCR_MMRDY_MASK); | 281 | + tcg_gen_andi_i32(fpscr, fpscr, ~FPCR_NZCV_MASK); |
88 | + break; | 282 | + tcg_gen_or_i32(fpscr, fpscr, tmp); |
89 | + case ARMV7M_EXCP_USAGE: | 283 | + store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]); |
90 | + escalate = !(fpccr & R_V7M_FPCCR_UFRDY_MASK); | 284 | + tcg_temp_free_i32(tmp); |
91 | + break; | 285 | + break; |
92 | + case ARMV7M_EXCP_BUS: | 286 | + } |
93 | + escalate = !(fpccr_s & R_V7M_FPCCR_BFRDY_MASK); | 287 | + case ARM_VFP_FPCXT_NS: |
94 | + break; | 288 | + lab_end = gen_new_label(); |
95 | + case ARMV7M_EXCP_SECURE: | 289 | + /* fpInactive case: write is a NOP, so branch to end */ |
96 | + escalate = !(fpccr_s & R_V7M_FPCCR_SFRDY_MASK); | 290 | + gen_branch_fpInactive(s, TCG_COND_NE, lab_end); |
97 | + break; | 291 | + /* |
292 | + * !fpInactive: if FPU disabled, take NOCP exception; | ||
293 | + * otherwise PreserveFPState(), and then FPCXT_NS writes | ||
294 | + * behave the same as FPCXT_S writes. | ||
295 | + */ | ||
296 | + if (s->fp_excp_el) { | ||
297 | + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
298 | + syn_uncategorized(), s->fp_excp_el); | ||
299 | + /* | ||
300 | + * This was only a conditional exception, so override | ||
301 | + * gen_exception_insn()'s default to DISAS_NORETURN | ||
302 | + */ | ||
303 | + s->base.is_jmp = DISAS_NEXT; | ||
304 | + break; | ||
305 | + } | ||
306 | + gen_preserve_fp_state(s); | ||
307 | + /* fall through */ | ||
308 | + case ARM_VFP_FPCXT_S: | ||
309 | + { | ||
310 | + TCGv_i32 sfpa, control; | ||
311 | + /* | ||
312 | + * Set FPSCR and CONTROL.SFPA from value; the new FPSCR takes | ||
313 | + * bits [27:0] from value and zeroes bits [31:28]. | ||
314 | + */ | ||
315 | + tmp = loadfn(s, opaque); | ||
316 | + sfpa = tcg_temp_new_i32(); | ||
317 | + tcg_gen_shri_i32(sfpa, tmp, 31); | ||
318 | + control = load_cpu_field(v7m.control[M_REG_S]); | ||
319 | + tcg_gen_deposit_i32(control, control, sfpa, | ||
320 | + R_V7M_CONTROL_SFPA_SHIFT, 1); | ||
321 | + store_cpu_field(control, v7m.control[M_REG_S]); | ||
322 | + tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK); | ||
323 | + gen_helper_vfp_set_fpscr(cpu_env, tmp); | ||
324 | + tcg_temp_free_i32(tmp); | ||
325 | + tcg_temp_free_i32(sfpa); | ||
326 | + break; | ||
327 | + } | ||
328 | + case ARM_VFP_VPR: | ||
329 | + /* Behaves as NOP if not privileged */ | ||
330 | + if (IS_USER(s)) { | ||
331 | + break; | ||
332 | + } | ||
333 | + tmp = loadfn(s, opaque); | ||
334 | + store_cpu_field(tmp, v7m.vpr); | ||
335 | + break; | ||
336 | + case ARM_VFP_P0: | ||
337 | + { | ||
338 | + TCGv_i32 vpr; | ||
339 | + tmp = loadfn(s, opaque); | ||
340 | + vpr = load_cpu_field(v7m.vpr); | ||
341 | + tcg_gen_deposit_i32(vpr, vpr, tmp, | ||
342 | + R_V7M_VPR_P0_SHIFT, R_V7M_VPR_P0_LENGTH); | ||
343 | + store_cpu_field(vpr, v7m.vpr); | ||
344 | + tcg_temp_free_i32(tmp); | ||
345 | + break; | ||
346 | + } | ||
98 | + default: | 347 | + default: |
99 | + g_assert_not_reached(); | 348 | + g_assert_not_reached(); |
100 | + } | 349 | + } |
101 | + | 350 | + if (lab_end) { |
102 | + if (escalate) { | 351 | + gen_set_label(lab_end); |
352 | + } | ||
353 | + return true; | ||
354 | +} | ||
355 | + | ||
356 | +static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, | ||
357 | + fp_sysreg_storefn *storefn, | ||
358 | + void *opaque) | ||
359 | +{ | ||
360 | + /* Do a read from an M-profile floating point system register */ | ||
361 | + TCGv_i32 tmp; | ||
362 | + TCGLabel *lab_end = NULL; | ||
363 | + bool lookup_tb = false; | ||
364 | + | ||
365 | + switch (fp_sysreg_checks(s, regno)) { | ||
366 | + case FPSysRegCheckFailed: | ||
367 | + return false; | ||
368 | + case FPSysRegCheckDone: | ||
369 | + return true; | ||
370 | + case FPSysRegCheckContinue: | ||
371 | + break; | ||
372 | + } | ||
373 | + | ||
374 | + if (regno == ARM_VFP_FPSCR_NZCVQC && !dc_isar_feature(aa32_mve, s)) { | ||
375 | + /* QC is RES0 without MVE, so NZCVQC simplifies to NZCV */ | ||
376 | + regno = QEMU_VFP_FPSCR_NZCV; | ||
377 | + } | ||
378 | + | ||
379 | + switch (regno) { | ||
380 | + case ARM_VFP_FPSCR: | ||
381 | + tmp = tcg_temp_new_i32(); | ||
382 | + gen_helper_vfp_get_fpscr(tmp, cpu_env); | ||
383 | + storefn(s, opaque, tmp); | ||
384 | + break; | ||
385 | + case ARM_VFP_FPSCR_NZCVQC: | ||
386 | + tmp = tcg_temp_new_i32(); | ||
387 | + gen_helper_vfp_get_fpscr(tmp, cpu_env); | ||
388 | + tcg_gen_andi_i32(tmp, tmp, FPCR_NZCVQC_MASK); | ||
389 | + storefn(s, opaque, tmp); | ||
390 | + break; | ||
391 | + case QEMU_VFP_FPSCR_NZCV: | ||
103 | + /* | 392 | + /* |
104 | + * Escalate to HardFault: faults that initially targeted Secure | 393 | + * Read just NZCV; this is a special case to avoid the |
105 | + * continue to do so, even if HF normally targets NonSecure. | 394 | + * helper call for the "VMRS to CPSR.NZCV" insn. |
106 | + */ | 395 | + */ |
107 | + irq = ARMV7M_EXCP_HARD; | 396 | + tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); |
108 | + if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) && | 397 | + tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); |
109 | + (targets_secure || | 398 | + storefn(s, opaque, tmp); |
110 | + !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK))) { | 399 | + break; |
111 | + vec = &s->sec_vectors[irq]; | 400 | + case ARM_VFP_FPCXT_S: |
401 | + { | ||
402 | + TCGv_i32 control, sfpa, fpscr; | ||
403 | + /* Bits [27:0] from FPSCR, bit [31] from CONTROL.SFPA */ | ||
404 | + tmp = tcg_temp_new_i32(); | ||
405 | + sfpa = tcg_temp_new_i32(); | ||
406 | + gen_helper_vfp_get_fpscr(tmp, cpu_env); | ||
407 | + tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK); | ||
408 | + control = load_cpu_field(v7m.control[M_REG_S]); | ||
409 | + tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK); | ||
410 | + tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT); | ||
411 | + tcg_gen_or_i32(tmp, tmp, sfpa); | ||
412 | + tcg_temp_free_i32(sfpa); | ||
413 | + /* | ||
414 | + * Store result before updating FPSCR etc, in case | ||
415 | + * it is a memory write which causes an exception. | ||
416 | + */ | ||
417 | + storefn(s, opaque, tmp); | ||
418 | + /* | ||
419 | + * Now we must reset FPSCR from FPDSCR_NS, and clear | ||
420 | + * CONTROL.SFPA; so we'll end the TB here. | ||
421 | + */ | ||
422 | + tcg_gen_andi_i32(control, control, ~R_V7M_CONTROL_SFPA_MASK); | ||
423 | + store_cpu_field(control, v7m.control[M_REG_S]); | ||
424 | + fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]); | ||
425 | + gen_helper_vfp_set_fpscr(cpu_env, fpscr); | ||
426 | + tcg_temp_free_i32(fpscr); | ||
427 | + lookup_tb = true; | ||
428 | + break; | ||
429 | + } | ||
430 | + case ARM_VFP_FPCXT_NS: | ||
431 | + { | ||
432 | + TCGv_i32 control, sfpa, fpscr, fpdscr, zero; | ||
433 | + TCGLabel *lab_active = gen_new_label(); | ||
434 | + | ||
435 | + lookup_tb = true; | ||
436 | + | ||
437 | + gen_branch_fpInactive(s, TCG_COND_EQ, lab_active); | ||
438 | + /* fpInactive case: reads as FPDSCR_NS */ | ||
439 | + TCGv_i32 tmp = load_cpu_field(v7m.fpdscr[M_REG_NS]); | ||
440 | + storefn(s, opaque, tmp); | ||
441 | + lab_end = gen_new_label(); | ||
442 | + tcg_gen_br(lab_end); | ||
443 | + | ||
444 | + gen_set_label(lab_active); | ||
445 | + /* | ||
446 | + * !fpInactive: if FPU disabled, take NOCP exception; | ||
447 | + * otherwise PreserveFPState(), and then FPCXT_NS | ||
448 | + * reads the same as FPCXT_S. | ||
449 | + */ | ||
450 | + if (s->fp_excp_el) { | ||
451 | + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
452 | + syn_uncategorized(), s->fp_excp_el); | ||
453 | + /* | ||
454 | + * This was only a conditional exception, so override | ||
455 | + * gen_exception_insn()'s default to DISAS_NORETURN | ||
456 | + */ | ||
457 | + s->base.is_jmp = DISAS_NEXT; | ||
458 | + break; | ||
459 | + } | ||
460 | + gen_preserve_fp_state(s); | ||
461 | + tmp = tcg_temp_new_i32(); | ||
462 | + sfpa = tcg_temp_new_i32(); | ||
463 | + fpscr = tcg_temp_new_i32(); | ||
464 | + gen_helper_vfp_get_fpscr(fpscr, cpu_env); | ||
465 | + tcg_gen_andi_i32(tmp, fpscr, ~FPCR_NZCV_MASK); | ||
466 | + control = load_cpu_field(v7m.control[M_REG_S]); | ||
467 | + tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK); | ||
468 | + tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT); | ||
469 | + tcg_gen_or_i32(tmp, tmp, sfpa); | ||
470 | + tcg_temp_free_i32(control); | ||
471 | + /* Store result before updating FPSCR, in case it faults */ | ||
472 | + storefn(s, opaque, tmp); | ||
473 | + /* If SFPA is zero then set FPSCR from FPDSCR_NS */ | ||
474 | + fpdscr = load_cpu_field(v7m.fpdscr[M_REG_NS]); | ||
475 | + zero = tcg_const_i32(0); | ||
476 | + tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, zero, fpdscr, fpscr); | ||
477 | + gen_helper_vfp_set_fpscr(cpu_env, fpscr); | ||
478 | + tcg_temp_free_i32(zero); | ||
479 | + tcg_temp_free_i32(sfpa); | ||
480 | + tcg_temp_free_i32(fpdscr); | ||
481 | + tcg_temp_free_i32(fpscr); | ||
482 | + break; | ||
483 | + } | ||
484 | + case ARM_VFP_VPR: | ||
485 | + /* Behaves as NOP if not privileged */ | ||
486 | + if (IS_USER(s)) { | ||
487 | + break; | ||
488 | + } | ||
489 | + tmp = load_cpu_field(v7m.vpr); | ||
490 | + storefn(s, opaque, tmp); | ||
491 | + break; | ||
492 | + case ARM_VFP_P0: | ||
493 | + tmp = load_cpu_field(v7m.vpr); | ||
494 | + tcg_gen_extract_i32(tmp, tmp, R_V7M_VPR_P0_SHIFT, R_V7M_VPR_P0_LENGTH); | ||
495 | + storefn(s, opaque, tmp); | ||
496 | + break; | ||
497 | + default: | ||
498 | + g_assert_not_reached(); | ||
499 | + } | ||
500 | + | ||
501 | + if (lab_end) { | ||
502 | + gen_set_label(lab_end); | ||
503 | + } | ||
504 | + if (lookup_tb) { | ||
505 | + gen_lookup_tb(s); | ||
506 | + } | ||
507 | + return true; | ||
508 | +} | ||
509 | + | ||
510 | +static void fp_sysreg_to_gpr(DisasContext *s, void *opaque, TCGv_i32 value) | ||
511 | +{ | ||
512 | + arg_VMSR_VMRS *a = opaque; | ||
513 | + | ||
514 | + if (a->rt == 15) { | ||
515 | + /* Set the 4 flag bits in the CPSR */ | ||
516 | + gen_set_nzcv(value); | ||
517 | + tcg_temp_free_i32(value); | ||
518 | + } else { | ||
519 | + store_reg(s, a->rt, value); | ||
520 | + } | ||
521 | +} | ||
522 | + | ||
523 | +static TCGv_i32 gpr_to_fp_sysreg(DisasContext *s, void *opaque) | ||
524 | +{ | ||
525 | + arg_VMSR_VMRS *a = opaque; | ||
526 | + | ||
527 | + return load_reg(s, a->rt); | ||
528 | +} | ||
529 | + | ||
530 | +static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) | ||
531 | +{ | ||
532 | + /* | ||
533 | + * Accesses to R15 are UNPREDICTABLE; we choose to undef. | ||
534 | + * FPSCR -> r15 is a special case which writes to the PSR flags; | ||
535 | + * set a->reg to a special value to tell gen_M_fp_sysreg_read() | ||
536 | + * we only care about the top 4 bits of FPSCR there. | ||
537 | + */ | ||
538 | + if (a->rt == 15) { | ||
539 | + if (a->l && a->reg == ARM_VFP_FPSCR) { | ||
540 | + a->reg = QEMU_VFP_FPSCR_NZCV; | ||
112 | + } else { | 541 | + } else { |
113 | + vec = &s->vectors[irq]; | 542 | + return false; |
114 | + } | 543 | + } |
115 | + } | 544 | + } |
116 | + | 545 | + |
117 | + if (!vec->enabled || | 546 | + if (a->l) { |
118 | + nvic_exec_prio(s) <= exc_group_prio(s, vec->prio, secure)) { | 547 | + /* VMRS, move FP system register to gp register */ |
119 | + if (!(fpccr_s & R_V7M_FPCCR_HFRDY_MASK)) { | 548 | + return gen_M_fp_sysreg_read(s, a->reg, fp_sysreg_to_gpr, a); |
120 | + /* | 549 | + } else { |
121 | + * We want to escalate to HardFault but the context the | 550 | + /* VMSR, move gp register to FP system register */ |
122 | + * FP state belongs to prevents the exception pre-empting. | 551 | + return gen_M_fp_sysreg_write(s, a->reg, gpr_to_fp_sysreg, a); |
123 | + */ | 552 | + } |
124 | + cpu_abort(&s->cpu->parent_obj, | 553 | +} |
125 | + "Lockup: can't escalate to HardFault during " | 554 | + |
126 | + "lazy FP register stacking\n"); | 555 | +static void fp_sysreg_to_memory(DisasContext *s, void *opaque, TCGv_i32 value) |
556 | +{ | ||
557 | + arg_vldr_sysreg *a = opaque; | ||
558 | + uint32_t offset = a->imm; | ||
559 | + TCGv_i32 addr; | ||
560 | + | ||
561 | + if (!a->a) { | ||
562 | + offset = -offset; | ||
563 | + } | ||
564 | + | ||
565 | + addr = load_reg(s, a->rn); | ||
566 | + if (a->p) { | ||
567 | + tcg_gen_addi_i32(addr, addr, offset); | ||
568 | + } | ||
569 | + | ||
570 | + if (s->v8m_stackcheck && a->rn == 13 && a->w) { | ||
571 | + gen_helper_v8m_stackcheck(cpu_env, addr); | ||
572 | + } | ||
573 | + | ||
574 | + gen_aa32_st_i32(s, value, addr, get_mem_index(s), | ||
575 | + MO_UL | MO_ALIGN | s->be_data); | ||
576 | + tcg_temp_free_i32(value); | ||
577 | + | ||
578 | + if (a->w) { | ||
579 | + /* writeback */ | ||
580 | + if (!a->p) { | ||
581 | + tcg_gen_addi_i32(addr, addr, offset); | ||
127 | + } | 582 | + } |
128 | + } | 583 | + store_reg(s, a->rn, addr); |
129 | + | 584 | + } else { |
130 | + if (escalate) { | 585 | + tcg_temp_free_i32(addr); |
131 | + s->cpu->env.v7m.hfsr |= R_V7M_HFSR_FORCED_MASK; | ||
132 | + } | ||
133 | + if (!vec->pending) { | ||
134 | + vec->pending = 1; | ||
135 | + /* | ||
136 | + * We do not call nvic_irq_update(), because we know our caller | ||
137 | + * is going to handle causing us to take the exception by | ||
138 | + * raising EXCP_LAZYFP, so raising the IRQ line would be | ||
139 | + * pointless extra work. We just need to recompute the | ||
140 | + * priorities so that armv7m_nvic_can_take_pending_exception() | ||
141 | + * returns the right answer. | ||
142 | + */ | ||
143 | + nvic_recompute_state(s); | ||
144 | + } | 586 | + } |
145 | +} | 587 | +} |
146 | + | 588 | + |
147 | /* Make pending IRQ active. */ | 589 | +static TCGv_i32 memory_to_fp_sysreg(DisasContext *s, void *opaque) |
148 | void armv7m_nvic_acknowledge_irq(void *opaque) | 590 | +{ |
591 | + arg_vldr_sysreg *a = opaque; | ||
592 | + uint32_t offset = a->imm; | ||
593 | + TCGv_i32 addr; | ||
594 | + TCGv_i32 value = tcg_temp_new_i32(); | ||
595 | + | ||
596 | + if (!a->a) { | ||
597 | + offset = -offset; | ||
598 | + } | ||
599 | + | ||
600 | + addr = load_reg(s, a->rn); | ||
601 | + if (a->p) { | ||
602 | + tcg_gen_addi_i32(addr, addr, offset); | ||
603 | + } | ||
604 | + | ||
605 | + if (s->v8m_stackcheck && a->rn == 13 && a->w) { | ||
606 | + gen_helper_v8m_stackcheck(cpu_env, addr); | ||
607 | + } | ||
608 | + | ||
609 | + gen_aa32_ld_i32(s, value, addr, get_mem_index(s), | ||
610 | + MO_UL | MO_ALIGN | s->be_data); | ||
611 | + | ||
612 | + if (a->w) { | ||
613 | + /* writeback */ | ||
614 | + if (!a->p) { | ||
615 | + tcg_gen_addi_i32(addr, addr, offset); | ||
616 | + } | ||
617 | + store_reg(s, a->rn, addr); | ||
618 | + } else { | ||
619 | + tcg_temp_free_i32(addr); | ||
620 | + } | ||
621 | + return value; | ||
622 | +} | ||
623 | + | ||
624 | +static bool trans_VLDR_sysreg(DisasContext *s, arg_vldr_sysreg *a) | ||
625 | +{ | ||
626 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
627 | + return false; | ||
628 | + } | ||
629 | + if (a->rn == 15) { | ||
630 | + return false; | ||
631 | + } | ||
632 | + return gen_M_fp_sysreg_write(s, a->reg, memory_to_fp_sysreg, a); | ||
633 | +} | ||
634 | + | ||
635 | +static bool trans_VSTR_sysreg(DisasContext *s, arg_vldr_sysreg *a) | ||
636 | +{ | ||
637 | + if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
638 | + return false; | ||
639 | + } | ||
640 | + if (a->rn == 15) { | ||
641 | + return false; | ||
642 | + } | ||
643 | + return gen_M_fp_sysreg_read(s, a->reg, fp_sysreg_to_memory, a); | ||
644 | +} | ||
645 | + | ||
646 | static bool trans_NOCP(DisasContext *s, arg_nocp *a) | ||
647 | { | ||
648 | /* | ||
649 | diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c | ||
650 | index XXXXXXX..XXXXXXX 100644 | ||
651 | --- a/target/arm/translate-vfp.c | ||
652 | +++ b/target/arm/translate-vfp.c | ||
653 | @@ -XXX,XX +XXX,XX @@ static inline long vfp_f16_offset(unsigned reg, bool top) | ||
654 | * Generate code for M-profile lazy FP state preservation if needed; | ||
655 | * this corresponds to the pseudocode PreserveFPState() function. | ||
656 | */ | ||
657 | -static void gen_preserve_fp_state(DisasContext *s) | ||
658 | +void gen_preserve_fp_state(DisasContext *s) | ||
659 | { | ||
660 | if (s->v7m_lspact) { | ||
661 | /* | ||
662 | @@ -XXX,XX +XXX,XX @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a) | ||
663 | return true; | ||
664 | } | ||
665 | |||
666 | -/* | ||
667 | - * M-profile provides two different sets of instructions that can | ||
668 | - * access floating point system registers: VMSR/VMRS (which move | ||
669 | - * to/from a general purpose register) and VLDR/VSTR sysreg (which | ||
670 | - * move directly to/from memory). In some cases there are also side | ||
671 | - * effects which must happen after any write to memory (which could | ||
672 | - * cause an exception). So we implement the common logic for the | ||
673 | - * sysreg access in gen_M_fp_sysreg_write() and gen_M_fp_sysreg_read(), | ||
674 | - * which take pointers to callback functions which will perform the | ||
675 | - * actual "read/write general purpose register" and "read/write | ||
676 | - * memory" operations. | ||
677 | - */ | ||
678 | - | ||
679 | -/* | ||
680 | - * Emit code to store the sysreg to its final destination; frees the | ||
681 | - * TCG temp 'value' it is passed. | ||
682 | - */ | ||
683 | -typedef void fp_sysreg_storefn(DisasContext *s, void *opaque, TCGv_i32 value); | ||
684 | -/* | ||
685 | - * Emit code to load the value to be copied to the sysreg; returns | ||
686 | - * a new TCG temporary | ||
687 | - */ | ||
688 | -typedef TCGv_i32 fp_sysreg_loadfn(DisasContext *s, void *opaque); | ||
689 | - | ||
690 | -/* Common decode/access checks for fp sysreg read/write */ | ||
691 | -typedef enum FPSysRegCheckResult { | ||
692 | - FPSysRegCheckFailed, /* caller should return false */ | ||
693 | - FPSysRegCheckDone, /* caller should return true */ | ||
694 | - FPSysRegCheckContinue, /* caller should continue generating code */ | ||
695 | -} FPSysRegCheckResult; | ||
696 | - | ||
697 | -static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno) | ||
698 | -{ | ||
699 | - if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)) { | ||
700 | - return FPSysRegCheckFailed; | ||
701 | - } | ||
702 | - | ||
703 | - switch (regno) { | ||
704 | - case ARM_VFP_FPSCR: | ||
705 | - case QEMU_VFP_FPSCR_NZCV: | ||
706 | - break; | ||
707 | - case ARM_VFP_FPSCR_NZCVQC: | ||
708 | - if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
709 | - return FPSysRegCheckFailed; | ||
710 | - } | ||
711 | - break; | ||
712 | - case ARM_VFP_FPCXT_S: | ||
713 | - case ARM_VFP_FPCXT_NS: | ||
714 | - if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
715 | - return FPSysRegCheckFailed; | ||
716 | - } | ||
717 | - if (!s->v8m_secure) { | ||
718 | - return FPSysRegCheckFailed; | ||
719 | - } | ||
720 | - break; | ||
721 | - case ARM_VFP_VPR: | ||
722 | - case ARM_VFP_P0: | ||
723 | - if (!dc_isar_feature(aa32_mve, s)) { | ||
724 | - return FPSysRegCheckFailed; | ||
725 | - } | ||
726 | - break; | ||
727 | - default: | ||
728 | - return FPSysRegCheckFailed; | ||
729 | - } | ||
730 | - | ||
731 | - /* | ||
732 | - * FPCXT_NS is a special case: it has specific handling for | ||
733 | - * "current FP state is inactive", and must do the PreserveFPState() | ||
734 | - * but not the usual full set of actions done by ExecuteFPCheck(). | ||
735 | - * So we don't call vfp_access_check() and the callers must handle this. | ||
736 | - */ | ||
737 | - if (regno != ARM_VFP_FPCXT_NS && !vfp_access_check(s)) { | ||
738 | - return FPSysRegCheckDone; | ||
739 | - } | ||
740 | - return FPSysRegCheckContinue; | ||
741 | -} | ||
742 | - | ||
743 | -static void gen_branch_fpInactive(DisasContext *s, TCGCond cond, | ||
744 | - TCGLabel *label) | ||
745 | -{ | ||
746 | - /* | ||
747 | - * FPCXT_NS is a special case: it has specific handling for | ||
748 | - * "current FP state is inactive", and must do the PreserveFPState() | ||
749 | - * but not the usual full set of actions done by ExecuteFPCheck(). | ||
750 | - * We don't have a TB flag that matches the fpInactive check, so we | ||
751 | - * do it at runtime as we don't expect FPCXT_NS accesses to be frequent. | ||
752 | - * | ||
753 | - * Emit code that checks fpInactive and does a conditional | ||
754 | - * branch to label based on it: | ||
755 | - * if cond is TCG_COND_NE then branch if fpInactive != 0 (ie if inactive) | ||
756 | - * if cond is TCG_COND_EQ then branch if fpInactive == 0 (ie if active) | ||
757 | - */ | ||
758 | - assert(cond == TCG_COND_EQ || cond == TCG_COND_NE); | ||
759 | - | ||
760 | - /* fpInactive = FPCCR_NS.ASPEN == 1 && CONTROL.FPCA == 0 */ | ||
761 | - TCGv_i32 aspen, fpca; | ||
762 | - aspen = load_cpu_field(v7m.fpccr[M_REG_NS]); | ||
763 | - fpca = load_cpu_field(v7m.control[M_REG_S]); | ||
764 | - tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); | ||
765 | - tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK); | ||
766 | - tcg_gen_andi_i32(fpca, fpca, R_V7M_CONTROL_FPCA_MASK); | ||
767 | - tcg_gen_or_i32(fpca, fpca, aspen); | ||
768 | - tcg_gen_brcondi_i32(tcg_invert_cond(cond), fpca, 0, label); | ||
769 | - tcg_temp_free_i32(aspen); | ||
770 | - tcg_temp_free_i32(fpca); | ||
771 | -} | ||
772 | - | ||
773 | -static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, | ||
774 | - fp_sysreg_loadfn *loadfn, | ||
775 | - void *opaque) | ||
776 | -{ | ||
777 | - /* Do a write to an M-profile floating point system register */ | ||
778 | - TCGv_i32 tmp; | ||
779 | - TCGLabel *lab_end = NULL; | ||
780 | - | ||
781 | - switch (fp_sysreg_checks(s, regno)) { | ||
782 | - case FPSysRegCheckFailed: | ||
783 | - return false; | ||
784 | - case FPSysRegCheckDone: | ||
785 | - return true; | ||
786 | - case FPSysRegCheckContinue: | ||
787 | - break; | ||
788 | - } | ||
789 | - | ||
790 | - switch (regno) { | ||
791 | - case ARM_VFP_FPSCR: | ||
792 | - tmp = loadfn(s, opaque); | ||
793 | - gen_helper_vfp_set_fpscr(cpu_env, tmp); | ||
794 | - tcg_temp_free_i32(tmp); | ||
795 | - gen_lookup_tb(s); | ||
796 | - break; | ||
797 | - case ARM_VFP_FPSCR_NZCVQC: | ||
798 | - { | ||
799 | - TCGv_i32 fpscr; | ||
800 | - tmp = loadfn(s, opaque); | ||
801 | - if (dc_isar_feature(aa32_mve, s)) { | ||
802 | - /* QC is only present for MVE; otherwise RES0 */ | ||
803 | - TCGv_i32 qc = tcg_temp_new_i32(); | ||
804 | - tcg_gen_andi_i32(qc, tmp, FPCR_QC); | ||
805 | - /* | ||
806 | - * The 4 vfp.qc[] fields need only be "zero" vs "non-zero"; | ||
807 | - * here writing the same value into all elements is simplest. | ||
808 | - */ | ||
809 | - tcg_gen_gvec_dup_i32(MO_32, offsetof(CPUARMState, vfp.qc), | ||
810 | - 16, 16, qc); | ||
811 | - } | ||
812 | - tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); | ||
813 | - fpscr = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); | ||
814 | - tcg_gen_andi_i32(fpscr, fpscr, ~FPCR_NZCV_MASK); | ||
815 | - tcg_gen_or_i32(fpscr, fpscr, tmp); | ||
816 | - store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]); | ||
817 | - tcg_temp_free_i32(tmp); | ||
818 | - break; | ||
819 | - } | ||
820 | - case ARM_VFP_FPCXT_NS: | ||
821 | - lab_end = gen_new_label(); | ||
822 | - /* fpInactive case: write is a NOP, so branch to end */ | ||
823 | - gen_branch_fpInactive(s, TCG_COND_NE, lab_end); | ||
824 | - /* | ||
825 | - * !fpInactive: if FPU disabled, take NOCP exception; | ||
826 | - * otherwise PreserveFPState(), and then FPCXT_NS writes | ||
827 | - * behave the same as FPCXT_S writes. | ||
828 | - */ | ||
829 | - if (s->fp_excp_el) { | ||
830 | - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
831 | - syn_uncategorized(), s->fp_excp_el); | ||
832 | - /* | ||
833 | - * This was only a conditional exception, so override | ||
834 | - * gen_exception_insn()'s default to DISAS_NORETURN | ||
835 | - */ | ||
836 | - s->base.is_jmp = DISAS_NEXT; | ||
837 | - break; | ||
838 | - } | ||
839 | - gen_preserve_fp_state(s); | ||
840 | - /* fall through */ | ||
841 | - case ARM_VFP_FPCXT_S: | ||
842 | - { | ||
843 | - TCGv_i32 sfpa, control; | ||
844 | - /* | ||
845 | - * Set FPSCR and CONTROL.SFPA from value; the new FPSCR takes | ||
846 | - * bits [27:0] from value and zeroes bits [31:28]. | ||
847 | - */ | ||
848 | - tmp = loadfn(s, opaque); | ||
849 | - sfpa = tcg_temp_new_i32(); | ||
850 | - tcg_gen_shri_i32(sfpa, tmp, 31); | ||
851 | - control = load_cpu_field(v7m.control[M_REG_S]); | ||
852 | - tcg_gen_deposit_i32(control, control, sfpa, | ||
853 | - R_V7M_CONTROL_SFPA_SHIFT, 1); | ||
854 | - store_cpu_field(control, v7m.control[M_REG_S]); | ||
855 | - tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK); | ||
856 | - gen_helper_vfp_set_fpscr(cpu_env, tmp); | ||
857 | - tcg_temp_free_i32(tmp); | ||
858 | - tcg_temp_free_i32(sfpa); | ||
859 | - break; | ||
860 | - } | ||
861 | - case ARM_VFP_VPR: | ||
862 | - /* Behaves as NOP if not privileged */ | ||
863 | - if (IS_USER(s)) { | ||
864 | - break; | ||
865 | - } | ||
866 | - tmp = loadfn(s, opaque); | ||
867 | - store_cpu_field(tmp, v7m.vpr); | ||
868 | - break; | ||
869 | - case ARM_VFP_P0: | ||
870 | - { | ||
871 | - TCGv_i32 vpr; | ||
872 | - tmp = loadfn(s, opaque); | ||
873 | - vpr = load_cpu_field(v7m.vpr); | ||
874 | - tcg_gen_deposit_i32(vpr, vpr, tmp, | ||
875 | - R_V7M_VPR_P0_SHIFT, R_V7M_VPR_P0_LENGTH); | ||
876 | - store_cpu_field(vpr, v7m.vpr); | ||
877 | - tcg_temp_free_i32(tmp); | ||
878 | - break; | ||
879 | - } | ||
880 | - default: | ||
881 | - g_assert_not_reached(); | ||
882 | - } | ||
883 | - if (lab_end) { | ||
884 | - gen_set_label(lab_end); | ||
885 | - } | ||
886 | - return true; | ||
887 | -} | ||
888 | - | ||
889 | -static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, | ||
890 | - fp_sysreg_storefn *storefn, | ||
891 | - void *opaque) | ||
892 | -{ | ||
893 | - /* Do a read from an M-profile floating point system register */ | ||
894 | - TCGv_i32 tmp; | ||
895 | - TCGLabel *lab_end = NULL; | ||
896 | - bool lookup_tb = false; | ||
897 | - | ||
898 | - switch (fp_sysreg_checks(s, regno)) { | ||
899 | - case FPSysRegCheckFailed: | ||
900 | - return false; | ||
901 | - case FPSysRegCheckDone: | ||
902 | - return true; | ||
903 | - case FPSysRegCheckContinue: | ||
904 | - break; | ||
905 | - } | ||
906 | - | ||
907 | - if (regno == ARM_VFP_FPSCR_NZCVQC && !dc_isar_feature(aa32_mve, s)) { | ||
908 | - /* QC is RES0 without MVE, so NZCVQC simplifies to NZCV */ | ||
909 | - regno = QEMU_VFP_FPSCR_NZCV; | ||
910 | - } | ||
911 | - | ||
912 | - switch (regno) { | ||
913 | - case ARM_VFP_FPSCR: | ||
914 | - tmp = tcg_temp_new_i32(); | ||
915 | - gen_helper_vfp_get_fpscr(tmp, cpu_env); | ||
916 | - storefn(s, opaque, tmp); | ||
917 | - break; | ||
918 | - case ARM_VFP_FPSCR_NZCVQC: | ||
919 | - tmp = tcg_temp_new_i32(); | ||
920 | - gen_helper_vfp_get_fpscr(tmp, cpu_env); | ||
921 | - tcg_gen_andi_i32(tmp, tmp, FPCR_NZCVQC_MASK); | ||
922 | - storefn(s, opaque, tmp); | ||
923 | - break; | ||
924 | - case QEMU_VFP_FPSCR_NZCV: | ||
925 | - /* | ||
926 | - * Read just NZCV; this is a special case to avoid the | ||
927 | - * helper call for the "VMRS to CPSR.NZCV" insn. | ||
928 | - */ | ||
929 | - tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); | ||
930 | - tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); | ||
931 | - storefn(s, opaque, tmp); | ||
932 | - break; | ||
933 | - case ARM_VFP_FPCXT_S: | ||
934 | - { | ||
935 | - TCGv_i32 control, sfpa, fpscr; | ||
936 | - /* Bits [27:0] from FPSCR, bit [31] from CONTROL.SFPA */ | ||
937 | - tmp = tcg_temp_new_i32(); | ||
938 | - sfpa = tcg_temp_new_i32(); | ||
939 | - gen_helper_vfp_get_fpscr(tmp, cpu_env); | ||
940 | - tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK); | ||
941 | - control = load_cpu_field(v7m.control[M_REG_S]); | ||
942 | - tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK); | ||
943 | - tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT); | ||
944 | - tcg_gen_or_i32(tmp, tmp, sfpa); | ||
945 | - tcg_temp_free_i32(sfpa); | ||
946 | - /* | ||
947 | - * Store result before updating FPSCR etc, in case | ||
948 | - * it is a memory write which causes an exception. | ||
949 | - */ | ||
950 | - storefn(s, opaque, tmp); | ||
951 | - /* | ||
952 | - * Now we must reset FPSCR from FPDSCR_NS, and clear | ||
953 | - * CONTROL.SFPA; so we'll end the TB here. | ||
954 | - */ | ||
955 | - tcg_gen_andi_i32(control, control, ~R_V7M_CONTROL_SFPA_MASK); | ||
956 | - store_cpu_field(control, v7m.control[M_REG_S]); | ||
957 | - fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]); | ||
958 | - gen_helper_vfp_set_fpscr(cpu_env, fpscr); | ||
959 | - tcg_temp_free_i32(fpscr); | ||
960 | - lookup_tb = true; | ||
961 | - break; | ||
962 | - } | ||
963 | - case ARM_VFP_FPCXT_NS: | ||
964 | - { | ||
965 | - TCGv_i32 control, sfpa, fpscr, fpdscr, zero; | ||
966 | - TCGLabel *lab_active = gen_new_label(); | ||
967 | - | ||
968 | - lookup_tb = true; | ||
969 | - | ||
970 | - gen_branch_fpInactive(s, TCG_COND_EQ, lab_active); | ||
971 | - /* fpInactive case: reads as FPDSCR_NS */ | ||
972 | - TCGv_i32 tmp = load_cpu_field(v7m.fpdscr[M_REG_NS]); | ||
973 | - storefn(s, opaque, tmp); | ||
974 | - lab_end = gen_new_label(); | ||
975 | - tcg_gen_br(lab_end); | ||
976 | - | ||
977 | - gen_set_label(lab_active); | ||
978 | - /* | ||
979 | - * !fpInactive: if FPU disabled, take NOCP exception; | ||
980 | - * otherwise PreserveFPState(), and then FPCXT_NS | ||
981 | - * reads the same as FPCXT_S. | ||
982 | - */ | ||
983 | - if (s->fp_excp_el) { | ||
984 | - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
985 | - syn_uncategorized(), s->fp_excp_el); | ||
986 | - /* | ||
987 | - * This was only a conditional exception, so override | ||
988 | - * gen_exception_insn()'s default to DISAS_NORETURN | ||
989 | - */ | ||
990 | - s->base.is_jmp = DISAS_NEXT; | ||
991 | - break; | ||
992 | - } | ||
993 | - gen_preserve_fp_state(s); | ||
994 | - tmp = tcg_temp_new_i32(); | ||
995 | - sfpa = tcg_temp_new_i32(); | ||
996 | - fpscr = tcg_temp_new_i32(); | ||
997 | - gen_helper_vfp_get_fpscr(fpscr, cpu_env); | ||
998 | - tcg_gen_andi_i32(tmp, fpscr, ~FPCR_NZCV_MASK); | ||
999 | - control = load_cpu_field(v7m.control[M_REG_S]); | ||
1000 | - tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK); | ||
1001 | - tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT); | ||
1002 | - tcg_gen_or_i32(tmp, tmp, sfpa); | ||
1003 | - tcg_temp_free_i32(control); | ||
1004 | - /* Store result before updating FPSCR, in case it faults */ | ||
1005 | - storefn(s, opaque, tmp); | ||
1006 | - /* If SFPA is zero then set FPSCR from FPDSCR_NS */ | ||
1007 | - fpdscr = load_cpu_field(v7m.fpdscr[M_REG_NS]); | ||
1008 | - zero = tcg_const_i32(0); | ||
1009 | - tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, zero, fpdscr, fpscr); | ||
1010 | - gen_helper_vfp_set_fpscr(cpu_env, fpscr); | ||
1011 | - tcg_temp_free_i32(zero); | ||
1012 | - tcg_temp_free_i32(sfpa); | ||
1013 | - tcg_temp_free_i32(fpdscr); | ||
1014 | - tcg_temp_free_i32(fpscr); | ||
1015 | - break; | ||
1016 | - } | ||
1017 | - case ARM_VFP_VPR: | ||
1018 | - /* Behaves as NOP if not privileged */ | ||
1019 | - if (IS_USER(s)) { | ||
1020 | - break; | ||
1021 | - } | ||
1022 | - tmp = load_cpu_field(v7m.vpr); | ||
1023 | - storefn(s, opaque, tmp); | ||
1024 | - break; | ||
1025 | - case ARM_VFP_P0: | ||
1026 | - tmp = load_cpu_field(v7m.vpr); | ||
1027 | - tcg_gen_extract_i32(tmp, tmp, R_V7M_VPR_P0_SHIFT, R_V7M_VPR_P0_LENGTH); | ||
1028 | - storefn(s, opaque, tmp); | ||
1029 | - break; | ||
1030 | - default: | ||
1031 | - g_assert_not_reached(); | ||
1032 | - } | ||
1033 | - | ||
1034 | - if (lab_end) { | ||
1035 | - gen_set_label(lab_end); | ||
1036 | - } | ||
1037 | - if (lookup_tb) { | ||
1038 | - gen_lookup_tb(s); | ||
1039 | - } | ||
1040 | - return true; | ||
1041 | -} | ||
1042 | - | ||
1043 | -static void fp_sysreg_to_gpr(DisasContext *s, void *opaque, TCGv_i32 value) | ||
1044 | -{ | ||
1045 | - arg_VMSR_VMRS *a = opaque; | ||
1046 | - | ||
1047 | - if (a->rt == 15) { | ||
1048 | - /* Set the 4 flag bits in the CPSR */ | ||
1049 | - gen_set_nzcv(value); | ||
1050 | - tcg_temp_free_i32(value); | ||
1051 | - } else { | ||
1052 | - store_reg(s, a->rt, value); | ||
1053 | - } | ||
1054 | -} | ||
1055 | - | ||
1056 | -static TCGv_i32 gpr_to_fp_sysreg(DisasContext *s, void *opaque) | ||
1057 | -{ | ||
1058 | - arg_VMSR_VMRS *a = opaque; | ||
1059 | - | ||
1060 | - return load_reg(s, a->rt); | ||
1061 | -} | ||
1062 | - | ||
1063 | -static bool gen_M_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) | ||
1064 | -{ | ||
1065 | - /* | ||
1066 | - * Accesses to R15 are UNPREDICTABLE; we choose to undef. | ||
1067 | - * FPSCR -> r15 is a special case which writes to the PSR flags; | ||
1068 | - * set a->reg to a special value to tell gen_M_fp_sysreg_read() | ||
1069 | - * we only care about the top 4 bits of FPSCR there. | ||
1070 | - */ | ||
1071 | - if (a->rt == 15) { | ||
1072 | - if (a->l && a->reg == ARM_VFP_FPSCR) { | ||
1073 | - a->reg = QEMU_VFP_FPSCR_NZCV; | ||
1074 | - } else { | ||
1075 | - return false; | ||
1076 | - } | ||
1077 | - } | ||
1078 | - | ||
1079 | - if (a->l) { | ||
1080 | - /* VMRS, move FP system register to gp register */ | ||
1081 | - return gen_M_fp_sysreg_read(s, a->reg, fp_sysreg_to_gpr, a); | ||
1082 | - } else { | ||
1083 | - /* VMSR, move gp register to FP system register */ | ||
1084 | - return gen_M_fp_sysreg_write(s, a->reg, gpr_to_fp_sysreg, a); | ||
1085 | - } | ||
1086 | -} | ||
1087 | - | ||
1088 | static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) | ||
1089 | { | ||
1090 | TCGv_i32 tmp; | ||
1091 | bool ignore_vfp_enabled = false; | ||
1092 | |||
1093 | if (arm_dc_feature(s, ARM_FEATURE_M)) { | ||
1094 | - return gen_M_VMSR_VMRS(s, a); | ||
1095 | + /* M profile version was already handled in m-nocp.decode */ | ||
1096 | + return false; | ||
1097 | } | ||
1098 | |||
1099 | if (!dc_isar_feature(aa32_fpsp_v2, s)) { | ||
1100 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) | ||
1101 | return true; | ||
1102 | } | ||
1103 | |||
1104 | -static void fp_sysreg_to_memory(DisasContext *s, void *opaque, TCGv_i32 value) | ||
1105 | -{ | ||
1106 | - arg_vldr_sysreg *a = opaque; | ||
1107 | - uint32_t offset = a->imm; | ||
1108 | - TCGv_i32 addr; | ||
1109 | - | ||
1110 | - if (!a->a) { | ||
1111 | - offset = -offset; | ||
1112 | - } | ||
1113 | - | ||
1114 | - addr = load_reg(s, a->rn); | ||
1115 | - if (a->p) { | ||
1116 | - tcg_gen_addi_i32(addr, addr, offset); | ||
1117 | - } | ||
1118 | - | ||
1119 | - if (s->v8m_stackcheck && a->rn == 13 && a->w) { | ||
1120 | - gen_helper_v8m_stackcheck(cpu_env, addr); | ||
1121 | - } | ||
1122 | - | ||
1123 | - gen_aa32_st_i32(s, value, addr, get_mem_index(s), | ||
1124 | - MO_UL | MO_ALIGN | s->be_data); | ||
1125 | - tcg_temp_free_i32(value); | ||
1126 | - | ||
1127 | - if (a->w) { | ||
1128 | - /* writeback */ | ||
1129 | - if (!a->p) { | ||
1130 | - tcg_gen_addi_i32(addr, addr, offset); | ||
1131 | - } | ||
1132 | - store_reg(s, a->rn, addr); | ||
1133 | - } else { | ||
1134 | - tcg_temp_free_i32(addr); | ||
1135 | - } | ||
1136 | -} | ||
1137 | - | ||
1138 | -static TCGv_i32 memory_to_fp_sysreg(DisasContext *s, void *opaque) | ||
1139 | -{ | ||
1140 | - arg_vldr_sysreg *a = opaque; | ||
1141 | - uint32_t offset = a->imm; | ||
1142 | - TCGv_i32 addr; | ||
1143 | - TCGv_i32 value = tcg_temp_new_i32(); | ||
1144 | - | ||
1145 | - if (!a->a) { | ||
1146 | - offset = -offset; | ||
1147 | - } | ||
1148 | - | ||
1149 | - addr = load_reg(s, a->rn); | ||
1150 | - if (a->p) { | ||
1151 | - tcg_gen_addi_i32(addr, addr, offset); | ||
1152 | - } | ||
1153 | - | ||
1154 | - if (s->v8m_stackcheck && a->rn == 13 && a->w) { | ||
1155 | - gen_helper_v8m_stackcheck(cpu_env, addr); | ||
1156 | - } | ||
1157 | - | ||
1158 | - gen_aa32_ld_i32(s, value, addr, get_mem_index(s), | ||
1159 | - MO_UL | MO_ALIGN | s->be_data); | ||
1160 | - | ||
1161 | - if (a->w) { | ||
1162 | - /* writeback */ | ||
1163 | - if (!a->p) { | ||
1164 | - tcg_gen_addi_i32(addr, addr, offset); | ||
1165 | - } | ||
1166 | - store_reg(s, a->rn, addr); | ||
1167 | - } else { | ||
1168 | - tcg_temp_free_i32(addr); | ||
1169 | - } | ||
1170 | - return value; | ||
1171 | -} | ||
1172 | - | ||
1173 | -static bool trans_VLDR_sysreg(DisasContext *s, arg_vldr_sysreg *a) | ||
1174 | -{ | ||
1175 | - if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
1176 | - return false; | ||
1177 | - } | ||
1178 | - if (a->rn == 15) { | ||
1179 | - return false; | ||
1180 | - } | ||
1181 | - return gen_M_fp_sysreg_write(s, a->reg, memory_to_fp_sysreg, a); | ||
1182 | -} | ||
1183 | - | ||
1184 | -static bool trans_VSTR_sysreg(DisasContext *s, arg_vldr_sysreg *a) | ||
1185 | -{ | ||
1186 | - if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) { | ||
1187 | - return false; | ||
1188 | - } | ||
1189 | - if (a->rn == 15) { | ||
1190 | - return false; | ||
1191 | - } | ||
1192 | - return gen_M_fp_sysreg_read(s, a->reg, fp_sysreg_to_memory, a); | ||
1193 | -} | ||
1194 | |||
1195 | static bool trans_VMOV_half(DisasContext *s, arg_VMOV_single *a) | ||
149 | { | 1196 | { |
150 | -- | 1197 | -- |
151 | 2.20.1 | 1198 | 2.20.1 |
152 | 1199 | ||
153 | 1200 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | A few subcases of VLDR/VSTR sysreg succeed but do not perform a | |
2 | memory access: | ||
3 | * VSTR of VPR when unprivileged | ||
4 | * VLDR to VPR when unprivileged | ||
5 | * VLDR to FPCXT_NS when fpInactive | ||
6 | |||
7 | In these cases, even though we don't do the memory access we should | ||
8 | still update the base register and perform the stack limit check if | ||
9 | the insn's addressing mode specifies writeback. Our implementation | ||
10 | failed to do this, because we handle these side-effects inside the | ||
11 | memory_to_fp_sysreg() and fp_sysreg_to_memory() callback functions, | ||
12 | which are only called if there's something to load or store. | ||
13 | |||
14 | Fix this by adding an extra argument to the callbacks which is set to | ||
15 | true to actually perform the access and false to only do side effects | ||
16 | like writeback, and calling the callback with do_access = false | ||
17 | for the three cases listed above. | ||
18 | |||
19 | This produces slightly suboptimal code for the case of a write | ||
20 | to FPCXT_NS when the FPU is inactive and the insn didn't have | ||
21 | side effects (ie no writeback, or via VMSR), in which case we'll | ||
22 | generate a conditional branch over an unconditional branch. | ||
23 | But this doesn't seem to be important enough to merit requiring | ||
24 | the callback to report back whether it generated any code or not. | ||
25 | |||
26 | Cc: qemu-stable@nongnu.org | ||
27 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
28 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
29 | Message-id: 20210618141019.10671-5-peter.maydell@linaro.org | ||
30 | --- | ||
31 | target/arm/translate-m-nocp.c | 102 ++++++++++++++++++++++++---------- | ||
32 | 1 file changed, 72 insertions(+), 30 deletions(-) | ||
33 | |||
34 | diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/target/arm/translate-m-nocp.c | ||
37 | +++ b/target/arm/translate-m-nocp.c | ||
38 | @@ -XXX,XX +XXX,XX @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a) | ||
39 | |||
40 | /* | ||
41 | * Emit code to store the sysreg to its final destination; frees the | ||
42 | - * TCG temp 'value' it is passed. | ||
43 | + * TCG temp 'value' it is passed. do_access is true to do the store, | ||
44 | + * and false to skip it and only perform side-effects like base | ||
45 | + * register writeback. | ||
46 | */ | ||
47 | -typedef void fp_sysreg_storefn(DisasContext *s, void *opaque, TCGv_i32 value); | ||
48 | +typedef void fp_sysreg_storefn(DisasContext *s, void *opaque, TCGv_i32 value, | ||
49 | + bool do_access); | ||
50 | /* | ||
51 | * Emit code to load the value to be copied to the sysreg; returns | ||
52 | - * a new TCG temporary | ||
53 | + * a new TCG temporary. do_access is true to do the store, | ||
54 | + * and false to skip it and only perform side-effects like base | ||
55 | + * register writeback. | ||
56 | */ | ||
57 | -typedef TCGv_i32 fp_sysreg_loadfn(DisasContext *s, void *opaque); | ||
58 | +typedef TCGv_i32 fp_sysreg_loadfn(DisasContext *s, void *opaque, | ||
59 | + bool do_access); | ||
60 | |||
61 | /* Common decode/access checks for fp sysreg read/write */ | ||
62 | typedef enum FPSysRegCheckResult { | ||
63 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, | ||
64 | |||
65 | switch (regno) { | ||
66 | case ARM_VFP_FPSCR: | ||
67 | - tmp = loadfn(s, opaque); | ||
68 | + tmp = loadfn(s, opaque, true); | ||
69 | gen_helper_vfp_set_fpscr(cpu_env, tmp); | ||
70 | tcg_temp_free_i32(tmp); | ||
71 | gen_lookup_tb(s); | ||
72 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, | ||
73 | case ARM_VFP_FPSCR_NZCVQC: | ||
74 | { | ||
75 | TCGv_i32 fpscr; | ||
76 | - tmp = loadfn(s, opaque); | ||
77 | + tmp = loadfn(s, opaque, true); | ||
78 | if (dc_isar_feature(aa32_mve, s)) { | ||
79 | /* QC is only present for MVE; otherwise RES0 */ | ||
80 | TCGv_i32 qc = tcg_temp_new_i32(); | ||
81 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, | ||
82 | break; | ||
83 | } | ||
84 | case ARM_VFP_FPCXT_NS: | ||
85 | + { | ||
86 | + TCGLabel *lab_active = gen_new_label(); | ||
87 | + | ||
88 | lab_end = gen_new_label(); | ||
89 | - /* fpInactive case: write is a NOP, so branch to end */ | ||
90 | - gen_branch_fpInactive(s, TCG_COND_NE, lab_end); | ||
91 | + gen_branch_fpInactive(s, TCG_COND_EQ, lab_active); | ||
92 | + /* | ||
93 | + * fpInactive case: write is a NOP, so only do side effects | ||
94 | + * like register writeback before we branch to end | ||
95 | + */ | ||
96 | + loadfn(s, opaque, false); | ||
97 | + tcg_gen_br(lab_end); | ||
98 | + | ||
99 | + gen_set_label(lab_active); | ||
100 | /* | ||
101 | * !fpInactive: if FPU disabled, take NOCP exception; | ||
102 | * otherwise PreserveFPState(), and then FPCXT_NS writes | ||
103 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, | ||
104 | break; | ||
105 | } | ||
106 | gen_preserve_fp_state(s); | ||
107 | - /* fall through */ | ||
108 | + } | ||
109 | + /* fall through */ | ||
110 | case ARM_VFP_FPCXT_S: | ||
111 | { | ||
112 | TCGv_i32 sfpa, control; | ||
113 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, | ||
114 | * Set FPSCR and CONTROL.SFPA from value; the new FPSCR takes | ||
115 | * bits [27:0] from value and zeroes bits [31:28]. | ||
116 | */ | ||
117 | - tmp = loadfn(s, opaque); | ||
118 | + tmp = loadfn(s, opaque, true); | ||
119 | sfpa = tcg_temp_new_i32(); | ||
120 | tcg_gen_shri_i32(sfpa, tmp, 31); | ||
121 | control = load_cpu_field(v7m.control[M_REG_S]); | ||
122 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, | ||
123 | case ARM_VFP_VPR: | ||
124 | /* Behaves as NOP if not privileged */ | ||
125 | if (IS_USER(s)) { | ||
126 | + loadfn(s, opaque, false); | ||
127 | break; | ||
128 | } | ||
129 | - tmp = loadfn(s, opaque); | ||
130 | + tmp = loadfn(s, opaque, true); | ||
131 | store_cpu_field(tmp, v7m.vpr); | ||
132 | break; | ||
133 | case ARM_VFP_P0: | ||
134 | { | ||
135 | TCGv_i32 vpr; | ||
136 | - tmp = loadfn(s, opaque); | ||
137 | + tmp = loadfn(s, opaque, true); | ||
138 | vpr = load_cpu_field(v7m.vpr); | ||
139 | tcg_gen_deposit_i32(vpr, vpr, tmp, | ||
140 | R_V7M_VPR_P0_SHIFT, R_V7M_VPR_P0_LENGTH); | ||
141 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, | ||
142 | case ARM_VFP_FPSCR: | ||
143 | tmp = tcg_temp_new_i32(); | ||
144 | gen_helper_vfp_get_fpscr(tmp, cpu_env); | ||
145 | - storefn(s, opaque, tmp); | ||
146 | + storefn(s, opaque, tmp, true); | ||
147 | break; | ||
148 | case ARM_VFP_FPSCR_NZCVQC: | ||
149 | tmp = tcg_temp_new_i32(); | ||
150 | gen_helper_vfp_get_fpscr(tmp, cpu_env); | ||
151 | tcg_gen_andi_i32(tmp, tmp, FPCR_NZCVQC_MASK); | ||
152 | - storefn(s, opaque, tmp); | ||
153 | + storefn(s, opaque, tmp, true); | ||
154 | break; | ||
155 | case QEMU_VFP_FPSCR_NZCV: | ||
156 | /* | ||
157 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, | ||
158 | */ | ||
159 | tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]); | ||
160 | tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK); | ||
161 | - storefn(s, opaque, tmp); | ||
162 | + storefn(s, opaque, tmp, true); | ||
163 | break; | ||
164 | case ARM_VFP_FPCXT_S: | ||
165 | { | ||
166 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, | ||
167 | * Store result before updating FPSCR etc, in case | ||
168 | * it is a memory write which causes an exception. | ||
169 | */ | ||
170 | - storefn(s, opaque, tmp); | ||
171 | + storefn(s, opaque, tmp, true); | ||
172 | /* | ||
173 | * Now we must reset FPSCR from FPDSCR_NS, and clear | ||
174 | * CONTROL.SFPA; so we'll end the TB here. | ||
175 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, | ||
176 | gen_branch_fpInactive(s, TCG_COND_EQ, lab_active); | ||
177 | /* fpInactive case: reads as FPDSCR_NS */ | ||
178 | TCGv_i32 tmp = load_cpu_field(v7m.fpdscr[M_REG_NS]); | ||
179 | - storefn(s, opaque, tmp); | ||
180 | + storefn(s, opaque, tmp, true); | ||
181 | lab_end = gen_new_label(); | ||
182 | tcg_gen_br(lab_end); | ||
183 | |||
184 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, | ||
185 | tcg_gen_or_i32(tmp, tmp, sfpa); | ||
186 | tcg_temp_free_i32(control); | ||
187 | /* Store result before updating FPSCR, in case it faults */ | ||
188 | - storefn(s, opaque, tmp); | ||
189 | + storefn(s, opaque, tmp, true); | ||
190 | /* If SFPA is zero then set FPSCR from FPDSCR_NS */ | ||
191 | fpdscr = load_cpu_field(v7m.fpdscr[M_REG_NS]); | ||
192 | zero = tcg_const_i32(0); | ||
193 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, | ||
194 | case ARM_VFP_VPR: | ||
195 | /* Behaves as NOP if not privileged */ | ||
196 | if (IS_USER(s)) { | ||
197 | + storefn(s, opaque, NULL, false); | ||
198 | break; | ||
199 | } | ||
200 | tmp = load_cpu_field(v7m.vpr); | ||
201 | - storefn(s, opaque, tmp); | ||
202 | + storefn(s, opaque, tmp, true); | ||
203 | break; | ||
204 | case ARM_VFP_P0: | ||
205 | tmp = load_cpu_field(v7m.vpr); | ||
206 | tcg_gen_extract_i32(tmp, tmp, R_V7M_VPR_P0_SHIFT, R_V7M_VPR_P0_LENGTH); | ||
207 | - storefn(s, opaque, tmp); | ||
208 | + storefn(s, opaque, tmp, true); | ||
209 | break; | ||
210 | default: | ||
211 | g_assert_not_reached(); | ||
212 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, | ||
213 | return true; | ||
214 | } | ||
215 | |||
216 | -static void fp_sysreg_to_gpr(DisasContext *s, void *opaque, TCGv_i32 value) | ||
217 | +static void fp_sysreg_to_gpr(DisasContext *s, void *opaque, TCGv_i32 value, | ||
218 | + bool do_access) | ||
219 | { | ||
220 | arg_VMSR_VMRS *a = opaque; | ||
221 | |||
222 | + if (!do_access) { | ||
223 | + return; | ||
224 | + } | ||
225 | + | ||
226 | if (a->rt == 15) { | ||
227 | /* Set the 4 flag bits in the CPSR */ | ||
228 | gen_set_nzcv(value); | ||
229 | @@ -XXX,XX +XXX,XX @@ static void fp_sysreg_to_gpr(DisasContext *s, void *opaque, TCGv_i32 value) | ||
230 | } | ||
231 | } | ||
232 | |||
233 | -static TCGv_i32 gpr_to_fp_sysreg(DisasContext *s, void *opaque) | ||
234 | +static TCGv_i32 gpr_to_fp_sysreg(DisasContext *s, void *opaque, bool do_access) | ||
235 | { | ||
236 | arg_VMSR_VMRS *a = opaque; | ||
237 | |||
238 | + if (!do_access) { | ||
239 | + return NULL; | ||
240 | + } | ||
241 | return load_reg(s, a->rt); | ||
242 | } | ||
243 | |||
244 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) | ||
245 | } | ||
246 | } | ||
247 | |||
248 | -static void fp_sysreg_to_memory(DisasContext *s, void *opaque, TCGv_i32 value) | ||
249 | +static void fp_sysreg_to_memory(DisasContext *s, void *opaque, TCGv_i32 value, | ||
250 | + bool do_access) | ||
251 | { | ||
252 | arg_vldr_sysreg *a = opaque; | ||
253 | uint32_t offset = a->imm; | ||
254 | @@ -XXX,XX +XXX,XX @@ static void fp_sysreg_to_memory(DisasContext *s, void *opaque, TCGv_i32 value) | ||
255 | offset = -offset; | ||
256 | } | ||
257 | |||
258 | + if (!do_access && !a->w) { | ||
259 | + return; | ||
260 | + } | ||
261 | + | ||
262 | addr = load_reg(s, a->rn); | ||
263 | if (a->p) { | ||
264 | tcg_gen_addi_i32(addr, addr, offset); | ||
265 | @@ -XXX,XX +XXX,XX @@ static void fp_sysreg_to_memory(DisasContext *s, void *opaque, TCGv_i32 value) | ||
266 | gen_helper_v8m_stackcheck(cpu_env, addr); | ||
267 | } | ||
268 | |||
269 | - gen_aa32_st_i32(s, value, addr, get_mem_index(s), | ||
270 | - MO_UL | MO_ALIGN | s->be_data); | ||
271 | - tcg_temp_free_i32(value); | ||
272 | + if (do_access) { | ||
273 | + gen_aa32_st_i32(s, value, addr, get_mem_index(s), | ||
274 | + MO_UL | MO_ALIGN | s->be_data); | ||
275 | + tcg_temp_free_i32(value); | ||
276 | + } | ||
277 | |||
278 | if (a->w) { | ||
279 | /* writeback */ | ||
280 | @@ -XXX,XX +XXX,XX @@ static void fp_sysreg_to_memory(DisasContext *s, void *opaque, TCGv_i32 value) | ||
281 | } | ||
282 | } | ||
283 | |||
284 | -static TCGv_i32 memory_to_fp_sysreg(DisasContext *s, void *opaque) | ||
285 | +static TCGv_i32 memory_to_fp_sysreg(DisasContext *s, void *opaque, | ||
286 | + bool do_access) | ||
287 | { | ||
288 | arg_vldr_sysreg *a = opaque; | ||
289 | uint32_t offset = a->imm; | ||
290 | TCGv_i32 addr; | ||
291 | - TCGv_i32 value = tcg_temp_new_i32(); | ||
292 | + TCGv_i32 value = NULL; | ||
293 | |||
294 | if (!a->a) { | ||
295 | offset = -offset; | ||
296 | } | ||
297 | |||
298 | + if (!do_access && !a->w) { | ||
299 | + return NULL; | ||
300 | + } | ||
301 | + | ||
302 | addr = load_reg(s, a->rn); | ||
303 | if (a->p) { | ||
304 | tcg_gen_addi_i32(addr, addr, offset); | ||
305 | @@ -XXX,XX +XXX,XX @@ static TCGv_i32 memory_to_fp_sysreg(DisasContext *s, void *opaque) | ||
306 | gen_helper_v8m_stackcheck(cpu_env, addr); | ||
307 | } | ||
308 | |||
309 | - gen_aa32_ld_i32(s, value, addr, get_mem_index(s), | ||
310 | - MO_UL | MO_ALIGN | s->be_data); | ||
311 | + if (do_access) { | ||
312 | + value = tcg_temp_new_i32(); | ||
313 | + gen_aa32_ld_i32(s, value, addr, get_mem_index(s), | ||
314 | + MO_UL | MO_ALIGN | s->be_data); | ||
315 | + } | ||
316 | |||
317 | if (a->w) { | ||
318 | /* writeback */ | ||
319 | -- | ||
320 | 2.20.1 | ||
321 | |||
322 | diff view generated by jsdifflib |
1 | Pushing registers to the stack for v7M needs to handle three cases: | 1 | Factor the code in full_vfp_access_check() which updates the |
---|---|---|---|
2 | * the "normal" case where we pend exceptions | 2 | ownership of the FP context and creates a new FP context |
3 | * an "ignore faults" case where we set FSR bits but | 3 | out into its own function. |
4 | do not pend exceptions (this is used when we are | ||
5 | handling some kinds of derived exception on exception entry) | ||
6 | * a "lazy FP stacking" case, where different FSR bits | ||
7 | are set and the exception is pended differently | ||
8 | |||
9 | Implement this by changing the existing flag argument that | ||
10 | tells us whether to ignore faults or not into an enum that | ||
11 | specifies which of the 3 modes we should handle. | ||
12 | 4 | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
15 | Message-id: 20190416125744.27770-23-peter.maydell@linaro.org | 7 | Message-id: 20210618141019.10671-6-peter.maydell@linaro.org |
16 | --- | 8 | --- |
17 | target/arm/helper.c | 118 +++++++++++++++++++++++++++++--------------- | 9 | target/arm/translate-vfp.c | 104 +++++++++++++++++++++---------------- |
18 | 1 file changed, 79 insertions(+), 39 deletions(-) | 10 | 1 file changed, 58 insertions(+), 46 deletions(-) |
19 | 11 | ||
20 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 12 | diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c |
21 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/target/arm/helper.c | 14 | --- a/target/arm/translate-vfp.c |
23 | +++ b/target/arm/helper.c | 15 | +++ b/target/arm/translate-vfp.c |
24 | @@ -XXX,XX +XXX,XX @@ static bool v7m_cpacr_pass(CPUARMState *env, bool is_secure, bool is_priv) | 16 | @@ -XXX,XX +XXX,XX @@ void gen_preserve_fp_state(DisasContext *s) |
25 | } | 17 | } |
26 | } | 18 | } |
27 | 19 | ||
28 | +/* | 20 | +/* |
29 | + * What kind of stack write are we doing? This affects how exceptions | 21 | + * Generate code for M-profile FP context handling: update the |
30 | + * generated during the stacking are treated. | 22 | + * ownership of the FP context, and create a new context if |
23 | + * necessary. This corresponds to the parts of the pseudocode | ||
24 | + * ExecuteFPCheck() after the inital PreserveFPState() call. | ||
31 | + */ | 25 | + */ |
32 | +typedef enum StackingMode { | 26 | +static void gen_update_fp_context(DisasContext *s) |
33 | + STACK_NORMAL, | 27 | +{ |
34 | + STACK_IGNFAULTS, | 28 | + /* Update ownership of FP context: set FPCCR.S to match current state */ |
35 | + STACK_LAZYFP, | 29 | + if (s->v8m_fpccr_s_wrong) { |
36 | +} StackingMode; | 30 | + TCGv_i32 tmp; |
37 | + | 31 | + |
38 | static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value, | 32 | + tmp = load_cpu_field(v7m.fpccr[M_REG_S]); |
39 | - ARMMMUIdx mmu_idx, bool ignfault) | 33 | + if (s->v8m_secure) { |
40 | + ARMMMUIdx mmu_idx, StackingMode mode) | 34 | + tcg_gen_ori_i32(tmp, tmp, R_V7M_FPCCR_S_MASK); |
41 | { | ||
42 | CPUState *cs = CPU(cpu); | ||
43 | CPUARMState *env = &cpu->env; | ||
44 | @@ -XXX,XX +XXX,XX @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value, | ||
45 | &attrs, &prot, &page_size, &fi, NULL)) { | ||
46 | /* MPU/SAU lookup failed */ | ||
47 | if (fi.type == ARMFault_QEMU_SFault) { | ||
48 | - qemu_log_mask(CPU_LOG_INT, | ||
49 | - "...SecureFault with SFSR.AUVIOL during stacking\n"); | ||
50 | - env->v7m.sfsr |= R_V7M_SFSR_AUVIOL_MASK | R_V7M_SFSR_SFARVALID_MASK; | ||
51 | + if (mode == STACK_LAZYFP) { | ||
52 | + qemu_log_mask(CPU_LOG_INT, | ||
53 | + "...SecureFault with SFSR.LSPERR " | ||
54 | + "during lazy stacking\n"); | ||
55 | + env->v7m.sfsr |= R_V7M_SFSR_LSPERR_MASK; | ||
56 | + } else { | ||
57 | + qemu_log_mask(CPU_LOG_INT, | ||
58 | + "...SecureFault with SFSR.AUVIOL " | ||
59 | + "during stacking\n"); | ||
60 | + env->v7m.sfsr |= R_V7M_SFSR_AUVIOL_MASK; | ||
61 | + } | ||
62 | + env->v7m.sfsr |= R_V7M_SFSR_SFARVALID_MASK; | ||
63 | env->v7m.sfar = addr; | ||
64 | exc = ARMV7M_EXCP_SECURE; | ||
65 | exc_secure = false; | ||
66 | } else { | ||
67 | - qemu_log_mask(CPU_LOG_INT, "...MemManageFault with CFSR.MSTKERR\n"); | ||
68 | - env->v7m.cfsr[secure] |= R_V7M_CFSR_MSTKERR_MASK; | ||
69 | + if (mode == STACK_LAZYFP) { | ||
70 | + qemu_log_mask(CPU_LOG_INT, | ||
71 | + "...MemManageFault with CFSR.MLSPERR\n"); | ||
72 | + env->v7m.cfsr[secure] |= R_V7M_CFSR_MLSPERR_MASK; | ||
73 | + } else { | ||
74 | + qemu_log_mask(CPU_LOG_INT, | ||
75 | + "...MemManageFault with CFSR.MSTKERR\n"); | ||
76 | + env->v7m.cfsr[secure] |= R_V7M_CFSR_MSTKERR_MASK; | ||
77 | + } | ||
78 | exc = ARMV7M_EXCP_MEM; | ||
79 | exc_secure = secure; | ||
80 | } | ||
81 | @@ -XXX,XX +XXX,XX @@ static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value, | ||
82 | attrs, &txres); | ||
83 | if (txres != MEMTX_OK) { | ||
84 | /* BusFault trying to write the data */ | ||
85 | - qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.STKERR\n"); | ||
86 | - env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_STKERR_MASK; | ||
87 | + if (mode == STACK_LAZYFP) { | ||
88 | + qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.LSPERR\n"); | ||
89 | + env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_LSPERR_MASK; | ||
90 | + } else { | 35 | + } else { |
91 | + qemu_log_mask(CPU_LOG_INT, "...BusFault with BFSR.STKERR\n"); | 36 | + tcg_gen_andi_i32(tmp, tmp, ~R_V7M_FPCCR_S_MASK); |
92 | + env->v7m.cfsr[M_REG_NS] |= R_V7M_CFSR_STKERR_MASK; | ||
93 | + } | 37 | + } |
94 | exc = ARMV7M_EXCP_BUS; | 38 | + store_cpu_field(tmp, v7m.fpccr[M_REG_S]); |
95 | exc_secure = false; | 39 | + /* Don't need to do this for any further FP insns in this TB */ |
96 | goto pend_fault; | 40 | + s->v8m_fpccr_s_wrong = false; |
97 | @@ -XXX,XX +XXX,XX @@ pend_fault: | 41 | + } |
98 | * later if we have two derived exceptions. | 42 | + |
99 | * The only case when we must not pend the exception but instead | 43 | + if (s->v7m_new_fp_ctxt_needed) { |
100 | * throw it away is if we are doing the push of the callee registers | 44 | + /* |
101 | - * and we've already generated a derived exception. Even in this | 45 | + * Create new FP context by updating CONTROL.FPCA, CONTROL.SFPA, |
102 | - * case we will still update the fault status registers. | 46 | + * the FPSCR, and VPR. |
103 | + * and we've already generated a derived exception (this is indicated | 47 | + */ |
104 | + * by the caller passing STACK_IGNFAULTS). Even in this case we will | 48 | + TCGv_i32 control, fpscr; |
105 | + * still update the fault status registers. | 49 | + uint32_t bits = R_V7M_CONTROL_FPCA_MASK; |
106 | */ | 50 | + |
107 | - if (!ignfault) { | 51 | + fpscr = load_cpu_field(v7m.fpdscr[s->v8m_secure]); |
108 | + switch (mode) { | 52 | + gen_helper_vfp_set_fpscr(cpu_env, fpscr); |
109 | + case STACK_NORMAL: | 53 | + tcg_temp_free_i32(fpscr); |
110 | armv7m_nvic_set_pending_derived(env->nvic, exc, exc_secure); | 54 | + if (dc_isar_feature(aa32_mve, s)) { |
111 | + break; | 55 | + TCGv_i32 z32 = tcg_const_i32(0); |
112 | + case STACK_LAZYFP: | 56 | + store_cpu_field(z32, v7m.vpr); |
113 | + armv7m_nvic_set_pending_lazyfp(env->nvic, exc, exc_secure); | 57 | + } |
114 | + break; | 58 | + |
115 | + case STACK_IGNFAULTS: | 59 | + /* |
116 | + break; | 60 | + * We don't need to arrange to end the TB, because the only |
61 | + * parts of FPSCR which we cache in the TB flags are the VECLEN | ||
62 | + * and VECSTRIDE, and those don't exist for M-profile. | ||
63 | + */ | ||
64 | + | ||
65 | + if (s->v8m_secure) { | ||
66 | + bits |= R_V7M_CONTROL_SFPA_MASK; | ||
67 | + } | ||
68 | + control = load_cpu_field(v7m.control[M_REG_S]); | ||
69 | + tcg_gen_ori_i32(control, control, bits); | ||
70 | + store_cpu_field(control, v7m.control[M_REG_S]); | ||
71 | + /* Don't need to do this for any further FP insns in this TB */ | ||
72 | + s->v7m_new_fp_ctxt_needed = false; | ||
73 | + } | ||
74 | +} | ||
75 | + | ||
76 | /* | ||
77 | * Check that VFP access is enabled. If it is, do the necessary | ||
78 | * M-profile lazy-FP handling and then return true. | ||
79 | @@ -XXX,XX +XXX,XX @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled) | ||
80 | /* Trigger lazy-state preservation if necessary */ | ||
81 | gen_preserve_fp_state(s); | ||
82 | |||
83 | - /* Update ownership of FP context: set FPCCR.S to match current state */ | ||
84 | - if (s->v8m_fpccr_s_wrong) { | ||
85 | - TCGv_i32 tmp; | ||
86 | - | ||
87 | - tmp = load_cpu_field(v7m.fpccr[M_REG_S]); | ||
88 | - if (s->v8m_secure) { | ||
89 | - tcg_gen_ori_i32(tmp, tmp, R_V7M_FPCCR_S_MASK); | ||
90 | - } else { | ||
91 | - tcg_gen_andi_i32(tmp, tmp, ~R_V7M_FPCCR_S_MASK); | ||
92 | - } | ||
93 | - store_cpu_field(tmp, v7m.fpccr[M_REG_S]); | ||
94 | - /* Don't need to do this for any further FP insns in this TB */ | ||
95 | - s->v8m_fpccr_s_wrong = false; | ||
96 | - } | ||
97 | - | ||
98 | - if (s->v7m_new_fp_ctxt_needed) { | ||
99 | - /* | ||
100 | - * Create new FP context by updating CONTROL.FPCA, CONTROL.SFPA, | ||
101 | - * the FPSCR, and VPR. | ||
102 | - */ | ||
103 | - TCGv_i32 control, fpscr; | ||
104 | - uint32_t bits = R_V7M_CONTROL_FPCA_MASK; | ||
105 | - | ||
106 | - fpscr = load_cpu_field(v7m.fpdscr[s->v8m_secure]); | ||
107 | - gen_helper_vfp_set_fpscr(cpu_env, fpscr); | ||
108 | - tcg_temp_free_i32(fpscr); | ||
109 | - if (dc_isar_feature(aa32_mve, s)) { | ||
110 | - TCGv_i32 z32 = tcg_const_i32(0); | ||
111 | - store_cpu_field(z32, v7m.vpr); | ||
112 | - } | ||
113 | - | ||
114 | - /* | ||
115 | - * We don't need to arrange to end the TB, because the only | ||
116 | - * parts of FPSCR which we cache in the TB flags are the VECLEN | ||
117 | - * and VECSTRIDE, and those don't exist for M-profile. | ||
118 | - */ | ||
119 | - | ||
120 | - if (s->v8m_secure) { | ||
121 | - bits |= R_V7M_CONTROL_SFPA_MASK; | ||
122 | - } | ||
123 | - control = load_cpu_field(v7m.control[M_REG_S]); | ||
124 | - tcg_gen_ori_i32(control, control, bits); | ||
125 | - store_cpu_field(control, v7m.control[M_REG_S]); | ||
126 | - /* Don't need to do this for any further FP insns in this TB */ | ||
127 | - s->v7m_new_fp_ctxt_needed = false; | ||
128 | - } | ||
129 | + /* Update ownership of FP context and create new FP context if needed */ | ||
130 | + gen_update_fp_context(s); | ||
117 | } | 131 | } |
118 | return false; | 132 | |
119 | } | 133 | return true; |
120 | @@ -XXX,XX +XXX,XX @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain, | ||
121 | uint32_t limit; | ||
122 | bool want_psp; | ||
123 | uint32_t sig; | ||
124 | + StackingMode smode = ignore_faults ? STACK_IGNFAULTS : STACK_NORMAL; | ||
125 | |||
126 | if (dotailchain) { | ||
127 | bool mode = lr & R_V7M_EXCRET_MODE_MASK; | ||
128 | @@ -XXX,XX +XXX,XX @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain, | ||
129 | */ | ||
130 | sig = v7m_integrity_sig(env, lr); | ||
131 | stacked_ok = | ||
132 | - v7m_stack_write(cpu, frameptr, sig, mmu_idx, ignore_faults) && | ||
133 | - v7m_stack_write(cpu, frameptr + 0x8, env->regs[4], mmu_idx, | ||
134 | - ignore_faults) && | ||
135 | - v7m_stack_write(cpu, frameptr + 0xc, env->regs[5], mmu_idx, | ||
136 | - ignore_faults) && | ||
137 | - v7m_stack_write(cpu, frameptr + 0x10, env->regs[6], mmu_idx, | ||
138 | - ignore_faults) && | ||
139 | - v7m_stack_write(cpu, frameptr + 0x14, env->regs[7], mmu_idx, | ||
140 | - ignore_faults) && | ||
141 | - v7m_stack_write(cpu, frameptr + 0x18, env->regs[8], mmu_idx, | ||
142 | - ignore_faults) && | ||
143 | - v7m_stack_write(cpu, frameptr + 0x1c, env->regs[9], mmu_idx, | ||
144 | - ignore_faults) && | ||
145 | - v7m_stack_write(cpu, frameptr + 0x20, env->regs[10], mmu_idx, | ||
146 | - ignore_faults) && | ||
147 | - v7m_stack_write(cpu, frameptr + 0x24, env->regs[11], mmu_idx, | ||
148 | - ignore_faults); | ||
149 | + v7m_stack_write(cpu, frameptr, sig, mmu_idx, smode) && | ||
150 | + v7m_stack_write(cpu, frameptr + 0x8, env->regs[4], mmu_idx, smode) && | ||
151 | + v7m_stack_write(cpu, frameptr + 0xc, env->regs[5], mmu_idx, smode) && | ||
152 | + v7m_stack_write(cpu, frameptr + 0x10, env->regs[6], mmu_idx, smode) && | ||
153 | + v7m_stack_write(cpu, frameptr + 0x14, env->regs[7], mmu_idx, smode) && | ||
154 | + v7m_stack_write(cpu, frameptr + 0x18, env->regs[8], mmu_idx, smode) && | ||
155 | + v7m_stack_write(cpu, frameptr + 0x1c, env->regs[9], mmu_idx, smode) && | ||
156 | + v7m_stack_write(cpu, frameptr + 0x20, env->regs[10], mmu_idx, smode) && | ||
157 | + v7m_stack_write(cpu, frameptr + 0x24, env->regs[11], mmu_idx, smode); | ||
158 | |||
159 | /* Update SP regardless of whether any of the stack accesses failed. */ | ||
160 | *frame_sp_p = frameptr; | ||
161 | @@ -XXX,XX +XXX,XX @@ static bool v7m_push_stack(ARMCPU *cpu) | ||
162 | * if it has higher priority). | ||
163 | */ | ||
164 | stacked_ok = stacked_ok && | ||
165 | - v7m_stack_write(cpu, frameptr, env->regs[0], mmu_idx, false) && | ||
166 | - v7m_stack_write(cpu, frameptr + 4, env->regs[1], mmu_idx, false) && | ||
167 | - v7m_stack_write(cpu, frameptr + 8, env->regs[2], mmu_idx, false) && | ||
168 | - v7m_stack_write(cpu, frameptr + 12, env->regs[3], mmu_idx, false) && | ||
169 | - v7m_stack_write(cpu, frameptr + 16, env->regs[12], mmu_idx, false) && | ||
170 | - v7m_stack_write(cpu, frameptr + 20, env->regs[14], mmu_idx, false) && | ||
171 | - v7m_stack_write(cpu, frameptr + 24, env->regs[15], mmu_idx, false) && | ||
172 | - v7m_stack_write(cpu, frameptr + 28, xpsr, mmu_idx, false); | ||
173 | + v7m_stack_write(cpu, frameptr, env->regs[0], mmu_idx, STACK_NORMAL) && | ||
174 | + v7m_stack_write(cpu, frameptr + 4, env->regs[1], | ||
175 | + mmu_idx, STACK_NORMAL) && | ||
176 | + v7m_stack_write(cpu, frameptr + 8, env->regs[2], | ||
177 | + mmu_idx, STACK_NORMAL) && | ||
178 | + v7m_stack_write(cpu, frameptr + 12, env->regs[3], | ||
179 | + mmu_idx, STACK_NORMAL) && | ||
180 | + v7m_stack_write(cpu, frameptr + 16, env->regs[12], | ||
181 | + mmu_idx, STACK_NORMAL) && | ||
182 | + v7m_stack_write(cpu, frameptr + 20, env->regs[14], | ||
183 | + mmu_idx, STACK_NORMAL) && | ||
184 | + v7m_stack_write(cpu, frameptr + 24, env->regs[15], | ||
185 | + mmu_idx, STACK_NORMAL) && | ||
186 | + v7m_stack_write(cpu, frameptr + 28, xpsr, mmu_idx, STACK_NORMAL); | ||
187 | |||
188 | if (env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) { | ||
189 | /* FPU is active, try to save its registers */ | ||
190 | @@ -XXX,XX +XXX,XX @@ static bool v7m_push_stack(ARMCPU *cpu) | ||
191 | faddr += 8; /* skip the slot for the FPSCR */ | ||
192 | } | ||
193 | stacked_ok = stacked_ok && | ||
194 | - v7m_stack_write(cpu, faddr, slo, mmu_idx, false) && | ||
195 | - v7m_stack_write(cpu, faddr + 4, shi, mmu_idx, false); | ||
196 | + v7m_stack_write(cpu, faddr, slo, | ||
197 | + mmu_idx, STACK_NORMAL) && | ||
198 | + v7m_stack_write(cpu, faddr + 4, shi, | ||
199 | + mmu_idx, STACK_NORMAL); | ||
200 | } | ||
201 | stacked_ok = stacked_ok && | ||
202 | v7m_stack_write(cpu, frameptr + 0x60, | ||
203 | - vfp_get_fpscr(env), mmu_idx, false); | ||
204 | + vfp_get_fpscr(env), mmu_idx, STACK_NORMAL); | ||
205 | if (cpacr_pass) { | ||
206 | for (i = 0; i < ((framesize == 0xa8) ? 32 : 16); i += 2) { | ||
207 | *aa32_vfp_dreg(env, i / 2) = 0; | ||
208 | -- | 134 | -- |
209 | 2.20.1 | 135 | 2.20.1 |
210 | 136 | ||
211 | 137 | diff view generated by jsdifflib |
1 | The M-profile FPCCR.ASPEN bit indicates that automatic floating-point | 1 | vfp_access_check and its helper routine full_vfp_access_check() has |
---|---|---|---|
2 | context preservation is enabled. Before executing any floating-point | 2 | gradually grown and is now an awkward mix of A-profile only and |
3 | instruction, if FPCCR.ASPEN is set and the CONTROL FPCA/SFPA bits | 3 | M-profile only pieces. Refactor it into an A-profile only and an |
4 | indicate that there is no active floating point context then we | 4 | M-profile only version, taking advantage of the fact that now the |
5 | must create a new context (by initializing FPSCR and setting | 5 | only direct call to full_vfp_access_check() is in A-profile-only |
6 | FPCA/SFPA to indicate that the context is now active). In the | 6 | code. |
7 | pseudocode this is handled by ExecuteFPCheck(). | ||
8 | |||
9 | Implement this with a new TB flag which tracks whether we | ||
10 | need to create a new FP context. | ||
11 | 7 | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
14 | Message-id: 20190416125744.27770-20-peter.maydell@linaro.org | 10 | Message-id: 20210618141019.10671-7-peter.maydell@linaro.org |
15 | --- | 11 | --- |
16 | target/arm/cpu.h | 2 ++ | 12 | target/arm/translate-vfp.c | 79 +++++++++++++++++++++++--------------- |
17 | target/arm/translate.h | 1 + | 13 | 1 file changed, 48 insertions(+), 31 deletions(-) |
18 | target/arm/helper.c | 13 +++++++++++++ | ||
19 | target/arm/translate.c | 29 +++++++++++++++++++++++++++++ | ||
20 | 4 files changed, 45 insertions(+) | ||
21 | 14 | ||
22 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 15 | diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c |
23 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
24 | --- a/target/arm/cpu.h | 17 | --- a/target/arm/translate-vfp.c |
25 | +++ b/target/arm/cpu.h | 18 | +++ b/target/arm/translate-vfp.c |
26 | @@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A32, NS, 6, 1) | 19 | @@ -XXX,XX +XXX,XX @@ static void gen_update_fp_context(DisasContext *s) |
27 | FIELD(TBFLAG_A32, VFPEN, 7, 1) | 20 | } |
28 | FIELD(TBFLAG_A32, CONDEXEC, 8, 8) | 21 | |
29 | FIELD(TBFLAG_A32, SCTLR_B, 16, 1) | 22 | /* |
30 | +/* For M profile only, set if we must create a new FP context */ | 23 | - * Check that VFP access is enabled. If it is, do the necessary |
31 | +FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1) | 24 | - * M-profile lazy-FP handling and then return true. |
32 | /* For M profile only, set if FPCCR.S does not match current security state */ | 25 | - * If not, emit code to generate an appropriate exception and |
33 | FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) | 26 | - * return false. |
34 | /* For M profile only, Handler (ie not Thread) mode */ | 27 | + * Check that VFP access is enabled, A-profile specific version. |
35 | diff --git a/target/arm/translate.h b/target/arm/translate.h | 28 | + * |
36 | index XXXXXXX..XXXXXXX 100644 | 29 | + * If VFP is enabled, return true. If not, emit code to generate an |
37 | --- a/target/arm/translate.h | 30 | + * appropriate exception and return false. |
38 | +++ b/target/arm/translate.h | 31 | * The ignore_vfp_enabled argument specifies that we should ignore |
39 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { | 32 | - * whether VFP is enabled via FPEXC[EN]: this should be true for FMXR/FMRX |
40 | bool v8m_secure; /* true if v8M and we're in Secure mode */ | 33 | + * whether VFP is enabled via FPEXC.EN: this should be true for FMXR/FMRX |
41 | bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */ | 34 | * accesses to FPSID, FPEXC, MVFR0, MVFR1, MVFR2, and false for all other insns. |
42 | bool v8m_fpccr_s_wrong; /* true if v8M FPCCR.S != v8m_secure */ | 35 | */ |
43 | + bool v7m_new_fp_ctxt_needed; /* ASPEN set but no active FP context */ | 36 | -static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled) |
44 | /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI | 37 | +static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled) |
45 | * so that top level loop can generate correct syndrome information. | 38 | { |
46 | */ | 39 | if (s->fp_excp_el) { |
47 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 40 | - if (arm_dc_feature(s, ARM_FEATURE_M)) { |
48 | index XXXXXXX..XXXXXXX 100644 | 41 | - /* |
49 | --- a/target/arm/helper.c | 42 | - * M-profile mostly catches the "FPU disabled" case early, in |
50 | +++ b/target/arm/helper.c | 43 | - * disas_m_nocp(), but a few insns (eg LCTP, WLSTP, DLSTP) |
51 | @@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, | 44 | - * which do coprocessor-checks are outside the large ranges of |
52 | flags = FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1); | 45 | - * the encoding space handled by the patterns in m-nocp.decode, |
46 | - * and for them we may need to raise NOCP here. | ||
47 | - */ | ||
48 | - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
49 | - syn_uncategorized(), s->fp_excp_el); | ||
50 | - } else { | ||
51 | - gen_exception_insn(s, s->pc_curr, EXCP_UDEF, | ||
52 | - syn_fp_access_trap(1, 0xe, false), | ||
53 | - s->fp_excp_el); | ||
54 | - } | ||
55 | + gen_exception_insn(s, s->pc_curr, EXCP_UDEF, | ||
56 | + syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); | ||
57 | return false; | ||
53 | } | 58 | } |
54 | 59 | ||
55 | + if (arm_feature(env, ARM_FEATURE_M) && | 60 | @@ -XXX,XX +XXX,XX @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled) |
56 | + (env->v7m.fpccr[env->v7m.secure] & R_V7M_FPCCR_ASPEN_MASK) && | 61 | unallocated_encoding(s); |
57 | + (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) || | 62 | return false; |
58 | + (env->v7m.secure && | 63 | } |
59 | + !(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)))) { | 64 | + return true; |
65 | +} | ||
66 | |||
67 | - if (arm_dc_feature(s, ARM_FEATURE_M)) { | ||
68 | - /* Handle M-profile lazy FP state mechanics */ | ||
69 | - | ||
70 | - /* Trigger lazy-state preservation if necessary */ | ||
71 | - gen_preserve_fp_state(s); | ||
72 | - | ||
73 | - /* Update ownership of FP context and create new FP context if needed */ | ||
74 | - gen_update_fp_context(s); | ||
75 | +/* | ||
76 | + * Check that VFP access is enabled, M-profile specific version. | ||
77 | + * | ||
78 | + * If VFP is enabled, do the necessary M-profile lazy-FP handling and then | ||
79 | + * return true. If not, emit code to generate an appropriate exception and | ||
80 | + * return false. | ||
81 | + */ | ||
82 | +static bool vfp_access_check_m(DisasContext *s) | ||
83 | +{ | ||
84 | + if (s->fp_excp_el) { | ||
60 | + /* | 85 | + /* |
61 | + * ASPEN is set, but FPCA/SFPA indicate that there is no active | 86 | + * M-profile mostly catches the "FPU disabled" case early, in |
62 | + * FP context; we must create a new FP context before executing | 87 | + * disas_m_nocp(), but a few insns (eg LCTP, WLSTP, DLSTP) |
63 | + * any FP insn. | 88 | + * which do coprocessor-checks are outside the large ranges of |
89 | + * the encoding space handled by the patterns in m-nocp.decode, | ||
90 | + * and for them we may need to raise NOCP here. | ||
64 | + */ | 91 | + */ |
65 | + flags = FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED, 1); | 92 | + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, |
93 | + syn_uncategorized(), s->fp_excp_el); | ||
94 | + return false; | ||
95 | } | ||
96 | |||
97 | + /* Handle M-profile lazy FP state mechanics */ | ||
98 | + | ||
99 | + /* Trigger lazy-state preservation if necessary */ | ||
100 | + gen_preserve_fp_state(s); | ||
101 | + | ||
102 | + /* Update ownership of FP context and create new FP context if needed */ | ||
103 | + gen_update_fp_context(s); | ||
104 | + | ||
105 | return true; | ||
106 | } | ||
107 | |||
108 | @@ -XXX,XX +XXX,XX @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled) | ||
109 | */ | ||
110 | bool vfp_access_check(DisasContext *s) | ||
111 | { | ||
112 | - return full_vfp_access_check(s, false); | ||
113 | + if (arm_dc_feature(s, ARM_FEATURE_M)) { | ||
114 | + return vfp_access_check_m(s); | ||
115 | + } else { | ||
116 | + return vfp_access_check_a(s, false); | ||
66 | + } | 117 | + } |
67 | + | ||
68 | *pflags = flags; | ||
69 | *cs_base = 0; | ||
70 | } | 118 | } |
71 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 119 | |
72 | index XXXXXXX..XXXXXXX 100644 | 120 | static bool trans_VSEL(DisasContext *s, arg_VSEL *a) |
73 | --- a/target/arm/translate.c | 121 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a) |
74 | +++ b/target/arm/translate.c | 122 | return false; |
75 | @@ -XXX,XX +XXX,XX @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) | ||
76 | /* Don't need to do this for any further FP insns in this TB */ | ||
77 | s->v8m_fpccr_s_wrong = false; | ||
78 | } | ||
79 | + | ||
80 | + if (s->v7m_new_fp_ctxt_needed) { | ||
81 | + /* | ||
82 | + * Create new FP context by updating CONTROL.FPCA, CONTROL.SFPA | ||
83 | + * and the FPSCR. | ||
84 | + */ | ||
85 | + TCGv_i32 control, fpscr; | ||
86 | + uint32_t bits = R_V7M_CONTROL_FPCA_MASK; | ||
87 | + | ||
88 | + fpscr = load_cpu_field(v7m.fpdscr[s->v8m_secure]); | ||
89 | + gen_helper_vfp_set_fpscr(cpu_env, fpscr); | ||
90 | + tcg_temp_free_i32(fpscr); | ||
91 | + /* | ||
92 | + * We don't need to arrange to end the TB, because the only | ||
93 | + * parts of FPSCR which we cache in the TB flags are the VECLEN | ||
94 | + * and VECSTRIDE, and those don't exist for M-profile. | ||
95 | + */ | ||
96 | + | ||
97 | + if (s->v8m_secure) { | ||
98 | + bits |= R_V7M_CONTROL_SFPA_MASK; | ||
99 | + } | ||
100 | + control = load_cpu_field(v7m.control[M_REG_S]); | ||
101 | + tcg_gen_ori_i32(control, control, bits); | ||
102 | + store_cpu_field(control, v7m.control[M_REG_S]); | ||
103 | + /* Don't need to do this for any further FP insns in this TB */ | ||
104 | + s->v7m_new_fp_ctxt_needed = false; | ||
105 | + } | ||
106 | } | 123 | } |
107 | 124 | ||
108 | if (extract32(insn, 28, 4) == 0xf) { | 125 | - if (!full_vfp_access_check(s, ignore_vfp_enabled)) { |
109 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) | 126 | + /* |
110 | regime_is_secure(env, dc->mmu_idx); | 127 | + * Call vfp_access_check_a() directly, because we need to tell |
111 | dc->v8m_stackcheck = FIELD_EX32(tb_flags, TBFLAG_A32, STACKCHECK); | 128 | + * it to ignore FPEXC.EN for some register accesses. |
112 | dc->v8m_fpccr_s_wrong = FIELD_EX32(tb_flags, TBFLAG_A32, FPCCR_S_WRONG); | 129 | + */ |
113 | + dc->v7m_new_fp_ctxt_needed = | 130 | + if (!vfp_access_check_a(s, ignore_vfp_enabled)) { |
114 | + FIELD_EX32(tb_flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED); | 131 | return true; |
115 | dc->cp_regs = cpu->cp_regs; | 132 | } |
116 | dc->features = env->features; | ||
117 | 133 | ||
118 | -- | 134 | -- |
119 | 2.20.1 | 135 | 2.20.1 |
120 | 136 | ||
121 | 137 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Instead of open-coding the "take NOCP exception if FPU disabled, | ||
2 | otherwise call gen_preserve_fp_state()" code in the accessors for | ||
3 | FPCXT_NS, add an argument to vfp_access_check_m() which tells it to | ||
4 | skip the gen_update_fp_context() call, so we can use it for the | ||
5 | FPCXT_NS case. | ||
1 | 6 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20210618141019.10671-8-peter.maydell@linaro.org | ||
10 | --- | ||
11 | target/arm/translate-a32.h | 2 +- | ||
12 | target/arm/translate-m-nocp.c | 10 ++-------- | ||
13 | target/arm/translate-vfp.c | 13 ++++++++----- | ||
14 | 3 files changed, 11 insertions(+), 14 deletions(-) | ||
15 | |||
16 | diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/arm/translate-a32.h | ||
19 | +++ b/target/arm/translate-a32.h | ||
20 | @@ -XXX,XX +XXX,XX @@ bool disas_neon_shared(DisasContext *s, uint32_t insn); | ||
21 | void load_reg_var(DisasContext *s, TCGv_i32 var, int reg); | ||
22 | void arm_gen_condlabel(DisasContext *s); | ||
23 | bool vfp_access_check(DisasContext *s); | ||
24 | -void gen_preserve_fp_state(DisasContext *s); | ||
25 | +bool vfp_access_check_m(DisasContext *s, bool skip_context_update); | ||
26 | void read_neon_element32(TCGv_i32 dest, int reg, int ele, MemOp memop); | ||
27 | void read_neon_element64(TCGv_i64 dest, int reg, int ele, MemOp memop); | ||
28 | void write_neon_element32(TCGv_i32 src, int reg, int ele, MemOp memop); | ||
29 | diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/target/arm/translate-m-nocp.c | ||
32 | +++ b/target/arm/translate-m-nocp.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, | ||
34 | * otherwise PreserveFPState(), and then FPCXT_NS writes | ||
35 | * behave the same as FPCXT_S writes. | ||
36 | */ | ||
37 | - if (s->fp_excp_el) { | ||
38 | - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
39 | - syn_uncategorized(), s->fp_excp_el); | ||
40 | + if (!vfp_access_check_m(s, true)) { | ||
41 | /* | ||
42 | * This was only a conditional exception, so override | ||
43 | * gen_exception_insn()'s default to DISAS_NORETURN | ||
44 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno, | ||
45 | s->base.is_jmp = DISAS_NEXT; | ||
46 | break; | ||
47 | } | ||
48 | - gen_preserve_fp_state(s); | ||
49 | } | ||
50 | /* fall through */ | ||
51 | case ARM_VFP_FPCXT_S: | ||
52 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, | ||
53 | * otherwise PreserveFPState(), and then FPCXT_NS | ||
54 | * reads the same as FPCXT_S. | ||
55 | */ | ||
56 | - if (s->fp_excp_el) { | ||
57 | - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, | ||
58 | - syn_uncategorized(), s->fp_excp_el); | ||
59 | + if (!vfp_access_check_m(s, true)) { | ||
60 | /* | ||
61 | * This was only a conditional exception, so override | ||
62 | * gen_exception_insn()'s default to DISAS_NORETURN | ||
63 | @@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno, | ||
64 | s->base.is_jmp = DISAS_NEXT; | ||
65 | break; | ||
66 | } | ||
67 | - gen_preserve_fp_state(s); | ||
68 | tmp = tcg_temp_new_i32(); | ||
69 | sfpa = tcg_temp_new_i32(); | ||
70 | fpscr = tcg_temp_new_i32(); | ||
71 | diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c | ||
72 | index XXXXXXX..XXXXXXX 100644 | ||
73 | --- a/target/arm/translate-vfp.c | ||
74 | +++ b/target/arm/translate-vfp.c | ||
75 | @@ -XXX,XX +XXX,XX @@ static inline long vfp_f16_offset(unsigned reg, bool top) | ||
76 | * Generate code for M-profile lazy FP state preservation if needed; | ||
77 | * this corresponds to the pseudocode PreserveFPState() function. | ||
78 | */ | ||
79 | -void gen_preserve_fp_state(DisasContext *s) | ||
80 | +static void gen_preserve_fp_state(DisasContext *s) | ||
81 | { | ||
82 | if (s->v7m_lspact) { | ||
83 | /* | ||
84 | @@ -XXX,XX +XXX,XX @@ static bool vfp_access_check_a(DisasContext *s, bool ignore_vfp_enabled) | ||
85 | * If VFP is enabled, do the necessary M-profile lazy-FP handling and then | ||
86 | * return true. If not, emit code to generate an appropriate exception and | ||
87 | * return false. | ||
88 | + * skip_context_update is true to skip the "update FP context" part of this. | ||
89 | */ | ||
90 | -static bool vfp_access_check_m(DisasContext *s) | ||
91 | +bool vfp_access_check_m(DisasContext *s, bool skip_context_update) | ||
92 | { | ||
93 | if (s->fp_excp_el) { | ||
94 | /* | ||
95 | @@ -XXX,XX +XXX,XX @@ static bool vfp_access_check_m(DisasContext *s) | ||
96 | /* Trigger lazy-state preservation if necessary */ | ||
97 | gen_preserve_fp_state(s); | ||
98 | |||
99 | - /* Update ownership of FP context and create new FP context if needed */ | ||
100 | - gen_update_fp_context(s); | ||
101 | + if (!skip_context_update) { | ||
102 | + /* Update ownership of FP context and create new FP context if needed */ | ||
103 | + gen_update_fp_context(s); | ||
104 | + } | ||
105 | |||
106 | return true; | ||
107 | } | ||
108 | @@ -XXX,XX +XXX,XX @@ static bool vfp_access_check_m(DisasContext *s) | ||
109 | bool vfp_access_check(DisasContext *s) | ||
110 | { | ||
111 | if (arm_dc_feature(s, ARM_FEATURE_M)) { | ||
112 | - return vfp_access_check_m(s); | ||
113 | + return vfp_access_check_m(s, false); | ||
114 | } else { | ||
115 | return vfp_access_check_a(s, false); | ||
116 | } | ||
117 | -- | ||
118 | 2.20.1 | ||
119 | |||
120 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | 1 | Implement the forms of the MVE VLDR and VSTR insns which perform |
---|---|---|---|
2 | non-widening loads of bytes, halfwords or words from memory into | ||
3 | vector elements of the same width (encodings T5, T6, T7). | ||
2 | 4 | ||
3 | Since uWireSlave is only used in this new header, there is no | 5 | (At the moment we know for MVE and M-profile in general that |
4 | need to expose it via "qemu/typedefs.h". | 6 | vfp_access_check() can never return false, but we include the |
7 | conventional return-true-on-failure check for consistency | ||
8 | with non-M-profile translation code.) | ||
5 | 9 | ||
6 | Reviewed-by: Markus Armbruster <armbru@redhat.com> | ||
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
8 | Message-id: 20190412165416.7977-9-philmd@redhat.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20210617121628.20116-2-peter.maydell@linaro.org | ||
10 | --- | 13 | --- |
11 | include/hw/arm/omap.h | 6 +----- | 14 | target/arm/{translate-mve.c => helper-mve.h} | 19 +- |
12 | include/hw/devices.h | 15 --------------- | 15 | target/arm/helper.h | 2 + |
13 | include/hw/input/tsc2xxx.h | 36 ++++++++++++++++++++++++++++++++++++ | 16 | target/arm/internals.h | 11 ++ |
14 | include/qemu/typedefs.h | 1 - | 17 | target/arm/mve.decode | 22 +++ |
15 | hw/arm/nseries.c | 2 +- | 18 | target/arm/mve_helper.c | 172 +++++++++++++++++++ |
16 | hw/arm/palm.c | 2 +- | 19 | target/arm/translate-mve.c | 119 +++++++++++++ |
17 | hw/input/tsc2005.c | 2 +- | 20 | target/arm/meson.build | 1 + |
18 | hw/input/tsc210x.c | 4 ++-- | 21 | 7 files changed, 334 insertions(+), 12 deletions(-) |
19 | MAINTAINERS | 2 ++ | 22 | copy target/arm/{translate-mve.c => helper-mve.h} (61%) |
20 | 9 files changed, 44 insertions(+), 26 deletions(-) | 23 | create mode 100644 target/arm/mve_helper.c |
21 | create mode 100644 include/hw/input/tsc2xxx.h | ||
22 | 24 | ||
23 | diff --git a/include/hw/arm/omap.h b/include/hw/arm/omap.h | 25 | diff --git a/target/arm/translate-mve.c b/target/arm/helper-mve.h |
24 | index XXXXXXX..XXXXXXX 100644 | 26 | similarity index 61% |
25 | --- a/include/hw/arm/omap.h | 27 | copy from target/arm/translate-mve.c |
26 | +++ b/include/hw/arm/omap.h | 28 | copy to target/arm/helper-mve.h |
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/target/arm/translate-mve.c | ||
31 | +++ b/target/arm/helper-mve.h | ||
27 | @@ -XXX,XX +XXX,XX @@ | 32 | @@ -XXX,XX +XXX,XX @@ |
28 | #include "exec/memory.h" | 33 | /* |
29 | # define hw_omap_h "omap.h" | 34 | - * ARM translation: M-profile MVE instructions |
30 | #include "hw/irq.h" | 35 | + * M-profile MVE specific helper definitions |
31 | +#include "hw/input/tsc2xxx.h" | 36 | * |
32 | #include "target/arm/cpu-qom.h" | 37 | * Copyright (c) 2021 Linaro, Ltd. |
33 | #include "qemu/log.h" | 38 | * |
34 | |||
35 | @@ -XXX,XX +XXX,XX @@ qemu_irq *omap_mpuio_in_get(struct omap_mpuio_s *s); | ||
36 | void omap_mpuio_out_set(struct omap_mpuio_s *s, int line, qemu_irq handler); | ||
37 | void omap_mpuio_key(struct omap_mpuio_s *s, int row, int col, int down); | ||
38 | |||
39 | -struct uWireSlave { | ||
40 | - uint16_t (*receive)(void *opaque); | ||
41 | - void (*send)(void *opaque, uint16_t data); | ||
42 | - void *opaque; | ||
43 | -}; | ||
44 | struct omap_uwire_s; | ||
45 | void omap_uwire_attach(struct omap_uwire_s *s, | ||
46 | uWireSlave *slave, int chipselect); | ||
47 | diff --git a/include/hw/devices.h b/include/hw/devices.h | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/include/hw/devices.h | ||
50 | +++ b/include/hw/devices.h | ||
51 | @@ -XXX,XX +XXX,XX @@ | 39 | @@ -XXX,XX +XXX,XX @@ |
52 | /* Devices that have nowhere better to go. */ | 40 | * You should have received a copy of the GNU Lesser General Public |
53 | 41 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. | |
54 | #include "hw/hw.h" | 42 | */ |
55 | -#include "ui/console.h" | ||
56 | |||
57 | /* smc91c111.c */ | ||
58 | void smc91c111_init(NICInfo *, uint32_t, qemu_irq); | ||
59 | @@ -XXX,XX +XXX,XX @@ void smc91c111_init(NICInfo *, uint32_t, qemu_irq); | ||
60 | /* lan9118.c */ | ||
61 | void lan9118_init(NICInfo *, uint32_t, qemu_irq); | ||
62 | |||
63 | -/* tsc210x.c */ | ||
64 | -uWireSlave *tsc2102_init(qemu_irq pint); | ||
65 | -uWireSlave *tsc2301_init(qemu_irq penirq, qemu_irq kbirq, qemu_irq dav); | ||
66 | -I2SCodec *tsc210x_codec(uWireSlave *chip); | ||
67 | -uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len); | ||
68 | -void tsc210x_set_transform(uWireSlave *chip, | ||
69 | - MouseTransformInfo *info); | ||
70 | -void tsc210x_key_event(uWireSlave *chip, int key, int down); | ||
71 | - | 43 | - |
72 | -/* tsc2005.c */ | 44 | -#include "qemu/osdep.h" |
73 | -void *tsc2005_init(qemu_irq pintdav); | 45 | -#include "tcg/tcg-op.h" |
74 | -uint32_t tsc2005_txrx(void *opaque, uint32_t value, int len); | 46 | -#include "tcg/tcg-op-gvec.h" |
75 | -void tsc2005_set_transform(void *opaque, MouseTransformInfo *info); | 47 | -#include "exec/exec-all.h" |
48 | -#include "exec/gen-icount.h" | ||
49 | -#include "translate.h" | ||
50 | -#include "translate-a32.h" | ||
76 | - | 51 | - |
52 | -/* Include the generated decoder */ | ||
53 | -#include "decode-mve.c.inc" | ||
54 | +DEF_HELPER_FLAGS_3(mve_vldrb, TCG_CALL_NO_WG, void, env, ptr, i32) | ||
55 | +DEF_HELPER_FLAGS_3(mve_vldrh, TCG_CALL_NO_WG, void, env, ptr, i32) | ||
56 | +DEF_HELPER_FLAGS_3(mve_vldrw, TCG_CALL_NO_WG, void, env, ptr, i32) | ||
57 | +DEF_HELPER_FLAGS_3(mve_vstrb, TCG_CALL_NO_WG, void, env, ptr, i32) | ||
58 | +DEF_HELPER_FLAGS_3(mve_vstrh, TCG_CALL_NO_WG, void, env, ptr, i32) | ||
59 | +DEF_HELPER_FLAGS_3(mve_vstrw, TCG_CALL_NO_WG, void, env, ptr, i32) | ||
60 | diff --git a/target/arm/helper.h b/target/arm/helper.h | ||
61 | index XXXXXXX..XXXXXXX 100644 | ||
62 | --- a/target/arm/helper.h | ||
63 | +++ b/target/arm/helper.h | ||
64 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_6(gvec_bfmlal_idx, TCG_CALL_NO_RWG, | ||
65 | #include "helper-a64.h" | ||
66 | #include "helper-sve.h" | ||
77 | #endif | 67 | #endif |
78 | diff --git a/include/hw/input/tsc2xxx.h b/include/hw/input/tsc2xxx.h | 68 | + |
69 | +#include "helper-mve.h" | ||
70 | diff --git a/target/arm/internals.h b/target/arm/internals.h | ||
71 | index XXXXXXX..XXXXXXX 100644 | ||
72 | --- a/target/arm/internals.h | ||
73 | +++ b/target/arm/internals.h | ||
74 | @@ -XXX,XX +XXX,XX @@ static inline uint64_t useronly_maybe_clean_ptr(uint32_t desc, uint64_t ptr) | ||
75 | return ptr; | ||
76 | } | ||
77 | |||
78 | +/* Values for M-profile PSR.ECI for MVE insns */ | ||
79 | +enum MVEECIState { | ||
80 | + ECI_NONE = 0, /* No completed beats */ | ||
81 | + ECI_A0 = 1, /* Completed: A0 */ | ||
82 | + ECI_A0A1 = 2, /* Completed: A0, A1 */ | ||
83 | + /* 3 is reserved */ | ||
84 | + ECI_A0A1A2 = 4, /* Completed: A0, A1, A2 */ | ||
85 | + ECI_A0A1A2B0 = 5, /* Completed: A0, A1, A2, B0 */ | ||
86 | + /* All other values reserved */ | ||
87 | +}; | ||
88 | + | ||
89 | #endif | ||
90 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
91 | index XXXXXXX..XXXXXXX 100644 | ||
92 | --- a/target/arm/mve.decode | ||
93 | +++ b/target/arm/mve.decode | ||
94 | @@ -XXX,XX +XXX,XX @@ | ||
95 | # | ||
96 | # This file is processed by scripts/decodetree.py | ||
97 | # | ||
98 | + | ||
99 | +%qd 22:1 13:3 | ||
100 | + | ||
101 | +&vldr_vstr rn qd imm p a w size l | ||
102 | + | ||
103 | +@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd | ||
104 | + | ||
105 | +# Vector loads and stores | ||
106 | + | ||
107 | +# Non-widening loads/stores (P=0 W=0 is 'related encoding') | ||
108 | +VLDR_VSTR 1110110 0 a:1 . 1 . .... ... 111100 ....... @vldr_vstr \ | ||
109 | + size=0 p=0 w=1 | ||
110 | +VLDR_VSTR 1110110 0 a:1 . 1 . .... ... 111101 ....... @vldr_vstr \ | ||
111 | + size=1 p=0 w=1 | ||
112 | +VLDR_VSTR 1110110 0 a:1 . 1 . .... ... 111110 ....... @vldr_vstr \ | ||
113 | + size=2 p=0 w=1 | ||
114 | +VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111100 ....... @vldr_vstr \ | ||
115 | + size=0 p=1 | ||
116 | +VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111101 ....... @vldr_vstr \ | ||
117 | + size=1 p=1 | ||
118 | +VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111110 ....... @vldr_vstr \ | ||
119 | + size=2 p=1 | ||
120 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
79 | new file mode 100644 | 121 | new file mode 100644 |
80 | index XXXXXXX..XXXXXXX | 122 | index XXXXXXX..XXXXXXX |
81 | --- /dev/null | 123 | --- /dev/null |
82 | +++ b/include/hw/input/tsc2xxx.h | 124 | +++ b/target/arm/mve_helper.c |
83 | @@ -XXX,XX +XXX,XX @@ | 125 | @@ -XXX,XX +XXX,XX @@ |
84 | +/* | 126 | +/* |
85 | + * TI touchscreen controller | 127 | + * M-profile MVE Operations |
86 | + * | 128 | + * |
87 | + * Copyright (c) 2006 Andrzej Zaborowski | 129 | + * Copyright (c) 2021 Linaro, Ltd. |
88 | + * Copyright (C) 2008 Nokia Corporation | ||
89 | + * | 130 | + * |
90 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | 131 | + * This library is free software; you can redistribute it and/or |
91 | + * See the COPYING file in the top-level directory. | 132 | + * modify it under the terms of the GNU Lesser General Public |
133 | + * License as published by the Free Software Foundation; either | ||
134 | + * version 2.1 of the License, or (at your option) any later version. | ||
135 | + * | ||
136 | + * This library is distributed in the hope that it will be useful, | ||
137 | + * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
138 | + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | ||
139 | + * Lesser General Public License for more details. | ||
140 | + * | ||
141 | + * You should have received a copy of the GNU Lesser General Public | ||
142 | + * License along with this library; if not, see <http://www.gnu.org/licenses/>. | ||
92 | + */ | 143 | + */ |
93 | + | 144 | + |
94 | +#ifndef HW_INPUT_TSC2XXX_H | 145 | +#include "qemu/osdep.h" |
95 | +#define HW_INPUT_TSC2XXX_H | 146 | +#include "cpu.h" |
96 | + | 147 | +#include "internals.h" |
97 | +#include "hw/irq.h" | 148 | +#include "vec_internal.h" |
98 | +#include "ui/console.h" | 149 | +#include "exec/helper-proto.h" |
99 | + | 150 | +#include "exec/cpu_ldst.h" |
100 | +typedef struct uWireSlave { | 151 | +#include "exec/exec-all.h" |
101 | + uint16_t (*receive)(void *opaque); | 152 | + |
102 | + void (*send)(void *opaque, uint16_t data); | 153 | +static uint16_t mve_element_mask(CPUARMState *env) |
103 | + void *opaque; | 154 | +{ |
104 | +} uWireSlave; | 155 | + /* |
105 | + | 156 | + * Return the mask of which elements in the MVE vector should be |
106 | +/* tsc210x.c */ | 157 | + * updated. This is a combination of multiple things: |
107 | +uWireSlave *tsc2102_init(qemu_irq pint); | 158 | + * (1) by default, we update every lane in the vector |
108 | +uWireSlave *tsc2301_init(qemu_irq penirq, qemu_irq kbirq, qemu_irq dav); | 159 | + * (2) VPT predication stores its state in the VPR register; |
109 | +I2SCodec *tsc210x_codec(uWireSlave *chip); | 160 | + * (3) low-overhead-branch tail predication will mask out part |
110 | +uint32_t tsc210x_txrx(void *opaque, uint32_t value, int len); | 161 | + * the vector on the final iteration of the loop |
111 | +void tsc210x_set_transform(uWireSlave *chip, MouseTransformInfo *info); | 162 | + * (4) if EPSR.ECI is set then we must execute only some beats |
112 | +void tsc210x_key_event(uWireSlave *chip, int key, int down); | 163 | + * of the insn |
113 | + | 164 | + * We combine all these into a 16-bit result with the same semantics |
114 | +/* tsc2005.c */ | 165 | + * as VPR.P0: 0 to mask the lane, 1 if it is active. |
115 | +void *tsc2005_init(qemu_irq pintdav); | 166 | + * 8-bit vector ops will look at all bits of the result; |
116 | +uint32_t tsc2005_txrx(void *opaque, uint32_t value, int len); | 167 | + * 16-bit ops will look at bits 0, 2, 4, ...; |
117 | +void tsc2005_set_transform(void *opaque, MouseTransformInfo *info); | 168 | + * 32-bit ops will look at bits 0, 4, 8 and 12. |
118 | + | 169 | + * Compare pseudocode GetCurInstrBeat(), though that only returns |
119 | +#endif | 170 | + * the 4-bit slice of the mask corresponding to a single beat. |
120 | diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h | 171 | + */ |
121 | index XXXXXXX..XXXXXXX 100644 | 172 | + uint16_t mask = FIELD_EX32(env->v7m.vpr, V7M_VPR, P0); |
122 | --- a/include/qemu/typedefs.h | 173 | + |
123 | +++ b/include/qemu/typedefs.h | 174 | + if (!(env->v7m.vpr & R_V7M_VPR_MASK01_MASK)) { |
124 | @@ -XXX,XX +XXX,XX @@ typedef struct RAMBlock RAMBlock; | 175 | + mask |= 0xff; |
125 | typedef struct Range Range; | 176 | + } |
126 | typedef struct SHPCDevice SHPCDevice; | 177 | + if (!(env->v7m.vpr & R_V7M_VPR_MASK23_MASK)) { |
127 | typedef struct SSIBus SSIBus; | 178 | + mask |= 0xff00; |
128 | -typedef struct uWireSlave uWireSlave; | 179 | + } |
129 | typedef struct VirtIODevice VirtIODevice; | 180 | + |
130 | typedef struct Visitor Visitor; | 181 | + if (env->v7m.ltpsize < 4 && |
131 | typedef void SaveStateHandler(QEMUFile *f, void *opaque); | 182 | + env->regs[14] <= (1 << (4 - env->v7m.ltpsize))) { |
132 | diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c | 183 | + /* |
133 | index XXXXXXX..XXXXXXX 100644 | 184 | + * Tail predication active, and this is the last loop iteration. |
134 | --- a/hw/arm/nseries.c | 185 | + * The element size is (1 << ltpsize), and we only want to process |
135 | +++ b/hw/arm/nseries.c | 186 | + * loopcount elements, so we want to retain the least significant |
187 | + * (loopcount * esize) predicate bits and zero out bits above that. | ||
188 | + */ | ||
189 | + int masklen = env->regs[14] << env->v7m.ltpsize; | ||
190 | + assert(masklen <= 16); | ||
191 | + mask &= MAKE_64BIT_MASK(0, masklen); | ||
192 | + } | ||
193 | + | ||
194 | + if ((env->condexec_bits & 0xf) == 0) { | ||
195 | + /* | ||
196 | + * ECI bits indicate which beats are already executed; | ||
197 | + * we handle this by effectively predicating them out. | ||
198 | + */ | ||
199 | + int eci = env->condexec_bits >> 4; | ||
200 | + switch (eci) { | ||
201 | + case ECI_NONE: | ||
202 | + break; | ||
203 | + case ECI_A0: | ||
204 | + mask &= 0xfff0; | ||
205 | + break; | ||
206 | + case ECI_A0A1: | ||
207 | + mask &= 0xff00; | ||
208 | + break; | ||
209 | + case ECI_A0A1A2: | ||
210 | + case ECI_A0A1A2B0: | ||
211 | + mask &= 0xf000; | ||
212 | + break; | ||
213 | + default: | ||
214 | + g_assert_not_reached(); | ||
215 | + } | ||
216 | + } | ||
217 | + | ||
218 | + return mask; | ||
219 | +} | ||
220 | + | ||
221 | +static void mve_advance_vpt(CPUARMState *env) | ||
222 | +{ | ||
223 | + /* Advance the VPT and ECI state if necessary */ | ||
224 | + uint32_t vpr = env->v7m.vpr; | ||
225 | + unsigned mask01, mask23; | ||
226 | + | ||
227 | + if ((env->condexec_bits & 0xf) == 0) { | ||
228 | + env->condexec_bits = (env->condexec_bits == (ECI_A0A1A2B0 << 4)) ? | ||
229 | + (ECI_A0 << 4) : (ECI_NONE << 4); | ||
230 | + } | ||
231 | + | ||
232 | + if (!(vpr & (R_V7M_VPR_MASK01_MASK | R_V7M_VPR_MASK23_MASK))) { | ||
233 | + /* VPT not enabled, nothing to do */ | ||
234 | + return; | ||
235 | + } | ||
236 | + | ||
237 | + mask01 = FIELD_EX32(vpr, V7M_VPR, MASK01); | ||
238 | + mask23 = FIELD_EX32(vpr, V7M_VPR, MASK23); | ||
239 | + if (mask01 > 8) { | ||
240 | + /* high bit set, but not 0b1000: invert the relevant half of P0 */ | ||
241 | + vpr ^= 0xff; | ||
242 | + } | ||
243 | + if (mask23 > 8) { | ||
244 | + /* high bit set, but not 0b1000: invert the relevant half of P0 */ | ||
245 | + vpr ^= 0xff00; | ||
246 | + } | ||
247 | + vpr = FIELD_DP32(vpr, V7M_VPR, MASK01, mask01 << 1); | ||
248 | + vpr = FIELD_DP32(vpr, V7M_VPR, MASK23, mask23 << 1); | ||
249 | + env->v7m.vpr = vpr; | ||
250 | +} | ||
251 | + | ||
252 | + | ||
253 | +#define DO_VLDR(OP, MSIZE, LDTYPE, ESIZE, TYPE) \ | ||
254 | + void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ | ||
255 | + { \ | ||
256 | + TYPE *d = vd; \ | ||
257 | + uint16_t mask = mve_element_mask(env); \ | ||
258 | + unsigned b, e; \ | ||
259 | + /* \ | ||
260 | + * R_SXTM allows the dest reg to become UNKNOWN for abandoned \ | ||
261 | + * beats so we don't care if we update part of the dest and \ | ||
262 | + * then take an exception. \ | ||
263 | + */ \ | ||
264 | + for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \ | ||
265 | + if (mask & (1 << b)) { \ | ||
266 | + d[H##ESIZE(e)] = cpu_##LDTYPE##_data_ra(env, addr, GETPC()); \ | ||
267 | + } \ | ||
268 | + addr += MSIZE; \ | ||
269 | + } \ | ||
270 | + mve_advance_vpt(env); \ | ||
271 | + } | ||
272 | + | ||
273 | +#define DO_VSTR(OP, MSIZE, STTYPE, ESIZE, TYPE) \ | ||
274 | + void HELPER(mve_##OP)(CPUARMState *env, void *vd, uint32_t addr) \ | ||
275 | + { \ | ||
276 | + TYPE *d = vd; \ | ||
277 | + uint16_t mask = mve_element_mask(env); \ | ||
278 | + unsigned b, e; \ | ||
279 | + for (b = 0, e = 0; b < 16; b += ESIZE, e++) { \ | ||
280 | + if (mask & (1 << b)) { \ | ||
281 | + cpu_##STTYPE##_data_ra(env, addr, d[H##ESIZE(e)], GETPC()); \ | ||
282 | + } \ | ||
283 | + addr += MSIZE; \ | ||
284 | + } \ | ||
285 | + mve_advance_vpt(env); \ | ||
286 | + } | ||
287 | + | ||
288 | +DO_VLDR(vldrb, 1, ldub, 1, uint8_t) | ||
289 | +DO_VLDR(vldrh, 2, lduw, 2, uint16_t) | ||
290 | +DO_VLDR(vldrw, 4, ldl, 4, uint32_t) | ||
291 | + | ||
292 | +DO_VSTR(vstrb, 1, stb, 1, uint8_t) | ||
293 | +DO_VSTR(vstrh, 2, stw, 2, uint16_t) | ||
294 | +DO_VSTR(vstrw, 4, stl, 4, uint32_t) | ||
295 | + | ||
296 | +#undef DO_VLDR | ||
297 | +#undef DO_VSTR | ||
298 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
299 | index XXXXXXX..XXXXXXX 100644 | ||
300 | --- a/target/arm/translate-mve.c | ||
301 | +++ b/target/arm/translate-mve.c | ||
136 | @@ -XXX,XX +XXX,XX @@ | 302 | @@ -XXX,XX +XXX,XX @@ |
137 | #include "ui/console.h" | 303 | |
138 | #include "hw/boards.h" | 304 | /* Include the generated decoder */ |
139 | #include "hw/i2c/i2c.h" | 305 | #include "decode-mve.c.inc" |
140 | -#include "hw/devices.h" | 306 | + |
141 | #include "hw/display/blizzard.h" | 307 | +typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32); |
142 | +#include "hw/input/tsc2xxx.h" | 308 | + |
143 | #include "hw/misc/cbus.h" | 309 | +/* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */ |
144 | #include "hw/misc/tmp105.h" | 310 | +static inline long mve_qreg_offset(unsigned reg) |
145 | #include "hw/block/flash.h" | 311 | +{ |
146 | diff --git a/hw/arm/palm.c b/hw/arm/palm.c | 312 | + return offsetof(CPUARMState, vfp.zregs[reg].d[0]); |
147 | index XXXXXXX..XXXXXXX 100644 | 313 | +} |
148 | --- a/hw/arm/palm.c | 314 | + |
149 | +++ b/hw/arm/palm.c | 315 | +static TCGv_ptr mve_qreg_ptr(unsigned reg) |
150 | @@ -XXX,XX +XXX,XX @@ | 316 | +{ |
151 | #include "hw/arm/omap.h" | 317 | + TCGv_ptr ret = tcg_temp_new_ptr(); |
152 | #include "hw/boards.h" | 318 | + tcg_gen_addi_ptr(ret, cpu_env, mve_qreg_offset(reg)); |
153 | #include "hw/arm/arm.h" | 319 | + return ret; |
154 | -#include "hw/devices.h" | 320 | +} |
155 | +#include "hw/input/tsc2xxx.h" | 321 | + |
156 | #include "hw/loader.h" | 322 | +static bool mve_check_qreg_bank(DisasContext *s, int qmask) |
157 | #include "exec/address-spaces.h" | 323 | +{ |
158 | #include "cpu.h" | 324 | + /* |
159 | diff --git a/hw/input/tsc2005.c b/hw/input/tsc2005.c | 325 | + * Check whether Qregs are in range. For v8.1M only Q0..Q7 |
160 | index XXXXXXX..XXXXXXX 100644 | 326 | + * are supported, see VFPSmallRegisterBank(). |
161 | --- a/hw/input/tsc2005.c | 327 | + */ |
162 | +++ b/hw/input/tsc2005.c | 328 | + return qmask < 8; |
163 | @@ -XXX,XX +XXX,XX @@ | 329 | +} |
164 | #include "hw/hw.h" | 330 | + |
165 | #include "qemu/timer.h" | 331 | +static bool mve_eci_check(DisasContext *s) |
166 | #include "ui/console.h" | 332 | +{ |
167 | -#include "hw/devices.h" | 333 | + /* |
168 | +#include "hw/input/tsc2xxx.h" | 334 | + * This is a beatwise insn: check that ECI is valid (not a |
169 | #include "trace.h" | 335 | + * reserved value) and note that we are handling it. |
170 | 336 | + * Return true if OK, false if we generated an exception. | |
171 | #define TSC_CUT_RESOLUTION(value, p) ((value) >> (16 - (p ? 12 : 10))) | 337 | + */ |
172 | diff --git a/hw/input/tsc210x.c b/hw/input/tsc210x.c | 338 | + s->eci_handled = true; |
173 | index XXXXXXX..XXXXXXX 100644 | 339 | + switch (s->eci) { |
174 | --- a/hw/input/tsc210x.c | 340 | + case ECI_NONE: |
175 | +++ b/hw/input/tsc210x.c | 341 | + case ECI_A0: |
176 | @@ -XXX,XX +XXX,XX @@ | 342 | + case ECI_A0A1: |
177 | #include "audio/audio.h" | 343 | + case ECI_A0A1A2: |
178 | #include "qemu/timer.h" | 344 | + case ECI_A0A1A2B0: |
179 | #include "ui/console.h" | 345 | + return true; |
180 | -#include "hw/arm/omap.h" /* For I2SCodec and uWireSlave */ | 346 | + default: |
181 | -#include "hw/devices.h" | 347 | + /* Reserved value: INVSTATE UsageFault */ |
182 | +#include "hw/arm/omap.h" /* For I2SCodec */ | 348 | + gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(), |
183 | +#include "hw/input/tsc2xxx.h" | 349 | + default_exception_el(s)); |
184 | 350 | + return false; | |
185 | #define TSC_DATA_REGISTERS_PAGE 0x0 | 351 | + } |
186 | #define TSC_CONTROL_REGISTERS_PAGE 0x1 | 352 | +} |
187 | diff --git a/MAINTAINERS b/MAINTAINERS | 353 | + |
188 | index XXXXXXX..XXXXXXX 100644 | 354 | +static void mve_update_eci(DisasContext *s) |
189 | --- a/MAINTAINERS | 355 | +{ |
190 | +++ b/MAINTAINERS | 356 | + /* |
191 | @@ -XXX,XX +XXX,XX @@ F: hw/input/tsc2005.c | 357 | + * The helper function will always update the CPUState field, |
192 | F: hw/misc/cbus.c | 358 | + * so we only need to update the DisasContext field. |
193 | F: hw/timer/twl92230.c | 359 | + */ |
194 | F: include/hw/display/blizzard.h | 360 | + if (s->eci) { |
195 | +F: include/hw/input/tsc2xxx.h | 361 | + s->eci = (s->eci == ECI_A0A1A2B0) ? ECI_A0 : ECI_NONE; |
196 | F: include/hw/misc/cbus.h | 362 | + } |
197 | 363 | +} | |
198 | Palm | 364 | + |
199 | @@ -XXX,XX +XXX,XX @@ L: qemu-arm@nongnu.org | 365 | +static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn) |
200 | S: Odd Fixes | 366 | +{ |
201 | F: hw/arm/palm.c | 367 | + TCGv_i32 addr; |
202 | F: hw/input/tsc210x.c | 368 | + uint32_t offset; |
203 | +F: include/hw/input/tsc2xxx.h | 369 | + TCGv_ptr qreg; |
204 | 370 | + | |
205 | Raspberry Pi | 371 | + if (!dc_isar_feature(aa32_mve, s) || |
206 | M: Peter Maydell <peter.maydell@linaro.org> | 372 | + !mve_check_qreg_bank(s, a->qd) || |
373 | + !fn) { | ||
374 | + return false; | ||
375 | + } | ||
376 | + | ||
377 | + /* CONSTRAINED UNPREDICTABLE: we choose to UNDEF */ | ||
378 | + if (a->rn == 15 || (a->rn == 13 && a->w)) { | ||
379 | + return false; | ||
380 | + } | ||
381 | + | ||
382 | + if (!mve_eci_check(s) || !vfp_access_check(s)) { | ||
383 | + return true; | ||
384 | + } | ||
385 | + | ||
386 | + offset = a->imm << a->size; | ||
387 | + if (!a->a) { | ||
388 | + offset = -offset; | ||
389 | + } | ||
390 | + addr = load_reg(s, a->rn); | ||
391 | + if (a->p) { | ||
392 | + tcg_gen_addi_i32(addr, addr, offset); | ||
393 | + } | ||
394 | + | ||
395 | + qreg = mve_qreg_ptr(a->qd); | ||
396 | + fn(cpu_env, qreg, addr); | ||
397 | + tcg_temp_free_ptr(qreg); | ||
398 | + | ||
399 | + /* | ||
400 | + * Writeback always happens after the last beat of the insn, | ||
401 | + * regardless of predication | ||
402 | + */ | ||
403 | + if (a->w) { | ||
404 | + if (!a->p) { | ||
405 | + tcg_gen_addi_i32(addr, addr, offset); | ||
406 | + } | ||
407 | + store_reg(s, a->rn, addr); | ||
408 | + } else { | ||
409 | + tcg_temp_free_i32(addr); | ||
410 | + } | ||
411 | + mve_update_eci(s); | ||
412 | + return true; | ||
413 | +} | ||
414 | + | ||
415 | +static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a) | ||
416 | +{ | ||
417 | + static MVEGenLdStFn * const ldstfns[4][2] = { | ||
418 | + { gen_helper_mve_vstrb, gen_helper_mve_vldrb }, | ||
419 | + { gen_helper_mve_vstrh, gen_helper_mve_vldrh }, | ||
420 | + { gen_helper_mve_vstrw, gen_helper_mve_vldrw }, | ||
421 | + { NULL, NULL } | ||
422 | + }; | ||
423 | + return do_ldst(s, a, ldstfns[a->size][a->l]); | ||
424 | +} | ||
425 | diff --git a/target/arm/meson.build b/target/arm/meson.build | ||
426 | index XXXXXXX..XXXXXXX 100644 | ||
427 | --- a/target/arm/meson.build | ||
428 | +++ b/target/arm/meson.build | ||
429 | @@ -XXX,XX +XXX,XX @@ arm_ss.add(files( | ||
430 | 'helper.c', | ||
431 | 'iwmmxt_helper.c', | ||
432 | 'm_helper.c', | ||
433 | + 'mve_helper.c', | ||
434 | 'neon_helper.c', | ||
435 | 'op_helper.c', | ||
436 | 'tlb_helper.c', | ||
207 | -- | 437 | -- |
208 | 2.20.1 | 438 | 2.20.1 |
209 | 439 | ||
210 | 440 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Implement the variants of MVE VLDR (encodings T1, T2) which perform | ||
2 | "widening" loads where bytes or halfwords are loaded from memory and | ||
3 | zero or sign-extended into halfword or word length vector elements, | ||
4 | and the narrowing MVE VSTR (encodings T1, T2) where bytes or | ||
5 | halfwords are stored from halfword or word elements. | ||
1 | 6 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20210617121628.20116-3-peter.maydell@linaro.org | ||
10 | --- | ||
11 | target/arm/helper-mve.h | 10 ++++++++++ | ||
12 | target/arm/mve.decode | 25 +++++++++++++++++++++++-- | ||
13 | target/arm/mve_helper.c | 11 +++++++++++ | ||
14 | target/arm/translate-mve.c | 14 ++++++++++++++ | ||
15 | 4 files changed, 58 insertions(+), 2 deletions(-) | ||
16 | |||
17 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/target/arm/helper-mve.h | ||
20 | +++ b/target/arm/helper-mve.h | ||
21 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vldrw, TCG_CALL_NO_WG, void, env, ptr, i32) | ||
22 | DEF_HELPER_FLAGS_3(mve_vstrb, TCG_CALL_NO_WG, void, env, ptr, i32) | ||
23 | DEF_HELPER_FLAGS_3(mve_vstrh, TCG_CALL_NO_WG, void, env, ptr, i32) | ||
24 | DEF_HELPER_FLAGS_3(mve_vstrw, TCG_CALL_NO_WG, void, env, ptr, i32) | ||
25 | + | ||
26 | +DEF_HELPER_FLAGS_3(mve_vldrb_sh, TCG_CALL_NO_WG, void, env, ptr, i32) | ||
27 | +DEF_HELPER_FLAGS_3(mve_vldrb_sw, TCG_CALL_NO_WG, void, env, ptr, i32) | ||
28 | +DEF_HELPER_FLAGS_3(mve_vldrb_uh, TCG_CALL_NO_WG, void, env, ptr, i32) | ||
29 | +DEF_HELPER_FLAGS_3(mve_vldrb_uw, TCG_CALL_NO_WG, void, env, ptr, i32) | ||
30 | +DEF_HELPER_FLAGS_3(mve_vldrh_sw, TCG_CALL_NO_WG, void, env, ptr, i32) | ||
31 | +DEF_HELPER_FLAGS_3(mve_vldrh_uw, TCG_CALL_NO_WG, void, env, ptr, i32) | ||
32 | +DEF_HELPER_FLAGS_3(mve_vstrb_h, TCG_CALL_NO_WG, void, env, ptr, i32) | ||
33 | +DEF_HELPER_FLAGS_3(mve_vstrb_w, TCG_CALL_NO_WG, void, env, ptr, i32) | ||
34 | +DEF_HELPER_FLAGS_3(mve_vstrh_w, TCG_CALL_NO_WG, void, env, ptr, i32) | ||
35 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/target/arm/mve.decode | ||
38 | +++ b/target/arm/mve.decode | ||
39 | @@ -XXX,XX +XXX,XX @@ | ||
40 | |||
41 | %qd 22:1 13:3 | ||
42 | |||
43 | -&vldr_vstr rn qd imm p a w size l | ||
44 | +&vldr_vstr rn qd imm p a w size l u | ||
45 | |||
46 | -@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd | ||
47 | +@vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0 | ||
48 | +# Note that both Rn and Qd are 3 bits only (no D bit) | ||
49 | +@vldst_wn ... u:1 ... . . . . l:1 . rn:3 qd:3 . ... .. imm:7 &vldr_vstr | ||
50 | |||
51 | # Vector loads and stores | ||
52 | |||
53 | +# Widening loads and narrowing stores: | ||
54 | +# for these P=0 W=0 is 'related encoding'; sz=11 is 'related encoding' | ||
55 | +# This means we need to expand out to multiple patterns for P, W, SZ. | ||
56 | +# For stores the U bit must be 0 but we catch that in the trans_ function. | ||
57 | +# The naming scheme here is "VLDSTB_H == in-memory byte load/store to/from | ||
58 | +# signed halfword element in register", etc. | ||
59 | +VLDSTB_H 111 . 110 0 a:1 0 1 . 0 ... ... 0 111 01 ....... @vldst_wn \ | ||
60 | + p=0 w=1 size=1 | ||
61 | +VLDSTB_H 111 . 110 1 a:1 0 w:1 . 0 ... ... 0 111 01 ....... @vldst_wn \ | ||
62 | + p=1 size=1 | ||
63 | +VLDSTB_W 111 . 110 0 a:1 0 1 . 0 ... ... 0 111 10 ....... @vldst_wn \ | ||
64 | + p=0 w=1 size=2 | ||
65 | +VLDSTB_W 111 . 110 1 a:1 0 w:1 . 0 ... ... 0 111 10 ....... @vldst_wn \ | ||
66 | + p=1 size=2 | ||
67 | +VLDSTH_W 111 . 110 0 a:1 0 1 . 1 ... ... 0 111 10 ....... @vldst_wn \ | ||
68 | + p=0 w=1 size=2 | ||
69 | +VLDSTH_W 111 . 110 1 a:1 0 w:1 . 1 ... ... 0 111 10 ....... @vldst_wn \ | ||
70 | + p=1 size=2 | ||
71 | + | ||
72 | # Non-widening loads/stores (P=0 W=0 is 'related encoding') | ||
73 | VLDR_VSTR 1110110 0 a:1 . 1 . .... ... 111100 ....... @vldr_vstr \ | ||
74 | size=0 p=0 w=1 | ||
75 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
76 | index XXXXXXX..XXXXXXX 100644 | ||
77 | --- a/target/arm/mve_helper.c | ||
78 | +++ b/target/arm/mve_helper.c | ||
79 | @@ -XXX,XX +XXX,XX @@ DO_VSTR(vstrb, 1, stb, 1, uint8_t) | ||
80 | DO_VSTR(vstrh, 2, stw, 2, uint16_t) | ||
81 | DO_VSTR(vstrw, 4, stl, 4, uint32_t) | ||
82 | |||
83 | +DO_VLDR(vldrb_sh, 1, ldsb, 2, int16_t) | ||
84 | +DO_VLDR(vldrb_sw, 1, ldsb, 4, int32_t) | ||
85 | +DO_VLDR(vldrb_uh, 1, ldub, 2, uint16_t) | ||
86 | +DO_VLDR(vldrb_uw, 1, ldub, 4, uint32_t) | ||
87 | +DO_VLDR(vldrh_sw, 2, ldsw, 4, int32_t) | ||
88 | +DO_VLDR(vldrh_uw, 2, lduw, 4, uint32_t) | ||
89 | + | ||
90 | +DO_VSTR(vstrb_h, 1, stb, 2, int16_t) | ||
91 | +DO_VSTR(vstrb_w, 1, stb, 4, int32_t) | ||
92 | +DO_VSTR(vstrh_w, 2, stw, 4, int32_t) | ||
93 | + | ||
94 | #undef DO_VLDR | ||
95 | #undef DO_VSTR | ||
96 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
97 | index XXXXXXX..XXXXXXX 100644 | ||
98 | --- a/target/arm/translate-mve.c | ||
99 | +++ b/target/arm/translate-mve.c | ||
100 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a) | ||
101 | }; | ||
102 | return do_ldst(s, a, ldstfns[a->size][a->l]); | ||
103 | } | ||
104 | + | ||
105 | +#define DO_VLDST_WIDE_NARROW(OP, SLD, ULD, ST) \ | ||
106 | + static bool trans_##OP(DisasContext *s, arg_VLDR_VSTR *a) \ | ||
107 | + { \ | ||
108 | + static MVEGenLdStFn * const ldstfns[2][2] = { \ | ||
109 | + { gen_helper_mve_##ST, gen_helper_mve_##SLD }, \ | ||
110 | + { NULL, gen_helper_mve_##ULD }, \ | ||
111 | + }; \ | ||
112 | + return do_ldst(s, a, ldstfns[a->u][a->l]); \ | ||
113 | + } | ||
114 | + | ||
115 | +DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h) | ||
116 | +DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w) | ||
117 | +DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w) | ||
118 | -- | ||
119 | 2.20.1 | ||
120 | |||
121 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | 1 | Implement the MVE VCLZ insn (and the necessary machinery |
---|---|---|---|
2 | 2 | for MVE 1-input vector ops). | |
3 | Reviewed-by: Thomas Huth <thuth@redhat.com> | 3 | |
4 | Reviewed-by: Markus Armbruster <armbru@redhat.com> | 4 | Note that for non-load instructions predication is always performed |
5 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 5 | at a byte level granularity regardless of element size (R_ZLSJ), |
6 | Message-id: 20190412165416.7977-7-philmd@redhat.com | 6 | and so the masking logic here differs from that used in the VLDR |
7 | and VSTR helpers. | ||
8 | |||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20210617121628.20116-4-peter.maydell@linaro.org | ||
8 | --- | 12 | --- |
9 | include/hw/devices.h | 14 -------------- | 13 | target/arm/helper-mve.h | 4 ++ |
10 | include/hw/misc/cbus.h | 32 ++++++++++++++++++++++++++++++++ | 14 | target/arm/mve.decode | 8 ++++ |
11 | hw/arm/nseries.c | 1 + | 15 | target/arm/mve_helper.c | 82 ++++++++++++++++++++++++++++++++++++++ |
12 | hw/misc/cbus.c | 2 +- | 16 | target/arm/translate-mve.c | 38 ++++++++++++++++++ |
13 | MAINTAINERS | 1 + | 17 | 4 files changed, 132 insertions(+) |
14 | 5 files changed, 35 insertions(+), 15 deletions(-) | 18 | |
15 | create mode 100644 include/hw/misc/cbus.h | 19 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
16 | 20 | index XXXXXXX..XXXXXXX 100644 | |
17 | diff --git a/include/hw/devices.h b/include/hw/devices.h | 21 | --- a/target/arm/helper-mve.h |
18 | index XXXXXXX..XXXXXXX 100644 | 22 | +++ b/target/arm/helper-mve.h |
19 | --- a/include/hw/devices.h | 23 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vldrh_uw, TCG_CALL_NO_WG, void, env, ptr, i32) |
20 | +++ b/include/hw/devices.h | 24 | DEF_HELPER_FLAGS_3(mve_vstrb_h, TCG_CALL_NO_WG, void, env, ptr, i32) |
21 | @@ -XXX,XX +XXX,XX @@ void tsc2005_set_transform(void *opaque, MouseTransformInfo *info); | 25 | DEF_HELPER_FLAGS_3(mve_vstrb_w, TCG_CALL_NO_WG, void, env, ptr, i32) |
22 | /* stellaris_input.c */ | 26 | DEF_HELPER_FLAGS_3(mve_vstrh_w, TCG_CALL_NO_WG, void, env, ptr, i32) |
23 | void stellaris_gamepad_init(int n, qemu_irq *irq, const int *keycode); | 27 | + |
24 | 28 | +DEF_HELPER_FLAGS_3(mve_vclzb, TCG_CALL_NO_WG, void, env, ptr, ptr) | |
25 | -/* cbus.c */ | 29 | +DEF_HELPER_FLAGS_3(mve_vclzh, TCG_CALL_NO_WG, void, env, ptr, ptr) |
26 | -typedef struct { | 30 | +DEF_HELPER_FLAGS_3(mve_vclzw, TCG_CALL_NO_WG, void, env, ptr, ptr) |
27 | - qemu_irq clk; | 31 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode |
28 | - qemu_irq dat; | 32 | index XXXXXXX..XXXXXXX 100644 |
29 | - qemu_irq sel; | 33 | --- a/target/arm/mve.decode |
30 | -} CBus; | 34 | +++ b/target/arm/mve.decode |
31 | -CBus *cbus_init(qemu_irq dat_out); | ||
32 | -void cbus_attach(CBus *bus, void *slave_opaque); | ||
33 | - | ||
34 | -void *retu_init(qemu_irq irq, int vilma); | ||
35 | -void *tahvo_init(qemu_irq irq, int betty); | ||
36 | - | ||
37 | -void retu_key_event(void *retu, int state); | ||
38 | - | ||
39 | #endif | ||
40 | diff --git a/include/hw/misc/cbus.h b/include/hw/misc/cbus.h | ||
41 | new file mode 100644 | ||
42 | index XXXXXXX..XXXXXXX | ||
43 | --- /dev/null | ||
44 | +++ b/include/hw/misc/cbus.h | ||
45 | @@ -XXX,XX +XXX,XX @@ | 35 | @@ -XXX,XX +XXX,XX @@ |
36 | # | ||
37 | |||
38 | %qd 22:1 13:3 | ||
39 | +%qm 5:1 1:3 | ||
40 | |||
41 | &vldr_vstr rn qd imm p a w size l u | ||
42 | +&1op qd qm size | ||
43 | |||
44 | @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0 | ||
45 | # Note that both Rn and Qd are 3 bits only (no D bit) | ||
46 | @vldst_wn ... u:1 ... . . . . l:1 . rn:3 qd:3 . ... .. imm:7 &vldr_vstr | ||
47 | |||
48 | +@1op .... .... .... size:2 .. .... .... .... .... &1op qd=%qd qm=%qm | ||
49 | + | ||
50 | # Vector loads and stores | ||
51 | |||
52 | # Widening loads and narrowing stores: | ||
53 | @@ -XXX,XX +XXX,XX @@ VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111101 ....... @vldr_vstr \ | ||
54 | size=1 p=1 | ||
55 | VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111110 ....... @vldr_vstr \ | ||
56 | size=2 p=1 | ||
57 | + | ||
58 | +# Vector miscellaneous | ||
59 | + | ||
60 | +VCLZ 1111 1111 1 . 11 .. 00 ... 0 0100 11 . 0 ... 0 @1op | ||
61 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
62 | index XXXXXXX..XXXXXXX 100644 | ||
63 | --- a/target/arm/mve_helper.c | ||
64 | +++ b/target/arm/mve_helper.c | ||
65 | @@ -XXX,XX +XXX,XX @@ DO_VSTR(vstrh_w, 2, stw, 4, int32_t) | ||
66 | |||
67 | #undef DO_VLDR | ||
68 | #undef DO_VSTR | ||
69 | + | ||
46 | +/* | 70 | +/* |
47 | + * CBUS three-pin bus and the Retu / Betty / Tahvo / Vilma / Avilma / | 71 | + * The mergemask(D, R, M) macro performs the operation "*D = R" but |
48 | + * Hinku / Vinku / Ahne / Pihi chips used in various Nokia platforms. | 72 | + * storing only the bytes which correspond to 1 bits in M, |
49 | + * Based on reverse-engineering of a linux driver. | 73 | + * leaving other bytes in *D unchanged. We use _Generic |
50 | + * | 74 | + * to select the correct implementation based on the type of D. |
51 | + * Copyright (C) 2008 Nokia Corporation | ||
52 | + * Written by Andrzej Zaborowski | ||
53 | + * | ||
54 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
55 | + * See the COPYING file in the top-level directory. | ||
56 | + */ | 75 | + */ |
57 | + | 76 | + |
58 | +#ifndef HW_MISC_CBUS_H | 77 | +static void mergemask_ub(uint8_t *d, uint8_t r, uint16_t mask) |
59 | +#define HW_MISC_CBUS_H | 78 | +{ |
60 | + | 79 | + if (mask & 1) { |
61 | +#include "hw/irq.h" | 80 | + *d = r; |
62 | + | 81 | + } |
63 | +typedef struct { | 82 | +} |
64 | + qemu_irq clk; | 83 | + |
65 | + qemu_irq dat; | 84 | +static void mergemask_sb(int8_t *d, int8_t r, uint16_t mask) |
66 | + qemu_irq sel; | 85 | +{ |
67 | +} CBus; | 86 | + mergemask_ub((uint8_t *)d, r, mask); |
68 | + | 87 | +} |
69 | +CBus *cbus_init(qemu_irq dat_out); | 88 | + |
70 | +void cbus_attach(CBus *bus, void *slave_opaque); | 89 | +static void mergemask_uh(uint16_t *d, uint16_t r, uint16_t mask) |
71 | + | 90 | +{ |
72 | +void *retu_init(qemu_irq irq, int vilma); | 91 | + uint16_t bmask = expand_pred_b_data[mask & 3]; |
73 | +void *tahvo_init(qemu_irq irq, int betty); | 92 | + *d = (*d & ~bmask) | (r & bmask); |
74 | + | 93 | +} |
75 | +void retu_key_event(void *retu, int state); | 94 | + |
76 | + | 95 | +static void mergemask_sh(int16_t *d, int16_t r, uint16_t mask) |
77 | +#endif | 96 | +{ |
78 | diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c | 97 | + mergemask_uh((uint16_t *)d, r, mask); |
79 | index XXXXXXX..XXXXXXX 100644 | 98 | +} |
80 | --- a/hw/arm/nseries.c | 99 | + |
81 | +++ b/hw/arm/nseries.c | 100 | +static void mergemask_uw(uint32_t *d, uint32_t r, uint16_t mask) |
101 | +{ | ||
102 | + uint32_t bmask = expand_pred_b_data[mask & 0xf]; | ||
103 | + *d = (*d & ~bmask) | (r & bmask); | ||
104 | +} | ||
105 | + | ||
106 | +static void mergemask_sw(int32_t *d, int32_t r, uint16_t mask) | ||
107 | +{ | ||
108 | + mergemask_uw((uint32_t *)d, r, mask); | ||
109 | +} | ||
110 | + | ||
111 | +static void mergemask_uq(uint64_t *d, uint64_t r, uint16_t mask) | ||
112 | +{ | ||
113 | + uint64_t bmask = expand_pred_b_data[mask & 0xff]; | ||
114 | + *d = (*d & ~bmask) | (r & bmask); | ||
115 | +} | ||
116 | + | ||
117 | +static void mergemask_sq(int64_t *d, int64_t r, uint16_t mask) | ||
118 | +{ | ||
119 | + mergemask_uq((uint64_t *)d, r, mask); | ||
120 | +} | ||
121 | + | ||
122 | +#define mergemask(D, R, M) \ | ||
123 | + _Generic(D, \ | ||
124 | + uint8_t *: mergemask_ub, \ | ||
125 | + int8_t *: mergemask_sb, \ | ||
126 | + uint16_t *: mergemask_uh, \ | ||
127 | + int16_t *: mergemask_sh, \ | ||
128 | + uint32_t *: mergemask_uw, \ | ||
129 | + int32_t *: mergemask_sw, \ | ||
130 | + uint64_t *: mergemask_uq, \ | ||
131 | + int64_t *: mergemask_sq)(D, R, M) | ||
132 | + | ||
133 | +#define DO_1OP(OP, ESIZE, TYPE, FN) \ | ||
134 | + void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ | ||
135 | + { \ | ||
136 | + TYPE *d = vd, *m = vm; \ | ||
137 | + uint16_t mask = mve_element_mask(env); \ | ||
138 | + unsigned e; \ | ||
139 | + for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ | ||
140 | + mergemask(&d[H##ESIZE(e)], FN(m[H##ESIZE(e)]), mask); \ | ||
141 | + } \ | ||
142 | + mve_advance_vpt(env); \ | ||
143 | + } | ||
144 | + | ||
145 | +#define DO_CLZ_B(N) (clz32(N) - 24) | ||
146 | +#define DO_CLZ_H(N) (clz32(N) - 16) | ||
147 | + | ||
148 | +DO_1OP(vclzb, 1, uint8_t, DO_CLZ_B) | ||
149 | +DO_1OP(vclzh, 2, uint16_t, DO_CLZ_H) | ||
150 | +DO_1OP(vclzw, 4, uint32_t, clz32) | ||
151 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
152 | index XXXXXXX..XXXXXXX 100644 | ||
153 | --- a/target/arm/translate-mve.c | ||
154 | +++ b/target/arm/translate-mve.c | ||
82 | @@ -XXX,XX +XXX,XX @@ | 155 | @@ -XXX,XX +XXX,XX @@ |
83 | #include "hw/i2c/i2c.h" | 156 | #include "decode-mve.c.inc" |
84 | #include "hw/devices.h" | 157 | |
85 | #include "hw/display/blizzard.h" | 158 | typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32); |
86 | +#include "hw/misc/cbus.h" | 159 | +typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); |
87 | #include "hw/misc/tmp105.h" | 160 | |
88 | #include "hw/block/flash.h" | 161 | /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */ |
89 | #include "hw/hw.h" | 162 | static inline long mve_qreg_offset(unsigned reg) |
90 | diff --git a/hw/misc/cbus.c b/hw/misc/cbus.c | 163 | @@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR(DisasContext *s, arg_VLDR_VSTR *a) |
91 | index XXXXXXX..XXXXXXX 100644 | 164 | DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h) |
92 | --- a/hw/misc/cbus.c | 165 | DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w) |
93 | +++ b/hw/misc/cbus.c | 166 | DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w) |
94 | @@ -XXX,XX +XXX,XX @@ | 167 | + |
95 | #include "qemu/osdep.h" | 168 | +static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn) |
96 | #include "hw/hw.h" | 169 | +{ |
97 | #include "hw/irq.h" | 170 | + TCGv_ptr qd, qm; |
98 | -#include "hw/devices.h" | 171 | + |
99 | +#include "hw/misc/cbus.h" | 172 | + if (!dc_isar_feature(aa32_mve, s) || |
100 | #include "sysemu/sysemu.h" | 173 | + !mve_check_qreg_bank(s, a->qd | a->qm) || |
101 | 174 | + !fn) { | |
102 | //#define DEBUG | 175 | + return false; |
103 | diff --git a/MAINTAINERS b/MAINTAINERS | 176 | + } |
104 | index XXXXXXX..XXXXXXX 100644 | 177 | + |
105 | --- a/MAINTAINERS | 178 | + if (!mve_eci_check(s) || !vfp_access_check(s)) { |
106 | +++ b/MAINTAINERS | 179 | + return true; |
107 | @@ -XXX,XX +XXX,XX @@ F: hw/input/tsc2005.c | 180 | + } |
108 | F: hw/misc/cbus.c | 181 | + |
109 | F: hw/timer/twl92230.c | 182 | + qd = mve_qreg_ptr(a->qd); |
110 | F: include/hw/display/blizzard.h | 183 | + qm = mve_qreg_ptr(a->qm); |
111 | +F: include/hw/misc/cbus.h | 184 | + fn(cpu_env, qd, qm); |
112 | 185 | + tcg_temp_free_ptr(qd); | |
113 | Palm | 186 | + tcg_temp_free_ptr(qm); |
114 | M: Andrzej Zaborowski <balrogg@gmail.com> | 187 | + mve_update_eci(s); |
188 | + return true; | ||
189 | +} | ||
190 | + | ||
191 | +#define DO_1OP(INSN, FN) \ | ||
192 | + static bool trans_##INSN(DisasContext *s, arg_1op *a) \ | ||
193 | + { \ | ||
194 | + static MVEGenOneOpFn * const fns[] = { \ | ||
195 | + gen_helper_mve_##FN##b, \ | ||
196 | + gen_helper_mve_##FN##h, \ | ||
197 | + gen_helper_mve_##FN##w, \ | ||
198 | + NULL, \ | ||
199 | + }; \ | ||
200 | + return do_1op(s, a, fns[a->size]); \ | ||
201 | + } | ||
202 | + | ||
203 | +DO_1OP(VCLZ, vclz) | ||
115 | -- | 204 | -- |
116 | 2.20.1 | 205 | 2.20.1 |
117 | 206 | ||
118 | 207 | diff view generated by jsdifflib |
1 | We are close to running out of TB flags for AArch32; we could | 1 | Implement the MVE VCLS insn. |
---|---|---|---|
2 | start using the cs_base word, but before we do that we can | ||
3 | economise on our usage by sharing the same bits for the VFP | ||
4 | VECSTRIDE field and the XScale XSCALE_CPAR field. This | ||
5 | works because no XScale CPU ever had VFP. | ||
6 | 2 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20190416125744.27770-18-peter.maydell@linaro.org | 5 | Message-id: 20210617121628.20116-5-peter.maydell@linaro.org |
10 | --- | 6 | --- |
11 | target/arm/cpu.h | 10 ++++++---- | 7 | target/arm/helper-mve.h | 4 ++++ |
12 | target/arm/cpu.c | 7 +++++++ | 8 | target/arm/mve.decode | 1 + |
13 | target/arm/helper.c | 6 +++++- | 9 | target/arm/mve_helper.c | 7 +++++++ |
14 | target/arm/translate.c | 9 +++++++-- | 10 | target/arm/translate-mve.c | 1 + |
15 | 4 files changed, 25 insertions(+), 7 deletions(-) | 11 | 4 files changed, 13 insertions(+) |
16 | 12 | ||
17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 13 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
18 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/cpu.h | 15 | --- a/target/arm/helper-mve.h |
20 | +++ b/target/arm/cpu.h | 16 | +++ b/target/arm/helper-mve.h |
21 | @@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_ANY, BE_DATA, 23, 1) | 17 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vstrb_h, TCG_CALL_NO_WG, void, env, ptr, i32) |
22 | FIELD(TBFLAG_A32, THUMB, 0, 1) | 18 | DEF_HELPER_FLAGS_3(mve_vstrb_w, TCG_CALL_NO_WG, void, env, ptr, i32) |
23 | FIELD(TBFLAG_A32, VECLEN, 1, 3) | 19 | DEF_HELPER_FLAGS_3(mve_vstrh_w, TCG_CALL_NO_WG, void, env, ptr, i32) |
24 | FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) | 20 | |
25 | +/* | 21 | +DEF_HELPER_FLAGS_3(mve_vclsb, TCG_CALL_NO_WG, void, env, ptr, ptr) |
26 | + * We store the bottom two bits of the CPAR as TB flags and handle | 22 | +DEF_HELPER_FLAGS_3(mve_vclsh, TCG_CALL_NO_WG, void, env, ptr, ptr) |
27 | + * checks on the other bits at runtime. This shares the same bits as | 23 | +DEF_HELPER_FLAGS_3(mve_vclsw, TCG_CALL_NO_WG, void, env, ptr, ptr) |
28 | + * VECSTRIDE, which is OK as no XScale CPU has VFP. | 24 | + |
29 | + */ | 25 | DEF_HELPER_FLAGS_3(mve_vclzb, TCG_CALL_NO_WG, void, env, ptr, ptr) |
30 | +FIELD(TBFLAG_A32, XSCALE_CPAR, 4, 2) | 26 | DEF_HELPER_FLAGS_3(mve_vclzh, TCG_CALL_NO_WG, void, env, ptr, ptr) |
31 | /* | 27 | DEF_HELPER_FLAGS_3(mve_vclzw, TCG_CALL_NO_WG, void, env, ptr, ptr) |
32 | * Indicates whether cp register reads and writes by guest code should access | 28 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode |
33 | * the secure or nonsecure bank of banked registers; note that this is not | ||
34 | @@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A32, NS, 6, 1) | ||
35 | FIELD(TBFLAG_A32, VFPEN, 7, 1) | ||
36 | FIELD(TBFLAG_A32, CONDEXEC, 8, 8) | ||
37 | FIELD(TBFLAG_A32, SCTLR_B, 16, 1) | ||
38 | -/* We store the bottom two bits of the CPAR as TB flags and handle | ||
39 | - * checks on the other bits at runtime | ||
40 | - */ | ||
41 | -FIELD(TBFLAG_A32, XSCALE_CPAR, 17, 2) | ||
42 | /* For M profile only, Handler (ie not Thread) mode */ | ||
43 | FIELD(TBFLAG_A32, HANDLER, 21, 1) | ||
44 | /* For M profile only, whether we should generate stack-limit checks */ | ||
45 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
46 | index XXXXXXX..XXXXXXX 100644 | 29 | index XXXXXXX..XXXXXXX 100644 |
47 | --- a/target/arm/cpu.c | 30 | --- a/target/arm/mve.decode |
48 | +++ b/target/arm/cpu.c | 31 | +++ b/target/arm/mve.decode |
49 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | 32 | @@ -XXX,XX +XXX,XX @@ VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111110 ....... @vldr_vstr \ |
50 | set_feature(env, ARM_FEATURE_THUMB_DSP); | 33 | |
34 | # Vector miscellaneous | ||
35 | |||
36 | +VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op | ||
37 | VCLZ 1111 1111 1 . 11 .. 00 ... 0 0100 11 . 0 ... 0 @1op | ||
38 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/target/arm/mve_helper.c | ||
41 | +++ b/target/arm/mve_helper.c | ||
42 | @@ -XXX,XX +XXX,XX @@ static void mergemask_sq(int64_t *d, int64_t r, uint16_t mask) | ||
43 | mve_advance_vpt(env); \ | ||
51 | } | 44 | } |
52 | 45 | ||
53 | + /* | 46 | +#define DO_CLS_B(N) (clrsb32(N) - 24) |
54 | + * We rely on no XScale CPU having VFP so we can use the same bits in the | 47 | +#define DO_CLS_H(N) (clrsb32(N) - 16) |
55 | + * TB flags field for VECSTRIDE and XSCALE_CPAR. | ||
56 | + */ | ||
57 | + assert(!(arm_feature(env, ARM_FEATURE_VFP) && | ||
58 | + arm_feature(env, ARM_FEATURE_XSCALE))); | ||
59 | + | 48 | + |
60 | if (arm_feature(env, ARM_FEATURE_V7) && | 49 | +DO_1OP(vclsb, 1, int8_t, DO_CLS_B) |
61 | !arm_feature(env, ARM_FEATURE_M) && | 50 | +DO_1OP(vclsh, 2, int16_t, DO_CLS_H) |
62 | !arm_feature(env, ARM_FEATURE_PMSA)) { | 51 | +DO_1OP(vclsw, 4, int32_t, clrsb32) |
63 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 52 | + |
53 | #define DO_CLZ_B(N) (clz32(N) - 24) | ||
54 | #define DO_CLZ_H(N) (clz32(N) - 16) | ||
55 | |||
56 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
64 | index XXXXXXX..XXXXXXX 100644 | 57 | index XXXXXXX..XXXXXXX 100644 |
65 | --- a/target/arm/helper.c | 58 | --- a/target/arm/translate-mve.c |
66 | +++ b/target/arm/helper.c | 59 | +++ b/target/arm/translate-mve.c |
67 | @@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, | 60 | @@ -XXX,XX +XXX,XX @@ static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn) |
68 | || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) { | ||
69 | flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); | ||
70 | } | ||
71 | - flags = FIELD_DP32(flags, TBFLAG_A32, XSCALE_CPAR, env->cp15.c15_cpar); | ||
72 | + /* Note that XSCALE_CPAR shares bits with VECSTRIDE */ | ||
73 | + if (arm_feature(env, ARM_FEATURE_XSCALE)) { | ||
74 | + flags = FIELD_DP32(flags, TBFLAG_A32, | ||
75 | + XSCALE_CPAR, env->cp15.c15_cpar); | ||
76 | + } | ||
77 | } | 61 | } |
78 | 62 | ||
79 | flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); | 63 | DO_1OP(VCLZ, vclz) |
80 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 64 | +DO_1OP(VCLS, vcls) |
81 | index XXXXXXX..XXXXXXX 100644 | ||
82 | --- a/target/arm/translate.c | ||
83 | +++ b/target/arm/translate.c | ||
84 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) | ||
85 | dc->fp_excp_el = FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL); | ||
86 | dc->vfp_enabled = FIELD_EX32(tb_flags, TBFLAG_A32, VFPEN); | ||
87 | dc->vec_len = FIELD_EX32(tb_flags, TBFLAG_A32, VECLEN); | ||
88 | - dc->vec_stride = FIELD_EX32(tb_flags, TBFLAG_A32, VECSTRIDE); | ||
89 | - dc->c15_cpar = FIELD_EX32(tb_flags, TBFLAG_A32, XSCALE_CPAR); | ||
90 | + if (arm_feature(env, ARM_FEATURE_XSCALE)) { | ||
91 | + dc->c15_cpar = FIELD_EX32(tb_flags, TBFLAG_A32, XSCALE_CPAR); | ||
92 | + dc->vec_stride = 0; | ||
93 | + } else { | ||
94 | + dc->vec_stride = FIELD_EX32(tb_flags, TBFLAG_A32, VECSTRIDE); | ||
95 | + dc->c15_cpar = 0; | ||
96 | + } | ||
97 | dc->v7m_handler_mode = FIELD_EX32(tb_flags, TBFLAG_A32, HANDLER); | ||
98 | dc->v8m_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) && | ||
99 | regime_is_secure(env, dc->mmu_idx); | ||
100 | -- | 65 | -- |
101 | 2.20.1 | 66 | 2.20.1 |
102 | 67 | ||
103 | 68 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Implement the MVE instructions VREV16, VREV32 and VREV64. | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20210617121628.20116-6-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/arm/helper-mve.h | 7 +++++++ | ||
8 | target/arm/mve.decode | 4 ++++ | ||
9 | target/arm/mve_helper.c | 7 +++++++ | ||
10 | target/arm/translate-mve.c | 33 +++++++++++++++++++++++++++++++++ | ||
11 | 4 files changed, 51 insertions(+) | ||
12 | |||
13 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/helper-mve.h | ||
16 | +++ b/target/arm/helper-mve.h | ||
17 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vclsw, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
18 | DEF_HELPER_FLAGS_3(mve_vclzb, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
19 | DEF_HELPER_FLAGS_3(mve_vclzh, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
20 | DEF_HELPER_FLAGS_3(mve_vclzw, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
21 | + | ||
22 | +DEF_HELPER_FLAGS_3(mve_vrev16b, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
23 | +DEF_HELPER_FLAGS_3(mve_vrev32b, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
24 | +DEF_HELPER_FLAGS_3(mve_vrev32h, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
25 | +DEF_HELPER_FLAGS_3(mve_vrev64b, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
26 | +DEF_HELPER_FLAGS_3(mve_vrev64h, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
27 | +DEF_HELPER_FLAGS_3(mve_vrev64w, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
28 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/target/arm/mve.decode | ||
31 | +++ b/target/arm/mve.decode | ||
32 | @@ -XXX,XX +XXX,XX @@ VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111110 ....... @vldr_vstr \ | ||
33 | |||
34 | VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op | ||
35 | VCLZ 1111 1111 1 . 11 .. 00 ... 0 0100 11 . 0 ... 0 @1op | ||
36 | + | ||
37 | +VREV16 1111 1111 1 . 11 .. 00 ... 0 0001 01 . 0 ... 0 @1op | ||
38 | +VREV32 1111 1111 1 . 11 .. 00 ... 0 0000 11 . 0 ... 0 @1op | ||
39 | +VREV64 1111 1111 1 . 11 .. 00 ... 0 0000 01 . 0 ... 0 @1op | ||
40 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/target/arm/mve_helper.c | ||
43 | +++ b/target/arm/mve_helper.c | ||
44 | @@ -XXX,XX +XXX,XX @@ DO_1OP(vclsw, 4, int32_t, clrsb32) | ||
45 | DO_1OP(vclzb, 1, uint8_t, DO_CLZ_B) | ||
46 | DO_1OP(vclzh, 2, uint16_t, DO_CLZ_H) | ||
47 | DO_1OP(vclzw, 4, uint32_t, clz32) | ||
48 | + | ||
49 | +DO_1OP(vrev16b, 2, uint16_t, bswap16) | ||
50 | +DO_1OP(vrev32b, 4, uint32_t, bswap32) | ||
51 | +DO_1OP(vrev32h, 4, uint32_t, hswap32) | ||
52 | +DO_1OP(vrev64b, 8, uint64_t, bswap64) | ||
53 | +DO_1OP(vrev64h, 8, uint64_t, hswap64) | ||
54 | +DO_1OP(vrev64w, 8, uint64_t, wswap64) | ||
55 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
56 | index XXXXXXX..XXXXXXX 100644 | ||
57 | --- a/target/arm/translate-mve.c | ||
58 | +++ b/target/arm/translate-mve.c | ||
59 | @@ -XXX,XX +XXX,XX @@ static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn) | ||
60 | |||
61 | DO_1OP(VCLZ, vclz) | ||
62 | DO_1OP(VCLS, vcls) | ||
63 | + | ||
64 | +static bool trans_VREV16(DisasContext *s, arg_1op *a) | ||
65 | +{ | ||
66 | + static MVEGenOneOpFn * const fns[] = { | ||
67 | + gen_helper_mve_vrev16b, | ||
68 | + NULL, | ||
69 | + NULL, | ||
70 | + NULL, | ||
71 | + }; | ||
72 | + return do_1op(s, a, fns[a->size]); | ||
73 | +} | ||
74 | + | ||
75 | +static bool trans_VREV32(DisasContext *s, arg_1op *a) | ||
76 | +{ | ||
77 | + static MVEGenOneOpFn * const fns[] = { | ||
78 | + gen_helper_mve_vrev32b, | ||
79 | + gen_helper_mve_vrev32h, | ||
80 | + NULL, | ||
81 | + NULL, | ||
82 | + }; | ||
83 | + return do_1op(s, a, fns[a->size]); | ||
84 | +} | ||
85 | + | ||
86 | +static bool trans_VREV64(DisasContext *s, arg_1op *a) | ||
87 | +{ | ||
88 | + static MVEGenOneOpFn * const fns[] = { | ||
89 | + gen_helper_mve_vrev64b, | ||
90 | + gen_helper_mve_vrev64h, | ||
91 | + gen_helper_mve_vrev64w, | ||
92 | + NULL, | ||
93 | + }; | ||
94 | + return do_1op(s, a, fns[a->size]); | ||
95 | +} | ||
96 | -- | ||
97 | 2.20.1 | ||
98 | |||
99 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Implement the MVE VMVN(register) operation. Note that for | ||
2 | predication this operation is byte-by-byte. | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20210617121628.20116-7-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/arm/helper-mve.h | 2 ++ | ||
9 | target/arm/mve.decode | 3 +++ | ||
10 | target/arm/mve_helper.c | 4 ++++ | ||
11 | target/arm/translate-mve.c | 5 +++++ | ||
12 | 4 files changed, 14 insertions(+) | ||
13 | |||
14 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/helper-mve.h | ||
17 | +++ b/target/arm/helper-mve.h | ||
18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vrev32h, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
19 | DEF_HELPER_FLAGS_3(mve_vrev64b, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
20 | DEF_HELPER_FLAGS_3(mve_vrev64h, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
21 | DEF_HELPER_FLAGS_3(mve_vrev64w, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
22 | + | ||
23 | +DEF_HELPER_FLAGS_3(mve_vmvn, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
24 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/target/arm/mve.decode | ||
27 | +++ b/target/arm/mve.decode | ||
28 | @@ -XXX,XX +XXX,XX @@ | ||
29 | @vldst_wn ... u:1 ... . . . . l:1 . rn:3 qd:3 . ... .. imm:7 &vldr_vstr | ||
30 | |||
31 | @1op .... .... .... size:2 .. .... .... .... .... &1op qd=%qd qm=%qm | ||
32 | +@1op_nosz .... .... .... .... .... .... .... .... &1op qd=%qd qm=%qm size=0 | ||
33 | |||
34 | # Vector loads and stores | ||
35 | |||
36 | @@ -XXX,XX +XXX,XX @@ VCLZ 1111 1111 1 . 11 .. 00 ... 0 0100 11 . 0 ... 0 @1op | ||
37 | VREV16 1111 1111 1 . 11 .. 00 ... 0 0001 01 . 0 ... 0 @1op | ||
38 | VREV32 1111 1111 1 . 11 .. 00 ... 0 0000 11 . 0 ... 0 @1op | ||
39 | VREV64 1111 1111 1 . 11 .. 00 ... 0 0000 01 . 0 ... 0 @1op | ||
40 | + | ||
41 | +VMVN 1111 1111 1 . 11 00 00 ... 0 0101 11 . 0 ... 0 @1op_nosz | ||
42 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/target/arm/mve_helper.c | ||
45 | +++ b/target/arm/mve_helper.c | ||
46 | @@ -XXX,XX +XXX,XX @@ DO_1OP(vrev32h, 4, uint32_t, hswap32) | ||
47 | DO_1OP(vrev64b, 8, uint64_t, bswap64) | ||
48 | DO_1OP(vrev64h, 8, uint64_t, hswap64) | ||
49 | DO_1OP(vrev64w, 8, uint64_t, wswap64) | ||
50 | + | ||
51 | +#define DO_NOT(N) (~(N)) | ||
52 | + | ||
53 | +DO_1OP(vmvn, 8, uint64_t, DO_NOT) | ||
54 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
55 | index XXXXXXX..XXXXXXX 100644 | ||
56 | --- a/target/arm/translate-mve.c | ||
57 | +++ b/target/arm/translate-mve.c | ||
58 | @@ -XXX,XX +XXX,XX @@ static bool trans_VREV64(DisasContext *s, arg_1op *a) | ||
59 | }; | ||
60 | return do_1op(s, a, fns[a->size]); | ||
61 | } | ||
62 | + | ||
63 | +static bool trans_VMVN(DisasContext *s, arg_1op *a) | ||
64 | +{ | ||
65 | + return do_1op(s, a, gen_helper_mve_vmvn); | ||
66 | +} | ||
67 | -- | ||
68 | 2.20.1 | ||
69 | |||
70 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Implement the MVE VABS functions (both integer and floating point). | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20210617121628.20116-8-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/arm/helper-mve.h | 6 ++++++ | ||
8 | target/arm/mve.decode | 3 +++ | ||
9 | target/arm/mve_helper.c | 13 +++++++++++++ | ||
10 | target/arm/translate-mve.c | 15 +++++++++++++++ | ||
11 | 4 files changed, 37 insertions(+) | ||
12 | |||
13 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/helper-mve.h | ||
16 | +++ b/target/arm/helper-mve.h | ||
17 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vrev64h, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
18 | DEF_HELPER_FLAGS_3(mve_vrev64w, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
19 | |||
20 | DEF_HELPER_FLAGS_3(mve_vmvn, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
21 | + | ||
22 | +DEF_HELPER_FLAGS_3(mve_vabsb, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
23 | +DEF_HELPER_FLAGS_3(mve_vabsh, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
24 | +DEF_HELPER_FLAGS_3(mve_vabsw, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
25 | +DEF_HELPER_FLAGS_3(mve_vfabsh, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
26 | +DEF_HELPER_FLAGS_3(mve_vfabss, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
27 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/target/arm/mve.decode | ||
30 | +++ b/target/arm/mve.decode | ||
31 | @@ -XXX,XX +XXX,XX @@ VREV32 1111 1111 1 . 11 .. 00 ... 0 0000 11 . 0 ... 0 @1op | ||
32 | VREV64 1111 1111 1 . 11 .. 00 ... 0 0000 01 . 0 ... 0 @1op | ||
33 | |||
34 | VMVN 1111 1111 1 . 11 00 00 ... 0 0101 11 . 0 ... 0 @1op_nosz | ||
35 | + | ||
36 | +VABS 1111 1111 1 . 11 .. 01 ... 0 0011 01 . 0 ... 0 @1op | ||
37 | +VABS_fp 1111 1111 1 . 11 .. 01 ... 0 0111 01 . 0 ... 0 @1op | ||
38 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/target/arm/mve_helper.c | ||
41 | +++ b/target/arm/mve_helper.c | ||
42 | @@ -XXX,XX +XXX,XX @@ | ||
43 | #include "exec/helper-proto.h" | ||
44 | #include "exec/cpu_ldst.h" | ||
45 | #include "exec/exec-all.h" | ||
46 | +#include "tcg/tcg.h" | ||
47 | |||
48 | static uint16_t mve_element_mask(CPUARMState *env) | ||
49 | { | ||
50 | @@ -XXX,XX +XXX,XX @@ DO_1OP(vrev64w, 8, uint64_t, wswap64) | ||
51 | #define DO_NOT(N) (~(N)) | ||
52 | |||
53 | DO_1OP(vmvn, 8, uint64_t, DO_NOT) | ||
54 | + | ||
55 | +#define DO_ABS(N) ((N) < 0 ? -(N) : (N)) | ||
56 | +#define DO_FABSH(N) ((N) & dup_const(MO_16, 0x7fff)) | ||
57 | +#define DO_FABSS(N) ((N) & dup_const(MO_32, 0x7fffffff)) | ||
58 | + | ||
59 | +DO_1OP(vabsb, 1, int8_t, DO_ABS) | ||
60 | +DO_1OP(vabsh, 2, int16_t, DO_ABS) | ||
61 | +DO_1OP(vabsw, 4, int32_t, DO_ABS) | ||
62 | + | ||
63 | +/* We can do these 64 bits at a time */ | ||
64 | +DO_1OP(vfabsh, 8, uint64_t, DO_FABSH) | ||
65 | +DO_1OP(vfabss, 8, uint64_t, DO_FABSS) | ||
66 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
67 | index XXXXXXX..XXXXXXX 100644 | ||
68 | --- a/target/arm/translate-mve.c | ||
69 | +++ b/target/arm/translate-mve.c | ||
70 | @@ -XXX,XX +XXX,XX @@ static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn) | ||
71 | |||
72 | DO_1OP(VCLZ, vclz) | ||
73 | DO_1OP(VCLS, vcls) | ||
74 | +DO_1OP(VABS, vabs) | ||
75 | |||
76 | static bool trans_VREV16(DisasContext *s, arg_1op *a) | ||
77 | { | ||
78 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMVN(DisasContext *s, arg_1op *a) | ||
79 | { | ||
80 | return do_1op(s, a, gen_helper_mve_vmvn); | ||
81 | } | ||
82 | + | ||
83 | +static bool trans_VABS_fp(DisasContext *s, arg_1op *a) | ||
84 | +{ | ||
85 | + static MVEGenOneOpFn * const fns[] = { | ||
86 | + NULL, | ||
87 | + gen_helper_mve_vfabsh, | ||
88 | + gen_helper_mve_vfabss, | ||
89 | + NULL, | ||
90 | + }; | ||
91 | + if (!dc_isar_feature(aa32_mve_fp, s)) { | ||
92 | + return false; | ||
93 | + } | ||
94 | + return do_1op(s, a, fns[a->size]); | ||
95 | +} | ||
96 | -- | ||
97 | 2.20.1 | ||
98 | |||
99 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Implement the MVE VNEG insn (both integer and floating point forms). | ||
1 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20210617121628.20116-9-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/arm/helper-mve.h | 6 ++++++ | ||
8 | target/arm/mve.decode | 2 ++ | ||
9 | target/arm/mve_helper.c | 12 ++++++++++++ | ||
10 | target/arm/translate-mve.c | 15 +++++++++++++++ | ||
11 | 4 files changed, 35 insertions(+) | ||
12 | |||
13 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/helper-mve.h | ||
16 | +++ b/target/arm/helper-mve.h | ||
17 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vabsh, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
18 | DEF_HELPER_FLAGS_3(mve_vabsw, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
19 | DEF_HELPER_FLAGS_3(mve_vfabsh, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
20 | DEF_HELPER_FLAGS_3(mve_vfabss, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
21 | + | ||
22 | +DEF_HELPER_FLAGS_3(mve_vnegb, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
23 | +DEF_HELPER_FLAGS_3(mve_vnegh, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
24 | +DEF_HELPER_FLAGS_3(mve_vnegw, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
25 | +DEF_HELPER_FLAGS_3(mve_vfnegh, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
26 | +DEF_HELPER_FLAGS_3(mve_vfnegs, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
27 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/target/arm/mve.decode | ||
30 | +++ b/target/arm/mve.decode | ||
31 | @@ -XXX,XX +XXX,XX @@ VMVN 1111 1111 1 . 11 00 00 ... 0 0101 11 . 0 ... 0 @1op_nosz | ||
32 | |||
33 | VABS 1111 1111 1 . 11 .. 01 ... 0 0011 01 . 0 ... 0 @1op | ||
34 | VABS_fp 1111 1111 1 . 11 .. 01 ... 0 0111 01 . 0 ... 0 @1op | ||
35 | +VNEG 1111 1111 1 . 11 .. 01 ... 0 0011 11 . 0 ... 0 @1op | ||
36 | +VNEG_fp 1111 1111 1 . 11 .. 01 ... 0 0111 11 . 0 ... 0 @1op | ||
37 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
38 | index XXXXXXX..XXXXXXX 100644 | ||
39 | --- a/target/arm/mve_helper.c | ||
40 | +++ b/target/arm/mve_helper.c | ||
41 | @@ -XXX,XX +XXX,XX @@ DO_1OP(vabsw, 4, int32_t, DO_ABS) | ||
42 | /* We can do these 64 bits at a time */ | ||
43 | DO_1OP(vfabsh, 8, uint64_t, DO_FABSH) | ||
44 | DO_1OP(vfabss, 8, uint64_t, DO_FABSS) | ||
45 | + | ||
46 | +#define DO_NEG(N) (-(N)) | ||
47 | +#define DO_FNEGH(N) ((N) ^ dup_const(MO_16, 0x8000)) | ||
48 | +#define DO_FNEGS(N) ((N) ^ dup_const(MO_32, 0x80000000)) | ||
49 | + | ||
50 | +DO_1OP(vnegb, 1, int8_t, DO_NEG) | ||
51 | +DO_1OP(vnegh, 2, int16_t, DO_NEG) | ||
52 | +DO_1OP(vnegw, 4, int32_t, DO_NEG) | ||
53 | + | ||
54 | +/* We can do these 64 bits at a time */ | ||
55 | +DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH) | ||
56 | +DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS) | ||
57 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
58 | index XXXXXXX..XXXXXXX 100644 | ||
59 | --- a/target/arm/translate-mve.c | ||
60 | +++ b/target/arm/translate-mve.c | ||
61 | @@ -XXX,XX +XXX,XX @@ static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn) | ||
62 | DO_1OP(VCLZ, vclz) | ||
63 | DO_1OP(VCLS, vcls) | ||
64 | DO_1OP(VABS, vabs) | ||
65 | +DO_1OP(VNEG, vneg) | ||
66 | |||
67 | static bool trans_VREV16(DisasContext *s, arg_1op *a) | ||
68 | { | ||
69 | @@ -XXX,XX +XXX,XX @@ static bool trans_VABS_fp(DisasContext *s, arg_1op *a) | ||
70 | } | ||
71 | return do_1op(s, a, fns[a->size]); | ||
72 | } | ||
73 | + | ||
74 | +static bool trans_VNEG_fp(DisasContext *s, arg_1op *a) | ||
75 | +{ | ||
76 | + static MVEGenOneOpFn * const fns[] = { | ||
77 | + NULL, | ||
78 | + gen_helper_mve_vfnegh, | ||
79 | + gen_helper_mve_vfnegs, | ||
80 | + NULL, | ||
81 | + }; | ||
82 | + if (!dc_isar_feature(aa32_mve_fp, s)) { | ||
83 | + return false; | ||
84 | + } | ||
85 | + return do_1op(s, a, fns[a->size]); | ||
86 | +} | ||
87 | -- | ||
88 | 2.20.1 | ||
89 | |||
90 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The Arm MVE VDUP implementation would like to be able to emit code to | ||
2 | duplicate a byte or halfword value into an i32. We have code to do | ||
3 | this already in tcg-op-gvec.c, so all we need to do is make the | ||
4 | functions global. | ||
1 | 5 | ||
6 | For consistency with other functions made available to the frontends: | ||
7 | * we rename to tcg_gen_dup_* | ||
8 | * we expose both the _i32 and _i64 forms | ||
9 | * we provide the #define for a _tl form | ||
10 | |||
11 | Suggested-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | Message-id: 20210617121628.20116-10-peter.maydell@linaro.org | ||
15 | --- | ||
16 | include/tcg/tcg-op.h | 8 ++++++++ | ||
17 | include/tcg/tcg.h | 1 - | ||
18 | tcg/tcg-op-gvec.c | 20 ++++++++++---------- | ||
19 | 3 files changed, 18 insertions(+), 11 deletions(-) | ||
20 | |||
21 | diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/include/tcg/tcg-op.h | ||
24 | +++ b/include/tcg/tcg-op.h | ||
25 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); | ||
26 | void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); | ||
27 | void tcg_gen_abs_i32(TCGv_i32, TCGv_i32); | ||
28 | |||
29 | +/* Replicate a value of size @vece from @in to all the lanes in @out */ | ||
30 | +void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in); | ||
31 | + | ||
32 | static inline void tcg_gen_discard_i32(TCGv_i32 arg) | ||
33 | { | ||
34 | tcg_gen_op1_i32(INDEX_op_discard, arg); | ||
35 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); | ||
36 | void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); | ||
37 | void tcg_gen_abs_i64(TCGv_i64, TCGv_i64); | ||
38 | |||
39 | +/* Replicate a value of size @vece from @in to all the lanes in @out */ | ||
40 | +void tcg_gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in); | ||
41 | + | ||
42 | #if TCG_TARGET_REG_BITS == 64 | ||
43 | static inline void tcg_gen_discard_i64(TCGv_i64 arg) | ||
44 | { | ||
45 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t); | ||
46 | #define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i64 | ||
47 | #define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i64 | ||
48 | #define tcg_gen_dup_tl_vec tcg_gen_dup_i64_vec | ||
49 | +#define tcg_gen_dup_tl tcg_gen_dup_i64 | ||
50 | #else | ||
51 | #define tcg_gen_movi_tl tcg_gen_movi_i32 | ||
52 | #define tcg_gen_mov_tl tcg_gen_mov_i32 | ||
53 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t); | ||
54 | #define tcg_gen_atomic_smax_fetch_tl tcg_gen_atomic_smax_fetch_i32 | ||
55 | #define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i32 | ||
56 | #define tcg_gen_dup_tl_vec tcg_gen_dup_i32_vec | ||
57 | +#define tcg_gen_dup_tl tcg_gen_dup_i32 | ||
58 | #endif | ||
59 | |||
60 | #if UINTPTR_MAX == UINT32_MAX | ||
61 | diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h | ||
62 | index XXXXXXX..XXXXXXX 100644 | ||
63 | --- a/include/tcg/tcg.h | ||
64 | +++ b/include/tcg/tcg.h | ||
65 | @@ -XXX,XX +XXX,XX @@ uint64_t dup_const(unsigned vece, uint64_t c); | ||
66 | : (qemu_build_not_reached_always(), 0)) \ | ||
67 | : dup_const(VECE, C)) | ||
68 | |||
69 | - | ||
70 | /* | ||
71 | * Memory helpers that will be used by TCG generated code. | ||
72 | */ | ||
73 | diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c | ||
74 | index XXXXXXX..XXXXXXX 100644 | ||
75 | --- a/tcg/tcg-op-gvec.c | ||
76 | +++ b/tcg/tcg-op-gvec.c | ||
77 | @@ -XXX,XX +XXX,XX @@ uint64_t (dup_const)(unsigned vece, uint64_t c) | ||
78 | } | ||
79 | |||
80 | /* Duplicate IN into OUT as per VECE. */ | ||
81 | -static void gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in) | ||
82 | +void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in) | ||
83 | { | ||
84 | switch (vece) { | ||
85 | case MO_8: | ||
86 | @@ -XXX,XX +XXX,XX @@ static void gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in) | ||
87 | } | ||
88 | } | ||
89 | |||
90 | -static void gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in) | ||
91 | +void tcg_gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in) | ||
92 | { | ||
93 | switch (vece) { | ||
94 | case MO_8: | ||
95 | @@ -XXX,XX +XXX,XX @@ static void do_dup(unsigned vece, uint32_t dofs, uint32_t oprsz, | ||
96 | && (vece != MO_32 || !check_size_impl(oprsz, 4))) { | ||
97 | t_64 = tcg_temp_new_i64(); | ||
98 | tcg_gen_extu_i32_i64(t_64, in_32); | ||
99 | - gen_dup_i64(vece, t_64, t_64); | ||
100 | + tcg_gen_dup_i64(vece, t_64, t_64); | ||
101 | } else { | ||
102 | t_32 = tcg_temp_new_i32(); | ||
103 | - gen_dup_i32(vece, t_32, in_32); | ||
104 | + tcg_gen_dup_i32(vece, t_32, in_32); | ||
105 | } | ||
106 | } else if (in_64) { | ||
107 | /* We are given a 64-bit variable input. */ | ||
108 | t_64 = tcg_temp_new_i64(); | ||
109 | - gen_dup_i64(vece, t_64, in_64); | ||
110 | + tcg_gen_dup_i64(vece, t_64, in_64); | ||
111 | } else { | ||
112 | /* We are given a constant input. */ | ||
113 | /* For 64-bit hosts, use 64-bit constants for "simple" constants | ||
114 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, uint32_t oprsz, | ||
115 | } else if (g->fni8 && check_size_impl(oprsz, 8)) { | ||
116 | TCGv_i64 t64 = tcg_temp_new_i64(); | ||
117 | |||
118 | - gen_dup_i64(g->vece, t64, c); | ||
119 | + tcg_gen_dup_i64(g->vece, t64, c); | ||
120 | expand_2s_i64(dofs, aofs, oprsz, t64, g->scalar_first, g->fni8); | ||
121 | tcg_temp_free_i64(t64); | ||
122 | } else if (g->fni4 && check_size_impl(oprsz, 4)) { | ||
123 | TCGv_i32 t32 = tcg_temp_new_i32(); | ||
124 | |||
125 | tcg_gen_extrl_i64_i32(t32, c); | ||
126 | - gen_dup_i32(g->vece, t32, t32); | ||
127 | + tcg_gen_dup_i32(g->vece, t32, t32); | ||
128 | expand_2s_i32(dofs, aofs, oprsz, t32, g->scalar_first, g->fni4); | ||
129 | tcg_temp_free_i32(t32); | ||
130 | } else { | ||
131 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_ands(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
132 | TCGv_i64 c, uint32_t oprsz, uint32_t maxsz) | ||
133 | { | ||
134 | TCGv_i64 tmp = tcg_temp_new_i64(); | ||
135 | - gen_dup_i64(vece, tmp, c); | ||
136 | + tcg_gen_dup_i64(vece, tmp, c); | ||
137 | tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ands); | ||
138 | tcg_temp_free_i64(tmp); | ||
139 | } | ||
140 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_xors(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
141 | TCGv_i64 c, uint32_t oprsz, uint32_t maxsz) | ||
142 | { | ||
143 | TCGv_i64 tmp = tcg_temp_new_i64(); | ||
144 | - gen_dup_i64(vece, tmp, c); | ||
145 | + tcg_gen_dup_i64(vece, tmp, c); | ||
146 | tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_xors); | ||
147 | tcg_temp_free_i64(tmp); | ||
148 | } | ||
149 | @@ -XXX,XX +XXX,XX @@ void tcg_gen_gvec_ors(unsigned vece, uint32_t dofs, uint32_t aofs, | ||
150 | TCGv_i64 c, uint32_t oprsz, uint32_t maxsz) | ||
151 | { | ||
152 | TCGv_i64 tmp = tcg_temp_new_i64(); | ||
153 | - gen_dup_i64(vece, tmp, c); | ||
154 | + tcg_gen_dup_i64(vece, tmp, c); | ||
155 | tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ors); | ||
156 | tcg_temp_free_i64(tmp); | ||
157 | } | ||
158 | -- | ||
159 | 2.20.1 | ||
160 | |||
161 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Implement the MVE VDUP insn, which duplicates a value from | ||
2 | a general-purpose register into every lane of a vector | ||
3 | register (subject to predication). | ||
1 | 4 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20210617121628.20116-11-peter.maydell@linaro.org | ||
8 | --- | ||
9 | target/arm/helper-mve.h | 2 ++ | ||
10 | target/arm/mve.decode | 10 ++++++++++ | ||
11 | target/arm/mve_helper.c | 16 ++++++++++++++++ | ||
12 | target/arm/translate-mve.c | 27 +++++++++++++++++++++++++++ | ||
13 | 4 files changed, 55 insertions(+) | ||
14 | |||
15 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | ||
17 | --- a/target/arm/helper-mve.h | ||
18 | +++ b/target/arm/helper-mve.h | ||
19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vstrb_h, TCG_CALL_NO_WG, void, env, ptr, i32) | ||
20 | DEF_HELPER_FLAGS_3(mve_vstrb_w, TCG_CALL_NO_WG, void, env, ptr, i32) | ||
21 | DEF_HELPER_FLAGS_3(mve_vstrh_w, TCG_CALL_NO_WG, void, env, ptr, i32) | ||
22 | |||
23 | +DEF_HELPER_FLAGS_3(mve_vdup, TCG_CALL_NO_WG, void, env, ptr, i32) | ||
24 | + | ||
25 | DEF_HELPER_FLAGS_3(mve_vclsb, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
26 | DEF_HELPER_FLAGS_3(mve_vclsh, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
27 | DEF_HELPER_FLAGS_3(mve_vclsw, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
28 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/target/arm/mve.decode | ||
31 | +++ b/target/arm/mve.decode | ||
32 | @@ -XXX,XX +XXX,XX @@ | ||
33 | |||
34 | %qd 22:1 13:3 | ||
35 | %qm 5:1 1:3 | ||
36 | +%qn 7:1 17:3 | ||
37 | |||
38 | &vldr_vstr rn qd imm p a w size l u | ||
39 | &1op qd qm size | ||
40 | @@ -XXX,XX +XXX,XX @@ VABS 1111 1111 1 . 11 .. 01 ... 0 0011 01 . 0 ... 0 @1op | ||
41 | VABS_fp 1111 1111 1 . 11 .. 01 ... 0 0111 01 . 0 ... 0 @1op | ||
42 | VNEG 1111 1111 1 . 11 .. 01 ... 0 0011 11 . 0 ... 0 @1op | ||
43 | VNEG_fp 1111 1111 1 . 11 .. 01 ... 0 0111 11 . 0 ... 0 @1op | ||
44 | + | ||
45 | +&vdup qd rt size | ||
46 | +# Qd is in the fields usually named Qn | ||
47 | +@vdup .... .... . . .. ... . rt:4 .... . . . . .... qd=%qn &vdup | ||
48 | + | ||
49 | +# B and E bits encode size, which we decode here to the usual size values | ||
50 | +VDUP 1110 1110 1 1 10 ... 0 .... 1011 . 0 0 1 0000 @vdup size=0 | ||
51 | +VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0 1 1 0000 @vdup size=1 | ||
52 | +VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0 0 1 0000 @vdup size=2 | ||
53 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
54 | index XXXXXXX..XXXXXXX 100644 | ||
55 | --- a/target/arm/mve_helper.c | ||
56 | +++ b/target/arm/mve_helper.c | ||
57 | @@ -XXX,XX +XXX,XX @@ static void mergemask_sq(int64_t *d, int64_t r, uint16_t mask) | ||
58 | uint64_t *: mergemask_uq, \ | ||
59 | int64_t *: mergemask_sq)(D, R, M) | ||
60 | |||
61 | +void HELPER(mve_vdup)(CPUARMState *env, void *vd, uint32_t val) | ||
62 | +{ | ||
63 | + /* | ||
64 | + * The generated code already replicated an 8 or 16 bit constant | ||
65 | + * into the 32-bit value, so we only need to write the 32-bit | ||
66 | + * value to all elements of the Qreg, allowing for predication. | ||
67 | + */ | ||
68 | + uint32_t *d = vd; | ||
69 | + uint16_t mask = mve_element_mask(env); | ||
70 | + unsigned e; | ||
71 | + for (e = 0; e < 16 / 4; e++, mask >>= 4) { | ||
72 | + mergemask(&d[H4(e)], val, mask); | ||
73 | + } | ||
74 | + mve_advance_vpt(env); | ||
75 | +} | ||
76 | + | ||
77 | #define DO_1OP(OP, ESIZE, TYPE, FN) \ | ||
78 | void HELPER(mve_##OP)(CPUARMState *env, void *vd, void *vm) \ | ||
79 | { \ | ||
80 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
81 | index XXXXXXX..XXXXXXX 100644 | ||
82 | --- a/target/arm/translate-mve.c | ||
83 | +++ b/target/arm/translate-mve.c | ||
84 | @@ -XXX,XX +XXX,XX @@ DO_VLDST_WIDE_NARROW(VLDSTB_H, vldrb_sh, vldrb_uh, vstrb_h) | ||
85 | DO_VLDST_WIDE_NARROW(VLDSTB_W, vldrb_sw, vldrb_uw, vstrb_w) | ||
86 | DO_VLDST_WIDE_NARROW(VLDSTH_W, vldrh_sw, vldrh_uw, vstrh_w) | ||
87 | |||
88 | +static bool trans_VDUP(DisasContext *s, arg_VDUP *a) | ||
89 | +{ | ||
90 | + TCGv_ptr qd; | ||
91 | + TCGv_i32 rt; | ||
92 | + | ||
93 | + if (!dc_isar_feature(aa32_mve, s) || | ||
94 | + !mve_check_qreg_bank(s, a->qd)) { | ||
95 | + return false; | ||
96 | + } | ||
97 | + if (a->rt == 13 || a->rt == 15) { | ||
98 | + /* UNPREDICTABLE; we choose to UNDEF */ | ||
99 | + return false; | ||
100 | + } | ||
101 | + if (!mve_eci_check(s) || !vfp_access_check(s)) { | ||
102 | + return true; | ||
103 | + } | ||
104 | + | ||
105 | + qd = mve_qreg_ptr(a->qd); | ||
106 | + rt = load_reg(s, a->rt); | ||
107 | + tcg_gen_dup_i32(a->size, rt, rt); | ||
108 | + gen_helper_mve_vdup(cpu_env, qd, rt); | ||
109 | + tcg_temp_free_ptr(qd); | ||
110 | + tcg_temp_free_i32(rt); | ||
111 | + mve_update_eci(s); | ||
112 | + return true; | ||
113 | +} | ||
114 | + | ||
115 | static bool do_1op(DisasContext *s, arg_1op *a, MVEGenOneOpFn fn) | ||
116 | { | ||
117 | TCGv_ptr qd, qm; | ||
118 | -- | ||
119 | 2.20.1 | ||
120 | |||
121 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Implement the MVE vector logical operations operating | ||
2 | on two registers. | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20210617121628.20116-12-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/arm/helper-mve.h | 6 ++++++ | ||
9 | target/arm/mve.decode | 9 +++++++++ | ||
10 | target/arm/mve_helper.c | 26 ++++++++++++++++++++++++++ | ||
11 | target/arm/translate-mve.c | 37 +++++++++++++++++++++++++++++++++++++ | ||
12 | 4 files changed, 78 insertions(+) | ||
13 | |||
14 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/helper-mve.h | ||
17 | +++ b/target/arm/helper-mve.h | ||
18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(mve_vnegh, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
19 | DEF_HELPER_FLAGS_3(mve_vnegw, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
20 | DEF_HELPER_FLAGS_3(mve_vfnegh, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
21 | DEF_HELPER_FLAGS_3(mve_vfnegs, TCG_CALL_NO_WG, void, env, ptr, ptr) | ||
22 | + | ||
23 | +DEF_HELPER_FLAGS_4(mve_vand, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
24 | +DEF_HELPER_FLAGS_4(mve_vbic, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
25 | +DEF_HELPER_FLAGS_4(mve_vorr, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
26 | +DEF_HELPER_FLAGS_4(mve_vorn, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
27 | +DEF_HELPER_FLAGS_4(mve_veor, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
28 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/target/arm/mve.decode | ||
31 | +++ b/target/arm/mve.decode | ||
32 | @@ -XXX,XX +XXX,XX @@ | ||
33 | |||
34 | &vldr_vstr rn qd imm p a w size l u | ||
35 | &1op qd qm size | ||
36 | +&2op qd qm qn size | ||
37 | |||
38 | @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0 | ||
39 | # Note that both Rn and Qd are 3 bits only (no D bit) | ||
40 | @@ -XXX,XX +XXX,XX @@ | ||
41 | |||
42 | @1op .... .... .... size:2 .. .... .... .... .... &1op qd=%qd qm=%qm | ||
43 | @1op_nosz .... .... .... .... .... .... .... .... &1op qd=%qd qm=%qm size=0 | ||
44 | +@2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0 | ||
45 | |||
46 | # Vector loads and stores | ||
47 | |||
48 | @@ -XXX,XX +XXX,XX @@ VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111101 ....... @vldr_vstr \ | ||
49 | VLDR_VSTR 1110110 1 a:1 . w:1 . .... ... 111110 ....... @vldr_vstr \ | ||
50 | size=2 p=1 | ||
51 | |||
52 | +# Vector 2-op | ||
53 | +VAND 1110 1111 0 . 00 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz | ||
54 | +VBIC 1110 1111 0 . 01 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz | ||
55 | +VORR 1110 1111 0 . 10 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz | ||
56 | +VORN 1110 1111 0 . 11 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz | ||
57 | +VEOR 1111 1111 0 . 00 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz | ||
58 | + | ||
59 | # Vector miscellaneous | ||
60 | |||
61 | VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op | ||
62 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
63 | index XXXXXXX..XXXXXXX 100644 | ||
64 | --- a/target/arm/mve_helper.c | ||
65 | +++ b/target/arm/mve_helper.c | ||
66 | @@ -XXX,XX +XXX,XX @@ DO_1OP(vnegw, 4, int32_t, DO_NEG) | ||
67 | /* We can do these 64 bits at a time */ | ||
68 | DO_1OP(vfnegh, 8, uint64_t, DO_FNEGH) | ||
69 | DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS) | ||
70 | + | ||
71 | +#define DO_2OP(OP, ESIZE, TYPE, FN) \ | ||
72 | + void HELPER(glue(mve_, OP))(CPUARMState *env, \ | ||
73 | + void *vd, void *vn, void *vm) \ | ||
74 | + { \ | ||
75 | + TYPE *d = vd, *n = vn, *m = vm; \ | ||
76 | + uint16_t mask = mve_element_mask(env); \ | ||
77 | + unsigned e; \ | ||
78 | + for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ | ||
79 | + mergemask(&d[H##ESIZE(e)], \ | ||
80 | + FN(n[H##ESIZE(e)], m[H##ESIZE(e)]), mask); \ | ||
81 | + } \ | ||
82 | + mve_advance_vpt(env); \ | ||
83 | + } | ||
84 | + | ||
85 | +#define DO_AND(N, M) ((N) & (M)) | ||
86 | +#define DO_BIC(N, M) ((N) & ~(M)) | ||
87 | +#define DO_ORR(N, M) ((N) | (M)) | ||
88 | +#define DO_ORN(N, M) ((N) | ~(M)) | ||
89 | +#define DO_EOR(N, M) ((N) ^ (M)) | ||
90 | + | ||
91 | +DO_2OP(vand, 8, uint64_t, DO_AND) | ||
92 | +DO_2OP(vbic, 8, uint64_t, DO_BIC) | ||
93 | +DO_2OP(vorr, 8, uint64_t, DO_ORR) | ||
94 | +DO_2OP(vorn, 8, uint64_t, DO_ORN) | ||
95 | +DO_2OP(veor, 8, uint64_t, DO_EOR) | ||
96 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
97 | index XXXXXXX..XXXXXXX 100644 | ||
98 | --- a/target/arm/translate-mve.c | ||
99 | +++ b/target/arm/translate-mve.c | ||
100 | @@ -XXX,XX +XXX,XX @@ | ||
101 | |||
102 | typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
103 | typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
104 | +typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
105 | |||
106 | /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */ | ||
107 | static inline long mve_qreg_offset(unsigned reg) | ||
108 | @@ -XXX,XX +XXX,XX @@ static bool trans_VNEG_fp(DisasContext *s, arg_1op *a) | ||
109 | } | ||
110 | return do_1op(s, a, fns[a->size]); | ||
111 | } | ||
112 | + | ||
113 | +static bool do_2op(DisasContext *s, arg_2op *a, MVEGenTwoOpFn fn) | ||
114 | +{ | ||
115 | + TCGv_ptr qd, qn, qm; | ||
116 | + | ||
117 | + if (!dc_isar_feature(aa32_mve, s) || | ||
118 | + !mve_check_qreg_bank(s, a->qd | a->qn | a->qm) || | ||
119 | + !fn) { | ||
120 | + return false; | ||
121 | + } | ||
122 | + if (!mve_eci_check(s) || !vfp_access_check(s)) { | ||
123 | + return true; | ||
124 | + } | ||
125 | + | ||
126 | + qd = mve_qreg_ptr(a->qd); | ||
127 | + qn = mve_qreg_ptr(a->qn); | ||
128 | + qm = mve_qreg_ptr(a->qm); | ||
129 | + fn(cpu_env, qd, qn, qm); | ||
130 | + tcg_temp_free_ptr(qd); | ||
131 | + tcg_temp_free_ptr(qn); | ||
132 | + tcg_temp_free_ptr(qm); | ||
133 | + mve_update_eci(s); | ||
134 | + return true; | ||
135 | +} | ||
136 | + | ||
137 | +#define DO_LOGIC(INSN, HELPER) \ | ||
138 | + static bool trans_##INSN(DisasContext *s, arg_2op *a) \ | ||
139 | + { \ | ||
140 | + return do_2op(s, a, HELPER); \ | ||
141 | + } | ||
142 | + | ||
143 | +DO_LOGIC(VAND, gen_helper_mve_vand) | ||
144 | +DO_LOGIC(VBIC, gen_helper_mve_vbic) | ||
145 | +DO_LOGIC(VORR, gen_helper_mve_vorr) | ||
146 | +DO_LOGIC(VORN, gen_helper_mve_vorn) | ||
147 | +DO_LOGIC(VEOR, gen_helper_mve_veor) | ||
148 | -- | ||
149 | 2.20.1 | ||
150 | |||
151 | diff view generated by jsdifflib |
1 | The M-profile FPCCR.S bit indicates the security status of | 1 | Implement the MVE VADD, VSUB and VMUL insns. |
---|---|---|---|
2 | the floating point context. In the pseudocode ExecuteFPCheck() | ||
3 | function it is unconditionally set to match the current | ||
4 | security state whenever a floating point instruction is | ||
5 | executed. | ||
6 | |||
7 | Implement this by adding a new TB flag which tracks whether | ||
8 | FPCCR.S is different from the current security state, so | ||
9 | that we only need to emit the code to update it in the | ||
10 | less-common case when it is not already set correctly. | ||
11 | |||
12 | Note that we will add the handling for the other work done | ||
13 | by ExecuteFPCheck() in later commits. | ||
14 | 2 | ||
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
17 | Message-id: 20190416125744.27770-19-peter.maydell@linaro.org | 5 | Message-id: 20210617121628.20116-13-peter.maydell@linaro.org |
18 | --- | 6 | --- |
19 | target/arm/cpu.h | 2 ++ | 7 | target/arm/helper-mve.h | 12 ++++++++++++ |
20 | target/arm/translate.h | 1 + | 8 | target/arm/mve.decode | 5 +++++ |
21 | target/arm/helper.c | 5 +++++ | 9 | target/arm/mve_helper.c | 14 ++++++++++++++ |
22 | target/arm/translate.c | 20 ++++++++++++++++++++ | 10 | target/arm/translate-mve.c | 16 ++++++++++++++++ |
23 | 4 files changed, 28 insertions(+) | 11 | 4 files changed, 47 insertions(+) |
24 | 12 | ||
25 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 13 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
26 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
27 | --- a/target/arm/cpu.h | 15 | --- a/target/arm/helper-mve.h |
28 | +++ b/target/arm/cpu.h | 16 | +++ b/target/arm/helper-mve.h |
29 | @@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A32, NS, 6, 1) | 17 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vbic, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
30 | FIELD(TBFLAG_A32, VFPEN, 7, 1) | 18 | DEF_HELPER_FLAGS_4(mve_vorr, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
31 | FIELD(TBFLAG_A32, CONDEXEC, 8, 8) | 19 | DEF_HELPER_FLAGS_4(mve_vorn, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
32 | FIELD(TBFLAG_A32, SCTLR_B, 16, 1) | 20 | DEF_HELPER_FLAGS_4(mve_veor, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
33 | +/* For M profile only, set if FPCCR.S does not match current security state */ | 21 | + |
34 | +FIELD(TBFLAG_A32, FPCCR_S_WRONG, 20, 1) | 22 | +DEF_HELPER_FLAGS_4(mve_vaddb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
35 | /* For M profile only, Handler (ie not Thread) mode */ | 23 | +DEF_HELPER_FLAGS_4(mve_vaddh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
36 | FIELD(TBFLAG_A32, HANDLER, 21, 1) | 24 | +DEF_HELPER_FLAGS_4(mve_vaddw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
37 | /* For M profile only, whether we should generate stack-limit checks */ | 25 | + |
38 | diff --git a/target/arm/translate.h b/target/arm/translate.h | 26 | +DEF_HELPER_FLAGS_4(mve_vsubb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
27 | +DEF_HELPER_FLAGS_4(mve_vsubh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
28 | +DEF_HELPER_FLAGS_4(mve_vsubw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
29 | + | ||
30 | +DEF_HELPER_FLAGS_4(mve_vmulb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
31 | +DEF_HELPER_FLAGS_4(mve_vmulh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
32 | +DEF_HELPER_FLAGS_4(mve_vmulw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
33 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
39 | index XXXXXXX..XXXXXXX 100644 | 34 | index XXXXXXX..XXXXXXX 100644 |
40 | --- a/target/arm/translate.h | 35 | --- a/target/arm/mve.decode |
41 | +++ b/target/arm/translate.h | 36 | +++ b/target/arm/mve.decode |
42 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { | 37 | @@ -XXX,XX +XXX,XX @@ |
43 | bool v7m_handler_mode; | 38 | |
44 | bool v8m_secure; /* true if v8M and we're in Secure mode */ | 39 | @1op .... .... .... size:2 .. .... .... .... .... &1op qd=%qd qm=%qm |
45 | bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */ | 40 | @1op_nosz .... .... .... .... .... .... .... .... &1op qd=%qd qm=%qm size=0 |
46 | + bool v8m_fpccr_s_wrong; /* true if v8M FPCCR.S != v8m_secure */ | 41 | +@2op .... .... .. size:2 .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn |
47 | /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI | 42 | @2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0 |
48 | * so that top level loop can generate correct syndrome information. | 43 | |
49 | */ | 44 | # Vector loads and stores |
50 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 45 | @@ -XXX,XX +XXX,XX @@ VORR 1110 1111 0 . 10 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz |
46 | VORN 1110 1111 0 . 11 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz | ||
47 | VEOR 1111 1111 0 . 00 ... 0 ... 0 0001 . 1 . 1 ... 0 @2op_nosz | ||
48 | |||
49 | +VADD 1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op | ||
50 | +VSUB 1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op | ||
51 | +VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op | ||
52 | + | ||
53 | # Vector miscellaneous | ||
54 | |||
55 | VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op | ||
56 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
51 | index XXXXXXX..XXXXXXX 100644 | 57 | index XXXXXXX..XXXXXXX 100644 |
52 | --- a/target/arm/helper.c | 58 | --- a/target/arm/mve_helper.c |
53 | +++ b/target/arm/helper.c | 59 | +++ b/target/arm/mve_helper.c |
54 | @@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, | 60 | @@ -XXX,XX +XXX,XX @@ DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS) |
55 | flags = FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1); | 61 | mve_advance_vpt(env); \ |
56 | } | 62 | } |
57 | 63 | ||
58 | + if (arm_feature(env, ARM_FEATURE_M_SECURITY) && | 64 | +/* provide unsigned 2-op helpers for all sizes */ |
59 | + FIELD_EX32(env->v7m.fpccr[M_REG_S], V7M_FPCCR, S) != env->v7m.secure) { | 65 | +#define DO_2OP_U(OP, FN) \ |
60 | + flags = FIELD_DP32(flags, TBFLAG_A32, FPCCR_S_WRONG, 1); | 66 | + DO_2OP(OP##b, 1, uint8_t, FN) \ |
67 | + DO_2OP(OP##h, 2, uint16_t, FN) \ | ||
68 | + DO_2OP(OP##w, 4, uint32_t, FN) | ||
69 | + | ||
70 | #define DO_AND(N, M) ((N) & (M)) | ||
71 | #define DO_BIC(N, M) ((N) & ~(M)) | ||
72 | #define DO_ORR(N, M) ((N) | (M)) | ||
73 | @@ -XXX,XX +XXX,XX @@ DO_2OP(vbic, 8, uint64_t, DO_BIC) | ||
74 | DO_2OP(vorr, 8, uint64_t, DO_ORR) | ||
75 | DO_2OP(vorn, 8, uint64_t, DO_ORN) | ||
76 | DO_2OP(veor, 8, uint64_t, DO_EOR) | ||
77 | + | ||
78 | +#define DO_ADD(N, M) ((N) + (M)) | ||
79 | +#define DO_SUB(N, M) ((N) - (M)) | ||
80 | +#define DO_MUL(N, M) ((N) * (M)) | ||
81 | + | ||
82 | +DO_2OP_U(vadd, DO_ADD) | ||
83 | +DO_2OP_U(vsub, DO_SUB) | ||
84 | +DO_2OP_U(vmul, DO_MUL) | ||
85 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
86 | index XXXXXXX..XXXXXXX 100644 | ||
87 | --- a/target/arm/translate-mve.c | ||
88 | +++ b/target/arm/translate-mve.c | ||
89 | @@ -XXX,XX +XXX,XX @@ DO_LOGIC(VBIC, gen_helper_mve_vbic) | ||
90 | DO_LOGIC(VORR, gen_helper_mve_vorr) | ||
91 | DO_LOGIC(VORN, gen_helper_mve_vorn) | ||
92 | DO_LOGIC(VEOR, gen_helper_mve_veor) | ||
93 | + | ||
94 | +#define DO_2OP(INSN, FN) \ | ||
95 | + static bool trans_##INSN(DisasContext *s, arg_2op *a) \ | ||
96 | + { \ | ||
97 | + static MVEGenTwoOpFn * const fns[] = { \ | ||
98 | + gen_helper_mve_##FN##b, \ | ||
99 | + gen_helper_mve_##FN##h, \ | ||
100 | + gen_helper_mve_##FN##w, \ | ||
101 | + NULL, \ | ||
102 | + }; \ | ||
103 | + return do_2op(s, a, fns[a->size]); \ | ||
61 | + } | 104 | + } |
62 | + | 105 | + |
63 | *pflags = flags; | 106 | +DO_2OP(VADD, vadd) |
64 | *cs_base = 0; | 107 | +DO_2OP(VSUB, vsub) |
65 | } | 108 | +DO_2OP(VMUL, vmul) |
66 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
67 | index XXXXXXX..XXXXXXX 100644 | ||
68 | --- a/target/arm/translate.c | ||
69 | +++ b/target/arm/translate.c | ||
70 | @@ -XXX,XX +XXX,XX @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) | ||
71 | } | ||
72 | } | ||
73 | |||
74 | + if (arm_dc_feature(s, ARM_FEATURE_M)) { | ||
75 | + /* Handle M-profile lazy FP state mechanics */ | ||
76 | + | ||
77 | + /* Update ownership of FP context: set FPCCR.S to match current state */ | ||
78 | + if (s->v8m_fpccr_s_wrong) { | ||
79 | + TCGv_i32 tmp; | ||
80 | + | ||
81 | + tmp = load_cpu_field(v7m.fpccr[M_REG_S]); | ||
82 | + if (s->v8m_secure) { | ||
83 | + tcg_gen_ori_i32(tmp, tmp, R_V7M_FPCCR_S_MASK); | ||
84 | + } else { | ||
85 | + tcg_gen_andi_i32(tmp, tmp, ~R_V7M_FPCCR_S_MASK); | ||
86 | + } | ||
87 | + store_cpu_field(tmp, v7m.fpccr[M_REG_S]); | ||
88 | + /* Don't need to do this for any further FP insns in this TB */ | ||
89 | + s->v8m_fpccr_s_wrong = false; | ||
90 | + } | ||
91 | + } | ||
92 | + | ||
93 | if (extract32(insn, 28, 4) == 0xf) { | ||
94 | /* | ||
95 | * Encodings with T=1 (Thumb) or unconditional (ARM): | ||
96 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) | ||
97 | dc->v8m_secure = arm_feature(env, ARM_FEATURE_M_SECURITY) && | ||
98 | regime_is_secure(env, dc->mmu_idx); | ||
99 | dc->v8m_stackcheck = FIELD_EX32(tb_flags, TBFLAG_A32, STACKCHECK); | ||
100 | + dc->v8m_fpccr_s_wrong = FIELD_EX32(tb_flags, TBFLAG_A32, FPCCR_S_WRONG); | ||
101 | dc->cp_regs = cpu->cp_regs; | ||
102 | dc->features = env->features; | ||
103 | |||
104 | -- | 109 | -- |
105 | 2.20.1 | 110 | 2.20.1 |
106 | 111 | ||
107 | 112 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Implement the MVE VMULH insn, which performs a vector | ||
2 | multiply and returns the high half of the result. | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
6 | Message-id: 20210617121628.20116-14-peter.maydell@linaro.org | ||
7 | --- | ||
8 | target/arm/helper-mve.h | 7 +++++++ | ||
9 | target/arm/mve.decode | 3 +++ | ||
10 | target/arm/mve_helper.c | 26 ++++++++++++++++++++++++++ | ||
11 | target/arm/translate-mve.c | 2 ++ | ||
12 | 4 files changed, 38 insertions(+) | ||
13 | |||
14 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/helper-mve.h | ||
17 | +++ b/target/arm/helper-mve.h | ||
18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vsubw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
19 | DEF_HELPER_FLAGS_4(mve_vmulb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
20 | DEF_HELPER_FLAGS_4(mve_vmulh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
21 | DEF_HELPER_FLAGS_4(mve_vmulw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
22 | + | ||
23 | +DEF_HELPER_FLAGS_4(mve_vmulhsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
24 | +DEF_HELPER_FLAGS_4(mve_vmulhsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
25 | +DEF_HELPER_FLAGS_4(mve_vmulhsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
26 | +DEF_HELPER_FLAGS_4(mve_vmulhub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
27 | +DEF_HELPER_FLAGS_4(mve_vmulhuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
28 | +DEF_HELPER_FLAGS_4(mve_vmulhuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
29 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/target/arm/mve.decode | ||
32 | +++ b/target/arm/mve.decode | ||
33 | @@ -XXX,XX +XXX,XX @@ VADD 1110 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op | ||
34 | VSUB 1111 1111 0 . .. ... 0 ... 0 1000 . 1 . 0 ... 0 @2op | ||
35 | VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op | ||
36 | |||
37 | +VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op | ||
38 | +VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op | ||
39 | + | ||
40 | # Vector miscellaneous | ||
41 | |||
42 | VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op | ||
43 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/target/arm/mve_helper.c | ||
46 | +++ b/target/arm/mve_helper.c | ||
47 | @@ -XXX,XX +XXX,XX @@ DO_2OP(veor, 8, uint64_t, DO_EOR) | ||
48 | DO_2OP_U(vadd, DO_ADD) | ||
49 | DO_2OP_U(vsub, DO_SUB) | ||
50 | DO_2OP_U(vmul, DO_MUL) | ||
51 | + | ||
52 | +/* | ||
53 | + * Because the computation type is at least twice as large as required, | ||
54 | + * these work for both signed and unsigned source types. | ||
55 | + */ | ||
56 | +static inline uint8_t do_mulh_b(int32_t n, int32_t m) | ||
57 | +{ | ||
58 | + return (n * m) >> 8; | ||
59 | +} | ||
60 | + | ||
61 | +static inline uint16_t do_mulh_h(int32_t n, int32_t m) | ||
62 | +{ | ||
63 | + return (n * m) >> 16; | ||
64 | +} | ||
65 | + | ||
66 | +static inline uint32_t do_mulh_w(int64_t n, int64_t m) | ||
67 | +{ | ||
68 | + return (n * m) >> 32; | ||
69 | +} | ||
70 | + | ||
71 | +DO_2OP(vmulhsb, 1, int8_t, do_mulh_b) | ||
72 | +DO_2OP(vmulhsh, 2, int16_t, do_mulh_h) | ||
73 | +DO_2OP(vmulhsw, 4, int32_t, do_mulh_w) | ||
74 | +DO_2OP(vmulhub, 1, uint8_t, do_mulh_b) | ||
75 | +DO_2OP(vmulhuh, 2, uint16_t, do_mulh_h) | ||
76 | +DO_2OP(vmulhuw, 4, uint32_t, do_mulh_w) | ||
77 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
78 | index XXXXXXX..XXXXXXX 100644 | ||
79 | --- a/target/arm/translate-mve.c | ||
80 | +++ b/target/arm/translate-mve.c | ||
81 | @@ -XXX,XX +XXX,XX @@ DO_LOGIC(VEOR, gen_helper_mve_veor) | ||
82 | DO_2OP(VADD, vadd) | ||
83 | DO_2OP(VSUB, vsub) | ||
84 | DO_2OP(VMUL, vmul) | ||
85 | +DO_2OP(VMULH_S, vmulhs) | ||
86 | +DO_2OP(VMULH_U, vmulhu) | ||
87 | -- | ||
88 | 2.20.1 | ||
89 | |||
90 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | 1 | Implement the MVE VRMULH insn, which performs a rounding multiply |
---|---|---|---|
2 | and then returns the high half. | ||
2 | 3 | ||
3 | No code used the tc6393xb_gpio_in_get() and tc6393xb_gpio_out_set() | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | functions since their introduction in commit 88d2c950b002. Time to | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | remove them. | 6 | Message-id: 20210617121628.20116-15-peter.maydell@linaro.org |
7 | --- | ||
8 | target/arm/helper-mve.h | 7 +++++++ | ||
9 | target/arm/mve.decode | 3 +++ | ||
10 | target/arm/mve_helper.c | 22 ++++++++++++++++++++++ | ||
11 | target/arm/translate-mve.c | 2 ++ | ||
12 | 4 files changed, 34 insertions(+) | ||
6 | 13 | ||
7 | Suggested-by: Markus Armbruster <armbru@redhat.com> | 14 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
8 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
9 | Message-id: 20190412165416.7977-4-philmd@redhat.com | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | include/hw/devices.h | 3 --- | ||
14 | hw/display/tc6393xb.c | 16 ---------------- | ||
15 | 2 files changed, 19 deletions(-) | ||
16 | |||
17 | diff --git a/include/hw/devices.h b/include/hw/devices.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/include/hw/devices.h | 16 | --- a/target/arm/helper-mve.h |
20 | +++ b/include/hw/devices.h | 17 | +++ b/target/arm/helper-mve.h |
21 | @@ -XXX,XX +XXX,XX @@ void retu_key_event(void *retu, int state); | 18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vmulhsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
22 | typedef struct TC6393xbState TC6393xbState; | 19 | DEF_HELPER_FLAGS_4(mve_vmulhub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
23 | TC6393xbState *tc6393xb_init(struct MemoryRegion *sysmem, | 20 | DEF_HELPER_FLAGS_4(mve_vmulhuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
24 | uint32_t base, qemu_irq irq); | 21 | DEF_HELPER_FLAGS_4(mve_vmulhuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
25 | -void tc6393xb_gpio_out_set(TC6393xbState *s, int line, | 22 | + |
26 | - qemu_irq handler); | 23 | +DEF_HELPER_FLAGS_4(mve_vrmulhsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
27 | -qemu_irq *tc6393xb_gpio_in_get(TC6393xbState *s); | 24 | +DEF_HELPER_FLAGS_4(mve_vrmulhsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
28 | qemu_irq tc6393xb_l3v_get(TC6393xbState *s); | 25 | +DEF_HELPER_FLAGS_4(mve_vrmulhsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
29 | 26 | +DEF_HELPER_FLAGS_4(mve_vrmulhub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | |
30 | #endif | 27 | +DEF_HELPER_FLAGS_4(mve_vrmulhuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
31 | diff --git a/hw/display/tc6393xb.c b/hw/display/tc6393xb.c | 28 | +DEF_HELPER_FLAGS_4(mve_vrmulhuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
29 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
32 | index XXXXXXX..XXXXXXX 100644 | 30 | index XXXXXXX..XXXXXXX 100644 |
33 | --- a/hw/display/tc6393xb.c | 31 | --- a/target/arm/mve.decode |
34 | +++ b/hw/display/tc6393xb.c | 32 | +++ b/target/arm/mve.decode |
35 | @@ -XXX,XX +XXX,XX @@ struct TC6393xbState { | 33 | @@ -XXX,XX +XXX,XX @@ VMUL 1110 1111 0 . .. ... 0 ... 0 1001 . 1 . 1 ... 0 @2op |
36 | blanked : 1; | 34 | VMULH_S 111 0 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op |
37 | }; | 35 | VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op |
38 | 36 | ||
39 | -qemu_irq *tc6393xb_gpio_in_get(TC6393xbState *s) | 37 | +VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op |
40 | -{ | 38 | +VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op |
41 | - return s->gpio_in; | 39 | + |
42 | -} | 40 | # Vector miscellaneous |
43 | - | 41 | |
44 | static void tc6393xb_gpio_set(void *opaque, int line, int level) | 42 | VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op |
45 | { | 43 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c |
46 | // TC6393xbState *s = opaque; | 44 | index XXXXXXX..XXXXXXX 100644 |
47 | @@ -XXX,XX +XXX,XX @@ static void tc6393xb_gpio_set(void *opaque, int line, int level) | 45 | --- a/target/arm/mve_helper.c |
48 | // FIXME: how does the chip reflect the GPIO input level change? | 46 | +++ b/target/arm/mve_helper.c |
47 | @@ -XXX,XX +XXX,XX @@ static inline uint32_t do_mulh_w(int64_t n, int64_t m) | ||
48 | return (n * m) >> 32; | ||
49 | } | 49 | } |
50 | 50 | ||
51 | -void tc6393xb_gpio_out_set(TC6393xbState *s, int line, | 51 | +static inline uint8_t do_rmulh_b(int32_t n, int32_t m) |
52 | - qemu_irq handler) | 52 | +{ |
53 | -{ | 53 | + return (n * m + (1U << 7)) >> 8; |
54 | - if (line >= TC6393XB_GPIOS) { | 54 | +} |
55 | - fprintf(stderr, "TC6393xb: no GPIO pin %d\n", line); | 55 | + |
56 | - return; | 56 | +static inline uint16_t do_rmulh_h(int32_t n, int32_t m) |
57 | - } | 57 | +{ |
58 | - | 58 | + return (n * m + (1U << 15)) >> 16; |
59 | - s->handler[line] = handler; | 59 | +} |
60 | -} | 60 | + |
61 | - | 61 | +static inline uint32_t do_rmulh_w(int64_t n, int64_t m) |
62 | static void tc6393xb_gpio_handler_update(TC6393xbState *s) | 62 | +{ |
63 | { | 63 | + return (n * m + (1U << 31)) >> 32; |
64 | uint32_t level, diff; | 64 | +} |
65 | + | ||
66 | DO_2OP(vmulhsb, 1, int8_t, do_mulh_b) | ||
67 | DO_2OP(vmulhsh, 2, int16_t, do_mulh_h) | ||
68 | DO_2OP(vmulhsw, 4, int32_t, do_mulh_w) | ||
69 | DO_2OP(vmulhub, 1, uint8_t, do_mulh_b) | ||
70 | DO_2OP(vmulhuh, 2, uint16_t, do_mulh_h) | ||
71 | DO_2OP(vmulhuw, 4, uint32_t, do_mulh_w) | ||
72 | + | ||
73 | +DO_2OP(vrmulhsb, 1, int8_t, do_rmulh_b) | ||
74 | +DO_2OP(vrmulhsh, 2, int16_t, do_rmulh_h) | ||
75 | +DO_2OP(vrmulhsw, 4, int32_t, do_rmulh_w) | ||
76 | +DO_2OP(vrmulhub, 1, uint8_t, do_rmulh_b) | ||
77 | +DO_2OP(vrmulhuh, 2, uint16_t, do_rmulh_h) | ||
78 | +DO_2OP(vrmulhuw, 4, uint32_t, do_rmulh_w) | ||
79 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
80 | index XXXXXXX..XXXXXXX 100644 | ||
81 | --- a/target/arm/translate-mve.c | ||
82 | +++ b/target/arm/translate-mve.c | ||
83 | @@ -XXX,XX +XXX,XX @@ DO_2OP(VSUB, vsub) | ||
84 | DO_2OP(VMUL, vmul) | ||
85 | DO_2OP(VMULH_S, vmulhs) | ||
86 | DO_2OP(VMULH_U, vmulhu) | ||
87 | +DO_2OP(VRMULH_S, vrmulhs) | ||
88 | +DO_2OP(VRMULH_U, vrmulhu) | ||
65 | -- | 89 | -- |
66 | 2.20.1 | 90 | 2.20.1 |
67 | 91 | ||
68 | 92 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | 1 | Implement the MVE VMAX and VMIN insns. |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Markus Armbruster <armbru@redhat.com> | ||
4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
5 | Message-id: 20190412165416.7977-12-philmd@redhat.com | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20210617121628.20116-16-peter.maydell@linaro.org | ||
7 | --- | 6 | --- |
8 | include/hw/net/lan9118.h | 2 ++ | 7 | target/arm/helper-mve.h | 14 ++++++++++++++ |
9 | hw/arm/exynos4_boards.c | 3 ++- | 8 | target/arm/mve.decode | 5 +++++ |
10 | hw/arm/mps2-tz.c | 3 ++- | 9 | target/arm/mve_helper.c | 14 ++++++++++++++ |
11 | hw/net/lan9118.c | 1 - | 10 | target/arm/translate-mve.c | 4 ++++ |
12 | 4 files changed, 6 insertions(+), 3 deletions(-) | 11 | 4 files changed, 37 insertions(+) |
13 | 12 | ||
14 | diff --git a/include/hw/net/lan9118.h b/include/hw/net/lan9118.h | 13 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
15 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/include/hw/net/lan9118.h | 15 | --- a/target/arm/helper-mve.h |
17 | +++ b/include/hw/net/lan9118.h | 16 | +++ b/target/arm/helper-mve.h |
18 | @@ -XXX,XX +XXX,XX @@ | 17 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrmulhsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
19 | #include "hw/irq.h" | 18 | DEF_HELPER_FLAGS_4(mve_vrmulhub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
20 | #include "net/net.h" | 19 | DEF_HELPER_FLAGS_4(mve_vrmulhuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
21 | 20 | DEF_HELPER_FLAGS_4(mve_vrmulhuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | |
22 | +#define TYPE_LAN9118 "lan9118" | ||
23 | + | 21 | + |
24 | void lan9118_init(NICInfo *, uint32_t, qemu_irq); | 22 | +DEF_HELPER_FLAGS_4(mve_vmaxsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
25 | 23 | +DEF_HELPER_FLAGS_4(mve_vmaxsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | |
26 | #endif | 24 | +DEF_HELPER_FLAGS_4(mve_vmaxsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
27 | diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c | 25 | +DEF_HELPER_FLAGS_4(mve_vmaxub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
26 | +DEF_HELPER_FLAGS_4(mve_vmaxuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
27 | +DEF_HELPER_FLAGS_4(mve_vmaxuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
28 | + | ||
29 | +DEF_HELPER_FLAGS_4(mve_vminsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
30 | +DEF_HELPER_FLAGS_4(mve_vminsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
31 | +DEF_HELPER_FLAGS_4(mve_vminsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
32 | +DEF_HELPER_FLAGS_4(mve_vminub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
33 | +DEF_HELPER_FLAGS_4(mve_vminuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
34 | +DEF_HELPER_FLAGS_4(mve_vminuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
35 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
28 | index XXXXXXX..XXXXXXX 100644 | 36 | index XXXXXXX..XXXXXXX 100644 |
29 | --- a/hw/arm/exynos4_boards.c | 37 | --- a/target/arm/mve.decode |
30 | +++ b/hw/arm/exynos4_boards.c | 38 | +++ b/target/arm/mve.decode |
31 | @@ -XXX,XX +XXX,XX @@ | 39 | @@ -XXX,XX +XXX,XX @@ VMULH_U 111 1 1110 0 . .. ...1 ... 0 1110 . 0 . 0 ... 1 @2op |
32 | #include "hw/arm/arm.h" | 40 | VRMULH_S 111 0 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op |
33 | #include "exec/address-spaces.h" | 41 | VRMULH_U 111 1 1110 0 . .. ...1 ... 1 1110 . 0 . 0 ... 1 @2op |
34 | #include "hw/arm/exynos4210.h" | 42 | |
35 | +#include "hw/net/lan9118.h" | 43 | +VMAX_S 111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op |
36 | #include "hw/boards.h" | 44 | +VMAX_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op |
37 | 45 | +VMIN_S 111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 1 ... 0 @2op | |
38 | #undef DEBUG | 46 | +VMIN_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 1 ... 0 @2op |
39 | @@ -XXX,XX +XXX,XX @@ static void lan9215_init(uint32_t base, qemu_irq irq) | 47 | + |
40 | /* This should be a 9215 but the 9118 is close enough */ | 48 | # Vector miscellaneous |
41 | if (nd_table[0].used) { | 49 | |
42 | qemu_check_nic_model(&nd_table[0], "lan9118"); | 50 | VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op |
43 | - dev = qdev_create(NULL, "lan9118"); | 51 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c |
44 | + dev = qdev_create(NULL, TYPE_LAN9118); | ||
45 | qdev_set_nic_properties(dev, &nd_table[0]); | ||
46 | qdev_prop_set_uint32(dev, "mode_16bit", 1); | ||
47 | qdev_init_nofail(dev); | ||
48 | diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c | ||
49 | index XXXXXXX..XXXXXXX 100644 | 52 | index XXXXXXX..XXXXXXX 100644 |
50 | --- a/hw/arm/mps2-tz.c | 53 | --- a/target/arm/mve_helper.c |
51 | +++ b/hw/arm/mps2-tz.c | 54 | +++ b/target/arm/mve_helper.c |
52 | @@ -XXX,XX +XXX,XX @@ | 55 | @@ -XXX,XX +XXX,XX @@ DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS) |
53 | #include "hw/arm/armsse.h" | 56 | DO_2OP(OP##h, 2, uint16_t, FN) \ |
54 | #include "hw/dma/pl080.h" | 57 | DO_2OP(OP##w, 4, uint32_t, FN) |
55 | #include "hw/ssi/pl022.h" | 58 | |
56 | +#include "hw/net/lan9118.h" | 59 | +/* provide signed 2-op helpers for all sizes */ |
57 | #include "net/net.h" | 60 | +#define DO_2OP_S(OP, FN) \ |
58 | #include "hw/core/split-irq.h" | 61 | + DO_2OP(OP##b, 1, int8_t, FN) \ |
59 | 62 | + DO_2OP(OP##h, 2, int16_t, FN) \ | |
60 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *make_eth_dev(MPS2TZMachineState *mms, void *opaque, | 63 | + DO_2OP(OP##w, 4, int32_t, FN) |
61 | * except that it doesn't support the checksum-offload feature. | 64 | + |
62 | */ | 65 | #define DO_AND(N, M) ((N) & (M)) |
63 | qemu_check_nic_model(nd, "lan9118"); | 66 | #define DO_BIC(N, M) ((N) & ~(M)) |
64 | - mms->lan9118 = qdev_create(NULL, "lan9118"); | 67 | #define DO_ORR(N, M) ((N) | (M)) |
65 | + mms->lan9118 = qdev_create(NULL, TYPE_LAN9118); | 68 | @@ -XXX,XX +XXX,XX @@ DO_2OP(vrmulhsw, 4, int32_t, do_rmulh_w) |
66 | qdev_set_nic_properties(mms->lan9118, nd); | 69 | DO_2OP(vrmulhub, 1, uint8_t, do_rmulh_b) |
67 | qdev_init_nofail(mms->lan9118); | 70 | DO_2OP(vrmulhuh, 2, uint16_t, do_rmulh_h) |
68 | 71 | DO_2OP(vrmulhuw, 4, uint32_t, do_rmulh_w) | |
69 | diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c | 72 | + |
73 | +#define DO_MAX(N, M) ((N) >= (M) ? (N) : (M)) | ||
74 | +#define DO_MIN(N, M) ((N) >= (M) ? (M) : (N)) | ||
75 | + | ||
76 | +DO_2OP_S(vmaxs, DO_MAX) | ||
77 | +DO_2OP_U(vmaxu, DO_MAX) | ||
78 | +DO_2OP_S(vmins, DO_MIN) | ||
79 | +DO_2OP_U(vminu, DO_MIN) | ||
80 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
70 | index XXXXXXX..XXXXXXX 100644 | 81 | index XXXXXXX..XXXXXXX 100644 |
71 | --- a/hw/net/lan9118.c | 82 | --- a/target/arm/translate-mve.c |
72 | +++ b/hw/net/lan9118.c | 83 | +++ b/target/arm/translate-mve.c |
73 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118_packet = { | 84 | @@ -XXX,XX +XXX,XX @@ DO_2OP(VMULH_S, vmulhs) |
74 | } | 85 | DO_2OP(VMULH_U, vmulhu) |
75 | }; | 86 | DO_2OP(VRMULH_S, vrmulhs) |
76 | 87 | DO_2OP(VRMULH_U, vrmulhu) | |
77 | -#define TYPE_LAN9118 "lan9118" | 88 | +DO_2OP(VMAX_S, vmaxs) |
78 | #define LAN9118(obj) OBJECT_CHECK(lan9118_state, (obj), TYPE_LAN9118) | 89 | +DO_2OP(VMAX_U, vmaxu) |
79 | 90 | +DO_2OP(VMIN_S, vmins) | |
80 | typedef struct { | 91 | +DO_2OP(VMIN_U, vminu) |
81 | -- | 92 | -- |
82 | 2.20.1 | 93 | 2.20.1 |
83 | 94 | ||
84 | 95 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | 1 | Implement the MVE VABD insn. |
---|---|---|---|
2 | 2 | ||
3 | Add an entries the Blizzard device in MAINTAINERS. | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20210617121628.20116-17-peter.maydell@linaro.org | ||
6 | --- | ||
7 | target/arm/helper-mve.h | 7 +++++++ | ||
8 | target/arm/mve.decode | 3 +++ | ||
9 | target/arm/mve_helper.c | 5 +++++ | ||
10 | target/arm/translate-mve.c | 2 ++ | ||
11 | 4 files changed, 17 insertions(+) | ||
4 | 12 | ||
5 | Reviewed-by: Thomas Huth <thuth@redhat.com> | 13 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
6 | Reviewed-by: Markus Armbruster <armbru@redhat.com> | ||
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
8 | Message-id: 20190412165416.7977-6-philmd@redhat.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | include/hw/devices.h | 7 ------- | ||
12 | include/hw/display/blizzard.h | 22 ++++++++++++++++++++++ | ||
13 | hw/arm/nseries.c | 1 + | ||
14 | hw/display/blizzard.c | 2 +- | ||
15 | MAINTAINERS | 2 ++ | ||
16 | 5 files changed, 26 insertions(+), 8 deletions(-) | ||
17 | create mode 100644 include/hw/display/blizzard.h | ||
18 | |||
19 | diff --git a/include/hw/devices.h b/include/hw/devices.h | ||
20 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/include/hw/devices.h | 15 | --- a/target/arm/helper-mve.h |
22 | +++ b/include/hw/devices.h | 16 | +++ b/target/arm/helper-mve.h |
23 | @@ -XXX,XX +XXX,XX @@ void tsc2005_set_transform(void *opaque, MouseTransformInfo *info); | 17 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vminsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
24 | /* stellaris_input.c */ | 18 | DEF_HELPER_FLAGS_4(mve_vminub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
25 | void stellaris_gamepad_init(int n, qemu_irq *irq, const int *keycode); | 19 | DEF_HELPER_FLAGS_4(mve_vminuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
26 | 20 | DEF_HELPER_FLAGS_4(mve_vminuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | |
27 | -/* blizzard.c */ | ||
28 | -void *s1d13745_init(qemu_irq gpio_int); | ||
29 | -void s1d13745_write(void *opaque, int dc, uint16_t value); | ||
30 | -void s1d13745_write_block(void *opaque, int dc, | ||
31 | - void *buf, size_t len, int pitch); | ||
32 | -uint16_t s1d13745_read(void *opaque, int dc); | ||
33 | - | ||
34 | /* cbus.c */ | ||
35 | typedef struct { | ||
36 | qemu_irq clk; | ||
37 | diff --git a/include/hw/display/blizzard.h b/include/hw/display/blizzard.h | ||
38 | new file mode 100644 | ||
39 | index XXXXXXX..XXXXXXX | ||
40 | --- /dev/null | ||
41 | +++ b/include/hw/display/blizzard.h | ||
42 | @@ -XXX,XX +XXX,XX @@ | ||
43 | +/* | ||
44 | + * Epson S1D13744/S1D13745 (Blizzard/Hailstorm/Tornado) LCD/TV controller. | ||
45 | + * | ||
46 | + * Copyright (C) 2008 Nokia Corporation | ||
47 | + * Written by Andrzej Zaborowski | ||
48 | + * | ||
49 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
50 | + * See the COPYING file in the top-level directory. | ||
51 | + */ | ||
52 | + | 21 | + |
53 | +#ifndef HW_DISPLAY_BLIZZARD_H | 22 | +DEF_HELPER_FLAGS_4(mve_vabdsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
54 | +#define HW_DISPLAY_BLIZZARD_H | 23 | +DEF_HELPER_FLAGS_4(mve_vabdsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
24 | +DEF_HELPER_FLAGS_4(mve_vabdsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
25 | +DEF_HELPER_FLAGS_4(mve_vabdub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
26 | +DEF_HELPER_FLAGS_4(mve_vabduh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
27 | +DEF_HELPER_FLAGS_4(mve_vabduw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
28 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/target/arm/mve.decode | ||
31 | +++ b/target/arm/mve.decode | ||
32 | @@ -XXX,XX +XXX,XX @@ VMAX_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 0 ... 0 @2op | ||
33 | VMIN_S 111 0 1111 0 . .. ... 0 ... 0 0110 . 1 . 1 ... 0 @2op | ||
34 | VMIN_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 1 ... 0 @2op | ||
35 | |||
36 | +VABD_S 111 0 1111 0 . .. ... 0 ... 0 0111 . 1 . 0 ... 0 @2op | ||
37 | +VABD_U 111 1 1111 0 . .. ... 0 ... 0 0111 . 1 . 0 ... 0 @2op | ||
55 | + | 38 | + |
56 | +#include "hw/irq.h" | 39 | # Vector miscellaneous |
40 | |||
41 | VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op | ||
42 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/target/arm/mve_helper.c | ||
45 | +++ b/target/arm/mve_helper.c | ||
46 | @@ -XXX,XX +XXX,XX @@ DO_2OP_S(vmaxs, DO_MAX) | ||
47 | DO_2OP_U(vmaxu, DO_MAX) | ||
48 | DO_2OP_S(vmins, DO_MIN) | ||
49 | DO_2OP_U(vminu, DO_MIN) | ||
57 | + | 50 | + |
58 | +void *s1d13745_init(qemu_irq gpio_int); | 51 | +#define DO_ABD(N, M) ((N) >= (M) ? (N) - (M) : (M) - (N)) |
59 | +void s1d13745_write(void *opaque, int dc, uint16_t value); | ||
60 | +void s1d13745_write_block(void *opaque, int dc, | ||
61 | + void *buf, size_t len, int pitch); | ||
62 | +uint16_t s1d13745_read(void *opaque, int dc); | ||
63 | + | 52 | + |
64 | +#endif | 53 | +DO_2OP_S(vabds, DO_ABD) |
65 | diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c | 54 | +DO_2OP_U(vabdu, DO_ABD) |
55 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
66 | index XXXXXXX..XXXXXXX 100644 | 56 | index XXXXXXX..XXXXXXX 100644 |
67 | --- a/hw/arm/nseries.c | 57 | --- a/target/arm/translate-mve.c |
68 | +++ b/hw/arm/nseries.c | 58 | +++ b/target/arm/translate-mve.c |
69 | @@ -XXX,XX +XXX,XX @@ | 59 | @@ -XXX,XX +XXX,XX @@ DO_2OP(VMAX_S, vmaxs) |
70 | #include "hw/boards.h" | 60 | DO_2OP(VMAX_U, vmaxu) |
71 | #include "hw/i2c/i2c.h" | 61 | DO_2OP(VMIN_S, vmins) |
72 | #include "hw/devices.h" | 62 | DO_2OP(VMIN_U, vminu) |
73 | +#include "hw/display/blizzard.h" | 63 | +DO_2OP(VABD_S, vabds) |
74 | #include "hw/misc/tmp105.h" | 64 | +DO_2OP(VABD_U, vabdu) |
75 | #include "hw/block/flash.h" | ||
76 | #include "hw/hw.h" | ||
77 | diff --git a/hw/display/blizzard.c b/hw/display/blizzard.c | ||
78 | index XXXXXXX..XXXXXXX 100644 | ||
79 | --- a/hw/display/blizzard.c | ||
80 | +++ b/hw/display/blizzard.c | ||
81 | @@ -XXX,XX +XXX,XX @@ | ||
82 | #include "qemu/osdep.h" | ||
83 | #include "qemu-common.h" | ||
84 | #include "ui/console.h" | ||
85 | -#include "hw/devices.h" | ||
86 | +#include "hw/display/blizzard.h" | ||
87 | #include "ui/pixel_ops.h" | ||
88 | |||
89 | typedef void (*blizzard_fn_t)(uint8_t *, const uint8_t *, unsigned int); | ||
90 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
91 | index XXXXXXX..XXXXXXX 100644 | ||
92 | --- a/MAINTAINERS | ||
93 | +++ b/MAINTAINERS | ||
94 | @@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org> | ||
95 | L: qemu-arm@nongnu.org | ||
96 | S: Odd Fixes | ||
97 | F: hw/arm/nseries.c | ||
98 | +F: hw/display/blizzard.c | ||
99 | F: hw/input/lm832x.c | ||
100 | F: hw/input/tsc2005.c | ||
101 | F: hw/misc/cbus.c | ||
102 | F: hw/timer/twl92230.c | ||
103 | +F: include/hw/display/blizzard.h | ||
104 | |||
105 | Palm | ||
106 | M: Andrzej Zaborowski <balrogg@gmail.com> | ||
107 | -- | 65 | -- |
108 | 2.20.1 | 66 | 2.20.1 |
109 | 67 | ||
110 | 68 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | 1 | Implement MVE VHADD and VHSUB insns, which perform an addition |
---|---|---|---|
2 | or subtraction and then halve the result. | ||
2 | 3 | ||
3 | This device is used by both ARM (BCM2836, for raspi2) and AArch64 | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | (BCM2837, for raspi3) targets, and is not CPU-specific. | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Move it to common object, so we build it once for all targets. | 6 | Message-id: 20210617121628.20116-18-peter.maydell@linaro.org |
7 | --- | ||
8 | target/arm/helper-mve.h | 14 ++++++++++++++ | ||
9 | target/arm/mve.decode | 5 +++++ | ||
10 | target/arm/mve_helper.c | 25 +++++++++++++++++++++++++ | ||
11 | target/arm/translate-mve.c | 4 ++++ | ||
12 | 4 files changed, 48 insertions(+) | ||
6 | 13 | ||
7 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 14 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
8 | Message-id: 20190427133028.12874-1-philmd@redhat.com | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | --- | ||
12 | hw/dma/Makefile.objs | 2 +- | ||
13 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
14 | |||
15 | diff --git a/hw/dma/Makefile.objs b/hw/dma/Makefile.objs | ||
16 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/dma/Makefile.objs | 16 | --- a/target/arm/helper-mve.h |
18 | +++ b/hw/dma/Makefile.objs | 17 | +++ b/target/arm/helper-mve.h |
19 | @@ -XXX,XX +XXX,XX @@ common-obj-$(CONFIG_XLNX_ZYNQMP_ARM) += xlnx-zdma.o | 18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vabdsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
20 | 19 | DEF_HELPER_FLAGS_4(mve_vabdub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | |
21 | obj-$(CONFIG_OMAP) += omap_dma.o soc_dma.o | 20 | DEF_HELPER_FLAGS_4(mve_vabduh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
22 | obj-$(CONFIG_PXA2XX) += pxa2xx_dma.o | 21 | DEF_HELPER_FLAGS_4(mve_vabduw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
23 | -obj-$(CONFIG_RASPI) += bcm2835_dma.o | 22 | + |
24 | +common-obj-$(CONFIG_RASPI) += bcm2835_dma.o | 23 | +DEF_HELPER_FLAGS_4(mve_vhaddsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
24 | +DEF_HELPER_FLAGS_4(mve_vhaddsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
25 | +DEF_HELPER_FLAGS_4(mve_vhaddsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
26 | +DEF_HELPER_FLAGS_4(mve_vhaddub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
27 | +DEF_HELPER_FLAGS_4(mve_vhadduh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
28 | +DEF_HELPER_FLAGS_4(mve_vhadduw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
29 | + | ||
30 | +DEF_HELPER_FLAGS_4(mve_vhsubsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
31 | +DEF_HELPER_FLAGS_4(mve_vhsubsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
32 | +DEF_HELPER_FLAGS_4(mve_vhsubsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
33 | +DEF_HELPER_FLAGS_4(mve_vhsubub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
34 | +DEF_HELPER_FLAGS_4(mve_vhsubuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
35 | +DEF_HELPER_FLAGS_4(mve_vhsubuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
36 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/target/arm/mve.decode | ||
39 | +++ b/target/arm/mve.decode | ||
40 | @@ -XXX,XX +XXX,XX @@ VMIN_U 111 1 1111 0 . .. ... 0 ... 0 0110 . 1 . 1 ... 0 @2op | ||
41 | VABD_S 111 0 1111 0 . .. ... 0 ... 0 0111 . 1 . 0 ... 0 @2op | ||
42 | VABD_U 111 1 1111 0 . .. ... 0 ... 0 0111 . 1 . 0 ... 0 @2op | ||
43 | |||
44 | +VHADD_S 111 0 1111 0 . .. ... 0 ... 0 0000 . 1 . 0 ... 0 @2op | ||
45 | +VHADD_U 111 1 1111 0 . .. ... 0 ... 0 0000 . 1 . 0 ... 0 @2op | ||
46 | +VHSUB_S 111 0 1111 0 . .. ... 0 ... 0 0010 . 1 . 0 ... 0 @2op | ||
47 | +VHSUB_U 111 1 1111 0 . .. ... 0 ... 0 0010 . 1 . 0 ... 0 @2op | ||
48 | + | ||
49 | # Vector miscellaneous | ||
50 | |||
51 | VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op | ||
52 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
53 | index XXXXXXX..XXXXXXX 100644 | ||
54 | --- a/target/arm/mve_helper.c | ||
55 | +++ b/target/arm/mve_helper.c | ||
56 | @@ -XXX,XX +XXX,XX @@ DO_2OP_U(vminu, DO_MIN) | ||
57 | |||
58 | DO_2OP_S(vabds, DO_ABD) | ||
59 | DO_2OP_U(vabdu, DO_ABD) | ||
60 | + | ||
61 | +static inline uint32_t do_vhadd_u(uint32_t n, uint32_t m) | ||
62 | +{ | ||
63 | + return ((uint64_t)n + m) >> 1; | ||
64 | +} | ||
65 | + | ||
66 | +static inline int32_t do_vhadd_s(int32_t n, int32_t m) | ||
67 | +{ | ||
68 | + return ((int64_t)n + m) >> 1; | ||
69 | +} | ||
70 | + | ||
71 | +static inline uint32_t do_vhsub_u(uint32_t n, uint32_t m) | ||
72 | +{ | ||
73 | + return ((uint64_t)n - m) >> 1; | ||
74 | +} | ||
75 | + | ||
76 | +static inline int32_t do_vhsub_s(int32_t n, int32_t m) | ||
77 | +{ | ||
78 | + return ((int64_t)n - m) >> 1; | ||
79 | +} | ||
80 | + | ||
81 | +DO_2OP_S(vhadds, do_vhadd_s) | ||
82 | +DO_2OP_U(vhaddu, do_vhadd_u) | ||
83 | +DO_2OP_S(vhsubs, do_vhsub_s) | ||
84 | +DO_2OP_U(vhsubu, do_vhsub_u) | ||
85 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
86 | index XXXXXXX..XXXXXXX 100644 | ||
87 | --- a/target/arm/translate-mve.c | ||
88 | +++ b/target/arm/translate-mve.c | ||
89 | @@ -XXX,XX +XXX,XX @@ DO_2OP(VMIN_S, vmins) | ||
90 | DO_2OP(VMIN_U, vminu) | ||
91 | DO_2OP(VABD_S, vabds) | ||
92 | DO_2OP(VABD_U, vabdu) | ||
93 | +DO_2OP(VHADD_S, vhadds) | ||
94 | +DO_2OP(VHADD_U, vhaddu) | ||
95 | +DO_2OP(VHSUB_S, vhsubs) | ||
96 | +DO_2OP(VHSUB_U, vhsubu) | ||
25 | -- | 97 | -- |
26 | 2.20.1 | 98 | 2.20.1 |
27 | 99 | ||
28 | 100 | diff view generated by jsdifflib |
1 | The TailChain() pseudocode specifies that a tail chaining | 1 | Implement the MVE VMULL insn, which multiplies two single |
---|---|---|---|
2 | exception should sanitize the excReturn all-ones bits and | 2 | width integer elements to produce a double width result. |
3 | (if there is no FPU) the excReturn FType bits; we weren't | ||
4 | doing this. | ||
5 | 3 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20190416125744.27770-14-peter.maydell@linaro.org | 6 | Message-id: 20210617121628.20116-19-peter.maydell@linaro.org |
9 | --- | 7 | --- |
10 | target/arm/helper.c | 8 ++++++++ | 8 | target/arm/helper-mve.h | 14 ++++++++++++++ |
11 | 1 file changed, 8 insertions(+) | 9 | target/arm/mve.decode | 5 +++++ |
10 | target/arm/mve_helper.c | 34 ++++++++++++++++++++++++++++++++++ | ||
11 | target/arm/translate-mve.c | 4 ++++ | ||
12 | 4 files changed, 57 insertions(+) | ||
12 | 13 | ||
13 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 14 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
14 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/helper.c | 16 | --- a/target/arm/helper-mve.h |
16 | +++ b/target/arm/helper.c | 17 | +++ b/target/arm/helper-mve.h |
17 | @@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain, | 18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vhsubsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
18 | qemu_log_mask(CPU_LOG_INT, "...taking pending %s exception %d\n", | 19 | DEF_HELPER_FLAGS_4(mve_vhsubub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
19 | targets_secure ? "secure" : "nonsecure", exc); | 20 | DEF_HELPER_FLAGS_4(mve_vhsubuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
20 | 21 | DEF_HELPER_FLAGS_4(mve_vhsubuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | |
21 | + if (dotailchain) { | 22 | + |
22 | + /* Sanitize LR FType and PREFIX bits */ | 23 | +DEF_HELPER_FLAGS_4(mve_vmullbsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
23 | + if (!arm_feature(env, ARM_FEATURE_VFP)) { | 24 | +DEF_HELPER_FLAGS_4(mve_vmullbsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
24 | + lr |= R_V7M_EXCRET_FTYPE_MASK; | 25 | +DEF_HELPER_FLAGS_4(mve_vmullbsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
25 | + } | 26 | +DEF_HELPER_FLAGS_4(mve_vmullbub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
26 | + lr = deposit32(lr, 24, 8, 0xff); | 27 | +DEF_HELPER_FLAGS_4(mve_vmullbuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
28 | +DEF_HELPER_FLAGS_4(mve_vmullbuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
29 | + | ||
30 | +DEF_HELPER_FLAGS_4(mve_vmulltsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
31 | +DEF_HELPER_FLAGS_4(mve_vmulltsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
32 | +DEF_HELPER_FLAGS_4(mve_vmulltsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
33 | +DEF_HELPER_FLAGS_4(mve_vmulltub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
34 | +DEF_HELPER_FLAGS_4(mve_vmulltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
35 | +DEF_HELPER_FLAGS_4(mve_vmulltuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
36 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
37 | index XXXXXXX..XXXXXXX 100644 | ||
38 | --- a/target/arm/mve.decode | ||
39 | +++ b/target/arm/mve.decode | ||
40 | @@ -XXX,XX +XXX,XX @@ VHADD_U 111 1 1111 0 . .. ... 0 ... 0 0000 . 1 . 0 ... 0 @2op | ||
41 | VHSUB_S 111 0 1111 0 . .. ... 0 ... 0 0010 . 1 . 0 ... 0 @2op | ||
42 | VHSUB_U 111 1 1111 0 . .. ... 0 ... 0 0010 . 1 . 0 ... 0 @2op | ||
43 | |||
44 | +VMULL_BS 111 0 1110 0 . .. ... 1 ... 0 1110 . 0 . 0 ... 0 @2op | ||
45 | +VMULL_BU 111 1 1110 0 . .. ... 1 ... 0 1110 . 0 . 0 ... 0 @2op | ||
46 | +VMULL_TS 111 0 1110 0 . .. ... 1 ... 1 1110 . 0 . 0 ... 0 @2op | ||
47 | +VMULL_TU 111 1 1110 0 . .. ... 1 ... 1 1110 . 0 . 0 ... 0 @2op | ||
48 | + | ||
49 | # Vector miscellaneous | ||
50 | |||
51 | VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op | ||
52 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
53 | index XXXXXXX..XXXXXXX 100644 | ||
54 | --- a/target/arm/mve_helper.c | ||
55 | +++ b/target/arm/mve_helper.c | ||
56 | @@ -XXX,XX +XXX,XX @@ DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS) | ||
57 | DO_2OP(OP##h, 2, int16_t, FN) \ | ||
58 | DO_2OP(OP##w, 4, int32_t, FN) | ||
59 | |||
60 | +/* | ||
61 | + * "Long" operations where two half-sized inputs (taken from either the | ||
62 | + * top or the bottom of the input vector) produce a double-width result. | ||
63 | + * Here ESIZE, TYPE are for the input, and LESIZE, LTYPE for the output. | ||
64 | + */ | ||
65 | +#define DO_2OP_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN) \ | ||
66 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ | ||
67 | + { \ | ||
68 | + LTYPE *d = vd; \ | ||
69 | + TYPE *n = vn, *m = vm; \ | ||
70 | + uint16_t mask = mve_element_mask(env); \ | ||
71 | + unsigned le; \ | ||
72 | + for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ | ||
73 | + LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)], \ | ||
74 | + m[H##ESIZE(le * 2 + TOP)]); \ | ||
75 | + mergemask(&d[H##LESIZE(le)], r, mask); \ | ||
76 | + } \ | ||
77 | + mve_advance_vpt(env); \ | ||
27 | + } | 78 | + } |
28 | + | 79 | + |
29 | if (arm_feature(env, ARM_FEATURE_V8)) { | 80 | #define DO_AND(N, M) ((N) & (M)) |
30 | if (arm_feature(env, ARM_FEATURE_M_SECURITY) && | 81 | #define DO_BIC(N, M) ((N) & ~(M)) |
31 | (lr & R_V7M_EXCRET_S_MASK)) { | 82 | #define DO_ORR(N, M) ((N) | (M)) |
83 | @@ -XXX,XX +XXX,XX @@ DO_2OP_U(vadd, DO_ADD) | ||
84 | DO_2OP_U(vsub, DO_SUB) | ||
85 | DO_2OP_U(vmul, DO_MUL) | ||
86 | |||
87 | +DO_2OP_L(vmullbsb, 0, 1, int8_t, 2, int16_t, DO_MUL) | ||
88 | +DO_2OP_L(vmullbsh, 0, 2, int16_t, 4, int32_t, DO_MUL) | ||
89 | +DO_2OP_L(vmullbsw, 0, 4, int32_t, 8, int64_t, DO_MUL) | ||
90 | +DO_2OP_L(vmullbub, 0, 1, uint8_t, 2, uint16_t, DO_MUL) | ||
91 | +DO_2OP_L(vmullbuh, 0, 2, uint16_t, 4, uint32_t, DO_MUL) | ||
92 | +DO_2OP_L(vmullbuw, 0, 4, uint32_t, 8, uint64_t, DO_MUL) | ||
93 | + | ||
94 | +DO_2OP_L(vmulltsb, 1, 1, int8_t, 2, int16_t, DO_MUL) | ||
95 | +DO_2OP_L(vmulltsh, 1, 2, int16_t, 4, int32_t, DO_MUL) | ||
96 | +DO_2OP_L(vmulltsw, 1, 4, int32_t, 8, int64_t, DO_MUL) | ||
97 | +DO_2OP_L(vmulltub, 1, 1, uint8_t, 2, uint16_t, DO_MUL) | ||
98 | +DO_2OP_L(vmulltuh, 1, 2, uint16_t, 4, uint32_t, DO_MUL) | ||
99 | +DO_2OP_L(vmulltuw, 1, 4, uint32_t, 8, uint64_t, DO_MUL) | ||
100 | + | ||
101 | /* | ||
102 | * Because the computation type is at least twice as large as required, | ||
103 | * these work for both signed and unsigned source types. | ||
104 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
105 | index XXXXXXX..XXXXXXX 100644 | ||
106 | --- a/target/arm/translate-mve.c | ||
107 | +++ b/target/arm/translate-mve.c | ||
108 | @@ -XXX,XX +XXX,XX @@ DO_2OP(VHADD_S, vhadds) | ||
109 | DO_2OP(VHADD_U, vhaddu) | ||
110 | DO_2OP(VHSUB_S, vhsubs) | ||
111 | DO_2OP(VHSUB_U, vhsubu) | ||
112 | +DO_2OP(VMULL_BS, vmullbs) | ||
113 | +DO_2OP(VMULL_BU, vmullbu) | ||
114 | +DO_2OP(VMULL_TS, vmullts) | ||
115 | +DO_2OP(VMULL_TU, vmulltu) | ||
32 | -- | 116 | -- |
33 | 2.20.1 | 117 | 2.20.1 |
34 | 118 | ||
35 | 119 | diff view generated by jsdifflib |
1 | The M-profile architecture floating point system supports | 1 | Implement the MVE VMLALDAV insn, which multiplies pairs of integer |
---|---|---|---|
2 | lazy FP state preservation, where FP registers are not | 2 | elements, accumulating them into a 64-bit result in a pair of |
3 | pushed to the stack when an exception occurs but are instead | 3 | general-purpose registers. |
4 | only saved if and when the first FP instruction in the exception | ||
5 | handler is executed. Implement this in QEMU, corresponding | ||
6 | to the check of LSPACT in the pseudocode ExecuteFPCheck(). | ||
7 | 4 | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
10 | Message-id: 20190416125744.27770-24-peter.maydell@linaro.org | 7 | Message-id: 20210617121628.20116-20-peter.maydell@linaro.org |
11 | --- | 8 | --- |
12 | target/arm/cpu.h | 3 ++ | 9 | target/arm/helper-mve.h | 8 ++++ |
13 | target/arm/helper.h | 2 + | 10 | target/arm/translate.h | 10 ++++ |
14 | target/arm/translate.h | 1 + | 11 | target/arm/mve.decode | 15 ++++++ |
15 | target/arm/helper.c | 112 +++++++++++++++++++++++++++++++++++++++++ | 12 | target/arm/mve_helper.c | 34 ++++++++++++++ |
16 | target/arm/translate.c | 22 ++++++++ | 13 | target/arm/translate-mve.c | 96 ++++++++++++++++++++++++++++++++++++++ |
17 | 5 files changed, 140 insertions(+) | 14 | 5 files changed, 163 insertions(+) |
18 | 15 | ||
19 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 16 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
20 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
21 | --- a/target/arm/cpu.h | 18 | --- a/target/arm/helper-mve.h |
22 | +++ b/target/arm/cpu.h | 19 | +++ b/target/arm/helper-mve.h |
23 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vmulltsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
24 | #define EXCP_NOCP 17 /* v7M NOCP UsageFault */ | 21 | DEF_HELPER_FLAGS_4(mve_vmulltub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
25 | #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ | 22 | DEF_HELPER_FLAGS_4(mve_vmulltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
26 | #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ | 23 | DEF_HELPER_FLAGS_4(mve_vmulltuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
27 | +#define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ | 24 | + |
28 | /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ | 25 | +DEF_HELPER_FLAGS_4(mve_vmlaldavsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
29 | 26 | +DEF_HELPER_FLAGS_4(mve_vmlaldavsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) | |
30 | #define ARMV7M_EXCP_RESET 1 | 27 | +DEF_HELPER_FLAGS_4(mve_vmlaldavxsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
31 | @@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A32, NS, 6, 1) | 28 | +DEF_HELPER_FLAGS_4(mve_vmlaldavxsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
32 | FIELD(TBFLAG_A32, VFPEN, 7, 1) | 29 | + |
33 | FIELD(TBFLAG_A32, CONDEXEC, 8, 8) | 30 | +DEF_HELPER_FLAGS_4(mve_vmlaldavuh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
34 | FIELD(TBFLAG_A32, SCTLR_B, 16, 1) | 31 | +DEF_HELPER_FLAGS_4(mve_vmlaldavuw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
35 | +/* For M profile only, set if FPCCR.LSPACT is set */ | ||
36 | +FIELD(TBFLAG_A32, LSPACT, 18, 1) | ||
37 | /* For M profile only, set if we must create a new FP context */ | ||
38 | FIELD(TBFLAG_A32, NEW_FP_CTXT_NEEDED, 19, 1) | ||
39 | /* For M profile only, set if FPCCR.S does not match current security state */ | ||
40 | diff --git a/target/arm/helper.h b/target/arm/helper.h | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/target/arm/helper.h | ||
43 | +++ b/target/arm/helper.h | ||
44 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(v7m_blxns, void, env, i32) | ||
45 | |||
46 | DEF_HELPER_3(v7m_tt, i32, env, i32, i32) | ||
47 | |||
48 | +DEF_HELPER_1(v7m_preserve_fp_state, void, env) | ||
49 | + | ||
50 | DEF_HELPER_2(v8m_stackcheck, void, env, i32) | ||
51 | |||
52 | DEF_HELPER_4(access_check_cp_reg, void, env, ptr, i32, i32) | ||
53 | diff --git a/target/arm/translate.h b/target/arm/translate.h | 32 | diff --git a/target/arm/translate.h b/target/arm/translate.h |
54 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
55 | --- a/target/arm/translate.h | 34 | --- a/target/arm/translate.h |
56 | +++ b/target/arm/translate.h | 35 | +++ b/target/arm/translate.h |
57 | @@ -XXX,XX +XXX,XX @@ typedef struct DisasContext { | 36 | @@ -XXX,XX +XXX,XX @@ static inline int negate(DisasContext *s, int x) |
58 | bool v8m_stackcheck; /* true if we need to perform v8M stack limit checks */ | 37 | return -x; |
59 | bool v8m_fpccr_s_wrong; /* true if v8M FPCCR.S != v8m_secure */ | ||
60 | bool v7m_new_fp_ctxt_needed; /* ASPEN set but no active FP context */ | ||
61 | + bool v7m_lspact; /* FPCCR.LSPACT set */ | ||
62 | /* Immediate value in AArch32 SVC insn; must be set if is_jmp == DISAS_SWI | ||
63 | * so that top level loop can generate correct syndrome information. | ||
64 | */ | ||
65 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
66 | index XXXXXXX..XXXXXXX 100644 | ||
67 | --- a/target/arm/helper.c | ||
68 | +++ b/target/arm/helper.c | ||
69 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) | ||
70 | g_assert_not_reached(); | ||
71 | } | 38 | } |
72 | 39 | ||
73 | +void HELPER(v7m_preserve_fp_state)(CPUARMState *env) | 40 | +static inline int plus_1(DisasContext *s, int x) |
74 | +{ | 41 | +{ |
75 | + /* translate.c should never generate calls here in user-only mode */ | 42 | + return x + 1; |
76 | + g_assert_not_reached(); | 43 | +} |
77 | +} | 44 | + |
78 | + | 45 | static inline int plus_2(DisasContext *s, int x) |
79 | uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) | ||
80 | { | 46 | { |
81 | /* The TT instructions can be used by unprivileged code, but in | 47 | return x + 2; |
82 | @@ -XXX,XX +XXX,XX @@ pend_fault: | 48 | @@ -XXX,XX +XXX,XX @@ static inline int times_4(DisasContext *s, int x) |
83 | return false; | 49 | return x * 4; |
84 | } | 50 | } |
85 | 51 | ||
86 | +void HELPER(v7m_preserve_fp_state)(CPUARMState *env) | 52 | +static inline int times_2_plus_1(DisasContext *s, int x) |
87 | +{ | 53 | +{ |
54 | + return x * 2 + 1; | ||
55 | +} | ||
56 | + | ||
57 | static inline int arm_dc_feature(DisasContext *dc, int feature) | ||
58 | { | ||
59 | return (dc->features & (1ULL << feature)) != 0; | ||
60 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
61 | index XXXXXXX..XXXXXXX 100644 | ||
62 | --- a/target/arm/mve.decode | ||
63 | +++ b/target/arm/mve.decode | ||
64 | @@ -XXX,XX +XXX,XX @@ VNEG_fp 1111 1111 1 . 11 .. 01 ... 0 0111 11 . 0 ... 0 @1op | ||
65 | VDUP 1110 1110 1 1 10 ... 0 .... 1011 . 0 0 1 0000 @vdup size=0 | ||
66 | VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0 1 1 0000 @vdup size=1 | ||
67 | VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0 0 1 0000 @vdup size=2 | ||
68 | + | ||
69 | +# multiply-add long dual accumulate | ||
70 | +# rdahi: bits [3:1] from insn, bit 0 is 1 | ||
71 | +# rdalo: bits [3:1] from insn, bit 0 is 0 | ||
72 | +%rdahi 20:3 !function=times_2_plus_1 | ||
73 | +%rdalo 13:3 !function=times_2 | ||
74 | +# size bit is 0 for 16 bit, 1 for 32 bit | ||
75 | +%size_16 16:1 !function=plus_1 | ||
76 | + | ||
77 | +&vmlaldav rdahi rdalo size qn qm x a | ||
78 | + | ||
79 | +@vmlaldav .... .... . ... ... . ... . .... .... qm:3 . \ | ||
80 | + qn=%qn rdahi=%rdahi rdalo=%rdalo size=%size_16 &vmlaldav | ||
81 | +VMLALDAV_S 1110 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 0 @vmlaldav | ||
82 | +VMLALDAV_U 1111 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 0 @vmlaldav | ||
83 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
84 | index XXXXXXX..XXXXXXX 100644 | ||
85 | --- a/target/arm/mve_helper.c | ||
86 | +++ b/target/arm/mve_helper.c | ||
87 | @@ -XXX,XX +XXX,XX @@ DO_2OP_S(vhadds, do_vhadd_s) | ||
88 | DO_2OP_U(vhaddu, do_vhadd_u) | ||
89 | DO_2OP_S(vhsubs, do_vhsub_s) | ||
90 | DO_2OP_U(vhsubu, do_vhsub_u) | ||
91 | + | ||
92 | + | ||
93 | +/* | ||
94 | + * Multiply add long dual accumulate ops. | ||
95 | + */ | ||
96 | +#define DO_LDAV(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC) \ | ||
97 | + uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ | ||
98 | + void *vm, uint64_t a) \ | ||
99 | + { \ | ||
100 | + uint16_t mask = mve_element_mask(env); \ | ||
101 | + unsigned e; \ | ||
102 | + TYPE *n = vn, *m = vm; \ | ||
103 | + for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ | ||
104 | + if (mask & 1) { \ | ||
105 | + if (e & 1) { \ | ||
106 | + a ODDACC \ | ||
107 | + (int64_t)n[H##ESIZE(e - 1 * XCHG)] * m[H##ESIZE(e)]; \ | ||
108 | + } else { \ | ||
109 | + a EVENACC \ | ||
110 | + (int64_t)n[H##ESIZE(e + 1 * XCHG)] * m[H##ESIZE(e)]; \ | ||
111 | + } \ | ||
112 | + } \ | ||
113 | + } \ | ||
114 | + mve_advance_vpt(env); \ | ||
115 | + return a; \ | ||
116 | + } | ||
117 | + | ||
118 | +DO_LDAV(vmlaldavsh, 2, int16_t, false, +=, +=) | ||
119 | +DO_LDAV(vmlaldavxsh, 2, int16_t, true, +=, +=) | ||
120 | +DO_LDAV(vmlaldavsw, 4, int32_t, false, +=, +=) | ||
121 | +DO_LDAV(vmlaldavxsw, 4, int32_t, true, +=, +=) | ||
122 | + | ||
123 | +DO_LDAV(vmlaldavuh, 2, uint16_t, false, +=, +=) | ||
124 | +DO_LDAV(vmlaldavuw, 4, uint32_t, false, +=, +=) | ||
125 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
126 | index XXXXXXX..XXXXXXX 100644 | ||
127 | --- a/target/arm/translate-mve.c | ||
128 | +++ b/target/arm/translate-mve.c | ||
129 | @@ -XXX,XX +XXX,XX @@ | ||
130 | typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
131 | typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
132 | typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr); | ||
133 | +typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64); | ||
134 | |||
135 | /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */ | ||
136 | static inline long mve_qreg_offset(unsigned reg) | ||
137 | @@ -XXX,XX +XXX,XX @@ static void mve_update_eci(DisasContext *s) | ||
138 | } | ||
139 | } | ||
140 | |||
141 | +static bool mve_skip_first_beat(DisasContext *s) | ||
142 | +{ | ||
143 | + /* Return true if PSR.ECI says we must skip the first beat of this insn */ | ||
144 | + switch (s->eci) { | ||
145 | + case ECI_NONE: | ||
146 | + return false; | ||
147 | + case ECI_A0: | ||
148 | + case ECI_A0A1: | ||
149 | + case ECI_A0A1A2: | ||
150 | + case ECI_A0A1A2B0: | ||
151 | + return true; | ||
152 | + default: | ||
153 | + g_assert_not_reached(); | ||
154 | + } | ||
155 | +} | ||
156 | + | ||
157 | static bool do_ldst(DisasContext *s, arg_VLDR_VSTR *a, MVEGenLdStFn *fn) | ||
158 | { | ||
159 | TCGv_i32 addr; | ||
160 | @@ -XXX,XX +XXX,XX @@ DO_2OP(VMULL_BS, vmullbs) | ||
161 | DO_2OP(VMULL_BU, vmullbu) | ||
162 | DO_2OP(VMULL_TS, vmullts) | ||
163 | DO_2OP(VMULL_TU, vmulltu) | ||
164 | + | ||
165 | +static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, | ||
166 | + MVEGenDualAccOpFn *fn) | ||
167 | +{ | ||
168 | + TCGv_ptr qn, qm; | ||
169 | + TCGv_i64 rda; | ||
170 | + TCGv_i32 rdalo, rdahi; | ||
171 | + | ||
172 | + if (!dc_isar_feature(aa32_mve, s) || | ||
173 | + !mve_check_qreg_bank(s, a->qn | a->qm) || | ||
174 | + !fn) { | ||
175 | + return false; | ||
176 | + } | ||
88 | + /* | 177 | + /* |
89 | + * Preserve FP state (because LSPACT was set and we are about | 178 | + * rdahi == 13 is UNPREDICTABLE; rdahi == 15 is a related |
90 | + * to execute an FP instruction). This corresponds to the | 179 | + * encoding; rdalo always has bit 0 clear so cannot be 13 or 15. |
91 | + * PreserveFPState() pseudocode. | ||
92 | + * We may throw an exception if the stacking fails. | ||
93 | + */ | 180 | + */ |
94 | + ARMCPU *cpu = arm_env_get_cpu(env); | 181 | + if (a->rdahi == 13 || a->rdahi == 15) { |
95 | + bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; | 182 | + return false; |
96 | + bool negpri = !(env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_HFRDY_MASK); | 183 | + } |
97 | + bool is_priv = !(env->v7m.fpccr[is_secure] & R_V7M_FPCCR_USER_MASK); | 184 | + if (!mve_eci_check(s) || !vfp_access_check(s)) { |
98 | + bool splimviol = env->v7m.fpccr[is_secure] & R_V7M_FPCCR_SPLIMVIOL_MASK; | 185 | + return true; |
99 | + uint32_t fpcar = env->v7m.fpcar[is_secure]; | 186 | + } |
100 | + bool stacked_ok = true; | 187 | + |
101 | + bool ts = is_secure && (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MASK); | 188 | + qn = mve_qreg_ptr(a->qn); |
102 | + bool take_exception; | 189 | + qm = mve_qreg_ptr(a->qm); |
103 | + | ||
104 | + /* Take the iothread lock as we are going to touch the NVIC */ | ||
105 | + qemu_mutex_lock_iothread(); | ||
106 | + | ||
107 | + /* Check the background context had access to the FPU */ | ||
108 | + if (!v7m_cpacr_pass(env, is_secure, is_priv)) { | ||
109 | + armv7m_nvic_set_pending_lazyfp(env->nvic, ARMV7M_EXCP_USAGE, is_secure); | ||
110 | + env->v7m.cfsr[is_secure] |= R_V7M_CFSR_NOCP_MASK; | ||
111 | + stacked_ok = false; | ||
112 | + } else if (!is_secure && !extract32(env->v7m.nsacr, 10, 1)) { | ||
113 | + armv7m_nvic_set_pending_lazyfp(env->nvic, ARMV7M_EXCP_USAGE, M_REG_S); | ||
114 | + env->v7m.cfsr[M_REG_S] |= R_V7M_CFSR_NOCP_MASK; | ||
115 | + stacked_ok = false; | ||
116 | + } | ||
117 | + | ||
118 | + if (!splimviol && stacked_ok) { | ||
119 | + /* We only stack if the stack limit wasn't violated */ | ||
120 | + int i; | ||
121 | + ARMMMUIdx mmu_idx; | ||
122 | + | ||
123 | + mmu_idx = arm_v7m_mmu_idx_all(env, is_secure, is_priv, negpri); | ||
124 | + for (i = 0; i < (ts ? 32 : 16); i += 2) { | ||
125 | + uint64_t dn = *aa32_vfp_dreg(env, i / 2); | ||
126 | + uint32_t faddr = fpcar + 4 * i; | ||
127 | + uint32_t slo = extract64(dn, 0, 32); | ||
128 | + uint32_t shi = extract64(dn, 32, 32); | ||
129 | + | ||
130 | + if (i >= 16) { | ||
131 | + faddr += 8; /* skip the slot for the FPSCR */ | ||
132 | + } | ||
133 | + stacked_ok = stacked_ok && | ||
134 | + v7m_stack_write(cpu, faddr, slo, mmu_idx, STACK_LAZYFP) && | ||
135 | + v7m_stack_write(cpu, faddr + 4, shi, mmu_idx, STACK_LAZYFP); | ||
136 | + } | ||
137 | + | ||
138 | + stacked_ok = stacked_ok && | ||
139 | + v7m_stack_write(cpu, fpcar + 0x40, | ||
140 | + vfp_get_fpscr(env), mmu_idx, STACK_LAZYFP); | ||
141 | + } | ||
142 | + | 190 | + |
143 | + /* | 191 | + /* |
144 | + * We definitely pended an exception, but it's possible that it | 192 | + * This insn is subject to beat-wise execution. Partial execution |
145 | + * might not be able to be taken now. If its priority permits us | 193 | + * of an A=0 (no-accumulate) insn which does not execute the first |
146 | + * to take it now, then we must not update the LSPACT or FP regs, | 194 | + * beat must start with the current rda value, not 0. |
147 | + * but instead jump out to take the exception immediately. | ||
148 | + * If it's just pending and won't be taken until the current | ||
149 | + * handler exits, then we do update LSPACT and the FP regs. | ||
150 | + */ | 195 | + */ |
151 | + take_exception = !stacked_ok && | 196 | + if (a->a || mve_skip_first_beat(s)) { |
152 | + armv7m_nvic_can_take_pending_exception(env->nvic); | 197 | + rda = tcg_temp_new_i64(); |
153 | + | 198 | + rdalo = load_reg(s, a->rdalo); |
154 | + qemu_mutex_unlock_iothread(); | 199 | + rdahi = load_reg(s, a->rdahi); |
155 | + | 200 | + tcg_gen_concat_i32_i64(rda, rdalo, rdahi); |
156 | + if (take_exception) { | 201 | + tcg_temp_free_i32(rdalo); |
157 | + raise_exception_ra(env, EXCP_LAZYFP, 0, 1, GETPC()); | 202 | + tcg_temp_free_i32(rdahi); |
158 | + } | 203 | + } else { |
159 | + | 204 | + rda = tcg_const_i64(0); |
160 | + env->v7m.fpccr[is_secure] &= ~R_V7M_FPCCR_LSPACT_MASK; | 205 | + } |
161 | + | 206 | + |
162 | + if (ts) { | 207 | + fn(rda, cpu_env, qn, qm, rda); |
163 | + /* Clear s0 to s31 and the FPSCR */ | 208 | + tcg_temp_free_ptr(qn); |
164 | + int i; | 209 | + tcg_temp_free_ptr(qm); |
165 | + | 210 | + |
166 | + for (i = 0; i < 32; i += 2) { | 211 | + rdalo = tcg_temp_new_i32(); |
167 | + *aa32_vfp_dreg(env, i / 2) = 0; | 212 | + rdahi = tcg_temp_new_i32(); |
168 | + } | 213 | + tcg_gen_extrl_i64_i32(rdalo, rda); |
169 | + vfp_set_fpscr(env, 0); | 214 | + tcg_gen_extrh_i64_i32(rdahi, rda); |
170 | + } | 215 | + store_reg(s, a->rdalo, rdalo); |
171 | + /* | 216 | + store_reg(s, a->rdahi, rdahi); |
172 | + * Otherwise s0 to s15 and FPSCR are UNKNOWN; we choose to leave them | 217 | + tcg_temp_free_i64(rda); |
173 | + * unchanged. | 218 | + mve_update_eci(s); |
174 | + */ | 219 | + return true; |
175 | +} | 220 | +} |
176 | + | 221 | + |
177 | /* Write to v7M CONTROL.SPSEL bit for the specified security bank. | 222 | +static bool trans_VMLALDAV_S(DisasContext *s, arg_vmlaldav *a) |
178 | * This may change the current stack pointer between Main and Process | 223 | +{ |
179 | * stack pointers if it is done for the CONTROL register for the current | 224 | + static MVEGenDualAccOpFn * const fns[4][2] = { |
180 | @@ -XXX,XX +XXX,XX @@ static void arm_log_exception(int idx) | 225 | + { NULL, NULL }, |
181 | [EXCP_NOCP] = "v7M NOCP UsageFault", | 226 | + { gen_helper_mve_vmlaldavsh, gen_helper_mve_vmlaldavxsh }, |
182 | [EXCP_INVSTATE] = "v7M INVSTATE UsageFault", | 227 | + { gen_helper_mve_vmlaldavsw, gen_helper_mve_vmlaldavxsw }, |
183 | [EXCP_STKOF] = "v8M STKOF UsageFault", | 228 | + { NULL, NULL }, |
184 | + [EXCP_LAZYFP] = "v7M exception during lazy FP stacking", | 229 | + }; |
185 | }; | 230 | + return do_long_dual_acc(s, a, fns[a->size][a->x]); |
186 | 231 | +} | |
187 | if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { | 232 | + |
188 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) | 233 | +static bool trans_VMLALDAV_U(DisasContext *s, arg_vmlaldav *a) |
189 | return; | 234 | +{ |
190 | } | 235 | + static MVEGenDualAccOpFn * const fns[4][2] = { |
191 | break; | 236 | + { NULL, NULL }, |
192 | + case EXCP_LAZYFP: | 237 | + { gen_helper_mve_vmlaldavuh, NULL }, |
193 | + /* | 238 | + { gen_helper_mve_vmlaldavuw, NULL }, |
194 | + * We already pended the specific exception in the NVIC in the | 239 | + { NULL, NULL }, |
195 | + * v7m_preserve_fp_state() helper function. | 240 | + }; |
196 | + */ | 241 | + return do_long_dual_acc(s, a, fns[a->size][a->x]); |
197 | + break; | 242 | +} |
198 | default: | ||
199 | cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); | ||
200 | return; /* Never happens. Keep compiler happy. */ | ||
201 | @@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, | ||
202 | flags = FIELD_DP32(flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED, 1); | ||
203 | } | ||
204 | |||
205 | + if (arm_feature(env, ARM_FEATURE_M)) { | ||
206 | + bool is_secure = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; | ||
207 | + | ||
208 | + if (env->v7m.fpccr[is_secure] & R_V7M_FPCCR_LSPACT_MASK) { | ||
209 | + flags = FIELD_DP32(flags, TBFLAG_A32, LSPACT, 1); | ||
210 | + } | ||
211 | + } | ||
212 | + | ||
213 | *pflags = flags; | ||
214 | *cs_base = 0; | ||
215 | } | ||
216 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
217 | index XXXXXXX..XXXXXXX 100644 | ||
218 | --- a/target/arm/translate.c | ||
219 | +++ b/target/arm/translate.c | ||
220 | @@ -XXX,XX +XXX,XX @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) | ||
221 | if (arm_dc_feature(s, ARM_FEATURE_M)) { | ||
222 | /* Handle M-profile lazy FP state mechanics */ | ||
223 | |||
224 | + /* Trigger lazy-state preservation if necessary */ | ||
225 | + if (s->v7m_lspact) { | ||
226 | + /* | ||
227 | + * Lazy state saving affects external memory and also the NVIC, | ||
228 | + * so we must mark it as an IO operation for icount. | ||
229 | + */ | ||
230 | + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { | ||
231 | + gen_io_start(); | ||
232 | + } | ||
233 | + gen_helper_v7m_preserve_fp_state(cpu_env); | ||
234 | + if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { | ||
235 | + gen_io_end(); | ||
236 | + } | ||
237 | + /* | ||
238 | + * If the preserve_fp_state helper doesn't throw an exception | ||
239 | + * then it will clear LSPACT; we don't need to repeat this for | ||
240 | + * any further FP insns in this TB. | ||
241 | + */ | ||
242 | + s->v7m_lspact = false; | ||
243 | + } | ||
244 | + | ||
245 | /* Update ownership of FP context: set FPCCR.S to match current state */ | ||
246 | if (s->v8m_fpccr_s_wrong) { | ||
247 | TCGv_i32 tmp; | ||
248 | @@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) | ||
249 | dc->v8m_fpccr_s_wrong = FIELD_EX32(tb_flags, TBFLAG_A32, FPCCR_S_WRONG); | ||
250 | dc->v7m_new_fp_ctxt_needed = | ||
251 | FIELD_EX32(tb_flags, TBFLAG_A32, NEW_FP_CTXT_NEEDED); | ||
252 | + dc->v7m_lspact = FIELD_EX32(tb_flags, TBFLAG_A32, LSPACT); | ||
253 | dc->cp_regs = cpu->cp_regs; | ||
254 | dc->features = env->features; | ||
255 | |||
256 | -- | 243 | -- |
257 | 2.20.1 | 244 | 2.20.1 |
258 | 245 | ||
259 | 246 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | 1 | Implement the MVE insn VMLSLDAV, which multiplies source elements, |
---|---|---|---|
2 | alternately adding and subtracting them, and accumulates into a | ||
3 | 64-bit result in a pair of general purpose registers. | ||
2 | 4 | ||
3 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
4 | Reviewed-by: Markus Armbruster <armbru@redhat.com> | ||
5 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
6 | Message-id: 20190412165416.7977-11-philmd@redhat.com | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20210617121628.20116-21-peter.maydell@linaro.org | ||
8 | --- | 8 | --- |
9 | include/hw/net/ne2000-isa.h | 6 ++++++ | 9 | target/arm/helper-mve.h | 5 +++++ |
10 | 1 file changed, 6 insertions(+) | 10 | target/arm/mve.decode | 2 ++ |
11 | target/arm/mve_helper.c | 5 +++++ | ||
12 | target/arm/translate-mve.c | 11 +++++++++++ | ||
13 | 4 files changed, 23 insertions(+) | ||
11 | 14 | ||
12 | diff --git a/include/hw/net/ne2000-isa.h b/include/hw/net/ne2000-isa.h | 15 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
13 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/include/hw/net/ne2000-isa.h | 17 | --- a/target/arm/helper-mve.h |
15 | +++ b/include/hw/net/ne2000-isa.h | 18 | +++ b/target/arm/helper-mve.h |
16 | @@ -XXX,XX +XXX,XX @@ | 19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vmlaldavxsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
17 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | 20 | |
18 | * See the COPYING file in the top-level directory. | 21 | DEF_HELPER_FLAGS_4(mve_vmlaldavuh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
19 | */ | 22 | DEF_HELPER_FLAGS_4(mve_vmlaldavuw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
20 | + | 23 | + |
21 | +#ifndef HW_NET_NE2K_ISA_H | 24 | +DEF_HELPER_FLAGS_4(mve_vmlsldavsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
22 | +#define HW_NET_NE2K_ISA_H | 25 | +DEF_HELPER_FLAGS_4(mve_vmlsldavsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
26 | +DEF_HELPER_FLAGS_4(mve_vmlsldavxsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) | ||
27 | +DEF_HELPER_FLAGS_4(mve_vmlsldavxsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) | ||
28 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/target/arm/mve.decode | ||
31 | +++ b/target/arm/mve.decode | ||
32 | @@ -XXX,XX +XXX,XX @@ VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0 0 1 0000 @vdup size=2 | ||
33 | qn=%qn rdahi=%rdahi rdalo=%rdalo size=%size_16 &vmlaldav | ||
34 | VMLALDAV_S 1110 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 0 @vmlaldav | ||
35 | VMLALDAV_U 1111 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 0 @vmlaldav | ||
23 | + | 36 | + |
24 | #include "hw/hw.h" | 37 | +VMLSLDAV 1110 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 1 @vmlaldav |
25 | #include "hw/qdev.h" | 38 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c |
26 | #include "hw/isa/isa.h" | 39 | index XXXXXXX..XXXXXXX 100644 |
27 | @@ -XXX,XX +XXX,XX @@ static inline ISADevice *isa_ne2000_init(ISABus *bus, int base, int irq, | 40 | --- a/target/arm/mve_helper.c |
28 | } | 41 | +++ b/target/arm/mve_helper.c |
29 | return d; | 42 | @@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlaldavxsw, 4, int32_t, true, +=, +=) |
43 | |||
44 | DO_LDAV(vmlaldavuh, 2, uint16_t, false, +=, +=) | ||
45 | DO_LDAV(vmlaldavuw, 4, uint32_t, false, +=, +=) | ||
46 | + | ||
47 | +DO_LDAV(vmlsldavsh, 2, int16_t, false, +=, -=) | ||
48 | +DO_LDAV(vmlsldavxsh, 2, int16_t, true, +=, -=) | ||
49 | +DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=) | ||
50 | +DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=) | ||
51 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
52 | index XXXXXXX..XXXXXXX 100644 | ||
53 | --- a/target/arm/translate-mve.c | ||
54 | +++ b/target/arm/translate-mve.c | ||
55 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMLALDAV_U(DisasContext *s, arg_vmlaldav *a) | ||
56 | }; | ||
57 | return do_long_dual_acc(s, a, fns[a->size][a->x]); | ||
30 | } | 58 | } |
31 | + | 59 | + |
32 | +#endif | 60 | +static bool trans_VMLSLDAV(DisasContext *s, arg_vmlaldav *a) |
61 | +{ | ||
62 | + static MVEGenDualAccOpFn * const fns[4][2] = { | ||
63 | + { NULL, NULL }, | ||
64 | + { gen_helper_mve_vmlsldavsh, gen_helper_mve_vmlsldavxsh }, | ||
65 | + { gen_helper_mve_vmlsldavsw, gen_helper_mve_vmlsldavxsw }, | ||
66 | + { NULL, NULL }, | ||
67 | + }; | ||
68 | + return do_long_dual_acc(s, a, fns[a->size][a->x]); | ||
69 | +} | ||
33 | -- | 70 | -- |
34 | 2.20.1 | 71 | 2.20.1 |
35 | 72 | ||
36 | 73 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | 1 | Implement the MVE VRMLALDAVH and VRMLSLDAVH insns, which accumulate |
---|---|---|---|
2 | the results of a rounded multiply of pairs of elements into a 72-bit | ||
3 | accumulator, returning the top 64 bits in a pair of general purpose | ||
4 | registers. | ||
2 | 5 | ||
3 | Reviewed-by: Markus Armbruster <armbru@redhat.com> | ||
4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
5 | Message-id: 20190412165416.7977-8-philmd@redhat.com | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20210617121628.20116-22-peter.maydell@linaro.org | ||
7 | --- | 9 | --- |
8 | include/hw/devices.h | 3 --- | 10 | target/arm/helper-mve.h | 8 ++++++++ |
9 | include/hw/input/gamepad.h | 19 +++++++++++++++++++ | 11 | target/arm/mve.decode | 7 +++++++ |
10 | hw/arm/stellaris.c | 2 +- | 12 | target/arm/mve_helper.c | 37 +++++++++++++++++++++++++++++++++++++ |
11 | hw/input/stellaris_input.c | 2 +- | 13 | target/arm/translate-mve.c | 24 ++++++++++++++++++++++++ |
12 | MAINTAINERS | 1 + | 14 | 4 files changed, 76 insertions(+) |
13 | 5 files changed, 22 insertions(+), 5 deletions(-) | ||
14 | create mode 100644 include/hw/input/gamepad.h | ||
15 | 15 | ||
16 | diff --git a/include/hw/devices.h b/include/hw/devices.h | 16 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
17 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/include/hw/devices.h | 18 | --- a/target/arm/helper-mve.h |
19 | +++ b/include/hw/devices.h | 19 | +++ b/target/arm/helper-mve.h |
20 | @@ -XXX,XX +XXX,XX @@ void *tsc2005_init(qemu_irq pintdav); | 20 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vmlsldavsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
21 | uint32_t tsc2005_txrx(void *opaque, uint32_t value, int len); | 21 | DEF_HELPER_FLAGS_4(mve_vmlsldavsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
22 | void tsc2005_set_transform(void *opaque, MouseTransformInfo *info); | 22 | DEF_HELPER_FLAGS_4(mve_vmlsldavxsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
23 | 23 | DEF_HELPER_FLAGS_4(mve_vmlsldavxsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) | |
24 | -/* stellaris_input.c */ | ||
25 | -void stellaris_gamepad_init(int n, qemu_irq *irq, const int *keycode); | ||
26 | - | ||
27 | #endif | ||
28 | diff --git a/include/hw/input/gamepad.h b/include/hw/input/gamepad.h | ||
29 | new file mode 100644 | ||
30 | index XXXXXXX..XXXXXXX | ||
31 | --- /dev/null | ||
32 | +++ b/include/hw/input/gamepad.h | ||
33 | @@ -XXX,XX +XXX,XX @@ | ||
34 | +/* | ||
35 | + * Gamepad style buttons connected to IRQ/GPIO lines | ||
36 | + * | ||
37 | + * Copyright (c) 2007 CodeSourcery. | ||
38 | + * Written by Paul Brook | ||
39 | + * | ||
40 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
41 | + * See the COPYING file in the top-level directory. | ||
42 | + */ | ||
43 | + | 24 | + |
44 | +#ifndef HW_INPUT_GAMEPAD_H | 25 | +DEF_HELPER_FLAGS_4(mve_vrmlaldavhsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
45 | +#define HW_INPUT_GAMEPAD_H | 26 | +DEF_HELPER_FLAGS_4(mve_vrmlaldavhxsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
46 | + | 27 | + |
47 | +#include "hw/irq.h" | 28 | +DEF_HELPER_FLAGS_4(mve_vrmlaldavhuw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
48 | + | 29 | + |
49 | +/* stellaris_input.c */ | 30 | +DEF_HELPER_FLAGS_4(mve_vrmlsldavhsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
50 | +void stellaris_gamepad_init(int n, qemu_irq *irq, const int *keycode); | 31 | +DEF_HELPER_FLAGS_4(mve_vrmlsldavhxsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
32 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/target/arm/mve.decode | ||
35 | +++ b/target/arm/mve.decode | ||
36 | @@ -XXX,XX +XXX,XX @@ VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0 0 1 0000 @vdup size=2 | ||
37 | |||
38 | @vmlaldav .... .... . ... ... . ... . .... .... qm:3 . \ | ||
39 | qn=%qn rdahi=%rdahi rdalo=%rdalo size=%size_16 &vmlaldav | ||
40 | +@vmlaldav_nosz .... .... . ... ... . ... . .... .... qm:3 . \ | ||
41 | + qn=%qn rdahi=%rdahi rdalo=%rdalo size=0 &vmlaldav | ||
42 | VMLALDAV_S 1110 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 0 @vmlaldav | ||
43 | VMLALDAV_U 1111 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 0 @vmlaldav | ||
44 | |||
45 | VMLSLDAV 1110 1110 1 ... ... . ... x:1 1110 . 0 a:1 0 ... 1 @vmlaldav | ||
51 | + | 46 | + |
52 | +#endif | 47 | +VRMLALDAVH_S 1110 1110 1 ... ... 0 ... x:1 1111 . 0 a:1 0 ... 0 @vmlaldav_nosz |
53 | diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c | 48 | +VRMLALDAVH_U 1111 1110 1 ... ... 0 ... x:1 1111 . 0 a:1 0 ... 0 @vmlaldav_nosz |
49 | + | ||
50 | +VRMLSLDAVH 1111 1110 1 ... ... 0 ... x:1 1110 . 0 a:1 0 ... 1 @vmlaldav_nosz | ||
51 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
54 | index XXXXXXX..XXXXXXX 100644 | 52 | index XXXXXXX..XXXXXXX 100644 |
55 | --- a/hw/arm/stellaris.c | 53 | --- a/target/arm/mve_helper.c |
56 | +++ b/hw/arm/stellaris.c | 54 | +++ b/target/arm/mve_helper.c |
57 | @@ -XXX,XX +XXX,XX @@ | ||
58 | #include "hw/sysbus.h" | ||
59 | #include "hw/ssi/ssi.h" | ||
60 | #include "hw/arm/arm.h" | ||
61 | -#include "hw/devices.h" | ||
62 | #include "qemu/timer.h" | ||
63 | #include "hw/i2c/i2c.h" | ||
64 | #include "net/net.h" | ||
65 | @@ -XXX,XX +XXX,XX @@ | ||
66 | #include "sysemu/sysemu.h" | ||
67 | #include "hw/arm/armv7m.h" | ||
68 | #include "hw/char/pl011.h" | ||
69 | +#include "hw/input/gamepad.h" | ||
70 | #include "hw/watchdog/cmsdk-apb-watchdog.h" | ||
71 | #include "hw/misc/unimp.h" | ||
72 | #include "cpu.h" | ||
73 | diff --git a/hw/input/stellaris_input.c b/hw/input/stellaris_input.c | ||
74 | index XXXXXXX..XXXXXXX 100644 | ||
75 | --- a/hw/input/stellaris_input.c | ||
76 | +++ b/hw/input/stellaris_input.c | ||
77 | @@ -XXX,XX +XXX,XX @@ | 55 | @@ -XXX,XX +XXX,XX @@ |
78 | */ | 56 | */ |
57 | |||
79 | #include "qemu/osdep.h" | 58 | #include "qemu/osdep.h" |
80 | #include "hw/hw.h" | 59 | +#include "qemu/int128.h" |
81 | -#include "hw/devices.h" | 60 | #include "cpu.h" |
82 | +#include "hw/input/gamepad.h" | 61 | #include "internals.h" |
83 | #include "ui/console.h" | 62 | #include "vec_internal.h" |
84 | 63 | @@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavsh, 2, int16_t, false, +=, -=) | |
85 | typedef struct { | 64 | DO_LDAV(vmlsldavxsh, 2, int16_t, true, +=, -=) |
86 | diff --git a/MAINTAINERS b/MAINTAINERS | 65 | DO_LDAV(vmlsldavsw, 4, int32_t, false, +=, -=) |
66 | DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=) | ||
67 | + | ||
68 | +/* | ||
69 | + * Rounding multiply add long dual accumulate high: we must keep | ||
70 | + * a 72-bit internal accumulator value and return the top 64 bits. | ||
71 | + */ | ||
72 | +#define DO_LDAVH(OP, ESIZE, TYPE, XCHG, EVENACC, ODDACC, TO128) \ | ||
73 | + uint64_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \ | ||
74 | + void *vm, uint64_t a) \ | ||
75 | + { \ | ||
76 | + uint16_t mask = mve_element_mask(env); \ | ||
77 | + unsigned e; \ | ||
78 | + TYPE *n = vn, *m = vm; \ | ||
79 | + Int128 acc = int128_lshift(TO128(a), 8); \ | ||
80 | + for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ | ||
81 | + if (mask & 1) { \ | ||
82 | + if (e & 1) { \ | ||
83 | + acc = ODDACC(acc, TO128(n[H##ESIZE(e - 1 * XCHG)] * \ | ||
84 | + m[H##ESIZE(e)])); \ | ||
85 | + } else { \ | ||
86 | + acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \ | ||
87 | + m[H##ESIZE(e)])); \ | ||
88 | + } \ | ||
89 | + acc = int128_add(acc, 1 << 7); \ | ||
90 | + } \ | ||
91 | + } \ | ||
92 | + mve_advance_vpt(env); \ | ||
93 | + return int128_getlo(int128_rshift(acc, 8)); \ | ||
94 | + } | ||
95 | + | ||
96 | +DO_LDAVH(vrmlaldavhsw, 4, int32_t, false, int128_add, int128_add, int128_makes64) | ||
97 | +DO_LDAVH(vrmlaldavhxsw, 4, int32_t, true, int128_add, int128_add, int128_makes64) | ||
98 | + | ||
99 | +DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64) | ||
100 | + | ||
101 | +DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64) | ||
102 | +DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64) | ||
103 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
87 | index XXXXXXX..XXXXXXX 100644 | 104 | index XXXXXXX..XXXXXXX 100644 |
88 | --- a/MAINTAINERS | 105 | --- a/target/arm/translate-mve.c |
89 | +++ b/MAINTAINERS | 106 | +++ b/target/arm/translate-mve.c |
90 | @@ -XXX,XX +XXX,XX @@ M: Peter Maydell <peter.maydell@linaro.org> | 107 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMLSLDAV(DisasContext *s, arg_vmlaldav *a) |
91 | L: qemu-arm@nongnu.org | 108 | }; |
92 | S: Maintained | 109 | return do_long_dual_acc(s, a, fns[a->size][a->x]); |
93 | F: hw/*/stellaris* | 110 | } |
94 | +F: include/hw/input/gamepad.h | 111 | + |
95 | 112 | +static bool trans_VRMLALDAVH_S(DisasContext *s, arg_vmlaldav *a) | |
96 | Versatile Express | 113 | +{ |
97 | M: Peter Maydell <peter.maydell@linaro.org> | 114 | + static MVEGenDualAccOpFn * const fns[] = { |
115 | + gen_helper_mve_vrmlaldavhsw, gen_helper_mve_vrmlaldavhxsw, | ||
116 | + }; | ||
117 | + return do_long_dual_acc(s, a, fns[a->x]); | ||
118 | +} | ||
119 | + | ||
120 | +static bool trans_VRMLALDAVH_U(DisasContext *s, arg_vmlaldav *a) | ||
121 | +{ | ||
122 | + static MVEGenDualAccOpFn * const fns[] = { | ||
123 | + gen_helper_mve_vrmlaldavhuw, NULL, | ||
124 | + }; | ||
125 | + return do_long_dual_acc(s, a, fns[a->x]); | ||
126 | +} | ||
127 | + | ||
128 | +static bool trans_VRMLSLDAVH(DisasContext *s, arg_vmlaldav *a) | ||
129 | +{ | ||
130 | + static MVEGenDualAccOpFn * const fns[] = { | ||
131 | + gen_helper_mve_vrmlsldavhsw, gen_helper_mve_vrmlsldavhxsw, | ||
132 | + }; | ||
133 | + return do_long_dual_acc(s, a, fns[a->x]); | ||
134 | +} | ||
98 | -- | 135 | -- |
99 | 2.20.1 | 136 | 2.20.1 |
100 | 137 | ||
101 | 138 | diff view generated by jsdifflib |
1 | Handle floating point registers in exception entry. | 1 | Implement the scalar form of the MVE VADD insn. This takes the |
---|---|---|---|
2 | This corresponds to the FP-specific parts of the pseudocode | 2 | scalar operand from a general purpose register. |
3 | functions ActivateException() and PushStack(). | ||
4 | |||
5 | We defer the code corresponding to UpdateFPCCR() to a later patch. | ||
6 | 3 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20190416125744.27770-11-peter.maydell@linaro.org | 6 | Message-id: 20210617121628.20116-23-peter.maydell@linaro.org |
10 | --- | 7 | --- |
11 | target/arm/helper.c | 98 +++++++++++++++++++++++++++++++++++++++++++-- | 8 | target/arm/helper-mve.h | 4 ++++ |
12 | 1 file changed, 95 insertions(+), 3 deletions(-) | 9 | target/arm/mve.decode | 7 ++++++ |
10 | target/arm/mve_helper.c | 22 +++++++++++++++++++ | ||
11 | target/arm/translate-mve.c | 45 ++++++++++++++++++++++++++++++++++++++ | ||
12 | 4 files changed, 78 insertions(+) | ||
13 | 13 | ||
14 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 14 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
15 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper.c | 16 | --- a/target/arm/helper-mve.h |
17 | +++ b/target/arm/helper.c | 17 | +++ b/target/arm/helper-mve.h |
18 | @@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain, | 18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vmulltub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
19 | switch_v7m_security_state(env, targets_secure); | 19 | DEF_HELPER_FLAGS_4(mve_vmulltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
20 | write_v7m_control_spsel(env, 0); | 20 | DEF_HELPER_FLAGS_4(mve_vmulltuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
21 | arm_clear_exclusive(env); | 21 | |
22 | + /* Clear SFPA and FPCA (has no effect if no FPU) */ | 22 | +DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
23 | + env->v7m.control[M_REG_S] &= | 23 | +DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
24 | + ~(R_V7M_CONTROL_FPCA_MASK | R_V7M_CONTROL_SFPA_MASK); | 24 | +DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
25 | /* Clear IT bits */ | ||
26 | env->condexec_bits = 0; | ||
27 | env->regs[14] = lr; | ||
28 | @@ -XXX,XX +XXX,XX @@ static bool v7m_push_stack(ARMCPU *cpu) | ||
29 | uint32_t xpsr = xpsr_read(env); | ||
30 | uint32_t frameptr = env->regs[13]; | ||
31 | ARMMMUIdx mmu_idx = arm_mmu_idx(env); | ||
32 | + uint32_t framesize; | ||
33 | + bool nsacr_cp10 = extract32(env->v7m.nsacr, 10, 1); | ||
34 | + | 25 | + |
35 | + if ((env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) && | 26 | DEF_HELPER_FLAGS_4(mve_vmlaldavsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
36 | + (env->v7m.secure || nsacr_cp10)) { | 27 | DEF_HELPER_FLAGS_4(mve_vmlaldavsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
37 | + if (env->v7m.secure && | 28 | DEF_HELPER_FLAGS_4(mve_vmlaldavxsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
38 | + env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MASK) { | 29 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode |
39 | + framesize = 0xa8; | 30 | index XXXXXXX..XXXXXXX 100644 |
40 | + } else { | 31 | --- a/target/arm/mve.decode |
41 | + framesize = 0x68; | 32 | +++ b/target/arm/mve.decode |
42 | + } | 33 | @@ -XXX,XX +XXX,XX @@ |
43 | + } else { | 34 | &vldr_vstr rn qd imm p a w size l u |
44 | + framesize = 0x20; | 35 | &1op qd qm size |
45 | + } | 36 | &2op qd qm qn size |
46 | 37 | +&2scalar qd qn rm size | |
47 | /* Align stack pointer if the guest wants that */ | 38 | |
48 | if ((frameptr & 4) && | 39 | @vldr_vstr ....... . . . . l:1 rn:4 ... ...... imm:7 &vldr_vstr qd=%qd u=0 |
49 | @@ -XXX,XX +XXX,XX @@ static bool v7m_push_stack(ARMCPU *cpu) | 40 | # Note that both Rn and Qd are 3 bits only (no D bit) |
50 | xpsr |= XPSR_SPREALIGN; | 41 | @@ -XXX,XX +XXX,XX @@ |
51 | } | 42 | @2op .... .... .. size:2 .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn |
52 | 43 | @2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0 | |
53 | - frameptr -= 0x20; | 44 | |
54 | + xpsr &= ~XPSR_SFPA; | 45 | +@2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn |
55 | + if (env->v7m.secure && | 46 | + |
56 | + (env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)) { | 47 | # Vector loads and stores |
57 | + xpsr |= XPSR_SFPA; | 48 | |
49 | # Widening loads and narrowing stores: | ||
50 | @@ -XXX,XX +XXX,XX @@ VRMLALDAVH_S 1110 1110 1 ... ... 0 ... x:1 1111 . 0 a:1 0 ... 0 @vmlaldav_no | ||
51 | VRMLALDAVH_U 1111 1110 1 ... ... 0 ... x:1 1111 . 0 a:1 0 ... 0 @vmlaldav_nosz | ||
52 | |||
53 | VRMLSLDAVH 1111 1110 1 ... ... 0 ... x:1 1110 . 0 a:1 0 ... 1 @vmlaldav_nosz | ||
54 | + | ||
55 | +# Scalar operations | ||
56 | + | ||
57 | +VADD_scalar 1110 1110 0 . .. ... 1 ... 0 1111 . 100 .... @2scalar | ||
58 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
59 | index XXXXXXX..XXXXXXX 100644 | ||
60 | --- a/target/arm/mve_helper.c | ||
61 | +++ b/target/arm/mve_helper.c | ||
62 | @@ -XXX,XX +XXX,XX @@ DO_2OP_S(vhsubs, do_vhsub_s) | ||
63 | DO_2OP_U(vhsubu, do_vhsub_u) | ||
64 | |||
65 | |||
66 | +#define DO_2OP_SCALAR(OP, ESIZE, TYPE, FN) \ | ||
67 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ | ||
68 | + uint32_t rm) \ | ||
69 | + { \ | ||
70 | + TYPE *d = vd, *n = vn; \ | ||
71 | + TYPE m = rm; \ | ||
72 | + uint16_t mask = mve_element_mask(env); \ | ||
73 | + unsigned e; \ | ||
74 | + for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ | ||
75 | + mergemask(&d[H##ESIZE(e)], FN(n[H##ESIZE(e)], m), mask); \ | ||
76 | + } \ | ||
77 | + mve_advance_vpt(env); \ | ||
58 | + } | 78 | + } |
59 | + | 79 | + |
60 | + frameptr -= framesize; | 80 | +/* provide unsigned 2-op scalar helpers for all sizes */ |
61 | 81 | +#define DO_2OP_SCALAR_U(OP, FN) \ | |
62 | if (arm_feature(env, ARM_FEATURE_V8)) { | 82 | + DO_2OP_SCALAR(OP##b, 1, uint8_t, FN) \ |
63 | uint32_t limit = v7m_sp_limit(env); | 83 | + DO_2OP_SCALAR(OP##h, 2, uint16_t, FN) \ |
64 | @@ -XXX,XX +XXX,XX @@ static bool v7m_push_stack(ARMCPU *cpu) | 84 | + DO_2OP_SCALAR(OP##w, 4, uint32_t, FN) |
65 | v7m_stack_write(cpu, frameptr + 24, env->regs[15], mmu_idx, false) && | ||
66 | v7m_stack_write(cpu, frameptr + 28, xpsr, mmu_idx, false); | ||
67 | |||
68 | + if (env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK) { | ||
69 | + /* FPU is active, try to save its registers */ | ||
70 | + bool fpccr_s = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; | ||
71 | + bool lspact = env->v7m.fpccr[fpccr_s] & R_V7M_FPCCR_LSPACT_MASK; | ||
72 | + | 85 | + |
73 | + if (lspact && arm_feature(env, ARM_FEATURE_M_SECURITY)) { | 86 | +DO_2OP_SCALAR_U(vadd_scalar, DO_ADD) |
74 | + qemu_log_mask(CPU_LOG_INT, | ||
75 | + "...SecureFault because LSPACT and FPCA both set\n"); | ||
76 | + env->v7m.sfsr |= R_V7M_SFSR_LSERR_MASK; | ||
77 | + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); | ||
78 | + } else if (!env->v7m.secure && !nsacr_cp10) { | ||
79 | + qemu_log_mask(CPU_LOG_INT, | ||
80 | + "...Secure UsageFault with CFSR.NOCP because " | ||
81 | + "NSACR.CP10 prevents stacking FP regs\n"); | ||
82 | + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, M_REG_S); | ||
83 | + env->v7m.cfsr[M_REG_S] |= R_V7M_CFSR_NOCP_MASK; | ||
84 | + } else { | ||
85 | + if (!(env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_LSPEN_MASK)) { | ||
86 | + /* Lazy stacking disabled, save registers now */ | ||
87 | + int i; | ||
88 | + bool cpacr_pass = v7m_cpacr_pass(env, env->v7m.secure, | ||
89 | + arm_current_el(env) != 0); | ||
90 | + | 87 | + |
91 | + if (stacked_ok && !cpacr_pass) { | 88 | /* |
92 | + /* | 89 | * Multiply add long dual accumulate ops. |
93 | + * Take UsageFault if CPACR forbids access. The pseudocode | 90 | */ |
94 | + * here does a full CheckCPEnabled() but we know the NSACR | 91 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c |
95 | + * check can never fail as we have already handled that. | 92 | index XXXXXXX..XXXXXXX 100644 |
96 | + */ | 93 | --- a/target/arm/translate-mve.c |
97 | + qemu_log_mask(CPU_LOG_INT, | 94 | +++ b/target/arm/translate-mve.c |
98 | + "...UsageFault with CFSR.NOCP because " | 95 | @@ -XXX,XX +XXX,XX @@ |
99 | + "CPACR.CP10 prevents stacking FP regs\n"); | 96 | typedef void MVEGenLdStFn(TCGv_ptr, TCGv_ptr, TCGv_i32); |
100 | + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, | 97 | typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); |
101 | + env->v7m.secure); | 98 | typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr); |
102 | + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_NOCP_MASK; | 99 | +typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); |
103 | + stacked_ok = false; | 100 | typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64); |
104 | + } | 101 | |
102 | /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */ | ||
103 | @@ -XXX,XX +XXX,XX @@ DO_2OP(VMULL_BU, vmullbu) | ||
104 | DO_2OP(VMULL_TS, vmullts) | ||
105 | DO_2OP(VMULL_TU, vmulltu) | ||
106 | |||
107 | +static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, | ||
108 | + MVEGenTwoOpScalarFn fn) | ||
109 | +{ | ||
110 | + TCGv_ptr qd, qn; | ||
111 | + TCGv_i32 rm; | ||
105 | + | 112 | + |
106 | + for (i = 0; i < ((framesize == 0xa8) ? 32 : 16); i += 2) { | 113 | + if (!dc_isar_feature(aa32_mve, s) || |
107 | + uint64_t dn = *aa32_vfp_dreg(env, i / 2); | 114 | + !mve_check_qreg_bank(s, a->qd | a->qn) || |
108 | + uint32_t faddr = frameptr + 0x20 + 4 * i; | 115 | + !fn) { |
109 | + uint32_t slo = extract64(dn, 0, 32); | 116 | + return false; |
110 | + uint32_t shi = extract64(dn, 32, 32); | 117 | + } |
111 | + | 118 | + if (a->rm == 13 || a->rm == 15) { |
112 | + if (i >= 16) { | 119 | + /* UNPREDICTABLE */ |
113 | + faddr += 8; /* skip the slot for the FPSCR */ | 120 | + return false; |
114 | + } | 121 | + } |
115 | + stacked_ok = stacked_ok && | 122 | + if (!mve_eci_check(s) || !vfp_access_check(s)) { |
116 | + v7m_stack_write(cpu, faddr, slo, mmu_idx, false) && | 123 | + return true; |
117 | + v7m_stack_write(cpu, faddr + 4, shi, mmu_idx, false); | ||
118 | + } | ||
119 | + stacked_ok = stacked_ok && | ||
120 | + v7m_stack_write(cpu, frameptr + 0x60, | ||
121 | + vfp_get_fpscr(env), mmu_idx, false); | ||
122 | + if (cpacr_pass) { | ||
123 | + for (i = 0; i < ((framesize == 0xa8) ? 32 : 16); i += 2) { | ||
124 | + *aa32_vfp_dreg(env, i / 2) = 0; | ||
125 | + } | ||
126 | + vfp_set_fpscr(env, 0); | ||
127 | + } | ||
128 | + } else { | ||
129 | + /* Lazy stacking enabled, save necessary info to stack later */ | ||
130 | + /* TODO : equivalent of UpdateFPCCR() pseudocode */ | ||
131 | + } | ||
132 | + } | ||
133 | + } | 124 | + } |
134 | + | 125 | + |
135 | /* | 126 | + qd = mve_qreg_ptr(a->qd); |
136 | * If we broke a stack limit then SP was already updated earlier; | 127 | + qn = mve_qreg_ptr(a->qn); |
137 | * otherwise we update SP regardless of whether any of the stack | 128 | + rm = load_reg(s, a->rm); |
138 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) | 129 | + fn(cpu_env, qd, qn, rm); |
139 | 130 | + tcg_temp_free_i32(rm); | |
140 | if (arm_feature(env, ARM_FEATURE_V8)) { | 131 | + tcg_temp_free_ptr(qd); |
141 | lr = R_V7M_EXCRET_RES1_MASK | | 132 | + tcg_temp_free_ptr(qn); |
142 | - R_V7M_EXCRET_DCRS_MASK | | 133 | + mve_update_eci(s); |
143 | - R_V7M_EXCRET_FTYPE_MASK; | 134 | + return true; |
144 | + R_V7M_EXCRET_DCRS_MASK; | 135 | +} |
145 | /* The S bit indicates whether we should return to Secure | 136 | + |
146 | * or NonSecure (ie our current state). | 137 | +#define DO_2OP_SCALAR(INSN, FN) \ |
147 | * The ES bit indicates whether we're taking this exception | 138 | + static bool trans_##INSN(DisasContext *s, arg_2scalar *a) \ |
148 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) | 139 | + { \ |
149 | if (env->v7m.secure) { | 140 | + static MVEGenTwoOpScalarFn * const fns[] = { \ |
150 | lr |= R_V7M_EXCRET_S_MASK; | 141 | + gen_helper_mve_##FN##b, \ |
151 | } | 142 | + gen_helper_mve_##FN##h, \ |
152 | + if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) { | 143 | + gen_helper_mve_##FN##w, \ |
153 | + lr |= R_V7M_EXCRET_FTYPE_MASK; | 144 | + NULL, \ |
154 | + } | 145 | + }; \ |
155 | } else { | 146 | + return do_2op_scalar(s, a, fns[a->size]); \ |
156 | lr = R_V7M_EXCRET_RES1_MASK | | 147 | + } |
157 | R_V7M_EXCRET_S_MASK | | 148 | + |
149 | +DO_2OP_SCALAR(VADD_scalar, vadd_scalar) | ||
150 | + | ||
151 | static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, | ||
152 | MVEGenDualAccOpFn *fn) | ||
153 | { | ||
158 | -- | 154 | -- |
159 | 2.20.1 | 155 | 2.20.1 |
160 | 156 | ||
161 | 157 | diff view generated by jsdifflib |
1 | Currently the code in v7m_push_stack() which detects a violation | 1 | Implement the scalar forms of the MVE VSUB and VMUL insns. |
---|---|---|---|
2 | of the v8M stack limit simply returns early if it does so. This | ||
3 | is OK for the current integer-only code, but won't work for the | ||
4 | floating point handling we're about to add. We need to continue | ||
5 | executing the rest of the function so that we check for other | ||
6 | exceptions like not having permission to use the FPU and so | ||
7 | that we correctly set the FPCCR state if we are doing lazy | ||
8 | stacking. Refactor to avoid the early return. | ||
9 | 2 | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
12 | Message-id: 20190416125744.27770-10-peter.maydell@linaro.org | 5 | Message-id: 20210617121628.20116-24-peter.maydell@linaro.org |
13 | --- | 6 | --- |
14 | target/arm/helper.c | 23 ++++++++++++++++++----- | 7 | target/arm/helper-mve.h | 8 ++++++++ |
15 | 1 file changed, 18 insertions(+), 5 deletions(-) | 8 | target/arm/mve.decode | 2 ++ |
9 | target/arm/mve_helper.c | 2 ++ | ||
10 | target/arm/translate-mve.c | 2 ++ | ||
11 | 4 files changed, 14 insertions(+) | ||
16 | 12 | ||
17 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 13 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
18 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/helper.c | 15 | --- a/target/arm/helper-mve.h |
20 | +++ b/target/arm/helper.c | 16 | +++ b/target/arm/helper-mve.h |
21 | @@ -XXX,XX +XXX,XX @@ static bool v7m_push_stack(ARMCPU *cpu) | 17 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
22 | * should ignore further stack faults trying to process | 18 | DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
23 | * that derived exception.) | 19 | DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
24 | */ | 20 | |
25 | - bool stacked_ok; | 21 | +DEF_HELPER_FLAGS_4(mve_vsub_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
26 | + bool stacked_ok = true, limitviol = false; | 22 | +DEF_HELPER_FLAGS_4(mve_vsub_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
27 | CPUARMState *env = &cpu->env; | 23 | +DEF_HELPER_FLAGS_4(mve_vsub_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
28 | uint32_t xpsr = xpsr_read(env); | 24 | + |
29 | uint32_t frameptr = env->regs[13]; | 25 | +DEF_HELPER_FLAGS_4(mve_vmul_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
30 | @@ -XXX,XX +XXX,XX @@ static bool v7m_push_stack(ARMCPU *cpu) | 26 | +DEF_HELPER_FLAGS_4(mve_vmul_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
31 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, | 27 | +DEF_HELPER_FLAGS_4(mve_vmul_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
32 | env->v7m.secure); | 28 | + |
33 | env->regs[13] = limit; | 29 | DEF_HELPER_FLAGS_4(mve_vmlaldavsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
34 | - return true; | 30 | DEF_HELPER_FLAGS_4(mve_vmlaldavsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
35 | + /* | 31 | DEF_HELPER_FLAGS_4(mve_vmlaldavxsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
36 | + * We won't try to perform any further memory accesses but | 32 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode |
37 | + * we must continue through the following code to check for | 33 | index XXXXXXX..XXXXXXX 100644 |
38 | + * permission faults during FPU state preservation, and we | 34 | --- a/target/arm/mve.decode |
39 | + * must update FPCCR if lazy stacking is enabled. | 35 | +++ b/target/arm/mve.decode |
40 | + */ | 36 | @@ -XXX,XX +XXX,XX @@ VRMLSLDAVH 1111 1110 1 ... ... 0 ... x:1 1110 . 0 a:1 0 ... 1 @vmlaldav_no |
41 | + limitviol = true; | 37 | # Scalar operations |
42 | + stacked_ok = false; | 38 | |
43 | } | 39 | VADD_scalar 1110 1110 0 . .. ... 1 ... 0 1111 . 100 .... @2scalar |
40 | +VSUB_scalar 1110 1110 0 . .. ... 1 ... 1 1111 . 100 .... @2scalar | ||
41 | +VMUL_scalar 1110 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar | ||
42 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/target/arm/mve_helper.c | ||
45 | +++ b/target/arm/mve_helper.c | ||
46 | @@ -XXX,XX +XXX,XX @@ DO_2OP_U(vhsubu, do_vhsub_u) | ||
47 | DO_2OP_SCALAR(OP##w, 4, uint32_t, FN) | ||
48 | |||
49 | DO_2OP_SCALAR_U(vadd_scalar, DO_ADD) | ||
50 | +DO_2OP_SCALAR_U(vsub_scalar, DO_SUB) | ||
51 | +DO_2OP_SCALAR_U(vmul_scalar, DO_MUL) | ||
52 | |||
53 | /* | ||
54 | * Multiply add long dual accumulate ops. | ||
55 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
56 | index XXXXXXX..XXXXXXX 100644 | ||
57 | --- a/target/arm/translate-mve.c | ||
58 | +++ b/target/arm/translate-mve.c | ||
59 | @@ -XXX,XX +XXX,XX @@ static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, | ||
44 | } | 60 | } |
45 | 61 | ||
46 | @@ -XXX,XX +XXX,XX @@ static bool v7m_push_stack(ARMCPU *cpu) | 62 | DO_2OP_SCALAR(VADD_scalar, vadd_scalar) |
47 | * (which may be taken in preference to the one we started with | 63 | +DO_2OP_SCALAR(VSUB_scalar, vsub_scalar) |
48 | * if it has higher priority). | 64 | +DO_2OP_SCALAR(VMUL_scalar, vmul_scalar) |
49 | */ | 65 | |
50 | - stacked_ok = | 66 | static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, |
51 | + stacked_ok = stacked_ok && | 67 | MVEGenDualAccOpFn *fn) |
52 | v7m_stack_write(cpu, frameptr, env->regs[0], mmu_idx, false) && | ||
53 | v7m_stack_write(cpu, frameptr + 4, env->regs[1], mmu_idx, false) && | ||
54 | v7m_stack_write(cpu, frameptr + 8, env->regs[2], mmu_idx, false) && | ||
55 | @@ -XXX,XX +XXX,XX @@ static bool v7m_push_stack(ARMCPU *cpu) | ||
56 | v7m_stack_write(cpu, frameptr + 24, env->regs[15], mmu_idx, false) && | ||
57 | v7m_stack_write(cpu, frameptr + 28, xpsr, mmu_idx, false); | ||
58 | |||
59 | - /* Update SP regardless of whether any of the stack accesses failed. */ | ||
60 | - env->regs[13] = frameptr; | ||
61 | + /* | ||
62 | + * If we broke a stack limit then SP was already updated earlier; | ||
63 | + * otherwise we update SP regardless of whether any of the stack | ||
64 | + * accesses failed or we took some other kind of fault. | ||
65 | + */ | ||
66 | + if (!limitviol) { | ||
67 | + env->regs[13] = frameptr; | ||
68 | + } | ||
69 | |||
70 | return !stacked_ok; | ||
71 | } | ||
72 | -- | 68 | -- |
73 | 2.20.1 | 69 | 2.20.1 |
74 | 70 | ||
75 | 71 | diff view generated by jsdifflib |
1 | Enable the FPU by default for the Cortex-M4 and Cortex-M33. | 1 | Implement the scalar variants of the MVE VHADD and VHSUB insns. |
---|---|---|---|
2 | 2 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 20190416125744.27770-27-peter.maydell@linaro.org | 5 | Message-id: 20210617121628.20116-25-peter.maydell@linaro.org |
6 | --- | 6 | --- |
7 | target/arm/cpu.c | 8 ++++++++ | 7 | target/arm/helper-mve.h | 16 ++++++++++++++++ |
8 | 1 file changed, 8 insertions(+) | 8 | target/arm/mve.decode | 4 ++++ |
9 | target/arm/mve_helper.c | 8 ++++++++ | ||
10 | target/arm/translate-mve.c | 4 ++++ | ||
11 | 4 files changed, 32 insertions(+) | ||
9 | 12 | ||
10 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 13 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
11 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
12 | --- a/target/arm/cpu.c | 15 | --- a/target/arm/helper-mve.h |
13 | +++ b/target/arm/cpu.c | 16 | +++ b/target/arm/helper-mve.h |
14 | @@ -XXX,XX +XXX,XX @@ static void cortex_m4_initfn(Object *obj) | 17 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vmul_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
15 | set_feature(&cpu->env, ARM_FEATURE_M); | 18 | DEF_HELPER_FLAGS_4(mve_vmul_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
16 | set_feature(&cpu->env, ARM_FEATURE_M_MAIN); | 19 | DEF_HELPER_FLAGS_4(mve_vmul_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
17 | set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); | 20 | |
18 | + set_feature(&cpu->env, ARM_FEATURE_VFP4); | 21 | +DEF_HELPER_FLAGS_4(mve_vhadds_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
19 | cpu->midr = 0x410fc240; /* r0p0 */ | 22 | +DEF_HELPER_FLAGS_4(mve_vhadds_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
20 | cpu->pmsav7_dregion = 8; | 23 | +DEF_HELPER_FLAGS_4(mve_vhadds_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
21 | + cpu->isar.mvfr0 = 0x10110021; | 24 | + |
22 | + cpu->isar.mvfr1 = 0x11000011; | 25 | +DEF_HELPER_FLAGS_4(mve_vhaddu_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
23 | + cpu->isar.mvfr2 = 0x00000000; | 26 | +DEF_HELPER_FLAGS_4(mve_vhaddu_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
24 | cpu->id_pfr0 = 0x00000030; | 27 | +DEF_HELPER_FLAGS_4(mve_vhaddu_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
25 | cpu->id_pfr1 = 0x00000200; | 28 | + |
26 | cpu->id_dfr0 = 0x00100000; | 29 | +DEF_HELPER_FLAGS_4(mve_vhsubs_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
27 | @@ -XXX,XX +XXX,XX @@ static void cortex_m33_initfn(Object *obj) | 30 | +DEF_HELPER_FLAGS_4(mve_vhsubs_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
28 | set_feature(&cpu->env, ARM_FEATURE_M_MAIN); | 31 | +DEF_HELPER_FLAGS_4(mve_vhsubs_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
29 | set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); | 32 | + |
30 | set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); | 33 | +DEF_HELPER_FLAGS_4(mve_vhsubu_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
31 | + set_feature(&cpu->env, ARM_FEATURE_VFP4); | 34 | +DEF_HELPER_FLAGS_4(mve_vhsubu_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
32 | cpu->midr = 0x410fd213; /* r0p3 */ | 35 | +DEF_HELPER_FLAGS_4(mve_vhsubu_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
33 | cpu->pmsav7_dregion = 16; | 36 | + |
34 | cpu->sau_sregion = 8; | 37 | DEF_HELPER_FLAGS_4(mve_vmlaldavsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
35 | + cpu->isar.mvfr0 = 0x10110021; | 38 | DEF_HELPER_FLAGS_4(mve_vmlaldavsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
36 | + cpu->isar.mvfr1 = 0x11000011; | 39 | DEF_HELPER_FLAGS_4(mve_vmlaldavxsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
37 | + cpu->isar.mvfr2 = 0x00000040; | 40 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode |
38 | cpu->id_pfr0 = 0x00000030; | 41 | index XXXXXXX..XXXXXXX 100644 |
39 | cpu->id_pfr1 = 0x00000210; | 42 | --- a/target/arm/mve.decode |
40 | cpu->id_dfr0 = 0x00200000; | 43 | +++ b/target/arm/mve.decode |
44 | @@ -XXX,XX +XXX,XX @@ VRMLSLDAVH 1111 1110 1 ... ... 0 ... x:1 1110 . 0 a:1 0 ... 1 @vmlaldav_no | ||
45 | VADD_scalar 1110 1110 0 . .. ... 1 ... 0 1111 . 100 .... @2scalar | ||
46 | VSUB_scalar 1110 1110 0 . .. ... 1 ... 1 1111 . 100 .... @2scalar | ||
47 | VMUL_scalar 1110 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar | ||
48 | +VHADD_S_scalar 1110 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar | ||
49 | +VHADD_U_scalar 1111 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar | ||
50 | +VHSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar | ||
51 | +VHSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar | ||
52 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
53 | index XXXXXXX..XXXXXXX 100644 | ||
54 | --- a/target/arm/mve_helper.c | ||
55 | +++ b/target/arm/mve_helper.c | ||
56 | @@ -XXX,XX +XXX,XX @@ DO_2OP_U(vhsubu, do_vhsub_u) | ||
57 | DO_2OP_SCALAR(OP##b, 1, uint8_t, FN) \ | ||
58 | DO_2OP_SCALAR(OP##h, 2, uint16_t, FN) \ | ||
59 | DO_2OP_SCALAR(OP##w, 4, uint32_t, FN) | ||
60 | +#define DO_2OP_SCALAR_S(OP, FN) \ | ||
61 | + DO_2OP_SCALAR(OP##b, 1, int8_t, FN) \ | ||
62 | + DO_2OP_SCALAR(OP##h, 2, int16_t, FN) \ | ||
63 | + DO_2OP_SCALAR(OP##w, 4, int32_t, FN) | ||
64 | |||
65 | DO_2OP_SCALAR_U(vadd_scalar, DO_ADD) | ||
66 | DO_2OP_SCALAR_U(vsub_scalar, DO_SUB) | ||
67 | DO_2OP_SCALAR_U(vmul_scalar, DO_MUL) | ||
68 | +DO_2OP_SCALAR_S(vhadds_scalar, do_vhadd_s) | ||
69 | +DO_2OP_SCALAR_U(vhaddu_scalar, do_vhadd_u) | ||
70 | +DO_2OP_SCALAR_S(vhsubs_scalar, do_vhsub_s) | ||
71 | +DO_2OP_SCALAR_U(vhsubu_scalar, do_vhsub_u) | ||
72 | |||
73 | /* | ||
74 | * Multiply add long dual accumulate ops. | ||
75 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
76 | index XXXXXXX..XXXXXXX 100644 | ||
77 | --- a/target/arm/translate-mve.c | ||
78 | +++ b/target/arm/translate-mve.c | ||
79 | @@ -XXX,XX +XXX,XX @@ static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, | ||
80 | DO_2OP_SCALAR(VADD_scalar, vadd_scalar) | ||
81 | DO_2OP_SCALAR(VSUB_scalar, vsub_scalar) | ||
82 | DO_2OP_SCALAR(VMUL_scalar, vmul_scalar) | ||
83 | +DO_2OP_SCALAR(VHADD_S_scalar, vhadds_scalar) | ||
84 | +DO_2OP_SCALAR(VHADD_U_scalar, vhaddu_scalar) | ||
85 | +DO_2OP_SCALAR(VHSUB_S_scalar, vhsubs_scalar) | ||
86 | +DO_2OP_SCALAR(VHSUB_U_scalar, vhsubu_scalar) | ||
87 | |||
88 | static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, | ||
89 | MVEGenDualAccOpFn *fn) | ||
41 | -- | 90 | -- |
42 | 2.20.1 | 91 | 2.20.1 |
43 | 92 | ||
44 | 93 | diff view generated by jsdifflib |
1 | The M-profile floating point support has three associated config | 1 | Implement the MVE VBRSR insn, which reverses a specified |
---|---|---|---|
2 | registers: FPCAR, FPCCR and FPDSCR. It also makes the registers | 2 | number of bits in each element, setting the rest to zero. |
3 | CPACR and NSACR have behaviour other than reads-as-zero. | ||
4 | Add support for all of these as simple reads-as-written registers. | ||
5 | We will hook up actual functionality later. | ||
6 | |||
7 | The main complexity here is handling the FPCCR register, which | ||
8 | has a mix of banked and unbanked bits. | ||
9 | |||
10 | Note that we don't share storage with the A-profile | ||
11 | cpu->cp15.nsacr and cpu->cp15.cpacr_el1, though the behaviour | ||
12 | is quite similar, for two reasons: | ||
13 | * the M profile CPACR is banked between security states | ||
14 | * it preserves the invariant that M profile uses no state | ||
15 | inside the cp15 substruct | ||
16 | 3 | ||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
18 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
19 | Message-id: 20190416125744.27770-4-peter.maydell@linaro.org | 6 | Message-id: 20210617121628.20116-26-peter.maydell@linaro.org |
20 | --- | 7 | --- |
21 | target/arm/cpu.h | 34 ++++++++++++ | 8 | target/arm/helper-mve.h | 4 ++++ |
22 | hw/intc/armv7m_nvic.c | 125 ++++++++++++++++++++++++++++++++++++++++++ | 9 | target/arm/mve.decode | 1 + |
23 | target/arm/cpu.c | 5 ++ | 10 | target/arm/mve_helper.c | 43 ++++++++++++++++++++++++++++++++++++++ |
24 | target/arm/machine.c | 16 ++++++ | 11 | target/arm/translate-mve.c | 1 + |
25 | 4 files changed, 180 insertions(+) | 12 | 4 files changed, 49 insertions(+) |
26 | 13 | ||
27 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 14 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
28 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
29 | --- a/target/arm/cpu.h | 16 | --- a/target/arm/helper-mve.h |
30 | +++ b/target/arm/cpu.h | 17 | +++ b/target/arm/helper-mve.h |
31 | @@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState { | 18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vhsubu_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
32 | uint32_t scr[M_REG_NUM_BANKS]; | 19 | DEF_HELPER_FLAGS_4(mve_vhsubu_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
33 | uint32_t msplim[M_REG_NUM_BANKS]; | 20 | DEF_HELPER_FLAGS_4(mve_vhsubu_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
34 | uint32_t psplim[M_REG_NUM_BANKS]; | 21 | |
35 | + uint32_t fpcar[M_REG_NUM_BANKS]; | 22 | +DEF_HELPER_FLAGS_4(mve_vbrsrb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
36 | + uint32_t fpccr[M_REG_NUM_BANKS]; | 23 | +DEF_HELPER_FLAGS_4(mve_vbrsrh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
37 | + uint32_t fpdscr[M_REG_NUM_BANKS]; | 24 | +DEF_HELPER_FLAGS_4(mve_vbrsrw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
38 | + uint32_t cpacr[M_REG_NUM_BANKS]; | 25 | + |
39 | + uint32_t nsacr; | 26 | DEF_HELPER_FLAGS_4(mve_vmlaldavsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
40 | } v7m; | 27 | DEF_HELPER_FLAGS_4(mve_vmlaldavsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
41 | 28 | DEF_HELPER_FLAGS_4(mve_vmlaldavxsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) | |
42 | /* Information associated with an exception about to be taken: | 29 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode |
43 | @@ -XXX,XX +XXX,XX @@ FIELD(V7M_CSSELR, LEVEL, 1, 3) | 30 | index XXXXXXX..XXXXXXX 100644 |
44 | */ | 31 | --- a/target/arm/mve.decode |
45 | FIELD(V7M_CSSELR, INDEX, 0, 4) | 32 | +++ b/target/arm/mve.decode |
46 | 33 | @@ -XXX,XX +XXX,XX @@ VHADD_S_scalar 1110 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar | |
47 | +/* v7M FPCCR bits */ | 34 | VHADD_U_scalar 1111 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar |
48 | +FIELD(V7M_FPCCR, LSPACT, 0, 1) | 35 | VHSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar |
49 | +FIELD(V7M_FPCCR, USER, 1, 1) | 36 | VHSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar |
50 | +FIELD(V7M_FPCCR, S, 2, 1) | 37 | +VBRSR 1111 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar |
51 | +FIELD(V7M_FPCCR, THREAD, 3, 1) | 38 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c |
52 | +FIELD(V7M_FPCCR, HFRDY, 4, 1) | 39 | index XXXXXXX..XXXXXXX 100644 |
53 | +FIELD(V7M_FPCCR, MMRDY, 5, 1) | 40 | --- a/target/arm/mve_helper.c |
54 | +FIELD(V7M_FPCCR, BFRDY, 6, 1) | 41 | +++ b/target/arm/mve_helper.c |
55 | +FIELD(V7M_FPCCR, SFRDY, 7, 1) | 42 | @@ -XXX,XX +XXX,XX @@ DO_2OP_SCALAR_U(vhaddu_scalar, do_vhadd_u) |
56 | +FIELD(V7M_FPCCR, MONRDY, 8, 1) | 43 | DO_2OP_SCALAR_S(vhsubs_scalar, do_vhsub_s) |
57 | +FIELD(V7M_FPCCR, SPLIMVIOL, 9, 1) | 44 | DO_2OP_SCALAR_U(vhsubu_scalar, do_vhsub_u) |
58 | +FIELD(V7M_FPCCR, UFRDY, 10, 1) | 45 | |
59 | +FIELD(V7M_FPCCR, RES0, 11, 15) | 46 | +static inline uint32_t do_vbrsrb(uint32_t n, uint32_t m) |
60 | +FIELD(V7M_FPCCR, TS, 26, 1) | 47 | +{ |
61 | +FIELD(V7M_FPCCR, CLRONRETS, 27, 1) | 48 | + m &= 0xff; |
62 | +FIELD(V7M_FPCCR, CLRONRET, 28, 1) | 49 | + if (m == 0) { |
63 | +FIELD(V7M_FPCCR, LSPENS, 29, 1) | 50 | + return 0; |
64 | +FIELD(V7M_FPCCR, LSPEN, 30, 1) | 51 | + } |
65 | +FIELD(V7M_FPCCR, ASPEN, 31, 1) | 52 | + n = revbit8(n); |
66 | +/* These bits are banked. Others are non-banked and live in the M_REG_S bank */ | 53 | + if (m < 8) { |
67 | +#define R_V7M_FPCCR_BANKED_MASK \ | 54 | + n >>= 8 - m; |
68 | + (R_V7M_FPCCR_LSPACT_MASK | \ | 55 | + } |
69 | + R_V7M_FPCCR_USER_MASK | \ | 56 | + return n; |
70 | + R_V7M_FPCCR_THREAD_MASK | \ | 57 | +} |
71 | + R_V7M_FPCCR_MMRDY_MASK | \ | 58 | + |
72 | + R_V7M_FPCCR_SPLIMVIOL_MASK | \ | 59 | +static inline uint32_t do_vbrsrh(uint32_t n, uint32_t m) |
73 | + R_V7M_FPCCR_UFRDY_MASK | \ | 60 | +{ |
74 | + R_V7M_FPCCR_ASPEN_MASK) | 61 | + m &= 0xff; |
62 | + if (m == 0) { | ||
63 | + return 0; | ||
64 | + } | ||
65 | + n = revbit16(n); | ||
66 | + if (m < 16) { | ||
67 | + n >>= 16 - m; | ||
68 | + } | ||
69 | + return n; | ||
70 | +} | ||
71 | + | ||
72 | +static inline uint32_t do_vbrsrw(uint32_t n, uint32_t m) | ||
73 | +{ | ||
74 | + m &= 0xff; | ||
75 | + if (m == 0) { | ||
76 | + return 0; | ||
77 | + } | ||
78 | + n = revbit32(n); | ||
79 | + if (m < 32) { | ||
80 | + n >>= 32 - m; | ||
81 | + } | ||
82 | + return n; | ||
83 | +} | ||
84 | + | ||
85 | +DO_2OP_SCALAR(vbrsrb, 1, uint8_t, do_vbrsrb) | ||
86 | +DO_2OP_SCALAR(vbrsrh, 2, uint16_t, do_vbrsrh) | ||
87 | +DO_2OP_SCALAR(vbrsrw, 4, uint32_t, do_vbrsrw) | ||
75 | + | 88 | + |
76 | /* | 89 | /* |
77 | * System register ID fields. | 90 | * Multiply add long dual accumulate ops. |
78 | */ | 91 | */ |
79 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 92 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c |
80 | index XXXXXXX..XXXXXXX 100644 | 93 | index XXXXXXX..XXXXXXX 100644 |
81 | --- a/hw/intc/armv7m_nvic.c | 94 | --- a/target/arm/translate-mve.c |
82 | +++ b/hw/intc/armv7m_nvic.c | 95 | +++ b/target/arm/translate-mve.c |
83 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | 96 | @@ -XXX,XX +XXX,XX @@ DO_2OP_SCALAR(VHADD_S_scalar, vhadds_scalar) |
84 | } | 97 | DO_2OP_SCALAR(VHADD_U_scalar, vhaddu_scalar) |
85 | case 0xd84: /* CSSELR */ | 98 | DO_2OP_SCALAR(VHSUB_S_scalar, vhsubs_scalar) |
86 | return cpu->env.v7m.csselr[attrs.secure]; | 99 | DO_2OP_SCALAR(VHSUB_U_scalar, vhsubu_scalar) |
87 | + case 0xd88: /* CPACR */ | 100 | +DO_2OP_SCALAR(VBRSR, vbrsr) |
88 | + if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { | 101 | |
89 | + return 0; | 102 | static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, |
90 | + } | 103 | MVEGenDualAccOpFn *fn) |
91 | + return cpu->env.v7m.cpacr[attrs.secure]; | ||
92 | + case 0xd8c: /* NSACR */ | ||
93 | + if (!attrs.secure || !arm_feature(&cpu->env, ARM_FEATURE_VFP)) { | ||
94 | + return 0; | ||
95 | + } | ||
96 | + return cpu->env.v7m.nsacr; | ||
97 | /* TODO: Implement debug registers. */ | ||
98 | case 0xd90: /* MPU_TYPE */ | ||
99 | /* Unified MPU; if the MPU is not present this value is zero */ | ||
100 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | ||
101 | return 0; | ||
102 | } | ||
103 | return cpu->env.v7m.sfar; | ||
104 | + case 0xf34: /* FPCCR */ | ||
105 | + if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { | ||
106 | + return 0; | ||
107 | + } | ||
108 | + if (attrs.secure) { | ||
109 | + return cpu->env.v7m.fpccr[M_REG_S]; | ||
110 | + } else { | ||
111 | + /* | ||
112 | + * NS can read LSPEN, CLRONRET and MONRDY. It can read | ||
113 | + * BFRDY and HFRDY if AIRCR.BFHFNMINS != 0; | ||
114 | + * other non-banked bits RAZ. | ||
115 | + * TODO: MONRDY should RAZ/WI if DEMCR.SDME is set. | ||
116 | + */ | ||
117 | + uint32_t value = cpu->env.v7m.fpccr[M_REG_S]; | ||
118 | + uint32_t mask = R_V7M_FPCCR_LSPEN_MASK | | ||
119 | + R_V7M_FPCCR_CLRONRET_MASK | | ||
120 | + R_V7M_FPCCR_MONRDY_MASK; | ||
121 | + | ||
122 | + if (s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK) { | ||
123 | + mask |= R_V7M_FPCCR_BFRDY_MASK | R_V7M_FPCCR_HFRDY_MASK; | ||
124 | + } | ||
125 | + | ||
126 | + value &= mask; | ||
127 | + | ||
128 | + value |= cpu->env.v7m.fpccr[M_REG_NS]; | ||
129 | + return value; | ||
130 | + } | ||
131 | + case 0xf38: /* FPCAR */ | ||
132 | + if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { | ||
133 | + return 0; | ||
134 | + } | ||
135 | + return cpu->env.v7m.fpcar[attrs.secure]; | ||
136 | + case 0xf3c: /* FPDSCR */ | ||
137 | + if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { | ||
138 | + return 0; | ||
139 | + } | ||
140 | + return cpu->env.v7m.fpdscr[attrs.secure]; | ||
141 | case 0xf40: /* MVFR0 */ | ||
142 | return cpu->isar.mvfr0; | ||
143 | case 0xf44: /* MVFR1 */ | ||
144 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
145 | cpu->env.v7m.csselr[attrs.secure] = value & R_V7M_CSSELR_INDEX_MASK; | ||
146 | } | ||
147 | break; | ||
148 | + case 0xd88: /* CPACR */ | ||
149 | + if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { | ||
150 | + /* We implement only the Floating Point extension's CP10/CP11 */ | ||
151 | + cpu->env.v7m.cpacr[attrs.secure] = value & (0xf << 20); | ||
152 | + } | ||
153 | + break; | ||
154 | + case 0xd8c: /* NSACR */ | ||
155 | + if (attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_VFP)) { | ||
156 | + /* We implement only the Floating Point extension's CP10/CP11 */ | ||
157 | + cpu->env.v7m.nsacr = value & (3 << 10); | ||
158 | + } | ||
159 | + break; | ||
160 | case 0xd90: /* MPU_TYPE */ | ||
161 | return; /* RO */ | ||
162 | case 0xd94: /* MPU_CTRL */ | ||
163 | @@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, | ||
164 | } | ||
165 | break; | ||
166 | } | ||
167 | + case 0xf34: /* FPCCR */ | ||
168 | + if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { | ||
169 | + /* Not all bits here are banked. */ | ||
170 | + uint32_t fpccr_s; | ||
171 | + | ||
172 | + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { | ||
173 | + /* Don't allow setting of bits not present in v7M */ | ||
174 | + value &= (R_V7M_FPCCR_LSPACT_MASK | | ||
175 | + R_V7M_FPCCR_USER_MASK | | ||
176 | + R_V7M_FPCCR_THREAD_MASK | | ||
177 | + R_V7M_FPCCR_HFRDY_MASK | | ||
178 | + R_V7M_FPCCR_MMRDY_MASK | | ||
179 | + R_V7M_FPCCR_BFRDY_MASK | | ||
180 | + R_V7M_FPCCR_MONRDY_MASK | | ||
181 | + R_V7M_FPCCR_LSPEN_MASK | | ||
182 | + R_V7M_FPCCR_ASPEN_MASK); | ||
183 | + } | ||
184 | + value &= ~R_V7M_FPCCR_RES0_MASK; | ||
185 | + | ||
186 | + if (!attrs.secure) { | ||
187 | + /* Some non-banked bits are configurably writable by NS */ | ||
188 | + fpccr_s = cpu->env.v7m.fpccr[M_REG_S]; | ||
189 | + if (!(fpccr_s & R_V7M_FPCCR_LSPENS_MASK)) { | ||
190 | + uint32_t lspen = FIELD_EX32(value, V7M_FPCCR, LSPEN); | ||
191 | + fpccr_s = FIELD_DP32(fpccr_s, V7M_FPCCR, LSPEN, lspen); | ||
192 | + } | ||
193 | + if (!(fpccr_s & R_V7M_FPCCR_CLRONRETS_MASK)) { | ||
194 | + uint32_t cor = FIELD_EX32(value, V7M_FPCCR, CLRONRET); | ||
195 | + fpccr_s = FIELD_DP32(fpccr_s, V7M_FPCCR, CLRONRET, cor); | ||
196 | + } | ||
197 | + if ((s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) { | ||
198 | + uint32_t hfrdy = FIELD_EX32(value, V7M_FPCCR, HFRDY); | ||
199 | + uint32_t bfrdy = FIELD_EX32(value, V7M_FPCCR, BFRDY); | ||
200 | + fpccr_s = FIELD_DP32(fpccr_s, V7M_FPCCR, HFRDY, hfrdy); | ||
201 | + fpccr_s = FIELD_DP32(fpccr_s, V7M_FPCCR, BFRDY, bfrdy); | ||
202 | + } | ||
203 | + /* TODO MONRDY should RAZ/WI if DEMCR.SDME is set */ | ||
204 | + { | ||
205 | + uint32_t monrdy = FIELD_EX32(value, V7M_FPCCR, MONRDY); | ||
206 | + fpccr_s = FIELD_DP32(fpccr_s, V7M_FPCCR, MONRDY, monrdy); | ||
207 | + } | ||
208 | + | ||
209 | + /* | ||
210 | + * All other non-banked bits are RAZ/WI from NS; write | ||
211 | + * just the banked bits to fpccr[M_REG_NS]. | ||
212 | + */ | ||
213 | + value &= R_V7M_FPCCR_BANKED_MASK; | ||
214 | + cpu->env.v7m.fpccr[M_REG_NS] = value; | ||
215 | + } else { | ||
216 | + fpccr_s = value; | ||
217 | + } | ||
218 | + cpu->env.v7m.fpccr[M_REG_S] = fpccr_s; | ||
219 | + } | ||
220 | + break; | ||
221 | + case 0xf38: /* FPCAR */ | ||
222 | + if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { | ||
223 | + value &= ~7; | ||
224 | + cpu->env.v7m.fpcar[attrs.secure] = value; | ||
225 | + } | ||
226 | + break; | ||
227 | + case 0xf3c: /* FPDSCR */ | ||
228 | + if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { | ||
229 | + value &= 0x07c00000; | ||
230 | + cpu->env.v7m.fpdscr[attrs.secure] = value; | ||
231 | + } | ||
232 | + break; | ||
233 | case 0xf50: /* ICIALLU */ | ||
234 | case 0xf58: /* ICIMVAU */ | ||
235 | case 0xf5c: /* DCIMVAC */ | ||
236 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
237 | index XXXXXXX..XXXXXXX 100644 | ||
238 | --- a/target/arm/cpu.c | ||
239 | +++ b/target/arm/cpu.c | ||
240 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s) | ||
241 | env->v7m.ccr[M_REG_S] |= R_V7M_CCR_UNALIGN_TRP_MASK; | ||
242 | } | ||
243 | |||
244 | + if (arm_feature(env, ARM_FEATURE_VFP)) { | ||
245 | + env->v7m.fpccr[M_REG_NS] = R_V7M_FPCCR_ASPEN_MASK; | ||
246 | + env->v7m.fpccr[M_REG_S] = R_V7M_FPCCR_ASPEN_MASK | | ||
247 | + R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; | ||
248 | + } | ||
249 | /* Unlike A/R profile, M profile defines the reset LR value */ | ||
250 | env->regs[14] = 0xffffffff; | ||
251 | |||
252 | diff --git a/target/arm/machine.c b/target/arm/machine.c | ||
253 | index XXXXXXX..XXXXXXX 100644 | ||
254 | --- a/target/arm/machine.c | ||
255 | +++ b/target/arm/machine.c | ||
256 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m_v8m = { | ||
257 | } | ||
258 | }; | ||
259 | |||
260 | +static const VMStateDescription vmstate_m_fp = { | ||
261 | + .name = "cpu/m/fp", | ||
262 | + .version_id = 1, | ||
263 | + .minimum_version_id = 1, | ||
264 | + .needed = vfp_needed, | ||
265 | + .fields = (VMStateField[]) { | ||
266 | + VMSTATE_UINT32_ARRAY(env.v7m.fpcar, ARMCPU, M_REG_NUM_BANKS), | ||
267 | + VMSTATE_UINT32_ARRAY(env.v7m.fpccr, ARMCPU, M_REG_NUM_BANKS), | ||
268 | + VMSTATE_UINT32_ARRAY(env.v7m.fpdscr, ARMCPU, M_REG_NUM_BANKS), | ||
269 | + VMSTATE_UINT32_ARRAY(env.v7m.cpacr, ARMCPU, M_REG_NUM_BANKS), | ||
270 | + VMSTATE_UINT32(env.v7m.nsacr, ARMCPU), | ||
271 | + VMSTATE_END_OF_LIST() | ||
272 | + } | ||
273 | +}; | ||
274 | + | ||
275 | static const VMStateDescription vmstate_m = { | ||
276 | .name = "cpu/m", | ||
277 | .version_id = 4, | ||
278 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_m = { | ||
279 | &vmstate_m_scr, | ||
280 | &vmstate_m_other_sp, | ||
281 | &vmstate_m_v8m, | ||
282 | + &vmstate_m_fp, | ||
283 | NULL | ||
284 | } | ||
285 | }; | ||
286 | -- | 104 | -- |
287 | 2.20.1 | 105 | 2.20.1 |
288 | 106 | ||
289 | 107 | diff view generated by jsdifflib |
1 | The magic value pushed onto the callee stack as an integrity | 1 | Implement the MVE VPST insn, which sets the predicate mask |
---|---|---|---|
2 | check is different if floating point is present. | 2 | fields in the VPR to the immediate value encoded in the insn. |
3 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
6 | Message-id: 20190416125744.27770-15-peter.maydell@linaro.org | 6 | Message-id: 20210617121628.20116-27-peter.maydell@linaro.org |
7 | --- | 7 | --- |
8 | target/arm/helper.c | 22 +++++++++++++++++++--- | 8 | target/arm/mve.decode | 4 +++ |
9 | 1 file changed, 19 insertions(+), 3 deletions(-) | 9 | target/arm/translate-mve.c | 59 ++++++++++++++++++++++++++++++++++++++ |
10 | 2 files changed, 63 insertions(+) | ||
10 | 11 | ||
11 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 12 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode |
12 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
13 | --- a/target/arm/helper.c | 14 | --- a/target/arm/mve.decode |
14 | +++ b/target/arm/helper.c | 15 | +++ b/target/arm/mve.decode |
15 | @@ -XXX,XX +XXX,XX @@ load_fail: | 16 | @@ -XXX,XX +XXX,XX @@ VHADD_U_scalar 1111 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar |
16 | return false; | 17 | VHSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar |
18 | VHSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar | ||
19 | VBRSR 1111 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar | ||
20 | + | ||
21 | +# Predicate operations | ||
22 | +%mask_22_13 22:1 13:3 | ||
23 | +VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13 | ||
24 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
25 | index XXXXXXX..XXXXXXX 100644 | ||
26 | --- a/target/arm/translate-mve.c | ||
27 | +++ b/target/arm/translate-mve.c | ||
28 | @@ -XXX,XX +XXX,XX @@ static void mve_update_eci(DisasContext *s) | ||
29 | } | ||
17 | } | 30 | } |
18 | 31 | ||
19 | +static uint32_t v7m_integrity_sig(CPUARMState *env, uint32_t lr) | 32 | +static void mve_update_and_store_eci(DisasContext *s) |
20 | +{ | 33 | +{ |
21 | + /* | 34 | + /* |
22 | + * Return the integrity signature value for the callee-saves | 35 | + * For insns which don't call a helper function that will call |
23 | + * stack frame section. @lr is the exception return payload/LR value | 36 | + * mve_advance_vpt(), this version updates s->eci and also stores |
24 | + * whose FType bit forms bit 0 of the signature if FP is present. | 37 | + * it out to the CPUState field. |
25 | + */ | 38 | + */ |
26 | + uint32_t sig = 0xfefa125a; | 39 | + if (s->eci) { |
27 | + | 40 | + mve_update_eci(s); |
28 | + if (!arm_feature(env, ARM_FEATURE_VFP) || (lr & R_V7M_EXCRET_FTYPE_MASK)) { | 41 | + store_cpu_field(tcg_constant_i32(s->eci << 4), condexec_bits); |
29 | + sig |= 1; | ||
30 | + } | 42 | + } |
31 | + return sig; | ||
32 | +} | 43 | +} |
33 | + | 44 | + |
34 | static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain, | 45 | static bool mve_skip_first_beat(DisasContext *s) |
35 | bool ignore_faults) | ||
36 | { | 46 | { |
37 | @@ -XXX,XX +XXX,XX @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain, | 47 | /* Return true if PSR.ECI says we must skip the first beat of this insn */ |
38 | bool stacked_ok; | 48 | @@ -XXX,XX +XXX,XX @@ static bool trans_VRMLSLDAVH(DisasContext *s, arg_vmlaldav *a) |
39 | uint32_t limit; | 49 | }; |
40 | bool want_psp; | 50 | return do_long_dual_acc(s, a, fns[a->x]); |
41 | + uint32_t sig; | 51 | } |
42 | 52 | + | |
43 | if (dotailchain) { | 53 | +static bool trans_VPST(DisasContext *s, arg_VPST *a) |
44 | bool mode = lr & R_V7M_EXCRET_MODE_MASK; | 54 | +{ |
45 | @@ -XXX,XX +XXX,XX @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain, | 55 | + TCGv_i32 vpr; |
46 | /* Write as much of the stack frame as we can. A write failure may | 56 | + |
47 | * cause us to pend a derived exception. | 57 | + /* mask == 0 is a "related encoding" */ |
48 | */ | 58 | + if (!dc_isar_feature(aa32_mve, s) || !a->mask) { |
49 | + sig = v7m_integrity_sig(env, lr); | 59 | + return false; |
50 | stacked_ok = | 60 | + } |
51 | - v7m_stack_write(cpu, frameptr, 0xfefa125b, mmu_idx, ignore_faults) && | 61 | + if (!mve_eci_check(s) || !vfp_access_check(s)) { |
52 | + v7m_stack_write(cpu, frameptr, sig, mmu_idx, ignore_faults) && | 62 | + return true; |
53 | v7m_stack_write(cpu, frameptr + 0x8, env->regs[4], mmu_idx, | 63 | + } |
54 | ignore_faults) && | 64 | + /* |
55 | v7m_stack_write(cpu, frameptr + 0xc, env->regs[5], mmu_idx, | 65 | + * Set the VPR mask fields. We take advantage of MASK01 and MASK23 |
56 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | 66 | + * being adjacent fields in the register. |
57 | if (return_to_secure && | 67 | + * |
58 | ((excret & R_V7M_EXCRET_ES_MASK) == 0 || | 68 | + * This insn is not predicated, but it is subject to beat-wise |
59 | (excret & R_V7M_EXCRET_DCRS_MASK) == 0)) { | 69 | + * execution, and the mask is updated on the odd-numbered beats. |
60 | - uint32_t expected_sig = 0xfefa125b; | 70 | + * So if PSR.ECI says we should skip beat 1, we mustn't update the |
61 | uint32_t actual_sig; | 71 | + * 01 mask field. |
62 | 72 | + */ | |
63 | pop_ok = v7m_stack_read(cpu, &actual_sig, frameptr, mmu_idx); | 73 | + vpr = load_cpu_field(v7m.vpr); |
64 | 74 | + switch (s->eci) { | |
65 | - if (pop_ok && expected_sig != actual_sig) { | 75 | + case ECI_NONE: |
66 | + if (pop_ok && v7m_integrity_sig(env, excret) != actual_sig) { | 76 | + case ECI_A0: |
67 | /* Take a SecureFault on the current stack */ | 77 | + /* Update both 01 and 23 fields */ |
68 | env->v7m.sfsr |= R_V7M_SFSR_INVIS_MASK; | 78 | + tcg_gen_deposit_i32(vpr, vpr, |
69 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); | 79 | + tcg_constant_i32(a->mask | (a->mask << 4)), |
80 | + R_V7M_VPR_MASK01_SHIFT, | ||
81 | + R_V7M_VPR_MASK01_LENGTH + R_V7M_VPR_MASK23_LENGTH); | ||
82 | + break; | ||
83 | + case ECI_A0A1: | ||
84 | + case ECI_A0A1A2: | ||
85 | + case ECI_A0A1A2B0: | ||
86 | + /* Update only the 23 mask field */ | ||
87 | + tcg_gen_deposit_i32(vpr, vpr, | ||
88 | + tcg_constant_i32(a->mask), | ||
89 | + R_V7M_VPR_MASK23_SHIFT, R_V7M_VPR_MASK23_LENGTH); | ||
90 | + break; | ||
91 | + default: | ||
92 | + g_assert_not_reached(); | ||
93 | + } | ||
94 | + store_cpu_field(vpr, v7m.vpr); | ||
95 | + mve_update_and_store_eci(s); | ||
96 | + return true; | ||
97 | +} | ||
70 | -- | 98 | -- |
71 | 2.20.1 | 99 | 2.20.1 |
72 | 100 | ||
73 | 101 | diff view generated by jsdifflib |
1 | Handle floating point registers in exception return. | 1 | Implement the MVE VQADD and VQSUB insns, which perform saturating |
---|---|---|---|
2 | This corresponds to pseudocode functions ValidateExceptionReturn(), | 2 | addition of a scalar to each element. Note that individual bytes of |
3 | ExceptionReturn(), PopStack() and ConsumeExcStackFrame(). | 3 | each result element are used or discarded according to the predicate |
4 | mask, but FPSCR.QC is only set if the predicate mask for the lowest | ||
5 | byte of the element is set. | ||
4 | 6 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20190416125744.27770-16-peter.maydell@linaro.org | 9 | Message-id: 20210617121628.20116-28-peter.maydell@linaro.org |
8 | --- | 10 | --- |
9 | target/arm/helper.c | 142 +++++++++++++++++++++++++++++++++++++++++++- | 11 | target/arm/helper-mve.h | 16 ++++++++++ |
10 | 1 file changed, 141 insertions(+), 1 deletion(-) | 12 | target/arm/mve.decode | 5 +++ |
13 | target/arm/mve_helper.c | 62 ++++++++++++++++++++++++++++++++++++++ | ||
14 | target/arm/translate-mve.c | 4 +++ | ||
15 | 4 files changed, 87 insertions(+) | ||
11 | 16 | ||
12 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 17 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
13 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/target/arm/helper.c | 19 | --- a/target/arm/helper-mve.h |
15 | +++ b/target/arm/helper.c | 20 | +++ b/target/arm/helper-mve.h |
16 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | 21 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vhsubu_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
17 | bool rettobase = false; | 22 | DEF_HELPER_FLAGS_4(mve_vhsubu_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
18 | bool exc_secure = false; | 23 | DEF_HELPER_FLAGS_4(mve_vhsubu_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
19 | bool return_to_secure; | 24 | |
20 | + bool ftype; | 25 | +DEF_HELPER_FLAGS_4(mve_vqadds_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
21 | + bool restore_s16_s31; | 26 | +DEF_HELPER_FLAGS_4(mve_vqadds_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
22 | 27 | +DEF_HELPER_FLAGS_4(mve_vqadds_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | |
23 | /* If we're not in Handler mode then jumps to magic exception-exit | 28 | + |
24 | * addresses don't have magic behaviour. However for the v8M | 29 | +DEF_HELPER_FLAGS_4(mve_vqaddu_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
25 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | 30 | +DEF_HELPER_FLAGS_4(mve_vqaddu_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
26 | excret); | 31 | +DEF_HELPER_FLAGS_4(mve_vqaddu_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
32 | + | ||
33 | +DEF_HELPER_FLAGS_4(mve_vqsubs_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
34 | +DEF_HELPER_FLAGS_4(mve_vqsubs_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
35 | +DEF_HELPER_FLAGS_4(mve_vqsubs_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
36 | + | ||
37 | +DEF_HELPER_FLAGS_4(mve_vqsubu_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
38 | +DEF_HELPER_FLAGS_4(mve_vqsubu_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
39 | +DEF_HELPER_FLAGS_4(mve_vqsubu_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
40 | + | ||
41 | DEF_HELPER_FLAGS_4(mve_vbrsrb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
42 | DEF_HELPER_FLAGS_4(mve_vbrsrh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
43 | DEF_HELPER_FLAGS_4(mve_vbrsrw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
44 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/target/arm/mve.decode | ||
47 | +++ b/target/arm/mve.decode | ||
48 | @@ -XXX,XX +XXX,XX @@ VHADD_S_scalar 1110 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar | ||
49 | VHADD_U_scalar 1111 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar | ||
50 | VHSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar | ||
51 | VHSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar | ||
52 | + | ||
53 | +VQADD_S_scalar 1110 1110 0 . .. ... 0 ... 0 1111 . 110 .... @2scalar | ||
54 | +VQADD_U_scalar 1111 1110 0 . .. ... 0 ... 0 1111 . 110 .... @2scalar | ||
55 | +VQSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 110 .... @2scalar | ||
56 | +VQSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 110 .... @2scalar | ||
57 | VBRSR 1111 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar | ||
58 | |||
59 | # Predicate operations | ||
60 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
61 | index XXXXXXX..XXXXXXX 100644 | ||
62 | --- a/target/arm/mve_helper.c | ||
63 | +++ b/target/arm/mve_helper.c | ||
64 | @@ -XXX,XX +XXX,XX @@ DO_2OP_U(vhaddu, do_vhadd_u) | ||
65 | DO_2OP_S(vhsubs, do_vhsub_s) | ||
66 | DO_2OP_U(vhsubu, do_vhsub_u) | ||
67 | |||
68 | +static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bool *s) | ||
69 | +{ | ||
70 | + if (val > max) { | ||
71 | + *s = true; | ||
72 | + return max; | ||
73 | + } else if (val < min) { | ||
74 | + *s = true; | ||
75 | + return min; | ||
76 | + } | ||
77 | + return val; | ||
78 | +} | ||
79 | + | ||
80 | +#define DO_SQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, INT8_MIN, INT8_MAX, s) | ||
81 | +#define DO_SQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, INT16_MIN, INT16_MAX, s) | ||
82 | +#define DO_SQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, INT32_MIN, INT32_MAX, s) | ||
83 | + | ||
84 | +#define DO_UQADD_B(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT8_MAX, s) | ||
85 | +#define DO_UQADD_H(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT16_MAX, s) | ||
86 | +#define DO_UQADD_W(n, m, s) do_sat_bhw((int64_t)n + m, 0, UINT32_MAX, s) | ||
87 | + | ||
88 | +#define DO_SQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, INT8_MIN, INT8_MAX, s) | ||
89 | +#define DO_SQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, INT16_MIN, INT16_MAX, s) | ||
90 | +#define DO_SQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, INT32_MIN, INT32_MAX, s) | ||
91 | + | ||
92 | +#define DO_UQSUB_B(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT8_MAX, s) | ||
93 | +#define DO_UQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT16_MAX, s) | ||
94 | +#define DO_UQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT32_MAX, s) | ||
95 | |||
96 | #define DO_2OP_SCALAR(OP, ESIZE, TYPE, FN) \ | ||
97 | void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ | ||
98 | @@ -XXX,XX +XXX,XX @@ DO_2OP_U(vhsubu, do_vhsub_u) | ||
99 | mve_advance_vpt(env); \ | ||
27 | } | 100 | } |
28 | 101 | ||
29 | + ftype = excret & R_V7M_EXCRET_FTYPE_MASK; | 102 | +#define DO_2OP_SAT_SCALAR(OP, ESIZE, TYPE, FN) \ |
30 | + | 103 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ |
31 | + if (!arm_feature(env, ARM_FEATURE_VFP) && !ftype) { | 104 | + uint32_t rm) \ |
32 | + qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero FTYPE in exception " | 105 | + { \ |
33 | + "exit PC value 0x%" PRIx32 " is UNPREDICTABLE " | 106 | + TYPE *d = vd, *n = vn; \ |
34 | + "if FPU not present\n", | 107 | + TYPE m = rm; \ |
35 | + excret); | 108 | + uint16_t mask = mve_element_mask(env); \ |
36 | + ftype = true; | 109 | + unsigned e; \ |
110 | + bool qc = false; \ | ||
111 | + for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ | ||
112 | + bool sat = false; \ | ||
113 | + mergemask(&d[H##ESIZE(e)], FN(n[H##ESIZE(e)], m, &sat), \ | ||
114 | + mask); \ | ||
115 | + qc |= sat & mask & 1; \ | ||
116 | + } \ | ||
117 | + if (qc) { \ | ||
118 | + env->vfp.qc[0] = qc; \ | ||
119 | + } \ | ||
120 | + mve_advance_vpt(env); \ | ||
37 | + } | 121 | + } |
38 | + | 122 | + |
39 | if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | 123 | /* provide unsigned 2-op scalar helpers for all sizes */ |
40 | /* EXC_RETURN.ES validation check (R_SMFL). We must do this before | 124 | #define DO_2OP_SCALAR_U(OP, FN) \ |
41 | * we pick which FAULTMASK to clear. | 125 | DO_2OP_SCALAR(OP##b, 1, uint8_t, FN) \ |
42 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | 126 | @@ -XXX,XX +XXX,XX @@ DO_2OP_SCALAR_U(vhaddu_scalar, do_vhadd_u) |
43 | */ | 127 | DO_2OP_SCALAR_S(vhsubs_scalar, do_vhsub_s) |
44 | write_v7m_control_spsel_for_secstate(env, return_to_sp_process, exc_secure); | 128 | DO_2OP_SCALAR_U(vhsubu_scalar, do_vhsub_u) |
45 | 129 | ||
46 | + /* | 130 | +DO_2OP_SAT_SCALAR(vqaddu_scalarb, 1, uint8_t, DO_UQADD_B) |
47 | + * Clear scratch FP values left in caller saved registers; this | 131 | +DO_2OP_SAT_SCALAR(vqaddu_scalarh, 2, uint16_t, DO_UQADD_H) |
48 | + * must happen before any kind of tail chaining. | 132 | +DO_2OP_SAT_SCALAR(vqaddu_scalarw, 4, uint32_t, DO_UQADD_W) |
49 | + */ | 133 | +DO_2OP_SAT_SCALAR(vqadds_scalarb, 1, int8_t, DO_SQADD_B) |
50 | + if ((env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_CLRONRET_MASK) && | 134 | +DO_2OP_SAT_SCALAR(vqadds_scalarh, 2, int16_t, DO_SQADD_H) |
51 | + (env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK)) { | 135 | +DO_2OP_SAT_SCALAR(vqadds_scalarw, 4, int32_t, DO_SQADD_W) |
52 | + if (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_LSPACT_MASK) { | ||
53 | + env->v7m.sfsr |= R_V7M_SFSR_LSERR_MASK; | ||
54 | + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); | ||
55 | + qemu_log_mask(CPU_LOG_INT, "...taking SecureFault on existing " | ||
56 | + "stackframe: error during lazy state deactivation\n"); | ||
57 | + v7m_exception_taken(cpu, excret, true, false); | ||
58 | + return; | ||
59 | + } else { | ||
60 | + /* Clear s0..s15 and FPSCR */ | ||
61 | + int i; | ||
62 | + | 136 | + |
63 | + for (i = 0; i < 16; i += 2) { | 137 | +DO_2OP_SAT_SCALAR(vqsubu_scalarb, 1, uint8_t, DO_UQSUB_B) |
64 | + *aa32_vfp_dreg(env, i / 2) = 0; | 138 | +DO_2OP_SAT_SCALAR(vqsubu_scalarh, 2, uint16_t, DO_UQSUB_H) |
65 | + } | 139 | +DO_2OP_SAT_SCALAR(vqsubu_scalarw, 4, uint32_t, DO_UQSUB_W) |
66 | + vfp_set_fpscr(env, 0); | 140 | +DO_2OP_SAT_SCALAR(vqsubs_scalarb, 1, int8_t, DO_SQSUB_B) |
67 | + } | 141 | +DO_2OP_SAT_SCALAR(vqsubs_scalarh, 2, int16_t, DO_SQSUB_H) |
68 | + } | 142 | +DO_2OP_SAT_SCALAR(vqsubs_scalarw, 4, int32_t, DO_SQSUB_W) |
69 | + | 143 | + |
70 | if (sfault) { | 144 | static inline uint32_t do_vbrsrb(uint32_t n, uint32_t m) |
71 | env->v7m.sfsr |= R_V7M_SFSR_INVER_MASK; | 145 | { |
72 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); | 146 | m &= 0xff; |
73 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | 147 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c |
74 | } | 148 | index XXXXXXX..XXXXXXX 100644 |
75 | } | 149 | --- a/target/arm/translate-mve.c |
76 | 150 | +++ b/target/arm/translate-mve.c | |
77 | + if (!ftype) { | 151 | @@ -XXX,XX +XXX,XX @@ DO_2OP_SCALAR(VHADD_S_scalar, vhadds_scalar) |
78 | + /* FP present and we need to handle it */ | 152 | DO_2OP_SCALAR(VHADD_U_scalar, vhaddu_scalar) |
79 | + if (!return_to_secure && | 153 | DO_2OP_SCALAR(VHSUB_S_scalar, vhsubs_scalar) |
80 | + (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_LSPACT_MASK)) { | 154 | DO_2OP_SCALAR(VHSUB_U_scalar, vhsubu_scalar) |
81 | + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); | 155 | +DO_2OP_SCALAR(VQADD_S_scalar, vqadds_scalar) |
82 | + env->v7m.sfsr |= R_V7M_SFSR_LSERR_MASK; | 156 | +DO_2OP_SCALAR(VQADD_U_scalar, vqaddu_scalar) |
83 | + qemu_log_mask(CPU_LOG_INT, | 157 | +DO_2OP_SCALAR(VQSUB_S_scalar, vqsubs_scalar) |
84 | + "...taking SecureFault on existing stackframe: " | 158 | +DO_2OP_SCALAR(VQSUB_U_scalar, vqsubu_scalar) |
85 | + "Secure LSPACT set but exception return is " | 159 | DO_2OP_SCALAR(VBRSR, vbrsr) |
86 | + "not to secure state\n"); | 160 | |
87 | + v7m_exception_taken(cpu, excret, true, false); | 161 | static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, |
88 | + return; | ||
89 | + } | ||
90 | + | ||
91 | + restore_s16_s31 = return_to_secure && | ||
92 | + (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MASK); | ||
93 | + | ||
94 | + if (env->v7m.fpccr[return_to_secure] & R_V7M_FPCCR_LSPACT_MASK) { | ||
95 | + /* State in FPU is still valid, just clear LSPACT */ | ||
96 | + env->v7m.fpccr[return_to_secure] &= ~R_V7M_FPCCR_LSPACT_MASK; | ||
97 | + } else { | ||
98 | + int i; | ||
99 | + uint32_t fpscr; | ||
100 | + bool cpacr_pass, nsacr_pass; | ||
101 | + | ||
102 | + cpacr_pass = v7m_cpacr_pass(env, return_to_secure, | ||
103 | + return_to_priv); | ||
104 | + nsacr_pass = return_to_secure || | ||
105 | + extract32(env->v7m.nsacr, 10, 1); | ||
106 | + | ||
107 | + if (!cpacr_pass) { | ||
108 | + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, | ||
109 | + return_to_secure); | ||
110 | + env->v7m.cfsr[return_to_secure] |= R_V7M_CFSR_NOCP_MASK; | ||
111 | + qemu_log_mask(CPU_LOG_INT, | ||
112 | + "...taking UsageFault on existing " | ||
113 | + "stackframe: CPACR.CP10 prevents unstacking " | ||
114 | + "FP regs\n"); | ||
115 | + v7m_exception_taken(cpu, excret, true, false); | ||
116 | + return; | ||
117 | + } else if (!nsacr_pass) { | ||
118 | + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, true); | ||
119 | + env->v7m.cfsr[M_REG_S] |= R_V7M_CFSR_INVPC_MASK; | ||
120 | + qemu_log_mask(CPU_LOG_INT, | ||
121 | + "...taking Secure UsageFault on existing " | ||
122 | + "stackframe: NSACR.CP10 prevents unstacking " | ||
123 | + "FP regs\n"); | ||
124 | + v7m_exception_taken(cpu, excret, true, false); | ||
125 | + return; | ||
126 | + } | ||
127 | + | ||
128 | + for (i = 0; i < (restore_s16_s31 ? 32 : 16); i += 2) { | ||
129 | + uint32_t slo, shi; | ||
130 | + uint64_t dn; | ||
131 | + uint32_t faddr = frameptr + 0x20 + 4 * i; | ||
132 | + | ||
133 | + if (i >= 16) { | ||
134 | + faddr += 8; /* Skip the slot for the FPSCR */ | ||
135 | + } | ||
136 | + | ||
137 | + pop_ok = pop_ok && | ||
138 | + v7m_stack_read(cpu, &slo, faddr, mmu_idx) && | ||
139 | + v7m_stack_read(cpu, &shi, faddr + 4, mmu_idx); | ||
140 | + | ||
141 | + if (!pop_ok) { | ||
142 | + break; | ||
143 | + } | ||
144 | + | ||
145 | + dn = (uint64_t)shi << 32 | slo; | ||
146 | + *aa32_vfp_dreg(env, i / 2) = dn; | ||
147 | + } | ||
148 | + pop_ok = pop_ok && | ||
149 | + v7m_stack_read(cpu, &fpscr, frameptr + 0x60, mmu_idx); | ||
150 | + if (pop_ok) { | ||
151 | + vfp_set_fpscr(env, fpscr); | ||
152 | + } | ||
153 | + if (!pop_ok) { | ||
154 | + /* | ||
155 | + * These regs are 0 if security extension present; | ||
156 | + * otherwise merely UNKNOWN. We zero always. | ||
157 | + */ | ||
158 | + for (i = 0; i < (restore_s16_s31 ? 32 : 16); i += 2) { | ||
159 | + *aa32_vfp_dreg(env, i / 2) = 0; | ||
160 | + } | ||
161 | + vfp_set_fpscr(env, 0); | ||
162 | + } | ||
163 | + } | ||
164 | + } | ||
165 | + env->v7m.control[M_REG_S] = FIELD_DP32(env->v7m.control[M_REG_S], | ||
166 | + V7M_CONTROL, FPCA, !ftype); | ||
167 | + | ||
168 | /* Commit to consuming the stack frame */ | ||
169 | frameptr += 0x20; | ||
170 | + if (!ftype) { | ||
171 | + frameptr += 0x48; | ||
172 | + if (restore_s16_s31) { | ||
173 | + frameptr += 0x40; | ||
174 | + } | ||
175 | + } | ||
176 | /* Undo stack alignment (the SPREALIGN bit indicates that the original | ||
177 | * pre-exception SP was not 8-aligned and we added a padding word to | ||
178 | * align it, so we undo this by ORing in the bit that increases it | ||
179 | @@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu) | ||
180 | *frame_sp_p = frameptr; | ||
181 | } | ||
182 | /* This xpsr_write() will invalidate frame_sp_p as it may switch stack */ | ||
183 | - xpsr_write(env, xpsr, ~XPSR_SPREALIGN); | ||
184 | + xpsr_write(env, xpsr, ~(XPSR_SPREALIGN | XPSR_SFPA)); | ||
185 | + | ||
186 | + if (env->v7m.secure) { | ||
187 | + bool sfpa = xpsr & XPSR_SFPA; | ||
188 | + | ||
189 | + env->v7m.control[M_REG_S] = FIELD_DP32(env->v7m.control[M_REG_S], | ||
190 | + V7M_CONTROL, SFPA, sfpa); | ||
191 | + } | ||
192 | |||
193 | /* The restored xPSR exception field will be zero if we're | ||
194 | * resuming in Thread mode. If that doesn't match what the | ||
195 | -- | 162 | -- |
196 | 2.20.1 | 163 | 2.20.1 |
197 | 164 | ||
198 | 165 | diff view generated by jsdifflib |
1 | Move the NS TBFLAG down from bit 19 to bit 6, which has not | 1 | Implement the MVE VQDMULH and VQRDMULH scalar insns, which multiply |
---|---|---|---|
2 | been used since commit c1e3781090b9d36c60 in 2015, when we | 2 | elements by the scalar, double, possibly round, take the high half |
3 | started passing the entire MMU index in the TB flags rather | 3 | and saturate. |
4 | than just a 'privilege level' bit. | ||
5 | |||
6 | This rearrangement is not strictly necessary, but means that | ||
7 | we can put M-profile-only bits next to each other rather | ||
8 | than scattered across the flag word. | ||
9 | 4 | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
12 | Message-id: 20190416125744.27770-17-peter.maydell@linaro.org | 7 | Message-id: 20210617121628.20116-29-peter.maydell@linaro.org |
13 | --- | 8 | --- |
14 | target/arm/cpu.h | 11 ++++++----- | 9 | target/arm/helper-mve.h | 8 ++++++++ |
15 | 1 file changed, 6 insertions(+), 5 deletions(-) | 10 | target/arm/mve.decode | 3 +++ |
11 | target/arm/mve_helper.c | 25 +++++++++++++++++++++++++ | ||
12 | target/arm/translate-mve.c | 2 ++ | ||
13 | 4 files changed, 38 insertions(+) | ||
16 | 14 | ||
17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 15 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
18 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/cpu.h | 17 | --- a/target/arm/helper-mve.h |
20 | +++ b/target/arm/cpu.h | 18 | +++ b/target/arm/helper-mve.h |
21 | @@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_ANY, BE_DATA, 23, 1) | 19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqsubu_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
22 | FIELD(TBFLAG_A32, THUMB, 0, 1) | 20 | DEF_HELPER_FLAGS_4(mve_vqsubu_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
23 | FIELD(TBFLAG_A32, VECLEN, 1, 3) | 21 | DEF_HELPER_FLAGS_4(mve_vqsubu_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
24 | FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) | 22 | |
23 | +DEF_HELPER_FLAGS_4(mve_vqdmulh_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
24 | +DEF_HELPER_FLAGS_4(mve_vqdmulh_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
25 | +DEF_HELPER_FLAGS_4(mve_vqdmulh_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
26 | + | ||
27 | +DEF_HELPER_FLAGS_4(mve_vqrdmulh_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
28 | +DEF_HELPER_FLAGS_4(mve_vqrdmulh_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
29 | +DEF_HELPER_FLAGS_4(mve_vqrdmulh_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
30 | + | ||
31 | DEF_HELPER_FLAGS_4(mve_vbrsrb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
32 | DEF_HELPER_FLAGS_4(mve_vbrsrh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
33 | DEF_HELPER_FLAGS_4(mve_vbrsrw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
34 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/target/arm/mve.decode | ||
37 | +++ b/target/arm/mve.decode | ||
38 | @@ -XXX,XX +XXX,XX @@ VQSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 110 .... @2scalar | ||
39 | VQSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 110 .... @2scalar | ||
40 | VBRSR 1111 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar | ||
41 | |||
42 | +VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar | ||
43 | +VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar | ||
44 | + | ||
45 | # Predicate operations | ||
46 | %mask_22_13 22:1 13:3 | ||
47 | VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13 | ||
48 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/target/arm/mve_helper.c | ||
51 | +++ b/target/arm/mve_helper.c | ||
52 | @@ -XXX,XX +XXX,XX @@ static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bool *s) | ||
53 | #define DO_UQSUB_H(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT16_MAX, s) | ||
54 | #define DO_UQSUB_W(n, m, s) do_sat_bhw((int64_t)n - m, 0, UINT32_MAX, s) | ||
55 | |||
25 | +/* | 56 | +/* |
26 | + * Indicates whether cp register reads and writes by guest code should access | 57 | + * For QDMULH and QRDMULH we simplify "double and shift by esize" into |
27 | + * the secure or nonsecure bank of banked registers; note that this is not | 58 | + * "shift by esize-1", adjusting the QRDMULH rounding constant to match. |
28 | + * the same thing as the current security state of the processor! | ||
29 | + */ | 59 | + */ |
30 | +FIELD(TBFLAG_A32, NS, 6, 1) | 60 | +#define DO_QDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m) >> 7, \ |
31 | FIELD(TBFLAG_A32, VFPEN, 7, 1) | 61 | + INT8_MIN, INT8_MAX, s) |
32 | FIELD(TBFLAG_A32, CONDEXEC, 8, 8) | 62 | +#define DO_QDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m) >> 15, \ |
33 | FIELD(TBFLAG_A32, SCTLR_B, 16, 1) | 63 | + INT16_MIN, INT16_MAX, s) |
34 | @@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A32, SCTLR_B, 16, 1) | 64 | +#define DO_QDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m) >> 31, \ |
35 | * checks on the other bits at runtime | 65 | + INT32_MIN, INT32_MAX, s) |
36 | */ | 66 | + |
37 | FIELD(TBFLAG_A32, XSCALE_CPAR, 17, 2) | 67 | +#define DO_QRDMULH_B(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 6)) >> 7, \ |
38 | -/* Indicates whether cp register reads and writes by guest code should access | 68 | + INT8_MIN, INT8_MAX, s) |
39 | - * the secure or nonsecure bank of banked registers; note that this is not | 69 | +#define DO_QRDMULH_H(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 14)) >> 15, \ |
40 | - * the same thing as the current security state of the processor! | 70 | + INT16_MIN, INT16_MAX, s) |
41 | - */ | 71 | +#define DO_QRDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 30)) >> 31, \ |
42 | -FIELD(TBFLAG_A32, NS, 19, 1) | 72 | + INT32_MIN, INT32_MAX, s) |
43 | /* For M profile only, Handler (ie not Thread) mode */ | 73 | + |
44 | FIELD(TBFLAG_A32, HANDLER, 21, 1) | 74 | #define DO_2OP_SCALAR(OP, ESIZE, TYPE, FN) \ |
45 | /* For M profile only, whether we should generate stack-limit checks */ | 75 | void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ |
76 | uint32_t rm) \ | ||
77 | @@ -XXX,XX +XXX,XX @@ DO_2OP_SAT_SCALAR(vqsubs_scalarb, 1, int8_t, DO_SQSUB_B) | ||
78 | DO_2OP_SAT_SCALAR(vqsubs_scalarh, 2, int16_t, DO_SQSUB_H) | ||
79 | DO_2OP_SAT_SCALAR(vqsubs_scalarw, 4, int32_t, DO_SQSUB_W) | ||
80 | |||
81 | +DO_2OP_SAT_SCALAR(vqdmulh_scalarb, 1, int8_t, DO_QDMULH_B) | ||
82 | +DO_2OP_SAT_SCALAR(vqdmulh_scalarh, 2, int16_t, DO_QDMULH_H) | ||
83 | +DO_2OP_SAT_SCALAR(vqdmulh_scalarw, 4, int32_t, DO_QDMULH_W) | ||
84 | +DO_2OP_SAT_SCALAR(vqrdmulh_scalarb, 1, int8_t, DO_QRDMULH_B) | ||
85 | +DO_2OP_SAT_SCALAR(vqrdmulh_scalarh, 2, int16_t, DO_QRDMULH_H) | ||
86 | +DO_2OP_SAT_SCALAR(vqrdmulh_scalarw, 4, int32_t, DO_QRDMULH_W) | ||
87 | + | ||
88 | static inline uint32_t do_vbrsrb(uint32_t n, uint32_t m) | ||
89 | { | ||
90 | m &= 0xff; | ||
91 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
92 | index XXXXXXX..XXXXXXX 100644 | ||
93 | --- a/target/arm/translate-mve.c | ||
94 | +++ b/target/arm/translate-mve.c | ||
95 | @@ -XXX,XX +XXX,XX @@ DO_2OP_SCALAR(VQADD_S_scalar, vqadds_scalar) | ||
96 | DO_2OP_SCALAR(VQADD_U_scalar, vqaddu_scalar) | ||
97 | DO_2OP_SCALAR(VQSUB_S_scalar, vqsubs_scalar) | ||
98 | DO_2OP_SCALAR(VQSUB_U_scalar, vqsubu_scalar) | ||
99 | +DO_2OP_SCALAR(VQDMULH_scalar, vqdmulh_scalar) | ||
100 | +DO_2OP_SCALAR(VQRDMULH_scalar, vqrdmulh_scalar) | ||
101 | DO_2OP_SCALAR(VBRSR, vbrsr) | ||
102 | |||
103 | static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, | ||
46 | -- | 104 | -- |
47 | 2.20.1 | 105 | 2.20.1 |
48 | 106 | ||
49 | 107 | diff view generated by jsdifflib |
1 | For v8M floating point support, transitions from Secure | 1 | Implement the MVE VQDMULL scalar insn. This multiplies the top or |
---|---|---|---|
2 | to Non-secure state via BLNS and BLXNS must clear the | 2 | bottom half of each element by the scalar, doubles and saturates |
3 | CONTROL.SFPA bit. (This corresponds to the pseudocode | 3 | to a double-width result. |
4 | BranchToNS() function.) | 4 | |
5 | Note that this encoding overlaps with VQADD and VQSUB; it uses | ||
6 | what in VQADD and VQSUB would be the 'size=0b11' encoding. | ||
5 | 7 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20190416125744.27770-13-peter.maydell@linaro.org | 10 | Message-id: 20210617121628.20116-30-peter.maydell@linaro.org |
9 | --- | 11 | --- |
10 | target/arm/helper.c | 4 ++++ | 12 | target/arm/helper-mve.h | 5 +++ |
11 | 1 file changed, 4 insertions(+) | 13 | target/arm/mve.decode | 23 +++++++++++--- |
12 | 14 | target/arm/mve_helper.c | 65 ++++++++++++++++++++++++++++++++++++++ | |
13 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 15 | target/arm/translate-mve.c | 30 ++++++++++++++++++ |
14 | index XXXXXXX..XXXXXXX 100644 | 16 | 4 files changed, 119 insertions(+), 4 deletions(-) |
15 | --- a/target/arm/helper.c | 17 | |
16 | +++ b/target/arm/helper.c | 18 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
17 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) | 19 | index XXXXXXX..XXXXXXX 100644 |
18 | /* translate.c should have made BXNS UNDEF unless we're secure */ | 20 | --- a/target/arm/helper-mve.h |
19 | assert(env->v7m.secure); | 21 | +++ b/target/arm/helper-mve.h |
20 | 22 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vbrsrb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | |
21 | + if (!(dest & 1)) { | 23 | DEF_HELPER_FLAGS_4(mve_vbrsrh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
22 | + env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK; | 24 | DEF_HELPER_FLAGS_4(mve_vbrsrw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
23 | + } | 25 | |
24 | switch_v7m_security_state(env, dest & 1); | 26 | +DEF_HELPER_FLAGS_4(mve_vqdmullb_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
25 | env->thumb = 1; | 27 | +DEF_HELPER_FLAGS_4(mve_vqdmullb_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
26 | env->regs[15] = dest & ~1; | 28 | +DEF_HELPER_FLAGS_4(mve_vqdmullt_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
27 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) | 29 | +DEF_HELPER_FLAGS_4(mve_vqdmullt_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
28 | */ | 30 | + |
29 | write_v7m_exception(env, 1); | 31 | DEF_HELPER_FLAGS_4(mve_vmlaldavsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
30 | } | 32 | DEF_HELPER_FLAGS_4(mve_vmlaldavsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
31 | + env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK; | 33 | DEF_HELPER_FLAGS_4(mve_vmlaldavxsh, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
32 | switch_v7m_security_state(env, 0); | 34 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode |
33 | env->thumb = 1; | 35 | index XXXXXXX..XXXXXXX 100644 |
34 | env->regs[15] = dest; | 36 | --- a/target/arm/mve.decode |
37 | +++ b/target/arm/mve.decode | ||
38 | @@ -XXX,XX +XXX,XX @@ | ||
39 | %qm 5:1 1:3 | ||
40 | %qn 7:1 17:3 | ||
41 | |||
42 | +# VQDMULL has size in bit 28: 0 for 16 bit, 1 for 32 bit | ||
43 | +%size_28 28:1 !function=plus_1 | ||
44 | + | ||
45 | &vldr_vstr rn qd imm p a w size l u | ||
46 | &1op qd qm size | ||
47 | &2op qd qm qn size | ||
48 | @@ -XXX,XX +XXX,XX @@ | ||
49 | @2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0 | ||
50 | |||
51 | @2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn | ||
52 | +@2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn | ||
53 | |||
54 | # Vector loads and stores | ||
55 | |||
56 | @@ -XXX,XX +XXX,XX @@ VHADD_U_scalar 1111 1110 0 . .. ... 0 ... 0 1111 . 100 .... @2scalar | ||
57 | VHSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar | ||
58 | VHSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 100 .... @2scalar | ||
59 | |||
60 | -VQADD_S_scalar 1110 1110 0 . .. ... 0 ... 0 1111 . 110 .... @2scalar | ||
61 | -VQADD_U_scalar 1111 1110 0 . .. ... 0 ... 0 1111 . 110 .... @2scalar | ||
62 | -VQSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 110 .... @2scalar | ||
63 | -VQSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 110 .... @2scalar | ||
64 | +{ | ||
65 | + VQADD_S_scalar 1110 1110 0 . .. ... 0 ... 0 1111 . 110 .... @2scalar | ||
66 | + VQADD_U_scalar 1111 1110 0 . .. ... 0 ... 0 1111 . 110 .... @2scalar | ||
67 | + VQDMULLB_scalar 111 . 1110 0 . 11 ... 0 ... 0 1111 . 110 .... @2scalar_nosz \ | ||
68 | + size=%size_28 | ||
69 | +} | ||
70 | + | ||
71 | +{ | ||
72 | + VQSUB_S_scalar 1110 1110 0 . .. ... 0 ... 1 1111 . 110 .... @2scalar | ||
73 | + VQSUB_U_scalar 1111 1110 0 . .. ... 0 ... 1 1111 . 110 .... @2scalar | ||
74 | + VQDMULLT_scalar 111 . 1110 0 . 11 ... 0 ... 1 1111 . 110 .... @2scalar_nosz \ | ||
75 | + size=%size_28 | ||
76 | +} | ||
77 | + | ||
78 | VBRSR 1111 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar | ||
79 | |||
80 | VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar | ||
81 | VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar | ||
82 | |||
83 | + | ||
84 | # Predicate operations | ||
85 | %mask_22_13 22:1 13:3 | ||
86 | VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13 | ||
87 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
88 | index XXXXXXX..XXXXXXX 100644 | ||
89 | --- a/target/arm/mve_helper.c | ||
90 | +++ b/target/arm/mve_helper.c | ||
91 | @@ -XXX,XX +XXX,XX @@ DO_2OP_SAT_SCALAR(vqrdmulh_scalarb, 1, int8_t, DO_QRDMULH_B) | ||
92 | DO_2OP_SAT_SCALAR(vqrdmulh_scalarh, 2, int16_t, DO_QRDMULH_H) | ||
93 | DO_2OP_SAT_SCALAR(vqrdmulh_scalarw, 4, int32_t, DO_QRDMULH_W) | ||
94 | |||
95 | +/* | ||
96 | + * Long saturating scalar ops. As with DO_2OP_L, TYPE and H are for the | ||
97 | + * input (smaller) type and LESIZE, LTYPE, LH for the output (long) type. | ||
98 | + * SATMASK specifies which bits of the predicate mask matter for determining | ||
99 | + * whether to propagate a saturation indication into FPSCR.QC -- for | ||
100 | + * the 16x16->32 case we must check only the bit corresponding to the T or B | ||
101 | + * half that we used, but for the 32x32->64 case we propagate if the mask | ||
102 | + * bit is set for either half. | ||
103 | + */ | ||
104 | +#define DO_2OP_SAT_SCALAR_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \ | ||
105 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ | ||
106 | + uint32_t rm) \ | ||
107 | + { \ | ||
108 | + LTYPE *d = vd; \ | ||
109 | + TYPE *n = vn; \ | ||
110 | + TYPE m = rm; \ | ||
111 | + uint16_t mask = mve_element_mask(env); \ | ||
112 | + unsigned le; \ | ||
113 | + bool qc = false; \ | ||
114 | + for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ | ||
115 | + bool sat = false; \ | ||
116 | + LTYPE r = FN((LTYPE)n[H##ESIZE(le * 2 + TOP)], m, &sat); \ | ||
117 | + mergemask(&d[H##LESIZE(le)], r, mask); \ | ||
118 | + qc |= sat && (mask & SATMASK); \ | ||
119 | + } \ | ||
120 | + if (qc) { \ | ||
121 | + env->vfp.qc[0] = qc; \ | ||
122 | + } \ | ||
123 | + mve_advance_vpt(env); \ | ||
124 | + } | ||
125 | + | ||
126 | +static inline int32_t do_qdmullh(int16_t n, int16_t m, bool *sat) | ||
127 | +{ | ||
128 | + int64_t r = ((int64_t)n * m) * 2; | ||
129 | + return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat); | ||
130 | +} | ||
131 | + | ||
132 | +static inline int64_t do_qdmullw(int32_t n, int32_t m, bool *sat) | ||
133 | +{ | ||
134 | + /* The multiply can't overflow, but the doubling might */ | ||
135 | + int64_t r = (int64_t)n * m; | ||
136 | + if (r > INT64_MAX / 2) { | ||
137 | + *sat = true; | ||
138 | + return INT64_MAX; | ||
139 | + } else if (r < INT64_MIN / 2) { | ||
140 | + *sat = true; | ||
141 | + return INT64_MIN; | ||
142 | + } else { | ||
143 | + return r * 2; | ||
144 | + } | ||
145 | +} | ||
146 | + | ||
147 | +#define SATMASK16B 1 | ||
148 | +#define SATMASK16T (1 << 2) | ||
149 | +#define SATMASK32 ((1 << 4) | 1) | ||
150 | + | ||
151 | +DO_2OP_SAT_SCALAR_L(vqdmullb_scalarh, 0, 2, int16_t, 4, int32_t, \ | ||
152 | + do_qdmullh, SATMASK16B) | ||
153 | +DO_2OP_SAT_SCALAR_L(vqdmullb_scalarw, 0, 4, int32_t, 8, int64_t, \ | ||
154 | + do_qdmullw, SATMASK32) | ||
155 | +DO_2OP_SAT_SCALAR_L(vqdmullt_scalarh, 1, 2, int16_t, 4, int32_t, \ | ||
156 | + do_qdmullh, SATMASK16T) | ||
157 | +DO_2OP_SAT_SCALAR_L(vqdmullt_scalarw, 1, 4, int32_t, 8, int64_t, \ | ||
158 | + do_qdmullw, SATMASK32) | ||
159 | + | ||
160 | static inline uint32_t do_vbrsrb(uint32_t n, uint32_t m) | ||
161 | { | ||
162 | m &= 0xff; | ||
163 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
164 | index XXXXXXX..XXXXXXX 100644 | ||
165 | --- a/target/arm/translate-mve.c | ||
166 | +++ b/target/arm/translate-mve.c | ||
167 | @@ -XXX,XX +XXX,XX @@ DO_2OP_SCALAR(VQDMULH_scalar, vqdmulh_scalar) | ||
168 | DO_2OP_SCALAR(VQRDMULH_scalar, vqrdmulh_scalar) | ||
169 | DO_2OP_SCALAR(VBRSR, vbrsr) | ||
170 | |||
171 | +static bool trans_VQDMULLB_scalar(DisasContext *s, arg_2scalar *a) | ||
172 | +{ | ||
173 | + static MVEGenTwoOpScalarFn * const fns[] = { | ||
174 | + NULL, | ||
175 | + gen_helper_mve_vqdmullb_scalarh, | ||
176 | + gen_helper_mve_vqdmullb_scalarw, | ||
177 | + NULL, | ||
178 | + }; | ||
179 | + if (a->qd == a->qn && a->size == MO_32) { | ||
180 | + /* UNPREDICTABLE; we choose to undef */ | ||
181 | + return false; | ||
182 | + } | ||
183 | + return do_2op_scalar(s, a, fns[a->size]); | ||
184 | +} | ||
185 | + | ||
186 | +static bool trans_VQDMULLT_scalar(DisasContext *s, arg_2scalar *a) | ||
187 | +{ | ||
188 | + static MVEGenTwoOpScalarFn * const fns[] = { | ||
189 | + NULL, | ||
190 | + gen_helper_mve_vqdmullt_scalarh, | ||
191 | + gen_helper_mve_vqdmullt_scalarw, | ||
192 | + NULL, | ||
193 | + }; | ||
194 | + if (a->qd == a->qn && a->size == MO_32) { | ||
195 | + /* UNPREDICTABLE; we choose to undef */ | ||
196 | + return false; | ||
197 | + } | ||
198 | + return do_2op_scalar(s, a, fns[a->size]); | ||
199 | +} | ||
200 | + | ||
201 | static bool do_long_dual_acc(DisasContext *s, arg_vmlaldav *a, | ||
202 | MVEGenDualAccOpFn *fn) | ||
203 | { | ||
35 | -- | 204 | -- |
36 | 2.20.1 | 205 | 2.20.1 |
37 | 206 | ||
38 | 207 | diff view generated by jsdifflib |
1 | Enforce that for M-profile various FPSCR bits which are RES0 there | 1 | Implement the vector forms of the MVE VQDMULH and VQRDMULH insns. |
---|---|---|---|
2 | but have defined meanings on A-profile are never settable. This | ||
3 | ensures that M-profile code can't enable the A-profile behaviour | ||
4 | (notably vector length/stride handling) by accident. | ||
5 | 2 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20190416125744.27770-2-peter.maydell@linaro.org | 5 | Message-id: 20210617121628.20116-31-peter.maydell@linaro.org |
9 | --- | 6 | --- |
10 | target/arm/vfp_helper.c | 8 ++++++++ | 7 | target/arm/helper-mve.h | 8 ++++++++ |
11 | 1 file changed, 8 insertions(+) | 8 | target/arm/mve.decode | 3 +++ |
9 | target/arm/mve_helper.c | 27 +++++++++++++++++++++++++++ | ||
10 | target/arm/translate-mve.c | 2 ++ | ||
11 | 4 files changed, 40 insertions(+) | ||
12 | 12 | ||
13 | diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c | 13 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
14 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/vfp_helper.c | 15 | --- a/target/arm/helper-mve.h |
16 | +++ b/target/arm/vfp_helper.c | 16 | +++ b/target/arm/helper-mve.h |
17 | @@ -XXX,XX +XXX,XX @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) | 17 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vmulltub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
18 | val &= ~FPCR_FZ16; | 18 | DEF_HELPER_FLAGS_4(mve_vmulltuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
19 | DEF_HELPER_FLAGS_4(mve_vmulltuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
20 | |||
21 | +DEF_HELPER_FLAGS_4(mve_vqdmulhb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
22 | +DEF_HELPER_FLAGS_4(mve_vqdmulhh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
23 | +DEF_HELPER_FLAGS_4(mve_vqdmulhw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
24 | + | ||
25 | +DEF_HELPER_FLAGS_4(mve_vqrdmulhb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
26 | +DEF_HELPER_FLAGS_4(mve_vqrdmulhh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
27 | +DEF_HELPER_FLAGS_4(mve_vqrdmulhw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
28 | + | ||
29 | DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
30 | DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
31 | DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
32 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/target/arm/mve.decode | ||
35 | +++ b/target/arm/mve.decode | ||
36 | @@ -XXX,XX +XXX,XX @@ VMULL_BU 111 1 1110 0 . .. ... 1 ... 0 1110 . 0 . 0 ... 0 @2op | ||
37 | VMULL_TS 111 0 1110 0 . .. ... 1 ... 1 1110 . 0 . 0 ... 0 @2op | ||
38 | VMULL_TU 111 1 1110 0 . .. ... 1 ... 1 1110 . 0 . 0 ... 0 @2op | ||
39 | |||
40 | +VQDMULH 1110 1111 0 . .. ... 0 ... 0 1011 . 1 . 0 ... 0 @2op | ||
41 | +VQRDMULH 1111 1111 0 . .. ... 0 ... 0 1011 . 1 . 0 ... 0 @2op | ||
42 | + | ||
43 | # Vector miscellaneous | ||
44 | |||
45 | VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op | ||
46 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/target/arm/mve_helper.c | ||
49 | +++ b/target/arm/mve_helper.c | ||
50 | @@ -XXX,XX +XXX,XX @@ DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS) | ||
51 | mve_advance_vpt(env); \ | ||
19 | } | 52 | } |
20 | 53 | ||
21 | + if (arm_feature(env, ARM_FEATURE_M)) { | 54 | +#define DO_2OP_SAT(OP, ESIZE, TYPE, FN) \ |
22 | + /* | 55 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ |
23 | + * M profile FPSCR is RES0 for the QC, STRIDE, FZ16, LEN bits | 56 | + { \ |
24 | + * and also for the trapped-exception-handling bits IxE. | 57 | + TYPE *d = vd, *n = vn, *m = vm; \ |
25 | + */ | 58 | + uint16_t mask = mve_element_mask(env); \ |
26 | + val &= 0xf7c0009f; | 59 | + unsigned e; \ |
60 | + bool qc = false; \ | ||
61 | + for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ | ||
62 | + bool sat = false; \ | ||
63 | + TYPE r = FN(n[H##ESIZE(e)], m[H##ESIZE(e)], &sat); \ | ||
64 | + mergemask(&d[H##ESIZE(e)], r, mask); \ | ||
65 | + qc |= sat & mask & 1; \ | ||
66 | + } \ | ||
67 | + if (qc) { \ | ||
68 | + env->vfp.qc[0] = qc; \ | ||
69 | + } \ | ||
70 | + mve_advance_vpt(env); \ | ||
27 | + } | 71 | + } |
28 | + | 72 | + |
29 | /* | 73 | #define DO_AND(N, M) ((N) & (M)) |
30 | * We don't implement trapped exception handling, so the | 74 | #define DO_BIC(N, M) ((N) & ~(M)) |
31 | * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!) | 75 | #define DO_ORR(N, M) ((N) | (M)) |
76 | @@ -XXX,XX +XXX,XX @@ static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bool *s) | ||
77 | #define DO_QRDMULH_W(n, m, s) do_sat_bhw(((int64_t)n * m + (1 << 30)) >> 31, \ | ||
78 | INT32_MIN, INT32_MAX, s) | ||
79 | |||
80 | +DO_2OP_SAT(vqdmulhb, 1, int8_t, DO_QDMULH_B) | ||
81 | +DO_2OP_SAT(vqdmulhh, 2, int16_t, DO_QDMULH_H) | ||
82 | +DO_2OP_SAT(vqdmulhw, 4, int32_t, DO_QDMULH_W) | ||
83 | + | ||
84 | +DO_2OP_SAT(vqrdmulhb, 1, int8_t, DO_QRDMULH_B) | ||
85 | +DO_2OP_SAT(vqrdmulhh, 2, int16_t, DO_QRDMULH_H) | ||
86 | +DO_2OP_SAT(vqrdmulhw, 4, int32_t, DO_QRDMULH_W) | ||
87 | + | ||
88 | #define DO_2OP_SCALAR(OP, ESIZE, TYPE, FN) \ | ||
89 | void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ | ||
90 | uint32_t rm) \ | ||
91 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
92 | index XXXXXXX..XXXXXXX 100644 | ||
93 | --- a/target/arm/translate-mve.c | ||
94 | +++ b/target/arm/translate-mve.c | ||
95 | @@ -XXX,XX +XXX,XX @@ DO_2OP(VMULL_BS, vmullbs) | ||
96 | DO_2OP(VMULL_BU, vmullbu) | ||
97 | DO_2OP(VMULL_TS, vmullts) | ||
98 | DO_2OP(VMULL_TU, vmulltu) | ||
99 | +DO_2OP(VQDMULH, vqdmulh) | ||
100 | +DO_2OP(VQRDMULH, vqrdmulh) | ||
101 | |||
102 | static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, | ||
103 | MVEGenTwoOpScalarFn fn) | ||
32 | -- | 104 | -- |
33 | 2.20.1 | 105 | 2.20.1 |
34 | 106 | ||
35 | 107 | diff view generated by jsdifflib |
1 | If the floating point extension is present, then the SG instruction | 1 | Implement the vector forms of the MVE VQADD and VQSUB insns. |
---|---|---|---|
2 | must clear the CONTROL_S.SFPA bit. Implement this. | ||
3 | |||
4 | (On a no-FPU system the bit will always be zero, so we don't need | ||
5 | to make the clearing of the bit conditional on ARM_FEATURE_VFP.) | ||
6 | 2 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20190416125744.27770-8-peter.maydell@linaro.org | 5 | Message-id: 20210617121628.20116-32-peter.maydell@linaro.org |
10 | --- | 6 | --- |
11 | target/arm/helper.c | 1 + | 7 | target/arm/helper-mve.h | 16 ++++++++++++++++ |
12 | 1 file changed, 1 insertion(+) | 8 | target/arm/mve.decode | 5 +++++ |
9 | target/arm/mve_helper.c | 14 ++++++++++++++ | ||
10 | target/arm/translate-mve.c | 4 ++++ | ||
11 | 4 files changed, 39 insertions(+) | ||
13 | 12 | ||
14 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 13 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
15 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper.c | 15 | --- a/target/arm/helper-mve.h |
17 | +++ b/target/arm/helper.c | 16 | +++ b/target/arm/helper-mve.h |
18 | @@ -XXX,XX +XXX,XX @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu) | 17 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrdmulhb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
19 | qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx32 | 18 | DEF_HELPER_FLAGS_4(mve_vqrdmulhh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
20 | ", executing it\n", env->regs[15]); | 19 | DEF_HELPER_FLAGS_4(mve_vqrdmulhw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
21 | env->regs[14] &= ~1; | 20 | |
22 | + env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK; | 21 | +DEF_HELPER_FLAGS_4(mve_vqaddsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
23 | switch_v7m_security_state(env, true); | 22 | +DEF_HELPER_FLAGS_4(mve_vqaddsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
24 | xpsr_write(env, 0, XPSR_IT); | 23 | +DEF_HELPER_FLAGS_4(mve_vqaddsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
25 | env->regs[15] += 4; | 24 | + |
25 | +DEF_HELPER_FLAGS_4(mve_vqaddub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
26 | +DEF_HELPER_FLAGS_4(mve_vqadduh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
27 | +DEF_HELPER_FLAGS_4(mve_vqadduw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
28 | + | ||
29 | +DEF_HELPER_FLAGS_4(mve_vqsubsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
30 | +DEF_HELPER_FLAGS_4(mve_vqsubsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
31 | +DEF_HELPER_FLAGS_4(mve_vqsubsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
32 | + | ||
33 | +DEF_HELPER_FLAGS_4(mve_vqsubub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
34 | +DEF_HELPER_FLAGS_4(mve_vqsubuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
35 | +DEF_HELPER_FLAGS_4(mve_vqsubuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
36 | + | ||
37 | DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
38 | DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
39 | DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
40 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
41 | index XXXXXXX..XXXXXXX 100644 | ||
42 | --- a/target/arm/mve.decode | ||
43 | +++ b/target/arm/mve.decode | ||
44 | @@ -XXX,XX +XXX,XX @@ VMULL_TU 111 1 1110 0 . .. ... 1 ... 1 1110 . 0 . 0 ... 0 @2op | ||
45 | VQDMULH 1110 1111 0 . .. ... 0 ... 0 1011 . 1 . 0 ... 0 @2op | ||
46 | VQRDMULH 1111 1111 0 . .. ... 0 ... 0 1011 . 1 . 0 ... 0 @2op | ||
47 | |||
48 | +VQADD_S 111 0 1111 0 . .. ... 0 ... 0 0000 . 1 . 1 ... 0 @2op | ||
49 | +VQADD_U 111 1 1111 0 . .. ... 0 ... 0 0000 . 1 . 1 ... 0 @2op | ||
50 | +VQSUB_S 111 0 1111 0 . .. ... 0 ... 0 0010 . 1 . 1 ... 0 @2op | ||
51 | +VQSUB_U 111 1 1111 0 . .. ... 0 ... 0 0010 . 1 . 1 ... 0 @2op | ||
52 | + | ||
53 | # Vector miscellaneous | ||
54 | |||
55 | VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op | ||
56 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
57 | index XXXXXXX..XXXXXXX 100644 | ||
58 | --- a/target/arm/mve_helper.c | ||
59 | +++ b/target/arm/mve_helper.c | ||
60 | @@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqrdmulhb, 1, int8_t, DO_QRDMULH_B) | ||
61 | DO_2OP_SAT(vqrdmulhh, 2, int16_t, DO_QRDMULH_H) | ||
62 | DO_2OP_SAT(vqrdmulhw, 4, int32_t, DO_QRDMULH_W) | ||
63 | |||
64 | +DO_2OP_SAT(vqaddub, 1, uint8_t, DO_UQADD_B) | ||
65 | +DO_2OP_SAT(vqadduh, 2, uint16_t, DO_UQADD_H) | ||
66 | +DO_2OP_SAT(vqadduw, 4, uint32_t, DO_UQADD_W) | ||
67 | +DO_2OP_SAT(vqaddsb, 1, int8_t, DO_SQADD_B) | ||
68 | +DO_2OP_SAT(vqaddsh, 2, int16_t, DO_SQADD_H) | ||
69 | +DO_2OP_SAT(vqaddsw, 4, int32_t, DO_SQADD_W) | ||
70 | + | ||
71 | +DO_2OP_SAT(vqsubub, 1, uint8_t, DO_UQSUB_B) | ||
72 | +DO_2OP_SAT(vqsubuh, 2, uint16_t, DO_UQSUB_H) | ||
73 | +DO_2OP_SAT(vqsubuw, 4, uint32_t, DO_UQSUB_W) | ||
74 | +DO_2OP_SAT(vqsubsb, 1, int8_t, DO_SQSUB_B) | ||
75 | +DO_2OP_SAT(vqsubsh, 2, int16_t, DO_SQSUB_H) | ||
76 | +DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W) | ||
77 | + | ||
78 | #define DO_2OP_SCALAR(OP, ESIZE, TYPE, FN) \ | ||
79 | void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ | ||
80 | uint32_t rm) \ | ||
81 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
82 | index XXXXXXX..XXXXXXX 100644 | ||
83 | --- a/target/arm/translate-mve.c | ||
84 | +++ b/target/arm/translate-mve.c | ||
85 | @@ -XXX,XX +XXX,XX @@ DO_2OP(VMULL_TS, vmullts) | ||
86 | DO_2OP(VMULL_TU, vmulltu) | ||
87 | DO_2OP(VQDMULH, vqdmulh) | ||
88 | DO_2OP(VQRDMULH, vqrdmulh) | ||
89 | +DO_2OP(VQADD_S, vqadds) | ||
90 | +DO_2OP(VQADD_U, vqaddu) | ||
91 | +DO_2OP(VQSUB_S, vqsubs) | ||
92 | +DO_2OP(VQSUB_U, vqsubu) | ||
93 | |||
94 | static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, | ||
95 | MVEGenTwoOpScalarFn fn) | ||
26 | -- | 96 | -- |
27 | 2.20.1 | 97 | 2.20.1 |
28 | 98 | ||
29 | 99 | diff view generated by jsdifflib |
1 | The M-profile CONTROL register has two bits -- SFPA and FPCA -- | 1 | Implement the MVE VQSHL insn (encoding T4, which is the |
---|---|---|---|
2 | which relate to floating-point support, and should be RES0 otherwise. | 2 | vector-shift-by-vector version). |
3 | Handle them correctly in the MSR/MRS register access code. | 3 | |
4 | Neither is banked between security states, so they are stored | 4 | The DO_SQSHL_OP and DO_UQSHL_OP macros here are derived from |
5 | in v7m.control[M_REG_S] regardless of current security state. | 5 | the neon_helper.c code for qshl_u{8,16,32} and qshl_s{8,16,32}. |
6 | 6 | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20190416125744.27770-9-peter.maydell@linaro.org | 9 | Message-id: 20210617121628.20116-33-peter.maydell@linaro.org |
10 | --- | 10 | --- |
11 | target/arm/helper.c | 57 ++++++++++++++++++++++++++++++++++++++------- | 11 | target/arm/helper-mve.h | 8 ++++++++ |
12 | 1 file changed, 49 insertions(+), 8 deletions(-) | 12 | target/arm/mve.decode | 12 ++++++++++++ |
13 | target/arm/mve_helper.c | 34 ++++++++++++++++++++++++++++++++++ | ||
14 | target/arm/translate-mve.c | 2 ++ | ||
15 | 4 files changed, 56 insertions(+) | ||
13 | 16 | ||
14 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 17 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
15 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/helper.c | 19 | --- a/target/arm/helper-mve.h |
17 | +++ b/target/arm/helper.c | 20 | +++ b/target/arm/helper-mve.h |
18 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) | 21 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqsubub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
19 | return xpsr_read(env) & mask; | 22 | DEF_HELPER_FLAGS_4(mve_vqsubuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
20 | break; | 23 | DEF_HELPER_FLAGS_4(mve_vqsubuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
21 | case 20: /* CONTROL */ | 24 | |
22 | - return env->v7m.control[env->v7m.secure]; | 25 | +DEF_HELPER_FLAGS_4(mve_vqshlsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
23 | + { | 26 | +DEF_HELPER_FLAGS_4(mve_vqshlsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
24 | + uint32_t value = env->v7m.control[env->v7m.secure]; | 27 | +DEF_HELPER_FLAGS_4(mve_vqshlsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
25 | + if (!env->v7m.secure) { | 28 | + |
26 | + /* SFPA is RAZ/WI from NS; FPCA is stored in the M_REG_S bank */ | 29 | +DEF_HELPER_FLAGS_4(mve_vqshlub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
27 | + value |= env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK; | 30 | +DEF_HELPER_FLAGS_4(mve_vqshluh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
28 | + } | 31 | +DEF_HELPER_FLAGS_4(mve_vqshluw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
29 | + return value; | 32 | + |
30 | + } | 33 | DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
31 | case 0x94: /* CONTROL_NS */ | 34 | DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
32 | /* We have to handle this here because unprivileged Secure code | 35 | DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
33 | * can read the NS CONTROL register. | 36 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode |
34 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) | 37 | index XXXXXXX..XXXXXXX 100644 |
35 | if (!env->v7m.secure) { | 38 | --- a/target/arm/mve.decode |
36 | return 0; | 39 | +++ b/target/arm/mve.decode |
37 | } | 40 | @@ -XXX,XX +XXX,XX @@ |
38 | - return env->v7m.control[M_REG_NS]; | 41 | @2op .... .... .. size:2 .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn |
39 | + return env->v7m.control[M_REG_NS] | | 42 | @2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0 |
40 | + (env->v7m.control[M_REG_S] & R_V7M_CONTROL_FPCA_MASK); | 43 | |
44 | +# The _rev suffix indicates that Vn and Vm are reversed. This is | ||
45 | +# the case for shifts. In the Arm ARM these insns are documented | ||
46 | +# with the Vm and Vn fields in their usual places, but in the | ||
47 | +# assembly the operands are listed "backwards", ie in the order | ||
48 | +# Qd, Qm, Qn where other insns use Qd, Qn, Qm. For QEMU we choose | ||
49 | +# to consider Vm and Vn as being in different fields in the insn. | ||
50 | +# This gives us consistency with A64 and Neon. | ||
51 | +@2op_rev .... .... .. size:2 .... .... .... .... .... &2op qd=%qd qm=%qn qn=%qm | ||
52 | + | ||
53 | @2scalar .... .... .. size:2 .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn | ||
54 | @2scalar_nosz .... .... .... .... .... .... .... rm:4 &2scalar qd=%qd qn=%qn | ||
55 | |||
56 | @@ -XXX,XX +XXX,XX @@ VQADD_U 111 1 1111 0 . .. ... 0 ... 0 0000 . 1 . 1 ... 0 @2op | ||
57 | VQSUB_S 111 0 1111 0 . .. ... 0 ... 0 0010 . 1 . 1 ... 0 @2op | ||
58 | VQSUB_U 111 1 1111 0 . .. ... 0 ... 0 0010 . 1 . 1 ... 0 @2op | ||
59 | |||
60 | +VQSHL_S 111 0 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev | ||
61 | +VQSHL_U 111 1 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev | ||
62 | + | ||
63 | # Vector miscellaneous | ||
64 | |||
65 | VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op | ||
66 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
67 | index XXXXXXX..XXXXXXX 100644 | ||
68 | --- a/target/arm/mve_helper.c | ||
69 | +++ b/target/arm/mve_helper.c | ||
70 | @@ -XXX,XX +XXX,XX @@ DO_1OP(vfnegs, 8, uint64_t, DO_FNEGS) | ||
71 | mve_advance_vpt(env); \ | ||
41 | } | 72 | } |
42 | 73 | ||
43 | if (el == 0) { | 74 | +/* provide unsigned 2-op helpers for all sizes */ |
44 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) | 75 | +#define DO_2OP_SAT_U(OP, FN) \ |
45 | */ | 76 | + DO_2OP_SAT(OP##b, 1, uint8_t, FN) \ |
46 | uint32_t mask = extract32(maskreg, 8, 4); | 77 | + DO_2OP_SAT(OP##h, 2, uint16_t, FN) \ |
47 | uint32_t reg = extract32(maskreg, 0, 8); | 78 | + DO_2OP_SAT(OP##w, 4, uint32_t, FN) |
48 | + int cur_el = arm_current_el(env); | 79 | + |
49 | 80 | +/* provide signed 2-op helpers for all sizes */ | |
50 | - if (arm_current_el(env) == 0 && reg > 7) { | 81 | +#define DO_2OP_SAT_S(OP, FN) \ |
51 | - /* only xPSR sub-fields may be written by unprivileged */ | 82 | + DO_2OP_SAT(OP##b, 1, int8_t, FN) \ |
52 | + if (cur_el == 0 && reg > 7 && reg != 20) { | 83 | + DO_2OP_SAT(OP##h, 2, int16_t, FN) \ |
53 | + /* | 84 | + DO_2OP_SAT(OP##w, 4, int32_t, FN) |
54 | + * only xPSR sub-fields and CONTROL.SFPA may be written by | 85 | + |
55 | + * unprivileged code | 86 | #define DO_AND(N, M) ((N) & (M)) |
56 | + */ | 87 | #define DO_BIC(N, M) ((N) & ~(M)) |
57 | return; | 88 | #define DO_ORR(N, M) ((N) | (M)) |
58 | } | 89 | @@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsb, 1, int8_t, DO_SQSUB_B) |
59 | 90 | DO_2OP_SAT(vqsubsh, 2, int16_t, DO_SQSUB_H) | |
60 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) | 91 | DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W) |
61 | env->v7m.control[M_REG_NS] &= ~R_V7M_CONTROL_NPRIV_MASK; | 92 | |
62 | env->v7m.control[M_REG_NS] |= val & R_V7M_CONTROL_NPRIV_MASK; | 93 | +/* |
63 | } | 94 | + * This wrapper fixes up the impedance mismatch between do_sqrshl_bhs() |
64 | + /* | 95 | + * and friends wanting a uint32_t* sat and our needing a bool*. |
65 | + * SFPA is RAZ/WI from NS. FPCA is RO if NSACR.CP10 == 0, | 96 | + */ |
66 | + * RES0 if the FPU is not present, and is stored in the S bank | 97 | +#define WRAP_QRSHL_HELPER(FN, N, M, ROUND, satp) \ |
67 | + */ | 98 | + ({ \ |
68 | + if (arm_feature(env, ARM_FEATURE_VFP) && | 99 | + uint32_t su32 = 0; \ |
69 | + extract32(env->v7m.nsacr, 10, 1)) { | 100 | + typeof(N) r = FN(N, (int8_t)(M), sizeof(N) * 8, ROUND, &su32); \ |
70 | + env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_FPCA_MASK; | 101 | + if (su32) { \ |
71 | + env->v7m.control[M_REG_S] |= val & R_V7M_CONTROL_FPCA_MASK; | 102 | + *satp = true; \ |
72 | + } | 103 | + } \ |
73 | return; | 104 | + r; \ |
74 | case 0x98: /* SP_NS */ | 105 | + }) |
75 | { | 106 | + |
76 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) | 107 | +#define DO_SQSHL_OP(N, M, satp) \ |
77 | env->v7m.faultmask[env->v7m.secure] = val & 1; | 108 | + WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, false, satp) |
78 | break; | 109 | +#define DO_UQSHL_OP(N, M, satp) \ |
79 | case 20: /* CONTROL */ | 110 | + WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, false, satp) |
80 | - /* Writing to the SPSEL bit only has an effect if we are in | 111 | + |
81 | + /* | 112 | +DO_2OP_SAT_S(vqshls, DO_SQSHL_OP) |
82 | + * Writing to the SPSEL bit only has an effect if we are in | 113 | +DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP) |
83 | * thread mode; other bits can be updated by any privileged code. | 114 | + |
84 | * write_v7m_control_spsel() deals with updating the SPSEL bit in | 115 | #define DO_2OP_SCALAR(OP, ESIZE, TYPE, FN) \ |
85 | * env->v7m.control, so we only need update the others. | 116 | void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ |
86 | * For v7M, we must just ignore explicit writes to SPSEL in handler | 117 | uint32_t rm) \ |
87 | * mode; for v8M the write is permitted but will have no effect. | 118 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c |
88 | + * All these bits are writes-ignored from non-privileged code, | 119 | index XXXXXXX..XXXXXXX 100644 |
89 | + * except for SFPA. | 120 | --- a/target/arm/translate-mve.c |
90 | */ | 121 | +++ b/target/arm/translate-mve.c |
91 | - if (arm_feature(env, ARM_FEATURE_V8) || | 122 | @@ -XXX,XX +XXX,XX @@ DO_2OP(VQADD_S, vqadds) |
92 | - !arm_v7m_is_handler_mode(env)) { | 123 | DO_2OP(VQADD_U, vqaddu) |
93 | + if (cur_el > 0 && (arm_feature(env, ARM_FEATURE_V8) || | 124 | DO_2OP(VQSUB_S, vqsubs) |
94 | + !arm_v7m_is_handler_mode(env))) { | 125 | DO_2OP(VQSUB_U, vqsubu) |
95 | write_v7m_control_spsel(env, (val & R_V7M_CONTROL_SPSEL_MASK) != 0); | 126 | +DO_2OP(VQSHL_S, vqshls) |
96 | } | 127 | +DO_2OP(VQSHL_U, vqshlu) |
97 | - if (arm_feature(env, ARM_FEATURE_M_MAIN)) { | 128 | |
98 | + if (cur_el > 0 && arm_feature(env, ARM_FEATURE_M_MAIN)) { | 129 | static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, |
99 | env->v7m.control[env->v7m.secure] &= ~R_V7M_CONTROL_NPRIV_MASK; | 130 | MVEGenTwoOpScalarFn fn) |
100 | env->v7m.control[env->v7m.secure] |= val & R_V7M_CONTROL_NPRIV_MASK; | ||
101 | } | ||
102 | + if (arm_feature(env, ARM_FEATURE_VFP)) { | ||
103 | + /* | ||
104 | + * SFPA is RAZ/WI from NS or if no FPU. | ||
105 | + * FPCA is RO if NSACR.CP10 == 0, RES0 if the FPU is not present. | ||
106 | + * Both are stored in the S bank. | ||
107 | + */ | ||
108 | + if (env->v7m.secure) { | ||
109 | + env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK; | ||
110 | + env->v7m.control[M_REG_S] |= val & R_V7M_CONTROL_SFPA_MASK; | ||
111 | + } | ||
112 | + if (cur_el > 0 && | ||
113 | + (env->v7m.secure || !arm_feature(env, ARM_FEATURE_M_SECURITY) || | ||
114 | + extract32(env->v7m.nsacr, 10, 1))) { | ||
115 | + env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_FPCA_MASK; | ||
116 | + env->v7m.control[M_REG_S] |= val & R_V7M_CONTROL_FPCA_MASK; | ||
117 | + } | ||
118 | + } | ||
119 | break; | ||
120 | default: | ||
121 | bad_reg: | ||
122 | -- | 131 | -- |
123 | 2.20.1 | 132 | 2.20.1 |
124 | 133 | ||
125 | 134 | diff view generated by jsdifflib |
1 | Correct the decode of the M-profile "coprocessor and | 1 | Implement the MV VQRSHL (vector) insn. Again, the code to perform |
---|---|---|---|
2 | floating-point instructions" space: | 2 | the actual shifts is borrowed from neon_helper.c. |
3 | * op0 == 0b11 is always unallocated | ||
4 | * if the CPU has an FPU then all insns with op1 == 0b101 | ||
5 | are floating point and go to disas_vfp_insn() | ||
6 | |||
7 | For the moment we leave VLLDM and VLSTM as NOPs; in | ||
8 | a later commit we will fill in the proper implementation | ||
9 | for the case where an FPU is present. | ||
10 | 3 | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
13 | Message-id: 20190416125744.27770-7-peter.maydell@linaro.org | 6 | Message-id: 20210617121628.20116-34-peter.maydell@linaro.org |
14 | --- | 7 | --- |
15 | target/arm/translate.c | 26 ++++++++++++++++++++++---- | 8 | target/arm/helper-mve.h | 8 ++++++++ |
16 | 1 file changed, 22 insertions(+), 4 deletions(-) | 9 | target/arm/mve.decode | 3 +++ |
10 | target/arm/mve_helper.c | 6 ++++++ | ||
11 | target/arm/translate-mve.c | 2 ++ | ||
12 | 4 files changed, 19 insertions(+) | ||
17 | 13 | ||
18 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 14 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
19 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/target/arm/translate.c | 16 | --- a/target/arm/helper-mve.h |
21 | +++ b/target/arm/translate.c | 17 | +++ b/target/arm/helper-mve.h |
22 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) | 18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqshlub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
23 | case 6: case 7: case 14: case 15: | 19 | DEF_HELPER_FLAGS_4(mve_vqshluh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
24 | /* Coprocessor. */ | 20 | DEF_HELPER_FLAGS_4(mve_vqshluw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
25 | if (arm_dc_feature(s, ARM_FEATURE_M)) { | 21 | |
26 | - /* We don't currently implement M profile FP support, | 22 | +DEF_HELPER_FLAGS_4(mve_vqrshlsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
27 | - * so this entire space should give a NOCP fault, with | 23 | +DEF_HELPER_FLAGS_4(mve_vqrshlsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
28 | - * the exception of the v8M VLLDM and VLSTM insns, which | 24 | +DEF_HELPER_FLAGS_4(mve_vqrshlsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
29 | - * must be NOPs in Secure state and UNDEF in Nonsecure state. | ||
30 | + /* 0b111x_11xx_xxxx_xxxx_xxxx_xxxx_xxxx_xxxx */ | ||
31 | + if (extract32(insn, 24, 2) == 3) { | ||
32 | + goto illegal_op; /* op0 = 0b11 : unallocated */ | ||
33 | + } | ||
34 | + | 25 | + |
35 | + /* | 26 | +DEF_HELPER_FLAGS_4(mve_vqrshlub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
36 | + * Decode VLLDM and VLSTM first: these are nonstandard because: | 27 | +DEF_HELPER_FLAGS_4(mve_vqrshluh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
37 | + * * if there is no FPU then these insns must NOP in | 28 | +DEF_HELPER_FLAGS_4(mve_vqrshluw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
38 | + * Secure state and UNDEF in Nonsecure state | ||
39 | + * * if there is an FPU then these insns do not have | ||
40 | + * the usual behaviour that disas_vfp_insn() provides of | ||
41 | + * being controlled by CPACR/NSACR enable bits or the | ||
42 | + * lazy-stacking logic. | ||
43 | */ | ||
44 | if (arm_dc_feature(s, ARM_FEATURE_V8) && | ||
45 | (insn & 0xffa00f00) == 0xec200a00) { | ||
46 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) | ||
47 | /* Just NOP since FP support is not implemented */ | ||
48 | break; | ||
49 | } | ||
50 | + if (arm_dc_feature(s, ARM_FEATURE_VFP) && | ||
51 | + ((insn >> 8) & 0xe) == 10) { | ||
52 | + /* FP, and the CPU supports it */ | ||
53 | + if (disas_vfp_insn(s, insn)) { | ||
54 | + goto illegal_op; | ||
55 | + } | ||
56 | + break; | ||
57 | + } | ||
58 | + | 29 | + |
59 | /* All other insns: NOCP */ | 30 | DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
60 | gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(), | 31 | DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
61 | default_exception_el(s)); | 32 | DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
33 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/target/arm/mve.decode | ||
36 | +++ b/target/arm/mve.decode | ||
37 | @@ -XXX,XX +XXX,XX @@ VQSUB_U 111 1 1111 0 . .. ... 0 ... 0 0010 . 1 . 1 ... 0 @2op | ||
38 | VQSHL_S 111 0 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev | ||
39 | VQSHL_U 111 1 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev | ||
40 | |||
41 | +VQRSHL_S 111 0 1111 0 . .. ... 0 ... 0 0101 . 1 . 1 ... 0 @2op_rev | ||
42 | +VQRSHL_U 111 1 1111 0 . .. ... 0 ... 0 0101 . 1 . 1 ... 0 @2op_rev | ||
43 | + | ||
44 | # Vector miscellaneous | ||
45 | |||
46 | VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op | ||
47 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/target/arm/mve_helper.c | ||
50 | +++ b/target/arm/mve_helper.c | ||
51 | @@ -XXX,XX +XXX,XX @@ DO_2OP_SAT(vqsubsw, 4, int32_t, DO_SQSUB_W) | ||
52 | WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, false, satp) | ||
53 | #define DO_UQSHL_OP(N, M, satp) \ | ||
54 | WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, false, satp) | ||
55 | +#define DO_SQRSHL_OP(N, M, satp) \ | ||
56 | + WRAP_QRSHL_HELPER(do_sqrshl_bhs, N, M, true, satp) | ||
57 | +#define DO_UQRSHL_OP(N, M, satp) \ | ||
58 | + WRAP_QRSHL_HELPER(do_uqrshl_bhs, N, M, true, satp) | ||
59 | |||
60 | DO_2OP_SAT_S(vqshls, DO_SQSHL_OP) | ||
61 | DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP) | ||
62 | +DO_2OP_SAT_S(vqrshls, DO_SQRSHL_OP) | ||
63 | +DO_2OP_SAT_U(vqrshlu, DO_UQRSHL_OP) | ||
64 | |||
65 | #define DO_2OP_SCALAR(OP, ESIZE, TYPE, FN) \ | ||
66 | void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ | ||
67 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
68 | index XXXXXXX..XXXXXXX 100644 | ||
69 | --- a/target/arm/translate-mve.c | ||
70 | +++ b/target/arm/translate-mve.c | ||
71 | @@ -XXX,XX +XXX,XX @@ DO_2OP(VQSUB_S, vqsubs) | ||
72 | DO_2OP(VQSUB_U, vqsubu) | ||
73 | DO_2OP(VQSHL_S, vqshls) | ||
74 | DO_2OP(VQSHL_U, vqshlu) | ||
75 | +DO_2OP(VQRSHL_S, vqrshls) | ||
76 | +DO_2OP(VQRSHL_U, vqrshlu) | ||
77 | |||
78 | static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, | ||
79 | MVEGenTwoOpScalarFn fn) | ||
62 | -- | 80 | -- |
63 | 2.20.1 | 81 | 2.20.1 |
64 | 82 | ||
65 | 83 | diff view generated by jsdifflib |
1 | The only "system register" that M-profile floating point exposes | 1 | Implement the MVE VSHL insn (vector form). |
---|---|---|---|
2 | via the VMRS/VMRS instructions is FPSCR, and it does not have | ||
3 | the odd special case for rd==15. Add a check to ensure we only | ||
4 | expose FPSCR. | ||
5 | 2 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20190416125744.27770-5-peter.maydell@linaro.org | 5 | Message-id: 20210617121628.20116-35-peter.maydell@linaro.org |
9 | --- | 6 | --- |
10 | target/arm/translate.c | 19 +++++++++++++++++-- | 7 | target/arm/helper-mve.h | 8 ++++++++ |
11 | 1 file changed, 17 insertions(+), 2 deletions(-) | 8 | target/arm/mve.decode | 3 +++ |
9 | target/arm/mve_helper.c | 6 ++++++ | ||
10 | target/arm/translate-mve.c | 2 ++ | ||
11 | 4 files changed, 19 insertions(+) | ||
12 | 12 | ||
13 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 13 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
14 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/translate.c | 15 | --- a/target/arm/helper-mve.h |
16 | +++ b/target/arm/translate.c | 16 | +++ b/target/arm/helper-mve.h |
17 | @@ -XXX,XX +XXX,XX @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) | 17 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqsubub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
18 | } | 18 | DEF_HELPER_FLAGS_4(mve_vqsubuh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
19 | } | 19 | DEF_HELPER_FLAGS_4(mve_vqsubuw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
20 | } else { /* !dp */ | 20 | |
21 | + bool is_sysreg; | 21 | +DEF_HELPER_FLAGS_4(mve_vshlsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
22 | +DEF_HELPER_FLAGS_4(mve_vshlsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
23 | +DEF_HELPER_FLAGS_4(mve_vshlsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
22 | + | 24 | + |
23 | if ((insn & 0x6f) != 0x00) | 25 | +DEF_HELPER_FLAGS_4(mve_vshlub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
24 | return 1; | 26 | +DEF_HELPER_FLAGS_4(mve_vshluh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
25 | rn = VFP_SREG_N(insn); | 27 | +DEF_HELPER_FLAGS_4(mve_vshluw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
26 | + | 28 | + |
27 | + is_sysreg = extract32(insn, 21, 1); | 29 | DEF_HELPER_FLAGS_4(mve_vqshlsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
30 | DEF_HELPER_FLAGS_4(mve_vqshlsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
31 | DEF_HELPER_FLAGS_4(mve_vqshlsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
32 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/target/arm/mve.decode | ||
35 | +++ b/target/arm/mve.decode | ||
36 | @@ -XXX,XX +XXX,XX @@ VQADD_U 111 1 1111 0 . .. ... 0 ... 0 0000 . 1 . 1 ... 0 @2op | ||
37 | VQSUB_S 111 0 1111 0 . .. ... 0 ... 0 0010 . 1 . 1 ... 0 @2op | ||
38 | VQSUB_U 111 1 1111 0 . .. ... 0 ... 0 0010 . 1 . 1 ... 0 @2op | ||
39 | |||
40 | +VSHL_S 111 0 1111 0 . .. ... 0 ... 0 0100 . 1 . 0 ... 0 @2op_rev | ||
41 | +VSHL_U 111 1 1111 0 . .. ... 0 ... 0 0100 . 1 . 0 ... 0 @2op_rev | ||
28 | + | 42 | + |
29 | + if (arm_dc_feature(s, ARM_FEATURE_M)) { | 43 | VQSHL_S 111 0 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev |
30 | + /* | 44 | VQSHL_U 111 1 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev |
31 | + * The only M-profile VFP vmrs/vmsr sysreg is FPSCR. | 45 | |
32 | + * Writes to R15 are UNPREDICTABLE; we choose to undef. | 46 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c |
33 | + */ | 47 | index XXXXXXX..XXXXXXX 100644 |
34 | + if (is_sysreg && (rd == 15 || (rn >> 1) != ARM_VFP_FPSCR)) { | 48 | --- a/target/arm/mve_helper.c |
35 | + return 1; | 49 | +++ b/target/arm/mve_helper.c |
36 | + } | 50 | @@ -XXX,XX +XXX,XX @@ DO_2OP_U(vhaddu, do_vhadd_u) |
37 | + } | 51 | DO_2OP_S(vhsubs, do_vhsub_s) |
52 | DO_2OP_U(vhsubu, do_vhsub_u) | ||
53 | |||
54 | +#define DO_VSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL) | ||
55 | +#define DO_VSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL) | ||
38 | + | 56 | + |
39 | if (insn & ARM_CP_RW_BIT) { | 57 | +DO_2OP_S(vshls, DO_VSHLS) |
40 | /* vfp->arm */ | 58 | +DO_2OP_U(vshlu, DO_VSHLU) |
41 | - if (insn & (1 << 21)) { | 59 | + |
42 | + if (is_sysreg) { | 60 | static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bool *s) |
43 | /* system register */ | 61 | { |
44 | rn >>= 1; | 62 | if (val > max) { |
45 | 63 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | |
46 | @@ -XXX,XX +XXX,XX @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) | 64 | index XXXXXXX..XXXXXXX 100644 |
47 | } | 65 | --- a/target/arm/translate-mve.c |
48 | } else { | 66 | +++ b/target/arm/translate-mve.c |
49 | /* arm->vfp */ | 67 | @@ -XXX,XX +XXX,XX @@ DO_2OP(VQADD_S, vqadds) |
50 | - if (insn & (1 << 21)) { | 68 | DO_2OP(VQADD_U, vqaddu) |
51 | + if (is_sysreg) { | 69 | DO_2OP(VQSUB_S, vqsubs) |
52 | rn >>= 1; | 70 | DO_2OP(VQSUB_U, vqsubu) |
53 | /* system register */ | 71 | +DO_2OP(VSHL_S, vshls) |
54 | switch (rn) { | 72 | +DO_2OP(VSHL_U, vshlu) |
73 | DO_2OP(VQSHL_S, vqshls) | ||
74 | DO_2OP(VQSHL_U, vqshlu) | ||
75 | DO_2OP(VQRSHL_S, vqrshls) | ||
55 | -- | 76 | -- |
56 | 2.20.1 | 77 | 2.20.1 |
57 | 78 | ||
58 | 79 | diff view generated by jsdifflib |
1 | For M-profile the MVFR* ID registers are memory mapped, in the | 1 | Implement the MVE VRSHL insn (vector form). |
---|---|---|---|
2 | range we implement via the NVIC. Allow them to be read. | ||
3 | (If the CPU has no FPU, these registers are defined to be RAZ.) | ||
4 | 2 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20190416125744.27770-3-peter.maydell@linaro.org | 5 | Message-id: 20210617121628.20116-36-peter.maydell@linaro.org |
8 | --- | 6 | --- |
9 | hw/intc/armv7m_nvic.c | 6 ++++++ | 7 | target/arm/helper-mve.h | 8 ++++++++ |
10 | 1 file changed, 6 insertions(+) | 8 | target/arm/mve.decode | 3 +++ |
9 | target/arm/mve_helper.c | 4 ++++ | ||
10 | target/arm/translate-mve.c | 2 ++ | ||
11 | 4 files changed, 17 insertions(+) | ||
11 | 12 | ||
12 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 13 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
13 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/hw/intc/armv7m_nvic.c | 15 | --- a/target/arm/helper-mve.h |
15 | +++ b/hw/intc/armv7m_nvic.c | 16 | +++ b/target/arm/helper-mve.h |
16 | @@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) | 17 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vshlub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
17 | return 0; | 18 | DEF_HELPER_FLAGS_4(mve_vshluh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
18 | } | 19 | DEF_HELPER_FLAGS_4(mve_vshluw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
19 | return cpu->env.v7m.sfar; | 20 | |
20 | + case 0xf40: /* MVFR0 */ | 21 | +DEF_HELPER_FLAGS_4(mve_vrshlsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
21 | + return cpu->isar.mvfr0; | 22 | +DEF_HELPER_FLAGS_4(mve_vrshlsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
22 | + case 0xf44: /* MVFR1 */ | 23 | +DEF_HELPER_FLAGS_4(mve_vrshlsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
23 | + return cpu->isar.mvfr1; | 24 | + |
24 | + case 0xf48: /* MVFR2 */ | 25 | +DEF_HELPER_FLAGS_4(mve_vrshlub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
25 | + return cpu->isar.mvfr2; | 26 | +DEF_HELPER_FLAGS_4(mve_vrshluh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
26 | default: | 27 | +DEF_HELPER_FLAGS_4(mve_vrshluw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
27 | bad_offset: | 28 | + |
28 | qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset); | 29 | DEF_HELPER_FLAGS_4(mve_vqshlsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
30 | DEF_HELPER_FLAGS_4(mve_vqshlsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
31 | DEF_HELPER_FLAGS_4(mve_vqshlsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
32 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/target/arm/mve.decode | ||
35 | +++ b/target/arm/mve.decode | ||
36 | @@ -XXX,XX +XXX,XX @@ VQSUB_U 111 1 1111 0 . .. ... 0 ... 0 0010 . 1 . 1 ... 0 @2op | ||
37 | VSHL_S 111 0 1111 0 . .. ... 0 ... 0 0100 . 1 . 0 ... 0 @2op_rev | ||
38 | VSHL_U 111 1 1111 0 . .. ... 0 ... 0 0100 . 1 . 0 ... 0 @2op_rev | ||
39 | |||
40 | +VRSHL_S 111 0 1111 0 . .. ... 0 ... 0 0101 . 1 . 0 ... 0 @2op_rev | ||
41 | +VRSHL_U 111 1 1111 0 . .. ... 0 ... 0 0101 . 1 . 0 ... 0 @2op_rev | ||
42 | + | ||
43 | VQSHL_S 111 0 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev | ||
44 | VQSHL_U 111 1 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev | ||
45 | |||
46 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/target/arm/mve_helper.c | ||
49 | +++ b/target/arm/mve_helper.c | ||
50 | @@ -XXX,XX +XXX,XX @@ DO_2OP_U(vhsubu, do_vhsub_u) | ||
51 | |||
52 | #define DO_VSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL) | ||
53 | #define DO_VSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, false, NULL) | ||
54 | +#define DO_VRSHLS(N, M) do_sqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true, NULL) | ||
55 | +#define DO_VRSHLU(N, M) do_uqrshl_bhs(N, (int8_t)(M), sizeof(N) * 8, true, NULL) | ||
56 | |||
57 | DO_2OP_S(vshls, DO_VSHLS) | ||
58 | DO_2OP_U(vshlu, DO_VSHLU) | ||
59 | +DO_2OP_S(vrshls, DO_VRSHLS) | ||
60 | +DO_2OP_U(vrshlu, DO_VRSHLU) | ||
61 | |||
62 | static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bool *s) | ||
63 | { | ||
64 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
65 | index XXXXXXX..XXXXXXX 100644 | ||
66 | --- a/target/arm/translate-mve.c | ||
67 | +++ b/target/arm/translate-mve.c | ||
68 | @@ -XXX,XX +XXX,XX @@ DO_2OP(VQSUB_S, vqsubs) | ||
69 | DO_2OP(VQSUB_U, vqsubu) | ||
70 | DO_2OP(VSHL_S, vshls) | ||
71 | DO_2OP(VSHL_U, vshlu) | ||
72 | +DO_2OP(VRSHL_S, vrshls) | ||
73 | +DO_2OP(VRSHL_U, vrshlu) | ||
74 | DO_2OP(VQSHL_S, vqshls) | ||
75 | DO_2OP(VQSHL_U, vqshlu) | ||
76 | DO_2OP(VQRSHL_S, vqrshls) | ||
29 | -- | 77 | -- |
30 | 2.20.1 | 78 | 2.20.1 |
31 | 79 | ||
32 | 80 | diff view generated by jsdifflib |
1 | Implement the code which updates the FPCCR register on an | 1 | Implement the MVE VQDMLADH and VQRDMLADH insns. These multiply |
---|---|---|---|
2 | exception entry where we are going to use lazy FP stacking. | 2 | elements, and then add pairs of products, double, possibly round, |
3 | We have to defer to the NVIC to determine whether the | 3 | saturate and return the high half of the result. |
4 | various exceptions are currently ready or not. | ||
5 | 4 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Message-id: 20190416125744.27770-12-peter.maydell@linaro.org | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Message-id: 20210617121628.20116-37-peter.maydell@linaro.org | ||
8 | --- | 8 | --- |
9 | target/arm/cpu.h | 14 +++++++++ | 9 | target/arm/helper-mve.h | 16 +++++++ |
10 | hw/intc/armv7m_nvic.c | 34 ++++++++++++++++++++++ | 10 | target/arm/mve.decode | 5 +++ |
11 | target/arm/helper.c | 67 ++++++++++++++++++++++++++++++++++++++++++- | 11 | target/arm/mve_helper.c | 89 ++++++++++++++++++++++++++++++++++++++ |
12 | 3 files changed, 114 insertions(+), 1 deletion(-) | 12 | target/arm/translate-mve.c | 4 ++ |
13 | 4 files changed, 114 insertions(+) | ||
13 | 14 | ||
14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 15 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
15 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/cpu.h | 17 | --- a/target/arm/helper-mve.h |
17 | +++ b/target/arm/cpu.h | 18 | +++ b/target/arm/helper-mve.h |
18 | @@ -XXX,XX +XXX,XX @@ void armv7m_nvic_acknowledge_irq(void *opaque); | 19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrshlub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
19 | * (Ignoring -1, this is the same as the RETTOBASE value before completion.) | 20 | DEF_HELPER_FLAGS_4(mve_vqrshluh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
20 | */ | 21 | DEF_HELPER_FLAGS_4(mve_vqrshluw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
21 | int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure); | 22 | |
22 | +/** | 23 | +DEF_HELPER_FLAGS_4(mve_vqdmladhb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
23 | + * armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | 24 | +DEF_HELPER_FLAGS_4(mve_vqdmladhh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
24 | + * @opaque: the NVIC | 25 | +DEF_HELPER_FLAGS_4(mve_vqdmladhw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
25 | + * @irq: the exception number to mark pending | 26 | + |
26 | + * @secure: false for non-banked exceptions or for the nonsecure | 27 | +DEF_HELPER_FLAGS_4(mve_vqdmladhxb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
27 | + * version of a banked exception, true for the secure version of a banked | 28 | +DEF_HELPER_FLAGS_4(mve_vqdmladhxh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
28 | + * exception. | 29 | +DEF_HELPER_FLAGS_4(mve_vqdmladhxw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
29 | + * | 30 | + |
30 | + * Return whether an exception is "ready", i.e. whether the exception is | 31 | +DEF_HELPER_FLAGS_4(mve_vqrdmladhb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
31 | + * enabled and is configured at a priority which would allow it to | 32 | +DEF_HELPER_FLAGS_4(mve_vqrdmladhh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
32 | + * interrupt the current execution priority. This controls whether the | 33 | +DEF_HELPER_FLAGS_4(mve_vqrdmladhw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
33 | + * RDY bit for it in the FPCCR is set. | 34 | + |
35 | +DEF_HELPER_FLAGS_4(mve_vqrdmladhxb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
36 | +DEF_HELPER_FLAGS_4(mve_vqrdmladhxh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
37 | +DEF_HELPER_FLAGS_4(mve_vqrdmladhxw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
38 | + | ||
39 | DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
40 | DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
41 | DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
42 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/target/arm/mve.decode | ||
45 | +++ b/target/arm/mve.decode | ||
46 | @@ -XXX,XX +XXX,XX @@ VQSHL_U 111 1 1111 0 . .. ... 0 ... 0 0100 . 1 . 1 ... 0 @2op_rev | ||
47 | VQRSHL_S 111 0 1111 0 . .. ... 0 ... 0 0101 . 1 . 1 ... 0 @2op_rev | ||
48 | VQRSHL_U 111 1 1111 0 . .. ... 0 ... 0 0101 . 1 . 1 ... 0 @2op_rev | ||
49 | |||
50 | +VQDMLADH 1110 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 0 @2op | ||
51 | +VQDMLADHX 1110 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 0 @2op | ||
52 | +VQRDMLADH 1110 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 1 @2op | ||
53 | +VQRDMLADHX 1110 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 1 @2op | ||
54 | + | ||
55 | # Vector miscellaneous | ||
56 | |||
57 | VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op | ||
58 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
59 | index XXXXXXX..XXXXXXX 100644 | ||
60 | --- a/target/arm/mve_helper.c | ||
61 | +++ b/target/arm/mve_helper.c | ||
62 | @@ -XXX,XX +XXX,XX @@ DO_2OP_SAT_U(vqshlu, DO_UQSHL_OP) | ||
63 | DO_2OP_SAT_S(vqrshls, DO_SQRSHL_OP) | ||
64 | DO_2OP_SAT_U(vqrshlu, DO_UQRSHL_OP) | ||
65 | |||
66 | +/* | ||
67 | + * Multiply add dual returning high half | ||
68 | + * The 'FN' here takes four inputs A, B, C, D, a 0/1 indicator of | ||
69 | + * whether to add the rounding constant, and the pointer to the | ||
70 | + * saturation flag, and should do "(A * B + C * D) * 2 + rounding constant", | ||
71 | + * saturate to twice the input size and return the high half; or | ||
72 | + * (A * B - C * D) etc for VQDMLSDH. | ||
34 | + */ | 73 | + */ |
35 | +bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure); | 74 | +#define DO_VQDMLADH_OP(OP, ESIZE, TYPE, XCHG, ROUND, FN) \ |
36 | /** | 75 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ |
37 | * armv7m_nvic_raw_execution_priority: return the raw execution priority | 76 | + void *vm) \ |
38 | * @opaque: the NVIC | 77 | + { \ |
39 | diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c | 78 | + TYPE *d = vd, *n = vn, *m = vm; \ |
40 | index XXXXXXX..XXXXXXX 100644 | 79 | + uint16_t mask = mve_element_mask(env); \ |
41 | --- a/hw/intc/armv7m_nvic.c | 80 | + unsigned e; \ |
42 | +++ b/hw/intc/armv7m_nvic.c | 81 | + bool qc = false; \ |
43 | @@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure) | 82 | + for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ |
44 | return ret; | 83 | + bool sat = false; \ |
45 | } | 84 | + if ((e & 1) == XCHG) { \ |
46 | 85 | + TYPE r = FN(n[H##ESIZE(e)], \ | |
47 | +bool armv7m_nvic_get_ready_status(void *opaque, int irq, bool secure) | 86 | + m[H##ESIZE(e - XCHG)], \ |
48 | +{ | 87 | + n[H##ESIZE(e + (1 - 2 * XCHG))], \ |
49 | + /* | 88 | + m[H##ESIZE(e + (1 - XCHG))], \ |
50 | + * Return whether an exception is "ready", i.e. it is enabled and is | 89 | + ROUND, &sat); \ |
51 | + * configured at a priority which would allow it to interrupt the | 90 | + mergemask(&d[H##ESIZE(e)], r, mask); \ |
52 | + * current execution priority. | 91 | + qc |= sat & mask & 1; \ |
53 | + * | 92 | + } \ |
54 | + * irq and secure have the same semantics as for armv7m_nvic_set_pending(): | 93 | + } \ |
55 | + * for non-banked exceptions secure is always false; for banked exceptions | 94 | + if (qc) { \ |
56 | + * it indicates which of the exceptions is required. | 95 | + env->vfp.qc[0] = qc; \ |
57 | + */ | 96 | + } \ |
58 | + NVICState *s = (NVICState *)opaque; | 97 | + mve_advance_vpt(env); \ |
59 | + bool banked = exc_is_banked(irq); | ||
60 | + VecInfo *vec; | ||
61 | + int running = nvic_exec_prio(s); | ||
62 | + | ||
63 | + assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq); | ||
64 | + assert(!secure || banked); | ||
65 | + | ||
66 | + /* | ||
67 | + * HardFault is an odd special case: we always check against -1, | ||
68 | + * even if we're secure and HardFault has priority -3; we never | ||
69 | + * need to check for enabled state. | ||
70 | + */ | ||
71 | + if (irq == ARMV7M_EXCP_HARD) { | ||
72 | + return running > -1; | ||
73 | + } | 98 | + } |
74 | + | 99 | + |
75 | + vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq]; | 100 | +static int8_t do_vqdmladh_b(int8_t a, int8_t b, int8_t c, int8_t d, |
76 | + | 101 | + int round, bool *sat) |
77 | + return vec->enabled && | 102 | +{ |
78 | + exc_group_prio(s, vec->prio, secure) < running; | 103 | + int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 7); |
104 | + return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; | ||
79 | +} | 105 | +} |
80 | + | 106 | + |
81 | /* callback when external interrupt line is changed */ | 107 | +static int16_t do_vqdmladh_h(int16_t a, int16_t b, int16_t c, int16_t d, |
82 | static void set_irq_level(void *opaque, int n, int level) | 108 | + int round, bool *sat) |
83 | { | ||
84 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
85 | index XXXXXXX..XXXXXXX 100644 | ||
86 | --- a/target/arm/helper.c | ||
87 | +++ b/target/arm/helper.c | ||
88 | @@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain, | ||
89 | env->thumb = addr & 1; | ||
90 | } | ||
91 | |||
92 | +static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr, | ||
93 | + bool apply_splim) | ||
94 | +{ | 109 | +{ |
95 | + /* | 110 | + int64_t r = ((int64_t)a * b + (int64_t)c * d) * 2 + (round << 15); |
96 | + * Like the pseudocode UpdateFPCCR: save state in FPCAR and FPCCR | 111 | + return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; |
97 | + * that we will need later in order to do lazy FP reg stacking. | ||
98 | + */ | ||
99 | + bool is_secure = env->v7m.secure; | ||
100 | + void *nvic = env->nvic; | ||
101 | + /* | ||
102 | + * Some bits are unbanked and live always in fpccr[M_REG_S]; some bits | ||
103 | + * are banked and we want to update the bit in the bank for the | ||
104 | + * current security state; and in one case we want to specifically | ||
105 | + * update the NS banked version of a bit even if we are secure. | ||
106 | + */ | ||
107 | + uint32_t *fpccr_s = &env->v7m.fpccr[M_REG_S]; | ||
108 | + uint32_t *fpccr_ns = &env->v7m.fpccr[M_REG_NS]; | ||
109 | + uint32_t *fpccr = &env->v7m.fpccr[is_secure]; | ||
110 | + bool hfrdy, bfrdy, mmrdy, ns_ufrdy, s_ufrdy, sfrdy, monrdy; | ||
111 | + | ||
112 | + env->v7m.fpcar[is_secure] = frameptr & ~0x7; | ||
113 | + | ||
114 | + if (apply_splim && arm_feature(env, ARM_FEATURE_V8)) { | ||
115 | + bool splimviol; | ||
116 | + uint32_t splim = v7m_sp_limit(env); | ||
117 | + bool ign = armv7m_nvic_neg_prio_requested(nvic, is_secure) && | ||
118 | + (env->v7m.ccr[is_secure] & R_V7M_CCR_STKOFHFNMIGN_MASK); | ||
119 | + | ||
120 | + splimviol = !ign && frameptr < splim; | ||
121 | + *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, SPLIMVIOL, splimviol); | ||
122 | + } | ||
123 | + | ||
124 | + *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, LSPACT, 1); | ||
125 | + | ||
126 | + *fpccr_s = FIELD_DP32(*fpccr_s, V7M_FPCCR, S, is_secure); | ||
127 | + | ||
128 | + *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, USER, arm_current_el(env) == 0); | ||
129 | + | ||
130 | + *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, THREAD, | ||
131 | + !arm_v7m_is_handler_mode(env)); | ||
132 | + | ||
133 | + hfrdy = armv7m_nvic_get_ready_status(nvic, ARMV7M_EXCP_HARD, false); | ||
134 | + *fpccr_s = FIELD_DP32(*fpccr_s, V7M_FPCCR, HFRDY, hfrdy); | ||
135 | + | ||
136 | + bfrdy = armv7m_nvic_get_ready_status(nvic, ARMV7M_EXCP_BUS, false); | ||
137 | + *fpccr_s = FIELD_DP32(*fpccr_s, V7M_FPCCR, BFRDY, bfrdy); | ||
138 | + | ||
139 | + mmrdy = armv7m_nvic_get_ready_status(nvic, ARMV7M_EXCP_MEM, is_secure); | ||
140 | + *fpccr = FIELD_DP32(*fpccr, V7M_FPCCR, MMRDY, mmrdy); | ||
141 | + | ||
142 | + ns_ufrdy = armv7m_nvic_get_ready_status(nvic, ARMV7M_EXCP_USAGE, false); | ||
143 | + *fpccr_ns = FIELD_DP32(*fpccr_ns, V7M_FPCCR, UFRDY, ns_ufrdy); | ||
144 | + | ||
145 | + monrdy = armv7m_nvic_get_ready_status(nvic, ARMV7M_EXCP_DEBUG, false); | ||
146 | + *fpccr_s = FIELD_DP32(*fpccr_s, V7M_FPCCR, MONRDY, monrdy); | ||
147 | + | ||
148 | + if (arm_feature(env, ARM_FEATURE_M_SECURITY)) { | ||
149 | + s_ufrdy = armv7m_nvic_get_ready_status(nvic, ARMV7M_EXCP_USAGE, true); | ||
150 | + *fpccr_s = FIELD_DP32(*fpccr_s, V7M_FPCCR, UFRDY, s_ufrdy); | ||
151 | + | ||
152 | + sfrdy = armv7m_nvic_get_ready_status(nvic, ARMV7M_EXCP_SECURE, false); | ||
153 | + *fpccr_s = FIELD_DP32(*fpccr_s, V7M_FPCCR, SFRDY, sfrdy); | ||
154 | + } | ||
155 | +} | 112 | +} |
156 | + | 113 | + |
157 | static bool v7m_push_stack(ARMCPU *cpu) | 114 | +static int32_t do_vqdmladh_w(int32_t a, int32_t b, int32_t c, int32_t d, |
158 | { | 115 | + int round, bool *sat) |
159 | /* Do the "set up stack frame" part of exception entry, | 116 | +{ |
160 | @@ -XXX,XX +XXX,XX @@ static bool v7m_push_stack(ARMCPU *cpu) | 117 | + int64_t m1 = (int64_t)a * b; |
161 | } | 118 | + int64_t m2 = (int64_t)c * d; |
162 | } else { | 119 | + int64_t r; |
163 | /* Lazy stacking enabled, save necessary info to stack later */ | 120 | + /* |
164 | - /* TODO : equivalent of UpdateFPCCR() pseudocode */ | 121 | + * Architecturally we should do the entire add, double, round |
165 | + v7m_update_fpccr(env, frameptr + 0x20, true); | 122 | + * and then check for saturation. We do three saturating adds, |
166 | } | 123 | + * but we need to be careful about the order. If the first |
167 | } | 124 | + * m1 + m2 saturates then it's impossible for the *2+rc to |
168 | } | 125 | + * bring it back into the non-saturated range. However, if |
126 | + * m1 + m2 is negative then it's possible that doing the doubling | ||
127 | + * would take the intermediate result below INT64_MAX and the | ||
128 | + * addition of the rounding constant then brings it back in range. | ||
129 | + * So we add half the rounding constant before doubling rather | ||
130 | + * than adding the rounding constant after the doubling. | ||
131 | + */ | ||
132 | + if (sadd64_overflow(m1, m2, &r) || | ||
133 | + sadd64_overflow(r, (round << 30), &r) || | ||
134 | + sadd64_overflow(r, r, &r)) { | ||
135 | + *sat = true; | ||
136 | + return r < 0 ? INT32_MAX : INT32_MIN; | ||
137 | + } | ||
138 | + return r >> 32; | ||
139 | +} | ||
140 | + | ||
141 | +DO_VQDMLADH_OP(vqdmladhb, 1, int8_t, 0, 0, do_vqdmladh_b) | ||
142 | +DO_VQDMLADH_OP(vqdmladhh, 2, int16_t, 0, 0, do_vqdmladh_h) | ||
143 | +DO_VQDMLADH_OP(vqdmladhw, 4, int32_t, 0, 0, do_vqdmladh_w) | ||
144 | +DO_VQDMLADH_OP(vqdmladhxb, 1, int8_t, 1, 0, do_vqdmladh_b) | ||
145 | +DO_VQDMLADH_OP(vqdmladhxh, 2, int16_t, 1, 0, do_vqdmladh_h) | ||
146 | +DO_VQDMLADH_OP(vqdmladhxw, 4, int32_t, 1, 0, do_vqdmladh_w) | ||
147 | + | ||
148 | +DO_VQDMLADH_OP(vqrdmladhb, 1, int8_t, 0, 1, do_vqdmladh_b) | ||
149 | +DO_VQDMLADH_OP(vqrdmladhh, 2, int16_t, 0, 1, do_vqdmladh_h) | ||
150 | +DO_VQDMLADH_OP(vqrdmladhw, 4, int32_t, 0, 1, do_vqdmladh_w) | ||
151 | +DO_VQDMLADH_OP(vqrdmladhxb, 1, int8_t, 1, 1, do_vqdmladh_b) | ||
152 | +DO_VQDMLADH_OP(vqrdmladhxh, 2, int16_t, 1, 1, do_vqdmladh_h) | ||
153 | +DO_VQDMLADH_OP(vqrdmladhxw, 4, int32_t, 1, 1, do_vqdmladh_w) | ||
154 | + | ||
155 | #define DO_2OP_SCALAR(OP, ESIZE, TYPE, FN) \ | ||
156 | void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ | ||
157 | uint32_t rm) \ | ||
158 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
159 | index XXXXXXX..XXXXXXX 100644 | ||
160 | --- a/target/arm/translate-mve.c | ||
161 | +++ b/target/arm/translate-mve.c | ||
162 | @@ -XXX,XX +XXX,XX @@ DO_2OP(VQSHL_S, vqshls) | ||
163 | DO_2OP(VQSHL_U, vqshlu) | ||
164 | DO_2OP(VQRSHL_S, vqrshls) | ||
165 | DO_2OP(VQRSHL_U, vqrshlu) | ||
166 | +DO_2OP(VQDMLADH, vqdmladh) | ||
167 | +DO_2OP(VQDMLADHX, vqdmladhx) | ||
168 | +DO_2OP(VQRDMLADH, vqrdmladh) | ||
169 | +DO_2OP(VQRDMLADHX, vqrdmladhx) | ||
170 | |||
171 | static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, | ||
172 | MVEGenTwoOpScalarFn fn) | ||
169 | -- | 173 | -- |
170 | 2.20.1 | 174 | 2.20.1 |
171 | 175 | ||
172 | 176 | diff view generated by jsdifflib |
1 | Implement the VLLDM instruction for v7M for the FPU present cas. | 1 | Implement the MVE VQDMLSDH and VQRDMLSDH insns, which are |
---|---|---|---|
2 | like VQDMLADH and VQRDMLADH except that products are subtracted | ||
3 | rather than added. | ||
2 | 4 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 20190416125744.27770-26-peter.maydell@linaro.org | 7 | Message-id: 20210617121628.20116-38-peter.maydell@linaro.org |
6 | --- | 8 | --- |
7 | target/arm/helper.h | 1 + | 9 | target/arm/helper-mve.h | 16 ++++++++++++++ |
8 | target/arm/helper.c | 54 ++++++++++++++++++++++++++++++++++++++++++ | 10 | target/arm/mve.decode | 5 +++++ |
9 | target/arm/translate.c | 2 +- | 11 | target/arm/mve_helper.c | 44 ++++++++++++++++++++++++++++++++++++++ |
10 | 3 files changed, 56 insertions(+), 1 deletion(-) | 12 | target/arm/translate-mve.c | 4 ++++ |
13 | 4 files changed, 69 insertions(+) | ||
11 | 14 | ||
12 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 15 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
13 | index XXXXXXX..XXXXXXX 100644 | 16 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/target/arm/helper.h | 17 | --- a/target/arm/helper-mve.h |
15 | +++ b/target/arm/helper.h | 18 | +++ b/target/arm/helper-mve.h |
16 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(v7m_tt, i32, env, i32, i32) | 19 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrdmladhxb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
17 | DEF_HELPER_1(v7m_preserve_fp_state, void, env) | 20 | DEF_HELPER_FLAGS_4(mve_vqrdmladhxh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
18 | 21 | DEF_HELPER_FLAGS_4(mve_vqrdmladhxw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | |
19 | DEF_HELPER_2(v7m_vlstm, void, env, i32) | 22 | |
20 | +DEF_HELPER_2(v7m_vlldm, void, env, i32) | 23 | +DEF_HELPER_FLAGS_4(mve_vqdmlsdhb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
21 | 24 | +DEF_HELPER_FLAGS_4(mve_vqdmlsdhh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | |
22 | DEF_HELPER_2(v8m_stackcheck, void, env, i32) | 25 | +DEF_HELPER_FLAGS_4(mve_vqdmlsdhw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
23 | 26 | + | |
24 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 27 | +DEF_HELPER_FLAGS_4(mve_vqdmlsdhxb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
28 | +DEF_HELPER_FLAGS_4(mve_vqdmlsdhxh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
29 | +DEF_HELPER_FLAGS_4(mve_vqdmlsdhxw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
30 | + | ||
31 | +DEF_HELPER_FLAGS_4(mve_vqrdmlsdhb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
32 | +DEF_HELPER_FLAGS_4(mve_vqrdmlsdhh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
33 | +DEF_HELPER_FLAGS_4(mve_vqrdmlsdhw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
34 | + | ||
35 | +DEF_HELPER_FLAGS_4(mve_vqrdmlsdhxb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
36 | +DEF_HELPER_FLAGS_4(mve_vqrdmlsdhxh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
37 | +DEF_HELPER_FLAGS_4(mve_vqrdmlsdhxw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
38 | + | ||
39 | DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
40 | DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
41 | DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
42 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
25 | index XXXXXXX..XXXXXXX 100644 | 43 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/target/arm/helper.c | 44 | --- a/target/arm/mve.decode |
27 | +++ b/target/arm/helper.c | 45 | +++ b/target/arm/mve.decode |
28 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr) | 46 | @@ -XXX,XX +XXX,XX @@ VQDMLADHX 1110 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 0 @2op |
29 | g_assert_not_reached(); | 47 | VQRDMLADH 1110 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 1 @2op |
48 | VQRDMLADHX 1110 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 1 @2op | ||
49 | |||
50 | +VQDMLSDH 1111 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 0 @2op | ||
51 | +VQDMLSDHX 1111 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 0 @2op | ||
52 | +VQRDMLSDH 1111 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 1 @2op | ||
53 | +VQRDMLSDHX 1111 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 1 @2op | ||
54 | + | ||
55 | # Vector miscellaneous | ||
56 | |||
57 | VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op | ||
58 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
59 | index XXXXXXX..XXXXXXX 100644 | ||
60 | --- a/target/arm/mve_helper.c | ||
61 | +++ b/target/arm/mve_helper.c | ||
62 | @@ -XXX,XX +XXX,XX @@ static int32_t do_vqdmladh_w(int32_t a, int32_t b, int32_t c, int32_t d, | ||
63 | return r >> 32; | ||
30 | } | 64 | } |
31 | 65 | ||
32 | +void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr) | 66 | +static int8_t do_vqdmlsdh_b(int8_t a, int8_t b, int8_t c, int8_t d, |
67 | + int round, bool *sat) | ||
33 | +{ | 68 | +{ |
34 | + /* translate.c should never generate calls here in user-only mode */ | 69 | + int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 7); |
35 | + g_assert_not_reached(); | 70 | + return do_sat_bhw(r, INT16_MIN, INT16_MAX, sat) >> 8; |
36 | +} | 71 | +} |
37 | + | 72 | + |
38 | uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) | 73 | +static int16_t do_vqdmlsdh_h(int16_t a, int16_t b, int16_t c, int16_t d, |
39 | { | 74 | + int round, bool *sat) |
40 | /* The TT instructions can be used by unprivileged code, but in | ||
41 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr) | ||
42 | env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_FPCA_MASK; | ||
43 | } | ||
44 | |||
45 | +void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr) | ||
46 | +{ | 75 | +{ |
47 | + /* fptr is the value of Rn, the frame pointer we load the FP regs from */ | 76 | + int64_t r = ((int64_t)a * b - (int64_t)c * d) * 2 + (round << 15); |
48 | + assert(env->v7m.secure); | 77 | + return do_sat_bhw(r, INT32_MIN, INT32_MAX, sat) >> 16; |
49 | + | ||
50 | + if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)) { | ||
51 | + return; | ||
52 | + } | ||
53 | + | ||
54 | + /* Check access to the coprocessor is permitted */ | ||
55 | + if (!v7m_cpacr_pass(env, true, arm_current_el(env) != 0)) { | ||
56 | + raise_exception_ra(env, EXCP_NOCP, 0, 1, GETPC()); | ||
57 | + } | ||
58 | + | ||
59 | + if (env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_LSPACT_MASK) { | ||
60 | + /* State in FP is still valid */ | ||
61 | + env->v7m.fpccr[M_REG_S] &= ~R_V7M_FPCCR_LSPACT_MASK; | ||
62 | + } else { | ||
63 | + bool ts = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MASK; | ||
64 | + int i; | ||
65 | + uint32_t fpscr; | ||
66 | + | ||
67 | + if (fptr & 7) { | ||
68 | + raise_exception_ra(env, EXCP_UNALIGNED, 0, 1, GETPC()); | ||
69 | + } | ||
70 | + | ||
71 | + for (i = 0; i < (ts ? 32 : 16); i += 2) { | ||
72 | + uint32_t slo, shi; | ||
73 | + uint64_t dn; | ||
74 | + uint32_t faddr = fptr + 4 * i; | ||
75 | + | ||
76 | + if (i >= 16) { | ||
77 | + faddr += 8; /* skip the slot for the FPSCR */ | ||
78 | + } | ||
79 | + | ||
80 | + slo = cpu_ldl_data(env, faddr); | ||
81 | + shi = cpu_ldl_data(env, faddr + 4); | ||
82 | + | ||
83 | + dn = (uint64_t) shi << 32 | slo; | ||
84 | + *aa32_vfp_dreg(env, i / 2) = dn; | ||
85 | + } | ||
86 | + fpscr = cpu_ldl_data(env, fptr + 0x40); | ||
87 | + vfp_set_fpscr(env, fpscr); | ||
88 | + } | ||
89 | + | ||
90 | + env->v7m.control[M_REG_S] |= R_V7M_CONTROL_FPCA_MASK; | ||
91 | +} | 78 | +} |
92 | + | 79 | + |
93 | static bool v7m_push_stack(ARMCPU *cpu) | 80 | +static int32_t do_vqdmlsdh_w(int32_t a, int32_t b, int32_t c, int32_t d, |
94 | { | 81 | + int round, bool *sat) |
95 | /* Do the "set up stack frame" part of exception entry, | 82 | +{ |
96 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 83 | + int64_t m1 = (int64_t)a * b; |
84 | + int64_t m2 = (int64_t)c * d; | ||
85 | + int64_t r; | ||
86 | + /* The same ordering issue as in do_vqdmladh_w applies here too */ | ||
87 | + if (ssub64_overflow(m1, m2, &r) || | ||
88 | + sadd64_overflow(r, (round << 30), &r) || | ||
89 | + sadd64_overflow(r, r, &r)) { | ||
90 | + *sat = true; | ||
91 | + return r < 0 ? INT32_MAX : INT32_MIN; | ||
92 | + } | ||
93 | + return r >> 32; | ||
94 | +} | ||
95 | + | ||
96 | DO_VQDMLADH_OP(vqdmladhb, 1, int8_t, 0, 0, do_vqdmladh_b) | ||
97 | DO_VQDMLADH_OP(vqdmladhh, 2, int16_t, 0, 0, do_vqdmladh_h) | ||
98 | DO_VQDMLADH_OP(vqdmladhw, 4, int32_t, 0, 0, do_vqdmladh_w) | ||
99 | @@ -XXX,XX +XXX,XX @@ DO_VQDMLADH_OP(vqrdmladhxb, 1, int8_t, 1, 1, do_vqdmladh_b) | ||
100 | DO_VQDMLADH_OP(vqrdmladhxh, 2, int16_t, 1, 1, do_vqdmladh_h) | ||
101 | DO_VQDMLADH_OP(vqrdmladhxw, 4, int32_t, 1, 1, do_vqdmladh_w) | ||
102 | |||
103 | +DO_VQDMLADH_OP(vqdmlsdhb, 1, int8_t, 0, 0, do_vqdmlsdh_b) | ||
104 | +DO_VQDMLADH_OP(vqdmlsdhh, 2, int16_t, 0, 0, do_vqdmlsdh_h) | ||
105 | +DO_VQDMLADH_OP(vqdmlsdhw, 4, int32_t, 0, 0, do_vqdmlsdh_w) | ||
106 | +DO_VQDMLADH_OP(vqdmlsdhxb, 1, int8_t, 1, 0, do_vqdmlsdh_b) | ||
107 | +DO_VQDMLADH_OP(vqdmlsdhxh, 2, int16_t, 1, 0, do_vqdmlsdh_h) | ||
108 | +DO_VQDMLADH_OP(vqdmlsdhxw, 4, int32_t, 1, 0, do_vqdmlsdh_w) | ||
109 | + | ||
110 | +DO_VQDMLADH_OP(vqrdmlsdhb, 1, int8_t, 0, 1, do_vqdmlsdh_b) | ||
111 | +DO_VQDMLADH_OP(vqrdmlsdhh, 2, int16_t, 0, 1, do_vqdmlsdh_h) | ||
112 | +DO_VQDMLADH_OP(vqrdmlsdhw, 4, int32_t, 0, 1, do_vqdmlsdh_w) | ||
113 | +DO_VQDMLADH_OP(vqrdmlsdhxb, 1, int8_t, 1, 1, do_vqdmlsdh_b) | ||
114 | +DO_VQDMLADH_OP(vqrdmlsdhxh, 2, int16_t, 1, 1, do_vqdmlsdh_h) | ||
115 | +DO_VQDMLADH_OP(vqrdmlsdhxw, 4, int32_t, 1, 1, do_vqdmlsdh_w) | ||
116 | + | ||
117 | #define DO_2OP_SCALAR(OP, ESIZE, TYPE, FN) \ | ||
118 | void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ | ||
119 | uint32_t rm) \ | ||
120 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
97 | index XXXXXXX..XXXXXXX 100644 | 121 | index XXXXXXX..XXXXXXX 100644 |
98 | --- a/target/arm/translate.c | 122 | --- a/target/arm/translate-mve.c |
99 | +++ b/target/arm/translate.c | 123 | +++ b/target/arm/translate-mve.c |
100 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) | 124 | @@ -XXX,XX +XXX,XX @@ DO_2OP(VQDMLADH, vqdmladh) |
101 | TCGv_i32 fptr = load_reg(s, rn); | 125 | DO_2OP(VQDMLADHX, vqdmladhx) |
102 | 126 | DO_2OP(VQRDMLADH, vqrdmladh) | |
103 | if (extract32(insn, 20, 1)) { | 127 | DO_2OP(VQRDMLADHX, vqrdmladhx) |
104 | - /* VLLDM */ | 128 | +DO_2OP(VQDMLSDH, vqdmlsdh) |
105 | + gen_helper_v7m_vlldm(cpu_env, fptr); | 129 | +DO_2OP(VQDMLSDHX, vqdmlsdhx) |
106 | } else { | 130 | +DO_2OP(VQRDMLSDH, vqrdmlsdh) |
107 | gen_helper_v7m_vlstm(cpu_env, fptr); | 131 | +DO_2OP(VQRDMLSDHX, vqrdmlsdhx) |
108 | } | 132 | |
133 | static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, | ||
134 | MVEGenTwoOpScalarFn fn) | ||
109 | -- | 135 | -- |
110 | 2.20.1 | 136 | 2.20.1 |
111 | 137 | ||
112 | 138 | diff view generated by jsdifflib |
1 | Add a new helper function which returns the MMU index to use | 1 | Implement the vector form of the MVE VQDMULL insn. |
---|---|---|---|
2 | for v7M, where the caller specifies all of the security | ||
3 | state, privilege level and whether the execution priority | ||
4 | is negative, and reimplement the existing | ||
5 | arm_v7m_mmu_idx_for_secstate_and_priv() in terms of it. | ||
6 | |||
7 | We are going to need this for the lazy-FP-stacking code. | ||
8 | 2 | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
11 | Message-id: 20190416125744.27770-21-peter.maydell@linaro.org | 5 | Message-id: 20210617121628.20116-39-peter.maydell@linaro.org |
12 | --- | 6 | --- |
13 | target/arm/cpu.h | 7 +++++++ | 7 | target/arm/helper-mve.h | 5 +++++ |
14 | target/arm/helper.c | 14 +++++++++++--- | 8 | target/arm/mve.decode | 5 +++++ |
15 | 2 files changed, 18 insertions(+), 3 deletions(-) | 9 | target/arm/mve_helper.c | 30 ++++++++++++++++++++++++++++++ |
10 | target/arm/translate-mve.c | 30 ++++++++++++++++++++++++++++++ | ||
11 | 4 files changed, 70 insertions(+) | ||
16 | 12 | ||
17 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 13 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
18 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/cpu.h | 15 | --- a/target/arm/helper-mve.h |
20 | +++ b/target/arm/cpu.h | 16 | +++ b/target/arm/helper-mve.h |
21 | @@ -XXX,XX +XXX,XX @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) | 17 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqrdmlsdhxb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
22 | } | 18 | DEF_HELPER_FLAGS_4(mve_vqrdmlsdhxh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
23 | } | 19 | DEF_HELPER_FLAGS_4(mve_vqrdmlsdhxw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
20 | |||
21 | +DEF_HELPER_FLAGS_4(mve_vqdmullbh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
22 | +DEF_HELPER_FLAGS_4(mve_vqdmullbw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
23 | +DEF_HELPER_FLAGS_4(mve_vqdmullth, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
24 | +DEF_HELPER_FLAGS_4(mve_vqdmulltw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
25 | + | ||
26 | DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
27 | DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
28 | DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
29 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/target/arm/mve.decode | ||
32 | +++ b/target/arm/mve.decode | ||
33 | @@ -XXX,XX +XXX,XX @@ | ||
34 | @1op_nosz .... .... .... .... .... .... .... .... &1op qd=%qd qm=%qm size=0 | ||
35 | @2op .... .... .. size:2 .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn | ||
36 | @2op_nosz .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn size=0 | ||
37 | +@2op_sz28 .... .... .... .... .... .... .... .... &2op qd=%qd qm=%qm qn=%qn \ | ||
38 | + size=%size_28 | ||
39 | |||
40 | # The _rev suffix indicates that Vn and Vm are reversed. This is | ||
41 | # the case for shifts. In the Arm ARM these insns are documented | ||
42 | @@ -XXX,XX +XXX,XX @@ VQDMLSDHX 1111 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 0 @2op | ||
43 | VQRDMLSDH 1111 1110 0 . .. ... 0 ... 0 1110 . 0 . 0 ... 1 @2op | ||
44 | VQRDMLSDHX 1111 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 1 @2op | ||
45 | |||
46 | +VQDMULLB 111 . 1110 0 . 11 ... 0 ... 0 1111 . 0 . 0 ... 1 @2op_sz28 | ||
47 | +VQDMULLT 111 . 1110 0 . 11 ... 0 ... 1 1111 . 0 . 0 ... 1 @2op_sz28 | ||
48 | + | ||
49 | # Vector miscellaneous | ||
50 | |||
51 | VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op | ||
52 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
53 | index XXXXXXX..XXXXXXX 100644 | ||
54 | --- a/target/arm/mve_helper.c | ||
55 | +++ b/target/arm/mve_helper.c | ||
56 | @@ -XXX,XX +XXX,XX @@ DO_2OP_SAT_SCALAR_L(vqdmullt_scalarh, 1, 2, int16_t, 4, int32_t, \ | ||
57 | DO_2OP_SAT_SCALAR_L(vqdmullt_scalarw, 1, 4, int32_t, 8, int64_t, \ | ||
58 | do_qdmullw, SATMASK32) | ||
24 | 59 | ||
25 | +/* | 60 | +/* |
26 | + * Return the MMU index for a v7M CPU with all relevant information | 61 | + * Long saturating ops |
27 | + * manually specified. | ||
28 | + */ | 62 | + */ |
29 | +ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, | 63 | +#define DO_2OP_SAT_L(OP, TOP, ESIZE, TYPE, LESIZE, LTYPE, FN, SATMASK) \ |
30 | + bool secstate, bool priv, bool negpri); | 64 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, \ |
65 | + void *vm) \ | ||
66 | + { \ | ||
67 | + LTYPE *d = vd; \ | ||
68 | + TYPE *n = vn, *m = vm; \ | ||
69 | + uint16_t mask = mve_element_mask(env); \ | ||
70 | + unsigned le; \ | ||
71 | + bool qc = false; \ | ||
72 | + for (le = 0; le < 16 / LESIZE; le++, mask >>= LESIZE) { \ | ||
73 | + bool sat = false; \ | ||
74 | + LTYPE op1 = n[H##ESIZE(le * 2 + TOP)]; \ | ||
75 | + LTYPE op2 = m[H##ESIZE(le * 2 + TOP)]; \ | ||
76 | + mergemask(&d[H##LESIZE(le)], FN(op1, op2, &sat), mask); \ | ||
77 | + qc |= sat && (mask & SATMASK); \ | ||
78 | + } \ | ||
79 | + if (qc) { \ | ||
80 | + env->vfp.qc[0] = qc; \ | ||
81 | + } \ | ||
82 | + mve_advance_vpt(env); \ | ||
83 | + } | ||
31 | + | 84 | + |
32 | /* Return the MMU index for a v7M CPU in the specified security and | 85 | +DO_2OP_SAT_L(vqdmullbh, 0, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16B) |
33 | * privilege state. | 86 | +DO_2OP_SAT_L(vqdmullbw, 0, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32) |
34 | */ | 87 | +DO_2OP_SAT_L(vqdmullth, 1, 2, int16_t, 4, int32_t, do_qdmullh, SATMASK16T) |
35 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 88 | +DO_2OP_SAT_L(vqdmulltw, 1, 4, int32_t, 8, int64_t, do_qdmullw, SATMASK32) |
89 | + | ||
90 | static inline uint32_t do_vbrsrb(uint32_t n, uint32_t m) | ||
91 | { | ||
92 | m &= 0xff; | ||
93 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
36 | index XXXXXXX..XXXXXXX 100644 | 94 | index XXXXXXX..XXXXXXX 100644 |
37 | --- a/target/arm/helper.c | 95 | --- a/target/arm/translate-mve.c |
38 | +++ b/target/arm/helper.c | 96 | +++ b/target/arm/translate-mve.c |
39 | @@ -XXX,XX +XXX,XX @@ int fp_exception_el(CPUARMState *env, int cur_el) | 97 | @@ -XXX,XX +XXX,XX @@ DO_2OP(VQDMLSDHX, vqdmlsdhx) |
40 | return 0; | 98 | DO_2OP(VQRDMLSDH, vqrdmlsdh) |
41 | } | 99 | DO_2OP(VQRDMLSDHX, vqrdmlsdhx) |
42 | 100 | ||
43 | -ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, | 101 | +static bool trans_VQDMULLB(DisasContext *s, arg_2op *a) |
44 | - bool secstate, bool priv) | ||
45 | +ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env, | ||
46 | + bool secstate, bool priv, bool negpri) | ||
47 | { | ||
48 | ARMMMUIdx mmu_idx = ARM_MMU_IDX_M; | ||
49 | |||
50 | @@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, | ||
51 | mmu_idx |= ARM_MMU_IDX_M_PRIV; | ||
52 | } | ||
53 | |||
54 | - if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) { | ||
55 | + if (negpri) { | ||
56 | mmu_idx |= ARM_MMU_IDX_M_NEGPRI; | ||
57 | } | ||
58 | |||
59 | @@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, | ||
60 | return mmu_idx; | ||
61 | } | ||
62 | |||
63 | +ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env, | ||
64 | + bool secstate, bool priv) | ||
65 | +{ | 102 | +{ |
66 | + bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate); | 103 | + static MVEGenTwoOpFn * const fns[] = { |
67 | + | 104 | + NULL, |
68 | + return arm_v7m_mmu_idx_all(env, secstate, priv, negpri); | 105 | + gen_helper_mve_vqdmullbh, |
106 | + gen_helper_mve_vqdmullbw, | ||
107 | + NULL, | ||
108 | + }; | ||
109 | + if (a->size == MO_32 && (a->qd == a->qm || a->qd == a->qn)) { | ||
110 | + /* UNPREDICTABLE; we choose to undef */ | ||
111 | + return false; | ||
112 | + } | ||
113 | + return do_2op(s, a, fns[a->size]); | ||
69 | +} | 114 | +} |
70 | + | 115 | + |
71 | /* Return the MMU index for a v7M CPU in the specified security state */ | 116 | +static bool trans_VQDMULLT(DisasContext *s, arg_2op *a) |
72 | ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) | 117 | +{ |
118 | + static MVEGenTwoOpFn * const fns[] = { | ||
119 | + NULL, | ||
120 | + gen_helper_mve_vqdmullth, | ||
121 | + gen_helper_mve_vqdmulltw, | ||
122 | + NULL, | ||
123 | + }; | ||
124 | + if (a->size == MO_32 && (a->qd == a->qm || a->qd == a->qn)) { | ||
125 | + /* UNPREDICTABLE; we choose to undef */ | ||
126 | + return false; | ||
127 | + } | ||
128 | + return do_2op(s, a, fns[a->size]); | ||
129 | +} | ||
130 | + | ||
131 | static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, | ||
132 | MVEGenTwoOpScalarFn fn) | ||
73 | { | 133 | { |
74 | -- | 134 | -- |
75 | 2.20.1 | 135 | 2.20.1 |
76 | 136 | ||
77 | 137 | diff view generated by jsdifflib |
1 | Normally configure identifies the source path by looking | 1 | Implement the MVE VRHADD insn, which performs a rounded halving |
---|---|---|---|
2 | at the location where the configure script itself exists. | 2 | addition. |
3 | We also provide a --source-path option which lets the user | ||
4 | manually override this. | ||
5 | |||
6 | There isn't really an obvious use case for the --source-path | ||
7 | option, and in commit 927128222b0a91f56c13a in 2017 we | ||
8 | accidentally added some logic that looks at $source_path | ||
9 | before the command line option that overrides it has been | ||
10 | processed. | ||
11 | |||
12 | The fact that nobody complained suggests that there isn't | ||
13 | any use of this option and we aren't testing it either; | ||
14 | remove it. This allows us to move the "make $source_path | ||
15 | absolute" logic up so that there is no window in the script | ||
16 | where $source_path is set but not yet absolute. | ||
17 | 3 | ||
18 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
19 | Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
20 | Message-id: 20190318134019.23729-1-peter.maydell@linaro.org | 6 | Message-id: 20210617121628.20116-40-peter.maydell@linaro.org |
21 | --- | 7 | --- |
22 | configure | 10 ++-------- | 8 | target/arm/helper-mve.h | 8 ++++++++ |
23 | 1 file changed, 2 insertions(+), 8 deletions(-) | 9 | target/arm/mve.decode | 3 +++ |
10 | target/arm/mve_helper.c | 6 ++++++ | ||
11 | target/arm/translate-mve.c | 2 ++ | ||
12 | 4 files changed, 19 insertions(+) | ||
24 | 13 | ||
25 | diff --git a/configure b/configure | 14 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
26 | index XXXXXXX..XXXXXXX 100755 | 15 | index XXXXXXX..XXXXXXX 100644 |
27 | --- a/configure | 16 | --- a/target/arm/helper-mve.h |
28 | +++ b/configure | 17 | +++ b/target/arm/helper-mve.h |
29 | @@ -XXX,XX +XXX,XX @@ ld_has() { | 18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vqdmullbw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
30 | 19 | DEF_HELPER_FLAGS_4(mve_vqdmullth, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | |
31 | # default parameters | 20 | DEF_HELPER_FLAGS_4(mve_vqdmulltw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
32 | source_path=$(dirname "$0") | 21 | |
33 | +# make source path absolute | 22 | +DEF_HELPER_FLAGS_4(mve_vrhaddsb, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
34 | +source_path=$(cd "$source_path"; pwd) | 23 | +DEF_HELPER_FLAGS_4(mve_vrhaddsh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
35 | cpu="" | 24 | +DEF_HELPER_FLAGS_4(mve_vrhaddsw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
36 | iasl="iasl" | 25 | + |
37 | interp_prefix="/usr/gnemul/qemu-%M" | 26 | +DEF_HELPER_FLAGS_4(mve_vrhaddub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
38 | @@ -XXX,XX +XXX,XX @@ for opt do | 27 | +DEF_HELPER_FLAGS_4(mve_vrhadduh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
39 | ;; | 28 | +DEF_HELPER_FLAGS_4(mve_vrhadduw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
40 | --cxx=*) CXX="$optarg" | 29 | + |
41 | ;; | 30 | DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
42 | - --source-path=*) source_path="$optarg" | 31 | DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
43 | - ;; | 32 | DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
44 | --cpu=*) cpu="$optarg" | 33 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode |
45 | ;; | 34 | index XXXXXXX..XXXXXXX 100644 |
46 | --extra-cflags=*) QEMU_CFLAGS="$QEMU_CFLAGS $optarg" | 35 | --- a/target/arm/mve.decode |
47 | @@ -XXX,XX +XXX,XX @@ if test "$debug_info" = "yes"; then | 36 | +++ b/target/arm/mve.decode |
48 | LDFLAGS="-g $LDFLAGS" | 37 | @@ -XXX,XX +XXX,XX @@ VQRDMLSDHX 1111 1110 0 . .. ... 0 ... 1 1110 . 0 . 0 ... 1 @2op |
49 | fi | 38 | VQDMULLB 111 . 1110 0 . 11 ... 0 ... 0 1111 . 0 . 0 ... 1 @2op_sz28 |
50 | 39 | VQDMULLT 111 . 1110 0 . 11 ... 0 ... 1 1111 . 0 . 0 ... 1 @2op_sz28 | |
51 | -# make source path absolute | 40 | |
52 | -source_path=$(cd "$source_path"; pwd) | 41 | +VRHADD_S 111 0 1111 0 . .. ... 0 ... 0 0001 . 1 . 0 ... 0 @2op |
53 | - | 42 | +VRHADD_U 111 1 1111 0 . .. ... 0 ... 0 0001 . 1 . 0 ... 0 @2op |
54 | # running configure in the source tree? | 43 | + |
55 | # we know that's the case if configure is there. | 44 | # Vector miscellaneous |
56 | if test -f "./configure"; then | 45 | |
57 | @@ -XXX,XX +XXX,XX @@ for opt do | 46 | VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op |
58 | ;; | 47 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c |
59 | --interp-prefix=*) interp_prefix="$optarg" | 48 | index XXXXXXX..XXXXXXX 100644 |
60 | ;; | 49 | --- a/target/arm/mve_helper.c |
61 | - --source-path=*) | 50 | +++ b/target/arm/mve_helper.c |
62 | - ;; | 51 | @@ -XXX,XX +XXX,XX @@ DO_2OP_U(vshlu, DO_VSHLU) |
63 | --cross-prefix=*) | 52 | DO_2OP_S(vrshls, DO_VRSHLS) |
64 | ;; | 53 | DO_2OP_U(vrshlu, DO_VRSHLU) |
65 | --cc=*) | 54 | |
66 | @@ -XXX,XX +XXX,XX @@ $(echo Available targets: $default_target_list | \ | 55 | +#define DO_RHADD_S(N, M) (((int64_t)(N) + (M) + 1) >> 1) |
67 | --target-list-exclude=LIST exclude a set of targets from the default target-list | 56 | +#define DO_RHADD_U(N, M) (((uint64_t)(N) + (M) + 1) >> 1) |
68 | 57 | + | |
69 | Advanced options (experts only): | 58 | +DO_2OP_S(vrhadds, DO_RHADD_S) |
70 | - --source-path=PATH path of source code [$source_path] | 59 | +DO_2OP_U(vrhaddu, DO_RHADD_U) |
71 | --cross-prefix=PREFIX use PREFIX for compile tools [$cross_prefix] | 60 | + |
72 | --cc=CC use C compiler CC [$cc] | 61 | static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bool *s) |
73 | --iasl=IASL use ACPI compiler IASL [$iasl] | 62 | { |
63 | if (val > max) { | ||
64 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
65 | index XXXXXXX..XXXXXXX 100644 | ||
66 | --- a/target/arm/translate-mve.c | ||
67 | +++ b/target/arm/translate-mve.c | ||
68 | @@ -XXX,XX +XXX,XX @@ DO_2OP(VQDMLSDH, vqdmlsdh) | ||
69 | DO_2OP(VQDMLSDHX, vqdmlsdhx) | ||
70 | DO_2OP(VQRDMLSDH, vqrdmlsdh) | ||
71 | DO_2OP(VQRDMLSDHX, vqrdmlsdhx) | ||
72 | +DO_2OP(VRHADD_S, vrhadds) | ||
73 | +DO_2OP(VRHADD_U, vrhaddu) | ||
74 | |||
75 | static bool trans_VQDMULLB(DisasContext *s, arg_2op *a) | ||
76 | { | ||
74 | -- | 77 | -- |
75 | 2.20.1 | 78 | 2.20.1 |
76 | 79 | ||
77 | 80 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | 1 | Implement the MVE VADC and VSBC insns. These perform an |
---|---|---|---|
2 | add-with-carry or subtract-with-carry of the 32-bit elements in each | ||
3 | lane of the input vectors, where the carry-out of each add is the | ||
4 | carry-in of the next. The initial carry input is either 1 or is from | ||
5 | FPSCR.C; the carry out at the end is written back to FPSCR.C. | ||
2 | 6 | ||
3 | Suggested-by: Markus Armbruster <armbru@redhat.com> | ||
4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
5 | Message-id: 20190412165416.7977-3-philmd@redhat.com | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20210617121628.20116-41-peter.maydell@linaro.org | ||
8 | --- | 10 | --- |
9 | hw/arm/nseries.c | 3 ++- | 11 | target/arm/helper-mve.h | 5 ++++ |
10 | 1 file changed, 2 insertions(+), 1 deletion(-) | 12 | target/arm/mve.decode | 5 ++++ |
13 | target/arm/mve_helper.c | 52 ++++++++++++++++++++++++++++++++++++++ | ||
14 | target/arm/translate-mve.c | 37 +++++++++++++++++++++++++++ | ||
15 | 4 files changed, 99 insertions(+) | ||
11 | 16 | ||
12 | diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c | 17 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
13 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
14 | --- a/hw/arm/nseries.c | 19 | --- a/target/arm/helper-mve.h |
15 | +++ b/hw/arm/nseries.c | 20 | +++ b/target/arm/helper-mve.h |
16 | @@ -XXX,XX +XXX,XX @@ | 21 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrhaddub, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
17 | #include "hw/boards.h" | 22 | DEF_HELPER_FLAGS_4(mve_vrhadduh, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
18 | #include "hw/i2c/i2c.h" | 23 | DEF_HELPER_FLAGS_4(mve_vrhadduw, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
19 | #include "hw/devices.h" | 24 | |
20 | +#include "hw/misc/tmp105.h" | 25 | +DEF_HELPER_FLAGS_4(mve_vadc, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
21 | #include "hw/block/flash.h" | 26 | +DEF_HELPER_FLAGS_4(mve_vadci, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
22 | #include "hw/hw.h" | 27 | +DEF_HELPER_FLAGS_4(mve_vsbc, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
23 | #include "hw/bt.h" | 28 | +DEF_HELPER_FLAGS_4(mve_vsbci, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
24 | @@ -XXX,XX +XXX,XX @@ static void n8x0_i2c_setup(struct n800_s *s) | 29 | + |
25 | qemu_register_powerdown_notifier(&n8x0_system_powerdown_notifier); | 30 | DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
26 | 31 | DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | |
27 | /* Attach a TMP105 PM chip (A0 wired to ground) */ | 32 | DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
28 | - dev = i2c_create_slave(i2c, "tmp105", N8X0_TMP105_ADDR); | 33 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode |
29 | + dev = i2c_create_slave(i2c, TYPE_TMP105, N8X0_TMP105_ADDR); | 34 | index XXXXXXX..XXXXXXX 100644 |
30 | qdev_connect_gpio_out(dev, 0, tmp_irq); | 35 | --- a/target/arm/mve.decode |
36 | +++ b/target/arm/mve.decode | ||
37 | @@ -XXX,XX +XXX,XX @@ VQDMULLT 111 . 1110 0 . 11 ... 0 ... 1 1111 . 0 . 0 ... 1 @2op_sz28 | ||
38 | VRHADD_S 111 0 1111 0 . .. ... 0 ... 0 0001 . 1 . 0 ... 0 @2op | ||
39 | VRHADD_U 111 1 1111 0 . .. ... 0 ... 0 0001 . 1 . 0 ... 0 @2op | ||
40 | |||
41 | +VADC 1110 1110 0 . 11 ... 0 ... 0 1111 . 0 . 0 ... 0 @2op_nosz | ||
42 | +VSBC 1111 1110 0 . 11 ... 0 ... 0 1111 . 0 . 0 ... 0 @2op_nosz | ||
43 | +VADCI 1110 1110 0 . 11 ... 0 ... 1 1111 . 0 . 0 ... 0 @2op_nosz | ||
44 | +VSBCI 1111 1110 0 . 11 ... 0 ... 1 1111 . 0 . 0 ... 0 @2op_nosz | ||
45 | + | ||
46 | # Vector miscellaneous | ||
47 | |||
48 | VCLS 1111 1111 1 . 11 .. 00 ... 0 0100 01 . 0 ... 0 @1op | ||
49 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
50 | index XXXXXXX..XXXXXXX 100644 | ||
51 | --- a/target/arm/mve_helper.c | ||
52 | +++ b/target/arm/mve_helper.c | ||
53 | @@ -XXX,XX +XXX,XX @@ DO_2OP_U(vrshlu, DO_VRSHLU) | ||
54 | DO_2OP_S(vrhadds, DO_RHADD_S) | ||
55 | DO_2OP_U(vrhaddu, DO_RHADD_U) | ||
56 | |||
57 | +static void do_vadc(CPUARMState *env, uint32_t *d, uint32_t *n, uint32_t *m, | ||
58 | + uint32_t inv, uint32_t carry_in, bool update_flags) | ||
59 | +{ | ||
60 | + uint16_t mask = mve_element_mask(env); | ||
61 | + unsigned e; | ||
62 | + | ||
63 | + /* If any additions trigger, we will update flags. */ | ||
64 | + if (mask & 0x1111) { | ||
65 | + update_flags = true; | ||
66 | + } | ||
67 | + | ||
68 | + for (e = 0; e < 16 / 4; e++, mask >>= 4) { | ||
69 | + uint64_t r = carry_in; | ||
70 | + r += n[H4(e)]; | ||
71 | + r += m[H4(e)] ^ inv; | ||
72 | + if (mask & 1) { | ||
73 | + carry_in = r >> 32; | ||
74 | + } | ||
75 | + mergemask(&d[H4(e)], r, mask); | ||
76 | + } | ||
77 | + | ||
78 | + if (update_flags) { | ||
79 | + /* Store C, clear NZV. */ | ||
80 | + env->vfp.xregs[ARM_VFP_FPSCR] &= ~FPCR_NZCV_MASK; | ||
81 | + env->vfp.xregs[ARM_VFP_FPSCR] |= carry_in * FPCR_C; | ||
82 | + } | ||
83 | + mve_advance_vpt(env); | ||
84 | +} | ||
85 | + | ||
86 | +void HELPER(mve_vadc)(CPUARMState *env, void *vd, void *vn, void *vm) | ||
87 | +{ | ||
88 | + bool carry_in = env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_C; | ||
89 | + do_vadc(env, vd, vn, vm, 0, carry_in, false); | ||
90 | +} | ||
91 | + | ||
92 | +void HELPER(mve_vsbc)(CPUARMState *env, void *vd, void *vn, void *vm) | ||
93 | +{ | ||
94 | + bool carry_in = env->vfp.xregs[ARM_VFP_FPSCR] & FPCR_C; | ||
95 | + do_vadc(env, vd, vn, vm, -1, carry_in, false); | ||
96 | +} | ||
97 | + | ||
98 | + | ||
99 | +void HELPER(mve_vadci)(CPUARMState *env, void *vd, void *vn, void *vm) | ||
100 | +{ | ||
101 | + do_vadc(env, vd, vn, vm, 0, 0, true); | ||
102 | +} | ||
103 | + | ||
104 | +void HELPER(mve_vsbci)(CPUARMState *env, void *vd, void *vn, void *vm) | ||
105 | +{ | ||
106 | + do_vadc(env, vd, vn, vm, -1, 1, true); | ||
107 | +} | ||
108 | + | ||
109 | static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bool *s) | ||
110 | { | ||
111 | if (val > max) { | ||
112 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
113 | index XXXXXXX..XXXXXXX 100644 | ||
114 | --- a/target/arm/translate-mve.c | ||
115 | +++ b/target/arm/translate-mve.c | ||
116 | @@ -XXX,XX +XXX,XX @@ static bool trans_VQDMULLT(DisasContext *s, arg_2op *a) | ||
117 | return do_2op(s, a, fns[a->size]); | ||
31 | } | 118 | } |
32 | 119 | ||
120 | +/* | ||
121 | + * VADC and VSBC: these perform an add-with-carry or subtract-with-carry | ||
122 | + * of the 32-bit elements in each lane of the input vectors, where the | ||
123 | + * carry-out of each add is the carry-in of the next. The initial carry | ||
124 | + * input is either fixed (0 for VADCI, 1 for VSBCI) or is from FPSCR.C | ||
125 | + * (for VADC and VSBC); the carry out at the end is written back to FPSCR.C. | ||
126 | + * These insns are subject to beat-wise execution. Partial execution | ||
127 | + * of an I=1 (initial carry input fixed) insn which does not | ||
128 | + * execute the first beat must start with the current FPSCR.NZCV | ||
129 | + * value, not the fixed constant input. | ||
130 | + */ | ||
131 | +static bool trans_VADC(DisasContext *s, arg_2op *a) | ||
132 | +{ | ||
133 | + return do_2op(s, a, gen_helper_mve_vadc); | ||
134 | +} | ||
135 | + | ||
136 | +static bool trans_VADCI(DisasContext *s, arg_2op *a) | ||
137 | +{ | ||
138 | + if (mve_skip_first_beat(s)) { | ||
139 | + return trans_VADC(s, a); | ||
140 | + } | ||
141 | + return do_2op(s, a, gen_helper_mve_vadci); | ||
142 | +} | ||
143 | + | ||
144 | +static bool trans_VSBC(DisasContext *s, arg_2op *a) | ||
145 | +{ | ||
146 | + return do_2op(s, a, gen_helper_mve_vsbc); | ||
147 | +} | ||
148 | + | ||
149 | +static bool trans_VSBCI(DisasContext *s, arg_2op *a) | ||
150 | +{ | ||
151 | + if (mve_skip_first_beat(s)) { | ||
152 | + return trans_VSBC(s, a); | ||
153 | + } | ||
154 | + return do_2op(s, a, gen_helper_mve_vsbci); | ||
155 | +} | ||
156 | + | ||
157 | static bool do_2op_scalar(DisasContext *s, arg_2scalar *a, | ||
158 | MVEGenTwoOpScalarFn fn) | ||
159 | { | ||
33 | -- | 160 | -- |
34 | 2.20.1 | 161 | 2.20.1 |
35 | 162 | ||
36 | 163 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | 1 | Implement the MVE VCADD insn, which performs a complex add with |
---|---|---|---|
2 | rotate. Note that the size=0b11 encoding is VSBC. | ||
2 | 3 | ||
3 | Reviewed-by: Thomas Huth <thuth@redhat.com> | 4 | The architecture grants some leeway for the "destination and Vm |
4 | Reviewed-by: Cédric Le Goater <clg@kaod.org> | 5 | source overlap" case for the size MO_32 case, but we choose not to |
5 | Reviewed-by: Markus Armbruster <armbru@redhat.com> | 6 | make use of it, instead always calculating all 16 bytes worth of |
6 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 7 | results before setting the destination register. |
7 | Message-id: 20190412165416.7977-2-philmd@redhat.com | 8 | |
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
11 | Message-id: 20210617121628.20116-42-peter.maydell@linaro.org | ||
9 | --- | 12 | --- |
10 | hw/arm/aspeed.c | 13 +++++++++---- | 13 | target/arm/helper-mve.h | 8 ++++++++ |
11 | 1 file changed, 9 insertions(+), 4 deletions(-) | 14 | target/arm/mve.decode | 9 +++++++-- |
15 | target/arm/mve_helper.c | 29 +++++++++++++++++++++++++++++ | ||
16 | target/arm/translate-mve.c | 7 +++++++ | ||
17 | 4 files changed, 51 insertions(+), 2 deletions(-) | ||
12 | 18 | ||
13 | diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c | 19 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
14 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/hw/arm/aspeed.c | 21 | --- a/target/arm/helper-mve.h |
16 | +++ b/hw/arm/aspeed.c | 22 | +++ b/target/arm/helper-mve.h |
17 | @@ -XXX,XX +XXX,XX @@ | 23 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vadci, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
18 | #include "hw/arm/aspeed_soc.h" | 24 | DEF_HELPER_FLAGS_4(mve_vsbc, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
19 | #include "hw/boards.h" | 25 | DEF_HELPER_FLAGS_4(mve_vsbci, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
20 | #include "hw/i2c/smbus_eeprom.h" | 26 | |
21 | +#include "hw/misc/pca9552.h" | 27 | +DEF_HELPER_FLAGS_4(mve_vcadd90b, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
22 | +#include "hw/misc/tmp105.h" | 28 | +DEF_HELPER_FLAGS_4(mve_vcadd90h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
23 | #include "qemu/log.h" | 29 | +DEF_HELPER_FLAGS_4(mve_vcadd90w, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
24 | #include "sysemu/block-backend.h" | 30 | + |
25 | #include "hw/loader.h" | 31 | +DEF_HELPER_FLAGS_4(mve_vcadd270b, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
26 | @@ -XXX,XX +XXX,XX @@ static void ast2500_evb_i2c_init(AspeedBoardState *bmc) | 32 | +DEF_HELPER_FLAGS_4(mve_vcadd270h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
27 | eeprom_buf); | 33 | +DEF_HELPER_FLAGS_4(mve_vcadd270w, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
28 | 34 | + | |
29 | /* The AST2500 EVB expects a LM75 but a TMP105 is compatible */ | 35 | DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
30 | - i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), "tmp105", 0x4d); | 36 | DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
31 | + i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 7), | 37 | DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) |
32 | + TYPE_TMP105, 0x4d); | 38 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode |
33 | 39 | index XXXXXXX..XXXXXXX 100644 | |
34 | /* The AST2500 EVB does not have an RTC. Let's pretend that one is | 40 | --- a/target/arm/mve.decode |
35 | * plugged on the I2C bus header */ | 41 | +++ b/target/arm/mve.decode |
36 | @@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc) | 42 | @@ -XXX,XX +XXX,XX @@ VRHADD_S 111 0 1111 0 . .. ... 0 ... 0 0001 . 1 . 0 ... 0 @2op |
37 | AspeedSoCState *soc = &bmc->soc; | 43 | VRHADD_U 111 1 1111 0 . .. ... 0 ... 0 0001 . 1 . 0 ... 0 @2op |
38 | uint8_t *eeprom_buf = g_malloc0(8 * 1024); | 44 | |
39 | 45 | VADC 1110 1110 0 . 11 ... 0 ... 0 1111 . 0 . 0 ... 0 @2op_nosz | |
40 | - i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), "pca9552", 0x60); | 46 | -VSBC 1111 1110 0 . 11 ... 0 ... 0 1111 . 0 . 0 ... 0 @2op_nosz |
41 | + i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 3), TYPE_PCA9552, | 47 | VADCI 1110 1110 0 . 11 ... 0 ... 1 1111 . 0 . 0 ... 0 @2op_nosz |
42 | + 0x60); | 48 | -VSBCI 1111 1110 0 . 11 ... 0 ... 1 1111 . 0 . 0 ... 0 @2op_nosz |
43 | 49 | + | |
44 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 4), "tmp423", 0x4c); | 50 | +{ |
45 | i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 5), "tmp423", 0x4c); | 51 | + VSBC 1111 1110 0 . 11 ... 0 ... 0 1111 . 0 . 0 ... 0 @2op_nosz |
46 | 52 | + VSBCI 1111 1110 0 . 11 ... 0 ... 1 1111 . 0 . 0 ... 0 @2op_nosz | |
47 | /* The Witherspoon expects a TMP275 but a TMP105 is compatible */ | 53 | + VCADD90 1111 1110 0 . .. ... 0 ... 0 1111 . 0 . 0 ... 0 @2op |
48 | - i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), "tmp105", 0x4a); | 54 | + VCADD270 1111 1110 0 . .. ... 0 ... 1 1111 . 0 . 0 ... 0 @2op |
49 | + i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 9), TYPE_TMP105, | 55 | +} |
50 | + 0x4a); | 56 | |
51 | 57 | # Vector miscellaneous | |
52 | /* The witherspoon board expects Epson RX8900 I2C RTC but a ds1338 is | 58 | |
53 | * good enough */ | 59 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c |
54 | @@ -XXX,XX +XXX,XX @@ static void witherspoon_bmc_i2c_init(AspeedBoardState *bmc) | 60 | index XXXXXXX..XXXXXXX 100644 |
55 | 61 | --- a/target/arm/mve_helper.c | |
56 | smbus_eeprom_init_one(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), 0x51, | 62 | +++ b/target/arm/mve_helper.c |
57 | eeprom_buf); | 63 | @@ -XXX,XX +XXX,XX @@ void HELPER(mve_vsbci)(CPUARMState *env, void *vd, void *vn, void *vm) |
58 | - i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), "pca9552", | 64 | do_vadc(env, vd, vn, vm, -1, 1, true); |
59 | + i2c_create_slave(aspeed_i2c_get_bus(DEVICE(&soc->i2c), 11), TYPE_PCA9552, | ||
60 | 0x60); | ||
61 | } | 65 | } |
62 | 66 | ||
67 | +#define DO_VCADD(OP, ESIZE, TYPE, FN0, FN1) \ | ||
68 | + void HELPER(glue(mve_, OP))(CPUARMState *env, void *vd, void *vn, void *vm) \ | ||
69 | + { \ | ||
70 | + TYPE *d = vd, *n = vn, *m = vm; \ | ||
71 | + uint16_t mask = mve_element_mask(env); \ | ||
72 | + unsigned e; \ | ||
73 | + TYPE r[16 / ESIZE]; \ | ||
74 | + /* Calculate all results first to avoid overwriting inputs */ \ | ||
75 | + for (e = 0; e < 16 / ESIZE; e++) { \ | ||
76 | + if (!(e & 1)) { \ | ||
77 | + r[e] = FN0(n[H##ESIZE(e)], m[H##ESIZE(e + 1)]); \ | ||
78 | + } else { \ | ||
79 | + r[e] = FN1(n[H##ESIZE(e)], m[H##ESIZE(e - 1)]); \ | ||
80 | + } \ | ||
81 | + } \ | ||
82 | + for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ | ||
83 | + mergemask(&d[H##ESIZE(e)], r[e], mask); \ | ||
84 | + } \ | ||
85 | + mve_advance_vpt(env); \ | ||
86 | + } | ||
87 | + | ||
88 | +#define DO_VCADD_ALL(OP, FN0, FN1) \ | ||
89 | + DO_VCADD(OP##b, 1, int8_t, FN0, FN1) \ | ||
90 | + DO_VCADD(OP##h, 2, int16_t, FN0, FN1) \ | ||
91 | + DO_VCADD(OP##w, 4, int32_t, FN0, FN1) | ||
92 | + | ||
93 | +DO_VCADD_ALL(vcadd90, DO_SUB, DO_ADD) | ||
94 | +DO_VCADD_ALL(vcadd270, DO_ADD, DO_SUB) | ||
95 | + | ||
96 | static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bool *s) | ||
97 | { | ||
98 | if (val > max) { | ||
99 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
100 | index XXXXXXX..XXXXXXX 100644 | ||
101 | --- a/target/arm/translate-mve.c | ||
102 | +++ b/target/arm/translate-mve.c | ||
103 | @@ -XXX,XX +XXX,XX @@ DO_2OP(VQRDMLSDH, vqrdmlsdh) | ||
104 | DO_2OP(VQRDMLSDHX, vqrdmlsdhx) | ||
105 | DO_2OP(VRHADD_S, vrhadds) | ||
106 | DO_2OP(VRHADD_U, vrhaddu) | ||
107 | +/* | ||
108 | + * VCADD Qd == Qm at size MO_32 is UNPREDICTABLE; we choose not to diagnose | ||
109 | + * so we can reuse the DO_2OP macro. (Our implementation calculates the | ||
110 | + * "expected" results in this case.) | ||
111 | + */ | ||
112 | +DO_2OP(VCADD90, vcadd90) | ||
113 | +DO_2OP(VCADD270, vcadd270) | ||
114 | |||
115 | static bool trans_VQDMULLB(DisasContext *s, arg_2op *a) | ||
116 | { | ||
63 | -- | 117 | -- |
64 | 2.20.1 | 118 | 2.20.1 |
65 | 119 | ||
66 | 120 | diff view generated by jsdifflib |
1 | In the stripe8() function we use a variable length array; however | 1 | Implement the MVE VHCADD insn, which is similar to VCADD |
---|---|---|---|
2 | we know that the maximum length required is MAX_NUM_BUSSES. Use | 2 | but performs a halving step. This one overlaps with VADC. |
3 | a fixed-length array and an assert instead. | ||
4 | 3 | ||
5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
7 | Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com> | 6 | Message-id: 20210617121628.20116-43-peter.maydell@linaro.org |
8 | Reviewed-by: Alistair Francis <alistair.francis@wdc.com> | ||
9 | Reviewed-by: Stefano Garzarella <sgarzare@redhat.com> | ||
10 | Message-id: 20190328152635.2794-1-peter.maydell@linaro.org | ||
11 | --- | 7 | --- |
12 | hw/ssi/xilinx_spips.c | 6 ++++-- | 8 | target/arm/helper-mve.h | 8 ++++++++ |
13 | 1 file changed, 4 insertions(+), 2 deletions(-) | 9 | target/arm/mve.decode | 8 ++++++-- |
10 | target/arm/mve_helper.c | 2 ++ | ||
11 | target/arm/translate-mve.c | 4 +++- | ||
12 | 4 files changed, 19 insertions(+), 3 deletions(-) | ||
14 | 13 | ||
15 | diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c | 14 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
16 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/ssi/xilinx_spips.c | 16 | --- a/target/arm/helper-mve.h |
18 | +++ b/hw/ssi/xilinx_spips.c | 17 | +++ b/target/arm/helper-mve.h |
19 | @@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_qspips_reset(DeviceState *d) | 18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vcadd270b, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
20 | 19 | DEF_HELPER_FLAGS_4(mve_vcadd270h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | |
21 | static inline void stripe8(uint8_t *x, int num, bool dir) | 20 | DEF_HELPER_FLAGS_4(mve_vcadd270w, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) |
21 | |||
22 | +DEF_HELPER_FLAGS_4(mve_vhcadd90b, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
23 | +DEF_HELPER_FLAGS_4(mve_vhcadd90h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
24 | +DEF_HELPER_FLAGS_4(mve_vhcadd90w, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
25 | + | ||
26 | +DEF_HELPER_FLAGS_4(mve_vhcadd270b, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
27 | +DEF_HELPER_FLAGS_4(mve_vhcadd270h, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
28 | +DEF_HELPER_FLAGS_4(mve_vhcadd270w, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr) | ||
29 | + | ||
30 | DEF_HELPER_FLAGS_4(mve_vadd_scalarb, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
31 | DEF_HELPER_FLAGS_4(mve_vadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
32 | DEF_HELPER_FLAGS_4(mve_vadd_scalarw, TCG_CALL_NO_WG, void, env, ptr, ptr, i32) | ||
33 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
34 | index XXXXXXX..XXXXXXX 100644 | ||
35 | --- a/target/arm/mve.decode | ||
36 | +++ b/target/arm/mve.decode | ||
37 | @@ -XXX,XX +XXX,XX @@ VQDMULLT 111 . 1110 0 . 11 ... 0 ... 1 1111 . 0 . 0 ... 1 @2op_sz28 | ||
38 | VRHADD_S 111 0 1111 0 . .. ... 0 ... 0 0001 . 1 . 0 ... 0 @2op | ||
39 | VRHADD_U 111 1 1111 0 . .. ... 0 ... 0 0001 . 1 . 0 ... 0 @2op | ||
40 | |||
41 | -VADC 1110 1110 0 . 11 ... 0 ... 0 1111 . 0 . 0 ... 0 @2op_nosz | ||
42 | -VADCI 1110 1110 0 . 11 ... 0 ... 1 1111 . 0 . 0 ... 0 @2op_nosz | ||
43 | +{ | ||
44 | + VADC 1110 1110 0 . 11 ... 0 ... 0 1111 . 0 . 0 ... 0 @2op_nosz | ||
45 | + VADCI 1110 1110 0 . 11 ... 0 ... 1 1111 . 0 . 0 ... 0 @2op_nosz | ||
46 | + VHCADD90 1110 1110 0 . .. ... 0 ... 0 1111 . 0 . 0 ... 0 @2op | ||
47 | + VHCADD270 1110 1110 0 . .. ... 0 ... 1 1111 . 0 . 0 ... 0 @2op | ||
48 | +} | ||
49 | |||
22 | { | 50 | { |
23 | - uint8_t r[num]; | 51 | VSBC 1111 1110 0 . 11 ... 0 ... 0 1111 . 0 . 0 ... 0 @2op_nosz |
24 | - memset(r, 0, sizeof(uint8_t) * num); | 52 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c |
25 | + uint8_t r[MAX_NUM_BUSSES]; | 53 | index XXXXXXX..XXXXXXX 100644 |
26 | int idx[2] = {0, 0}; | 54 | --- a/target/arm/mve_helper.c |
27 | int bit[2] = {0, 7}; | 55 | +++ b/target/arm/mve_helper.c |
28 | int d = dir; | 56 | @@ -XXX,XX +XXX,XX @@ void HELPER(mve_vsbci)(CPUARMState *env, void *vd, void *vn, void *vm) |
29 | 57 | ||
30 | + assert(num <= MAX_NUM_BUSSES); | 58 | DO_VCADD_ALL(vcadd90, DO_SUB, DO_ADD) |
31 | + memset(r, 0, sizeof(uint8_t) * num); | 59 | DO_VCADD_ALL(vcadd270, DO_ADD, DO_SUB) |
32 | + | 60 | +DO_VCADD_ALL(vhcadd90, do_vhsub_s, do_vhadd_s) |
33 | for (idx[0] = 0; idx[0] < num; ++idx[0]) { | 61 | +DO_VCADD_ALL(vhcadd270, do_vhadd_s, do_vhsub_s) |
34 | for (bit[0] = 7; bit[0] >= 0; bit[0]--) { | 62 | |
35 | r[idx[!d]] |= x[idx[d]] & 1 << bit[d] ? 1 << bit[!d] : 0; | 63 | static inline int32_t do_sat_bhw(int64_t val, int64_t min, int64_t max, bool *s) |
64 | { | ||
65 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
66 | index XXXXXXX..XXXXXXX 100644 | ||
67 | --- a/target/arm/translate-mve.c | ||
68 | +++ b/target/arm/translate-mve.c | ||
69 | @@ -XXX,XX +XXX,XX @@ DO_2OP(VRHADD_U, vrhaddu) | ||
70 | /* | ||
71 | * VCADD Qd == Qm at size MO_32 is UNPREDICTABLE; we choose not to diagnose | ||
72 | * so we can reuse the DO_2OP macro. (Our implementation calculates the | ||
73 | - * "expected" results in this case.) | ||
74 | + * "expected" results in this case.) Similarly for VHCADD. | ||
75 | */ | ||
76 | DO_2OP(VCADD90, vcadd90) | ||
77 | DO_2OP(VCADD270, vcadd270) | ||
78 | +DO_2OP(VHCADD90, vhcadd90) | ||
79 | +DO_2OP(VHCADD270, vhcadd270) | ||
80 | |||
81 | static bool trans_VQDMULLB(DisasContext *s, arg_2op *a) | ||
82 | { | ||
36 | -- | 83 | -- |
37 | 2.20.1 | 84 | 2.20.1 |
38 | 85 | ||
39 | 86 | diff view generated by jsdifflib |
1 | Implement the VLSTM instruction for v7M for the FPU present case. | 1 | Implement the MVE VADDV insn, which performs an addition |
---|---|---|---|
2 | across vector lanes. | ||
2 | 3 | ||
3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 5 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 20190416125744.27770-25-peter.maydell@linaro.org | 6 | Message-id: 20210617121628.20116-44-peter.maydell@linaro.org |
6 | --- | 7 | --- |
7 | target/arm/cpu.h | 2 + | 8 | target/arm/helper-mve.h | 7 +++++++ |
8 | target/arm/helper.h | 2 + | 9 | target/arm/mve.decode | 2 ++ |
9 | target/arm/helper.c | 84 ++++++++++++++++++++++++++++++++++++++++++ | 10 | target/arm/mve_helper.c | 24 +++++++++++++++++++++ |
10 | target/arm/translate.c | 15 +++++++- | 11 | target/arm/translate-mve.c | 43 ++++++++++++++++++++++++++++++++++++++ |
11 | 4 files changed, 102 insertions(+), 1 deletion(-) | 12 | 4 files changed, 76 insertions(+) |
12 | 13 | ||
13 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 14 | diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h |
14 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/cpu.h | 16 | --- a/target/arm/helper-mve.h |
16 | +++ b/target/arm/cpu.h | 17 | +++ b/target/arm/helper-mve.h |
17 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_4(mve_vrmlaldavhuw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
18 | #define EXCP_INVSTATE 18 /* v7M INVSTATE UsageFault */ | 19 | |
19 | #define EXCP_STKOF 19 /* v8M STKOF UsageFault */ | 20 | DEF_HELPER_FLAGS_4(mve_vrmlsldavhsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
20 | #define EXCP_LAZYFP 20 /* v7M fault during lazy FP stacking */ | 21 | DEF_HELPER_FLAGS_4(mve_vrmlsldavhxsw, TCG_CALL_NO_WG, i64, env, ptr, ptr, i64) |
21 | +#define EXCP_LSERR 21 /* v8M LSERR SecureFault */ | 22 | + |
22 | +#define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ | 23 | +DEF_HELPER_FLAGS_3(mve_vaddvsb, TCG_CALL_NO_WG, i32, env, ptr, i32) |
23 | /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ | 24 | +DEF_HELPER_FLAGS_3(mve_vaddvub, TCG_CALL_NO_WG, i32, env, ptr, i32) |
24 | 25 | +DEF_HELPER_FLAGS_3(mve_vaddvsh, TCG_CALL_NO_WG, i32, env, ptr, i32) | |
25 | #define ARMV7M_EXCP_RESET 1 | 26 | +DEF_HELPER_FLAGS_3(mve_vaddvuh, TCG_CALL_NO_WG, i32, env, ptr, i32) |
26 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 27 | +DEF_HELPER_FLAGS_3(mve_vaddvsw, TCG_CALL_NO_WG, i32, env, ptr, i32) |
28 | +DEF_HELPER_FLAGS_3(mve_vaddvuw, TCG_CALL_NO_WG, i32, env, ptr, i32) | ||
29 | diff --git a/target/arm/mve.decode b/target/arm/mve.decode | ||
27 | index XXXXXXX..XXXXXXX 100644 | 30 | index XXXXXXX..XXXXXXX 100644 |
28 | --- a/target/arm/helper.h | 31 | --- a/target/arm/mve.decode |
29 | +++ b/target/arm/helper.h | 32 | +++ b/target/arm/mve.decode |
30 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(v7m_tt, i32, env, i32, i32) | 33 | @@ -XXX,XX +XXX,XX @@ VBRSR 1111 1110 0 . .. ... 1 ... 1 1110 . 110 .... @2scalar |
31 | 34 | VQDMULH_scalar 1110 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar | |
32 | DEF_HELPER_1(v7m_preserve_fp_state, void, env) | 35 | VQRDMULH_scalar 1111 1110 0 . .. ... 1 ... 0 1110 . 110 .... @2scalar |
33 | 36 | ||
34 | +DEF_HELPER_2(v7m_vlstm, void, env, i32) | 37 | +# Vector add across vector |
38 | +VADDV 111 u:1 1110 1111 size:2 01 ... 0 1111 0 0 a:1 0 qm:3 0 rda=%rdalo | ||
39 | |||
40 | # Predicate operations | ||
41 | %mask_22_13 22:1 13:3 | ||
42 | diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c | ||
43 | index XXXXXXX..XXXXXXX 100644 | ||
44 | --- a/target/arm/mve_helper.c | ||
45 | +++ b/target/arm/mve_helper.c | ||
46 | @@ -XXX,XX +XXX,XX @@ DO_LDAVH(vrmlaldavhuw, 4, uint32_t, false, int128_add, int128_add, int128_make64 | ||
47 | |||
48 | DO_LDAVH(vrmlsldavhsw, 4, int32_t, false, int128_add, int128_sub, int128_makes64) | ||
49 | DO_LDAVH(vrmlsldavhxsw, 4, int32_t, true, int128_add, int128_sub, int128_makes64) | ||
35 | + | 50 | + |
36 | DEF_HELPER_2(v8m_stackcheck, void, env, i32) | 51 | +/* Vector add across vector */ |
37 | 52 | +#define DO_VADDV(OP, ESIZE, TYPE) \ | |
38 | DEF_HELPER_4(access_check_cp_reg, void, env, ptr, i32, i32) | 53 | + uint32_t HELPER(glue(mve_, OP))(CPUARMState *env, void *vm, \ |
39 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 54 | + uint32_t ra) \ |
55 | + { \ | ||
56 | + uint16_t mask = mve_element_mask(env); \ | ||
57 | + unsigned e; \ | ||
58 | + TYPE *m = vm; \ | ||
59 | + for (e = 0; e < 16 / ESIZE; e++, mask >>= ESIZE) { \ | ||
60 | + if (mask & 1) { \ | ||
61 | + ra += m[H##ESIZE(e)]; \ | ||
62 | + } \ | ||
63 | + } \ | ||
64 | + mve_advance_vpt(env); \ | ||
65 | + return ra; \ | ||
66 | + } \ | ||
67 | + | ||
68 | +DO_VADDV(vaddvsb, 1, uint8_t) | ||
69 | +DO_VADDV(vaddvsh, 2, uint16_t) | ||
70 | +DO_VADDV(vaddvsw, 4, uint32_t) | ||
71 | +DO_VADDV(vaddvub, 1, uint8_t) | ||
72 | +DO_VADDV(vaddvuh, 2, uint16_t) | ||
73 | +DO_VADDV(vaddvuw, 4, uint32_t) | ||
74 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
40 | index XXXXXXX..XXXXXXX 100644 | 75 | index XXXXXXX..XXXXXXX 100644 |
41 | --- a/target/arm/helper.c | 76 | --- a/target/arm/translate-mve.c |
42 | +++ b/target/arm/helper.c | 77 | +++ b/target/arm/translate-mve.c |
43 | @@ -XXX,XX +XXX,XX @@ void HELPER(v7m_preserve_fp_state)(CPUARMState *env) | 78 | @@ -XXX,XX +XXX,XX @@ typedef void MVEGenOneOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); |
44 | g_assert_not_reached(); | 79 | typedef void MVEGenTwoOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr); |
80 | typedef void MVEGenTwoOpScalarFn(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
81 | typedef void MVEGenDualAccOpFn(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i64); | ||
82 | +typedef void MVEGenVADDVFn(TCGv_i32, TCGv_ptr, TCGv_ptr, TCGv_i32); | ||
83 | |||
84 | /* Return the offset of a Qn register (same semantics as aa32_vfp_qreg()) */ | ||
85 | static inline long mve_qreg_offset(unsigned reg) | ||
86 | @@ -XXX,XX +XXX,XX @@ static bool trans_VPST(DisasContext *s, arg_VPST *a) | ||
87 | mve_update_and_store_eci(s); | ||
88 | return true; | ||
45 | } | 89 | } |
46 | 90 | + | |
47 | +void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr) | 91 | +static bool trans_VADDV(DisasContext *s, arg_VADDV *a) |
48 | +{ | 92 | +{ |
49 | + /* translate.c should never generate calls here in user-only mode */ | 93 | + /* VADDV: vector add across vector */ |
50 | + g_assert_not_reached(); | 94 | + static MVEGenVADDVFn * const fns[4][2] = { |
51 | +} | 95 | + { gen_helper_mve_vaddvsb, gen_helper_mve_vaddvub }, |
96 | + { gen_helper_mve_vaddvsh, gen_helper_mve_vaddvuh }, | ||
97 | + { gen_helper_mve_vaddvsw, gen_helper_mve_vaddvuw }, | ||
98 | + { NULL, NULL } | ||
99 | + }; | ||
100 | + TCGv_ptr qm; | ||
101 | + TCGv_i32 rda; | ||
52 | + | 102 | + |
53 | uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) | 103 | + if (!dc_isar_feature(aa32_mve, s) || |
54 | { | 104 | + a->size == 3) { |
55 | /* The TT instructions can be used by unprivileged code, but in | 105 | + return false; |
56 | @@ -XXX,XX +XXX,XX @@ static void v7m_update_fpccr(CPUARMState *env, uint32_t frameptr, | ||
57 | } | ||
58 | } | ||
59 | |||
60 | +void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr) | ||
61 | +{ | ||
62 | + /* fptr is the value of Rn, the frame pointer we store the FP regs to */ | ||
63 | + bool s = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_S_MASK; | ||
64 | + bool lspact = env->v7m.fpccr[s] & R_V7M_FPCCR_LSPACT_MASK; | ||
65 | + | ||
66 | + assert(env->v7m.secure); | ||
67 | + | ||
68 | + if (!(env->v7m.control[M_REG_S] & R_V7M_CONTROL_SFPA_MASK)) { | ||
69 | + return; | ||
70 | + } | 106 | + } |
71 | + | 107 | + if (!mve_eci_check(s) || !vfp_access_check(s)) { |
72 | + /* Check access to the coprocessor is permitted */ | 108 | + return true; |
73 | + if (!v7m_cpacr_pass(env, true, arm_current_el(env) != 0)) { | ||
74 | + raise_exception_ra(env, EXCP_NOCP, 0, 1, GETPC()); | ||
75 | + } | ||
76 | + | ||
77 | + if (lspact) { | ||
78 | + /* LSPACT should not be active when there is active FP state */ | ||
79 | + raise_exception_ra(env, EXCP_LSERR, 0, 1, GETPC()); | ||
80 | + } | ||
81 | + | ||
82 | + if (fptr & 7) { | ||
83 | + raise_exception_ra(env, EXCP_UNALIGNED, 0, 1, GETPC()); | ||
84 | + } | 109 | + } |
85 | + | 110 | + |
86 | + /* | 111 | + /* |
87 | + * Note that we do not use v7m_stack_write() here, because the | 112 | + * This insn is subject to beat-wise execution. Partial execution |
88 | + * accesses should not set the FSR bits for stacking errors if they | 113 | + * of an A=0 (no-accumulate) insn which does not execute the first |
89 | + * fail. (In pseudocode terms, they are AccType_NORMAL, not AccType_STACK | 114 | + * beat must start with the current value of Rda, not zero. |
90 | + * or AccType_LAZYFP). Faults in cpu_stl_data() will throw exceptions | ||
91 | + * and longjmp out. | ||
92 | + */ | 115 | + */ |
93 | + if (!(env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_LSPEN_MASK)) { | 116 | + if (a->a || mve_skip_first_beat(s)) { |
94 | + bool ts = env->v7m.fpccr[M_REG_S] & R_V7M_FPCCR_TS_MASK; | 117 | + /* Accumulate input from Rda */ |
95 | + int i; | 118 | + rda = load_reg(s, a->rda); |
96 | + | ||
97 | + for (i = 0; i < (ts ? 32 : 16); i += 2) { | ||
98 | + uint64_t dn = *aa32_vfp_dreg(env, i / 2); | ||
99 | + uint32_t faddr = fptr + 4 * i; | ||
100 | + uint32_t slo = extract64(dn, 0, 32); | ||
101 | + uint32_t shi = extract64(dn, 32, 32); | ||
102 | + | ||
103 | + if (i >= 16) { | ||
104 | + faddr += 8; /* skip the slot for the FPSCR */ | ||
105 | + } | ||
106 | + cpu_stl_data(env, faddr, slo); | ||
107 | + cpu_stl_data(env, faddr + 4, shi); | ||
108 | + } | ||
109 | + cpu_stl_data(env, fptr + 0x40, vfp_get_fpscr(env)); | ||
110 | + | ||
111 | + /* | ||
112 | + * If TS is 0 then s0 to s15 and FPSCR are UNKNOWN; we choose to | ||
113 | + * leave them unchanged, matching our choice in v7m_preserve_fp_state. | ||
114 | + */ | ||
115 | + if (ts) { | ||
116 | + for (i = 0; i < 32; i += 2) { | ||
117 | + *aa32_vfp_dreg(env, i / 2) = 0; | ||
118 | + } | ||
119 | + vfp_set_fpscr(env, 0); | ||
120 | + } | ||
121 | + } else { | 119 | + } else { |
122 | + v7m_update_fpccr(env, fptr, false); | 120 | + /* Accumulate starting at zero */ |
121 | + rda = tcg_const_i32(0); | ||
123 | + } | 122 | + } |
124 | + | 123 | + |
125 | + env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_FPCA_MASK; | 124 | + qm = mve_qreg_ptr(a->qm); |
125 | + fns[a->size][a->u](rda, cpu_env, qm, rda); | ||
126 | + store_reg(s, a->rda, rda); | ||
127 | + tcg_temp_free_ptr(qm); | ||
128 | + | ||
129 | + mve_update_eci(s); | ||
130 | + return true; | ||
126 | +} | 131 | +} |
127 | + | ||
128 | static bool v7m_push_stack(ARMCPU *cpu) | ||
129 | { | ||
130 | /* Do the "set up stack frame" part of exception entry, | ||
131 | @@ -XXX,XX +XXX,XX @@ static void arm_log_exception(int idx) | ||
132 | [EXCP_INVSTATE] = "v7M INVSTATE UsageFault", | ||
133 | [EXCP_STKOF] = "v8M STKOF UsageFault", | ||
134 | [EXCP_LAZYFP] = "v7M exception during lazy FP stacking", | ||
135 | + [EXCP_LSERR] = "v8M LSERR UsageFault", | ||
136 | + [EXCP_UNALIGNED] = "v7M UNALIGNED UsageFault", | ||
137 | }; | ||
138 | |||
139 | if (idx >= 0 && idx < ARRAY_SIZE(excnames)) { | ||
140 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) | ||
141 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); | ||
142 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_STKOF_MASK; | ||
143 | break; | ||
144 | + case EXCP_LSERR: | ||
145 | + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false); | ||
146 | + env->v7m.sfsr |= R_V7M_SFSR_LSERR_MASK; | ||
147 | + break; | ||
148 | + case EXCP_UNALIGNED: | ||
149 | + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); | ||
150 | + env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNALIGNED_MASK; | ||
151 | + break; | ||
152 | case EXCP_SWI: | ||
153 | /* The PC already points to the next instruction. */ | ||
154 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC, env->v7m.secure); | ||
155 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
156 | index XXXXXXX..XXXXXXX 100644 | ||
157 | --- a/target/arm/translate.c | ||
158 | +++ b/target/arm/translate.c | ||
159 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) | ||
160 | if (!s->v8m_secure || (insn & 0x0040f0ff)) { | ||
161 | goto illegal_op; | ||
162 | } | ||
163 | - /* Just NOP since FP support is not implemented */ | ||
164 | + | ||
165 | + if (arm_dc_feature(s, ARM_FEATURE_VFP)) { | ||
166 | + TCGv_i32 fptr = load_reg(s, rn); | ||
167 | + | ||
168 | + if (extract32(insn, 20, 1)) { | ||
169 | + /* VLLDM */ | ||
170 | + } else { | ||
171 | + gen_helper_v7m_vlstm(cpu_env, fptr); | ||
172 | + } | ||
173 | + tcg_temp_free_i32(fptr); | ||
174 | + | ||
175 | + /* End the TB, because we have updated FP control bits */ | ||
176 | + s->base.is_jmp = DISAS_UPDATE; | ||
177 | + } | ||
178 | break; | ||
179 | } | ||
180 | if (arm_dc_feature(s, ARM_FEATURE_VFP) && | ||
181 | -- | 132 | -- |
182 | 2.20.1 | 133 | 2.20.1 |
183 | 134 | ||
184 | 135 | diff view generated by jsdifflib |
1 | Like AArch64, M-profile floating point has no FPEXC enable | 1 | In a CPU with MVE, the VMOV (vector lane to general-purpose register) |
---|---|---|---|
2 | bit to gate floating point; so always set the VFPEN TB flag. | 2 | and VMOV (general-purpose register to vector lane) insns are not |
3 | predicated, but they are subject to beatwise execution if they | ||
4 | are not in an IT block. | ||
3 | 5 | ||
4 | M-profile also has CPACR and NSACR similar to A-profile; | 6 | Since our implementation always executes all 4 beats in one tick, |
5 | they behave slightly differently: | 7 | this means only that we need to handle PSR.ECI: |
6 | * the CPACR is banked between Secure and Non-Secure | 8 | * we must do the usual check for bad ECI state |
7 | * if the NSACR forces a trap then this is taken to | 9 | * we must advance ECI state if the insn succeeds |
8 | the Secure state, not the Non-Secure state | 10 | * if ECI says we should not be executing the beat corresponding |
11 | to the lane of the vector register being accessed then we | ||
12 | should skip performing the move | ||
9 | 13 | ||
10 | Honour the CPACR and NSACR settings. The NSACR handling | 14 | Note that if PSR.ECI is non-zero then we cannot be in an IT block. |
11 | requires us to borrow the exception.target_el field | ||
12 | (usually meaningless for M profile) to distinguish the | ||
13 | NOCP UsageFault taken to Secure state from the more | ||
14 | usual fault taken to the current security state. | ||
15 | 15 | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 17 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
18 | Message-id: 20190416125744.27770-6-peter.maydell@linaro.org | 18 | Message-id: 20210617121628.20116-45-peter.maydell@linaro.org |
19 | --- | 19 | --- |
20 | target/arm/helper.c | 55 +++++++++++++++++++++++++++++++++++++++--- | 20 | target/arm/translate-a32.h | 2 + |
21 | target/arm/translate.c | 10 ++++++-- | 21 | target/arm/translate-mve.c | 4 +- |
22 | 2 files changed, 60 insertions(+), 5 deletions(-) | 22 | target/arm/translate-vfp.c | 77 +++++++++++++++++++++++++++++++++++--- |
23 | 3 files changed, 75 insertions(+), 8 deletions(-) | ||
23 | 24 | ||
24 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 25 | diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h |
25 | index XXXXXXX..XXXXXXX 100644 | 26 | index XXXXXXX..XXXXXXX 100644 |
26 | --- a/target/arm/helper.c | 27 | --- a/target/arm/translate-a32.h |
27 | +++ b/target/arm/helper.c | 28 | +++ b/target/arm/translate-a32.h |
28 | @@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx, | 29 | @@ -XXX,XX +XXX,XX @@ long neon_full_reg_offset(unsigned reg); |
29 | return target_el; | 30 | long neon_element_offset(int reg, int element, MemOp memop); |
31 | void gen_rev16(TCGv_i32 dest, TCGv_i32 var); | ||
32 | void clear_eci_state(DisasContext *s); | ||
33 | +bool mve_eci_check(DisasContext *s); | ||
34 | +void mve_update_and_store_eci(DisasContext *s); | ||
35 | |||
36 | static inline TCGv_i32 load_cpu_offset(int offset) | ||
37 | { | ||
38 | diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c | ||
39 | index XXXXXXX..XXXXXXX 100644 | ||
40 | --- a/target/arm/translate-mve.c | ||
41 | +++ b/target/arm/translate-mve.c | ||
42 | @@ -XXX,XX +XXX,XX @@ static bool mve_check_qreg_bank(DisasContext *s, int qmask) | ||
43 | return qmask < 8; | ||
30 | } | 44 | } |
31 | 45 | ||
32 | +/* | 46 | -static bool mve_eci_check(DisasContext *s) |
33 | + * Return true if the v7M CPACR permits access to the FPU for the specified | 47 | +bool mve_eci_check(DisasContext *s) |
34 | + * security state and privilege level. | 48 | { |
35 | + */ | 49 | /* |
36 | +static bool v7m_cpacr_pass(CPUARMState *env, bool is_secure, bool is_priv) | 50 | * This is a beatwise insn: check that ECI is valid (not a |
51 | @@ -XXX,XX +XXX,XX @@ static void mve_update_eci(DisasContext *s) | ||
52 | } | ||
53 | } | ||
54 | |||
55 | -static void mve_update_and_store_eci(DisasContext *s) | ||
56 | +void mve_update_and_store_eci(DisasContext *s) | ||
57 | { | ||
58 | /* | ||
59 | * For insns which don't call a helper function that will call | ||
60 | diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c | ||
61 | index XXXXXXX..XXXXXXX 100644 | ||
62 | --- a/target/arm/translate-vfp.c | ||
63 | +++ b/target/arm/translate-vfp.c | ||
64 | @@ -XXX,XX +XXX,XX @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) | ||
65 | return true; | ||
66 | } | ||
67 | |||
68 | +static bool mve_skip_vmov(DisasContext *s, int vn, int index, int size) | ||
37 | +{ | 69 | +{ |
38 | + switch (extract32(env->v7m.cpacr[is_secure], 20, 2)) { | 70 | + /* |
39 | + case 0: | 71 | + * In a CPU with MVE, the VMOV (vector lane to general-purpose register) |
40 | + case 2: /* UNPREDICTABLE: we treat like 0 */ | 72 | + * and VMOV (general-purpose register to vector lane) insns are not |
73 | + * predicated, but they are subject to beatwise execution if they are | ||
74 | + * not in an IT block. | ||
75 | + * | ||
76 | + * Since our implementation always executes all 4 beats in one tick, | ||
77 | + * this means only that if PSR.ECI says we should not be executing | ||
78 | + * the beat corresponding to the lane of the vector register being | ||
79 | + * accessed then we should skip performing the move, and that we need | ||
80 | + * to do the usual check for bad ECI state and advance of ECI state. | ||
81 | + * | ||
82 | + * Note that if PSR.ECI is non-zero then we cannot be in an IT block. | ||
83 | + * | ||
84 | + * Return true if this VMOV scalar <-> gpreg should be skipped because | ||
85 | + * the MVE PSR.ECI state says we skip the beat where the store happens. | ||
86 | + */ | ||
87 | + | ||
88 | + /* Calculate the byte offset into Qn which we're going to access */ | ||
89 | + int ofs = (index << size) + ((vn & 1) * 8); | ||
90 | + | ||
91 | + if (!dc_isar_feature(aa32_mve, s)) { | ||
41 | + return false; | 92 | + return false; |
42 | + case 1: | 93 | + } |
43 | + return is_priv; | 94 | + |
44 | + case 3: | 95 | + switch (s->eci) { |
45 | + return true; | 96 | + case ECI_NONE: |
97 | + return false; | ||
98 | + case ECI_A0: | ||
99 | + return ofs < 4; | ||
100 | + case ECI_A0A1: | ||
101 | + return ofs < 8; | ||
102 | + case ECI_A0A1A2: | ||
103 | + case ECI_A0A1A2B0: | ||
104 | + return ofs < 12; | ||
46 | + default: | 105 | + default: |
47 | + g_assert_not_reached(); | 106 | + g_assert_not_reached(); |
48 | + } | 107 | + } |
49 | +} | 108 | +} |
50 | + | 109 | + |
51 | static bool v7m_stack_write(ARMCPU *cpu, uint32_t addr, uint32_t value, | 110 | static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a) |
52 | ARMMMUIdx mmu_idx, bool ignfault) | ||
53 | { | 111 | { |
54 | @@ -XXX,XX +XXX,XX @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) | 112 | /* VMOV scalar to general purpose register */ |
55 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_UNDEFINSTR_MASK; | 113 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_to_gp *a) |
56 | break; | 114 | return false; |
57 | case EXCP_NOCP: | 115 | } |
58 | - armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); | 116 | |
59 | - env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_NOCP_MASK; | 117 | + if (dc_isar_feature(aa32_mve, s)) { |
60 | + { | 118 | + if (!mve_eci_check(s)) { |
61 | + /* | 119 | + return true; |
62 | + * NOCP might be directed to something other than the current | ||
63 | + * security state if this fault is because of NSACR; we indicate | ||
64 | + * the target security state using exception.target_el. | ||
65 | + */ | ||
66 | + int target_secstate; | ||
67 | + | ||
68 | + if (env->exception.target_el == 3) { | ||
69 | + target_secstate = M_REG_S; | ||
70 | + } else { | ||
71 | + target_secstate = env->v7m.secure; | ||
72 | + } | 120 | + } |
73 | + armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, target_secstate); | ||
74 | + env->v7m.cfsr[target_secstate] |= R_V7M_CFSR_NOCP_MASK; | ||
75 | break; | ||
76 | + } | ||
77 | case EXCP_INVSTATE: | ||
78 | armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, env->v7m.secure); | ||
79 | env->v7m.cfsr[env->v7m.secure] |= R_V7M_CFSR_INVSTATE_MASK; | ||
80 | @@ -XXX,XX +XXX,XX @@ int fp_exception_el(CPUARMState *env, int cur_el) | ||
81 | return 0; | ||
82 | } | ||
83 | |||
84 | + if (arm_feature(env, ARM_FEATURE_M)) { | ||
85 | + /* CPACR can cause a NOCP UsageFault taken to current security state */ | ||
86 | + if (!v7m_cpacr_pass(env, env->v7m.secure, cur_el != 0)) { | ||
87 | + return 1; | ||
88 | + } | ||
89 | + | ||
90 | + if (arm_feature(env, ARM_FEATURE_M_SECURITY) && !env->v7m.secure) { | ||
91 | + if (!extract32(env->v7m.nsacr, 10, 1)) { | ||
92 | + /* FP insns cause a NOCP UsageFault taken to Secure */ | ||
93 | + return 3; | ||
94 | + } | ||
95 | + } | ||
96 | + | ||
97 | + return 0; | ||
98 | + } | 121 | + } |
99 | + | 122 | + |
100 | /* The CPACR controls traps to EL1, or PL1 if we're 32 bit: | 123 | if (!vfp_access_check(s)) { |
101 | * 0, 2 : trap EL0 and EL1/PL1 accesses | 124 | return true; |
102 | * 1 : trap only EL0 accesses | 125 | } |
103 | @@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, | 126 | |
104 | flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env)); | 127 | - tmp = tcg_temp_new_i32(); |
105 | flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); | 128 | - read_neon_element32(tmp, a->vn, a->index, a->size | (a->u ? 0 : MO_SIGN)); |
106 | if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) | 129 | - store_reg(s, a->rt, tmp); |
107 | - || arm_el_is_aa64(env, 1)) { | 130 | + if (!mve_skip_vmov(s, a->vn, a->index, a->size)) { |
108 | + || arm_el_is_aa64(env, 1) || arm_feature(env, ARM_FEATURE_M)) { | 131 | + tmp = tcg_temp_new_i32(); |
109 | flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); | 132 | + read_neon_element32(tmp, a->vn, a->index, |
110 | } | 133 | + a->size | (a->u ? 0 : MO_SIGN)); |
111 | flags = FIELD_DP32(flags, TBFLAG_A32, XSCALE_CPAR, env->cp15.c15_cpar); | 134 | + store_reg(s, a->rt, tmp); |
112 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 135 | + } |
113 | index XXXXXXX..XXXXXXX 100644 | 136 | |
114 | --- a/target/arm/translate.c | 137 | + if (dc_isar_feature(aa32_mve, s)) { |
115 | +++ b/target/arm/translate.c | 138 | + mve_update_and_store_eci(s); |
116 | @@ -XXX,XX +XXX,XX @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) | 139 | + } |
117 | * for attempts to execute invalid vfp/neon encodings with FP disabled. | 140 | return true; |
118 | */ | 141 | } |
119 | if (s->fp_excp_el) { | 142 | |
120 | - gen_exception_insn(s, 4, EXCP_UDEF, | 143 | @@ -XXX,XX +XXX,XX @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMOV_from_gp *a) |
121 | - syn_fp_access_trap(1, 0xe, false), s->fp_excp_el); | 144 | return false; |
122 | + if (arm_dc_feature(s, ARM_FEATURE_M)) { | 145 | } |
123 | + gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(), | 146 | |
124 | + s->fp_excp_el); | 147 | + if (dc_isar_feature(aa32_mve, s)) { |
125 | + } else { | 148 | + if (!mve_eci_check(s)) { |
126 | + gen_exception_insn(s, 4, EXCP_UDEF, | 149 | + return true; |
127 | + syn_fp_access_trap(1, 0xe, false), | ||
128 | + s->fp_excp_el); | ||
129 | + } | 150 | + } |
130 | return 0; | 151 | + } |
152 | + | ||
153 | if (!vfp_access_check(s)) { | ||
154 | return true; | ||
131 | } | 155 | } |
156 | |||
157 | - tmp = load_reg(s, a->rt); | ||
158 | - write_neon_element32(tmp, a->vn, a->index, a->size); | ||
159 | - tcg_temp_free_i32(tmp); | ||
160 | + if (!mve_skip_vmov(s, a->vn, a->index, a->size)) { | ||
161 | + tmp = load_reg(s, a->rt); | ||
162 | + write_neon_element32(tmp, a->vn, a->index, a->size); | ||
163 | + tcg_temp_free_i32(tmp); | ||
164 | + } | ||
165 | |||
166 | + if (dc_isar_feature(aa32_mve, s)) { | ||
167 | + mve_update_and_store_eci(s); | ||
168 | + } | ||
169 | return true; | ||
170 | } | ||
132 | 171 | ||
133 | -- | 172 | -- |
134 | 2.20.1 | 173 | 2.20.1 |
135 | 174 | ||
136 | 175 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | From: Peter Collingbourne <pcc@google.com> |
---|---|---|---|
2 | 2 | ||
3 | The SMMUNotifierNode struct is not necessary and brings extra | 3 | MTE3 introduces an asymmetric tag checking mode, in which loads are |
4 | complexity so let's remove it. We now directly track the SMMUDevices | 4 | checked synchronously and stores are checked asynchronously. Add |
5 | which have registered IOMMU MR notifiers. | 5 | support for it. |
6 | 6 | ||
7 | This is inspired from the same transformation on intel-iommu | 7 | Signed-off-by: Peter Collingbourne <pcc@google.com> |
8 | done in commit b4a4ba0d68f50f218ee3957b6638dbee32a5eeef | 8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | ("intel-iommu: remove IntelIOMMUNotifierNode") | 9 | Message-id: 20210616195614.11785-1-pcc@google.com |
10 | 10 | [PMM: Add line to emulation.rst] | |
11 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
12 | Reviewed-by: Peter Xu <peterx@redhat.com> | ||
13 | Message-id: 20190409160219.19026-1-eric.auger@redhat.com | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
15 | --- | 12 | --- |
16 | include/hw/arm/smmu-common.h | 8 ++------ | 13 | docs/system/arm/emulation.rst | 1 + |
17 | hw/arm/smmu-common.c | 6 +++--- | 14 | target/arm/cpu64.c | 2 +- |
18 | hw/arm/smmuv3.c | 28 +++++++--------------------- | 15 | target/arm/mte_helper.c | 82 ++++++++++++++++++++++------------- |
19 | 3 files changed, 12 insertions(+), 30 deletions(-) | 16 | 3 files changed, 53 insertions(+), 32 deletions(-) |
20 | 17 | ||
21 | diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h | 18 | diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst |
22 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
23 | --- a/include/hw/arm/smmu-common.h | 20 | --- a/docs/system/arm/emulation.rst |
24 | +++ b/include/hw/arm/smmu-common.h | 21 | +++ b/docs/system/arm/emulation.rst |
25 | @@ -XXX,XX +XXX,XX @@ typedef struct SMMUDevice { | 22 | @@ -XXX,XX +XXX,XX @@ the following architecture extensions: |
26 | AddressSpace as; | 23 | - FEAT_LSE (Large System Extensions) |
27 | uint32_t cfg_cache_hits; | 24 | - FEAT_MTE (Memory Tagging Extension) |
28 | uint32_t cfg_cache_misses; | 25 | - FEAT_MTE2 (Memory Tagging Extension) |
29 | + QLIST_ENTRY(SMMUDevice) next; | 26 | +- FEAT_MTE3 (MTE Asymmetric Fault Handling) |
30 | } SMMUDevice; | 27 | - FEAT_PAN (Privileged access never) |
31 | 28 | - FEAT_PAN2 (AT S1E1R and AT S1E1W instruction variants affected by PSTATE.PAN) | |
32 | -typedef struct SMMUNotifierNode { | 29 | - FEAT_PAuth (Pointer authentication) |
33 | - SMMUDevice *sdev; | 30 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c |
34 | - QLIST_ENTRY(SMMUNotifierNode) next; | ||
35 | -} SMMUNotifierNode; | ||
36 | - | ||
37 | typedef struct SMMUPciBus { | ||
38 | PCIBus *bus; | ||
39 | SMMUDevice *pbdev[0]; /* Parent array is sparse, so dynamically alloc */ | ||
40 | @@ -XXX,XX +XXX,XX @@ typedef struct SMMUState { | ||
41 | GHashTable *iotlb; | ||
42 | SMMUPciBus *smmu_pcibus_by_bus_num[SMMU_PCI_BUS_MAX]; | ||
43 | PCIBus *pci_bus; | ||
44 | - QLIST_HEAD(, SMMUNotifierNode) notifiers_list; | ||
45 | + QLIST_HEAD(, SMMUDevice) devices_with_notifiers; | ||
46 | uint8_t bus_num; | ||
47 | PCIBus *primary_bus; | ||
48 | } SMMUState; | ||
49 | diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c | ||
50 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
51 | --- a/hw/arm/smmu-common.c | 32 | --- a/target/arm/cpu64.c |
52 | +++ b/hw/arm/smmu-common.c | 33 | +++ b/target/arm/cpu64.c |
53 | @@ -XXX,XX +XXX,XX @@ inline void smmu_inv_notifiers_mr(IOMMUMemoryRegion *mr) | 34 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) |
54 | /* Unmap all notifiers of all mr's */ | 35 | * during realize if the board provides no tag memory, much like |
55 | void smmu_inv_notifiers_all(SMMUState *s) | 36 | * we do for EL2 with the virtualization=on property. |
56 | { | 37 | */ |
57 | - SMMUNotifierNode *node; | 38 | - t = FIELD_DP64(t, ID_AA64PFR1, MTE, 2); |
58 | + SMMUDevice *sdev; | 39 | + t = FIELD_DP64(t, ID_AA64PFR1, MTE, 3); |
59 | 40 | cpu->isar.id_aa64pfr1 = t; | |
60 | - QLIST_FOREACH(node, &s->notifiers_list, next) { | 41 | |
61 | - smmu_inv_notifiers_mr(&node->sdev->iommu); | 42 | t = cpu->isar.id_aa64mmfr0; |
62 | + QLIST_FOREACH(sdev, &s->devices_with_notifiers, next) { | 43 | diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c |
63 | + smmu_inv_notifiers_mr(&sdev->iommu); | 44 | index XXXXXXX..XXXXXXX 100644 |
45 | --- a/target/arm/mte_helper.c | ||
46 | +++ b/target/arm/mte_helper.c | ||
47 | @@ -XXX,XX +XXX,XX @@ void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr, uint64_t val) | ||
64 | } | 48 | } |
65 | } | 49 | } |
66 | 50 | ||
67 | diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c | 51 | +static void mte_sync_check_fail(CPUARMState *env, uint32_t desc, |
68 | index XXXXXXX..XXXXXXX 100644 | 52 | + uint64_t dirty_ptr, uintptr_t ra) |
69 | --- a/hw/arm/smmuv3.c | 53 | +{ |
70 | +++ b/hw/arm/smmuv3.c | 54 | + int is_write, syn; |
71 | @@ -XXX,XX +XXX,XX @@ static void smmuv3_notify_iova(IOMMUMemoryRegion *mr, | 55 | + |
72 | /* invalidate an asid/iova tuple in all mr's */ | 56 | + env->exception.vaddress = dirty_ptr; |
73 | static void smmuv3_inv_notifiers_iova(SMMUState *s, int asid, dma_addr_t iova) | 57 | + |
58 | + is_write = FIELD_EX32(desc, MTEDESC, WRITE); | ||
59 | + syn = syn_data_abort_no_iss(arm_current_el(env) != 0, 0, 0, 0, 0, is_write, | ||
60 | + 0x11); | ||
61 | + raise_exception_ra(env, EXCP_DATA_ABORT, syn, exception_target_el(env), ra); | ||
62 | + g_assert_not_reached(); | ||
63 | +} | ||
64 | + | ||
65 | +static void mte_async_check_fail(CPUARMState *env, uint64_t dirty_ptr, | ||
66 | + uintptr_t ra, ARMMMUIdx arm_mmu_idx, int el) | ||
67 | +{ | ||
68 | + int select; | ||
69 | + | ||
70 | + if (regime_has_2_ranges(arm_mmu_idx)) { | ||
71 | + select = extract64(dirty_ptr, 55, 1); | ||
72 | + } else { | ||
73 | + select = 0; | ||
74 | + } | ||
75 | + env->cp15.tfsr_el[el] |= 1 << select; | ||
76 | +#ifdef CONFIG_USER_ONLY | ||
77 | + /* | ||
78 | + * Stand in for a timer irq, setting _TIF_MTE_ASYNC_FAULT, | ||
79 | + * which then sends a SIGSEGV when the thread is next scheduled. | ||
80 | + * This cpu will return to the main loop at the end of the TB, | ||
81 | + * which is rather sooner than "normal". But the alternative | ||
82 | + * is waiting until the next syscall. | ||
83 | + */ | ||
84 | + qemu_cpu_kick(env_cpu(env)); | ||
85 | +#endif | ||
86 | +} | ||
87 | + | ||
88 | /* Record a tag check failure. */ | ||
89 | static void mte_check_fail(CPUARMState *env, uint32_t desc, | ||
90 | uint64_t dirty_ptr, uintptr_t ra) | ||
74 | { | 91 | { |
75 | - SMMUNotifierNode *node; | 92 | int mmu_idx = FIELD_EX32(desc, MTEDESC, MIDX); |
76 | + SMMUDevice *sdev; | 93 | ARMMMUIdx arm_mmu_idx = core_to_aa64_mmu_idx(mmu_idx); |
77 | 94 | - int el, reg_el, tcf, select, is_write, syn; | |
78 | - QLIST_FOREACH(node, &s->notifiers_list, next) { | 95 | + int el, reg_el, tcf; |
79 | - IOMMUMemoryRegion *mr = &node->sdev->iommu; | 96 | uint64_t sctlr; |
80 | + QLIST_FOREACH(sdev, &s->devices_with_notifiers, next) { | 97 | |
81 | + IOMMUMemoryRegion *mr = &sdev->iommu; | 98 | reg_el = regime_el(env, arm_mmu_idx); |
82 | IOMMUNotifier *n; | 99 | @@ -XXX,XX +XXX,XX @@ static void mte_check_fail(CPUARMState *env, uint32_t desc, |
83 | 100 | switch (tcf) { | |
84 | trace_smmuv3_inv_notifiers_iova(mr->parent_obj.name, asid, iova); | 101 | case 1: |
85 | @@ -XXX,XX +XXX,XX @@ static void smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, | 102 | /* Tag check fail causes a synchronous exception. */ |
86 | SMMUDevice *sdev = container_of(iommu, SMMUDevice, iommu); | 103 | - env->exception.vaddress = dirty_ptr; |
87 | SMMUv3State *s3 = sdev->smmu; | ||
88 | SMMUState *s = &(s3->smmu_state); | ||
89 | - SMMUNotifierNode *node = NULL; | ||
90 | - SMMUNotifierNode *next_node = NULL; | ||
91 | |||
92 | if (new & IOMMU_NOTIFIER_MAP) { | ||
93 | int bus_num = pci_bus_num(sdev->bus); | ||
94 | @@ -XXX,XX +XXX,XX @@ static void smmuv3_notify_flag_changed(IOMMUMemoryRegion *iommu, | ||
95 | |||
96 | if (old == IOMMU_NOTIFIER_NONE) { | ||
97 | trace_smmuv3_notify_flag_add(iommu->parent_obj.name); | ||
98 | - node = g_malloc0(sizeof(*node)); | ||
99 | - node->sdev = sdev; | ||
100 | - QLIST_INSERT_HEAD(&s->notifiers_list, node, next); | ||
101 | - return; | ||
102 | - } | ||
103 | - | 104 | - |
104 | - /* update notifier node with new flags */ | 105 | - is_write = FIELD_EX32(desc, MTEDESC, WRITE); |
105 | - QLIST_FOREACH_SAFE(node, &s->notifiers_list, next, next_node) { | 106 | - syn = syn_data_abort_no_iss(arm_current_el(env) != 0, 0, 0, 0, 0, |
106 | - if (node->sdev == sdev) { | 107 | - is_write, 0x11); |
107 | - if (new == IOMMU_NOTIFIER_NONE) { | 108 | - raise_exception_ra(env, EXCP_DATA_ABORT, syn, |
108 | - trace_smmuv3_notify_flag_del(iommu->parent_obj.name); | 109 | - exception_target_el(env), ra); |
109 | - QLIST_REMOVE(node, next); | 110 | - /* noreturn, but fall through to the assert anyway */ |
110 | - g_free(node); | 111 | + mte_sync_check_fail(env, desc, dirty_ptr, ra); |
111 | - } | 112 | + break; |
112 | - return; | 113 | |
114 | case 0: | ||
115 | /* | ||
116 | @@ -XXX,XX +XXX,XX @@ static void mte_check_fail(CPUARMState *env, uint32_t desc, | ||
117 | |||
118 | case 2: | ||
119 | /* Tag check fail causes asynchronous flag set. */ | ||
120 | - if (regime_has_2_ranges(arm_mmu_idx)) { | ||
121 | - select = extract64(dirty_ptr, 55, 1); | ||
122 | - } else { | ||
123 | - select = 0; | ||
113 | - } | 124 | - } |
114 | + QLIST_INSERT_HEAD(&s->devices_with_notifiers, sdev, next); | 125 | - env->cp15.tfsr_el[el] |= 1 << select; |
115 | + } else if (new == IOMMU_NOTIFIER_NONE) { | 126 | -#ifdef CONFIG_USER_ONLY |
116 | + trace_smmuv3_notify_flag_del(iommu->parent_obj.name); | 127 | - /* |
117 | + QLIST_REMOVE(sdev, next); | 128 | - * Stand in for a timer irq, setting _TIF_MTE_ASYNC_FAULT, |
129 | - * which then sends a SIGSEGV when the thread is next scheduled. | ||
130 | - * This cpu will return to the main loop at the end of the TB, | ||
131 | - * which is rather sooner than "normal". But the alternative | ||
132 | - * is waiting until the next syscall. | ||
133 | - */ | ||
134 | - qemu_cpu_kick(env_cpu(env)); | ||
135 | -#endif | ||
136 | + mte_async_check_fail(env, dirty_ptr, ra, arm_mmu_idx, el); | ||
137 | break; | ||
138 | |||
139 | - default: | ||
140 | - /* Case 3: Reserved. */ | ||
141 | - qemu_log_mask(LOG_GUEST_ERROR, | ||
142 | - "Tag check failure with SCTLR_EL%d.TCF%s " | ||
143 | - "set to reserved value %d\n", | ||
144 | - reg_el, el ? "" : "0", tcf); | ||
145 | + case 3: | ||
146 | + /* | ||
147 | + * Tag check fail causes asynchronous flag set for stores, or | ||
148 | + * a synchronous exception for loads. | ||
149 | + */ | ||
150 | + if (FIELD_EX32(desc, MTEDESC, WRITE)) { | ||
151 | + mte_async_check_fail(env, dirty_ptr, ra, arm_mmu_idx, el); | ||
152 | + } else { | ||
153 | + mte_sync_check_fail(env, desc, dirty_ptr, ra); | ||
154 | + } | ||
155 | break; | ||
118 | } | 156 | } |
119 | } | 157 | } |
120 | |||
121 | -- | 158 | -- |
122 | 2.20.1 | 159 | 2.20.1 |
123 | 160 | ||
124 | 161 | diff view generated by jsdifflib |
1 | From: Philippe Mathieu-Daudé <philmd@redhat.com> | 1 | From: Alexandre Iooss <erdnaxe@crans.org> |
---|---|---|---|
2 | 2 | ||
3 | Reviewed-by: Markus Armbruster <armbru@redhat.com> | 3 | This adds the target guide for BBC Micro:bit. |
4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> | 4 | |
5 | Message-id: 20190412165416.7977-5-philmd@redhat.com | 5 | Information is taken from https://wiki.qemu.org/Features/MicroBit |
6 | and from hw/arm/nrf51_soc.c. | ||
7 | |||
8 | Signed-off-by: Alexandre Iooss <erdnaxe@crans.org> | ||
9 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | ||
10 | Reviewed-by: Joel Stanley <joel@jms.id.au> | ||
11 | Message-id: 20210621075625.540471-1-erdnaxe@crans.org | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 13 | --- |
8 | include/hw/devices.h | 6 ------ | 14 | docs/system/arm/nrf.rst | 51 ++++++++++++++++++++++++++++++++++++++ |
9 | include/hw/display/tc6393xb.h | 24 ++++++++++++++++++++++++ | 15 | docs/system/target-arm.rst | 1 + |
10 | hw/arm/tosa.c | 2 +- | 16 | MAINTAINERS | 1 + |
11 | hw/display/tc6393xb.c | 2 +- | 17 | 3 files changed, 53 insertions(+) |
12 | MAINTAINERS | 1 + | 18 | create mode 100644 docs/system/arm/nrf.rst |
13 | 5 files changed, 27 insertions(+), 8 deletions(-) | ||
14 | create mode 100644 include/hw/display/tc6393xb.h | ||
15 | 19 | ||
16 | diff --git a/include/hw/devices.h b/include/hw/devices.h | 20 | diff --git a/docs/system/arm/nrf.rst b/docs/system/arm/nrf.rst |
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/include/hw/devices.h | ||
19 | +++ b/include/hw/devices.h | ||
20 | @@ -XXX,XX +XXX,XX @@ void *tahvo_init(qemu_irq irq, int betty); | ||
21 | |||
22 | void retu_key_event(void *retu, int state); | ||
23 | |||
24 | -/* tc6393xb.c */ | ||
25 | -typedef struct TC6393xbState TC6393xbState; | ||
26 | -TC6393xbState *tc6393xb_init(struct MemoryRegion *sysmem, | ||
27 | - uint32_t base, qemu_irq irq); | ||
28 | -qemu_irq tc6393xb_l3v_get(TC6393xbState *s); | ||
29 | - | ||
30 | #endif | ||
31 | diff --git a/include/hw/display/tc6393xb.h b/include/hw/display/tc6393xb.h | ||
32 | new file mode 100644 | 21 | new file mode 100644 |
33 | index XXXXXXX..XXXXXXX | 22 | index XXXXXXX..XXXXXXX |
34 | --- /dev/null | 23 | --- /dev/null |
35 | +++ b/include/hw/display/tc6393xb.h | 24 | +++ b/docs/system/arm/nrf.rst |
36 | @@ -XXX,XX +XXX,XX @@ | 25 | @@ -XXX,XX +XXX,XX @@ |
37 | +/* | 26 | +Nordic nRF boards (``microbit``) |
38 | + * Toshiba TC6393XB I/O Controller. | 27 | +================================ |
39 | + * Found in Sharp Zaurus SL-6000 (tosa) or some | ||
40 | + * Toshiba e-Series PDAs. | ||
41 | + * | ||
42 | + * Copyright (c) 2007 Hervé Poussineau | ||
43 | + * | ||
44 | + * This work is licensed under the terms of the GNU GPL, version 2 or later. | ||
45 | + * See the COPYING file in the top-level directory. | ||
46 | + */ | ||
47 | + | 28 | + |
48 | +#ifndef HW_DISPLAY_TC6393XB_H | 29 | +The `Nordic nRF`_ chips are a family of ARM-based System-on-Chip that |
49 | +#define HW_DISPLAY_TC6393XB_H | 30 | +are designed to be used for low-power and short-range wireless solutions. |
50 | + | 31 | + |
51 | +#include "exec/memory.h" | 32 | +.. _Nordic nRF: https://www.nordicsemi.com/Products |
52 | +#include "hw/irq.h" | ||
53 | + | 33 | + |
54 | +typedef struct TC6393xbState TC6393xbState; | 34 | +The nRF51 series is the first series for short range wireless applications. |
35 | +It is superseded by the nRF52 series. | ||
36 | +The following machines are based on this chip : | ||
55 | + | 37 | + |
56 | +TC6393xbState *tc6393xb_init(struct MemoryRegion *sysmem, | 38 | +- ``microbit`` BBC micro:bit board with nRF51822 SoC |
57 | + uint32_t base, qemu_irq irq); | ||
58 | +qemu_irq tc6393xb_l3v_get(TC6393xbState *s); | ||
59 | + | 39 | + |
60 | +#endif | 40 | +There are other series such as nRF52, nRF53 and nRF91 which are currently not |
61 | diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c | 41 | +supported by QEMU. |
42 | + | ||
43 | +Supported devices | ||
44 | +----------------- | ||
45 | + | ||
46 | + * ARM Cortex-M0 (ARMv6-M) | ||
47 | + * Serial ports (UART) | ||
48 | + * Clock controller | ||
49 | + * Timers | ||
50 | + * Random Number Generator (RNG) | ||
51 | + * GPIO controller | ||
52 | + * NVMC | ||
53 | + * SWI | ||
54 | + | ||
55 | +Missing devices | ||
56 | +--------------- | ||
57 | + | ||
58 | + * Watchdog | ||
59 | + * Real-Time Clock (RTC) controller | ||
60 | + * TWI (i2c) | ||
61 | + * SPI controller | ||
62 | + * Analog to Digital Converter (ADC) | ||
63 | + * Quadrature decoder | ||
64 | + * Radio | ||
65 | + | ||
66 | +Boot options | ||
67 | +------------ | ||
68 | + | ||
69 | +The Micro:bit machine can be started using the ``-device`` option to load a | ||
70 | +firmware in `ihex format`_. Example: | ||
71 | + | ||
72 | +.. _ihex format: https://en.wikipedia.org/wiki/Intel_HEX | ||
73 | + | ||
74 | +.. code-block:: bash | ||
75 | + | ||
76 | + $ qemu-system-arm -M microbit -device loader,file=test.hex | ||
77 | diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst | ||
62 | index XXXXXXX..XXXXXXX 100644 | 78 | index XXXXXXX..XXXXXXX 100644 |
63 | --- a/hw/arm/tosa.c | 79 | --- a/docs/system/target-arm.rst |
64 | +++ b/hw/arm/tosa.c | 80 | +++ b/docs/system/target-arm.rst |
65 | @@ -XXX,XX +XXX,XX @@ | 81 | @@ -XXX,XX +XXX,XX @@ undocumented; you can get a complete list by running |
66 | #include "hw/hw.h" | 82 | arm/digic |
67 | #include "hw/arm/pxa.h" | 83 | arm/musicpal |
68 | #include "hw/arm/arm.h" | 84 | arm/gumstix |
69 | -#include "hw/devices.h" | 85 | + arm/nrf |
70 | #include "hw/arm/sharpsl.h" | 86 | arm/nseries |
71 | #include "hw/pcmcia.h" | 87 | arm/nuvoton |
72 | #include "hw/boards.h" | 88 | arm/orangepi |
73 | +#include "hw/display/tc6393xb.h" | ||
74 | #include "hw/i2c/i2c.h" | ||
75 | #include "hw/ssi/ssi.h" | ||
76 | #include "hw/sysbus.h" | ||
77 | diff --git a/hw/display/tc6393xb.c b/hw/display/tc6393xb.c | ||
78 | index XXXXXXX..XXXXXXX 100644 | ||
79 | --- a/hw/display/tc6393xb.c | ||
80 | +++ b/hw/display/tc6393xb.c | ||
81 | @@ -XXX,XX +XXX,XX @@ | ||
82 | #include "qapi/error.h" | ||
83 | #include "qemu/host-utils.h" | ||
84 | #include "hw/hw.h" | ||
85 | -#include "hw/devices.h" | ||
86 | +#include "hw/display/tc6393xb.h" | ||
87 | #include "hw/block/flash.h" | ||
88 | #include "ui/console.h" | ||
89 | #include "ui/pixel_ops.h" | ||
90 | diff --git a/MAINTAINERS b/MAINTAINERS | 89 | diff --git a/MAINTAINERS b/MAINTAINERS |
91 | index XXXXXXX..XXXXXXX 100644 | 90 | index XXXXXXX..XXXXXXX 100644 |
92 | --- a/MAINTAINERS | 91 | --- a/MAINTAINERS |
93 | +++ b/MAINTAINERS | 92 | +++ b/MAINTAINERS |
94 | @@ -XXX,XX +XXX,XX @@ F: hw/misc/mst_fpga.c | 93 | @@ -XXX,XX +XXX,XX @@ F: hw/*/microbit*.c |
95 | F: hw/misc/max111x.c | 94 | F: include/hw/*/nrf51*.h |
96 | F: include/hw/arm/pxa.h | 95 | F: include/hw/*/microbit*.h |
97 | F: include/hw/arm/sharpsl.h | 96 | F: tests/qtest/microbit-test.c |
98 | +F: include/hw/display/tc6393xb.h | 97 | +F: docs/system/arm/nrf.rst |
99 | 98 | ||
100 | SABRELITE / i.MX6 | 99 | AVR Machines |
101 | M: Peter Maydell <peter.maydell@linaro.org> | 100 | ------------- |
102 | -- | 101 | -- |
103 | 2.20.1 | 102 | 2.20.1 |
104 | 103 | ||
105 | 104 | diff view generated by jsdifflib |