[Qemu-devel] [PULL 00/15] tcg patch queue
[PULL 00/20] tcg patch queue
1
The following changes since commit 3284aa128153750f14a61e8a96fd085e6f2999b6:
1
TCG patch queue, plus one target/sh4 patch that
2
Yoshinori Sato asked me to process.
2
3
3
Merge remote-tracking branch 'remotes/lersek/tags/edk2-pull-2019-04-22' into staging (2019-04-24 13:19:41 +0100)
4
5
r~
6
7
8
The following changes since commit efbf38d73e5dcc4d5f8b98c6e7a12be1f3b91745:
9
10
Merge tag 'for-upstream' of git://repo.or.cz/qemu/kevin into staging (2022-10-03 15:06:07 -0400)
4
11
5
are available in the Git repository at:
12
are available in the Git repository at:
6
13
7
https://github.com/rth7680/qemu.git tags/pull-tcg-20190426
14
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20221004
8
15
9
for you to fetch changes up to ef5dae6805cce7b59d129d801bdc5db71bcbd60d:
16
for you to fetch changes up to ab419fd8a035a65942de4e63effcd55ccbf1a9fe:
10
17
11
cputlb: Fix io_readx() to respect the access_type (2019-04-25 10:40:06 -0700)
18
target/sh4: Fix TB_FLAG_UNALIGN (2022-10-04 12:33:05 -0700)
12
19
13
----------------------------------------------------------------
20
----------------------------------------------------------------
14
Add tcg_gen_extract2_*.
21
Cache CPUClass for use in hot code paths.
15
Deal with overflow of TranslationBlocks.
22
Add CPUTLBEntryFull, probe_access_full, tlb_set_page_full.
16
Respect access_type in io_readx.
23
Add generic support for TARGET_TB_PCREL.
24
tcg/ppc: Optimize 26-bit jumps using STQ for POWER 2.07
25
target/sh4: Fix TB_FLAG_UNALIGN
17
26
18
----------------------------------------------------------------
27
----------------------------------------------------------------
19
David Hildenbrand (1):
28
Alex Bennée (3):
20
tcg: Implement tcg_gen_extract2_{i32,i64}
29
cpu: cache CPUClass in CPUState for hot code paths
30
hw/core/cpu-sysemu: used cached class in cpu_asidx_from_attrs
31
cputlb: used cached CPUClass in our hot-paths
21
32
22
Richard Henderson (13):
33
Leandro Lupori (1):
23
tcg: Add INDEX_op_extract2_{i32,i64}
34
tcg/ppc: Optimize 26-bit jumps
24
tcg: Use deposit and extract2 in tcg_gen_shifti_i64
25
tcg: Use extract2 in tcg_gen_deposit_{i32,i64}
26
tcg/i386: Support INDEX_op_extract2_{i32,i64}
27
tcg/arm: Support INDEX_op_extract2_i32
28
tcg/aarch64: Support INDEX_op_extract2_{i32,i64}
29
tcg: Hoist max_insns computation to tb_gen_code
30
tcg: Restart after TB code generation overflow
31
tcg: Restart TB generation after relocation overflow
32
tcg: Restart TB generation after constant pool overflow
33
tcg: Restart TB generation after out-of-line ldst overflow
34
tcg/ppc: Allow the constant pool to overflow at 32k
35
tcg/arm: Restrict constant pool displacement to 12 bits
36
35
37
Shahab Vahedi (1):
36
Richard Henderson (16):
38
cputlb: Fix io_readx() to respect the access_type
37
accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull
38
accel/tcg: Drop addr member from SavedIOTLB
39
accel/tcg: Suppress auto-invalidate in probe_access_internal
40
accel/tcg: Introduce probe_access_full
41
accel/tcg: Introduce tlb_set_page_full
42
include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA
43
accel/tcg: Remove PageDesc code_bitmap
44
accel/tcg: Use bool for page_find_alloc
45
accel/tcg: Use DisasContextBase in plugin_gen_tb_start
46
accel/tcg: Do not align tb->page_addr[0]
47
accel/tcg: Inline tb_flush_jmp_cache
48
include/hw/core: Create struct CPUJumpCache
49
hw/core: Add CPUClass.get_pc
50
accel/tcg: Introduce tb_pc and log_pc
51
accel/tcg: Introduce TARGET_TB_PCREL
52
target/sh4: Fix TB_FLAG_UNALIGN
39
53
40
include/exec/exec-all.h | 4 +-
54
accel/tcg/internal.h | 10 ++
41
include/exec/translator.h | 3 +-
55
accel/tcg/tb-hash.h | 1 +
42
tcg/aarch64/tcg-target.h | 2 +
56
accel/tcg/tb-jmp-cache.h | 65 ++++++++
43
tcg/arm/tcg-target.h | 1 +
57
include/exec/cpu-common.h | 1 +
44
tcg/i386/tcg-target.h | 2 +
58
include/exec/cpu-defs.h | 48 ++++--
45
tcg/mips/tcg-target.h | 2 +
59
include/exec/exec-all.h | 75 ++++++++-
46
tcg/ppc/tcg-target.h | 2 +
60
include/exec/plugin-gen.h | 7 +-
47
tcg/riscv/tcg-target.h | 2 +
61
include/hw/core/cpu.h | 28 ++--
48
tcg/s390/tcg-target.h | 2 +
62
include/qemu/typedefs.h | 2 +
49
tcg/sparc/tcg-target.h | 2 +
63
include/tcg/tcg.h | 2 +-
50
tcg/tcg-op.h | 6 ++
64
target/sh4/cpu.h | 56 ++++---
51
tcg/tcg-opc.h | 2 +
65
accel/stubs/tcg-stub.c | 4 +
52
tcg/tcg.h | 16 +++---
66
accel/tcg/cpu-exec.c | 80 +++++-----
53
tcg/tci/tcg-target.h | 2 +
67
accel/tcg/cputlb.c | 259 ++++++++++++++++++--------------
54
accel/tcg/cputlb.c | 5 +-
68
accel/tcg/plugin-gen.c | 22 +--
55
accel/tcg/translate-all.c | 53 ++++++++++++++---
69
accel/tcg/translate-all.c | 214 ++++++++++++--------------
56
accel/tcg/translator.c | 15 +----
70
accel/tcg/translator.c | 2 +-
57
target/alpha/translate.c | 4 +-
71
cpu.c | 9 +-
58
target/arm/translate.c | 4 +-
72
hw/core/cpu-common.c | 3 +-
59
target/cris/translate.c | 10 +---
73
hw/core/cpu-sysemu.c | 5 +-
60
target/hppa/translate.c | 5 +-
74
linux-user/sh4/signal.c | 6 +-
61
target/i386/translate.c | 4 +-
75
plugins/core.c | 2 +-
62
target/lm32/translate.c | 10 +---
76
target/alpha/cpu.c | 9 ++
63
target/m68k/translate.c | 4 +-
77
target/arm/cpu.c | 17 ++-
64
target/microblaze/translate.c | 10 +---
78
target/arm/mte_helper.c | 14 +-
65
target/mips/translate.c | 4 +-
79
target/arm/sve_helper.c | 4 +-
66
target/moxie/translate.c | 11 +---
80
target/arm/translate-a64.c | 2 +-
67
target/nios2/translate.c | 14 +----
81
target/avr/cpu.c | 10 +-
68
target/openrisc/translate.c | 4 +-
82
target/cris/cpu.c | 8 +
69
target/ppc/translate.c | 4 +-
83
target/hexagon/cpu.c | 10 +-
70
target/riscv/translate.c | 4 +-
84
target/hppa/cpu.c | 12 +-
71
target/s390x/translate.c | 4 +-
85
target/i386/cpu.c | 9 ++
72
target/sh4/translate.c | 4 +-
86
target/i386/tcg/tcg-cpu.c | 2 +-
73
target/sparc/translate.c | 4 +-
87
target/loongarch/cpu.c | 11 +-
74
target/tilegx/translate.c | 12 +---
88
target/m68k/cpu.c | 8 +
75
target/tricore/translate.c | 16 +-----
89
target/microblaze/cpu.c | 10 +-
76
target/unicore32/translate.c | 10 +---
90
target/mips/cpu.c | 8 +
77
target/xtensa/translate.c | 4 +-
91
target/mips/tcg/exception.c | 2 +-
78
tcg/aarch64/tcg-target.inc.c | 27 +++++++--
92
target/mips/tcg/sysemu/special_helper.c | 2 +-
79
tcg/arm/tcg-target.inc.c | 98 ++++++++++++++++++--------------
93
target/nios2/cpu.c | 9 ++
80
tcg/i386/tcg-target.inc.c | 17 +++++-
94
target/openrisc/cpu.c | 10 +-
81
tcg/mips/tcg-target.inc.c | 6 +-
95
target/ppc/cpu_init.c | 8 +
82
tcg/optimize.c | 16 ++++++
96
target/riscv/cpu.c | 17 ++-
83
tcg/ppc/tcg-target.inc.c | 42 +++++++-------
97
target/rx/cpu.c | 10 +-
84
tcg/riscv/tcg-target.inc.c | 16 ++++--
98
target/s390x/cpu.c | 8 +
85
tcg/s390/tcg-target.inc.c | 20 ++++---
99
target/s390x/tcg/mem_helper.c | 4 -
86
tcg/tcg-ldst.inc.c | 18 +++---
100
target/sh4/cpu.c | 18 ++-
87
tcg/tcg-op.c | 129 +++++++++++++++++++++++++++++++++---------
101
target/sh4/helper.c | 6 +-
88
tcg/tcg-pool.inc.c | 12 ++--
102
target/sh4/translate.c | 90 +++++------
89
tcg/tcg.c | 85 +++++++++++++++-------------
103
target/sparc/cpu.c | 10 +-
90
tcg/README | 7 +++
104
target/tricore/cpu.c | 11 +-
91
51 files changed, 451 insertions(+), 309 deletions(-)
105
target/xtensa/cpu.c | 8 +
106
tcg/tcg.c | 8 +-
107
trace/control-target.c | 2 +-
108
tcg/ppc/tcg-target.c.inc | 119 +++++++++++----
109
55 files changed, 915 insertions(+), 462 deletions(-)
110
create mode 100644 accel/tcg/tb-jmp-cache.h
92
111
diff view generated by jsdifflib
New patch
[PULL 01/20] cpu: cache CPUClass in CPUState for hot code paths
1
From: Alex Bennée <alex.bennee@linaro.org>
1
2
3
The class cast checkers are quite expensive and always on (unlike the
4
dynamic case who's checks are gated by CONFIG_QOM_CAST_DEBUG). To
5
avoid the overhead of repeatedly checking something which should never
6
change we cache the CPUClass reference for use in the hot code paths.
7
8
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-Id: <20220811151413.3350684-3-alex.bennee@linaro.org>
11
Signed-off-by: Cédric Le Goater <clg@kaod.org>
12
Message-Id: <20220923084803.498337-3-clg@kaod.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
---
15
include/hw/core/cpu.h | 9 +++++++++
16
cpu.c | 9 ++++-----
17
2 files changed, 13 insertions(+), 5 deletions(-)
18
19
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/include/hw/core/cpu.h
22
+++ b/include/hw/core/cpu.h
23
@@ -XXX,XX +XXX,XX @@ typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size,
24
*/
25
#define CPU(obj) ((CPUState *)(obj))
26
27
+/*
28
+ * The class checkers bring in CPU_GET_CLASS() which is potentially
29
+ * expensive given the eventual call to
30
+ * object_class_dynamic_cast_assert(). Because of this the CPUState
31
+ * has a cached value for the class in cs->cc which is set up in
32
+ * cpu_exec_realizefn() for use in hot code paths.
33
+ */
34
typedef struct CPUClass CPUClass;
35
DECLARE_CLASS_CHECKERS(CPUClass, CPU,
36
TYPE_CPU)
37
@@ -XXX,XX +XXX,XX @@ struct qemu_work_item;
38
struct CPUState {
39
/*< private >*/
40
DeviceState parent_obj;
41
+ /* cache to avoid expensive CPU_GET_CLASS */
42
+ CPUClass *cc;
43
/*< public >*/
44
45
int nr_cores;
46
diff --git a/cpu.c b/cpu.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/cpu.c
49
+++ b/cpu.c
50
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_cpu_common = {
51
52
void cpu_exec_realizefn(CPUState *cpu, Error **errp)
53
{
54
-#ifndef CONFIG_USER_ONLY
55
- CPUClass *cc = CPU_GET_CLASS(cpu);
56
-#endif
57
+ /* cache the cpu class for the hotpath */
58
+ cpu->cc = CPU_GET_CLASS(cpu);
59
60
cpu_list_add(cpu);
61
if (!accel_cpu_realizefn(cpu, errp)) {
62
@@ -XXX,XX +XXX,XX @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp)
63
if (qdev_get_vmsd(DEVICE(cpu)) == NULL) {
64
vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu);
65
}
66
- if (cc->sysemu_ops->legacy_vmsd != NULL) {
67
- vmstate_register(NULL, cpu->cpu_index, cc->sysemu_ops->legacy_vmsd, cpu);
68
+ if (cpu->cc->sysemu_ops->legacy_vmsd != NULL) {
69
+ vmstate_register(NULL, cpu->cpu_index, cpu->cc->sysemu_ops->legacy_vmsd, cpu);
70
}
71
#endif /* CONFIG_USER_ONLY */
72
}
73
--
74
2.34.1
75
76
diff view generated by jsdifflib
New patch
[PULL 02/20] hw/core/cpu-sysemu: used cached class in cpu_asidx_from_attrs
1
From: Alex Bennée <alex.bennee@linaro.org>
1
2
3
This is a heavily used function so lets avoid the cost of
4
CPU_GET_CLASS. On the romulus-bmc run it has a modest effect:
5
6
Before: 36.812 s ± 0.506 s
7
After: 35.912 s ± 0.168 s
8
9
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-Id: <20220811151413.3350684-4-alex.bennee@linaro.org>
12
Signed-off-by: Cédric Le Goater <clg@kaod.org>
13
Message-Id: <20220923084803.498337-4-clg@kaod.org>
14
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
---
16
hw/core/cpu-sysemu.c | 5 ++---
17
1 file changed, 2 insertions(+), 3 deletions(-)
18
19
diff --git a/hw/core/cpu-sysemu.c b/hw/core/cpu-sysemu.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/core/cpu-sysemu.c
22
+++ b/hw/core/cpu-sysemu.c
23
@@ -XXX,XX +XXX,XX @@ hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr)
24
25
int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs)
26
{
27
- CPUClass *cc = CPU_GET_CLASS(cpu);
28
int ret = 0;
29
30
- if (cc->sysemu_ops->asidx_from_attrs) {
31
- ret = cc->sysemu_ops->asidx_from_attrs(cpu, attrs);
32
+ if (cpu->cc->sysemu_ops->asidx_from_attrs) {
33
+ ret = cpu->cc->sysemu_ops->asidx_from_attrs(cpu, attrs);
34
assert(ret < cpu->num_ases && ret >= 0);
35
}
36
return ret;
37
--
38
2.34.1
39
40
diff view generated by jsdifflib
New patch
[PULL 03/20] cputlb: used cached CPUClass in our hot-paths
1
From: Alex Bennée <alex.bennee@linaro.org>
1
2
3
Before: 35.912 s ± 0.168 s
4
After: 35.565 s ± 0.087 s
5
6
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-Id: <20220811151413.3350684-5-alex.bennee@linaro.org>
9
Signed-off-by: Cédric Le Goater <clg@kaod.org>
10
Message-Id: <20220923084803.498337-5-clg@kaod.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
---
13
accel/tcg/cputlb.c | 15 ++++++---------
14
1 file changed, 6 insertions(+), 9 deletions(-)
15
16
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/accel/tcg/cputlb.c
19
+++ b/accel/tcg/cputlb.c
20
@@ -XXX,XX +XXX,XX @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr,
21
static void tlb_fill(CPUState *cpu, target_ulong addr, int size,
22
MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
23
{
24
- CPUClass *cc = CPU_GET_CLASS(cpu);
25
bool ok;
26
27
/*
28
* This is not a probe, so only valid return is success; failure
29
* should result in exception + longjmp to the cpu loop.
30
*/
31
- ok = cc->tcg_ops->tlb_fill(cpu, addr, size,
32
- access_type, mmu_idx, false, retaddr);
33
+ ok = cpu->cc->tcg_ops->tlb_fill(cpu, addr, size,
34
+ access_type, mmu_idx, false, retaddr);
35
assert(ok);
36
}
37
38
@@ -XXX,XX +XXX,XX @@ static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
39
MMUAccessType access_type,
40
int mmu_idx, uintptr_t retaddr)
41
{
42
- CPUClass *cc = CPU_GET_CLASS(cpu);
43
-
44
- cc->tcg_ops->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
45
+ cpu->cc->tcg_ops->do_unaligned_access(cpu, addr, access_type,
46
+ mmu_idx, retaddr);
47
}
48
49
static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
50
@@ -XXX,XX +XXX,XX @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
51
if (!tlb_hit_page(tlb_addr, page_addr)) {
52
if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page_addr)) {
53
CPUState *cs = env_cpu(env);
54
- CPUClass *cc = CPU_GET_CLASS(cs);
55
56
- if (!cc->tcg_ops->tlb_fill(cs, addr, fault_size, access_type,
57
- mmu_idx, nonfault, retaddr)) {
58
+ if (!cs->cc->tcg_ops->tlb_fill(cs, addr, fault_size, access_type,
59
+ mmu_idx, nonfault, retaddr)) {
60
/* Non-faulting page table read failed. */
61
*phost = NULL;
62
return TLB_INVALID_MASK;
63
--
64
2.34.1
65
66
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/15] tcg: Restart TB generation after constant pool overflow
[PULL 04/20] accel/tcg: Rename CPUIOTLBEntry to CPUTLBEntryFull
1
This is part b of relocation overflow handling.
1
This structure will shortly contain more than just
2
data for accessing MMIO. Rename the 'addr' member
3
to 'xlat_section' to more clearly indicate its purpose.
2
4
5
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
9
---
5
tcg/tcg-pool.inc.c | 12 +++++++-----
10
include/exec/cpu-defs.h | 22 ++++----
6
tcg/tcg.c | 9 +++++----
11
accel/tcg/cputlb.c | 102 +++++++++++++++++++------------------
7
2 files changed, 12 insertions(+), 9 deletions(-)
12
target/arm/mte_helper.c | 14 ++---
13
target/arm/sve_helper.c | 4 +-
14
target/arm/translate-a64.c | 2 +-
15
5 files changed, 73 insertions(+), 71 deletions(-)
8
16
9
diff --git a/tcg/tcg-pool.inc.c b/tcg/tcg-pool.inc.c
17
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
10
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/tcg-pool.inc.c
19
--- a/include/exec/cpu-defs.h
12
+++ b/tcg/tcg-pool.inc.c
20
+++ b/include/exec/cpu-defs.h
13
@@ -XXX,XX +XXX,XX @@ static inline void new_pool_l8(TCGContext *s, int rtype, tcg_insn_unit *label,
21
@@ -XXX,XX +XXX,XX @@ typedef uint64_t target_ulong;
14
/* To be provided by cpu/tcg-target.inc.c. */
22
# endif
15
static void tcg_out_nop_fill(tcg_insn_unit *p, int count);
23
# endif
16
24
17
-static bool tcg_out_pool_finalize(TCGContext *s)
25
+/* Minimalized TLB entry for use by TCG fast path. */
18
+static int tcg_out_pool_finalize(TCGContext *s)
26
typedef struct CPUTLBEntry {
27
/* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address
28
bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not
29
@@ -XXX,XX +XXX,XX @@ typedef struct CPUTLBEntry {
30
31
QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS));
32
33
-/* The IOTLB is not accessed directly inline by generated TCG code,
34
- * so the CPUIOTLBEntry layout is not as critical as that of the
35
- * CPUTLBEntry. (This is also why we don't want to combine the two
36
- * structs into one.)
37
+/*
38
+ * The full TLB entry, which is not accessed by generated TCG code,
39
+ * so the layout is not as critical as that of CPUTLBEntry. This is
40
+ * also why we don't want to combine the two structs.
41
*/
42
-typedef struct CPUIOTLBEntry {
43
+typedef struct CPUTLBEntryFull {
44
/*
45
- * @addr contains:
46
+ * @xlat_section contains:
47
* - in the lower TARGET_PAGE_BITS, a physical section number
48
* - with the lower TARGET_PAGE_BITS masked off, an offset which
49
* must be added to the virtual address to obtain:
50
@@ -XXX,XX +XXX,XX @@ typedef struct CPUIOTLBEntry {
51
* number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM)
52
* + the offset within the target MemoryRegion (otherwise)
53
*/
54
- hwaddr addr;
55
+ hwaddr xlat_section;
56
MemTxAttrs attrs;
57
-} CPUIOTLBEntry;
58
+} CPUTLBEntryFull;
59
60
/*
61
* Data elements that are per MMU mode, minus the bits accessed by
62
@@ -XXX,XX +XXX,XX @@ typedef struct CPUTLBDesc {
63
size_t vindex;
64
/* The tlb victim table, in two parts. */
65
CPUTLBEntry vtable[CPU_VTLB_SIZE];
66
- CPUIOTLBEntry viotlb[CPU_VTLB_SIZE];
67
- /* The iotlb. */
68
- CPUIOTLBEntry *iotlb;
69
+ CPUTLBEntryFull vfulltlb[CPU_VTLB_SIZE];
70
+ CPUTLBEntryFull *fulltlb;
71
} CPUTLBDesc;
72
73
/*
74
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
75
index XXXXXXX..XXXXXXX 100644
76
--- a/accel/tcg/cputlb.c
77
+++ b/accel/tcg/cputlb.c
78
@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast,
79
}
80
81
g_free(fast->table);
82
- g_free(desc->iotlb);
83
+ g_free(desc->fulltlb);
84
85
tlb_window_reset(desc, now, 0);
86
/* desc->n_used_entries is cleared by the caller */
87
fast->mask = (new_size - 1) << CPU_TLB_ENTRY_BITS;
88
fast->table = g_try_new(CPUTLBEntry, new_size);
89
- desc->iotlb = g_try_new(CPUIOTLBEntry, new_size);
90
+ desc->fulltlb = g_try_new(CPUTLBEntryFull, new_size);
91
92
/*
93
* If the allocations fail, try smaller sizes. We just freed some
94
@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast,
95
* allocations to fail though, so we progressively reduce the allocation
96
* size, aborting if we cannot even allocate the smallest TLB we support.
97
*/
98
- while (fast->table == NULL || desc->iotlb == NULL) {
99
+ while (fast->table == NULL || desc->fulltlb == NULL) {
100
if (new_size == (1 << CPU_TLB_DYN_MIN_BITS)) {
101
error_report("%s: %s", __func__, strerror(errno));
102
abort();
103
@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_resize_locked(CPUTLBDesc *desc, CPUTLBDescFast *fast,
104
fast->mask = (new_size - 1) << CPU_TLB_ENTRY_BITS;
105
106
g_free(fast->table);
107
- g_free(desc->iotlb);
108
+ g_free(desc->fulltlb);
109
fast->table = g_try_new(CPUTLBEntry, new_size);
110
- desc->iotlb = g_try_new(CPUIOTLBEntry, new_size);
111
+ desc->fulltlb = g_try_new(CPUTLBEntryFull, new_size);
112
}
113
}
114
115
@@ -XXX,XX +XXX,XX @@ static void tlb_mmu_init(CPUTLBDesc *desc, CPUTLBDescFast *fast, int64_t now)
116
desc->n_used_entries = 0;
117
fast->mask = (n_entries - 1) << CPU_TLB_ENTRY_BITS;
118
fast->table = g_new(CPUTLBEntry, n_entries);
119
- desc->iotlb = g_new(CPUIOTLBEntry, n_entries);
120
+ desc->fulltlb = g_new(CPUTLBEntryFull, n_entries);
121
tlb_mmu_flush_locked(desc, fast);
122
}
123
124
@@ -XXX,XX +XXX,XX @@ void tlb_destroy(CPUState *cpu)
125
CPUTLBDescFast *fast = &env_tlb(env)->f[i];
126
127
g_free(fast->table);
128
- g_free(desc->iotlb);
129
+ g_free(desc->fulltlb);
130
}
131
}
132
133
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
134
135
/* Evict the old entry into the victim tlb. */
136
copy_tlb_helper_locked(tv, te);
137
- desc->viotlb[vidx] = desc->iotlb[index];
138
+ desc->vfulltlb[vidx] = desc->fulltlb[index];
139
tlb_n_used_entries_dec(env, mmu_idx);
140
}
141
142
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
143
* subtract here is that of the page base, and not the same as the
144
* vaddr we add back in io_readx()/io_writex()/get_page_addr_code().
145
*/
146
- desc->iotlb[index].addr = iotlb - vaddr_page;
147
- desc->iotlb[index].attrs = attrs;
148
+ desc->fulltlb[index].xlat_section = iotlb - vaddr_page;
149
+ desc->fulltlb[index].attrs = attrs;
150
151
/* Now calculate the new entry */
152
tn.addend = addend - vaddr_page;
153
@@ -XXX,XX +XXX,XX @@ static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
154
}
155
}
156
157
-static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
158
+static uint64_t io_readx(CPUArchState *env, CPUTLBEntryFull *full,
159
int mmu_idx, target_ulong addr, uintptr_t retaddr,
160
MMUAccessType access_type, MemOp op)
19
{
161
{
20
TCGLabelPoolData *p = s->pool_labels;
162
@@ -XXX,XX +XXX,XX @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
21
TCGLabelPoolData *l = NULL;
163
bool locked = false;
22
void *a;
164
MemTxResult r;
23
165
24
if (p == NULL) {
166
- section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs);
25
- return true;
167
+ section = iotlb_to_section(cpu, full->xlat_section, full->attrs);
26
+ return 0;
168
mr = section->mr;
27
}
169
- mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
28
170
+ mr_offset = (full->xlat_section & TARGET_PAGE_MASK) + addr;
29
/* ??? Round up to qemu_icache_linesize, but then do not round
171
cpu->mem_io_pc = retaddr;
30
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_pool_finalize(TCGContext *s)
172
if (!cpu->can_do_io) {
31
size_t size = sizeof(tcg_target_ulong) * p->nlong;
173
cpu_io_recompile(cpu, retaddr);
32
if (!l || l->nlong != p->nlong || memcmp(l->data, p->data, size)) {
174
@@ -XXX,XX +XXX,XX @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
33
if (unlikely(a > s->code_gen_highwater)) {
175
qemu_mutex_lock_iothread();
34
- return false;
176
locked = true;
35
+ return -1;
177
}
36
}
178
- r = memory_region_dispatch_read(mr, mr_offset, &val, op, iotlbentry->attrs);
37
memcpy(a, p->data, size);
179
+ r = memory_region_dispatch_read(mr, mr_offset, &val, op, full->attrs);
38
a += size;
180
if (r != MEMTX_OK) {
39
l = p;
181
hwaddr physaddr = mr_offset +
40
}
182
section->offset_within_address_space -
41
- patch_reloc(p->label, p->rtype, (intptr_t)a - size, p->addend);
183
section->offset_within_region;
42
+ if (!patch_reloc(p->label, p->rtype, (intptr_t)a - size, p->addend)) {
184
43
+ return -2;
185
cpu_transaction_failed(cpu, physaddr, addr, memop_size(op), access_type,
44
+ }
186
- mmu_idx, iotlbentry->attrs, r, retaddr);
45
}
187
+ mmu_idx, full->attrs, r, retaddr);
46
188
}
47
s->code_ptr = a;
189
if (locked) {
48
- return true;
190
qemu_mutex_unlock_iothread();
49
+ return 0;
191
@@ -XXX,XX +XXX,XX @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
50
}
192
}
51
diff --git a/tcg/tcg.c b/tcg/tcg.c
193
194
/*
195
- * Save a potentially trashed IOTLB entry for later lookup by plugin.
196
- * This is read by tlb_plugin_lookup if the iotlb entry doesn't match
197
+ * Save a potentially trashed CPUTLBEntryFull for later lookup by plugin.
198
+ * This is read by tlb_plugin_lookup if the fulltlb entry doesn't match
199
* because of the side effect of io_writex changing memory layout.
200
*/
201
static void save_iotlb_data(CPUState *cs, hwaddr addr,
202
@@ -XXX,XX +XXX,XX @@ static void save_iotlb_data(CPUState *cs, hwaddr addr,
203
#endif
204
}
205
206
-static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
207
+static void io_writex(CPUArchState *env, CPUTLBEntryFull *full,
208
int mmu_idx, uint64_t val, target_ulong addr,
209
uintptr_t retaddr, MemOp op)
210
{
211
@@ -XXX,XX +XXX,XX @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
212
bool locked = false;
213
MemTxResult r;
214
215
- section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs);
216
+ section = iotlb_to_section(cpu, full->xlat_section, full->attrs);
217
mr = section->mr;
218
- mr_offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
219
+ mr_offset = (full->xlat_section & TARGET_PAGE_MASK) + addr;
220
if (!cpu->can_do_io) {
221
cpu_io_recompile(cpu, retaddr);
222
}
223
@@ -XXX,XX +XXX,XX @@ static void io_writex(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
224
* The memory_region_dispatch may trigger a flush/resize
225
* so for plugins we save the iotlb_data just in case.
226
*/
227
- save_iotlb_data(cpu, iotlbentry->addr, section, mr_offset);
228
+ save_iotlb_data(cpu, full->xlat_section, section, mr_offset);
229
230
if (!qemu_mutex_iothread_locked()) {
231
qemu_mutex_lock_iothread();
232
locked = true;
233
}
234
- r = memory_region_dispatch_write(mr, mr_offset, val, op, iotlbentry->attrs);
235
+ r = memory_region_dispatch_write(mr, mr_offset, val, op, full->attrs);
236
if (r != MEMTX_OK) {
237
hwaddr physaddr = mr_offset +
238
section->offset_within_address_space -
239
section->offset_within_region;
240
241
cpu_transaction_failed(cpu, physaddr, addr, memop_size(op),
242
- MMU_DATA_STORE, mmu_idx, iotlbentry->attrs, r,
243
+ MMU_DATA_STORE, mmu_idx, full->attrs, r,
244
retaddr);
245
}
246
if (locked) {
247
@@ -XXX,XX +XXX,XX @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index,
248
copy_tlb_helper_locked(vtlb, &tmptlb);
249
qemu_spin_unlock(&env_tlb(env)->c.lock);
250
251
- CPUIOTLBEntry tmpio, *io = &env_tlb(env)->d[mmu_idx].iotlb[index];
252
- CPUIOTLBEntry *vio = &env_tlb(env)->d[mmu_idx].viotlb[vidx];
253
- tmpio = *io; *io = *vio; *vio = tmpio;
254
+ CPUTLBEntryFull *f1 = &env_tlb(env)->d[mmu_idx].fulltlb[index];
255
+ CPUTLBEntryFull *f2 = &env_tlb(env)->d[mmu_idx].vfulltlb[vidx];
256
+ CPUTLBEntryFull tmpf;
257
+ tmpf = *f1; *f1 = *f2; *f2 = tmpf;
258
return true;
259
}
260
}
261
@@ -XXX,XX +XXX,XX @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index,
262
(ADDR) & TARGET_PAGE_MASK)
263
264
static void notdirty_write(CPUState *cpu, vaddr mem_vaddr, unsigned size,
265
- CPUIOTLBEntry *iotlbentry, uintptr_t retaddr)
266
+ CPUTLBEntryFull *full, uintptr_t retaddr)
267
{
268
- ram_addr_t ram_addr = mem_vaddr + iotlbentry->addr;
269
+ ram_addr_t ram_addr = mem_vaddr + full->xlat_section;
270
271
trace_memory_notdirty_write_access(mem_vaddr, ram_addr, size);
272
273
@@ -XXX,XX +XXX,XX @@ int probe_access_flags(CPUArchState *env, target_ulong addr,
274
/* Handle clean RAM pages. */
275
if (unlikely(flags & TLB_NOTDIRTY)) {
276
uintptr_t index = tlb_index(env, mmu_idx, addr);
277
- CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
278
+ CPUTLBEntryFull *full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
279
280
- notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr);
281
+ notdirty_write(env_cpu(env), addr, 1, full, retaddr);
282
flags &= ~TLB_NOTDIRTY;
283
}
284
285
@@ -XXX,XX +XXX,XX @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
286
287
if (unlikely(flags & (TLB_NOTDIRTY | TLB_WATCHPOINT))) {
288
uintptr_t index = tlb_index(env, mmu_idx, addr);
289
- CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
290
+ CPUTLBEntryFull *full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
291
292
/* Handle watchpoints. */
293
if (flags & TLB_WATCHPOINT) {
294
int wp_access = (access_type == MMU_DATA_STORE
295
? BP_MEM_WRITE : BP_MEM_READ);
296
cpu_check_watchpoint(env_cpu(env), addr, size,
297
- iotlbentry->attrs, wp_access, retaddr);
298
+ full->attrs, wp_access, retaddr);
299
}
300
301
/* Handle clean RAM pages. */
302
if (flags & TLB_NOTDIRTY) {
303
- notdirty_write(env_cpu(env), addr, 1, iotlbentry, retaddr);
304
+ notdirty_write(env_cpu(env), addr, 1, full, retaddr);
305
}
306
}
307
308
@@ -XXX,XX +XXX,XX @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr,
309
* should have just filled the TLB. The one corner case is io_writex
310
* which can cause TLB flushes and potential resizing of the TLBs
311
* losing the information we need. In those cases we need to recover
312
- * data from a copy of the iotlbentry. As long as this always occurs
313
+ * data from a copy of the CPUTLBEntryFull. As long as this always occurs
314
* from the same thread (which a mem callback will be) this is safe.
315
*/
316
317
@@ -XXX,XX +XXX,XX @@ bool tlb_plugin_lookup(CPUState *cpu, target_ulong addr, int mmu_idx,
318
if (likely(tlb_hit(tlb_addr, addr))) {
319
/* We must have an iotlb entry for MMIO */
320
if (tlb_addr & TLB_MMIO) {
321
- CPUIOTLBEntry *iotlbentry;
322
- iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
323
+ CPUTLBEntryFull *full;
324
+ full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
325
data->is_io = true;
326
- data->v.io.section = iotlb_to_section(cpu, iotlbentry->addr, iotlbentry->attrs);
327
- data->v.io.offset = (iotlbentry->addr & TARGET_PAGE_MASK) + addr;
328
+ data->v.io.section =
329
+ iotlb_to_section(cpu, full->xlat_section, full->attrs);
330
+ data->v.io.offset = (full->xlat_section & TARGET_PAGE_MASK) + addr;
331
} else {
332
data->is_io = false;
333
data->v.ram.hostaddr = (void *)((uintptr_t)addr + tlbe->addend);
334
@@ -XXX,XX +XXX,XX @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
335
336
if (unlikely(tlb_addr & TLB_NOTDIRTY)) {
337
notdirty_write(env_cpu(env), addr, size,
338
- &env_tlb(env)->d[mmu_idx].iotlb[index], retaddr);
339
+ &env_tlb(env)->d[mmu_idx].fulltlb[index], retaddr);
340
}
341
342
return hostaddr;
343
@@ -XXX,XX +XXX,XX @@ load_helper(CPUArchState *env, target_ulong addr, MemOpIdx oi,
344
345
/* Handle anything that isn't just a straight memory access. */
346
if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
347
- CPUIOTLBEntry *iotlbentry;
348
+ CPUTLBEntryFull *full;
349
bool need_swap;
350
351
/* For anything that is unaligned, recurse through full_load. */
352
@@ -XXX,XX +XXX,XX @@ load_helper(CPUArchState *env, target_ulong addr, MemOpIdx oi,
353
goto do_unaligned_access;
354
}
355
356
- iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
357
+ full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
358
359
/* Handle watchpoints. */
360
if (unlikely(tlb_addr & TLB_WATCHPOINT)) {
361
/* On watchpoint hit, this will longjmp out. */
362
cpu_check_watchpoint(env_cpu(env), addr, size,
363
- iotlbentry->attrs, BP_MEM_READ, retaddr);
364
+ full->attrs, BP_MEM_READ, retaddr);
365
}
366
367
need_swap = size > 1 && (tlb_addr & TLB_BSWAP);
368
369
/* Handle I/O access. */
370
if (likely(tlb_addr & TLB_MMIO)) {
371
- return io_readx(env, iotlbentry, mmu_idx, addr, retaddr,
372
+ return io_readx(env, full, mmu_idx, addr, retaddr,
373
access_type, op ^ (need_swap * MO_BSWAP));
374
}
375
376
@@ -XXX,XX +XXX,XX @@ store_helper_unaligned(CPUArchState *env, target_ulong addr, uint64_t val,
377
*/
378
if (unlikely(tlb_addr & TLB_WATCHPOINT)) {
379
cpu_check_watchpoint(env_cpu(env), addr, size - size2,
380
- env_tlb(env)->d[mmu_idx].iotlb[index].attrs,
381
+ env_tlb(env)->d[mmu_idx].fulltlb[index].attrs,
382
BP_MEM_WRITE, retaddr);
383
}
384
if (unlikely(tlb_addr2 & TLB_WATCHPOINT)) {
385
cpu_check_watchpoint(env_cpu(env), page2, size2,
386
- env_tlb(env)->d[mmu_idx].iotlb[index2].attrs,
387
+ env_tlb(env)->d[mmu_idx].fulltlb[index2].attrs,
388
BP_MEM_WRITE, retaddr);
389
}
390
391
@@ -XXX,XX +XXX,XX @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
392
393
/* Handle anything that isn't just a straight memory access. */
394
if (unlikely(tlb_addr & ~TARGET_PAGE_MASK)) {
395
- CPUIOTLBEntry *iotlbentry;
396
+ CPUTLBEntryFull *full;
397
bool need_swap;
398
399
/* For anything that is unaligned, recurse through byte stores. */
400
@@ -XXX,XX +XXX,XX @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
401
goto do_unaligned_access;
402
}
403
404
- iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
405
+ full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
406
407
/* Handle watchpoints. */
408
if (unlikely(tlb_addr & TLB_WATCHPOINT)) {
409
/* On watchpoint hit, this will longjmp out. */
410
cpu_check_watchpoint(env_cpu(env), addr, size,
411
- iotlbentry->attrs, BP_MEM_WRITE, retaddr);
412
+ full->attrs, BP_MEM_WRITE, retaddr);
413
}
414
415
need_swap = size > 1 && (tlb_addr & TLB_BSWAP);
416
417
/* Handle I/O access. */
418
if (tlb_addr & TLB_MMIO) {
419
- io_writex(env, iotlbentry, mmu_idx, val, addr, retaddr,
420
+ io_writex(env, full, mmu_idx, val, addr, retaddr,
421
op ^ (need_swap * MO_BSWAP));
422
return;
423
}
424
@@ -XXX,XX +XXX,XX @@ store_helper(CPUArchState *env, target_ulong addr, uint64_t val,
425
426
/* Handle clean RAM pages. */
427
if (tlb_addr & TLB_NOTDIRTY) {
428
- notdirty_write(env_cpu(env), addr, size, iotlbentry, retaddr);
429
+ notdirty_write(env_cpu(env), addr, size, full, retaddr);
430
}
431
432
haddr = (void *)((uintptr_t)addr + entry->addend);
433
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
52
index XXXXXXX..XXXXXXX 100644
434
index XXXXXXX..XXXXXXX 100644
53
--- a/tcg/tcg.c
435
--- a/target/arm/mte_helper.c
54
+++ b/tcg/tcg.c
436
+++ b/target/arm/mte_helper.c
55
@@ -XXX,XX +XXX,XX @@ void tcg_prologue_init(TCGContext *s)
437
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
56
#ifdef TCG_TARGET_NEED_POOL_LABELS
438
return tags + index;
57
/* Allow the prologue to put e.g. guest_base into a pool entry. */
439
#else
58
{
440
uintptr_t index;
59
- bool ok = tcg_out_pool_finalize(s);
441
- CPUIOTLBEntry *iotlbentry;
60
- tcg_debug_assert(ok);
442
+ CPUTLBEntryFull *full;
61
+ int result = tcg_out_pool_finalize(s);
443
int in_page, flags;
62
+ tcg_debug_assert(result == 0);
444
ram_addr_t ptr_ra;
445
hwaddr ptr_paddr, tag_paddr, xlat;
446
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
447
assert(!(flags & TLB_INVALID_MASK));
448
449
/*
450
- * Find the iotlbentry for ptr. This *must* be present in the TLB
451
+ * Find the CPUTLBEntryFull for ptr. This *must* be present in the TLB
452
* because we just found the mapping.
453
* TODO: Perhaps there should be a cputlb helper that returns a
454
* matching tlb entry + iotlb entry.
455
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
456
g_assert(tlb_hit(comparator, ptr));
457
}
458
# endif
459
- iotlbentry = &env_tlb(env)->d[ptr_mmu_idx].iotlb[index];
460
+ full = &env_tlb(env)->d[ptr_mmu_idx].fulltlb[index];
461
462
/* If the virtual page MemAttr != Tagged, access unchecked. */
463
- if (!arm_tlb_mte_tagged(&iotlbentry->attrs)) {
464
+ if (!arm_tlb_mte_tagged(&full->attrs)) {
465
return NULL;
466
}
467
468
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
469
int wp = ptr_access == MMU_DATA_LOAD ? BP_MEM_READ : BP_MEM_WRITE;
470
assert(ra != 0);
471
cpu_check_watchpoint(env_cpu(env), ptr, ptr_size,
472
- iotlbentry->attrs, wp, ra);
473
+ full->attrs, wp, ra);
474
}
475
476
/*
477
@@ -XXX,XX +XXX,XX @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
478
tag_paddr = ptr_paddr >> (LOG2_TAG_GRANULE + 1);
479
480
/* Look up the address in tag space. */
481
- tag_asi = iotlbentry->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS;
482
+ tag_asi = full->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS;
483
tag_as = cpu_get_address_space(env_cpu(env), tag_asi);
484
mr = address_space_translate(tag_as, tag_paddr, &xlat, NULL,
485
tag_access == MMU_DATA_STORE,
486
- iotlbentry->attrs);
487
+ full->attrs);
488
489
/*
490
* Note that @mr will never be NULL. If there is nothing in the address
491
diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c
492
index XXXXXXX..XXXXXXX 100644
493
--- a/target/arm/sve_helper.c
494
+++ b/target/arm/sve_helper.c
495
@@ -XXX,XX +XXX,XX @@ bool sve_probe_page(SVEHostPage *info, bool nofault, CPUARMState *env,
496
g_assert(tlb_hit(comparator, addr));
497
# endif
498
499
- CPUIOTLBEntry *iotlbentry = &env_tlb(env)->d[mmu_idx].iotlb[index];
500
- info->attrs = iotlbentry->attrs;
501
+ CPUTLBEntryFull *full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
502
+ info->attrs = full->attrs;
63
}
503
}
64
#endif
504
#endif
65
505
66
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
506
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
67
}
507
index XXXXXXX..XXXXXXX 100644
508
--- a/target/arm/translate-a64.c
509
+++ b/target/arm/translate-a64.c
510
@@ -XXX,XX +XXX,XX @@ static bool is_guarded_page(CPUARMState *env, DisasContext *s)
511
* table entry even for that case.
512
*/
513
return (tlb_hit(entry->addr_code, addr) &&
514
- arm_tlb_bti_gp(&env_tlb(env)->d[mmu_idx].iotlb[index].attrs));
515
+ arm_tlb_bti_gp(&env_tlb(env)->d[mmu_idx].fulltlb[index].attrs));
68
#endif
516
#endif
69
#ifdef TCG_TARGET_NEED_POOL_LABELS
517
}
70
- if (!tcg_out_pool_finalize(s)) {
518
71
- return -1;
72
+ i = tcg_out_pool_finalize(s);
73
+ if (i < 0) {
74
+ return i;
75
}
76
#endif
77
if (!tcg_resolve_relocs(s)) {
78
--
519
--
79
2.17.1
520
2.34.1
80
521
81
522
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/15] tcg/aarch64: Support INDEX_op_extract2_{i32, i64}
[PULL 05/20] accel/tcg: Drop addr member from SavedIOTLB
1
This field is only written, not read; remove it.
2
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
1
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
7
---
4
tcg/aarch64/tcg-target.h | 4 ++--
8
include/hw/core/cpu.h | 1 -
5
tcg/aarch64/tcg-target.inc.c | 11 +++++++++++
9
accel/tcg/cputlb.c | 7 +++----
6
2 files changed, 13 insertions(+), 2 deletions(-)
10
2 files changed, 3 insertions(+), 5 deletions(-)
7
11
8
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
12
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
9
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
10
--- a/tcg/aarch64/tcg-target.h
14
--- a/include/hw/core/cpu.h
11
+++ b/tcg/aarch64/tcg-target.h
15
+++ b/include/hw/core/cpu.h
12
@@ -XXX,XX +XXX,XX @@ typedef enum {
16
@@ -XXX,XX +XXX,XX @@ struct CPUWatchpoint {
13
#define TCG_TARGET_HAS_deposit_i32 1
17
* the memory regions get moved around by io_writex.
14
#define TCG_TARGET_HAS_extract_i32 1
18
*/
15
#define TCG_TARGET_HAS_sextract_i32 1
19
typedef struct SavedIOTLB {
16
-#define TCG_TARGET_HAS_extract2_i32 0
20
- hwaddr addr;
17
+#define TCG_TARGET_HAS_extract2_i32 1
21
MemoryRegionSection *section;
18
#define TCG_TARGET_HAS_movcond_i32 1
22
hwaddr mr_offset;
19
#define TCG_TARGET_HAS_add2_i32 1
23
} SavedIOTLB;
20
#define TCG_TARGET_HAS_sub2_i32 1
24
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
21
@@ -XXX,XX +XXX,XX @@ typedef enum {
22
#define TCG_TARGET_HAS_deposit_i64 1
23
#define TCG_TARGET_HAS_extract_i64 1
24
#define TCG_TARGET_HAS_sextract_i64 1
25
-#define TCG_TARGET_HAS_extract2_i64 0
26
+#define TCG_TARGET_HAS_extract2_i64 1
27
#define TCG_TARGET_HAS_movcond_i64 1
28
#define TCG_TARGET_HAS_add2_i64 1
29
#define TCG_TARGET_HAS_sub2_i64 1
30
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
31
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
32
--- a/tcg/aarch64/tcg-target.inc.c
26
--- a/accel/tcg/cputlb.c
33
+++ b/tcg/aarch64/tcg-target.inc.c
27
+++ b/accel/tcg/cputlb.c
34
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
28
@@ -XXX,XX +XXX,XX @@ static uint64_t io_readx(CPUArchState *env, CPUTLBEntryFull *full,
35
tcg_out_sbfm(s, ext, a0, a1, a2, a2 + args[3] - 1);
29
* This is read by tlb_plugin_lookup if the fulltlb entry doesn't match
36
break;
30
* because of the side effect of io_writex changing memory layout.
37
31
*/
38
+ case INDEX_op_extract2_i64:
32
-static void save_iotlb_data(CPUState *cs, hwaddr addr,
39
+ case INDEX_op_extract2_i32:
33
- MemoryRegionSection *section, hwaddr mr_offset)
40
+ tcg_out_extr(s, ext, a0, a1, a2, args[3]);
34
+static void save_iotlb_data(CPUState *cs, MemoryRegionSection *section,
41
+ break;
35
+ hwaddr mr_offset)
42
+
36
{
43
case INDEX_op_add2_i32:
37
#ifdef CONFIG_PLUGIN
44
tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, REG0(2), REG0(3),
38
SavedIOTLB *saved = &cs->saved_iotlb;
45
(int32_t)args[4], args[5], const_args[4],
39
- saved->addr = addr;
46
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
40
saved->section = section;
47
= { .args_ct_str = { "r", "r", "rAL" } };
41
saved->mr_offset = mr_offset;
48
static const TCGTargetOpDef dep
42
#endif
49
= { .args_ct_str = { "r", "0", "rZ" } };
43
@@ -XXX,XX +XXX,XX @@ static void io_writex(CPUArchState *env, CPUTLBEntryFull *full,
50
+ static const TCGTargetOpDef ext2
44
* The memory_region_dispatch may trigger a flush/resize
51
+ = { .args_ct_str = { "r", "rZ", "rZ" } };
45
* so for plugins we save the iotlb_data just in case.
52
static const TCGTargetOpDef movc
46
*/
53
= { .args_ct_str = { "r", "r", "rA", "rZ", "rZ" } };
47
- save_iotlb_data(cpu, full->xlat_section, section, mr_offset);
54
static const TCGTargetOpDef add2
48
+ save_iotlb_data(cpu, section, mr_offset);
55
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
49
56
case INDEX_op_deposit_i64:
50
if (!qemu_mutex_iothread_locked()) {
57
return &dep;
51
qemu_mutex_lock_iothread();
58
59
+ case INDEX_op_extract2_i32:
60
+ case INDEX_op_extract2_i64:
61
+ return &ext2;
62
+
63
case INDEX_op_add2_i32:
64
case INDEX_op_add2_i64:
65
case INDEX_op_sub2_i32:
66
--
52
--
67
2.17.1
53
2.34.1
68
54
69
55
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/15] cputlb: Fix io_readx() to respect the access_type
[PULL 06/20] accel/tcg: Suppress auto-invalidate in probe_access_internal
1
From: Shahab Vahedi <shahab.vahedi@gmail.com>
1
When PAGE_WRITE_INV is set when calling tlb_set_page,
2
we immediately set TLB_INVALID_MASK in order to force
3
tlb_fill to be called on the next lookup. Here in
4
probe_access_internal, we have just called tlb_fill
5
and eliminated true misses, thus the lookup must be valid.
2
6
3
This change adapts io_readx() to its input access_type. Currently
7
This allows us to remove a warning comment from s390x.
4
io_readx() treats any memory access as a read, although it has an
8
There doesn't seem to be a reason to change the code though.
5
input argument "MMUAccessType access_type". This results in:
6
9
7
1) Calling the tlb_fill() only with MMU_DATA_LOAD
10
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
2) Considering only entry->addr_read as the tlb_addr
11
Reviewed-by: David Hildenbrand <david@redhat.com>
9
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Buglink: https://bugs.launchpad.net/qemu/+bug/1825359
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Shahab Vahedi <shahab.vahedi@gmail.com>
13
Message-Id: <20190420072236.12347-1-shahab.vahedi@gmail.com>
14
[rth: Remove assert; fix expression formatting.]
15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16
---
14
---
17
accel/tcg/cputlb.c | 5 +++--
15
accel/tcg/cputlb.c | 10 +++++++++-
18
1 file changed, 3 insertions(+), 2 deletions(-)
16
target/s390x/tcg/mem_helper.c | 4 ----
17
2 files changed, 9 insertions(+), 5 deletions(-)
19
18
20
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
19
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
21
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
22
--- a/accel/tcg/cputlb.c
21
--- a/accel/tcg/cputlb.c
23
+++ b/accel/tcg/cputlb.c
22
+++ b/accel/tcg/cputlb.c
24
@@ -XXX,XX +XXX,XX @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
23
@@ -XXX,XX +XXX,XX @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
25
CPUTLBEntry *entry;
24
}
26
target_ulong tlb_addr;
25
tlb_addr = tlb_read_ofs(entry, elt_ofs);
27
26
28
- tlb_fill(cpu, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr);
27
+ flags = TLB_FLAGS_MASK;
29
+ tlb_fill(cpu, addr, size, access_type, mmu_idx, retaddr);
28
page_addr = addr & TARGET_PAGE_MASK;
30
29
if (!tlb_hit_page(tlb_addr, page_addr)) {
31
entry = tlb_entry(env, mmu_idx, addr);
30
if (!victim_tlb_hit(env, mmu_idx, index, elt_ofs, page_addr)) {
32
- tlb_addr = entry->addr_read;
31
@@ -XXX,XX +XXX,XX @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
33
+ tlb_addr = (access_type == MMU_DATA_LOAD ?
32
34
+ entry->addr_read : entry->addr_code);
33
/* TLB resize via tlb_fill may have moved the entry. */
35
if (!(tlb_addr & ~(TARGET_PAGE_MASK | TLB_RECHECK))) {
34
entry = tlb_entry(env, mmu_idx, addr);
36
/* RAM access */
35
+
37
uintptr_t haddr = addr + entry->addend;
36
+ /*
37
+ * With PAGE_WRITE_INV, we set TLB_INVALID_MASK immediately,
38
+ * to force the next access through tlb_fill. We've just
39
+ * called tlb_fill, so we know that this entry *is* valid.
40
+ */
41
+ flags &= ~TLB_INVALID_MASK;
42
}
43
tlb_addr = tlb_read_ofs(entry, elt_ofs);
44
}
45
- flags = tlb_addr & TLB_FLAGS_MASK;
46
+ flags &= tlb_addr;
47
48
/* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */
49
if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) {
50
diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/target/s390x/tcg/mem_helper.c
53
+++ b/target/s390x/tcg/mem_helper.c
54
@@ -XXX,XX +XXX,XX @@ static int s390_probe_access(CPUArchState *env, target_ulong addr, int size,
55
#else
56
int flags;
57
58
- /*
59
- * For !CONFIG_USER_ONLY, we cannot rely on TLB_INVALID_MASK or haddr==NULL
60
- * to detect if there was an exception during tlb_fill().
61
- */
62
env->tlb_fill_exc = 0;
63
flags = probe_access_flags(env, addr, access_type, mmu_idx, nonfault, phost,
64
ra);
38
--
65
--
39
2.17.1
66
2.34.1
40
67
41
68
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/15] tcg/i386: Support INDEX_op_extract2_{i32, i64}
[PULL 07/20] accel/tcg: Introduce probe_access_full
1
Add an interface to return the CPUTLBEntryFull struct
2
that goes with the lookup. The result is not intended
3
to be valid across multiple lookups, so the user must
4
use the results immediately.
5
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2
---
10
---
3
tcg/i386/tcg-target.h | 4 ++--
11
include/exec/exec-all.h | 15 +++++++++++++
4
tcg/i386/tcg-target.inc.c | 11 +++++++++++
12
include/qemu/typedefs.h | 1 +
5
2 files changed, 13 insertions(+), 2 deletions(-)
13
accel/tcg/cputlb.c | 47 +++++++++++++++++++++++++----------------
14
3 files changed, 45 insertions(+), 18 deletions(-)
6
15
7
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
16
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
8
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
9
--- a/tcg/i386/tcg-target.h
18
--- a/include/exec/exec-all.h
10
+++ b/tcg/i386/tcg-target.h
19
+++ b/include/exec/exec-all.h
11
@@ -XXX,XX +XXX,XX @@ extern bool have_avx2;
20
@@ -XXX,XX +XXX,XX @@ int probe_access_flags(CPUArchState *env, target_ulong addr,
12
#define TCG_TARGET_HAS_deposit_i32 1
21
MMUAccessType access_type, int mmu_idx,
13
#define TCG_TARGET_HAS_extract_i32 1
22
bool nonfault, void **phost, uintptr_t retaddr);
14
#define TCG_TARGET_HAS_sextract_i32 1
23
15
-#define TCG_TARGET_HAS_extract2_i32 0
24
+#ifndef CONFIG_USER_ONLY
16
+#define TCG_TARGET_HAS_extract2_i32 1
25
+/**
17
#define TCG_TARGET_HAS_movcond_i32 1
26
+ * probe_access_full:
18
#define TCG_TARGET_HAS_add2_i32 1
27
+ * Like probe_access_flags, except also return into @pfull.
19
#define TCG_TARGET_HAS_sub2_i32 1
28
+ *
20
@@ -XXX,XX +XXX,XX @@ extern bool have_avx2;
29
+ * The CPUTLBEntryFull structure returned via @pfull is transient
21
#define TCG_TARGET_HAS_deposit_i64 1
30
+ * and must be consumed or copied immediately, before any further
22
#define TCG_TARGET_HAS_extract_i64 1
31
+ * access or changes to TLB @mmu_idx.
23
#define TCG_TARGET_HAS_sextract_i64 0
32
+ */
24
-#define TCG_TARGET_HAS_extract2_i64 0
33
+int probe_access_full(CPUArchState *env, target_ulong addr,
25
+#define TCG_TARGET_HAS_extract2_i64 1
34
+ MMUAccessType access_type, int mmu_idx,
26
#define TCG_TARGET_HAS_movcond_i64 1
35
+ bool nonfault, void **phost,
27
#define TCG_TARGET_HAS_add2_i64 1
36
+ CPUTLBEntryFull **pfull, uintptr_t retaddr);
28
#define TCG_TARGET_HAS_sub2_i64 1
37
+#endif
29
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
38
+
39
#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
40
41
/* Estimated block size for TB allocation. */
42
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
30
index XXXXXXX..XXXXXXX 100644
43
index XXXXXXX..XXXXXXX 100644
31
--- a/tcg/i386/tcg-target.inc.c
44
--- a/include/qemu/typedefs.h
32
+++ b/tcg/i386/tcg-target.inc.c
45
+++ b/include/qemu/typedefs.h
33
@@ -XXX,XX +XXX,XX @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
46
@@ -XXX,XX +XXX,XX @@ typedef struct ConfidentialGuestSupport ConfidentialGuestSupport;
34
#define OPC_SHUFPS (0xc6 | P_EXT)
47
typedef struct CPUAddressSpace CPUAddressSpace;
35
#define OPC_SHLX (0xf7 | P_EXT38 | P_DATA16)
48
typedef struct CPUArchState CPUArchState;
36
#define OPC_SHRX (0xf7 | P_EXT38 | P_SIMDF2)
49
typedef struct CPUState CPUState;
37
+#define OPC_SHRD_Ib (0xac | P_EXT)
50
+typedef struct CPUTLBEntryFull CPUTLBEntryFull;
38
#define OPC_TESTL    (0x85)
51
typedef struct DeviceListener DeviceListener;
39
#define OPC_TZCNT (0xbc | P_EXT | P_SIMDF3)
52
typedef struct DeviceState DeviceState;
40
#define OPC_UD2 (0x0b | P_EXT)
53
typedef struct DirtyBitmapSnapshot DirtyBitmapSnapshot;
41
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
54
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
42
}
55
index XXXXXXX..XXXXXXX 100644
43
break;
56
--- a/accel/tcg/cputlb.c
44
57
+++ b/accel/tcg/cputlb.c
45
+ OP_32_64(extract2):
58
@@ -XXX,XX +XXX,XX @@ static void notdirty_write(CPUState *cpu, vaddr mem_vaddr, unsigned size,
46
+ /* Note that SHRD outputs to the r/m operand. */
59
static int probe_access_internal(CPUArchState *env, target_ulong addr,
47
+ tcg_out_modrm(s, OPC_SHRD_Ib + rexw, a2, a0);
60
int fault_size, MMUAccessType access_type,
48
+ tcg_out8(s, args[3]);
61
int mmu_idx, bool nonfault,
49
+ break;
62
- void **phost, uintptr_t retaddr)
63
+ void **phost, CPUTLBEntryFull **pfull,
64
+ uintptr_t retaddr)
65
{
66
uintptr_t index = tlb_index(env, mmu_idx, addr);
67
CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
68
@@ -XXX,XX +XXX,XX @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
69
mmu_idx, nonfault, retaddr)) {
70
/* Non-faulting page table read failed. */
71
*phost = NULL;
72
+ *pfull = NULL;
73
return TLB_INVALID_MASK;
74
}
75
76
/* TLB resize via tlb_fill may have moved the entry. */
77
+ index = tlb_index(env, mmu_idx, addr);
78
entry = tlb_entry(env, mmu_idx, addr);
79
80
/*
81
@@ -XXX,XX +XXX,XX @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
82
}
83
flags &= tlb_addr;
84
85
+ *pfull = &env_tlb(env)->d[mmu_idx].fulltlb[index];
50
+
86
+
51
case INDEX_op_mb:
87
/* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */
52
tcg_out_mb(s, a0);
88
if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) {
53
break;
89
*phost = NULL;
54
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
90
@@ -XXX,XX +XXX,XX @@ static int probe_access_internal(CPUArchState *env, target_ulong addr,
55
static const TCGTargetOpDef r_0 = { .args_ct_str = { "r", "0" } };
91
return flags;
56
static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
92
}
57
static const TCGTargetOpDef r_r_re = { .args_ct_str = { "r", "r", "re" } };
93
58
+ static const TCGTargetOpDef r_0_r = { .args_ct_str = { "r", "0", "r" } };
94
-int probe_access_flags(CPUArchState *env, target_ulong addr,
59
static const TCGTargetOpDef r_0_re = { .args_ct_str = { "r", "0", "re" } };
95
- MMUAccessType access_type, int mmu_idx,
60
static const TCGTargetOpDef r_0_ci = { .args_ct_str = { "r", "0", "ci" } };
96
- bool nonfault, void **phost, uintptr_t retaddr)
61
static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
97
+int probe_access_full(CPUArchState *env, target_ulong addr,
62
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
98
+ MMUAccessType access_type, int mmu_idx,
63
case INDEX_op_ctpop_i32:
99
+ bool nonfault, void **phost, CPUTLBEntryFull **pfull,
64
case INDEX_op_ctpop_i64:
100
+ uintptr_t retaddr)
65
return &r_r;
101
{
66
+ case INDEX_op_extract2_i32:
102
- int flags;
67
+ case INDEX_op_extract2_i64:
103
-
68
+ return &r_0_r;
104
- flags = probe_access_internal(env, addr, 0, access_type, mmu_idx,
69
105
- nonfault, phost, retaddr);
70
case INDEX_op_deposit_i32:
106
+ int flags = probe_access_internal(env, addr, 0, access_type, mmu_idx,
71
case INDEX_op_deposit_i64:
107
+ nonfault, phost, pfull, retaddr);
108
109
/* Handle clean RAM pages. */
110
if (unlikely(flags & TLB_NOTDIRTY)) {
111
- uintptr_t index = tlb_index(env, mmu_idx, addr);
112
- CPUTLBEntryFull *full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
113
-
114
- notdirty_write(env_cpu(env), addr, 1, full, retaddr);
115
+ notdirty_write(env_cpu(env), addr, 1, *pfull, retaddr);
116
flags &= ~TLB_NOTDIRTY;
117
}
118
119
return flags;
120
}
121
122
+int probe_access_flags(CPUArchState *env, target_ulong addr,
123
+ MMUAccessType access_type, int mmu_idx,
124
+ bool nonfault, void **phost, uintptr_t retaddr)
125
+{
126
+ CPUTLBEntryFull *full;
127
+
128
+ return probe_access_full(env, addr, access_type, mmu_idx,
129
+ nonfault, phost, &full, retaddr);
130
+}
131
+
132
void *probe_access(CPUArchState *env, target_ulong addr, int size,
133
MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
134
{
135
+ CPUTLBEntryFull *full;
136
void *host;
137
int flags;
138
139
g_assert(-(addr | TARGET_PAGE_MASK) >= size);
140
141
flags = probe_access_internal(env, addr, size, access_type, mmu_idx,
142
- false, &host, retaddr);
143
+ false, &host, &full, retaddr);
144
145
/* Per the interface, size == 0 merely faults the access. */
146
if (size == 0) {
147
@@ -XXX,XX +XXX,XX @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
148
}
149
150
if (unlikely(flags & (TLB_NOTDIRTY | TLB_WATCHPOINT))) {
151
- uintptr_t index = tlb_index(env, mmu_idx, addr);
152
- CPUTLBEntryFull *full = &env_tlb(env)->d[mmu_idx].fulltlb[index];
153
-
154
/* Handle watchpoints. */
155
if (flags & TLB_WATCHPOINT) {
156
int wp_access = (access_type == MMU_DATA_STORE
157
@@ -XXX,XX +XXX,XX @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
158
void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
159
MMUAccessType access_type, int mmu_idx)
160
{
161
+ CPUTLBEntryFull *full;
162
void *host;
163
int flags;
164
165
flags = probe_access_internal(env, addr, 0, access_type,
166
- mmu_idx, true, &host, 0);
167
+ mmu_idx, true, &host, &full, 0);
168
169
/* No combination of flags are expected by the caller. */
170
return flags ? NULL : host;
171
@@ -XXX,XX +XXX,XX @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
172
tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr,
173
void **hostp)
174
{
175
+ CPUTLBEntryFull *full;
176
void *p;
177
178
(void)probe_access_internal(env, addr, 1, MMU_INST_FETCH,
179
- cpu_mmu_index(env, true), false, &p, 0);
180
+ cpu_mmu_index(env, true), false, &p, &full, 0);
181
if (p == NULL) {
182
return -1;
183
}
72
--
184
--
73
2.17.1
185
2.34.1
74
186
75
187
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/15] tcg: Implement tcg_gen_extract2_{i32, i64}
[PULL 08/20] accel/tcg: Introduce tlb_set_page_full
1
From: David Hildenbrand <david@redhat.com>
1
Now that we have collected all of the page data into
2
CPUTLBEntryFull, provide an interface to record that
3
all in one go, instead of using 4 arguments. This interface
4
allows CPUTLBEntryFull to be extended without having to
5
change the number of arguments.
2
6
3
Will be helpful for s390x. Input 128 bit and output 64 bit only,
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
which is sufficient for now.
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: David Hildenbrand <david@redhat.com>
9
Message-Id: <20190225154204.26751-1-david@redhat.com>
10
[rth: Add matching tcg_gen_extract2_i32.]
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
---
11
---
13
tcg/tcg-op.h | 6 ++++++
12
include/exec/cpu-defs.h | 14 +++++++++++
14
tcg/tcg-op.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
13
include/exec/exec-all.h | 22 ++++++++++++++++++
15
2 files changed, 50 insertions(+)
14
accel/tcg/cputlb.c | 51 ++++++++++++++++++++++++++---------------
15
3 files changed, 69 insertions(+), 18 deletions(-)
16
16
17
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
17
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
18
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
19
--- a/tcg/tcg-op.h
19
--- a/include/exec/cpu-defs.h
20
+++ b/tcg/tcg-op.h
20
+++ b/include/exec/cpu-defs.h
21
@@ -XXX,XX +XXX,XX @@ void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg,
21
@@ -XXX,XX +XXX,XX @@ typedef struct CPUTLBEntryFull {
22
unsigned int ofs, unsigned int len);
22
* + the offset within the target MemoryRegion (otherwise)
23
void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg,
23
*/
24
unsigned int ofs, unsigned int len);
24
hwaddr xlat_section;
25
+void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah,
25
+
26
+ unsigned int ofs);
26
+ /*
27
void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *);
27
+ * @phys_addr contains the physical address in the address space
28
void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *);
28
+ * given by cpu_asidx_from_attrs(cpu, @attrs).
29
void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
29
+ */
30
@@ -XXX,XX +XXX,XX @@ void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg,
30
+ hwaddr phys_addr;
31
unsigned int ofs, unsigned int len);
31
+
32
void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg,
32
+ /* @attrs contains the memory transaction attributes for the page. */
33
unsigned int ofs, unsigned int len);
33
MemTxAttrs attrs;
34
+void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah,
34
+
35
+ unsigned int ofs);
35
+ /* @prot contains the complete protections for the page. */
36
void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *);
36
+ uint8_t prot;
37
void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *);
37
+
38
void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
38
+ /* @lg_page_size contains the log2 of the page size. */
39
@@ -XXX,XX +XXX,XX @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
39
+ uint8_t lg_page_size;
40
#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64
40
} CPUTLBEntryFull;
41
#define tcg_gen_extract_tl tcg_gen_extract_i64
41
42
#define tcg_gen_sextract_tl tcg_gen_sextract_i64
42
/*
43
+#define tcg_gen_extract2_tl tcg_gen_extract2_i64
43
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
44
#define tcg_const_tl tcg_const_i64
45
#define tcg_const_local_tl tcg_const_local_i64
46
#define tcg_gen_movcond_tl tcg_gen_movcond_i64
47
@@ -XXX,XX +XXX,XX @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
48
#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32
49
#define tcg_gen_extract_tl tcg_gen_extract_i32
50
#define tcg_gen_sextract_tl tcg_gen_sextract_i32
51
+#define tcg_gen_extract2_tl tcg_gen_extract2_i32
52
#define tcg_const_tl tcg_const_i32
53
#define tcg_const_local_tl tcg_const_local_i32
54
#define tcg_gen_movcond_tl tcg_gen_movcond_i32
55
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
56
index XXXXXXX..XXXXXXX 100644
44
index XXXXXXX..XXXXXXX 100644
57
--- a/tcg/tcg-op.c
45
--- a/include/exec/exec-all.h
58
+++ b/tcg/tcg-op.c
46
+++ b/include/exec/exec-all.h
59
@@ -XXX,XX +XXX,XX @@ void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg,
47
@@ -XXX,XX +XXX,XX @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu,
60
tcg_gen_sari_i32(ret, ret, 32 - len);
48
uint16_t idxmap,
49
unsigned bits);
50
51
+/**
52
+ * tlb_set_page_full:
53
+ * @cpu: CPU context
54
+ * @mmu_idx: mmu index of the tlb to modify
55
+ * @vaddr: virtual address of the entry to add
56
+ * @full: the details of the tlb entry
57
+ *
58
+ * Add an entry to @cpu tlb index @mmu_idx. All of the fields of
59
+ * @full must be filled, except for xlat_section, and constitute
60
+ * the complete description of the translated page.
61
+ *
62
+ * This is generally called by the target tlb_fill function after
63
+ * having performed a successful page table walk to find the physical
64
+ * address and attributes for the translation.
65
+ *
66
+ * At most one entry for a given virtual address is permitted. Only a
67
+ * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only
68
+ * used by tlb_flush_page.
69
+ */
70
+void tlb_set_page_full(CPUState *cpu, int mmu_idx, target_ulong vaddr,
71
+ CPUTLBEntryFull *full);
72
+
73
/**
74
* tlb_set_page_with_attrs:
75
* @cpu: CPU to add this TLB entry for
76
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
77
index XXXXXXX..XXXXXXX 100644
78
--- a/accel/tcg/cputlb.c
79
+++ b/accel/tcg/cputlb.c
80
@@ -XXX,XX +XXX,XX @@ static void tlb_add_large_page(CPUArchState *env, int mmu_idx,
81
env_tlb(env)->d[mmu_idx].large_page_mask = lp_mask;
61
}
82
}
62
83
84
-/* Add a new TLB entry. At most one entry for a given virtual address
63
+/*
85
+/*
64
+ * Extract 32-bits from a 64-bit input, ah:al, starting from ofs.
86
+ * Add a new TLB entry. At most one entry for a given virtual address
65
+ * Unlike tcg_gen_extract_i32 above, len is fixed at 32.
87
* is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the
66
+ */
88
* supplied size is only used by tlb_flush_page.
67
+void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah,
89
*
68
+ unsigned int ofs)
90
* Called from TCG-generated code, which is under an RCU read-side
91
* critical section.
92
*/
93
-void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
94
- hwaddr paddr, MemTxAttrs attrs, int prot,
95
- int mmu_idx, target_ulong size)
96
+void tlb_set_page_full(CPUState *cpu, int mmu_idx,
97
+ target_ulong vaddr, CPUTLBEntryFull *full)
98
{
99
CPUArchState *env = cpu->env_ptr;
100
CPUTLB *tlb = env_tlb(env);
101
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
102
CPUTLBEntry *te, tn;
103
hwaddr iotlb, xlat, sz, paddr_page;
104
target_ulong vaddr_page;
105
- int asidx = cpu_asidx_from_attrs(cpu, attrs);
106
- int wp_flags;
107
+ int asidx, wp_flags, prot;
108
bool is_ram, is_romd;
109
110
assert_cpu_is_self(cpu);
111
112
- if (size <= TARGET_PAGE_SIZE) {
113
+ if (full->lg_page_size <= TARGET_PAGE_BITS) {
114
sz = TARGET_PAGE_SIZE;
115
} else {
116
- tlb_add_large_page(env, mmu_idx, vaddr, size);
117
- sz = size;
118
+ sz = (hwaddr)1 << full->lg_page_size;
119
+ tlb_add_large_page(env, mmu_idx, vaddr, sz);
120
}
121
vaddr_page = vaddr & TARGET_PAGE_MASK;
122
- paddr_page = paddr & TARGET_PAGE_MASK;
123
+ paddr_page = full->phys_addr & TARGET_PAGE_MASK;
124
125
+ prot = full->prot;
126
+ asidx = cpu_asidx_from_attrs(cpu, full->attrs);
127
section = address_space_translate_for_iotlb(cpu, asidx, paddr_page,
128
- &xlat, &sz, attrs, &prot);
129
+ &xlat, &sz, full->attrs, &prot);
130
assert(sz >= TARGET_PAGE_SIZE);
131
132
tlb_debug("vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
133
" prot=%x idx=%d\n",
134
- vaddr, paddr, prot, mmu_idx);
135
+ vaddr, full->phys_addr, prot, mmu_idx);
136
137
address = vaddr_page;
138
- if (size < TARGET_PAGE_SIZE) {
139
+ if (full->lg_page_size < TARGET_PAGE_BITS) {
140
/* Repeat the MMU check and TLB fill on every access. */
141
address |= TLB_INVALID_MASK;
142
}
143
- if (attrs.byte_swap) {
144
+ if (full->attrs.byte_swap) {
145
address |= TLB_BSWAP;
146
}
147
148
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
149
* subtract here is that of the page base, and not the same as the
150
* vaddr we add back in io_readx()/io_writex()/get_page_addr_code().
151
*/
152
+ desc->fulltlb[index] = *full;
153
desc->fulltlb[index].xlat_section = iotlb - vaddr_page;
154
- desc->fulltlb[index].attrs = attrs;
155
+ desc->fulltlb[index].phys_addr = paddr_page;
156
+ desc->fulltlb[index].prot = prot;
157
158
/* Now calculate the new entry */
159
tn.addend = addend - vaddr_page;
160
@@ -XXX,XX +XXX,XX @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
161
qemu_spin_unlock(&tlb->c.lock);
162
}
163
164
-/* Add a new TLB entry, but without specifying the memory
165
- * transaction attributes to be used.
166
- */
167
+void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
168
+ hwaddr paddr, MemTxAttrs attrs, int prot,
169
+ int mmu_idx, target_ulong size)
69
+{
170
+{
70
+ tcg_debug_assert(ofs <= 32);
171
+ CPUTLBEntryFull full = {
71
+ if (ofs == 0) {
172
+ .phys_addr = paddr,
72
+ tcg_gen_mov_i32(ret, al);
173
+ .attrs = attrs,
73
+ } else if (ofs == 32) {
174
+ .prot = prot,
74
+ tcg_gen_mov_i32(ret, ah);
175
+ .lg_page_size = ctz64(size)
75
+ } else if (al == ah) {
176
+ };
76
+ tcg_gen_rotri_i32(ret, al, ofs);
177
+
77
+ } else {
178
+ assert(is_power_of_2(size));
78
+ TCGv_i32 t0 = tcg_temp_new_i32();
179
+ tlb_set_page_full(cpu, mmu_idx, vaddr, &full);
79
+ tcg_gen_shri_i32(t0, al, ofs);
80
+ tcg_gen_deposit_i32(ret, t0, ah, 32 - ofs, ofs);
81
+ tcg_temp_free_i32(t0);
82
+ }
83
+}
180
+}
84
+
181
+
85
void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1,
182
void tlb_set_page(CPUState *cpu, target_ulong vaddr,
86
TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2)
183
hwaddr paddr, int prot,
87
{
184
int mmu_idx, target_ulong size)
88
@@ -XXX,XX +XXX,XX @@ void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg,
89
tcg_gen_sari_i64(ret, ret, 64 - len);
90
}
91
92
+/*
93
+ * Extract 64 bits from a 128-bit input, ah:al, starting from ofs.
94
+ * Unlike tcg_gen_extract_i64 above, len is fixed at 64.
95
+ */
96
+void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah,
97
+ unsigned int ofs)
98
+{
99
+ tcg_debug_assert(ofs <= 64);
100
+ if (ofs == 0) {
101
+ tcg_gen_mov_i64(ret, al);
102
+ } else if (ofs == 64) {
103
+ tcg_gen_mov_i64(ret, ah);
104
+ } else if (al == ah) {
105
+ tcg_gen_rotri_i64(ret, al, ofs);
106
+ } else {
107
+ TCGv_i64 t0 = tcg_temp_new_i64();
108
+ tcg_gen_shri_i64(t0, al, ofs);
109
+ tcg_gen_deposit_i64(ret, t0, ah, 64 - ofs, ofs);
110
+ tcg_temp_free_i64(t0);
111
+ }
112
+}
113
+
114
void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1,
115
TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2)
116
{
117
--
185
--
118
2.17.1
186
2.34.1
119
187
120
188
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/15] tcg/arm: Support INDEX_op_extract2_i32
[PULL 09/20] include/exec: Introduce TARGET_PAGE_ENTRY_EXTRA
1
Allow the target to cache items from the guest page tables.
2
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
1
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
7
---
4
tcg/arm/tcg-target.h | 2 +-
8
include/exec/cpu-defs.h | 9 +++++++++
5
tcg/arm/tcg-target.inc.c | 25 +++++++++++++++++++++++++
9
1 file changed, 9 insertions(+)
6
2 files changed, 26 insertions(+), 1 deletion(-)
7
10
8
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
11
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
9
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
10
--- a/tcg/arm/tcg-target.h
13
--- a/include/exec/cpu-defs.h
11
+++ b/tcg/arm/tcg-target.h
14
+++ b/include/exec/cpu-defs.h
12
@@ -XXX,XX +XXX,XX @@ extern bool use_idiv_instructions;
15
@@ -XXX,XX +XXX,XX @@ typedef struct CPUTLBEntryFull {
13
#define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions
16
14
#define TCG_TARGET_HAS_extract_i32 use_armv7_instructions
17
/* @lg_page_size contains the log2 of the page size. */
15
#define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions
18
uint8_t lg_page_size;
16
-#define TCG_TARGET_HAS_extract2_i32 0
19
+
17
+#define TCG_TARGET_HAS_extract2_i32 1
20
+ /*
18
#define TCG_TARGET_HAS_movcond_i32 1
21
+ * Allow target-specific additions to this structure.
19
#define TCG_TARGET_HAS_mulu2_i32 1
22
+ * This may be used to cache items from the guest cpu
20
#define TCG_TARGET_HAS_muls2_i32 1
23
+ * page tables for later use by the implementation.
21
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
24
+ */
22
index XXXXXXX..XXXXXXX 100644
25
+#ifdef TARGET_PAGE_ENTRY_EXTRA
23
--- a/tcg/arm/tcg-target.inc.c
26
+ TARGET_PAGE_ENTRY_EXTRA
24
+++ b/tcg/arm/tcg-target.inc.c
27
+#endif
25
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
28
} CPUTLBEntryFull;
26
case INDEX_op_sextract_i32:
29
27
tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]);
30
/*
28
break;
29
+ case INDEX_op_extract2_i32:
30
+ /* ??? These optimization vs zero should be generic. */
31
+ /* ??? But we can't substitute 2 for 1 in the opcode stream yet. */
32
+ if (const_args[1]) {
33
+ if (const_args[2]) {
34
+ tcg_out_movi(s, TCG_TYPE_REG, args[0], 0);
35
+ } else {
36
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0,
37
+ args[2], SHIFT_IMM_LSL(32 - args[3]));
38
+ }
39
+ } else if (const_args[2]) {
40
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0,
41
+ args[1], SHIFT_IMM_LSR(args[3]));
42
+ } else {
43
+ /* We can do extract2 in 2 insns, vs the 3 required otherwise. */
44
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0,
45
+ args[2], SHIFT_IMM_LSL(32 - args[3]));
46
+ tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP,
47
+ args[1], SHIFT_IMM_LSR(args[3]));
48
+ }
49
+ break;
50
51
case INDEX_op_div_i32:
52
tcg_out_sdiv(s, COND_AL, args[0], args[1], args[2]);
53
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
54
= { .args_ct_str = { "s", "s", "s", "s" } };
55
static const TCGTargetOpDef br
56
= { .args_ct_str = { "r", "rIN" } };
57
+ static const TCGTargetOpDef ext2
58
+ = { .args_ct_str = { "r", "rZ", "rZ" } };
59
static const TCGTargetOpDef dep
60
= { .args_ct_str = { "r", "0", "rZ" } };
61
static const TCGTargetOpDef movc
62
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
63
return &br;
64
case INDEX_op_deposit_i32:
65
return &dep;
66
+ case INDEX_op_extract2_i32:
67
+ return &ext2;
68
case INDEX_op_movcond_i32:
69
return &movc;
70
case INDEX_op_add2_i32:
71
--
31
--
72
2.17.1
32
2.34.1
73
33
74
34
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/15] tcg: Restart TB generation after out-of-line ldst overflow
[PULL 10/20] accel/tcg: Remove PageDesc code_bitmap
1
This is part c of relocation overflow handling.
1
This bitmap is created and discarded immediately.
2
We gain nothing by its existence.
2
3
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-Id: <20220822232338.1727934-2-richard.henderson@linaro.org>
4
---
7
---
5
tcg/aarch64/tcg-target.inc.c | 16 ++++++++++------
8
accel/tcg/translate-all.c | 78 ++-------------------------------------
6
tcg/arm/tcg-target.inc.c | 16 ++++++++++------
9
1 file changed, 4 insertions(+), 74 deletions(-)
7
tcg/i386/tcg-target.inc.c | 6 ++++--
8
tcg/mips/tcg-target.inc.c | 6 ++++--
9
tcg/ppc/tcg-target.inc.c | 14 ++++++++++----
10
tcg/riscv/tcg-target.inc.c | 16 ++++++++++++----
11
tcg/s390/tcg-target.inc.c | 20 ++++++++++++--------
12
tcg/tcg-ldst.inc.c | 18 +++++++++---------
13
tcg/tcg.c | 7 ++++---
14
9 files changed, 75 insertions(+), 44 deletions(-)
15
10
16
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
11
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
17
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
18
--- a/tcg/aarch64/tcg-target.inc.c
13
--- a/accel/tcg/translate-all.c
19
+++ b/tcg/aarch64/tcg-target.inc.c
14
+++ b/accel/tcg/translate-all.c
20
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_adr(TCGContext *s, TCGReg rd, void *target)
15
@@ -XXX,XX +XXX,XX @@
21
tcg_out_insn(s, 3406, ADR, rd, offset);
16
#define assert_memory_lock() tcg_debug_assert(have_mmap_lock())
17
#endif
18
19
-#define SMC_BITMAP_USE_THRESHOLD 10
20
-
21
typedef struct PageDesc {
22
/* list of TBs intersecting this ram page */
23
uintptr_t first_tb;
24
-#ifdef CONFIG_SOFTMMU
25
- /* in order to optimize self modifying code, we count the number
26
- of lookups we do to a given page to use a bitmap */
27
- unsigned long *code_bitmap;
28
- unsigned int code_write_count;
29
-#else
30
+#ifdef CONFIG_USER_ONLY
31
unsigned long flags;
32
void *target_data;
33
#endif
34
-#ifndef CONFIG_USER_ONLY
35
+#ifdef CONFIG_SOFTMMU
36
QemuSpin lock;
37
#endif
38
} PageDesc;
39
@@ -XXX,XX +XXX,XX @@ void tb_htable_init(void)
40
qht_init(&tb_ctx.htable, tb_cmp, CODE_GEN_HTABLE_SIZE, mode);
22
}
41
}
23
42
24
-static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
43
-/* call with @p->lock held */
25
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
44
-static inline void invalidate_page_bitmap(PageDesc *p)
45
-{
46
- assert_page_locked(p);
47
-#ifdef CONFIG_SOFTMMU
48
- g_free(p->code_bitmap);
49
- p->code_bitmap = NULL;
50
- p->code_write_count = 0;
51
-#endif
52
-}
53
-
54
/* Set to NULL all the 'first_tb' fields in all PageDescs. */
55
static void page_flush_tb_1(int level, void **lp)
26
{
56
{
27
TCGMemOpIdx oi = lb->oi;
57
@@ -XXX,XX +XXX,XX @@ static void page_flush_tb_1(int level, void **lp)
28
TCGMemOp opc = get_memop(oi);
58
for (i = 0; i < V_L2_SIZE; ++i) {
29
TCGMemOp size = opc & MO_SIZE;
59
page_lock(&pd[i]);
30
60
pd[i].first_tb = (uintptr_t)NULL;
31
- bool ok = reloc_pc19(lb->label_ptr[0], s->code_ptr);
61
- invalidate_page_bitmap(pd + i);
32
- tcg_debug_assert(ok);
62
page_unlock(&pd[i]);
33
+ if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) {
63
}
34
+ return false;
64
} else {
35
+ }
65
@@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
36
66
if (rm_from_page_list) {
37
tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0);
67
p = page_find(tb->page_addr[0] >> TARGET_PAGE_BITS);
38
tcg_out_mov(s, TARGET_LONG_BITS == 64, TCG_REG_X1, lb->addrlo_reg);
68
tb_page_remove(p, tb);
39
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
69
- invalidate_page_bitmap(p);
70
if (tb->page_addr[1] != -1) {
71
p = page_find(tb->page_addr[1] >> TARGET_PAGE_BITS);
72
tb_page_remove(p, tb);
73
- invalidate_page_bitmap(p);
74
}
40
}
75
}
41
76
42
tcg_out_goto(s, lb->raddr);
77
@@ -XXX,XX +XXX,XX @@ void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr)
43
+ return true;
44
}
45
46
-static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
47
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
48
{
49
TCGMemOpIdx oi = lb->oi;
50
TCGMemOp opc = get_memop(oi);
51
TCGMemOp size = opc & MO_SIZE;
52
53
- bool ok = reloc_pc19(lb->label_ptr[0], s->code_ptr);
54
- tcg_debug_assert(ok);
55
+ if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) {
56
+ return false;
57
+ }
58
59
tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0);
60
tcg_out_mov(s, TARGET_LONG_BITS == 64, TCG_REG_X1, lb->addrlo_reg);
61
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
62
tcg_out_adr(s, TCG_REG_X4, lb->raddr);
63
tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
64
tcg_out_goto(s, lb->raddr);
65
+ return true;
66
}
67
68
static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
69
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
70
index XXXXXXX..XXXXXXX 100644
71
--- a/tcg/arm/tcg-target.inc.c
72
+++ b/tcg/arm/tcg-target.inc.c
73
@@ -XXX,XX +XXX,XX @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
74
label->label_ptr[0] = label_ptr;
75
}
76
77
-static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
78
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
79
{
80
TCGReg argreg, datalo, datahi;
81
TCGMemOpIdx oi = lb->oi;
82
TCGMemOp opc = get_memop(oi);
83
void *func;
84
85
- bool ok = reloc_pc24(lb->label_ptr[0], s->code_ptr);
86
- tcg_debug_assert(ok);
87
+ if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) {
88
+ return false;
89
+ }
90
91
argreg = tcg_out_arg_reg32(s, TCG_REG_R0, TCG_AREG0);
92
if (TARGET_LONG_BITS == 64) {
93
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
94
}
95
96
tcg_out_goto(s, COND_AL, lb->raddr);
97
+ return true;
98
}
99
100
-static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
101
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
102
{
103
TCGReg argreg, datalo, datahi;
104
TCGMemOpIdx oi = lb->oi;
105
TCGMemOp opc = get_memop(oi);
106
107
- bool ok = reloc_pc24(lb->label_ptr[0], s->code_ptr);
108
- tcg_debug_assert(ok);
109
+ if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) {
110
+ return false;
111
+ }
112
113
argreg = TCG_REG_R0;
114
argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0);
115
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
116
117
/* Tail-call to the helper, which will return to the fast path. */
118
tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
119
+ return true;
120
}
121
#endif /* SOFTMMU */
122
123
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
124
index XXXXXXX..XXXXXXX 100644
125
--- a/tcg/i386/tcg-target.inc.c
126
+++ b/tcg/i386/tcg-target.inc.c
127
@@ -XXX,XX +XXX,XX @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64,
128
/*
129
* Generate code for the slow path for a load at the end of block
130
*/
131
-static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
132
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
133
{
134
TCGMemOpIdx oi = l->oi;
135
TCGMemOp opc = get_memop(oi);
136
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
137
138
/* Jump to the code corresponding to next IR of qemu_st */
139
tcg_out_jmp(s, l->raddr);
140
+ return true;
141
}
142
143
/*
144
* Generate code for the slow path for a store at the end of block
145
*/
146
-static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
147
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
148
{
149
TCGMemOpIdx oi = l->oi;
150
TCGMemOp opc = get_memop(oi);
151
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
152
/* "Tail call" to the helper, with the return address back inline. */
153
tcg_out_push(s, retaddr);
154
tcg_out_jmp(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
155
+ return true;
156
}
157
#elif TCG_TARGET_REG_BITS == 32
158
# define x86_guest_base_seg 0
159
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
160
index XXXXXXX..XXXXXXX 100644
161
--- a/tcg/mips/tcg-target.inc.c
162
+++ b/tcg/mips/tcg-target.inc.c
163
@@ -XXX,XX +XXX,XX @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
164
}
78
}
165
}
79
}
166
80
167
-static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
81
-#ifdef CONFIG_SOFTMMU
168
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
82
-/* call with @p->lock held */
169
{
83
-static void build_page_bitmap(PageDesc *p)
170
TCGMemOpIdx oi = l->oi;
84
-{
171
TCGMemOp opc = get_memop(oi);
85
- int n, tb_start, tb_end;
172
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
86
- TranslationBlock *tb;
173
} else {
87
-
174
tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO);
88
- assert_page_locked(p);
89
- p->code_bitmap = bitmap_new(TARGET_PAGE_SIZE);
90
-
91
- PAGE_FOR_EACH_TB(p, tb, n) {
92
- /* NOTE: this is subtle as a TB may span two physical pages */
93
- if (n == 0) {
94
- /* NOTE: tb_end may be after the end of the page, but
95
- it is not a problem */
96
- tb_start = tb->pc & ~TARGET_PAGE_MASK;
97
- tb_end = tb_start + tb->size;
98
- if (tb_end > TARGET_PAGE_SIZE) {
99
- tb_end = TARGET_PAGE_SIZE;
100
- }
101
- } else {
102
- tb_start = 0;
103
- tb_end = ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
104
- }
105
- bitmap_set(p->code_bitmap, tb_start, tb_end - tb_start);
106
- }
107
-}
108
-#endif
109
-
110
/* add the tb in the target page and protect it if necessary
111
*
112
* Called with mmap_lock held for user-mode emulation.
113
@@ -XXX,XX +XXX,XX @@ static inline void tb_page_add(PageDesc *p, TranslationBlock *tb,
114
page_already_protected = p->first_tb != (uintptr_t)NULL;
115
#endif
116
p->first_tb = (uintptr_t)tb | n;
117
- invalidate_page_bitmap(p);
118
119
#if defined(CONFIG_USER_ONLY)
120
/* translator_loop() must have made all TB pages non-writable */
121
@@ -XXX,XX +XXX,XX @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
122
/* remove TB from the page(s) if we couldn't insert it */
123
if (unlikely(existing_tb)) {
124
tb_page_remove(p, tb);
125
- invalidate_page_bitmap(p);
126
if (p2) {
127
tb_page_remove(p2, tb);
128
- invalidate_page_bitmap(p2);
129
}
130
tb = existing_tb;
175
}
131
}
176
+ return true;
132
@@ -XXX,XX +XXX,XX @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages,
177
}
133
#if !defined(CONFIG_USER_ONLY)
178
134
/* if no code remaining, no need to continue to use slow writes */
179
-static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
135
if (!p->first_tb) {
180
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
136
- invalidate_page_bitmap(p);
181
{
137
tlb_unprotect_code(start);
182
TCGMemOpIdx oi = l->oi;
138
}
183
TCGMemOp opc = get_memop(oi);
184
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
185
tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true);
186
/* delay slot */
187
tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
188
+ return true;
189
}
190
#endif
139
#endif
191
140
@@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_page_fast(struct page_collection *pages,
192
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
193
index XXXXXXX..XXXXXXX 100644
194
--- a/tcg/ppc/tcg-target.inc.c
195
+++ b/tcg/ppc/tcg-target.inc.c
196
@@ -XXX,XX +XXX,XX @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
197
label->label_ptr[0] = lptr;
198
}
199
200
-static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
201
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
202
{
203
TCGMemOpIdx oi = lb->oi;
204
TCGMemOp opc = get_memop(oi);
205
TCGReg hi, lo, arg = TCG_REG_R3;
206
207
- **lb->label_ptr |= reloc_pc14_val(*lb->label_ptr, s->code_ptr);
208
+ if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) {
209
+ return false;
210
+ }
211
212
tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
213
214
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
215
}
141
}
216
142
217
tcg_out_b(s, 0, lb->raddr);
143
assert_page_locked(p);
218
+ return true;
144
- if (!p->code_bitmap &&
219
}
145
- ++p->code_write_count >= SMC_BITMAP_USE_THRESHOLD) {
220
146
- build_page_bitmap(p);
221
-static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
147
- }
222
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
148
- if (p->code_bitmap) {
223
{
149
- unsigned int nr;
224
TCGMemOpIdx oi = lb->oi;
150
- unsigned long b;
225
TCGMemOp opc = get_memop(oi);
151
-
226
TCGMemOp s_bits = opc & MO_SIZE;
152
- nr = start & ~TARGET_PAGE_MASK;
227
TCGReg hi, lo, arg = TCG_REG_R3;
153
- b = p->code_bitmap[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG - 1));
228
154
- if (b & ((1 << len) - 1)) {
229
- **lb->label_ptr |= reloc_pc14_val(*lb->label_ptr, s->code_ptr);
155
- goto do_invalidate;
230
+ if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) {
156
- }
231
+ return false;
157
- } else {
232
+ }
158
- do_invalidate:
233
159
- tb_invalidate_phys_page_range__locked(pages, p, start, start + len,
234
tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
160
- retaddr);
235
161
- }
236
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
162
+ tb_invalidate_phys_page_range__locked(pages, p, start, start + len,
237
tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
163
+ retaddr);
238
239
tcg_out_b(s, 0, lb->raddr);
240
+ return true;
241
}
242
#endif /* SOFTMMU */
243
244
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
245
index XXXXXXX..XXXXXXX 100644
246
--- a/tcg/riscv/tcg-target.inc.c
247
+++ b/tcg/riscv/tcg-target.inc.c
248
@@ -XXX,XX +XXX,XX @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
249
label->label_ptr[0] = label_ptr[0];
250
}
251
252
-static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
253
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
254
{
255
TCGMemOpIdx oi = l->oi;
256
TCGMemOp opc = get_memop(oi);
257
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
258
}
259
260
/* resolve label address */
261
- patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, (intptr_t) s->code_ptr, 0);
262
+ if (!patch_reloc(l->label_ptr[0], R_RISCV_BRANCH,
263
+ (intptr_t) s->code_ptr, 0)) {
264
+ return false;
265
+ }
266
267
/* call load helper */
268
tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0);
269
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
270
tcg_out_mov(s, (opc & MO_SIZE) == MO_64, l->datalo_reg, a0);
271
272
tcg_out_goto(s, l->raddr);
273
+ return true;
274
}
275
276
-static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
277
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
278
{
279
TCGMemOpIdx oi = l->oi;
280
TCGMemOp opc = get_memop(oi);
281
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
282
}
283
284
/* resolve label address */
285
- patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, (intptr_t) s->code_ptr, 0);
286
+ if (!patch_reloc(l->label_ptr[0], R_RISCV_BRANCH,
287
+ (intptr_t) s->code_ptr, 0)) {
288
+ return false;
289
+ }
290
291
/* call store helper */
292
tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0);
293
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
294
tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SSIZE)]);
295
296
tcg_out_goto(s, l->raddr);
297
+ return true;
298
}
299
#endif /* CONFIG_SOFTMMU */
300
301
diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
302
index XXXXXXX..XXXXXXX 100644
303
--- a/tcg/s390/tcg-target.inc.c
304
+++ b/tcg/s390/tcg-target.inc.c
305
@@ -XXX,XX +XXX,XX @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
306
label->label_ptr[0] = label_ptr;
307
}
308
309
-static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
310
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
311
{
312
TCGReg addr_reg = lb->addrlo_reg;
313
TCGReg data_reg = lb->datalo_reg;
314
TCGMemOpIdx oi = lb->oi;
315
TCGMemOp opc = get_memop(oi);
316
317
- bool ok = patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
318
- (intptr_t)s->code_ptr, 2);
319
- tcg_debug_assert(ok);
320
+ if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
321
+ (intptr_t)s->code_ptr, 2)) {
322
+ return false;
323
+ }
324
325
tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0);
326
if (TARGET_LONG_BITS == 64) {
327
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
328
tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_R2);
329
330
tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr);
331
+ return true;
332
}
333
334
-static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
335
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
336
{
337
TCGReg addr_reg = lb->addrlo_reg;
338
TCGReg data_reg = lb->datalo_reg;
339
TCGMemOpIdx oi = lb->oi;
340
TCGMemOp opc = get_memop(oi);
341
342
- bool ok = patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
343
- (intptr_t)s->code_ptr, 2);
344
- tcg_debug_assert(ok);
345
+ if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
346
+ (intptr_t)s->code_ptr, 2)) {
347
+ return false;
348
+ }
349
350
tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0);
351
if (TARGET_LONG_BITS == 64) {
352
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
353
tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
354
355
tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr);
356
+ return true;
357
}
164
}
358
#else
165
#else
359
static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg,
166
/* Called with mmap_lock held. If pc is not 0 then it indicates the
360
diff --git a/tcg/tcg-ldst.inc.c b/tcg/tcg-ldst.inc.c
361
index XXXXXXX..XXXXXXX 100644
362
--- a/tcg/tcg-ldst.inc.c
363
+++ b/tcg/tcg-ldst.inc.c
364
@@ -XXX,XX +XXX,XX @@ typedef struct TCGLabelQemuLdst {
365
* Generate TB finalization at the end of block
366
*/
367
368
-static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l);
369
-static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l);
370
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l);
371
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l);
372
373
-static bool tcg_out_ldst_finalize(TCGContext *s)
374
+static int tcg_out_ldst_finalize(TCGContext *s)
375
{
376
TCGLabelQemuLdst *lb;
377
378
/* qemu_ld/st slow paths */
379
QSIMPLEQ_FOREACH(lb, &s->ldst_labels, next) {
380
- if (lb->is_ld) {
381
- tcg_out_qemu_ld_slow_path(s, lb);
382
- } else {
383
- tcg_out_qemu_st_slow_path(s, lb);
384
+ if (lb->is_ld
385
+ ? !tcg_out_qemu_ld_slow_path(s, lb)
386
+ : !tcg_out_qemu_st_slow_path(s, lb)) {
387
+ return -2;
388
}
389
390
/* Test for (pending) buffer overflow. The assumption is that any
391
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_ldst_finalize(TCGContext *s)
392
the buffer completely. Thus we can test for overflow after
393
generating code without having to check during generation. */
394
if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) {
395
- return false;
396
+ return -1;
397
}
398
}
399
- return true;
400
+ return 0;
401
}
402
403
/*
404
diff --git a/tcg/tcg.c b/tcg/tcg.c
405
index XXXXXXX..XXXXXXX 100644
406
--- a/tcg/tcg.c
407
+++ b/tcg/tcg.c
408
@@ -XXX,XX +XXX,XX @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *target);
409
static int tcg_target_const_match(tcg_target_long val, TCGType type,
410
const TCGArgConstraint *arg_ct);
411
#ifdef TCG_TARGET_NEED_LDST_LABELS
412
-static bool tcg_out_ldst_finalize(TCGContext *s);
413
+static int tcg_out_ldst_finalize(TCGContext *s);
414
#endif
415
416
#define TCG_HIGHWATER 1024
417
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
418
419
/* Generate TB finalization at the end of block */
420
#ifdef TCG_TARGET_NEED_LDST_LABELS
421
- if (!tcg_out_ldst_finalize(s)) {
422
- return -1;
423
+ i = tcg_out_ldst_finalize(s);
424
+ if (i < 0) {
425
+ return i;
426
}
427
#endif
428
#ifdef TCG_TARGET_NEED_POOL_LABELS
429
--
167
--
430
2.17.1
168
2.34.1
431
169
432
170
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/15] tcg: Hoist max_insns computation to tb_gen_code
[PULL 11/20] accel/tcg: Use bool for page_find_alloc
1
In order to handle TB's that translate to too much code, we
1
Bool is more appropriate type for the alloc parameter.
2
need to place the control of the length of the translation
3
in the hands of the code gen master loop.
4
2
5
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
6
---
9
include/exec/exec-all.h | 4 ++--
7
accel/tcg/translate-all.c | 14 +++++++-------
10
include/exec/translator.h | 3 ++-
8
1 file changed, 7 insertions(+), 7 deletions(-)
11
accel/tcg/translate-all.c | 15 +++++++++++++--
12
accel/tcg/translator.c | 15 ++-------------
13
target/alpha/translate.c | 4 ++--
14
target/arm/translate.c | 4 ++--
15
target/cris/translate.c | 10 +---------
16
target/hppa/translate.c | 5 ++---
17
target/i386/translate.c | 4 ++--
18
target/lm32/translate.c | 10 +---------
19
target/m68k/translate.c | 4 ++--
20
target/microblaze/translate.c | 10 +---------
21
target/mips/translate.c | 4 ++--
22
target/moxie/translate.c | 11 ++---------
23
target/nios2/translate.c | 14 ++------------
24
target/openrisc/translate.c | 4 ++--
25
target/ppc/translate.c | 4 ++--
26
target/riscv/translate.c | 4 ++--
27
target/s390x/translate.c | 4 ++--
28
target/sh4/translate.c | 4 ++--
29
target/sparc/translate.c | 4 ++--
30
target/tilegx/translate.c | 12 +-----------
31
target/tricore/translate.c | 16 ++--------------
32
target/unicore32/translate.c | 10 +---------
33
target/xtensa/translate.c | 4 ++--
34
25 files changed, 56 insertions(+), 127 deletions(-)
35
9
36
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/include/exec/exec-all.h
39
+++ b/include/exec/exec-all.h
40
@@ -XXX,XX +XXX,XX @@ typedef ram_addr_t tb_page_addr_t;
41
42
#include "qemu/log.h"
43
44
-void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb);
45
-void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
46
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns);
47
+void restore_state_to_opc(CPUArchState *env, TranslationBlock *tb,
48
target_ulong *data);
49
50
void cpu_gen_init(void);
51
diff --git a/include/exec/translator.h b/include/exec/translator.h
52
index XXXXXXX..XXXXXXX 100644
53
--- a/include/exec/translator.h
54
+++ b/include/exec/translator.h
55
@@ -XXX,XX +XXX,XX @@ typedef struct TranslatorOps {
56
* @db: Disassembly context.
57
* @cpu: Target vCPU.
58
* @tb: Translation block.
59
+ * @max_insns: Maximum number of insns to translate.
60
*
61
* Generic translator loop.
62
*
63
@@ -XXX,XX +XXX,XX @@ typedef struct TranslatorOps {
64
* - When too many instructions have been translated.
65
*/
66
void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
67
- CPUState *cpu, TranslationBlock *tb);
68
+ CPUState *cpu, TranslationBlock *tb, int max_insns);
69
70
void translator_loop_temp_check(DisasContextBase *db);
71
72
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
10
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
73
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
74
--- a/accel/tcg/translate-all.c
12
--- a/accel/tcg/translate-all.c
75
+++ b/accel/tcg/translate-all.c
13
+++ b/accel/tcg/translate-all.c
76
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
14
@@ -XXX,XX +XXX,XX @@ void page_init(void)
77
tb_page_addr_t phys_pc, phys_page2;
15
#endif
78
target_ulong virt_page2;
79
tcg_insn_unit *gen_code_buf;
80
- int gen_code_size, search_size;
81
+ int gen_code_size, search_size, max_insns;
82
#ifdef CONFIG_PROFILER
83
TCGProfile *prof = &tcg_ctx->prof;
84
int64_t ti;
85
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
86
cflags &= ~CF_CLUSTER_MASK;
87
cflags |= cpu->cluster_index << CF_CLUSTER_SHIFT;
88
89
+ max_insns = cflags & CF_COUNT_MASK;
90
+ if (max_insns == 0) {
91
+ max_insns = CF_COUNT_MASK;
92
+ }
93
+ if (max_insns > TCG_MAX_INSNS) {
94
+ max_insns = TCG_MAX_INSNS;
95
+ }
96
+ if (cpu->singlestep_enabled || singlestep) {
97
+ max_insns = 1;
98
+ }
99
+
100
buffer_overflow:
101
tb = tb_alloc(pc);
102
if (unlikely(!tb)) {
103
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
104
tcg_func_start(tcg_ctx);
105
106
tcg_ctx->cpu = ENV_GET_CPU(env);
107
- gen_intermediate_code(cpu, tb);
108
+ gen_intermediate_code(cpu, tb, max_insns);
109
tcg_ctx->cpu = NULL;
110
111
trace_translate_block(tb, tb->pc, tb->tc.ptr);
112
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
113
index XXXXXXX..XXXXXXX 100644
114
--- a/accel/tcg/translator.c
115
+++ b/accel/tcg/translator.c
116
@@ -XXX,XX +XXX,XX @@ void translator_loop_temp_check(DisasContextBase *db)
117
}
16
}
118
17
119
void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
18
-static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc)
120
- CPUState *cpu, TranslationBlock *tb)
19
+static PageDesc *page_find_alloc(tb_page_addr_t index, bool alloc)
121
+ CPUState *cpu, TranslationBlock *tb, int max_insns)
122
{
20
{
123
int bp_insn = 0;
21
PageDesc *pd;
124
22
void **lp;
125
@@ -XXX,XX +XXX,XX @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
23
@@ -XXX,XX +XXX,XX @@ static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc)
126
db->pc_next = db->pc_first;
24
127
db->is_jmp = DISAS_NEXT;
25
static inline PageDesc *page_find(tb_page_addr_t index)
128
db->num_insns = 0;
129
+ db->max_insns = max_insns;
130
db->singlestep_enabled = cpu->singlestep_enabled;
131
132
- /* Instruction counting */
133
- db->max_insns = tb_cflags(db->tb) & CF_COUNT_MASK;
134
- if (db->max_insns == 0) {
135
- db->max_insns = CF_COUNT_MASK;
136
- }
137
- if (db->max_insns > TCG_MAX_INSNS) {
138
- db->max_insns = TCG_MAX_INSNS;
139
- }
140
- if (db->singlestep_enabled || singlestep) {
141
- db->max_insns = 1;
142
- }
143
-
144
ops->init_disas_context(db, cpu);
145
tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */
146
147
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
148
index XXXXXXX..XXXXXXX 100644
149
--- a/target/alpha/translate.c
150
+++ b/target/alpha/translate.c
151
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps alpha_tr_ops = {
152
.disas_log = alpha_tr_disas_log,
153
};
154
155
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
156
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
157
{
26
{
158
DisasContext dc;
27
- return page_find_alloc(index, 0);
159
- translator_loop(&alpha_tr_ops, &dc.base, cpu, tb);
28
+ return page_find_alloc(index, false);
160
+ translator_loop(&alpha_tr_ops, &dc.base, cpu, tb, max_insns);
161
}
29
}
162
30
163
void restore_state_to_opc(CPUAlphaState *env, TranslationBlock *tb,
31
static void page_lock_pair(PageDesc **ret_p1, tb_page_addr_t phys1,
164
diff --git a/target/arm/translate.c b/target/arm/translate.c
32
- PageDesc **ret_p2, tb_page_addr_t phys2, int alloc);
165
index XXXXXXX..XXXXXXX 100644
33
+ PageDesc **ret_p2, tb_page_addr_t phys2, bool alloc);
166
--- a/target/arm/translate.c
34
167
+++ b/target/arm/translate.c
35
/* In user-mode page locks aren't used; mmap_lock is enough */
168
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps thumb_translator_ops = {
36
#ifdef CONFIG_USER_ONLY
169
};
37
@@ -XXX,XX +XXX,XX @@ static inline void page_unlock(PageDesc *pd)
170
38
/* lock the page(s) of a TB in the correct acquisition order */
171
/* generate intermediate code for basic block 'tb'. */
39
static inline void page_lock_tb(const TranslationBlock *tb)
172
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
173
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
174
{
40
{
175
DisasContext dc;
41
- page_lock_pair(NULL, tb->page_addr[0], NULL, tb->page_addr[1], 0);
176
const TranslatorOps *ops = &arm_translator_ops;
42
+ page_lock_pair(NULL, tb->page_addr[0], NULL, tb->page_addr[1], false);
177
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
178
}
179
#endif
180
181
- translator_loop(ops, &dc.base, cpu, tb);
182
+ translator_loop(ops, &dc.base, cpu, tb, max_insns);
183
}
43
}
184
44
185
void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
45
static inline void page_unlock_tb(const TranslationBlock *tb)
186
diff --git a/target/cris/translate.c b/target/cris/translate.c
46
@@ -XXX,XX +XXX,XX @@ void page_collection_unlock(struct page_collection *set)
187
index XXXXXXX..XXXXXXX 100644
47
#endif /* !CONFIG_USER_ONLY */
188
--- a/target/cris/translate.c
48
189
+++ b/target/cris/translate.c
49
static void page_lock_pair(PageDesc **ret_p1, tb_page_addr_t phys1,
190
@@ -XXX,XX +XXX,XX @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
50
- PageDesc **ret_p2, tb_page_addr_t phys2, int alloc)
191
*/
51
+ PageDesc **ret_p2, tb_page_addr_t phys2, bool alloc)
192
193
/* generate intermediate code for basic block 'tb'. */
194
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
195
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
196
{
52
{
197
CPUCRISState *env = cs->env_ptr;
53
PageDesc *p1, *p2;
198
uint32_t pc_start;
54
tb_page_addr_t page1;
199
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
55
@@ -XXX,XX +XXX,XX @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
200
uint32_t page_start;
56
* Note that inserting into the hash table first isn't an option, since
201
target_ulong npc;
57
* we can only insert TBs that are fully initialized.
202
int num_insns;
58
*/
203
- int max_insns;
59
- page_lock_pair(&p, phys_pc, &p2, phys_page2, 1);
204
60
+ page_lock_pair(&p, phys_pc, &p2, phys_page2, true);
205
if (env->pregs[PR_VR] == 32) {
61
tb_page_add(p, tb, 0, phys_pc & TARGET_PAGE_MASK);
206
dc->decoder = crisv32_decoder;
62
if (p2) {
207
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
63
tb_page_add(p2, tb, 1, phys_page2);
208
64
@@ -XXX,XX +XXX,XX @@ void page_set_flags(target_ulong start, target_ulong end, int flags)
209
page_start = pc_start & TARGET_PAGE_MASK;
65
for (addr = start, len = end - start;
210
num_insns = 0;
66
len != 0;
211
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
67
len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) {
212
- if (max_insns == 0) {
68
- PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, 1);
213
- max_insns = CF_COUNT_MASK;
69
+ PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, true);
214
- }
70
215
- if (max_insns > TCG_MAX_INSNS) {
71
/* If the write protection bit is set, then we invalidate
216
- max_insns = TCG_MAX_INSNS;
72
the code inside. */
217
- }
218
219
gen_tb_start(tb);
220
do {
221
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
222
index XXXXXXX..XXXXXXX 100644
223
--- a/target/hppa/translate.c
224
+++ b/target/hppa/translate.c
225
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps hppa_tr_ops = {
226
.disas_log = hppa_tr_disas_log,
227
};
228
229
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
230
-
231
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
232
{
233
DisasContext ctx;
234
- translator_loop(&hppa_tr_ops, &ctx.base, cs, tb);
235
+ translator_loop(&hppa_tr_ops, &ctx.base, cs, tb, max_insns);
236
}
237
238
void restore_state_to_opc(CPUHPPAState *env, TranslationBlock *tb,
239
diff --git a/target/i386/translate.c b/target/i386/translate.c
240
index XXXXXXX..XXXXXXX 100644
241
--- a/target/i386/translate.c
242
+++ b/target/i386/translate.c
243
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps i386_tr_ops = {
244
};
245
246
/* generate intermediate code for basic block 'tb'. */
247
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
248
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
249
{
250
DisasContext dc;
251
252
- translator_loop(&i386_tr_ops, &dc.base, cpu, tb);
253
+ translator_loop(&i386_tr_ops, &dc.base, cpu, tb, max_insns);
254
}
255
256
void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb,
257
diff --git a/target/lm32/translate.c b/target/lm32/translate.c
258
index XXXXXXX..XXXXXXX 100644
259
--- a/target/lm32/translate.c
260
+++ b/target/lm32/translate.c
261
@@ -XXX,XX +XXX,XX @@ static inline void decode(DisasContext *dc, uint32_t ir)
262
}
263
264
/* generate intermediate code for basic block 'tb'. */
265
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
266
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
267
{
268
CPULM32State *env = cs->env_ptr;
269
LM32CPU *cpu = lm32_env_get_cpu(env);
270
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
271
uint32_t pc_start;
272
uint32_t page_start;
273
int num_insns;
274
- int max_insns;
275
276
pc_start = tb->pc;
277
dc->features = cpu->features;
278
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
279
280
page_start = pc_start & TARGET_PAGE_MASK;
281
num_insns = 0;
282
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
283
- if (max_insns == 0) {
284
- max_insns = CF_COUNT_MASK;
285
- }
286
- if (max_insns > TCG_MAX_INSNS) {
287
- max_insns = TCG_MAX_INSNS;
288
- }
289
290
gen_tb_start(tb);
291
do {
292
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
293
index XXXXXXX..XXXXXXX 100644
294
--- a/target/m68k/translate.c
295
+++ b/target/m68k/translate.c
296
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps m68k_tr_ops = {
297
.disas_log = m68k_tr_disas_log,
298
};
299
300
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
301
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
302
{
303
DisasContext dc;
304
- translator_loop(&m68k_tr_ops, &dc.base, cpu, tb);
305
+ translator_loop(&m68k_tr_ops, &dc.base, cpu, tb, max_insns);
306
}
307
308
static double floatx80_to_double(CPUM68KState *env, uint16_t high, uint64_t low)
309
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
310
index XXXXXXX..XXXXXXX 100644
311
--- a/target/microblaze/translate.c
312
+++ b/target/microblaze/translate.c
313
@@ -XXX,XX +XXX,XX @@ static inline void decode(DisasContext *dc, uint32_t ir)
314
}
315
316
/* generate intermediate code for basic block 'tb'. */
317
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
318
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
319
{
320
CPUMBState *env = cs->env_ptr;
321
MicroBlazeCPU *cpu = mb_env_get_cpu(env);
322
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
323
uint32_t page_start, org_flags;
324
uint32_t npc;
325
int num_insns;
326
- int max_insns;
327
328
pc_start = tb->pc;
329
dc->cpu = cpu;
330
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
331
332
page_start = pc_start & TARGET_PAGE_MASK;
333
num_insns = 0;
334
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
335
- if (max_insns == 0) {
336
- max_insns = CF_COUNT_MASK;
337
- }
338
- if (max_insns > TCG_MAX_INSNS) {
339
- max_insns = TCG_MAX_INSNS;
340
- }
341
342
gen_tb_start(tb);
343
do
344
diff --git a/target/mips/translate.c b/target/mips/translate.c
345
index XXXXXXX..XXXXXXX 100644
346
--- a/target/mips/translate.c
347
+++ b/target/mips/translate.c
348
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps mips_tr_ops = {
349
.disas_log = mips_tr_disas_log,
350
};
351
352
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
353
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
354
{
355
DisasContext ctx;
356
357
- translator_loop(&mips_tr_ops, &ctx.base, cs, tb);
358
+ translator_loop(&mips_tr_ops, &ctx.base, cs, tb, max_insns);
359
}
360
361
static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags)
362
diff --git a/target/moxie/translate.c b/target/moxie/translate.c
363
index XXXXXXX..XXXXXXX 100644
364
--- a/target/moxie/translate.c
365
+++ b/target/moxie/translate.c
366
@@ -XXX,XX +XXX,XX @@ static int decode_opc(MoxieCPU *cpu, DisasContext *ctx)
367
}
368
369
/* generate intermediate code for basic block 'tb'. */
370
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
371
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
372
{
373
CPUMoxieState *env = cs->env_ptr;
374
MoxieCPU *cpu = moxie_env_get_cpu(env);
375
DisasContext ctx;
376
target_ulong pc_start;
377
- int num_insns, max_insns;
378
+ int num_insns;
379
380
pc_start = tb->pc;
381
ctx.pc = pc_start;
382
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
383
ctx.singlestep_enabled = 0;
384
ctx.bstate = BS_NONE;
385
num_insns = 0;
386
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
387
- if (max_insns == 0) {
388
- max_insns = CF_COUNT_MASK;
389
- }
390
- if (max_insns > TCG_MAX_INSNS) {
391
- max_insns = TCG_MAX_INSNS;
392
- }
393
394
gen_tb_start(tb);
395
do {
396
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
397
index XXXXXXX..XXXXXXX 100644
398
--- a/target/nios2/translate.c
399
+++ b/target/nios2/translate.c
400
@@ -XXX,XX +XXX,XX @@ static void gen_exception(DisasContext *dc, uint32_t excp)
401
}
402
403
/* generate intermediate code for basic block 'tb'. */
404
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
405
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
406
{
407
CPUNios2State *env = cs->env_ptr;
408
DisasContext dc1, *dc = &dc1;
409
int num_insns;
410
- int max_insns;
411
412
/* Initialize DC */
413
dc->cpu_env = cpu_env;
414
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
415
416
/* Set up instruction counts */
417
num_insns = 0;
418
- if (cs->singlestep_enabled || singlestep) {
419
- max_insns = 1;
420
- } else {
421
+ if (max_insns > 1) {
422
int page_insns = (TARGET_PAGE_SIZE - (tb->pc & TARGET_PAGE_MASK)) / 4;
423
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
424
- if (max_insns == 0) {
425
- max_insns = CF_COUNT_MASK;
426
- }
427
if (max_insns > page_insns) {
428
max_insns = page_insns;
429
}
430
- if (max_insns > TCG_MAX_INSNS) {
431
- max_insns = TCG_MAX_INSNS;
432
- }
433
}
434
435
gen_tb_start(tb);
436
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
437
index XXXXXXX..XXXXXXX 100644
438
--- a/target/openrisc/translate.c
439
+++ b/target/openrisc/translate.c
440
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps openrisc_tr_ops = {
441
.disas_log = openrisc_tr_disas_log,
442
};
443
444
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
445
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
446
{
447
DisasContext ctx;
448
449
- translator_loop(&openrisc_tr_ops, &ctx.base, cs, tb);
450
+ translator_loop(&openrisc_tr_ops, &ctx.base, cs, tb, max_insns);
451
}
452
453
void openrisc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
454
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
455
index XXXXXXX..XXXXXXX 100644
456
--- a/target/ppc/translate.c
457
+++ b/target/ppc/translate.c
458
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps ppc_tr_ops = {
459
.disas_log = ppc_tr_disas_log,
460
};
461
462
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
463
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
464
{
465
DisasContext ctx;
466
467
- translator_loop(&ppc_tr_ops, &ctx.base, cs, tb);
468
+ translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns);
469
}
470
471
void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
472
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
473
index XXXXXXX..XXXXXXX 100644
474
--- a/target/riscv/translate.c
475
+++ b/target/riscv/translate.c
476
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps riscv_tr_ops = {
477
.disas_log = riscv_tr_disas_log,
478
};
479
480
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
481
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
482
{
483
DisasContext ctx;
484
485
- translator_loop(&riscv_tr_ops, &ctx.base, cs, tb);
486
+ translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns);
487
}
488
489
void riscv_translate_init(void)
490
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
491
index XXXXXXX..XXXXXXX 100644
492
--- a/target/s390x/translate.c
493
+++ b/target/s390x/translate.c
494
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps s390x_tr_ops = {
495
.disas_log = s390x_tr_disas_log,
496
};
497
498
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
499
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
500
{
501
DisasContext dc;
502
503
- translator_loop(&s390x_tr_ops, &dc.base, cs, tb);
504
+ translator_loop(&s390x_tr_ops, &dc.base, cs, tb, max_insns);
505
}
506
507
void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb,
508
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
509
index XXXXXXX..XXXXXXX 100644
510
--- a/target/sh4/translate.c
511
+++ b/target/sh4/translate.c
512
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps sh4_tr_ops = {
513
.disas_log = sh4_tr_disas_log,
514
};
515
516
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
517
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
518
{
519
DisasContext ctx;
520
521
- translator_loop(&sh4_tr_ops, &ctx.base, cs, tb);
522
+ translator_loop(&sh4_tr_ops, &ctx.base, cs, tb, max_insns);
523
}
524
525
void restore_state_to_opc(CPUSH4State *env, TranslationBlock *tb,
526
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
527
index XXXXXXX..XXXXXXX 100644
528
--- a/target/sparc/translate.c
529
+++ b/target/sparc/translate.c
530
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps sparc_tr_ops = {
531
.disas_log = sparc_tr_disas_log,
532
};
533
534
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
535
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
536
{
537
DisasContext dc = {};
538
539
- translator_loop(&sparc_tr_ops, &dc.base, cs, tb);
540
+ translator_loop(&sparc_tr_ops, &dc.base, cs, tb, max_insns);
541
}
542
543
void sparc_tcg_init(void)
544
diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c
545
index XXXXXXX..XXXXXXX 100644
546
--- a/target/tilegx/translate.c
547
+++ b/target/tilegx/translate.c
548
@@ -XXX,XX +XXX,XX @@ static void translate_one_bundle(DisasContext *dc, uint64_t bundle)
549
}
550
}
551
552
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
553
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
554
{
555
CPUTLGState *env = cs->env_ptr;
556
DisasContext ctx;
557
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
558
uint64_t pc_start = tb->pc;
559
uint64_t page_start = pc_start & TARGET_PAGE_MASK;
560
int num_insns = 0;
561
- int max_insns = tb_cflags(tb) & CF_COUNT_MASK;
562
563
dc->pc = pc_start;
564
dc->mmuidx = 0;
565
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
566
qemu_log_lock();
567
qemu_log("IN: %s\n", lookup_symbol(pc_start));
568
}
569
- if (!max_insns) {
570
- max_insns = CF_COUNT_MASK;
571
- }
572
- if (cs->singlestep_enabled || singlestep) {
573
- max_insns = 1;
574
- }
575
- if (max_insns > TCG_MAX_INSNS) {
576
- max_insns = TCG_MAX_INSNS;
577
- }
578
gen_tb_start(tb);
579
580
while (1) {
581
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
582
index XXXXXXX..XXXXXXX 100644
583
--- a/target/tricore/translate.c
584
+++ b/target/tricore/translate.c
585
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch)
586
}
587
}
588
589
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
590
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
591
{
592
CPUTriCoreState *env = cs->env_ptr;
593
DisasContext ctx;
594
target_ulong pc_start;
595
- int num_insns, max_insns;
596
-
597
- num_insns = 0;
598
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
599
- if (max_insns == 0) {
600
- max_insns = CF_COUNT_MASK;
601
- }
602
- if (singlestep) {
603
- max_insns = 1;
604
- }
605
- if (max_insns > TCG_MAX_INSNS) {
606
- max_insns = TCG_MAX_INSNS;
607
- }
608
+ int num_insns = 0;
609
610
pc_start = tb->pc;
611
ctx.pc = pc_start;
612
diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c
613
index XXXXXXX..XXXXXXX 100644
614
--- a/target/unicore32/translate.c
615
+++ b/target/unicore32/translate.c
616
@@ -XXX,XX +XXX,XX @@ static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
617
}
618
619
/* generate intermediate code for basic block 'tb'. */
620
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
621
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
622
{
623
CPUUniCore32State *env = cs->env_ptr;
624
DisasContext dc1, *dc = &dc1;
625
target_ulong pc_start;
626
uint32_t page_start;
627
int num_insns;
628
- int max_insns;
629
630
/* generate intermediate code */
631
num_temps = 0;
632
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
633
cpu_F1d = tcg_temp_new_i64();
634
page_start = pc_start & TARGET_PAGE_MASK;
635
num_insns = 0;
636
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
637
- if (max_insns == 0) {
638
- max_insns = CF_COUNT_MASK;
639
- }
640
- if (max_insns > TCG_MAX_INSNS) {
641
- max_insns = TCG_MAX_INSNS;
642
- }
643
644
#ifndef CONFIG_USER_ONLY
645
if ((env->uncached_asr & ASR_M) == ASR_MODE_USER) {
646
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
647
index XXXXXXX..XXXXXXX 100644
648
--- a/target/xtensa/translate.c
649
+++ b/target/xtensa/translate.c
650
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps xtensa_translator_ops = {
651
.disas_log = xtensa_tr_disas_log,
652
};
653
654
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
655
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
656
{
657
DisasContext dc = {};
658
- translator_loop(&xtensa_translator_ops, &dc.base, cpu, tb);
659
+ translator_loop(&xtensa_translator_ops, &dc.base, cpu, tb, max_insns);
660
}
661
662
void xtensa_cpu_dump_state(CPUState *cs, FILE *f, int flags)
663
--
73
--
664
2.17.1
74
2.34.1
665
75
666
76
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/15] tcg/arm: Restrict constant pool displacement to 12 bits
[PULL 12/20] accel/tcg: Use DisasContextBase in plugin_gen_tb_start
1
This will not necessarily restrict the size of the TB, since for v7
1
Use the pc coming from db->pc_first rather than the TB.
2
the majority of constant pool usage is for calls from the out-of-line
3
ldst code, which is already at the end of the TB. But this does
4
allow us to save one insn per reference on the off-chance.
5
2
3
Use the cached host_addr rather than re-computing for the
4
first page. We still need a separate lookup for the second
5
page because it won't be computed for DisasContextBase until
6
the translator actually performs a read from the page.
7
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
10
---
8
tcg/arm/tcg-target.inc.c | 57 +++++++++++++++-------------------------
11
include/exec/plugin-gen.h | 7 ++++---
9
1 file changed, 21 insertions(+), 36 deletions(-)
12
accel/tcg/plugin-gen.c | 22 +++++++++++-----------
13
accel/tcg/translator.c | 2 +-
14
3 files changed, 16 insertions(+), 15 deletions(-)
10
15
11
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
16
diff --git a/include/exec/plugin-gen.h b/include/exec/plugin-gen.h
12
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/arm/tcg-target.inc.c
18
--- a/include/exec/plugin-gen.h
14
+++ b/tcg/arm/tcg-target.inc.c
19
+++ b/include/exec/plugin-gen.h
15
@@ -XXX,XX +XXX,XX @@ static inline bool reloc_pc24(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
20
@@ -XXX,XX +XXX,XX @@ struct DisasContextBase;
21
22
#ifdef CONFIG_PLUGIN
23
24
-bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool supress);
25
+bool plugin_gen_tb_start(CPUState *cpu, const struct DisasContextBase *db,
26
+ bool supress);
27
void plugin_gen_tb_end(CPUState *cpu);
28
void plugin_gen_insn_start(CPUState *cpu, const struct DisasContextBase *db);
29
void plugin_gen_insn_end(void);
30
@@ -XXX,XX +XXX,XX @@ static inline void plugin_insn_append(abi_ptr pc, const void *from, size_t size)
31
32
#else /* !CONFIG_PLUGIN */
33
34
-static inline
35
-bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool supress)
36
+static inline bool
37
+plugin_gen_tb_start(CPUState *cpu, const struct DisasContextBase *db, bool sup)
38
{
16
return false;
39
return false;
17
}
40
}
18
41
diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c
19
+static inline bool reloc_pc13(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
42
index XXXXXXX..XXXXXXX 100644
20
+{
43
--- a/accel/tcg/plugin-gen.c
21
+ ptrdiff_t offset = tcg_ptr_byte_diff(target, code_ptr) - 8;
44
+++ b/accel/tcg/plugin-gen.c
22
+
45
@@ -XXX,XX +XXX,XX @@ static void plugin_gen_inject(const struct qemu_plugin_tb *plugin_tb)
23
+ if (offset >= -0xfff && offset <= 0xfff) {
46
pr_ops();
24
+ tcg_insn_unit insn = *code_ptr;
47
}
25
+ bool u = (offset >= 0);
48
26
+ if (!u) {
49
-bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool mem_only)
27
+ offset = -offset;
50
+bool plugin_gen_tb_start(CPUState *cpu, const DisasContextBase *db,
51
+ bool mem_only)
52
{
53
bool ret = false;
54
55
@@ -XXX,XX +XXX,XX @@ bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool mem_onl
56
57
ret = true;
58
59
- ptb->vaddr = tb->pc;
60
+ ptb->vaddr = db->pc_first;
61
ptb->vaddr2 = -1;
62
- get_page_addr_code_hostp(cpu->env_ptr, tb->pc, &ptb->haddr1);
63
+ ptb->haddr1 = db->host_addr[0];
64
ptb->haddr2 = NULL;
65
ptb->mem_only = mem_only;
66
67
@@ -XXX,XX +XXX,XX @@ void plugin_gen_insn_start(CPUState *cpu, const DisasContextBase *db)
68
* Note that we skip this when haddr1 == NULL, e.g. when we're
69
* fetching instructions from a region not backed by RAM.
70
*/
71
- if (likely(ptb->haddr1 != NULL && ptb->vaddr2 == -1) &&
72
- unlikely((db->pc_next & TARGET_PAGE_MASK) !=
73
- (db->pc_first & TARGET_PAGE_MASK))) {
74
- get_page_addr_code_hostp(cpu->env_ptr, db->pc_next,
75
- &ptb->haddr2);
76
- ptb->vaddr2 = db->pc_next;
77
- }
78
- if (likely(ptb->vaddr2 == -1)) {
79
+ if (ptb->haddr1 == NULL) {
80
+ pinsn->haddr = NULL;
81
+ } else if (is_same_page(db, db->pc_next)) {
82
pinsn->haddr = ptb->haddr1 + pinsn->vaddr - ptb->vaddr;
83
} else {
84
+ if (ptb->vaddr2 == -1) {
85
+ ptb->vaddr2 = TARGET_PAGE_ALIGN(db->pc_first);
86
+ get_page_addr_code_hostp(cpu->env_ptr, ptb->vaddr2, &ptb->haddr2);
28
+ }
87
+ }
29
+ insn = deposit32(insn, 23, 1, u);
88
pinsn->haddr = ptb->haddr2 + pinsn->vaddr - ptb->vaddr2;
30
+ insn = deposit32(insn, 0, 12, offset);
31
+ *code_ptr = insn;
32
+ return true;
33
+ }
34
+ return false;
35
+}
36
+
37
static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
38
intptr_t value, intptr_t addend)
39
{
40
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
41
if (type == R_ARM_PC24) {
42
return reloc_pc24(code_ptr, (tcg_insn_unit *)value);
43
} else if (type == R_ARM_PC13) {
44
- intptr_t diff = value - (uintptr_t)(code_ptr + 2);
45
- tcg_insn_unit insn = *code_ptr;
46
- bool u;
47
-
48
- if (diff >= -0xfff && diff <= 0xfff) {
49
- u = (diff >= 0);
50
- if (!u) {
51
- diff = -diff;
52
- }
53
- } else {
54
- int rd = extract32(insn, 12, 4);
55
- int rt = rd == TCG_REG_PC ? TCG_REG_TMP : rd;
56
-
57
- if (diff < 0x1000 || diff >= 0x100000) {
58
- return false;
59
- }
60
-
61
- /* add rt, pc, #high */
62
- *code_ptr++ = ((insn & 0xf0000000) | (1 << 25) | ARITH_ADD
63
- | (TCG_REG_PC << 16) | (rt << 12)
64
- | (20 << 7) | (diff >> 12));
65
- /* ldr rd, [rt, #low] */
66
- insn = deposit32(insn, 12, 4, rt);
67
- diff &= 0xfff;
68
- u = 1;
69
- }
70
- insn = deposit32(insn, 23, 1, u);
71
- insn = deposit32(insn, 0, 12, diff);
72
- *code_ptr = insn;
73
+ return reloc_pc13(code_ptr, (tcg_insn_unit *)value);
74
} else {
75
g_assert_not_reached();
76
}
77
- return true;
78
}
79
80
#define TCG_CT_CONST_ARM 0x100
81
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_ld8s_r(TCGContext *s, int cond, TCGReg rt,
82
83
static void tcg_out_movi_pool(TCGContext *s, int cond, int rd, uint32_t arg)
84
{
85
- /* The 12-bit range on the ldr insn is sometimes a bit too small.
86
- In order to get around that we require two insns, one of which
87
- will usually be a nop, but may be replaced in patch_reloc. */
88
new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0);
89
tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0);
90
- tcg_out_nop(s);
91
}
92
93
static void tcg_out_movi32(TCGContext *s, int cond, int rd, uint32_t arg)
94
@@ -XXX,XX +XXX,XX @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *addr)
95
tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri);
96
tcg_out_blx(s, COND_AL, TCG_REG_TMP);
97
} else {
98
- /* ??? Know that movi_pool emits exactly 2 insns. */
99
- tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 4);
100
+ /* ??? Know that movi_pool emits exactly 1 insn. */
101
+ tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 0);
102
tcg_out_movi_pool(s, COND_AL, TCG_REG_PC, addri);
103
}
89
}
104
}
90
}
91
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
92
index XXXXXXX..XXXXXXX 100644
93
--- a/accel/tcg/translator.c
94
+++ b/accel/tcg/translator.c
95
@@ -XXX,XX +XXX,XX @@ void translator_loop(CPUState *cpu, TranslationBlock *tb, int max_insns,
96
ops->tb_start(db, cpu);
97
tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */
98
99
- plugin_enabled = plugin_gen_tb_start(cpu, tb, cflags & CF_MEMI_ONLY);
100
+ plugin_enabled = plugin_gen_tb_start(cpu, db, cflags & CF_MEMI_ONLY);
101
102
while (true) {
103
db->num_insns++;
105
--
104
--
106
2.17.1
105
2.34.1
107
106
108
107
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/15] tcg: Add INDEX_op_extract2_{i32,i64}
[PULL 13/20] accel/tcg: Do not align tb->page_addr[0]
1
This will let backends implement the double-word shift operation.
1
Let tb->page_addr[0] contain the address of the first byte of the
2
translated block, rather than the address of the page containing the
3
start of the translated block. We need to recover this value anyway
4
at various points, and it is easier to discard a page offset when it
5
is not needed, which happens naturally via the existing find_page shift.
2
6
3
Reviewed-by: David Hildenbrand <david@redhat.com>
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
9
---
6
tcg/aarch64/tcg-target.h | 2 ++
10
accel/tcg/cpu-exec.c | 16 ++++++++--------
7
tcg/arm/tcg-target.h | 1 +
11
accel/tcg/cputlb.c | 3 ++-
8
tcg/i386/tcg-target.h | 2 ++
12
accel/tcg/translate-all.c | 9 +++++----
9
tcg/mips/tcg-target.h | 2 ++
13
3 files changed, 15 insertions(+), 13 deletions(-)
10
tcg/ppc/tcg-target.h | 2 ++
11
tcg/riscv/tcg-target.h | 2 ++
12
tcg/s390/tcg-target.h | 2 ++
13
tcg/sparc/tcg-target.h | 2 ++
14
tcg/tcg-opc.h | 2 ++
15
tcg/tcg.h | 1 +
16
tcg/tci/tcg-target.h | 2 ++
17
tcg/optimize.c | 16 ++++++++++++++++
18
tcg/tcg-op.c | 4 ++++
19
tcg/tcg.c | 4 ++++
20
tcg/README | 7 +++++++
21
15 files changed, 51 insertions(+)
22
14
23
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
15
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
24
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
25
--- a/tcg/aarch64/tcg-target.h
17
--- a/accel/tcg/cpu-exec.c
26
+++ b/tcg/aarch64/tcg-target.h
18
+++ b/accel/tcg/cpu-exec.c
27
@@ -XXX,XX +XXX,XX @@ typedef enum {
19
@@ -XXX,XX +XXX,XX @@ struct tb_desc {
28
#define TCG_TARGET_HAS_deposit_i32 1
20
target_ulong pc;
29
#define TCG_TARGET_HAS_extract_i32 1
21
target_ulong cs_base;
30
#define TCG_TARGET_HAS_sextract_i32 1
22
CPUArchState *env;
31
+#define TCG_TARGET_HAS_extract2_i32 0
23
- tb_page_addr_t phys_page1;
32
#define TCG_TARGET_HAS_movcond_i32 1
24
+ tb_page_addr_t page_addr0;
33
#define TCG_TARGET_HAS_add2_i32 1
25
uint32_t flags;
34
#define TCG_TARGET_HAS_sub2_i32 1
26
uint32_t cflags;
35
@@ -XXX,XX +XXX,XX @@ typedef enum {
27
uint32_t trace_vcpu_dstate;
36
#define TCG_TARGET_HAS_deposit_i64 1
28
@@ -XXX,XX +XXX,XX @@ static bool tb_lookup_cmp(const void *p, const void *d)
37
#define TCG_TARGET_HAS_extract_i64 1
29
const struct tb_desc *desc = d;
38
#define TCG_TARGET_HAS_sextract_i64 1
30
39
+#define TCG_TARGET_HAS_extract2_i64 0
31
if (tb->pc == desc->pc &&
40
#define TCG_TARGET_HAS_movcond_i64 1
32
- tb->page_addr[0] == desc->phys_page1 &&
41
#define TCG_TARGET_HAS_add2_i64 1
33
+ tb->page_addr[0] == desc->page_addr0 &&
42
#define TCG_TARGET_HAS_sub2_i64 1
34
tb->cs_base == desc->cs_base &&
43
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
35
tb->flags == desc->flags &&
36
tb->trace_vcpu_dstate == desc->trace_vcpu_dstate &&
37
@@ -XXX,XX +XXX,XX @@ static bool tb_lookup_cmp(const void *p, const void *d)
38
if (tb->page_addr[1] == -1) {
39
return true;
40
} else {
41
- tb_page_addr_t phys_page2;
42
- target_ulong virt_page2;
43
+ tb_page_addr_t phys_page1;
44
+ target_ulong virt_page1;
45
46
/*
47
* We know that the first page matched, and an otherwise valid TB
48
@@ -XXX,XX +XXX,XX @@ static bool tb_lookup_cmp(const void *p, const void *d)
49
* is different for the new TB. Therefore any exception raised
50
* here by the faulting lookup is not premature.
51
*/
52
- virt_page2 = TARGET_PAGE_ALIGN(desc->pc);
53
- phys_page2 = get_page_addr_code(desc->env, virt_page2);
54
- if (tb->page_addr[1] == phys_page2) {
55
+ virt_page1 = TARGET_PAGE_ALIGN(desc->pc);
56
+ phys_page1 = get_page_addr_code(desc->env, virt_page1);
57
+ if (tb->page_addr[1] == phys_page1) {
58
return true;
59
}
60
}
61
@@ -XXX,XX +XXX,XX @@ static TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
62
if (phys_pc == -1) {
63
return NULL;
64
}
65
- desc.phys_page1 = phys_pc & TARGET_PAGE_MASK;
66
+ desc.page_addr0 = phys_pc;
67
h = tb_hash_func(phys_pc, pc, flags, cflags, *cpu->trace_dstate);
68
return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp);
69
}
70
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
44
index XXXXXXX..XXXXXXX 100644
71
index XXXXXXX..XXXXXXX 100644
45
--- a/tcg/arm/tcg-target.h
72
--- a/accel/tcg/cputlb.c
46
+++ b/tcg/arm/tcg-target.h
73
+++ b/accel/tcg/cputlb.c
47
@@ -XXX,XX +XXX,XX @@ extern bool use_idiv_instructions;
74
@@ -XXX,XX +XXX,XX @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu,
48
#define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions
75
can be detected */
49
#define TCG_TARGET_HAS_extract_i32 use_armv7_instructions
76
void tlb_protect_code(ram_addr_t ram_addr)
50
#define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions
77
{
51
+#define TCG_TARGET_HAS_extract2_i32 0
78
- cpu_physical_memory_test_and_clear_dirty(ram_addr, TARGET_PAGE_SIZE,
52
#define TCG_TARGET_HAS_movcond_i32 1
79
+ cpu_physical_memory_test_and_clear_dirty(ram_addr & TARGET_PAGE_MASK,
53
#define TCG_TARGET_HAS_mulu2_i32 1
80
+ TARGET_PAGE_SIZE,
54
#define TCG_TARGET_HAS_muls2_i32 1
81
DIRTY_MEMORY_CODE);
55
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
82
}
83
84
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
56
index XXXXXXX..XXXXXXX 100644
85
index XXXXXXX..XXXXXXX 100644
57
--- a/tcg/i386/tcg-target.h
86
--- a/accel/tcg/translate-all.c
58
+++ b/tcg/i386/tcg-target.h
87
+++ b/accel/tcg/translate-all.c
59
@@ -XXX,XX +XXX,XX @@ extern bool have_avx2;
88
@@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
60
#define TCG_TARGET_HAS_deposit_i32 1
89
qemu_spin_unlock(&tb->jmp_lock);
61
#define TCG_TARGET_HAS_extract_i32 1
90
62
#define TCG_TARGET_HAS_sextract_i32 1
91
/* remove the TB from the hash list */
63
+#define TCG_TARGET_HAS_extract2_i32 0
92
- phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
64
#define TCG_TARGET_HAS_movcond_i32 1
93
+ phys_pc = tb->page_addr[0];
65
#define TCG_TARGET_HAS_add2_i32 1
94
h = tb_hash_func(phys_pc, tb->pc, tb->flags, orig_cflags,
66
#define TCG_TARGET_HAS_sub2_i32 1
95
tb->trace_vcpu_dstate);
67
@@ -XXX,XX +XXX,XX @@ extern bool have_avx2;
96
if (!qht_remove(&tb_ctx.htable, tb, h)) {
68
#define TCG_TARGET_HAS_deposit_i64 1
97
@@ -XXX,XX +XXX,XX @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
69
#define TCG_TARGET_HAS_extract_i64 1
98
* we can only insert TBs that are fully initialized.
70
#define TCG_TARGET_HAS_sextract_i64 0
99
*/
71
+#define TCG_TARGET_HAS_extract2_i64 0
100
page_lock_pair(&p, phys_pc, &p2, phys_page2, true);
72
#define TCG_TARGET_HAS_movcond_i64 1
101
- tb_page_add(p, tb, 0, phys_pc & TARGET_PAGE_MASK);
73
#define TCG_TARGET_HAS_add2_i64 1
102
+ tb_page_add(p, tb, 0, phys_pc);
74
#define TCG_TARGET_HAS_sub2_i64 1
103
if (p2) {
75
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
104
tb_page_add(p2, tb, 1, phys_page2);
76
index XXXXXXX..XXXXXXX 100644
77
--- a/tcg/mips/tcg-target.h
78
+++ b/tcg/mips/tcg-target.h
79
@@ -XXX,XX +XXX,XX @@ extern bool use_mips32r2_instructions;
80
#define TCG_TARGET_HAS_deposit_i32 use_mips32r2_instructions
81
#define TCG_TARGET_HAS_extract_i32 use_mips32r2_instructions
82
#define TCG_TARGET_HAS_sextract_i32 0
83
+#define TCG_TARGET_HAS_extract2_i32 0
84
#define TCG_TARGET_HAS_ext8s_i32 use_mips32r2_instructions
85
#define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions
86
#define TCG_TARGET_HAS_rot_i32 use_mips32r2_instructions
87
@@ -XXX,XX +XXX,XX @@ extern bool use_mips32r2_instructions;
88
#define TCG_TARGET_HAS_deposit_i64 use_mips32r2_instructions
89
#define TCG_TARGET_HAS_extract_i64 use_mips32r2_instructions
90
#define TCG_TARGET_HAS_sextract_i64 0
91
+#define TCG_TARGET_HAS_extract2_i64 0
92
#define TCG_TARGET_HAS_ext8s_i64 use_mips32r2_instructions
93
#define TCG_TARGET_HAS_ext16s_i64 use_mips32r2_instructions
94
#define TCG_TARGET_HAS_rot_i64 use_mips32r2_instructions
95
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
96
index XXXXXXX..XXXXXXX 100644
97
--- a/tcg/ppc/tcg-target.h
98
+++ b/tcg/ppc/tcg-target.h
99
@@ -XXX,XX +XXX,XX @@ extern bool have_isa_3_00;
100
#define TCG_TARGET_HAS_deposit_i32 1
101
#define TCG_TARGET_HAS_extract_i32 1
102
#define TCG_TARGET_HAS_sextract_i32 0
103
+#define TCG_TARGET_HAS_extract2_i32 0
104
#define TCG_TARGET_HAS_movcond_i32 1
105
#define TCG_TARGET_HAS_mulu2_i32 0
106
#define TCG_TARGET_HAS_muls2_i32 0
107
@@ -XXX,XX +XXX,XX @@ extern bool have_isa_3_00;
108
#define TCG_TARGET_HAS_deposit_i64 1
109
#define TCG_TARGET_HAS_extract_i64 1
110
#define TCG_TARGET_HAS_sextract_i64 0
111
+#define TCG_TARGET_HAS_extract2_i64 0
112
#define TCG_TARGET_HAS_movcond_i64 1
113
#define TCG_TARGET_HAS_add2_i64 1
114
#define TCG_TARGET_HAS_sub2_i64 1
115
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
116
index XXXXXXX..XXXXXXX 100644
117
--- a/tcg/riscv/tcg-target.h
118
+++ b/tcg/riscv/tcg-target.h
119
@@ -XXX,XX +XXX,XX @@ typedef enum {
120
#define TCG_TARGET_HAS_deposit_i32 0
121
#define TCG_TARGET_HAS_extract_i32 0
122
#define TCG_TARGET_HAS_sextract_i32 0
123
+#define TCG_TARGET_HAS_extract2_i32 0
124
#define TCG_TARGET_HAS_add2_i32 1
125
#define TCG_TARGET_HAS_sub2_i32 1
126
#define TCG_TARGET_HAS_mulu2_i32 0
127
@@ -XXX,XX +XXX,XX @@ typedef enum {
128
#define TCG_TARGET_HAS_deposit_i64 0
129
#define TCG_TARGET_HAS_extract_i64 0
130
#define TCG_TARGET_HAS_sextract_i64 0
131
+#define TCG_TARGET_HAS_extract2_i64 0
132
#define TCG_TARGET_HAS_extrl_i64_i32 1
133
#define TCG_TARGET_HAS_extrh_i64_i32 1
134
#define TCG_TARGET_HAS_ext8s_i64 1
135
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
136
index XXXXXXX..XXXXXXX 100644
137
--- a/tcg/s390/tcg-target.h
138
+++ b/tcg/s390/tcg-target.h
139
@@ -XXX,XX +XXX,XX @@ extern uint64_t s390_facilities;
140
#define TCG_TARGET_HAS_deposit_i32 (s390_facilities & FACILITY_GEN_INST_EXT)
141
#define TCG_TARGET_HAS_extract_i32 (s390_facilities & FACILITY_GEN_INST_EXT)
142
#define TCG_TARGET_HAS_sextract_i32 0
143
+#define TCG_TARGET_HAS_extract2_i32 0
144
#define TCG_TARGET_HAS_movcond_i32 1
145
#define TCG_TARGET_HAS_add2_i32 1
146
#define TCG_TARGET_HAS_sub2_i32 1
147
@@ -XXX,XX +XXX,XX @@ extern uint64_t s390_facilities;
148
#define TCG_TARGET_HAS_deposit_i64 (s390_facilities & FACILITY_GEN_INST_EXT)
149
#define TCG_TARGET_HAS_extract_i64 (s390_facilities & FACILITY_GEN_INST_EXT)
150
#define TCG_TARGET_HAS_sextract_i64 0
151
+#define TCG_TARGET_HAS_extract2_i64 0
152
#define TCG_TARGET_HAS_movcond_i64 1
153
#define TCG_TARGET_HAS_add2_i64 1
154
#define TCG_TARGET_HAS_sub2_i64 1
155
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
156
index XXXXXXX..XXXXXXX 100644
157
--- a/tcg/sparc/tcg-target.h
158
+++ b/tcg/sparc/tcg-target.h
159
@@ -XXX,XX +XXX,XX @@ extern bool use_vis3_instructions;
160
#define TCG_TARGET_HAS_deposit_i32 0
161
#define TCG_TARGET_HAS_extract_i32 0
162
#define TCG_TARGET_HAS_sextract_i32 0
163
+#define TCG_TARGET_HAS_extract2_i32 0
164
#define TCG_TARGET_HAS_movcond_i32 1
165
#define TCG_TARGET_HAS_add2_i32 1
166
#define TCG_TARGET_HAS_sub2_i32 1
167
@@ -XXX,XX +XXX,XX @@ extern bool use_vis3_instructions;
168
#define TCG_TARGET_HAS_deposit_i64 0
169
#define TCG_TARGET_HAS_extract_i64 0
170
#define TCG_TARGET_HAS_sextract_i64 0
171
+#define TCG_TARGET_HAS_extract2_i64 0
172
#define TCG_TARGET_HAS_movcond_i64 1
173
#define TCG_TARGET_HAS_add2_i64 1
174
#define TCG_TARGET_HAS_sub2_i64 1
175
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
176
index XXXXXXX..XXXXXXX 100644
177
--- a/tcg/tcg-opc.h
178
+++ b/tcg/tcg-opc.h
179
@@ -XXX,XX +XXX,XX @@ DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
180
DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32))
181
DEF(extract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_extract_i32))
182
DEF(sextract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_sextract_i32))
183
+DEF(extract2_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_extract2_i32))
184
185
DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END)
186
187
@@ -XXX,XX +XXX,XX @@ DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
188
DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64))
189
DEF(extract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_extract_i64))
190
DEF(sextract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_sextract_i64))
191
+DEF(extract2_i64, 1, 2, 1, IMPL64 | IMPL(TCG_TARGET_HAS_extract2_i64))
192
193
/* size changing ops */
194
DEF(ext_i32_i64, 1, 1, 0, IMPL64)
195
diff --git a/tcg/tcg.h b/tcg/tcg.h
196
index XXXXXXX..XXXXXXX 100644
197
--- a/tcg/tcg.h
198
+++ b/tcg/tcg.h
199
@@ -XXX,XX +XXX,XX @@ typedef uint64_t TCGRegSet;
200
#define TCG_TARGET_HAS_deposit_i64 0
201
#define TCG_TARGET_HAS_extract_i64 0
202
#define TCG_TARGET_HAS_sextract_i64 0
203
+#define TCG_TARGET_HAS_extract2_i64 0
204
#define TCG_TARGET_HAS_movcond_i64 0
205
#define TCG_TARGET_HAS_add2_i64 0
206
#define TCG_TARGET_HAS_sub2_i64 0
207
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
208
index XXXXXXX..XXXXXXX 100644
209
--- a/tcg/tci/tcg-target.h
210
+++ b/tcg/tci/tcg-target.h
211
@@ -XXX,XX +XXX,XX @@
212
#define TCG_TARGET_HAS_deposit_i32 1
213
#define TCG_TARGET_HAS_extract_i32 0
214
#define TCG_TARGET_HAS_sextract_i32 0
215
+#define TCG_TARGET_HAS_extract2_i32 0
216
#define TCG_TARGET_HAS_eqv_i32 0
217
#define TCG_TARGET_HAS_nand_i32 0
218
#define TCG_TARGET_HAS_nor_i32 0
219
@@ -XXX,XX +XXX,XX @@
220
#define TCG_TARGET_HAS_deposit_i64 1
221
#define TCG_TARGET_HAS_extract_i64 0
222
#define TCG_TARGET_HAS_sextract_i64 0
223
+#define TCG_TARGET_HAS_extract2_i64 0
224
#define TCG_TARGET_HAS_div_i64 0
225
#define TCG_TARGET_HAS_rem_i64 0
226
#define TCG_TARGET_HAS_ext8s_i64 1
227
diff --git a/tcg/optimize.c b/tcg/optimize.c
228
index XXXXXXX..XXXXXXX 100644
229
--- a/tcg/optimize.c
230
+++ b/tcg/optimize.c
231
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
232
}
233
goto do_default;
234
235
+ CASE_OP_32_64(extract2):
236
+ if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
237
+ TCGArg v1 = arg_info(op->args[1])->val;
238
+ TCGArg v2 = arg_info(op->args[2])->val;
239
+
240
+ if (opc == INDEX_op_extract2_i64) {
241
+ tmp = (v1 >> op->args[3]) | (v2 << (64 - op->args[3]));
242
+ } else {
243
+ tmp = (v1 >> op->args[3]) | (v2 << (32 - op->args[3]));
244
+ tmp = (int32_t)tmp;
245
+ }
246
+ tcg_opt_gen_movi(s, op, op->args[0], tmp);
247
+ break;
248
+ }
249
+ goto do_default;
250
+
251
CASE_OP_32_64(setcond):
252
tmp = do_constant_folding_cond(opc, op->args[1],
253
op->args[2], op->args[3]);
254
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
255
index XXXXXXX..XXXXXXX 100644
256
--- a/tcg/tcg-op.c
257
+++ b/tcg/tcg-op.c
258
@@ -XXX,XX +XXX,XX @@ void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah,
259
tcg_gen_mov_i32(ret, ah);
260
} else if (al == ah) {
261
tcg_gen_rotri_i32(ret, al, ofs);
262
+ } else if (TCG_TARGET_HAS_extract2_i32) {
263
+ tcg_gen_op4i_i32(INDEX_op_extract2_i32, ret, al, ah, ofs);
264
} else {
105
} else {
265
TCGv_i32 t0 = tcg_temp_new_i32();
106
@@ -XXX,XX +XXX,XX @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages,
266
tcg_gen_shri_i32(t0, al, ofs);
107
if (n == 0) {
267
@@ -XXX,XX +XXX,XX @@ void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah,
108
/* NOTE: tb_end may be after the end of the page, but
268
tcg_gen_mov_i64(ret, ah);
109
it is not a problem */
269
} else if (al == ah) {
110
- tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK);
270
tcg_gen_rotri_i64(ret, al, ofs);
111
+ tb_start = tb->page_addr[0];
271
+ } else if (TCG_TARGET_HAS_extract2_i64) {
112
tb_end = tb_start + tb->size;
272
+ tcg_gen_op4i_i64(INDEX_op_extract2_i64, ret, al, ah, ofs);
113
} else {
273
} else {
114
tb_start = tb->page_addr[1];
274
TCGv_i64 t0 = tcg_temp_new_i64();
115
- tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK);
275
tcg_gen_shri_i64(t0, al, ofs);
116
+ tb_end = tb_start + ((tb->page_addr[0] + tb->size)
276
diff --git a/tcg/tcg.c b/tcg/tcg.c
117
+ & ~TARGET_PAGE_MASK);
277
index XXXXXXX..XXXXXXX 100644
118
}
278
--- a/tcg/tcg.c
119
if (!(tb_end <= start || tb_start >= end)) {
279
+++ b/tcg/tcg.c
120
#ifdef TARGET_HAS_PRECISE_SMC
280
@@ -XXX,XX +XXX,XX @@ bool tcg_op_supported(TCGOpcode op)
281
return TCG_TARGET_HAS_extract_i32;
282
case INDEX_op_sextract_i32:
283
return TCG_TARGET_HAS_sextract_i32;
284
+ case INDEX_op_extract2_i32:
285
+ return TCG_TARGET_HAS_extract2_i32;
286
case INDEX_op_add2_i32:
287
return TCG_TARGET_HAS_add2_i32;
288
case INDEX_op_sub2_i32:
289
@@ -XXX,XX +XXX,XX @@ bool tcg_op_supported(TCGOpcode op)
290
return TCG_TARGET_HAS_extract_i64;
291
case INDEX_op_sextract_i64:
292
return TCG_TARGET_HAS_sextract_i64;
293
+ case INDEX_op_extract2_i64:
294
+ return TCG_TARGET_HAS_extract2_i64;
295
case INDEX_op_extrl_i64_i32:
296
return TCG_TARGET_HAS_extrl_i64_i32;
297
case INDEX_op_extrh_i64_i32:
298
diff --git a/tcg/README b/tcg/README
299
index XXXXXXX..XXXXXXX 100644
300
--- a/tcg/README
301
+++ b/tcg/README
302
@@ -XXX,XX +XXX,XX @@ at bit 8. This operation would be equivalent to
303
304
(using an arithmetic right shift).
305
306
+* extract2_i32/i64 dest, t1, t2, pos
307
+
308
+For N = {32,64}, extract an N-bit quantity from the concatenation
309
+of t2:t1, beginning at pos. The tcg_gen_extract2_{i32,i64} expander
310
+accepts 0 <= pos <= N as inputs. The backend code generator will
311
+not see either 0 or N as inputs for these opcodes.
312
+
313
* extrl_i64_i32 t0, t1
314
315
For 64-bit hosts only, extract the low 32-bits of input T1 and place it
316
--
121
--
317
2.17.1
122
2.34.1
318
123
319
124
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/15] tcg/ppc: Allow the constant pool to overflow at 32k
[PULL 14/20] accel/tcg: Inline tb_flush_jmp_cache
1
There is no point in coding for a 2GB offset when the max TB size
1
This function has two users, who use it incompatibly.
2
is already limited to 64k. If we further restrict to 32k then we
2
In tlb_flush_page_by_mmuidx_async_0, when flushing a
3
can eliminate the extra ADDIS instruction.
3
single page, we need to flush exactly two pages.
4
In tlb_flush_range_by_mmuidx_async_0, when flushing a
5
range of pages, we need to flush N+1 pages.
4
6
7
This avoids double-flushing of jmp cache pages in a range.
8
9
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
11
---
7
tcg/ppc/tcg-target.inc.c | 28 ++++++++++------------------
12
accel/tcg/cputlb.c | 25 ++++++++++++++-----------
8
1 file changed, 10 insertions(+), 18 deletions(-)
13
1 file changed, 14 insertions(+), 11 deletions(-)
9
14
10
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
15
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
11
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/ppc/tcg-target.inc.c
17
--- a/accel/tcg/cputlb.c
13
+++ b/tcg/ppc/tcg-target.inc.c
18
+++ b/accel/tcg/cputlb.c
14
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
19
@@ -XXX,XX +XXX,XX @@ static void tb_jmp_cache_clear_page(CPUState *cpu, target_ulong page_addr)
15
intptr_t value, intptr_t addend)
20
}
16
{
21
}
17
tcg_insn_unit *target;
22
18
- tcg_insn_unit old;
23
-static void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr)
19
24
-{
20
value += addend;
25
- /* Discard jump cache entries for any tb which might potentially
21
target = (tcg_insn_unit *)value;
26
- overlap the flushed page. */
22
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
27
- tb_jmp_cache_clear_page(cpu, addr - TARGET_PAGE_SIZE);
23
case R_PPC_REL24:
28
- tb_jmp_cache_clear_page(cpu, addr);
24
return reloc_pc24(code_ptr, target);
29
-}
25
case R_PPC_ADDR16:
30
-
26
- /* We are abusing this relocation type. This points to a pair
31
/**
27
- of insns, addis + load. If the displacement is small, we
32
* tlb_mmu_resize_locked() - perform TLB resize bookkeeping; resize if necessary
28
- can nop out the addis. */
33
* @desc: The CPUTLBDesc portion of the TLB
29
- if (value == (int16_t)value) {
34
@@ -XXX,XX +XXX,XX @@ static void tlb_flush_page_by_mmuidx_async_0(CPUState *cpu,
30
- code_ptr[0] = NOP;
35
}
31
- old = deposit32(code_ptr[1], 0, 16, value);
36
qemu_spin_unlock(&env_tlb(env)->c.lock);
32
- code_ptr[1] = deposit32(old, 16, 5, TCG_REG_TB);
37
33
- } else {
38
- tb_flush_jmp_cache(cpu, addr);
34
- int16_t lo = value;
39
+ /*
35
- int hi = value - lo;
40
+ * Discard jump cache entries for any tb which might potentially
36
- if (hi + lo != value) {
41
+ * overlap the flushed page, which includes the previous.
37
- return false;
42
+ */
38
- }
43
+ tb_jmp_cache_clear_page(cpu, addr - TARGET_PAGE_SIZE);
39
- code_ptr[0] = deposit32(code_ptr[0], 0, 16, hi >> 16);
44
+ tb_jmp_cache_clear_page(cpu, addr);
40
- code_ptr[1] = deposit32(code_ptr[1], 0, 16, lo);
45
}
41
+ /*
46
42
+ * We are (slightly) abusing this relocation type. In particular,
47
/**
43
+ * assert that the low 2 bits are zero, and do not modify them.
48
@@ -XXX,XX +XXX,XX @@ static void tlb_flush_range_by_mmuidx_async_0(CPUState *cpu,
44
+ * That way we can use this with LD et al that have opcode bits
45
+ * in the low 2 bits of the insn.
46
+ */
47
+ if ((value & 3) || value != (int16_t)value) {
48
+ return false;
49
}
50
+ *code_ptr = (*code_ptr & ~0xfffc) | (value & 0xfffc);
51
break;
52
default:
53
g_assert_not_reached();
54
@@ -XXX,XX +XXX,XX @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
55
if (!in_prologue && USE_REG_TB) {
56
new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr,
57
-(intptr_t)s->code_gen_ptr);
58
- tcg_out32(s, ADDIS | TAI(ret, TCG_REG_TB, 0));
59
- tcg_out32(s, LD | TAI(ret, ret, 0));
60
+ tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0));
61
return;
49
return;
62
}
50
}
63
51
52
- for (target_ulong i = 0; i < d.len; i += TARGET_PAGE_SIZE) {
53
- tb_flush_jmp_cache(cpu, d.addr + i);
54
+ /*
55
+ * Discard jump cache entries for any tb which might potentially
56
+ * overlap the flushed pages, which includes the previous.
57
+ */
58
+ d.addr -= TARGET_PAGE_SIZE;
59
+ for (target_ulong i = 0, n = d.len / TARGET_PAGE_SIZE + 1; i < n; i++) {
60
+ tb_jmp_cache_clear_page(cpu, d.addr);
61
+ d.addr += TARGET_PAGE_SIZE;
62
}
63
}
64
64
--
65
--
65
2.17.1
66
2.34.1
66
67
67
68
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/15] tcg: Use extract2 in tcg_gen_deposit_{i32, i64}
[PULL 15/20] include/hw/core: Create struct CPUJumpCache
1
Wrap the bare TranslationBlock pointer into a structure.
2
3
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2
---
6
---
3
tcg/tcg-op.c | 34 ++++++++++++++++++++++++++++++----
7
accel/tcg/tb-hash.h | 1 +
4
1 file changed, 30 insertions(+), 4 deletions(-)
8
accel/tcg/tb-jmp-cache.h | 24 ++++++++++++++++++++++++
9
include/exec/cpu-common.h | 1 +
10
include/hw/core/cpu.h | 15 +--------------
11
include/qemu/typedefs.h | 1 +
12
accel/stubs/tcg-stub.c | 4 ++++
13
accel/tcg/cpu-exec.c | 10 +++++++---
14
accel/tcg/cputlb.c | 9 +++++----
15
accel/tcg/translate-all.c | 28 +++++++++++++++++++++++++---
16
hw/core/cpu-common.c | 3 +--
17
plugins/core.c | 2 +-
18
trace/control-target.c | 2 +-
19
12 files changed, 72 insertions(+), 28 deletions(-)
20
create mode 100644 accel/tcg/tb-jmp-cache.h
5
21
6
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
22
diff --git a/accel/tcg/tb-hash.h b/accel/tcg/tb-hash.h
7
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
8
--- a/tcg/tcg-op.c
24
--- a/accel/tcg/tb-hash.h
9
+++ b/tcg/tcg-op.c
25
+++ b/accel/tcg/tb-hash.h
10
@@ -XXX,XX +XXX,XX @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
26
@@ -XXX,XX +XXX,XX @@
27
#include "exec/cpu-defs.h"
28
#include "exec/exec-all.h"
29
#include "qemu/xxhash.h"
30
+#include "tb-jmp-cache.h"
31
32
#ifdef CONFIG_SOFTMMU
33
34
diff --git a/accel/tcg/tb-jmp-cache.h b/accel/tcg/tb-jmp-cache.h
35
new file mode 100644
36
index XXXXXXX..XXXXXXX
37
--- /dev/null
38
+++ b/accel/tcg/tb-jmp-cache.h
39
@@ -XXX,XX +XXX,XX @@
40
+/*
41
+ * The per-CPU TranslationBlock jump cache.
42
+ *
43
+ * Copyright (c) 2003 Fabrice Bellard
44
+ *
45
+ * SPDX-License-Identifier: GPL-2.0-or-later
46
+ */
47
+
48
+#ifndef ACCEL_TCG_TB_JMP_CACHE_H
49
+#define ACCEL_TCG_TB_JMP_CACHE_H
50
+
51
+#define TB_JMP_CACHE_BITS 12
52
+#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
53
+
54
+/*
55
+ * Accessed in parallel; all accesses to 'tb' must be atomic.
56
+ */
57
+struct CPUJumpCache {
58
+ struct {
59
+ TranslationBlock *tb;
60
+ } array[TB_JMP_CACHE_SIZE];
61
+};
62
+
63
+#endif /* ACCEL_TCG_TB_JMP_CACHE_H */
64
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
65
index XXXXXXX..XXXXXXX 100644
66
--- a/include/exec/cpu-common.h
67
+++ b/include/exec/cpu-common.h
68
@@ -XXX,XX +XXX,XX @@ void cpu_list_unlock(void);
69
unsigned int cpu_list_generation_id_get(void);
70
71
void tcg_flush_softmmu_tlb(CPUState *cs);
72
+void tcg_flush_jmp_cache(CPUState *cs);
73
74
void tcg_iommu_init_notifier_list(CPUState *cpu);
75
void tcg_iommu_free_notifier_list(CPUState *cpu);
76
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
77
index XXXXXXX..XXXXXXX 100644
78
--- a/include/hw/core/cpu.h
79
+++ b/include/hw/core/cpu.h
80
@@ -XXX,XX +XXX,XX @@ struct kvm_run;
81
struct hax_vcpu_state;
82
struct hvf_vcpu_state;
83
84
-#define TB_JMP_CACHE_BITS 12
85
-#define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS)
86
-
87
/* work queue */
88
89
/* The union type allows passing of 64 bit target pointers on 32 bit
90
@@ -XXX,XX +XXX,XX @@ struct CPUState {
91
CPUArchState *env_ptr;
92
IcountDecr *icount_decr_ptr;
93
94
- /* Accessed in parallel; all accesses must be atomic */
95
- TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE];
96
+ CPUJumpCache *tb_jmp_cache;
97
98
struct GDBRegisterState *gdb_regs;
99
int gdb_num_regs;
100
@@ -XXX,XX +XXX,XX @@ extern CPUTailQ cpus;
101
102
extern __thread CPUState *current_cpu;
103
104
-static inline void cpu_tb_jmp_cache_clear(CPUState *cpu)
105
-{
106
- unsigned int i;
107
-
108
- for (i = 0; i < TB_JMP_CACHE_SIZE; i++) {
109
- qatomic_set(&cpu->tb_jmp_cache[i], NULL);
110
- }
111
-}
112
-
113
/**
114
* qemu_tcg_mttcg_enabled:
115
* Check whether we are running MultiThread TCG or not.
116
diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h
117
index XXXXXXX..XXXXXXX 100644
118
--- a/include/qemu/typedefs.h
119
+++ b/include/qemu/typedefs.h
120
@@ -XXX,XX +XXX,XX @@ typedef struct CoMutex CoMutex;
121
typedef struct ConfidentialGuestSupport ConfidentialGuestSupport;
122
typedef struct CPUAddressSpace CPUAddressSpace;
123
typedef struct CPUArchState CPUArchState;
124
+typedef struct CPUJumpCache CPUJumpCache;
125
typedef struct CPUState CPUState;
126
typedef struct CPUTLBEntryFull CPUTLBEntryFull;
127
typedef struct DeviceListener DeviceListener;
128
diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c
129
index XXXXXXX..XXXXXXX 100644
130
--- a/accel/stubs/tcg-stub.c
131
+++ b/accel/stubs/tcg-stub.c
132
@@ -XXX,XX +XXX,XX @@ void tlb_set_dirty(CPUState *cpu, target_ulong vaddr)
133
{
134
}
135
136
+void tcg_flush_jmp_cache(CPUState *cpu)
137
+{
138
+}
139
+
140
int probe_access_flags(CPUArchState *env, target_ulong addr,
141
MMUAccessType access_type, int mmu_idx,
142
bool nonfault, void **phost, uintptr_t retaddr)
143
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
144
index XXXXXXX..XXXXXXX 100644
145
--- a/accel/tcg/cpu-exec.c
146
+++ b/accel/tcg/cpu-exec.c
147
@@ -XXX,XX +XXX,XX @@
148
#include "sysemu/replay.h"
149
#include "sysemu/tcg.h"
150
#include "exec/helper-proto.h"
151
+#include "tb-jmp-cache.h"
152
#include "tb-hash.h"
153
#include "tb-context.h"
154
#include "internal.h"
155
@@ -XXX,XX +XXX,XX @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc,
156
tcg_debug_assert(!(cflags & CF_INVALID));
157
158
hash = tb_jmp_cache_hash_func(pc);
159
- tb = qatomic_rcu_read(&cpu->tb_jmp_cache[hash]);
160
+ tb = qatomic_rcu_read(&cpu->tb_jmp_cache->array[hash].tb);
161
162
if (likely(tb &&
163
tb->pc == pc &&
164
@@ -XXX,XX +XXX,XX @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc,
165
if (tb == NULL) {
166
return NULL;
167
}
168
- qatomic_set(&cpu->tb_jmp_cache[hash], tb);
169
+ qatomic_set(&cpu->tb_jmp_cache->array[hash].tb, tb);
170
return tb;
171
}
172
173
@@ -XXX,XX +XXX,XX @@ int cpu_exec(CPUState *cpu)
174
175
tb = tb_lookup(cpu, pc, cs_base, flags, cflags);
176
if (tb == NULL) {
177
+ uint32_t h;
178
+
179
mmap_lock();
180
tb = tb_gen_code(cpu, pc, cs_base, flags, cflags);
181
mmap_unlock();
182
@@ -XXX,XX +XXX,XX @@ int cpu_exec(CPUState *cpu)
183
* We add the TB in the virtual pc hash table
184
* for the fast lookup
185
*/
186
- qatomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)], tb);
187
+ h = tb_jmp_cache_hash_func(pc);
188
+ qatomic_set(&cpu->tb_jmp_cache->array[h].tb, tb);
189
}
190
191
#ifndef CONFIG_USER_ONLY
192
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
193
index XXXXXXX..XXXXXXX 100644
194
--- a/accel/tcg/cputlb.c
195
+++ b/accel/tcg/cputlb.c
196
@@ -XXX,XX +XXX,XX @@ static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns,
197
198
static void tb_jmp_cache_clear_page(CPUState *cpu, target_ulong page_addr)
199
{
200
- unsigned int i, i0 = tb_jmp_cache_hash_page(page_addr);
201
+ int i, i0 = tb_jmp_cache_hash_page(page_addr);
202
+ CPUJumpCache *jc = cpu->tb_jmp_cache;
203
204
for (i = 0; i < TB_JMP_PAGE_SIZE; i++) {
205
- qatomic_set(&cpu->tb_jmp_cache[i0 + i], NULL);
206
+ qatomic_set(&jc->array[i0 + i].tb, NULL);
207
}
208
}
209
210
@@ -XXX,XX +XXX,XX @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data data)
211
212
qemu_spin_unlock(&env_tlb(env)->c.lock);
213
214
- cpu_tb_jmp_cache_clear(cpu);
215
+ tcg_flush_jmp_cache(cpu);
216
217
if (to_clean == ALL_MMUIDX_BITS) {
218
qatomic_set(&env_tlb(env)->c.full_flush_count,
219
@@ -XXX,XX +XXX,XX @@ static void tlb_flush_range_by_mmuidx_async_0(CPUState *cpu,
220
* longer to clear each entry individually than it will to clear it all.
221
*/
222
if (d.len >= (TARGET_PAGE_SIZE * TB_JMP_CACHE_SIZE)) {
223
- cpu_tb_jmp_cache_clear(cpu);
224
+ tcg_flush_jmp_cache(cpu);
11
return;
225
return;
12
}
226
}
13
227
14
- mask = (1u << len) - 1;
228
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
15
t1 = tcg_temp_new_i32();
229
index XXXXXXX..XXXXXXX 100644
16
230
--- a/accel/tcg/translate-all.c
17
+ if (TCG_TARGET_HAS_extract2_i32) {
231
+++ b/accel/tcg/translate-all.c
18
+ if (ofs + len == 32) {
232
@@ -XXX,XX +XXX,XX @@
19
+ tcg_gen_shli_i32(t1, arg1, len);
233
#include "sysemu/tcg.h"
20
+ tcg_gen_extract2_i32(ret, t1, arg2, len);
234
#include "qapi/error.h"
21
+ goto done;
235
#include "hw/core/tcg-cpu-ops.h"
236
+#include "tb-jmp-cache.h"
237
#include "tb-hash.h"
238
#include "tb-context.h"
239
#include "internal.h"
240
@@ -XXX,XX +XXX,XX @@ static void do_tb_flush(CPUState *cpu, run_on_cpu_data tb_flush_count)
241
}
242
243
CPU_FOREACH(cpu) {
244
- cpu_tb_jmp_cache_clear(cpu);
245
+ tcg_flush_jmp_cache(cpu);
246
}
247
248
qht_reset_size(&tb_ctx.htable, CODE_GEN_HTABLE_SIZE);
249
@@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
250
/* remove the TB from the hash list */
251
h = tb_jmp_cache_hash_func(tb->pc);
252
CPU_FOREACH(cpu) {
253
- if (qatomic_read(&cpu->tb_jmp_cache[h]) == tb) {
254
- qatomic_set(&cpu->tb_jmp_cache[h], NULL);
255
+ CPUJumpCache *jc = cpu->tb_jmp_cache;
256
+ if (qatomic_read(&jc->array[h].tb) == tb) {
257
+ qatomic_set(&jc->array[h].tb, NULL);
258
}
259
}
260
261
@@ -XXX,XX +XXX,XX @@ int page_unprotect(target_ulong address, uintptr_t pc)
262
}
263
#endif /* CONFIG_USER_ONLY */
264
265
+/*
266
+ * Called by generic code at e.g. cpu reset after cpu creation,
267
+ * therefore we must be prepared to allocate the jump cache.
268
+ */
269
+void tcg_flush_jmp_cache(CPUState *cpu)
270
+{
271
+ CPUJumpCache *jc = cpu->tb_jmp_cache;
272
+
273
+ if (likely(jc)) {
274
+ for (int i = 0; i < TB_JMP_CACHE_SIZE; i++) {
275
+ qatomic_set(&jc->array[i].tb, NULL);
22
+ }
276
+ }
23
+ if (ofs == 0) {
277
+ } else {
24
+ tcg_gen_extract2_i32(ret, arg1, arg2, len);
278
+ /* This should happen once during realize, and thus never race. */
25
+ tcg_gen_rotli_i32(ret, ret, len);
279
+ jc = g_new0(CPUJumpCache, 1);
26
+ goto done;
280
+ jc = qatomic_xchg(&cpu->tb_jmp_cache, jc);
27
+ }
281
+ assert(jc == NULL);
28
+ }
282
+ }
29
+
283
+}
30
+ mask = (1u << len) - 1;
284
+
31
if (ofs + len < 32) {
285
/* This is a wrapper for common code that can not use CONFIG_SOFTMMU */
32
tcg_gen_andi_i32(t1, arg2, mask);
286
void tcg_flush_softmmu_tlb(CPUState *cs)
33
tcg_gen_shli_i32(t1, t1, ofs);
287
{
34
@@ -XXX,XX +XXX,XX @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
288
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
35
}
289
index XXXXXXX..XXXXXXX 100644
36
tcg_gen_andi_i32(ret, arg1, ~(mask << ofs));
290
--- a/hw/core/cpu-common.c
37
tcg_gen_or_i32(ret, ret, t1);
291
+++ b/hw/core/cpu-common.c
292
@@ -XXX,XX +XXX,XX @@ static void cpu_common_reset(DeviceState *dev)
293
cpu->cflags_next_tb = -1;
294
295
if (tcg_enabled()) {
296
- cpu_tb_jmp_cache_clear(cpu);
38
-
297
-
39
+ done:
298
+ tcg_flush_jmp_cache(cpu);
40
tcg_temp_free_i32(t1);
299
tcg_flush_softmmu_tlb(cpu);
41
}
300
}
42
301
}
43
@@ -XXX,XX +XXX,XX @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
302
diff --git a/plugins/core.c b/plugins/core.c
44
}
303
index XXXXXXX..XXXXXXX 100644
45
}
304
--- a/plugins/core.c
46
305
+++ b/plugins/core.c
47
- mask = (1ull << len) - 1;
306
@@ -XXX,XX +XXX,XX @@ struct qemu_plugin_ctx *plugin_id_to_ctx_locked(qemu_plugin_id_t id)
48
t1 = tcg_temp_new_i64();
307
static void plugin_cpu_update__async(CPUState *cpu, run_on_cpu_data data)
49
308
{
50
+ if (TCG_TARGET_HAS_extract2_i64) {
309
bitmap_copy(cpu->plugin_mask, &data.host_ulong, QEMU_PLUGIN_EV_MAX);
51
+ if (ofs + len == 64) {
310
- cpu_tb_jmp_cache_clear(cpu);
52
+ tcg_gen_shli_i64(t1, arg1, len);
311
+ tcg_flush_jmp_cache(cpu);
53
+ tcg_gen_extract2_i64(ret, t1, arg2, len);
312
}
54
+ goto done;
313
55
+ }
314
static void plugin_cpu_update__locked(gpointer k, gpointer v, gpointer udata)
56
+ if (ofs == 0) {
315
diff --git a/trace/control-target.c b/trace/control-target.c
57
+ tcg_gen_extract2_i64(ret, arg1, arg2, len);
316
index XXXXXXX..XXXXXXX 100644
58
+ tcg_gen_rotli_i64(ret, ret, len);
317
--- a/trace/control-target.c
59
+ goto done;
318
+++ b/trace/control-target.c
60
+ }
319
@@ -XXX,XX +XXX,XX @@ static void trace_event_synchronize_vcpu_state_dynamic(
61
+ }
320
{
62
+
321
bitmap_copy(vcpu->trace_dstate, vcpu->trace_dstate_delayed,
63
+ mask = (1ull << len) - 1;
322
CPU_TRACE_DSTATE_MAX_EVENTS);
64
if (ofs + len < 64) {
323
- cpu_tb_jmp_cache_clear(vcpu);
65
tcg_gen_andi_i64(t1, arg2, mask);
324
+ tcg_flush_jmp_cache(vcpu);
66
tcg_gen_shli_i64(t1, t1, ofs);
325
}
67
@@ -XXX,XX +XXX,XX @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
326
68
}
327
void trace_event_set_vcpu_state_dynamic(CPUState *vcpu,
69
tcg_gen_andi_i64(ret, arg1, ~(mask << ofs));
70
tcg_gen_or_i64(ret, ret, t1);
71
-
72
+ done:
73
tcg_temp_free_i64(t1);
74
}
75
76
--
328
--
77
2.17.1
329
2.34.1
78
330
79
331
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/15] tcg: Use deposit and extract2 in tcg_gen_shifti_i64
[PULL 16/20] hw/core: Add CPUClass.get_pc
1
Populate this new method for all targets. Always match
2
the result that would be given by cpu_get_tb_cpu_state,
3
as we will want these values to correspond in the logs.
4
5
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
6
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
7
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> (target/sparc)
1
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2
---
9
---
3
tcg/tcg-op.c | 47 ++++++++++++++++++++++++-----------------------
10
Cc: Eduardo Habkost <eduardo@habkost.net> (supporter:Machine core)
4
1 file changed, 24 insertions(+), 23 deletions(-)
11
Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com> (supporter:Machine core)
12
Cc: "Philippe Mathieu-Daudé" <f4bug@amsat.org> (reviewer:Machine core)
13
Cc: Yanan Wang <wangyanan55@huawei.com> (reviewer:Machine core)
14
Cc: Michael Rolnik <mrolnik@gmail.com> (maintainer:AVR TCG CPUs)
15
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com> (maintainer:CRIS TCG CPUs)
16
Cc: Taylor Simpson <tsimpson@quicinc.com> (supporter:Hexagon TCG CPUs)
17
Cc: Song Gao <gaosong@loongson.cn> (maintainer:LoongArch TCG CPUs)
18
Cc: Xiaojuan Yang <yangxiaojuan@loongson.cn> (maintainer:LoongArch TCG CPUs)
19
Cc: Laurent Vivier <laurent@vivier.eu> (maintainer:M68K TCG CPUs)
20
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> (reviewer:MIPS TCG CPUs)
21
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> (reviewer:MIPS TCG CPUs)
22
Cc: Chris Wulff <crwulff@gmail.com> (maintainer:NiosII TCG CPUs)
23
Cc: Marek Vasut <marex@denx.de> (maintainer:NiosII TCG CPUs)
24
Cc: Stafford Horne <shorne@gmail.com> (odd fixer:OpenRISC TCG CPUs)
25
Cc: Yoshinori Sato <ysato@users.sourceforge.jp> (reviewer:RENESAS RX CPUs)
26
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> (maintainer:SPARC TCG CPUs)
27
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> (maintainer:TriCore TCG CPUs)
28
Cc: Max Filippov <jcmvbkbc@gmail.com> (maintainer:Xtensa TCG CPUs)
29
Cc: qemu-arm@nongnu.org (open list:ARM TCG CPUs)
30
Cc: qemu-ppc@nongnu.org (open list:PowerPC TCG CPUs)
31
Cc: qemu-riscv@nongnu.org (open list:RISC-V TCG CPUs)
32
Cc: qemu-s390x@nongnu.org (open list:S390 TCG CPUs)
33
---
34
include/hw/core/cpu.h | 3 +++
35
target/alpha/cpu.c | 9 +++++++++
36
target/arm/cpu.c | 13 +++++++++++++
37
target/avr/cpu.c | 8 ++++++++
38
target/cris/cpu.c | 8 ++++++++
39
target/hexagon/cpu.c | 8 ++++++++
40
target/hppa/cpu.c | 8 ++++++++
41
target/i386/cpu.c | 9 +++++++++
42
target/loongarch/cpu.c | 9 +++++++++
43
target/m68k/cpu.c | 8 ++++++++
44
target/microblaze/cpu.c | 8 ++++++++
45
target/mips/cpu.c | 8 ++++++++
46
target/nios2/cpu.c | 9 +++++++++
47
target/openrisc/cpu.c | 8 ++++++++
48
target/ppc/cpu_init.c | 8 ++++++++
49
target/riscv/cpu.c | 13 +++++++++++++
50
target/rx/cpu.c | 8 ++++++++
51
target/s390x/cpu.c | 8 ++++++++
52
target/sh4/cpu.c | 8 ++++++++
53
target/sparc/cpu.c | 8 ++++++++
54
target/tricore/cpu.c | 9 +++++++++
55
target/xtensa/cpu.c | 8 ++++++++
56
22 files changed, 186 insertions(+)
5
57
6
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
58
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
7
index XXXXXXX..XXXXXXX 100644
59
index XXXXXXX..XXXXXXX 100644
8
--- a/tcg/tcg-op.c
60
--- a/include/hw/core/cpu.h
9
+++ b/tcg/tcg-op.c
61
+++ b/include/hw/core/cpu.h
10
@@ -XXX,XX +XXX,XX @@ static inline void tcg_gen_shifti_i64(TCGv_i64 ret, TCGv_i64 arg1,
62
@@ -XXX,XX +XXX,XX @@ struct SysemuCPUOps;
11
tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_LOW(arg1), c);
63
* If the target behaviour here is anything other than "set
12
tcg_gen_movi_i32(TCGV_LOW(ret), 0);
64
* the PC register to the value passed in" then the target must
13
}
65
* also implement the synchronize_from_tb hook.
14
- } else {
66
+ * @get_pc: Callback for getting the Program Counter register.
15
- TCGv_i32 t0, t1;
67
+ * As above, with the semantics of the target architecture.
16
-
68
* @gdb_read_register: Callback for letting GDB read a register.
17
- t0 = tcg_temp_new_i32();
69
* @gdb_write_register: Callback for letting GDB write a register.
18
- t1 = tcg_temp_new_i32();
70
* @gdb_adjust_breakpoint: Callback for adjusting the address of a
19
- if (right) {
71
@@ -XXX,XX +XXX,XX @@ struct CPUClass {
20
- tcg_gen_shli_i32(t0, TCGV_HIGH(arg1), 32 - c);
72
void (*dump_state)(CPUState *cpu, FILE *, int flags);
21
- if (arith) {
73
int64_t (*get_arch_id)(CPUState *cpu);
22
- tcg_gen_sari_i32(t1, TCGV_HIGH(arg1), c);
74
void (*set_pc)(CPUState *cpu, vaddr value);
23
- } else {
75
+ vaddr (*get_pc)(CPUState *cpu);
24
- tcg_gen_shri_i32(t1, TCGV_HIGH(arg1), c);
76
int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg);
25
- }
77
int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg);
26
- tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
78
vaddr (*gdb_adjust_breakpoint)(CPUState *cpu, vaddr addr);
27
- tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t0);
79
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
28
- tcg_gen_mov_i32(TCGV_HIGH(ret), t1);
80
index XXXXXXX..XXXXXXX 100644
29
+ } else if (right) {
81
--- a/target/alpha/cpu.c
30
+ if (TCG_TARGET_HAS_extract2_i32) {
82
+++ b/target/alpha/cpu.c
31
+ tcg_gen_extract2_i32(TCGV_LOW(ret),
83
@@ -XXX,XX +XXX,XX @@ static void alpha_cpu_set_pc(CPUState *cs, vaddr value)
32
+ TCGV_LOW(arg1), TCGV_HIGH(arg1), c);
84
cpu->env.pc = value;
33
} else {
85
}
34
- tcg_gen_shri_i32(t0, TCGV_LOW(arg1), 32 - c);
86
35
- /* Note: ret can be the same as arg1, so we use t1 */
87
+static vaddr alpha_cpu_get_pc(CPUState *cs)
36
- tcg_gen_shli_i32(t1, TCGV_LOW(arg1), c);
88
+{
37
- tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
89
+ AlphaCPU *cpu = ALPHA_CPU(cs);
38
- tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t0);
90
+
39
- tcg_gen_mov_i32(TCGV_LOW(ret), t1);
91
+ return cpu->env.pc;
40
+ tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
92
+}
41
+ tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(ret),
93
+
42
+ TCGV_HIGH(arg1), 32 - c, c);
94
+
43
}
95
static bool alpha_cpu_has_work(CPUState *cs)
44
- tcg_temp_free_i32(t0);
96
{
45
- tcg_temp_free_i32(t1);
97
/* Here we are checking to see if the CPU should wake up from HALT.
46
+ if (arith) {
98
@@ -XXX,XX +XXX,XX @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data)
47
+ tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
99
cc->has_work = alpha_cpu_has_work;
48
+ } else {
100
cc->dump_state = alpha_cpu_dump_state;
49
+ tcg_gen_shri_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
101
cc->set_pc = alpha_cpu_set_pc;
50
+ }
102
+ cc->get_pc = alpha_cpu_get_pc;
103
cc->gdb_read_register = alpha_cpu_gdb_read_register;
104
cc->gdb_write_register = alpha_cpu_gdb_write_register;
105
#ifndef CONFIG_USER_ONLY
106
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
107
index XXXXXXX..XXXXXXX 100644
108
--- a/target/arm/cpu.c
109
+++ b/target/arm/cpu.c
110
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value)
111
}
112
}
113
114
+static vaddr arm_cpu_get_pc(CPUState *cs)
115
+{
116
+ ARMCPU *cpu = ARM_CPU(cs);
117
+ CPUARMState *env = &cpu->env;
118
+
119
+ if (is_a64(env)) {
120
+ return env->pc;
51
+ } else {
121
+ } else {
52
+ if (TCG_TARGET_HAS_extract2_i32) {
122
+ return env->regs[15];
53
+ tcg_gen_extract2_i32(TCGV_HIGH(ret),
123
+ }
54
+ TCGV_LOW(arg1), TCGV_HIGH(arg1), 32 - c);
124
+}
55
+ } else {
125
+
56
+ TCGv_i32 t0 = tcg_temp_new_i32();
126
#ifdef CONFIG_TCG
57
+ tcg_gen_shri_i32(t0, TCGV_LOW(arg1), 32 - c);
127
void arm_cpu_synchronize_from_tb(CPUState *cs,
58
+ tcg_gen_deposit_i32(TCGV_HIGH(ret), t0,
128
const TranslationBlock *tb)
59
+ TCGV_HIGH(arg1), c, 32 - c);
129
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)
60
+ tcg_temp_free_i32(t0);
130
cc->has_work = arm_cpu_has_work;
61
+ }
131
cc->dump_state = arm_cpu_dump_state;
62
+ tcg_gen_shli_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
132
cc->set_pc = arm_cpu_set_pc;
133
+ cc->get_pc = arm_cpu_get_pc;
134
cc->gdb_read_register = arm_cpu_gdb_read_register;
135
cc->gdb_write_register = arm_cpu_gdb_write_register;
136
#ifndef CONFIG_USER_ONLY
137
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
138
index XXXXXXX..XXXXXXX 100644
139
--- a/target/avr/cpu.c
140
+++ b/target/avr/cpu.c
141
@@ -XXX,XX +XXX,XX @@ static void avr_cpu_set_pc(CPUState *cs, vaddr value)
142
cpu->env.pc_w = value / 2; /* internally PC points to words */
143
}
144
145
+static vaddr avr_cpu_get_pc(CPUState *cs)
146
+{
147
+ AVRCPU *cpu = AVR_CPU(cs);
148
+
149
+ return cpu->env.pc_w * 2;
150
+}
151
+
152
static bool avr_cpu_has_work(CPUState *cs)
153
{
154
AVRCPU *cpu = AVR_CPU(cs);
155
@@ -XXX,XX +XXX,XX @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
156
cc->has_work = avr_cpu_has_work;
157
cc->dump_state = avr_cpu_dump_state;
158
cc->set_pc = avr_cpu_set_pc;
159
+ cc->get_pc = avr_cpu_get_pc;
160
dc->vmsd = &vms_avr_cpu;
161
cc->sysemu_ops = &avr_sysemu_ops;
162
cc->disas_set_info = avr_cpu_disas_set_info;
163
diff --git a/target/cris/cpu.c b/target/cris/cpu.c
164
index XXXXXXX..XXXXXXX 100644
165
--- a/target/cris/cpu.c
166
+++ b/target/cris/cpu.c
167
@@ -XXX,XX +XXX,XX @@ static void cris_cpu_set_pc(CPUState *cs, vaddr value)
168
cpu->env.pc = value;
169
}
170
171
+static vaddr cris_cpu_get_pc(CPUState *cs)
172
+{
173
+ CRISCPU *cpu = CRIS_CPU(cs);
174
+
175
+ return cpu->env.pc;
176
+}
177
+
178
static bool cris_cpu_has_work(CPUState *cs)
179
{
180
return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
181
@@ -XXX,XX +XXX,XX @@ static void cris_cpu_class_init(ObjectClass *oc, void *data)
182
cc->has_work = cris_cpu_has_work;
183
cc->dump_state = cris_cpu_dump_state;
184
cc->set_pc = cris_cpu_set_pc;
185
+ cc->get_pc = cris_cpu_get_pc;
186
cc->gdb_read_register = cris_cpu_gdb_read_register;
187
cc->gdb_write_register = cris_cpu_gdb_write_register;
188
#ifndef CONFIG_USER_ONLY
189
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
190
index XXXXXXX..XXXXXXX 100644
191
--- a/target/hexagon/cpu.c
192
+++ b/target/hexagon/cpu.c
193
@@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_set_pc(CPUState *cs, vaddr value)
194
env->gpr[HEX_REG_PC] = value;
195
}
196
197
+static vaddr hexagon_cpu_get_pc(CPUState *cs)
198
+{
199
+ HexagonCPU *cpu = HEXAGON_CPU(cs);
200
+ CPUHexagonState *env = &cpu->env;
201
+ return env->gpr[HEX_REG_PC];
202
+}
203
+
204
static void hexagon_cpu_synchronize_from_tb(CPUState *cs,
205
const TranslationBlock *tb)
206
{
207
@@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data)
208
cc->has_work = hexagon_cpu_has_work;
209
cc->dump_state = hexagon_dump_state;
210
cc->set_pc = hexagon_cpu_set_pc;
211
+ cc->get_pc = hexagon_cpu_get_pc;
212
cc->gdb_read_register = hexagon_gdb_read_register;
213
cc->gdb_write_register = hexagon_gdb_write_register;
214
cc->gdb_num_core_regs = TOTAL_PER_THREAD_REGS + NUM_VREGS + NUM_QREGS;
215
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
216
index XXXXXXX..XXXXXXX 100644
217
--- a/target/hppa/cpu.c
218
+++ b/target/hppa/cpu.c
219
@@ -XXX,XX +XXX,XX @@ static void hppa_cpu_set_pc(CPUState *cs, vaddr value)
220
cpu->env.iaoq_b = value + 4;
221
}
222
223
+static vaddr hppa_cpu_get_pc(CPUState *cs)
224
+{
225
+ HPPACPU *cpu = HPPA_CPU(cs);
226
+
227
+ return cpu->env.iaoq_f;
228
+}
229
+
230
static void hppa_cpu_synchronize_from_tb(CPUState *cs,
231
const TranslationBlock *tb)
232
{
233
@@ -XXX,XX +XXX,XX @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data)
234
cc->has_work = hppa_cpu_has_work;
235
cc->dump_state = hppa_cpu_dump_state;
236
cc->set_pc = hppa_cpu_set_pc;
237
+ cc->get_pc = hppa_cpu_get_pc;
238
cc->gdb_read_register = hppa_cpu_gdb_read_register;
239
cc->gdb_write_register = hppa_cpu_gdb_write_register;
240
#ifndef CONFIG_USER_ONLY
241
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
242
index XXXXXXX..XXXXXXX 100644
243
--- a/target/i386/cpu.c
244
+++ b/target/i386/cpu.c
245
@@ -XXX,XX +XXX,XX @@ static void x86_cpu_set_pc(CPUState *cs, vaddr value)
246
cpu->env.eip = value;
247
}
248
249
+static vaddr x86_cpu_get_pc(CPUState *cs)
250
+{
251
+ X86CPU *cpu = X86_CPU(cs);
252
+
253
+ /* Match cpu_get_tb_cpu_state. */
254
+ return cpu->env.eip + cpu->env.segs[R_CS].base;
255
+}
256
+
257
int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request)
258
{
259
X86CPU *cpu = X86_CPU(cs);
260
@@ -XXX,XX +XXX,XX @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
261
cc->has_work = x86_cpu_has_work;
262
cc->dump_state = x86_cpu_dump_state;
263
cc->set_pc = x86_cpu_set_pc;
264
+ cc->get_pc = x86_cpu_get_pc;
265
cc->gdb_read_register = x86_cpu_gdb_read_register;
266
cc->gdb_write_register = x86_cpu_gdb_write_register;
267
cc->get_arch_id = x86_cpu_get_arch_id;
268
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
269
index XXXXXXX..XXXXXXX 100644
270
--- a/target/loongarch/cpu.c
271
+++ b/target/loongarch/cpu.c
272
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_set_pc(CPUState *cs, vaddr value)
273
env->pc = value;
274
}
275
276
+static vaddr loongarch_cpu_get_pc(CPUState *cs)
277
+{
278
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
279
+ CPULoongArchState *env = &cpu->env;
280
+
281
+ return env->pc;
282
+}
283
+
284
#ifndef CONFIG_USER_ONLY
285
#include "hw/loongarch/virt.h"
286
287
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
288
cc->has_work = loongarch_cpu_has_work;
289
cc->dump_state = loongarch_cpu_dump_state;
290
cc->set_pc = loongarch_cpu_set_pc;
291
+ cc->get_pc = loongarch_cpu_get_pc;
292
#ifndef CONFIG_USER_ONLY
293
dc->vmsd = &vmstate_loongarch_cpu;
294
cc->sysemu_ops = &loongarch_sysemu_ops;
295
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
296
index XXXXXXX..XXXXXXX 100644
297
--- a/target/m68k/cpu.c
298
+++ b/target/m68k/cpu.c
299
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_set_pc(CPUState *cs, vaddr value)
300
cpu->env.pc = value;
301
}
302
303
+static vaddr m68k_cpu_get_pc(CPUState *cs)
304
+{
305
+ M68kCPU *cpu = M68K_CPU(cs);
306
+
307
+ return cpu->env.pc;
308
+}
309
+
310
static bool m68k_cpu_has_work(CPUState *cs)
311
{
312
return cs->interrupt_request & CPU_INTERRUPT_HARD;
313
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
314
cc->has_work = m68k_cpu_has_work;
315
cc->dump_state = m68k_cpu_dump_state;
316
cc->set_pc = m68k_cpu_set_pc;
317
+ cc->get_pc = m68k_cpu_get_pc;
318
cc->gdb_read_register = m68k_cpu_gdb_read_register;
319
cc->gdb_write_register = m68k_cpu_gdb_write_register;
320
#if defined(CONFIG_SOFTMMU)
321
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
322
index XXXXXXX..XXXXXXX 100644
323
--- a/target/microblaze/cpu.c
324
+++ b/target/microblaze/cpu.c
325
@@ -XXX,XX +XXX,XX @@ static void mb_cpu_set_pc(CPUState *cs, vaddr value)
326
cpu->env.iflags = 0;
327
}
328
329
+static vaddr mb_cpu_get_pc(CPUState *cs)
330
+{
331
+ MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
332
+
333
+ return cpu->env.pc;
334
+}
335
+
336
static void mb_cpu_synchronize_from_tb(CPUState *cs,
337
const TranslationBlock *tb)
338
{
339
@@ -XXX,XX +XXX,XX @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
340
341
cc->dump_state = mb_cpu_dump_state;
342
cc->set_pc = mb_cpu_set_pc;
343
+ cc->get_pc = mb_cpu_get_pc;
344
cc->gdb_read_register = mb_cpu_gdb_read_register;
345
cc->gdb_write_register = mb_cpu_gdb_write_register;
346
347
diff --git a/target/mips/cpu.c b/target/mips/cpu.c
348
index XXXXXXX..XXXXXXX 100644
349
--- a/target/mips/cpu.c
350
+++ b/target/mips/cpu.c
351
@@ -XXX,XX +XXX,XX @@ static void mips_cpu_set_pc(CPUState *cs, vaddr value)
352
mips_env_set_pc(&cpu->env, value);
353
}
354
355
+static vaddr mips_cpu_get_pc(CPUState *cs)
356
+{
357
+ MIPSCPU *cpu = MIPS_CPU(cs);
358
+
359
+ return cpu->env.active_tc.PC;
360
+}
361
+
362
static bool mips_cpu_has_work(CPUState *cs)
363
{
364
MIPSCPU *cpu = MIPS_CPU(cs);
365
@@ -XXX,XX +XXX,XX @@ static void mips_cpu_class_init(ObjectClass *c, void *data)
366
cc->has_work = mips_cpu_has_work;
367
cc->dump_state = mips_cpu_dump_state;
368
cc->set_pc = mips_cpu_set_pc;
369
+ cc->get_pc = mips_cpu_get_pc;
370
cc->gdb_read_register = mips_cpu_gdb_read_register;
371
cc->gdb_write_register = mips_cpu_gdb_write_register;
372
#ifndef CONFIG_USER_ONLY
373
diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c
374
index XXXXXXX..XXXXXXX 100644
375
--- a/target/nios2/cpu.c
376
+++ b/target/nios2/cpu.c
377
@@ -XXX,XX +XXX,XX @@ static void nios2_cpu_set_pc(CPUState *cs, vaddr value)
378
env->pc = value;
379
}
380
381
+static vaddr nios2_cpu_get_pc(CPUState *cs)
382
+{
383
+ Nios2CPU *cpu = NIOS2_CPU(cs);
384
+ CPUNios2State *env = &cpu->env;
385
+
386
+ return env->pc;
387
+}
388
+
389
static bool nios2_cpu_has_work(CPUState *cs)
390
{
391
return cs->interrupt_request & CPU_INTERRUPT_HARD;
392
@@ -XXX,XX +XXX,XX @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data)
393
cc->has_work = nios2_cpu_has_work;
394
cc->dump_state = nios2_cpu_dump_state;
395
cc->set_pc = nios2_cpu_set_pc;
396
+ cc->get_pc = nios2_cpu_get_pc;
397
cc->disas_set_info = nios2_cpu_disas_set_info;
398
#ifndef CONFIG_USER_ONLY
399
cc->sysemu_ops = &nios2_sysemu_ops;
400
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
401
index XXXXXXX..XXXXXXX 100644
402
--- a/target/openrisc/cpu.c
403
+++ b/target/openrisc/cpu.c
404
@@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
405
cpu->env.dflag = 0;
406
}
407
408
+static vaddr openrisc_cpu_get_pc(CPUState *cs)
409
+{
410
+ OpenRISCCPU *cpu = OPENRISC_CPU(cs);
411
+
412
+ return cpu->env.pc;
413
+}
414
+
415
static void openrisc_cpu_synchronize_from_tb(CPUState *cs,
416
const TranslationBlock *tb)
417
{
418
@@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
419
cc->has_work = openrisc_cpu_has_work;
420
cc->dump_state = openrisc_cpu_dump_state;
421
cc->set_pc = openrisc_cpu_set_pc;
422
+ cc->get_pc = openrisc_cpu_get_pc;
423
cc->gdb_read_register = openrisc_cpu_gdb_read_register;
424
cc->gdb_write_register = openrisc_cpu_gdb_write_register;
425
#ifndef CONFIG_USER_ONLY
426
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
427
index XXXXXXX..XXXXXXX 100644
428
--- a/target/ppc/cpu_init.c
429
+++ b/target/ppc/cpu_init.c
430
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
431
cpu->env.nip = value;
432
}
433
434
+static vaddr ppc_cpu_get_pc(CPUState *cs)
435
+{
436
+ PowerPCCPU *cpu = POWERPC_CPU(cs);
437
+
438
+ return cpu->env.nip;
439
+}
440
+
441
static bool ppc_cpu_has_work(CPUState *cs)
442
{
443
PowerPCCPU *cpu = POWERPC_CPU(cs);
444
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data)
445
cc->has_work = ppc_cpu_has_work;
446
cc->dump_state = ppc_cpu_dump_state;
447
cc->set_pc = ppc_cpu_set_pc;
448
+ cc->get_pc = ppc_cpu_get_pc;
449
cc->gdb_read_register = ppc_cpu_gdb_read_register;
450
cc->gdb_write_register = ppc_cpu_gdb_write_register;
451
#ifndef CONFIG_USER_ONLY
452
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
453
index XXXXXXX..XXXXXXX 100644
454
--- a/target/riscv/cpu.c
455
+++ b/target/riscv/cpu.c
456
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
63
}
457
}
64
}
458
}
65
459
460
+static vaddr riscv_cpu_get_pc(CPUState *cs)
461
+{
462
+ RISCVCPU *cpu = RISCV_CPU(cs);
463
+ CPURISCVState *env = &cpu->env;
464
+
465
+ /* Match cpu_get_tb_cpu_state. */
466
+ if (env->xl == MXL_RV32) {
467
+ return env->pc & UINT32_MAX;
468
+ }
469
+ return env->pc;
470
+}
471
+
472
static void riscv_cpu_synchronize_from_tb(CPUState *cs,
473
const TranslationBlock *tb)
474
{
475
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_class_init(ObjectClass *c, void *data)
476
cc->has_work = riscv_cpu_has_work;
477
cc->dump_state = riscv_cpu_dump_state;
478
cc->set_pc = riscv_cpu_set_pc;
479
+ cc->get_pc = riscv_cpu_get_pc;
480
cc->gdb_read_register = riscv_cpu_gdb_read_register;
481
cc->gdb_write_register = riscv_cpu_gdb_write_register;
482
cc->gdb_num_core_regs = 33;
483
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
484
index XXXXXXX..XXXXXXX 100644
485
--- a/target/rx/cpu.c
486
+++ b/target/rx/cpu.c
487
@@ -XXX,XX +XXX,XX @@ static void rx_cpu_set_pc(CPUState *cs, vaddr value)
488
cpu->env.pc = value;
489
}
490
491
+static vaddr rx_cpu_get_pc(CPUState *cs)
492
+{
493
+ RXCPU *cpu = RX_CPU(cs);
494
+
495
+ return cpu->env.pc;
496
+}
497
+
498
static void rx_cpu_synchronize_from_tb(CPUState *cs,
499
const TranslationBlock *tb)
500
{
501
@@ -XXX,XX +XXX,XX @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)
502
cc->has_work = rx_cpu_has_work;
503
cc->dump_state = rx_cpu_dump_state;
504
cc->set_pc = rx_cpu_set_pc;
505
+ cc->get_pc = rx_cpu_get_pc;
506
507
#ifndef CONFIG_USER_ONLY
508
cc->sysemu_ops = &rx_sysemu_ops;
509
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
510
index XXXXXXX..XXXXXXX 100644
511
--- a/target/s390x/cpu.c
512
+++ b/target/s390x/cpu.c
513
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_set_pc(CPUState *cs, vaddr value)
514
cpu->env.psw.addr = value;
515
}
516
517
+static vaddr s390_cpu_get_pc(CPUState *cs)
518
+{
519
+ S390CPU *cpu = S390_CPU(cs);
520
+
521
+ return cpu->env.psw.addr;
522
+}
523
+
524
static bool s390_cpu_has_work(CPUState *cs)
525
{
526
S390CPU *cpu = S390_CPU(cs);
527
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)
528
cc->has_work = s390_cpu_has_work;
529
cc->dump_state = s390_cpu_dump_state;
530
cc->set_pc = s390_cpu_set_pc;
531
+ cc->get_pc = s390_cpu_get_pc;
532
cc->gdb_read_register = s390_cpu_gdb_read_register;
533
cc->gdb_write_register = s390_cpu_gdb_write_register;
534
#ifndef CONFIG_USER_ONLY
535
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
536
index XXXXXXX..XXXXXXX 100644
537
--- a/target/sh4/cpu.c
538
+++ b/target/sh4/cpu.c
539
@@ -XXX,XX +XXX,XX @@ static void superh_cpu_set_pc(CPUState *cs, vaddr value)
540
cpu->env.pc = value;
541
}
542
543
+static vaddr superh_cpu_get_pc(CPUState *cs)
544
+{
545
+ SuperHCPU *cpu = SUPERH_CPU(cs);
546
+
547
+ return cpu->env.pc;
548
+}
549
+
550
static void superh_cpu_synchronize_from_tb(CPUState *cs,
551
const TranslationBlock *tb)
552
{
553
@@ -XXX,XX +XXX,XX @@ static void superh_cpu_class_init(ObjectClass *oc, void *data)
554
cc->has_work = superh_cpu_has_work;
555
cc->dump_state = superh_cpu_dump_state;
556
cc->set_pc = superh_cpu_set_pc;
557
+ cc->get_pc = superh_cpu_get_pc;
558
cc->gdb_read_register = superh_cpu_gdb_read_register;
559
cc->gdb_write_register = superh_cpu_gdb_write_register;
560
#ifndef CONFIG_USER_ONLY
561
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
562
index XXXXXXX..XXXXXXX 100644
563
--- a/target/sparc/cpu.c
564
+++ b/target/sparc/cpu.c
565
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_set_pc(CPUState *cs, vaddr value)
566
cpu->env.npc = value + 4;
567
}
568
569
+static vaddr sparc_cpu_get_pc(CPUState *cs)
570
+{
571
+ SPARCCPU *cpu = SPARC_CPU(cs);
572
+
573
+ return cpu->env.pc;
574
+}
575
+
576
static void sparc_cpu_synchronize_from_tb(CPUState *cs,
577
const TranslationBlock *tb)
578
{
579
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data)
580
cc->memory_rw_debug = sparc_cpu_memory_rw_debug;
581
#endif
582
cc->set_pc = sparc_cpu_set_pc;
583
+ cc->get_pc = sparc_cpu_get_pc;
584
cc->gdb_read_register = sparc_cpu_gdb_read_register;
585
cc->gdb_write_register = sparc_cpu_gdb_write_register;
586
#ifndef CONFIG_USER_ONLY
587
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
588
index XXXXXXX..XXXXXXX 100644
589
--- a/target/tricore/cpu.c
590
+++ b/target/tricore/cpu.c
591
@@ -XXX,XX +XXX,XX @@ static void tricore_cpu_set_pc(CPUState *cs, vaddr value)
592
env->PC = value & ~(target_ulong)1;
593
}
594
595
+static vaddr tricore_cpu_get_pc(CPUState *cs)
596
+{
597
+ TriCoreCPU *cpu = TRICORE_CPU(cs);
598
+ CPUTriCoreState *env = &cpu->env;
599
+
600
+ return env->PC;
601
+}
602
+
603
static void tricore_cpu_synchronize_from_tb(CPUState *cs,
604
const TranslationBlock *tb)
605
{
606
@@ -XXX,XX +XXX,XX @@ static void tricore_cpu_class_init(ObjectClass *c, void *data)
607
608
cc->dump_state = tricore_cpu_dump_state;
609
cc->set_pc = tricore_cpu_set_pc;
610
+ cc->get_pc = tricore_cpu_get_pc;
611
cc->sysemu_ops = &tricore_sysemu_ops;
612
cc->tcg_ops = &tricore_tcg_ops;
613
}
614
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
615
index XXXXXXX..XXXXXXX 100644
616
--- a/target/xtensa/cpu.c
617
+++ b/target/xtensa/cpu.c
618
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
619
cpu->env.pc = value;
620
}
621
622
+static vaddr xtensa_cpu_get_pc(CPUState *cs)
623
+{
624
+ XtensaCPU *cpu = XTENSA_CPU(cs);
625
+
626
+ return cpu->env.pc;
627
+}
628
+
629
static bool xtensa_cpu_has_work(CPUState *cs)
630
{
631
#ifndef CONFIG_USER_ONLY
632
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
633
cc->has_work = xtensa_cpu_has_work;
634
cc->dump_state = xtensa_cpu_dump_state;
635
cc->set_pc = xtensa_cpu_set_pc;
636
+ cc->get_pc = xtensa_cpu_get_pc;
637
cc->gdb_read_register = xtensa_cpu_gdb_read_register;
638
cc->gdb_write_register = xtensa_cpu_gdb_write_register;
639
cc->gdb_stop_before_watchpoint = true;
66
--
640
--
67
2.17.1
641
2.34.1
68
642
69
643
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/15] tcg: Restart after TB code generation overflow
[PULL 17/20] accel/tcg: Introduce tb_pc and log_pc
1
If a TB generates too much code, try again with fewer insns.
1
The availability of tb->pc will shortly be conditional.
2
Introduce accessor functions to minimize ifdefs.
2
3
3
Fixes: https://bugs.launchpad.net/bugs/1824853
4
Pass around a known pc to places like tcg_gen_code,
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
where the caller must already have the value.
6
7
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
9
---
7
accel/tcg/translate-all.c | 38 ++++++++++++++++++++++++++++++++------
10
accel/tcg/internal.h | 6 ++++
8
tcg/tcg.c | 4 ++++
11
include/exec/exec-all.h | 6 ++++
9
2 files changed, 36 insertions(+), 6 deletions(-)
12
include/tcg/tcg.h | 2 +-
13
accel/tcg/cpu-exec.c | 46 ++++++++++++++-----------
14
accel/tcg/translate-all.c | 37 +++++++++++---------
15
target/arm/cpu.c | 4 +--
16
target/avr/cpu.c | 2 +-
17
target/hexagon/cpu.c | 2 +-
18
target/hppa/cpu.c | 4 +--
19
target/i386/tcg/tcg-cpu.c | 2 +-
20
target/loongarch/cpu.c | 2 +-
21
target/microblaze/cpu.c | 2 +-
22
target/mips/tcg/exception.c | 2 +-
23
target/mips/tcg/sysemu/special_helper.c | 2 +-
24
target/openrisc/cpu.c | 2 +-
25
target/riscv/cpu.c | 4 +--
26
target/rx/cpu.c | 2 +-
27
target/sh4/cpu.c | 4 +--
28
target/sparc/cpu.c | 2 +-
29
target/tricore/cpu.c | 2 +-
30
tcg/tcg.c | 8 ++---
31
21 files changed, 82 insertions(+), 61 deletions(-)
10
32
33
diff --git a/accel/tcg/internal.h b/accel/tcg/internal.h
34
index XXXXXXX..XXXXXXX 100644
35
--- a/accel/tcg/internal.h
36
+++ b/accel/tcg/internal.h
37
@@ -XXX,XX +XXX,XX @@ G_NORETURN void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr);
38
void page_init(void);
39
void tb_htable_init(void);
40
41
+/* Return the current PC from CPU, which may be cached in TB. */
42
+static inline target_ulong log_pc(CPUState *cpu, const TranslationBlock *tb)
43
+{
44
+ return tb_pc(tb);
45
+}
46
+
47
#endif /* ACCEL_TCG_INTERNAL_H */
48
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
49
index XXXXXXX..XXXXXXX 100644
50
--- a/include/exec/exec-all.h
51
+++ b/include/exec/exec-all.h
52
@@ -XXX,XX +XXX,XX @@ struct TranslationBlock {
53
uintptr_t jmp_dest[2];
54
};
55
56
+/* Hide the read to avoid ifdefs for TARGET_TB_PCREL. */
57
+static inline target_ulong tb_pc(const TranslationBlock *tb)
58
+{
59
+ return tb->pc;
60
+}
61
+
62
/* Hide the qatomic_read to make code a little easier on the eyes */
63
static inline uint32_t tb_cflags(const TranslationBlock *tb)
64
{
65
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
66
index XXXXXXX..XXXXXXX 100644
67
--- a/include/tcg/tcg.h
68
+++ b/include/tcg/tcg.h
69
@@ -XXX,XX +XXX,XX @@ void tcg_register_thread(void);
70
void tcg_prologue_init(TCGContext *s);
71
void tcg_func_start(TCGContext *s);
72
73
-int tcg_gen_code(TCGContext *s, TranslationBlock *tb);
74
+int tcg_gen_code(TCGContext *s, TranslationBlock *tb, target_ulong pc_start);
75
76
void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
77
78
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
79
index XXXXXXX..XXXXXXX 100644
80
--- a/accel/tcg/cpu-exec.c
81
+++ b/accel/tcg/cpu-exec.c
82
@@ -XXX,XX +XXX,XX @@ static bool tb_lookup_cmp(const void *p, const void *d)
83
const TranslationBlock *tb = p;
84
const struct tb_desc *desc = d;
85
86
- if (tb->pc == desc->pc &&
87
+ if (tb_pc(tb) == desc->pc &&
88
tb->page_addr[0] == desc->page_addr0 &&
89
tb->cs_base == desc->cs_base &&
90
tb->flags == desc->flags &&
91
@@ -XXX,XX +XXX,XX @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc,
92
return tb;
93
}
94
95
-static inline void log_cpu_exec(target_ulong pc, CPUState *cpu,
96
- const TranslationBlock *tb)
97
+static void log_cpu_exec(target_ulong pc, CPUState *cpu,
98
+ const TranslationBlock *tb)
99
{
100
- if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC))
101
- && qemu_log_in_addr_range(pc)) {
102
-
103
+ if (qemu_log_in_addr_range(pc)) {
104
qemu_log_mask(CPU_LOG_EXEC,
105
"Trace %d: %p [" TARGET_FMT_lx
106
"/" TARGET_FMT_lx "/%08x/%08x] %s\n",
107
@@ -XXX,XX +XXX,XX @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env)
108
return tcg_code_gen_epilogue;
109
}
110
111
- log_cpu_exec(pc, cpu, tb);
112
+ if (qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) {
113
+ log_cpu_exec(pc, cpu, tb);
114
+ }
115
116
return tb->tc.ptr;
117
}
118
@@ -XXX,XX +XXX,XX @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
119
TranslationBlock *last_tb;
120
const void *tb_ptr = itb->tc.ptr;
121
122
- log_cpu_exec(itb->pc, cpu, itb);
123
+ if (qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) {
124
+ log_cpu_exec(log_pc(cpu, itb), cpu, itb);
125
+ }
126
127
qemu_thread_jit_execute();
128
ret = tcg_qemu_tb_exec(env, tb_ptr);
129
@@ -XXX,XX +XXX,XX @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
130
* of the start of the TB.
131
*/
132
CPUClass *cc = CPU_GET_CLASS(cpu);
133
- qemu_log_mask_and_addr(CPU_LOG_EXEC, last_tb->pc,
134
- "Stopped execution of TB chain before %p ["
135
- TARGET_FMT_lx "] %s\n",
136
- last_tb->tc.ptr, last_tb->pc,
137
- lookup_symbol(last_tb->pc));
138
+
139
if (cc->tcg_ops->synchronize_from_tb) {
140
cc->tcg_ops->synchronize_from_tb(cpu, last_tb);
141
} else {
142
assert(cc->set_pc);
143
- cc->set_pc(cpu, last_tb->pc);
144
+ cc->set_pc(cpu, tb_pc(last_tb));
145
+ }
146
+ if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
147
+ target_ulong pc = log_pc(cpu, last_tb);
148
+ if (qemu_log_in_addr_range(pc)) {
149
+ qemu_log("Stopped execution of TB chain before %p ["
150
+ TARGET_FMT_lx "] %s\n",
151
+ last_tb->tc.ptr, pc, lookup_symbol(pc));
152
+ }
153
}
154
}
155
156
@@ -XXX,XX +XXX,XX @@ static inline void tb_add_jump(TranslationBlock *tb, int n,
157
158
qemu_spin_unlock(&tb_next->jmp_lock);
159
160
- qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc,
161
- "Linking TBs %p [" TARGET_FMT_lx
162
- "] index %d -> %p [" TARGET_FMT_lx "]\n",
163
- tb->tc.ptr, tb->pc, n,
164
- tb_next->tc.ptr, tb_next->pc);
165
+ qemu_log_mask(CPU_LOG_EXEC, "Linking TBs %p index %d -> %p\n",
166
+ tb->tc.ptr, n, tb_next->tc.ptr);
167
return;
168
169
out_unlock_next:
170
@@ -XXX,XX +XXX,XX @@ static inline bool cpu_handle_interrupt(CPUState *cpu,
171
}
172
173
static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb,
174
+ target_ulong pc,
175
TranslationBlock **last_tb, int *tb_exit)
176
{
177
int32_t insns_left;
178
179
- trace_exec_tb(tb, tb->pc);
180
+ trace_exec_tb(tb, pc);
181
tb = cpu_tb_exec(cpu, tb, tb_exit);
182
if (*tb_exit != TB_EXIT_REQUESTED) {
183
*last_tb = tb;
184
@@ -XXX,XX +XXX,XX @@ int cpu_exec(CPUState *cpu)
185
tb_add_jump(last_tb, tb_exit, tb);
186
}
187
188
- cpu_loop_exec_tb(cpu, tb, &last_tb, &tb_exit);
189
+ cpu_loop_exec_tb(cpu, tb, pc, &last_tb, &tb_exit);
190
191
/* Try to align the host and virtual clocks
192
if the guest is in advance */
11
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
193
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
12
index XXXXXXX..XXXXXXX 100644
194
index XXXXXXX..XXXXXXX 100644
13
--- a/accel/tcg/translate-all.c
195
--- a/accel/tcg/translate-all.c
14
+++ b/accel/tcg/translate-all.c
196
+++ b/accel/tcg/translate-all.c
197
@@ -XXX,XX +XXX,XX @@ static int encode_search(TranslationBlock *tb, uint8_t *block)
198
199
for (j = 0; j < TARGET_INSN_START_WORDS; ++j) {
200
if (i == 0) {
201
- prev = (j == 0 ? tb->pc : 0);
202
+ prev = (j == 0 ? tb_pc(tb) : 0);
203
} else {
204
prev = tcg_ctx->gen_insn_data[i - 1][j];
205
}
206
@@ -XXX,XX +XXX,XX @@ static int encode_search(TranslationBlock *tb, uint8_t *block)
207
static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
208
uintptr_t searched_pc, bool reset_icount)
209
{
210
- target_ulong data[TARGET_INSN_START_WORDS] = { tb->pc };
211
+ target_ulong data[TARGET_INSN_START_WORDS] = { tb_pc(tb) };
212
uintptr_t host_pc = (uintptr_t)tb->tc.ptr;
213
CPUArchState *env = cpu->env_ptr;
214
const uint8_t *p = tb->tc.ptr + tb->tc.size;
215
@@ -XXX,XX +XXX,XX @@ static bool tb_cmp(const void *ap, const void *bp)
216
const TranslationBlock *a = ap;
217
const TranslationBlock *b = bp;
218
219
- return a->pc == b->pc &&
220
+ return tb_pc(a) == tb_pc(b) &&
221
a->cs_base == b->cs_base &&
222
a->flags == b->flags &&
223
(tb_cflags(a) & ~CF_INVALID) == (tb_cflags(b) & ~CF_INVALID) &&
224
@@ -XXX,XX +XXX,XX @@ static void do_tb_invalidate_check(void *p, uint32_t hash, void *userp)
225
TranslationBlock *tb = p;
226
target_ulong addr = *(target_ulong *)userp;
227
228
- if (!(addr + TARGET_PAGE_SIZE <= tb->pc || addr >= tb->pc + tb->size)) {
229
+ if (!(addr + TARGET_PAGE_SIZE <= tb_pc(tb) ||
230
+ addr >= tb_pc(tb) + tb->size)) {
231
printf("ERROR invalidate: address=" TARGET_FMT_lx
232
- " PC=%08lx size=%04x\n", addr, (long)tb->pc, tb->size);
233
+ " PC=%08lx size=%04x\n", addr, (long)tb_pc(tb), tb->size);
234
}
235
}
236
237
@@ -XXX,XX +XXX,XX @@ static void do_tb_page_check(void *p, uint32_t hash, void *userp)
238
TranslationBlock *tb = p;
239
int flags1, flags2;
240
241
- flags1 = page_get_flags(tb->pc);
242
- flags2 = page_get_flags(tb->pc + tb->size - 1);
243
+ flags1 = page_get_flags(tb_pc(tb));
244
+ flags2 = page_get_flags(tb_pc(tb) + tb->size - 1);
245
if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) {
246
printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n",
247
- (long)tb->pc, tb->size, flags1, flags2);
248
+ (long)tb_pc(tb), tb->size, flags1, flags2);
249
}
250
}
251
252
@@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
253
254
/* remove the TB from the hash list */
255
phys_pc = tb->page_addr[0];
256
- h = tb_hash_func(phys_pc, tb->pc, tb->flags, orig_cflags,
257
+ h = tb_hash_func(phys_pc, tb_pc(tb), tb->flags, orig_cflags,
258
tb->trace_vcpu_dstate);
259
if (!qht_remove(&tb_ctx.htable, tb, h)) {
260
return;
261
@@ -XXX,XX +XXX,XX @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
262
}
263
264
/* add in the hash table */
265
- h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags,
266
+ h = tb_hash_func(phys_pc, tb_pc(tb), tb->flags, tb->cflags,
267
tb->trace_vcpu_dstate);
268
qht_insert(&tb_ctx.htable, tb, h, &existing_tb);
269
15
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
270
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
16
tb->cflags = cflags;
271
tcg_ctx->cpu = NULL;
17
tb->trace_vcpu_dstate = *cpu->trace_dstate;
272
max_insns = tb->icount;
18
tcg_ctx->tb_cflags = cflags;
273
19
+ tb_overflow:
274
- trace_translate_block(tb, tb->pc, tb->tc.ptr);
20
275
+ trace_translate_block(tb, pc, tb->tc.ptr);
21
#ifdef CONFIG_PROFILER
276
22
/* includes aborted translations because of exceptions */
277
/* generate machine code */
278
tb->jmp_reset_offset[0] = TB_JMP_RESET_OFFSET_INVALID;
23
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
279
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
24
ti = profile_getclock();
280
ti = profile_getclock();
25
#endif
281
#endif
26
282
27
- /* ??? Overflow could be handled better here. In particular, we
283
- gen_code_size = tcg_gen_code(tcg_ctx, tb);
28
- don't need to re-do gen_intermediate_code, nor should we re-do
284
+ gen_code_size = tcg_gen_code(tcg_ctx, tb, pc);
29
- the tcg optimization currently hidden inside tcg_gen_code. All
30
- that should be required is to flush the TBs, allocate a new TB,
31
- re-initialize it per above, and re-do the actual code generation. */
32
gen_code_size = tcg_gen_code(tcg_ctx, tb);
33
if (unlikely(gen_code_size < 0)) {
285
if (unlikely(gen_code_size < 0)) {
34
- goto buffer_overflow;
286
error_return:
35
+ switch (gen_code_size) {
287
switch (gen_code_size) {
36
+ case -1:
288
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
37
+ /*
289
38
+ * Overflow of code_gen_buffer, or the current slice of it.
290
#ifdef DEBUG_DISAS
39
+ *
291
if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM) &&
40
+ * TODO: We don't need to re-do gen_intermediate_code, nor
292
- qemu_log_in_addr_range(tb->pc)) {
41
+ * should we re-do the tcg optimization currently hidden
293
+ qemu_log_in_addr_range(pc)) {
42
+ * inside tcg_gen_code. All that should be required is to
294
FILE *logfile = qemu_log_trylock();
43
+ * flush the TBs, allocate a new TB, re-initialize it per
295
if (logfile) {
44
+ * above, and re-do the actual code generation.
296
int code_size, data_size;
45
+ */
297
@@ -XXX,XX +XXX,XX @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
46
+ goto buffer_overflow;
298
*/
47
+
299
cpu->cflags_next_tb = curr_cflags(cpu) | CF_MEMI_ONLY | CF_LAST_IO | n;
48
+ case -2:
300
49
+ /*
301
- qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc,
50
+ * The code generated for the TranslationBlock is too large.
302
- "cpu_io_recompile: rewound execution of TB to "
51
+ * The maximum size allowed by the unwind info is 64k.
303
- TARGET_FMT_lx "\n", tb->pc);
52
+ * There may be stricter constraints from relocations
304
+ if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
53
+ * in the tcg backend.
305
+ target_ulong pc = log_pc(cpu, tb);
54
+ *
306
+ if (qemu_log_in_addr_range(pc)) {
55
+ * Try again with half as many insns as we attempted this time.
307
+ qemu_log("cpu_io_recompile: rewound execution of TB to "
56
+ * If a single insn overflows, there's a bug somewhere...
308
+ TARGET_FMT_lx "\n", pc);
57
+ */
58
+ max_insns = tb->icount;
59
+ assert(max_insns > 1);
60
+ max_insns /= 2;
61
+ goto tb_overflow;
62
+
63
+ default:
64
+ g_assert_not_reached();
65
+ }
309
+ }
66
}
310
+ }
67
search_size = encode_search(tb, (void *)gen_code_buf + gen_code_size);
311
68
if (unlikely(search_size < 0)) {
312
cpu_loop_exit_noexc(cpu);
313
}
314
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
315
index XXXXXXX..XXXXXXX 100644
316
--- a/target/arm/cpu.c
317
+++ b/target/arm/cpu.c
318
@@ -XXX,XX +XXX,XX @@ void arm_cpu_synchronize_from_tb(CPUState *cs,
319
* never possible for an AArch64 TB to chain to an AArch32 TB.
320
*/
321
if (is_a64(env)) {
322
- env->pc = tb->pc;
323
+ env->pc = tb_pc(tb);
324
} else {
325
- env->regs[15] = tb->pc;
326
+ env->regs[15] = tb_pc(tb);
327
}
328
}
329
#endif /* CONFIG_TCG */
330
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
331
index XXXXXXX..XXXXXXX 100644
332
--- a/target/avr/cpu.c
333
+++ b/target/avr/cpu.c
334
@@ -XXX,XX +XXX,XX @@ static void avr_cpu_synchronize_from_tb(CPUState *cs,
335
AVRCPU *cpu = AVR_CPU(cs);
336
CPUAVRState *env = &cpu->env;
337
338
- env->pc_w = tb->pc / 2; /* internally PC points to words */
339
+ env->pc_w = tb_pc(tb) / 2; /* internally PC points to words */
340
}
341
342
static void avr_cpu_reset(DeviceState *ds)
343
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
344
index XXXXXXX..XXXXXXX 100644
345
--- a/target/hexagon/cpu.c
346
+++ b/target/hexagon/cpu.c
347
@@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_synchronize_from_tb(CPUState *cs,
348
{
349
HexagonCPU *cpu = HEXAGON_CPU(cs);
350
CPUHexagonState *env = &cpu->env;
351
- env->gpr[HEX_REG_PC] = tb->pc;
352
+ env->gpr[HEX_REG_PC] = tb_pc(tb);
353
}
354
355
static bool hexagon_cpu_has_work(CPUState *cs)
356
diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c
357
index XXXXXXX..XXXXXXX 100644
358
--- a/target/hppa/cpu.c
359
+++ b/target/hppa/cpu.c
360
@@ -XXX,XX +XXX,XX @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs,
361
HPPACPU *cpu = HPPA_CPU(cs);
362
363
#ifdef CONFIG_USER_ONLY
364
- cpu->env.iaoq_f = tb->pc;
365
+ cpu->env.iaoq_f = tb_pc(tb);
366
cpu->env.iaoq_b = tb->cs_base;
367
#else
368
/* Recover the IAOQ values from the GVA + PRIV. */
369
@@ -XXX,XX +XXX,XX @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs,
370
int32_t diff = cs_base;
371
372
cpu->env.iasq_f = iasq_f;
373
- cpu->env.iaoq_f = (tb->pc & ~iasq_f) + priv;
374
+ cpu->env.iaoq_f = (tb_pc(tb) & ~iasq_f) + priv;
375
if (diff) {
376
cpu->env.iaoq_b = cpu->env.iaoq_f + diff;
377
}
378
diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c
379
index XXXXXXX..XXXXXXX 100644
380
--- a/target/i386/tcg/tcg-cpu.c
381
+++ b/target/i386/tcg/tcg-cpu.c
382
@@ -XXX,XX +XXX,XX @@ static void x86_cpu_synchronize_from_tb(CPUState *cs,
383
{
384
X86CPU *cpu = X86_CPU(cs);
385
386
- cpu->env.eip = tb->pc - tb->cs_base;
387
+ cpu->env.eip = tb_pc(tb) - tb->cs_base;
388
}
389
390
#ifndef CONFIG_USER_ONLY
391
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
392
index XXXXXXX..XXXXXXX 100644
393
--- a/target/loongarch/cpu.c
394
+++ b/target/loongarch/cpu.c
395
@@ -XXX,XX +XXX,XX @@ static void loongarch_cpu_synchronize_from_tb(CPUState *cs,
396
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
397
CPULoongArchState *env = &cpu->env;
398
399
- env->pc = tb->pc;
400
+ env->pc = tb_pc(tb);
401
}
402
#endif /* CONFIG_TCG */
403
404
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
405
index XXXXXXX..XXXXXXX 100644
406
--- a/target/microblaze/cpu.c
407
+++ b/target/microblaze/cpu.c
408
@@ -XXX,XX +XXX,XX @@ static void mb_cpu_synchronize_from_tb(CPUState *cs,
409
{
410
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
411
412
- cpu->env.pc = tb->pc;
413
+ cpu->env.pc = tb_pc(tb);
414
cpu->env.iflags = tb->flags & IFLAGS_TB_MASK;
415
}
416
417
diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c
418
index XXXXXXX..XXXXXXX 100644
419
--- a/target/mips/tcg/exception.c
420
+++ b/target/mips/tcg/exception.c
421
@@ -XXX,XX +XXX,XX @@ void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb)
422
MIPSCPU *cpu = MIPS_CPU(cs);
423
CPUMIPSState *env = &cpu->env;
424
425
- env->active_tc.PC = tb->pc;
426
+ env->active_tc.PC = tb_pc(tb);
427
env->hflags &= ~MIPS_HFLAG_BMASK;
428
env->hflags |= tb->flags & MIPS_HFLAG_BMASK;
429
}
430
diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/sysemu/special_helper.c
431
index XXXXXXX..XXXXXXX 100644
432
--- a/target/mips/tcg/sysemu/special_helper.c
433
+++ b/target/mips/tcg/sysemu/special_helper.c
434
@@ -XXX,XX +XXX,XX @@ bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb)
435
CPUMIPSState *env = &cpu->env;
436
437
if ((env->hflags & MIPS_HFLAG_BMASK) != 0
438
- && env->active_tc.PC != tb->pc) {
439
+ && env->active_tc.PC != tb_pc(tb)) {
440
env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
441
env->hflags &= ~MIPS_HFLAG_BMASK;
442
return true;
443
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
444
index XXXXXXX..XXXXXXX 100644
445
--- a/target/openrisc/cpu.c
446
+++ b/target/openrisc/cpu.c
447
@@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_synchronize_from_tb(CPUState *cs,
448
{
449
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
450
451
- cpu->env.pc = tb->pc;
452
+ cpu->env.pc = tb_pc(tb);
453
}
454
455
456
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
457
index XXXXXXX..XXXXXXX 100644
458
--- a/target/riscv/cpu.c
459
+++ b/target/riscv/cpu.c
460
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs,
461
RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
462
463
if (xl == MXL_RV32) {
464
- env->pc = (int32_t)tb->pc;
465
+ env->pc = (int32_t)tb_pc(tb);
466
} else {
467
- env->pc = tb->pc;
468
+ env->pc = tb_pc(tb);
469
}
470
}
471
472
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
473
index XXXXXXX..XXXXXXX 100644
474
--- a/target/rx/cpu.c
475
+++ b/target/rx/cpu.c
476
@@ -XXX,XX +XXX,XX @@ static void rx_cpu_synchronize_from_tb(CPUState *cs,
477
{
478
RXCPU *cpu = RX_CPU(cs);
479
480
- cpu->env.pc = tb->pc;
481
+ cpu->env.pc = tb_pc(tb);
482
}
483
484
static bool rx_cpu_has_work(CPUState *cs)
485
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
486
index XXXXXXX..XXXXXXX 100644
487
--- a/target/sh4/cpu.c
488
+++ b/target/sh4/cpu.c
489
@@ -XXX,XX +XXX,XX @@ static void superh_cpu_synchronize_from_tb(CPUState *cs,
490
{
491
SuperHCPU *cpu = SUPERH_CPU(cs);
492
493
- cpu->env.pc = tb->pc;
494
+ cpu->env.pc = tb_pc(tb);
495
cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK;
496
}
497
498
@@ -XXX,XX +XXX,XX @@ static bool superh_io_recompile_replay_branch(CPUState *cs,
499
CPUSH4State *env = &cpu->env;
500
501
if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0
502
- && env->pc != tb->pc) {
503
+ && env->pc != tb_pc(tb)) {
504
env->pc -= 2;
505
env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
506
return true;
507
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
508
index XXXXXXX..XXXXXXX 100644
509
--- a/target/sparc/cpu.c
510
+++ b/target/sparc/cpu.c
511
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs,
512
{
513
SPARCCPU *cpu = SPARC_CPU(cs);
514
515
- cpu->env.pc = tb->pc;
516
+ cpu->env.pc = tb_pc(tb);
517
cpu->env.npc = tb->cs_base;
518
}
519
520
diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c
521
index XXXXXXX..XXXXXXX 100644
522
--- a/target/tricore/cpu.c
523
+++ b/target/tricore/cpu.c
524
@@ -XXX,XX +XXX,XX @@ static void tricore_cpu_synchronize_from_tb(CPUState *cs,
525
TriCoreCPU *cpu = TRICORE_CPU(cs);
526
CPUTriCoreState *env = &cpu->env;
527
528
- env->PC = tb->pc;
529
+ env->PC = tb_pc(tb);
530
}
531
532
static void tricore_cpu_reset(DeviceState *dev)
69
diff --git a/tcg/tcg.c b/tcg/tcg.c
533
diff --git a/tcg/tcg.c b/tcg/tcg.c
70
index XXXXXXX..XXXXXXX 100644
534
index XXXXXXX..XXXXXXX 100644
71
--- a/tcg/tcg.c
535
--- a/tcg/tcg.c
72
+++ b/tcg/tcg.c
536
+++ b/tcg/tcg.c
537
@@ -XXX,XX +XXX,XX @@ int64_t tcg_cpu_exec_time(void)
538
#endif
539
540
541
-int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
542
+int tcg_gen_code(TCGContext *s, TranslationBlock *tb, target_ulong pc_start)
543
{
544
#ifdef CONFIG_PROFILER
545
TCGProfile *prof = &s->prof;
73
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
546
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
74
if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) {
547
75
return -1;
548
#ifdef DEBUG_DISAS
76
}
549
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)
77
+ /* Test for TB overflow, as seen by gen_insn_end_off. */
550
- && qemu_log_in_addr_range(tb->pc))) {
78
+ if (unlikely(tcg_current_code_size(s) > UINT16_MAX)) {
551
+ && qemu_log_in_addr_range(pc_start))) {
79
+ return -2;
552
FILE *logfile = qemu_log_trylock();
80
+ }
553
if (logfile) {
81
}
554
fprintf(logfile, "OP:\n");
82
tcg_debug_assert(num_insns >= 0);
555
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
83
s->gen_insn_end_off[num_insns] = tcg_current_code_size(s);
556
if (s->nb_indirects > 0) {
557
#ifdef DEBUG_DISAS
558
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND)
559
- && qemu_log_in_addr_range(tb->pc))) {
560
+ && qemu_log_in_addr_range(pc_start))) {
561
FILE *logfile = qemu_log_trylock();
562
if (logfile) {
563
fprintf(logfile, "OP before indirect lowering:\n");
564
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
565
566
#ifdef DEBUG_DISAS
567
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT)
568
- && qemu_log_in_addr_range(tb->pc))) {
569
+ && qemu_log_in_addr_range(pc_start))) {
570
FILE *logfile = qemu_log_trylock();
571
if (logfile) {
572
fprintf(logfile, "OP after optimization and liveness analysis:\n");
84
--
573
--
85
2.17.1
574
2.34.1
86
575
87
576
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/15] tcg: Restart TB generation after relocation overflow
[PULL 18/20] accel/tcg: Introduce TARGET_TB_PCREL
1
If the TB generates too much code, such that backend relocations
1
Prepare for targets to be able to produce TBs that can
2
overflow, try again with a smaller TB. In support of this, move
2
run in more than one virtual context.
3
relocation processing from a random place within tcg_out_op, in
4
the handling of branch opcodes, to a new function at the end of
5
tcg_gen_code.
6
3
7
This is not a complete solution, as there are additional relocs
4
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
8
generated for out-of-line ldst handling and constant pools.
9
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
6
---
12
tcg/tcg.h | 15 +++++++-------
7
accel/tcg/internal.h | 4 +++
13
tcg/tcg.c | 61 ++++++++++++++++++++++++++-----------------------------
8
accel/tcg/tb-jmp-cache.h | 41 +++++++++++++++++++++++++
14
2 files changed, 36 insertions(+), 40 deletions(-)
9
include/exec/cpu-defs.h | 3 ++
10
include/exec/exec-all.h | 32 ++++++++++++++++++--
11
accel/tcg/cpu-exec.c | 16 ++++++----
12
accel/tcg/translate-all.c | 64 ++++++++++++++++++++++++++-------------
13
6 files changed, 131 insertions(+), 29 deletions(-)
15
14
16
diff --git a/tcg/tcg.h b/tcg/tcg.h
15
diff --git a/accel/tcg/internal.h b/accel/tcg/internal.h
17
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
18
--- a/tcg/tcg.h
17
--- a/accel/tcg/internal.h
19
+++ b/tcg/tcg.h
18
+++ b/accel/tcg/internal.h
20
@@ -XXX,XX +XXX,XX @@ typedef uint64_t tcg_insn_unit;
19
@@ -XXX,XX +XXX,XX @@ void tb_htable_init(void);
21
do { if (!(X)) { __builtin_unreachable(); } } while (0)
20
/* Return the current PC from CPU, which may be cached in TB. */
21
static inline target_ulong log_pc(CPUState *cpu, const TranslationBlock *tb)
22
{
23
+#if TARGET_TB_PCREL
24
+ return cpu->cc->get_pc(cpu);
25
+#else
26
return tb_pc(tb);
27
+#endif
28
}
29
30
#endif /* ACCEL_TCG_INTERNAL_H */
31
diff --git a/accel/tcg/tb-jmp-cache.h b/accel/tcg/tb-jmp-cache.h
32
index XXXXXXX..XXXXXXX 100644
33
--- a/accel/tcg/tb-jmp-cache.h
34
+++ b/accel/tcg/tb-jmp-cache.h
35
@@ -XXX,XX +XXX,XX @@
36
37
/*
38
* Accessed in parallel; all accesses to 'tb' must be atomic.
39
+ * For TARGET_TB_PCREL, accesses to 'pc' must be protected by
40
+ * a load_acquire/store_release to 'tb'.
41
*/
42
struct CPUJumpCache {
43
struct {
44
TranslationBlock *tb;
45
+#if TARGET_TB_PCREL
46
+ target_ulong pc;
47
+#endif
48
} array[TB_JMP_CACHE_SIZE];
49
};
50
51
+static inline TranslationBlock *
52
+tb_jmp_cache_get_tb(CPUJumpCache *jc, uint32_t hash)
53
+{
54
+#if TARGET_TB_PCREL
55
+ /* Use acquire to ensure current load of pc from jc. */
56
+ return qatomic_load_acquire(&jc->array[hash].tb);
57
+#else
58
+ /* Use rcu_read to ensure current load of pc from *tb. */
59
+ return qatomic_rcu_read(&jc->array[hash].tb);
60
+#endif
61
+}
62
+
63
+static inline target_ulong
64
+tb_jmp_cache_get_pc(CPUJumpCache *jc, uint32_t hash, TranslationBlock *tb)
65
+{
66
+#if TARGET_TB_PCREL
67
+ return jc->array[hash].pc;
68
+#else
69
+ return tb_pc(tb);
70
+#endif
71
+}
72
+
73
+static inline void
74
+tb_jmp_cache_set(CPUJumpCache *jc, uint32_t hash,
75
+ TranslationBlock *tb, target_ulong pc)
76
+{
77
+#if TARGET_TB_PCREL
78
+ jc->array[hash].pc = pc;
79
+ /* Use store_release on tb to ensure pc is written first. */
80
+ qatomic_store_release(&jc->array[hash].tb, tb);
81
+#else
82
+ /* Use the pc value already stored in tb->pc. */
83
+ qatomic_set(&jc->array[hash].tb, tb);
84
+#endif
85
+}
86
+
87
#endif /* ACCEL_TCG_TB_JMP_CACHE_H */
88
diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h
89
index XXXXXXX..XXXXXXX 100644
90
--- a/include/exec/cpu-defs.h
91
+++ b/include/exec/cpu-defs.h
92
@@ -XXX,XX +XXX,XX @@
93
# error TARGET_PAGE_BITS must be defined in cpu-param.h
94
# endif
22
#endif
95
#endif
23
96
+#ifndef TARGET_TB_PCREL
24
-typedef struct TCGRelocation {
97
+# define TARGET_TB_PCREL 0
25
- struct TCGRelocation *next;
98
+#endif
26
- int type;
99
27
+typedef struct TCGRelocation TCGRelocation;
100
#define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8)
28
+struct TCGRelocation {
101
29
+ QSIMPLEQ_ENTRY(TCGRelocation) next;
102
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
30
tcg_insn_unit *ptr;
103
index XXXXXXX..XXXXXXX 100644
31
intptr_t addend;
104
--- a/include/exec/exec-all.h
32
-} TCGRelocation;
105
+++ b/include/exec/exec-all.h
33
+ int type;
106
@@ -XXX,XX +XXX,XX @@ struct tb_tc {
34
+};
35
36
typedef struct TCGLabel TCGLabel;
37
struct TCGLabel {
38
@@ -XXX,XX +XXX,XX @@ struct TCGLabel {
39
union {
40
uintptr_t value;
41
tcg_insn_unit *value_ptr;
42
- TCGRelocation *first_reloc;
43
} u;
44
-#ifdef CONFIG_DEBUG_TCG
45
+ QSIMPLEQ_HEAD(, TCGRelocation) relocs;
46
QSIMPLEQ_ENTRY(TCGLabel) next;
47
-#endif
48
};
107
};
49
108
50
typedef struct TCGPool {
109
struct TranslationBlock {
51
@@ -XXX,XX +XXX,XX @@ struct TCGContext {
110
- target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */
52
#endif
111
- target_ulong cs_base; /* CS base for this block */
53
112
+#if !TARGET_TB_PCREL
54
#ifdef CONFIG_DEBUG_TCG
113
+ /*
55
- QSIMPLEQ_HEAD(, TCGLabel) labels;
114
+ * Guest PC corresponding to this block. This must be the true
56
int temps_in_use;
115
+ * virtual address. Therefore e.g. x86 stores EIP + CS_BASE, and
57
int goto_tb_issue_mask;
116
+ * targets like Arm, MIPS, HP-PA, which reuse low bits for ISA or
58
#endif
117
+ * privilege, must store those bits elsewhere.
59
@@ -XXX,XX +XXX,XX @@ struct TCGContext {
118
+ *
60
TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */
119
+ * If TARGET_TB_PCREL, the opcodes for the TranslationBlock are
61
120
+ * written such that the TB is associated only with the physical
62
QTAILQ_HEAD(, TCGOp) ops, free_ops;
121
+ * page and may be run in any virtual address context. In this case,
63
+ QSIMPLEQ_HEAD(, TCGLabel) labels;
122
+ * PC must always be taken from ENV in a target-specific manner.
64
123
+ * Unwind information is taken as offsets from the page, to be
65
/* Tells which temporary holds a given register.
124
+ * deposited into the "current" PC.
66
It does not take into account fixed registers */
125
+ */
67
diff --git a/tcg/tcg.c b/tcg/tcg.c
126
+ target_ulong pc;
68
index XXXXXXX..XXXXXXX 100644
127
+#endif
69
--- a/tcg/tcg.c
128
+
70
+++ b/tcg/tcg.c
129
+ /*
71
@@ -XXX,XX +XXX,XX @@ static __attribute__((unused)) inline void tcg_patch64(tcg_insn_unit *p,
130
+ * Target-specific data associated with the TranslationBlock, e.g.:
72
static void tcg_out_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type,
131
+ * x86: the original user, the Code Segment virtual base,
73
TCGLabel *l, intptr_t addend)
132
+ * arm: an extension of tb->flags,
74
{
133
+ * s390x: instruction data for EXECUTE,
75
- TCGRelocation *r;
134
+ * sparc: the next pc of the instruction queue (for delay slots).
76
+ TCGRelocation *r = tcg_malloc(sizeof(TCGRelocation));
135
+ */
77
136
+ target_ulong cs_base;
78
- if (l->has_value) {
137
+
79
- /* FIXME: This may break relocations on RISC targets that
138
uint32_t flags; /* flags defining in which context the code was generated */
80
- modify instruction fields in place. The caller may not have
139
uint32_t cflags; /* compile flags */
81
- written the initial value. */
140
82
- bool ok = patch_reloc(code_ptr, type, l->u.value, addend);
141
@@ -XXX,XX +XXX,XX @@ struct TranslationBlock {
83
- tcg_debug_assert(ok);
142
/* Hide the read to avoid ifdefs for TARGET_TB_PCREL. */
84
- } else {
143
static inline target_ulong tb_pc(const TranslationBlock *tb)
85
- /* add a new relocation entry */
144
{
86
- r = tcg_malloc(sizeof(TCGRelocation));
145
+#if TARGET_TB_PCREL
87
- r->type = type;
146
+ qemu_build_not_reached();
88
- r->ptr = code_ptr;
147
+#else
89
- r->addend = addend;
148
return tb->pc;
90
- r->next = l->u.first_reloc;
149
+#endif
91
- l->u.first_reloc = r;
150
}
92
- }
151
93
+ r->type = type;
152
/* Hide the qatomic_read to make code a little easier on the eyes */
94
+ r->ptr = code_ptr;
153
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
95
+ r->addend = addend;
154
index XXXXXXX..XXXXXXX 100644
96
+ QSIMPLEQ_INSERT_TAIL(&l->relocs, r, next);
155
--- a/accel/tcg/cpu-exec.c
97
}
156
+++ b/accel/tcg/cpu-exec.c
98
157
@@ -XXX,XX +XXX,XX @@ static bool tb_lookup_cmp(const void *p, const void *d)
99
static void tcg_out_label(TCGContext *s, TCGLabel *l, tcg_insn_unit *ptr)
158
const TranslationBlock *tb = p;
100
{
159
const struct tb_desc *desc = d;
101
- intptr_t value = (intptr_t)ptr;
160
102
- TCGRelocation *r;
161
- if (tb_pc(tb) == desc->pc &&
103
-
162
+ if ((TARGET_TB_PCREL || tb_pc(tb) == desc->pc) &&
104
tcg_debug_assert(!l->has_value);
163
tb->page_addr[0] == desc->page_addr0 &&
105
-
164
tb->cs_base == desc->cs_base &&
106
- for (r = l->u.first_reloc; r != NULL; r = r->next) {
165
tb->flags == desc->flags &&
107
- bool ok = patch_reloc(r->ptr, r->type, value, r->addend);
166
@@ -XXX,XX +XXX,XX @@ static TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
108
- tcg_debug_assert(ok);
167
return NULL;
109
- }
168
}
110
-
169
desc.page_addr0 = phys_pc;
111
l->has_value = 1;
170
- h = tb_hash_func(phys_pc, pc, flags, cflags, *cpu->trace_dstate);
112
l->u.value_ptr = ptr;
171
+ h = tb_hash_func(phys_pc, (TARGET_TB_PCREL ? 0 : pc),
113
}
172
+ flags, cflags, *cpu->trace_dstate);
114
@@ -XXX,XX +XXX,XX @@ TCGLabel *gen_new_label(void)
173
return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp);
115
TCGContext *s = tcg_ctx;
174
}
116
TCGLabel *l = tcg_malloc(sizeof(TCGLabel));
175
117
176
@@ -XXX,XX +XXX,XX @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc,
118
- *l = (TCGLabel){
177
uint32_t flags, uint32_t cflags)
119
- .id = s->nb_labels++
178
{
120
- };
179
TranslationBlock *tb;
121
-#ifdef CONFIG_DEBUG_TCG
180
+ CPUJumpCache *jc;
122
+ memset(l, 0, sizeof(TCGLabel));
181
uint32_t hash;
123
+ l->id = s->nb_labels++;
182
124
+ QSIMPLEQ_INIT(&l->relocs);
183
/* we should never be trying to look up an INVALID tb */
125
+
184
tcg_debug_assert(!(cflags & CF_INVALID));
126
QSIMPLEQ_INSERT_TAIL(&s->labels, l, next);
185
127
-#endif
186
hash = tb_jmp_cache_hash_func(pc);
128
187
- tb = qatomic_rcu_read(&cpu->tb_jmp_cache->array[hash].tb);
129
return l;
188
+ jc = cpu->tb_jmp_cache;
130
}
189
+ tb = tb_jmp_cache_get_tb(jc, hash);
131
190
132
+static bool tcg_resolve_relocs(TCGContext *s)
191
if (likely(tb &&
192
- tb->pc == pc &&
193
+ tb_jmp_cache_get_pc(jc, hash, tb) == pc &&
194
tb->cs_base == cs_base &&
195
tb->flags == flags &&
196
tb->trace_vcpu_dstate == *cpu->trace_dstate &&
197
@@ -XXX,XX +XXX,XX @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc,
198
if (tb == NULL) {
199
return NULL;
200
}
201
- qatomic_set(&cpu->tb_jmp_cache->array[hash].tb, tb);
202
+ tb_jmp_cache_set(jc, hash, tb, pc);
203
return tb;
204
}
205
206
@@ -XXX,XX +XXX,XX @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
207
if (cc->tcg_ops->synchronize_from_tb) {
208
cc->tcg_ops->synchronize_from_tb(cpu, last_tb);
209
} else {
210
+ assert(!TARGET_TB_PCREL);
211
assert(cc->set_pc);
212
cc->set_pc(cpu, tb_pc(last_tb));
213
}
214
@@ -XXX,XX +XXX,XX @@ int cpu_exec(CPUState *cpu)
215
* for the fast lookup
216
*/
217
h = tb_jmp_cache_hash_func(pc);
218
- qatomic_set(&cpu->tb_jmp_cache->array[h].tb, tb);
219
+ tb_jmp_cache_set(cpu->tb_jmp_cache, h, tb, pc);
220
}
221
222
#ifndef CONFIG_USER_ONLY
223
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
224
index XXXXXXX..XXXXXXX 100644
225
--- a/accel/tcg/translate-all.c
226
+++ b/accel/tcg/translate-all.c
227
@@ -XXX,XX +XXX,XX @@ static int encode_search(TranslationBlock *tb, uint8_t *block)
228
229
for (j = 0; j < TARGET_INSN_START_WORDS; ++j) {
230
if (i == 0) {
231
- prev = (j == 0 ? tb_pc(tb) : 0);
232
+ prev = (!TARGET_TB_PCREL && j == 0 ? tb_pc(tb) : 0);
233
} else {
234
prev = tcg_ctx->gen_insn_data[i - 1][j];
235
}
236
@@ -XXX,XX +XXX,XX @@ static int encode_search(TranslationBlock *tb, uint8_t *block)
237
static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
238
uintptr_t searched_pc, bool reset_icount)
239
{
240
- target_ulong data[TARGET_INSN_START_WORDS] = { tb_pc(tb) };
241
+ target_ulong data[TARGET_INSN_START_WORDS];
242
uintptr_t host_pc = (uintptr_t)tb->tc.ptr;
243
CPUArchState *env = cpu->env_ptr;
244
const uint8_t *p = tb->tc.ptr + tb->tc.size;
245
@@ -XXX,XX +XXX,XX @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb,
246
return -1;
247
}
248
249
+ memset(data, 0, sizeof(data));
250
+ if (!TARGET_TB_PCREL) {
251
+ data[0] = tb_pc(tb);
252
+ }
253
+
254
/* Reconstruct the stored insn data while looking for the point at
255
which the end of the insn exceeds the searched_pc. */
256
for (i = 0; i < num_insns; ++i) {
257
@@ -XXX,XX +XXX,XX @@ static bool tb_cmp(const void *ap, const void *bp)
258
const TranslationBlock *a = ap;
259
const TranslationBlock *b = bp;
260
261
- return tb_pc(a) == tb_pc(b) &&
262
- a->cs_base == b->cs_base &&
263
- a->flags == b->flags &&
264
- (tb_cflags(a) & ~CF_INVALID) == (tb_cflags(b) & ~CF_INVALID) &&
265
- a->trace_vcpu_dstate == b->trace_vcpu_dstate &&
266
- a->page_addr[0] == b->page_addr[0] &&
267
- a->page_addr[1] == b->page_addr[1];
268
+ return ((TARGET_TB_PCREL || tb_pc(a) == tb_pc(b)) &&
269
+ a->cs_base == b->cs_base &&
270
+ a->flags == b->flags &&
271
+ (tb_cflags(a) & ~CF_INVALID) == (tb_cflags(b) & ~CF_INVALID) &&
272
+ a->trace_vcpu_dstate == b->trace_vcpu_dstate &&
273
+ a->page_addr[0] == b->page_addr[0] &&
274
+ a->page_addr[1] == b->page_addr[1]);
275
}
276
277
void tb_htable_init(void)
278
@@ -XXX,XX +XXX,XX @@ static inline void tb_jmp_unlink(TranslationBlock *dest)
279
qemu_spin_unlock(&dest->jmp_lock);
280
}
281
282
+static void tb_jmp_cache_inval_tb(TranslationBlock *tb)
133
+{
283
+{
134
+ TCGLabel *l;
284
+ CPUState *cpu;
135
+
285
+
136
+ QSIMPLEQ_FOREACH(l, &s->labels, next) {
286
+ if (TARGET_TB_PCREL) {
137
+ TCGRelocation *r;
287
+ /* A TB may be at any virtual address */
138
+ uintptr_t value = l->u.value;
288
+ CPU_FOREACH(cpu) {
139
+
289
+ tcg_flush_jmp_cache(cpu);
140
+ QSIMPLEQ_FOREACH(r, &l->relocs, next) {
290
+ }
141
+ if (!patch_reloc(r->ptr, r->type, value, r->addend)) {
291
+ } else {
142
+ return false;
292
+ uint32_t h = tb_jmp_cache_hash_func(tb_pc(tb));
293
+
294
+ CPU_FOREACH(cpu) {
295
+ CPUJumpCache *jc = cpu->tb_jmp_cache;
296
+
297
+ if (qatomic_read(&jc->array[h].tb) == tb) {
298
+ qatomic_set(&jc->array[h].tb, NULL);
143
+ }
299
+ }
144
+ }
300
+ }
145
+ }
301
+ }
146
+ return true;
147
+}
302
+}
148
+
303
+
149
static void set_jmp_reset_offset(TCGContext *s, int which)
304
/*
150
{
305
* In user-mode, call with mmap_lock held.
151
size_t off = tcg_current_code_size(s);
306
* In !user-mode, if @rm_from_page_list is set, call with the TB's pages'
152
@@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s)
307
@@ -XXX,XX +XXX,XX @@ static inline void tb_jmp_unlink(TranslationBlock *dest)
153
308
*/
154
QTAILQ_INIT(&s->ops);
309
static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
155
QTAILQ_INIT(&s->free_ops);
310
{
156
-#ifdef CONFIG_DEBUG_TCG
311
- CPUState *cpu;
157
QSIMPLEQ_INIT(&s->labels);
312
PageDesc *p;
158
-#endif
313
uint32_t h;
159
}
314
tb_page_addr_t phys_pc;
160
315
@@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
161
static inline TCGTemp *tcg_temp_alloc(TCGContext *s)
316
162
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
317
/* remove the TB from the hash list */
163
return -1;
318
phys_pc = tb->page_addr[0];
164
}
319
- h = tb_hash_func(phys_pc, tb_pc(tb), tb->flags, orig_cflags,
165
#endif
320
- tb->trace_vcpu_dstate);
166
+ if (!tcg_resolve_relocs(s)) {
321
+ h = tb_hash_func(phys_pc, (TARGET_TB_PCREL ? 0 : tb_pc(tb)),
167
+ return -2;
322
+ tb->flags, orig_cflags, tb->trace_vcpu_dstate);
168
+ }
323
if (!qht_remove(&tb_ctx.htable, tb, h)) {
169
324
return;
170
/* flush instruction cache */
325
}
171
flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr);
326
@@ -XXX,XX +XXX,XX @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list)
327
}
328
329
/* remove the TB from the hash list */
330
- h = tb_jmp_cache_hash_func(tb->pc);
331
- CPU_FOREACH(cpu) {
332
- CPUJumpCache *jc = cpu->tb_jmp_cache;
333
- if (qatomic_read(&jc->array[h].tb) == tb) {
334
- qatomic_set(&jc->array[h].tb, NULL);
335
- }
336
- }
337
+ tb_jmp_cache_inval_tb(tb);
338
339
/* suppress this TB from the two jump lists */
340
tb_remove_from_jmp_list(tb, 0);
341
@@ -XXX,XX +XXX,XX @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc,
342
}
343
344
/* add in the hash table */
345
- h = tb_hash_func(phys_pc, tb_pc(tb), tb->flags, tb->cflags,
346
- tb->trace_vcpu_dstate);
347
+ h = tb_hash_func(phys_pc, (TARGET_TB_PCREL ? 0 : tb_pc(tb)),
348
+ tb->flags, tb->cflags, tb->trace_vcpu_dstate);
349
qht_insert(&tb_ctx.htable, tb, h, &existing_tb);
350
351
/* remove TB from the page(s) if we couldn't insert it */
352
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
353
354
gen_code_buf = tcg_ctx->code_gen_ptr;
355
tb->tc.ptr = tcg_splitwx_to_rx(gen_code_buf);
356
+#if !TARGET_TB_PCREL
357
tb->pc = pc;
358
+#endif
359
tb->cs_base = cs_base;
360
tb->flags = flags;
361
tb->cflags = cflags;
172
--
362
--
173
2.17.1
363
2.34.1
174
364
175
365
diff view generated by jsdifflib
New patch
[PULL 19/20] tcg/ppc: Optimize 26-bit jumps
1
From: Leandro Lupori <leandro.lupori@eldorado.org.br>
1
2
3
PowerPC64 processors handle direct branches better than indirect
4
ones, resulting in less stalled cycles and branch misses.
5
6
However, PPC's tb_target_set_jmp_target() was only using direct
7
branches for 16-bit jumps, while PowerPC64's unconditional branch
8
instructions are able to handle displacements of up to 26 bits.
9
To take advantage of this, now jumps whose displacements fit in
10
between 17 and 26 bits are also converted to direct branches.
11
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
14
[rth: Expanded some commentary.]
15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16
---
17
tcg/ppc/tcg-target.c.inc | 119 +++++++++++++++++++++++++++++----------
18
1 file changed, 88 insertions(+), 31 deletions(-)
19
20
diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc
21
index XXXXXXX..XXXXXXX 100644
22
--- a/tcg/ppc/tcg-target.c.inc
23
+++ b/tcg/ppc/tcg-target.c.inc
24
@@ -XXX,XX +XXX,XX @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
25
tcg_out32(s, insn);
26
}
27
28
+static inline uint64_t make_pair(tcg_insn_unit i1, tcg_insn_unit i2)
29
+{
30
+ if (HOST_BIG_ENDIAN) {
31
+ return (uint64_t)i1 << 32 | i2;
32
+ }
33
+ return (uint64_t)i2 << 32 | i1;
34
+}
35
+
36
+static inline void ppc64_replace2(uintptr_t rx, uintptr_t rw,
37
+ tcg_insn_unit i0, tcg_insn_unit i1)
38
+{
39
+#if TCG_TARGET_REG_BITS == 64
40
+ qatomic_set((uint64_t *)rw, make_pair(i0, i1));
41
+ flush_idcache_range(rx, rw, 8);
42
+#else
43
+ qemu_build_not_reached();
44
+#endif
45
+}
46
+
47
+static inline void ppc64_replace4(uintptr_t rx, uintptr_t rw,
48
+ tcg_insn_unit i0, tcg_insn_unit i1,
49
+ tcg_insn_unit i2, tcg_insn_unit i3)
50
+{
51
+ uint64_t p[2];
52
+
53
+ p[!HOST_BIG_ENDIAN] = make_pair(i0, i1);
54
+ p[HOST_BIG_ENDIAN] = make_pair(i2, i3);
55
+
56
+ /*
57
+ * There's no convenient way to get the compiler to allocate a pair
58
+ * of registers at an even index, so copy into r6/r7 and clobber.
59
+ */
60
+ asm("mr %%r6, %1\n\t"
61
+ "mr %%r7, %2\n\t"
62
+ "stq %%r6, %0"
63
+ : "=Q"(*(__int128 *)rw) : "r"(p[0]), "r"(p[1]) : "r6", "r7");
64
+ flush_idcache_range(rx, rw, 16);
65
+}
66
+
67
void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx,
68
uintptr_t jmp_rw, uintptr_t addr)
69
{
70
- if (TCG_TARGET_REG_BITS == 64) {
71
- tcg_insn_unit i1, i2;
72
- intptr_t tb_diff = addr - tc_ptr;
73
- intptr_t br_diff = addr - (jmp_rx + 4);
74
- uint64_t pair;
75
+ tcg_insn_unit i0, i1, i2, i3;
76
+ intptr_t tb_diff = addr - tc_ptr;
77
+ intptr_t br_diff = addr - (jmp_rx + 4);
78
+ intptr_t lo, hi;
79
80
- /* This does not exercise the range of the branch, but we do
81
- still need to be able to load the new value of TCG_REG_TB.
82
- But this does still happen quite often. */
83
- if (tb_diff == (int16_t)tb_diff) {
84
- i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff);
85
- i2 = B | (br_diff & 0x3fffffc);
86
- } else {
87
- intptr_t lo = (int16_t)tb_diff;
88
- intptr_t hi = (int32_t)(tb_diff - lo);
89
- assert(tb_diff == hi + lo);
90
- i1 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16);
91
- i2 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo);
92
- }
93
-#if HOST_BIG_ENDIAN
94
- pair = (uint64_t)i1 << 32 | i2;
95
-#else
96
- pair = (uint64_t)i2 << 32 | i1;
97
-#endif
98
-
99
- /* As per the enclosing if, this is ppc64. Avoid the _Static_assert
100
- within qatomic_set that would fail to build a ppc32 host. */
101
- qatomic_set__nocheck((uint64_t *)jmp_rw, pair);
102
- flush_idcache_range(jmp_rx, jmp_rw, 8);
103
- } else {
104
+ if (TCG_TARGET_REG_BITS == 32) {
105
intptr_t diff = addr - jmp_rx;
106
tcg_debug_assert(in_range_b(diff));
107
qatomic_set((uint32_t *)jmp_rw, B | (diff & 0x3fffffc));
108
flush_idcache_range(jmp_rx, jmp_rw, 4);
109
+ return;
110
}
111
+
112
+ /*
113
+ * For 16-bit displacements, we can use a single add + branch.
114
+ * This happens quite often.
115
+ */
116
+ if (tb_diff == (int16_t)tb_diff) {
117
+ i0 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, tb_diff);
118
+ i1 = B | (br_diff & 0x3fffffc);
119
+ ppc64_replace2(jmp_rx, jmp_rw, i0, i1);
120
+ return;
121
+ }
122
+
123
+ lo = (int16_t)tb_diff;
124
+ hi = (int32_t)(tb_diff - lo);
125
+ assert(tb_diff == hi + lo);
126
+ i0 = ADDIS | TAI(TCG_REG_TB, TCG_REG_TB, hi >> 16);
127
+ i1 = ADDI | TAI(TCG_REG_TB, TCG_REG_TB, lo);
128
+
129
+ /*
130
+ * Without stq from 2.07, we can only update two insns,
131
+ * and those must be the ones that load the target address.
132
+ */
133
+ if (!have_isa_2_07) {
134
+ ppc64_replace2(jmp_rx, jmp_rw, i0, i1);
135
+ return;
136
+ }
137
+
138
+ /*
139
+ * For 26-bit displacements, we can use a direct branch.
140
+ * Otherwise we still need the indirect branch, which we
141
+ * must restore after a potential direct branch write.
142
+ */
143
+ br_diff -= 4;
144
+ if (in_range_b(br_diff)) {
145
+ i2 = B | (br_diff & 0x3fffffc);
146
+ i3 = NOP;
147
+ } else {
148
+ i2 = MTSPR | RS(TCG_REG_TB) | CTR;
149
+ i3 = BCCTR | BO_ALWAYS;
150
+ }
151
+ ppc64_replace4(jmp_rx, jmp_rw, i0, i1, i2, i3);
152
}
153
154
static void tcg_out_call_int(TCGContext *s, int lk,
155
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
156
if (s->tb_jmp_insn_offset) {
157
/* Direct jump. */
158
if (TCG_TARGET_REG_BITS == 64) {
159
- /* Ensure the next insns are 8-byte aligned. */
160
- if ((uintptr_t)s->code_ptr & 7) {
161
+ /* Ensure the next insns are 8 or 16-byte aligned. */
162
+ while ((uintptr_t)s->code_ptr & (have_isa_2_07 ? 15 : 7)) {
163
tcg_out32(s, NOP);
164
}
165
s->tb_jmp_insn_offset[args[0]] = tcg_current_code_size(s);
166
--
167
2.34.1
diff view generated by jsdifflib
New patch
[PULL 20/20] target/sh4: Fix TB_FLAG_UNALIGN
1
The value previously chosen overlaps GUSA_MASK.
1
2
3
Rename all DELAY_SLOT_* and GUSA_* defines to emphasize
4
that they are included in TB_FLAGs. Add aliases for the
5
FPSCR and SR bits that are included in TB_FLAGS, so that
6
we don't accidentally reassign those bits.
7
8
Fixes: 4da06fb3062 ("target/sh4: Implement prctl_unalign_sigbus")
9
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/856
10
Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
---
13
target/sh4/cpu.h | 56 +++++++++++++------------
14
linux-user/sh4/signal.c | 6 +--
15
target/sh4/cpu.c | 6 +--
16
target/sh4/helper.c | 6 +--
17
target/sh4/translate.c | 90 ++++++++++++++++++++++-------------------
18
5 files changed, 88 insertions(+), 76 deletions(-)
19
20
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/sh4/cpu.h
23
+++ b/target/sh4/cpu.h
24
@@ -XXX,XX +XXX,XX @@
25
#define FPSCR_RM_NEAREST (0 << 0)
26
#define FPSCR_RM_ZERO (1 << 0)
27
28
-#define DELAY_SLOT_MASK 0x7
29
-#define DELAY_SLOT (1 << 0)
30
-#define DELAY_SLOT_CONDITIONAL (1 << 1)
31
-#define DELAY_SLOT_RTE (1 << 2)
32
+#define TB_FLAG_DELAY_SLOT (1 << 0)
33
+#define TB_FLAG_DELAY_SLOT_COND (1 << 1)
34
+#define TB_FLAG_DELAY_SLOT_RTE (1 << 2)
35
+#define TB_FLAG_PENDING_MOVCA (1 << 3)
36
+#define TB_FLAG_GUSA_SHIFT 4 /* [11:4] */
37
+#define TB_FLAG_GUSA_EXCLUSIVE (1 << 12)
38
+#define TB_FLAG_UNALIGN (1 << 13)
39
+#define TB_FLAG_SR_FD (1 << SR_FD) /* 15 */
40
+#define TB_FLAG_FPSCR_PR FPSCR_PR /* 19 */
41
+#define TB_FLAG_FPSCR_SZ FPSCR_SZ /* 20 */
42
+#define TB_FLAG_FPSCR_FR FPSCR_FR /* 21 */
43
+#define TB_FLAG_SR_RB (1 << SR_RB) /* 29 */
44
+#define TB_FLAG_SR_MD (1 << SR_MD) /* 30 */
45
46
-#define TB_FLAG_PENDING_MOVCA (1 << 3)
47
-#define TB_FLAG_UNALIGN (1 << 4)
48
-
49
-#define GUSA_SHIFT 4
50
-#ifdef CONFIG_USER_ONLY
51
-#define GUSA_EXCLUSIVE (1 << 12)
52
-#define GUSA_MASK ((0xff << GUSA_SHIFT) | GUSA_EXCLUSIVE)
53
-#else
54
-/* Provide dummy versions of the above to allow tests against tbflags
55
- to be elided while avoiding ifdefs. */
56
-#define GUSA_EXCLUSIVE 0
57
-#define GUSA_MASK 0
58
-#endif
59
-
60
-#define TB_FLAG_ENVFLAGS_MASK (DELAY_SLOT_MASK | GUSA_MASK)
61
+#define TB_FLAG_DELAY_SLOT_MASK (TB_FLAG_DELAY_SLOT | \
62
+ TB_FLAG_DELAY_SLOT_COND | \
63
+ TB_FLAG_DELAY_SLOT_RTE)
64
+#define TB_FLAG_GUSA_MASK ((0xff << TB_FLAG_GUSA_SHIFT) | \
65
+ TB_FLAG_GUSA_EXCLUSIVE)
66
+#define TB_FLAG_FPSCR_MASK (TB_FLAG_FPSCR_PR | \
67
+ TB_FLAG_FPSCR_SZ | \
68
+ TB_FLAG_FPSCR_FR)
69
+#define TB_FLAG_SR_MASK (TB_FLAG_SR_FD | \
70
+ TB_FLAG_SR_RB | \
71
+ TB_FLAG_SR_MD)
72
+#define TB_FLAG_ENVFLAGS_MASK (TB_FLAG_DELAY_SLOT_MASK | \
73
+ TB_FLAG_GUSA_MASK)
74
75
typedef struct tlb_t {
76
uint32_t vpn;        /* virtual page number */
77
@@ -XXX,XX +XXX,XX @@ static inline int cpu_mmu_index (CPUSH4State *env, bool ifetch)
78
{
79
/* The instruction in a RTE delay slot is fetched in privileged
80
mode, but executed in user mode. */
81
- if (ifetch && (env->flags & DELAY_SLOT_RTE)) {
82
+ if (ifetch && (env->flags & TB_FLAG_DELAY_SLOT_RTE)) {
83
return 0;
84
} else {
85
return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
86
@@ -XXX,XX +XXX,XX @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
87
{
88
*pc = env->pc;
89
/* For a gUSA region, notice the end of the region. */
90
- *cs_base = env->flags & GUSA_MASK ? env->gregs[0] : 0;
91
- *flags = env->flags /* TB_FLAG_ENVFLAGS_MASK: bits 0-2, 4-12 */
92
- | (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR)) /* Bits 19-21 */
93
- | (env->sr & ((1u << SR_MD) | (1u << SR_RB))) /* Bits 29-30 */
94
- | (env->sr & (1u << SR_FD)) /* Bit 15 */
95
+ *cs_base = env->flags & TB_FLAG_GUSA_MASK ? env->gregs[0] : 0;
96
+ *flags = env->flags
97
+ | (env->fpscr & TB_FLAG_FPSCR_MASK)
98
+ | (env->sr & TB_FLAG_SR_MASK)
99
| (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 3 */
100
#ifdef CONFIG_USER_ONLY
101
*flags |= TB_FLAG_UNALIGN * !env_cpu(env)->prctl_unalign_sigbus;
102
diff --git a/linux-user/sh4/signal.c b/linux-user/sh4/signal.c
103
index XXXXXXX..XXXXXXX 100644
104
--- a/linux-user/sh4/signal.c
105
+++ b/linux-user/sh4/signal.c
106
@@ -XXX,XX +XXX,XX @@ static void restore_sigcontext(CPUSH4State *regs, struct target_sigcontext *sc)
107
__get_user(regs->fpul, &sc->sc_fpul);
108
109
regs->tra = -1; /* disable syscall checks */
110
- regs->flags &= ~(DELAY_SLOT_MASK | GUSA_MASK);
111
+ regs->flags = 0;
112
}
113
114
void setup_frame(int sig, struct target_sigaction *ka,
115
@@ -XXX,XX +XXX,XX @@ void setup_frame(int sig, struct target_sigaction *ka,
116
regs->gregs[5] = 0;
117
regs->gregs[6] = frame_addr += offsetof(typeof(*frame), sc);
118
regs->pc = (unsigned long) ka->_sa_handler;
119
- regs->flags &= ~(DELAY_SLOT_MASK | GUSA_MASK);
120
+ regs->flags &= ~(TB_FLAG_DELAY_SLOT_MASK | TB_FLAG_GUSA_MASK);
121
122
unlock_user_struct(frame, frame_addr, 1);
123
return;
124
@@ -XXX,XX +XXX,XX @@ void setup_rt_frame(int sig, struct target_sigaction *ka,
125
regs->gregs[5] = frame_addr + offsetof(typeof(*frame), info);
126
regs->gregs[6] = frame_addr + offsetof(typeof(*frame), uc);
127
regs->pc = (unsigned long) ka->_sa_handler;
128
- regs->flags &= ~(DELAY_SLOT_MASK | GUSA_MASK);
129
+ regs->flags &= ~(TB_FLAG_DELAY_SLOT_MASK | TB_FLAG_GUSA_MASK);
130
131
unlock_user_struct(frame, frame_addr, 1);
132
return;
133
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
134
index XXXXXXX..XXXXXXX 100644
135
--- a/target/sh4/cpu.c
136
+++ b/target/sh4/cpu.c
137
@@ -XXX,XX +XXX,XX @@ static void superh_cpu_synchronize_from_tb(CPUState *cs,
138
SuperHCPU *cpu = SUPERH_CPU(cs);
139
140
cpu->env.pc = tb_pc(tb);
141
- cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK;
142
+ cpu->env.flags = tb->flags;
143
}
144
145
#ifndef CONFIG_USER_ONLY
146
@@ -XXX,XX +XXX,XX @@ static bool superh_io_recompile_replay_branch(CPUState *cs,
147
SuperHCPU *cpu = SUPERH_CPU(cs);
148
CPUSH4State *env = &cpu->env;
149
150
- if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0
151
+ if ((env->flags & (TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND))
152
&& env->pc != tb_pc(tb)) {
153
env->pc -= 2;
154
- env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL);
155
+ env->flags &= ~(TB_FLAG_DELAY_SLOT | TB_FLAG_DELAY_SLOT_COND);
156
return true;
157
}
158
return false;
159
diff --git a/target/sh4/helper.c b/target/sh4/helper.c
160
index XXXXXXX..XXXXXXX 100644
161
--- a/target/sh4/helper.c
162
+++ b/target/sh4/helper.c
163
@@ -XXX,XX +XXX,XX @@ void superh_cpu_do_interrupt(CPUState *cs)
164
env->sr |= (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB);
165
env->lock_addr = -1;
166
167
- if (env->flags & DELAY_SLOT_MASK) {
168
+ if (env->flags & TB_FLAG_DELAY_SLOT_MASK) {
169
/* Branch instruction should be executed again before delay slot. */
170
    env->spc -= 2;
171
    /* Clear flags for exception/interrupt routine. */
172
- env->flags &= ~DELAY_SLOT_MASK;
173
+ env->flags &= ~TB_FLAG_DELAY_SLOT_MASK;
174
}
175
176
if (do_exp) {
177
@@ -XXX,XX +XXX,XX @@ bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
178
CPUSH4State *env = &cpu->env;
179
180
/* Delay slots are indivisible, ignore interrupts */
181
- if (env->flags & DELAY_SLOT_MASK) {
182
+ if (env->flags & TB_FLAG_DELAY_SLOT_MASK) {
183
return false;
184
} else {
185
superh_cpu_do_interrupt(cs);
186
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
187
index XXXXXXX..XXXXXXX 100644
188
--- a/target/sh4/translate.c
189
+++ b/target/sh4/translate.c
190
@@ -XXX,XX +XXX,XX @@ void superh_cpu_dump_state(CPUState *cs, FILE *f, int flags)
191
         i, env->gregs[i], i + 1, env->gregs[i + 1],
192
         i + 2, env->gregs[i + 2], i + 3, env->gregs[i + 3]);
193
}
194
- if (env->flags & DELAY_SLOT) {
195
+ if (env->flags & TB_FLAG_DELAY_SLOT) {
196
qemu_printf("in delay slot (delayed_pc=0x%08x)\n",
197
         env->delayed_pc);
198
- } else if (env->flags & DELAY_SLOT_CONDITIONAL) {
199
+ } else if (env->flags & TB_FLAG_DELAY_SLOT_COND) {
200
qemu_printf("in conditional delay slot (delayed_pc=0x%08x)\n",
201
         env->delayed_pc);
202
- } else if (env->flags & DELAY_SLOT_RTE) {
203
+ } else if (env->flags & TB_FLAG_DELAY_SLOT_RTE) {
204
qemu_fprintf(f, "in rte delay slot (delayed_pc=0x%08x)\n",
205
env->delayed_pc);
206
}
207
@@ -XXX,XX +XXX,XX @@ static inline void gen_save_cpu_state(DisasContext *ctx, bool save_pc)
208
209
static inline bool use_exit_tb(DisasContext *ctx)
210
{
211
- return (ctx->tbflags & GUSA_EXCLUSIVE) != 0;
212
+ return (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) != 0;
213
}
214
215
static bool use_goto_tb(DisasContext *ctx, target_ulong dest)
216
@@ -XXX,XX +XXX,XX @@ static void gen_conditional_jump(DisasContext *ctx, target_ulong dest,
217
TCGLabel *l1 = gen_new_label();
218
TCGCond cond_not_taken = jump_if_true ? TCG_COND_EQ : TCG_COND_NE;
219
220
- if (ctx->tbflags & GUSA_EXCLUSIVE) {
221
+ if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) {
222
/* When in an exclusive region, we must continue to the end.
223
Therefore, exit the region on a taken branch, but otherwise
224
fall through to the next instruction. */
225
tcg_gen_brcondi_i32(cond_not_taken, cpu_sr_t, 0, l1);
226
- tcg_gen_movi_i32(cpu_flags, ctx->envflags & ~GUSA_MASK);
227
+ tcg_gen_movi_i32(cpu_flags, ctx->envflags & ~TB_FLAG_GUSA_MASK);
228
/* Note that this won't actually use a goto_tb opcode because we
229
disallow it in use_goto_tb, but it handles exit + singlestep. */
230
gen_goto_tb(ctx, 0, dest);
231
@@ -XXX,XX +XXX,XX @@ static void gen_delayed_conditional_jump(DisasContext * ctx)
232
tcg_gen_mov_i32(ds, cpu_delayed_cond);
233
tcg_gen_discard_i32(cpu_delayed_cond);
234
235
- if (ctx->tbflags & GUSA_EXCLUSIVE) {
236
+ if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) {
237
/* When in an exclusive region, we must continue to the end.
238
Therefore, exit the region on a taken branch, but otherwise
239
fall through to the next instruction. */
240
tcg_gen_brcondi_i32(TCG_COND_EQ, ds, 0, l1);
241
242
/* Leave the gUSA region. */
243
- tcg_gen_movi_i32(cpu_flags, ctx->envflags & ~GUSA_MASK);
244
+ tcg_gen_movi_i32(cpu_flags, ctx->envflags & ~TB_FLAG_GUSA_MASK);
245
gen_jump(ctx);
246
247
gen_set_label(l1);
248
@@ -XXX,XX +XXX,XX @@ static inline void gen_store_fpr64(DisasContext *ctx, TCGv_i64 t, int reg)
249
#define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe))
250
251
#define CHECK_NOT_DELAY_SLOT \
252
- if (ctx->envflags & DELAY_SLOT_MASK) { \
253
- goto do_illegal_slot; \
254
+ if (ctx->envflags & TB_FLAG_DELAY_SLOT_MASK) { \
255
+ goto do_illegal_slot; \
256
}
257
258
#define CHECK_PRIVILEGED \
259
@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
260
case 0x000b:        /* rts */
261
    CHECK_NOT_DELAY_SLOT
262
    tcg_gen_mov_i32(cpu_delayed_pc, cpu_pr);
263
- ctx->envflags |= DELAY_SLOT;
264
+ ctx->envflags |= TB_FLAG_DELAY_SLOT;
265
    ctx->delayed_pc = (uint32_t) - 1;
266
    return;
267
case 0x0028:        /* clrmac */
268
@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
269
    CHECK_NOT_DELAY_SLOT
270
gen_write_sr(cpu_ssr);
271
    tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc);
272
- ctx->envflags |= DELAY_SLOT_RTE;
273
+ ctx->envflags |= TB_FLAG_DELAY_SLOT_RTE;
274
    ctx->delayed_pc = (uint32_t) - 1;
275
ctx->base.is_jmp = DISAS_STOP;
276
    return;
277
@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
278
    return;
279
case 0xe000:        /* mov #imm,Rn */
280
#ifdef CONFIG_USER_ONLY
281
- /* Detect the start of a gUSA region. If so, update envflags
282
- and end the TB. This will allow us to see the end of the
283
- region (stored in R0) in the next TB. */
284
+ /*
285
+ * Detect the start of a gUSA region (mov #-n, r15).
286
+ * If so, update envflags and end the TB. This will allow us
287
+ * to see the end of the region (stored in R0) in the next TB.
288
+ */
289
if (B11_8 == 15 && B7_0s < 0 &&
290
(tb_cflags(ctx->base.tb) & CF_PARALLEL)) {
291
- ctx->envflags = deposit32(ctx->envflags, GUSA_SHIFT, 8, B7_0s);
292
+ ctx->envflags =
293
+ deposit32(ctx->envflags, TB_FLAG_GUSA_SHIFT, 8, B7_0s);
294
ctx->base.is_jmp = DISAS_STOP;
295
}
296
#endif
297
@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
298
case 0xa000:        /* bra disp */
299
    CHECK_NOT_DELAY_SLOT
300
ctx->delayed_pc = ctx->base.pc_next + 4 + B11_0s * 2;
301
- ctx->envflags |= DELAY_SLOT;
302
+ ctx->envflags |= TB_FLAG_DELAY_SLOT;
303
    return;
304
case 0xb000:        /* bsr disp */
305
    CHECK_NOT_DELAY_SLOT
306
tcg_gen_movi_i32(cpu_pr, ctx->base.pc_next + 4);
307
ctx->delayed_pc = ctx->base.pc_next + 4 + B11_0s * 2;
308
- ctx->envflags |= DELAY_SLOT;
309
+ ctx->envflags |= TB_FLAG_DELAY_SLOT;
310
    return;
311
}
312
313
@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
314
    CHECK_NOT_DELAY_SLOT
315
tcg_gen_xori_i32(cpu_delayed_cond, cpu_sr_t, 1);
316
ctx->delayed_pc = ctx->base.pc_next + 4 + B7_0s * 2;
317
- ctx->envflags |= DELAY_SLOT_CONDITIONAL;
318
+ ctx->envflags |= TB_FLAG_DELAY_SLOT_COND;
319
    return;
320
case 0x8900:        /* bt label */
321
    CHECK_NOT_DELAY_SLOT
322
@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
323
    CHECK_NOT_DELAY_SLOT
324
tcg_gen_mov_i32(cpu_delayed_cond, cpu_sr_t);
325
ctx->delayed_pc = ctx->base.pc_next + 4 + B7_0s * 2;
326
- ctx->envflags |= DELAY_SLOT_CONDITIONAL;
327
+ ctx->envflags |= TB_FLAG_DELAY_SLOT_COND;
328
    return;
329
case 0x8800:        /* cmp/eq #imm,R0 */
330
tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, REG(0), B7_0s);
331
@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
332
case 0x0023:        /* braf Rn */
333
    CHECK_NOT_DELAY_SLOT
334
tcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->base.pc_next + 4);
335
- ctx->envflags |= DELAY_SLOT;
336
+ ctx->envflags |= TB_FLAG_DELAY_SLOT;
337
    ctx->delayed_pc = (uint32_t) - 1;
338
    return;
339
case 0x0003:        /* bsrf Rn */
340
    CHECK_NOT_DELAY_SLOT
341
tcg_gen_movi_i32(cpu_pr, ctx->base.pc_next + 4);
342
    tcg_gen_add_i32(cpu_delayed_pc, REG(B11_8), cpu_pr);
343
- ctx->envflags |= DELAY_SLOT;
344
+ ctx->envflags |= TB_FLAG_DELAY_SLOT;
345
    ctx->delayed_pc = (uint32_t) - 1;
346
    return;
347
case 0x4015:        /* cmp/pl Rn */
348
@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
349
case 0x402b:        /* jmp @Rn */
350
    CHECK_NOT_DELAY_SLOT
351
    tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8));
352
- ctx->envflags |= DELAY_SLOT;
353
+ ctx->envflags |= TB_FLAG_DELAY_SLOT;
354
    ctx->delayed_pc = (uint32_t) - 1;
355
    return;
356
case 0x400b:        /* jsr @Rn */
357
    CHECK_NOT_DELAY_SLOT
358
tcg_gen_movi_i32(cpu_pr, ctx->base.pc_next + 4);
359
    tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8));
360
- ctx->envflags |= DELAY_SLOT;
361
+ ctx->envflags |= TB_FLAG_DELAY_SLOT;
362
    ctx->delayed_pc = (uint32_t) - 1;
363
    return;
364
case 0x400e:        /* ldc Rm,SR */
365
@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
366
fflush(stderr);
367
#endif
368
do_illegal:
369
- if (ctx->envflags & DELAY_SLOT_MASK) {
370
+ if (ctx->envflags & TB_FLAG_DELAY_SLOT_MASK) {
371
do_illegal_slot:
372
gen_save_cpu_state(ctx, true);
373
gen_helper_raise_slot_illegal_instruction(cpu_env);
374
@@ -XXX,XX +XXX,XX @@ static void _decode_opc(DisasContext * ctx)
375
376
do_fpu_disabled:
377
gen_save_cpu_state(ctx, true);
378
- if (ctx->envflags & DELAY_SLOT_MASK) {
379
+ if (ctx->envflags & TB_FLAG_DELAY_SLOT_MASK) {
380
gen_helper_raise_slot_fpu_disable(cpu_env);
381
} else {
382
gen_helper_raise_fpu_disable(cpu_env);
383
@@ -XXX,XX +XXX,XX @@ static void decode_opc(DisasContext * ctx)
384
385
_decode_opc(ctx);
386
387
- if (old_flags & DELAY_SLOT_MASK) {
388
+ if (old_flags & TB_FLAG_DELAY_SLOT_MASK) {
389
/* go out of the delay slot */
390
- ctx->envflags &= ~DELAY_SLOT_MASK;
391
+ ctx->envflags &= ~TB_FLAG_DELAY_SLOT_MASK;
392
393
/* When in an exclusive region, we must continue to the end
394
for conditional branches. */
395
- if (ctx->tbflags & GUSA_EXCLUSIVE
396
- && old_flags & DELAY_SLOT_CONDITIONAL) {
397
+ if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE
398
+ && old_flags & TB_FLAG_DELAY_SLOT_COND) {
399
gen_delayed_conditional_jump(ctx);
400
return;
401
}
402
/* Otherwise this is probably an invalid gUSA region.
403
Drop the GUSA bits so the next TB doesn't see them. */
404
- ctx->envflags &= ~GUSA_MASK;
405
+ ctx->envflags &= ~TB_FLAG_GUSA_MASK;
406
407
tcg_gen_movi_i32(cpu_flags, ctx->envflags);
408
- if (old_flags & DELAY_SLOT_CONDITIONAL) {
409
+ if (old_flags & TB_FLAG_DELAY_SLOT_COND) {
410
     gen_delayed_conditional_jump(ctx);
411
} else {
412
gen_jump(ctx);
413
@@ -XXX,XX +XXX,XX @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
414
}
415
416
/* The entire region has been translated. */
417
- ctx->envflags &= ~GUSA_MASK;
418
+ ctx->envflags &= ~TB_FLAG_GUSA_MASK;
419
ctx->base.pc_next = pc_end;
420
ctx->base.num_insns += max_insns - 1;
421
return;
422
@@ -XXX,XX +XXX,XX @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
423
424
/* Restart with the EXCLUSIVE bit set, within a TB run via
425
cpu_exec_step_atomic holding the exclusive lock. */
426
- ctx->envflags |= GUSA_EXCLUSIVE;
427
+ ctx->envflags |= TB_FLAG_GUSA_EXCLUSIVE;
428
gen_save_cpu_state(ctx, false);
429
gen_helper_exclusive(cpu_env);
430
ctx->base.is_jmp = DISAS_NORETURN;
431
@@ -XXX,XX +XXX,XX @@ static void sh4_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
432
(tbflags & (1 << SR_RB))) * 0x10;
433
ctx->fbank = tbflags & FPSCR_FR ? 0x10 : 0;
434
435
- if (tbflags & GUSA_MASK) {
436
+#ifdef CONFIG_USER_ONLY
437
+ if (tbflags & TB_FLAG_GUSA_MASK) {
438
+ /* In gUSA exclusive region. */
439
uint32_t pc = ctx->base.pc_next;
440
uint32_t pc_end = ctx->base.tb->cs_base;
441
- int backup = sextract32(ctx->tbflags, GUSA_SHIFT, 8);
442
+ int backup = sextract32(ctx->tbflags, TB_FLAG_GUSA_SHIFT, 8);
443
int max_insns = (pc_end - pc) / 2;
444
445
if (pc != pc_end + backup || max_insns < 2) {
446
/* This is a malformed gUSA region. Don't do anything special,
447
since the interpreter is likely to get confused. */
448
- ctx->envflags &= ~GUSA_MASK;
449
- } else if (tbflags & GUSA_EXCLUSIVE) {
450
+ ctx->envflags &= ~TB_FLAG_GUSA_MASK;
451
+ } else if (tbflags & TB_FLAG_GUSA_EXCLUSIVE) {
452
/* Regardless of single-stepping or the end of the page,
453
we must complete execution of the gUSA region while
454
holding the exclusive lock. */
455
@@ -XXX,XX +XXX,XX @@ static void sh4_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
456
return;
457
}
458
}
459
+#endif
460
461
/* Since the ISA is fixed-width, we can bound by the number
462
of instructions remaining on the page. */
463
@@ -XXX,XX +XXX,XX @@ static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
464
DisasContext *ctx = container_of(dcbase, DisasContext, base);
465
466
#ifdef CONFIG_USER_ONLY
467
- if (unlikely(ctx->envflags & GUSA_MASK)
468
- && !(ctx->envflags & GUSA_EXCLUSIVE)) {
469
+ if (unlikely(ctx->envflags & TB_FLAG_GUSA_MASK)
470
+ && !(ctx->envflags & TB_FLAG_GUSA_EXCLUSIVE)) {
471
/* We're in an gUSA region, and we have not already fallen
472
back on using an exclusive region. Attempt to parse the
473
region into a single supported atomic operation. Failure
474
@@ -XXX,XX +XXX,XX @@ static void sh4_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
475
{
476
DisasContext *ctx = container_of(dcbase, DisasContext, base);
477
478
- if (ctx->tbflags & GUSA_EXCLUSIVE) {
479
+ if (ctx->tbflags & TB_FLAG_GUSA_EXCLUSIVE) {
480
/* Ending the region of exclusivity. Clear the bits. */
481
- ctx->envflags &= ~GUSA_MASK;
482
+ ctx->envflags &= ~TB_FLAG_GUSA_MASK;
483
}
484
485
switch (ctx->base.is_jmp) {
486
--
487
2.34.1
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.