[Qemu-devel] [PULL 00/15] tcg patch queue
[PULL 00/20] tcg patch queue
1
The following changes since commit 3284aa128153750f14a61e8a96fd085e6f2999b6:
1
The following changes since commit e93ded1bf6c94ab95015b33e188bc8b0b0c32670:
2
2
3
Merge remote-tracking branch 'remotes/lersek/tags/edk2-pull-2019-04-22' into staging (2019-04-24 13:19:41 +0100)
3
Merge tag 'testing-pull-request-2022-08-30' of https://gitlab.com/thuth/qemu into staging (2022-08-31 18:19:03 -0400)
4
4
5
are available in the Git repository at:
5
are available in the Git repository at:
6
6
7
https://github.com/rth7680/qemu.git tags/pull-tcg-20190426
7
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220901
8
8
9
for you to fetch changes up to ef5dae6805cce7b59d129d801bdc5db71bcbd60d:
9
for you to fetch changes up to 20011be2e30b8aa8ef1fc258485f00c688703deb:
10
10
11
cputlb: Fix io_readx() to respect the access_type (2019-04-25 10:40:06 -0700)
11
target/riscv: Make translator stop before the end of a page (2022-09-01 07:43:08 +0100)
12
12
13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
Add tcg_gen_extract2_*.
14
Respect PROT_EXEC in user-only mode.
15
Deal with overflow of TranslationBlocks.
15
Fix s390x, i386 and riscv for translations crossing a page.
16
Respect access_type in io_readx.
17
16
18
----------------------------------------------------------------
17
----------------------------------------------------------------
19
David Hildenbrand (1):
18
Ilya Leoshkevich (4):
20
tcg: Implement tcg_gen_extract2_{i32,i64}
19
linux-user: Clear translations on mprotect()
20
accel/tcg: Introduce is_same_page()
21
target/s390x: Make translator stop before the end of a page
22
target/i386: Make translator stop before the end of a page
21
23
22
Richard Henderson (13):
24
Richard Henderson (16):
23
tcg: Add INDEX_op_extract2_{i32,i64}
25
linux-user/arm: Mark the commpage executable
24
tcg: Use deposit and extract2 in tcg_gen_shifti_i64
26
linux-user/hppa: Allocate page zero as a commpage
25
tcg: Use extract2 in tcg_gen_deposit_{i32,i64}
27
linux-user/x86_64: Allocate vsyscall page as a commpage
26
tcg/i386: Support INDEX_op_extract2_{i32,i64}
28
linux-user: Honor PT_GNU_STACK
27
tcg/arm: Support INDEX_op_extract2_i32
29
tests/tcg/i386: Move smc_code2 to an executable section
28
tcg/aarch64: Support INDEX_op_extract2_{i32,i64}
30
accel/tcg: Properly implement get_page_addr_code for user-only
29
tcg: Hoist max_insns computation to tb_gen_code
31
accel/tcg: Unlock mmap_lock after longjmp
30
tcg: Restart after TB code generation overflow
32
accel/tcg: Make tb_htable_lookup static
31
tcg: Restart TB generation after relocation overflow
33
accel/tcg: Move qemu_ram_addr_from_host_nofail to physmem.c
32
tcg: Restart TB generation after constant pool overflow
34
accel/tcg: Use probe_access_internal for softmmu get_page_addr_code_hostp
33
tcg: Restart TB generation after out-of-line ldst overflow
35
accel/tcg: Document the faulting lookup in tb_lookup_cmp
34
tcg/ppc: Allow the constant pool to overflow at 32k
36
accel/tcg: Remove translator_ldsw
35
tcg/arm: Restrict constant pool displacement to 12 bits
37
accel/tcg: Add pc and host_pc params to gen_intermediate_code
38
accel/tcg: Add fast path for translator_ld*
39
target/riscv: Add MAX_INSN_LEN and insn_len
40
target/riscv: Make translator stop before the end of a page
36
41
37
Shahab Vahedi (1):
42
include/elf.h | 1 +
38
cputlb: Fix io_readx() to respect the access_type
43
include/exec/cpu-common.h | 1 +
39
44
include/exec/exec-all.h | 89 ++++++++----------------
40
include/exec/exec-all.h | 4 +-
45
include/exec/translator.h | 96 ++++++++++++++++---------
41
include/exec/translator.h | 3 +-
46
linux-user/arm/target_cpu.h | 4 +-
42
tcg/aarch64/tcg-target.h | 2 +
47
linux-user/qemu.h | 1 +
43
tcg/arm/tcg-target.h | 1 +
48
accel/tcg/cpu-exec.c | 143 ++++++++++++++++++++------------------
44
tcg/i386/tcg-target.h | 2 +
49
accel/tcg/cputlb.c | 93 +++++++------------------
45
tcg/mips/tcg-target.h | 2 +
50
accel/tcg/translate-all.c | 29 ++++----
46
tcg/ppc/tcg-target.h | 2 +
51
accel/tcg/translator.c | 135 ++++++++++++++++++++++++++---------
47
tcg/riscv/tcg-target.h | 2 +
52
accel/tcg/user-exec.c | 17 ++++-
48
tcg/s390/tcg-target.h | 2 +
53
linux-user/elfload.c | 82 ++++++++++++++++++++--
49
tcg/sparc/tcg-target.h | 2 +
54
linux-user/mmap.c | 6 +-
50
tcg/tcg-op.h | 6 ++
55
softmmu/physmem.c | 12 ++++
51
tcg/tcg-opc.h | 2 +
56
target/alpha/translate.c | 5 +-
52
tcg/tcg.h | 16 +++---
57
target/arm/translate.c | 5 +-
53
tcg/tci/tcg-target.h | 2 +
58
target/avr/translate.c | 5 +-
54
accel/tcg/cputlb.c | 5 +-
59
target/cris/translate.c | 5 +-
55
accel/tcg/translate-all.c | 53 ++++++++++++++---
60
target/hexagon/translate.c | 6 +-
56
accel/tcg/translator.c | 15 +----
61
target/hppa/translate.c | 5 +-
57
target/alpha/translate.c | 4 +-
62
target/i386/tcg/translate.c | 71 +++++++++++--------
58
target/arm/translate.c | 4 +-
63
target/loongarch/translate.c | 6 +-
59
target/cris/translate.c | 10 +---
64
target/m68k/translate.c | 5 +-
60
target/hppa/translate.c | 5 +-
65
target/microblaze/translate.c | 5 +-
61
target/i386/translate.c | 4 +-
66
target/mips/tcg/translate.c | 5 +-
62
target/lm32/translate.c | 10 +---
67
target/nios2/translate.c | 5 +-
63
target/m68k/translate.c | 4 +-
68
target/openrisc/translate.c | 6 +-
64
target/microblaze/translate.c | 10 +---
69
target/ppc/translate.c | 5 +-
65
target/mips/translate.c | 4 +-
70
target/riscv/translate.c | 32 +++++++--
66
target/moxie/translate.c | 11 +---
71
target/rx/translate.c | 5 +-
67
target/nios2/translate.c | 14 +----
72
target/s390x/tcg/translate.c | 20 ++++--
68
target/openrisc/translate.c | 4 +-
73
target/sh4/translate.c | 5 +-
69
target/ppc/translate.c | 4 +-
74
target/sparc/translate.c | 5 +-
70
target/riscv/translate.c | 4 +-
75
target/tricore/translate.c | 6 +-
71
target/s390x/translate.c | 4 +-
76
target/xtensa/translate.c | 6 +-
72
target/sh4/translate.c | 4 +-
77
tests/tcg/i386/test-i386.c | 2 +-
73
target/sparc/translate.c | 4 +-
78
tests/tcg/riscv64/noexec.c | 79 +++++++++++++++++++++
74
target/tilegx/translate.c | 12 +---
79
tests/tcg/s390x/noexec.c | 106 ++++++++++++++++++++++++++++
75
target/tricore/translate.c | 16 +-----
80
tests/tcg/x86_64/noexec.c | 75 ++++++++++++++++++++
76
target/unicore32/translate.c | 10 +---
81
tests/tcg/multiarch/noexec.c.inc | 139 ++++++++++++++++++++++++++++++++++++
77
target/xtensa/translate.c | 4 +-
82
tests/tcg/riscv64/Makefile.target | 1 +
78
tcg/aarch64/tcg-target.inc.c | 27 +++++++--
83
tests/tcg/s390x/Makefile.target | 1 +
79
tcg/arm/tcg-target.inc.c | 98 ++++++++++++++++++--------------
84
tests/tcg/x86_64/Makefile.target | 3 +-
80
tcg/i386/tcg-target.inc.c | 17 +++++-
85
43 files changed, 966 insertions(+), 367 deletions(-)
81
tcg/mips/tcg-target.inc.c | 6 +-
86
create mode 100644 tests/tcg/riscv64/noexec.c
82
tcg/optimize.c | 16 ++++++
87
create mode 100644 tests/tcg/s390x/noexec.c
83
tcg/ppc/tcg-target.inc.c | 42 +++++++-------
88
create mode 100644 tests/tcg/x86_64/noexec.c
84
tcg/riscv/tcg-target.inc.c | 16 ++++--
89
create mode 100644 tests/tcg/multiarch/noexec.c.inc
85
tcg/s390/tcg-target.inc.c | 20 ++++---
86
tcg/tcg-ldst.inc.c | 18 +++---
87
tcg/tcg-op.c | 129 +++++++++++++++++++++++++++++++++---------
88
tcg/tcg-pool.inc.c | 12 ++--
89
tcg/tcg.c | 85 +++++++++++++++-------------
90
tcg/README | 7 +++
91
51 files changed, 451 insertions(+), 309 deletions(-)
92
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/15] tcg: Use deposit and extract2 in tcg_gen_shifti_i64
[PULL 01/20] linux-user/arm: Mark the commpage executable
1
We're about to start validating PAGE_EXEC, which means
2
that we've got to mark the commpage executable. We had
3
been placing the commpage outside of reserved_va, which
4
was incorrect and lead to an abort.
5
6
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
7
Tested-by: Ilya Leoshkevich <iii@linux.ibm.com>
1
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2
---
9
---
3
tcg/tcg-op.c | 47 ++++++++++++++++++++++++-----------------------
10
linux-user/arm/target_cpu.h | 4 ++--
4
1 file changed, 24 insertions(+), 23 deletions(-)
11
linux-user/elfload.c | 6 +++++-
12
2 files changed, 7 insertions(+), 3 deletions(-)
5
13
6
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
14
diff --git a/linux-user/arm/target_cpu.h b/linux-user/arm/target_cpu.h
7
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
8
--- a/tcg/tcg-op.c
16
--- a/linux-user/arm/target_cpu.h
9
+++ b/tcg/tcg-op.c
17
+++ b/linux-user/arm/target_cpu.h
10
@@ -XXX,XX +XXX,XX @@ static inline void tcg_gen_shifti_i64(TCGv_i64 ret, TCGv_i64 arg1,
18
@@ -XXX,XX +XXX,XX @@ static inline unsigned long arm_max_reserved_va(CPUState *cs)
11
tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_LOW(arg1), c);
19
} else {
12
tcg_gen_movi_i32(TCGV_LOW(ret), 0);
20
/*
13
}
21
* We need to be able to map the commpage.
14
- } else {
22
- * See validate_guest_space in linux-user/elfload.c.
15
- TCGv_i32 t0, t1;
23
+ * See init_guest_commpage in linux-user/elfload.c.
16
-
24
*/
17
- t0 = tcg_temp_new_i32();
25
- return 0xffff0000ul;
18
- t1 = tcg_temp_new_i32();
26
+ return 0xfffffffful;
19
- if (right) {
20
- tcg_gen_shli_i32(t0, TCGV_HIGH(arg1), 32 - c);
21
- if (arith) {
22
- tcg_gen_sari_i32(t1, TCGV_HIGH(arg1), c);
23
- } else {
24
- tcg_gen_shri_i32(t1, TCGV_HIGH(arg1), c);
25
- }
26
- tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
27
- tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t0);
28
- tcg_gen_mov_i32(TCGV_HIGH(ret), t1);
29
+ } else if (right) {
30
+ if (TCG_TARGET_HAS_extract2_i32) {
31
+ tcg_gen_extract2_i32(TCGV_LOW(ret),
32
+ TCGV_LOW(arg1), TCGV_HIGH(arg1), c);
33
} else {
34
- tcg_gen_shri_i32(t0, TCGV_LOW(arg1), 32 - c);
35
- /* Note: ret can be the same as arg1, so we use t1 */
36
- tcg_gen_shli_i32(t1, TCGV_LOW(arg1), c);
37
- tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
38
- tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t0);
39
- tcg_gen_mov_i32(TCGV_LOW(ret), t1);
40
+ tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
41
+ tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(ret),
42
+ TCGV_HIGH(arg1), 32 - c, c);
43
}
44
- tcg_temp_free_i32(t0);
45
- tcg_temp_free_i32(t1);
46
+ if (arith) {
47
+ tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
48
+ } else {
49
+ tcg_gen_shri_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
50
+ }
51
+ } else {
52
+ if (TCG_TARGET_HAS_extract2_i32) {
53
+ tcg_gen_extract2_i32(TCGV_HIGH(ret),
54
+ TCGV_LOW(arg1), TCGV_HIGH(arg1), 32 - c);
55
+ } else {
56
+ TCGv_i32 t0 = tcg_temp_new_i32();
57
+ tcg_gen_shri_i32(t0, TCGV_LOW(arg1), 32 - c);
58
+ tcg_gen_deposit_i32(TCGV_HIGH(ret), t0,
59
+ TCGV_HIGH(arg1), c, 32 - c);
60
+ tcg_temp_free_i32(t0);
61
+ }
62
+ tcg_gen_shli_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
63
}
27
}
64
}
28
}
29
#define MAX_RESERVED_VA arm_max_reserved_va
30
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/linux-user/elfload.c
33
+++ b/linux-user/elfload.c
34
@@ -XXX,XX +XXX,XX @@ enum {
35
36
static bool init_guest_commpage(void)
37
{
38
- void *want = g2h_untagged(HI_COMMPAGE & -qemu_host_page_size);
39
+ abi_ptr commpage = HI_COMMPAGE & -qemu_host_page_size;
40
+ void *want = g2h_untagged(commpage);
41
void *addr = mmap(want, qemu_host_page_size, PROT_READ | PROT_WRITE,
42
MAP_ANONYMOUS | MAP_PRIVATE | MAP_FIXED, -1, 0);
43
44
@@ -XXX,XX +XXX,XX @@ static bool init_guest_commpage(void)
45
perror("Protecting guest commpage");
46
exit(EXIT_FAILURE);
47
}
48
+
49
+ page_set_flags(commpage, commpage + qemu_host_page_size,
50
+ PAGE_READ | PAGE_EXEC | PAGE_VALID);
51
return true;
52
}
65
53
66
--
54
--
67
2.17.1
55
2.34.1
68
69
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/15] tcg: Restart TB generation after constant pool overflow
[PULL 1/4] target/avr: Support probe argument to tlb_fill
1
This is part b of relocation overflow handling.
1
While there are no target-specific nonfaulting probes,
2
generic code may grow some uses at some point.
2
3
4
Note that the attrs argument was incorrect -- it should have
5
been MEMTXATTRS_UNSPECIFIED. Just use the simpler interface.
6
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
9
---
5
tcg/tcg-pool.inc.c | 12 +++++++-----
10
target/avr/helper.c | 46 ++++++++++++++++++++++++++++-----------------
6
tcg/tcg.c | 9 +++++----
11
1 file changed, 29 insertions(+), 17 deletions(-)
7
2 files changed, 12 insertions(+), 9 deletions(-)
8
12
9
diff --git a/tcg/tcg-pool.inc.c b/tcg/tcg-pool.inc.c
13
diff --git a/target/avr/helper.c b/target/avr/helper.c
10
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/tcg-pool.inc.c
15
--- a/target/avr/helper.c
12
+++ b/tcg/tcg-pool.inc.c
16
+++ b/target/avr/helper.c
13
@@ -XXX,XX +XXX,XX @@ static inline void new_pool_l8(TCGContext *s, int rtype, tcg_insn_unit *label,
17
@@ -XXX,XX +XXX,XX @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
14
/* To be provided by cpu/tcg-target.inc.c. */
18
MMUAccessType access_type, int mmu_idx,
15
static void tcg_out_nop_fill(tcg_insn_unit *p, int count);
19
bool probe, uintptr_t retaddr)
16
17
-static bool tcg_out_pool_finalize(TCGContext *s)
18
+static int tcg_out_pool_finalize(TCGContext *s)
19
{
20
{
20
TCGLabelPoolData *p = s->pool_labels;
21
- int prot = 0;
21
TCGLabelPoolData *l = NULL;
22
- MemTxAttrs attrs = {};
22
void *a;
23
+ int prot, page_size = TARGET_PAGE_SIZE;
23
24
uint32_t paddr;
24
if (p == NULL) {
25
25
- return true;
26
address &= TARGET_PAGE_MASK;
26
+ return 0;
27
27
}
28
if (mmu_idx == MMU_CODE_IDX) {
28
29
- /* access to code in flash */
29
/* ??? Round up to qemu_icache_linesize, but then do not round
30
+ /* Access to code in flash. */
30
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_pool_finalize(TCGContext *s)
31
paddr = OFFSET_CODE + address;
31
size_t size = sizeof(tcg_target_ulong) * p->nlong;
32
prot = PAGE_READ | PAGE_EXEC;
32
if (!l || l->nlong != p->nlong || memcmp(l->data, p->data, size)) {
33
- if (paddr + TARGET_PAGE_SIZE > OFFSET_DATA) {
33
if (unlikely(a > s->code_gen_highwater)) {
34
+ if (paddr >= OFFSET_DATA) {
34
- return false;
35
+ /*
35
+ return -1;
36
+ * This should not be possible via any architectural operations.
36
}
37
+ * There is certainly not an exception that we can deliver.
37
memcpy(a, p->data, size);
38
+ * Accept probing that might come from generic code.
38
a += size;
39
+ */
39
l = p;
40
+ if (probe) {
41
+ return false;
42
+ }
43
error_report("execution left flash memory");
44
abort();
40
}
45
}
41
- patch_reloc(p->label, p->rtype, (intptr_t)a - size, p->addend);
46
- } else if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
42
+ if (!patch_reloc(p->label, p->rtype, (intptr_t)a - size, p->addend)) {
47
- /*
43
+ return -2;
48
- * access to CPU registers, exit and rebuilt this TB to use full access
49
- * incase it touches specially handled registers like SREG or SP
50
- */
51
- AVRCPU *cpu = AVR_CPU(cs);
52
- CPUAVRState *env = &cpu->env;
53
- env->fullacc = 1;
54
- cpu_loop_exit_restore(cs, retaddr);
55
} else {
56
- /* access to memory. nothing special */
57
+ /* Access to memory. */
58
paddr = OFFSET_DATA + address;
59
prot = PAGE_READ | PAGE_WRITE;
60
+ if (address < NUMBER_OF_CPU_REGISTERS + NUMBER_OF_IO_REGISTERS) {
61
+ /*
62
+ * Access to CPU registers, exit and rebuilt this TB to use
63
+ * full access in case it touches specially handled registers
64
+ * like SREG or SP. For probing, set page_size = 1, in order
65
+ * to force tlb_fill to be called for the next access.
66
+ */
67
+ if (probe) {
68
+ page_size = 1;
69
+ } else {
70
+ AVRCPU *cpu = AVR_CPU(cs);
71
+ CPUAVRState *env = &cpu->env;
72
+ env->fullacc = 1;
73
+ cpu_loop_exit_restore(cs, retaddr);
74
+ }
44
+ }
75
+ }
45
}
76
}
46
77
47
s->code_ptr = a;
78
- tlb_set_page_with_attrs(cs, address, paddr, attrs, prot,
48
- return true;
79
- mmu_idx, TARGET_PAGE_SIZE);
49
+ return 0;
80
-
81
+ tlb_set_page(cs, address, paddr, prot, mmu_idx, page_size);
82
return true;
50
}
83
}
51
diff --git a/tcg/tcg.c b/tcg/tcg.c
84
52
index XXXXXXX..XXXXXXX 100644
53
--- a/tcg/tcg.c
54
+++ b/tcg/tcg.c
55
@@ -XXX,XX +XXX,XX @@ void tcg_prologue_init(TCGContext *s)
56
#ifdef TCG_TARGET_NEED_POOL_LABELS
57
/* Allow the prologue to put e.g. guest_base into a pool entry. */
58
{
59
- bool ok = tcg_out_pool_finalize(s);
60
- tcg_debug_assert(ok);
61
+ int result = tcg_out_pool_finalize(s);
62
+ tcg_debug_assert(result == 0);
63
}
64
#endif
65
66
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
67
}
68
#endif
69
#ifdef TCG_TARGET_NEED_POOL_LABELS
70
- if (!tcg_out_pool_finalize(s)) {
71
- return -1;
72
+ i = tcg_out_pool_finalize(s);
73
+ if (i < 0) {
74
+ return i;
75
}
76
#endif
77
if (!tcg_resolve_relocs(s)) {
78
--
85
--
79
2.17.1
86
2.34.1
80
87
81
88
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/15] tcg/aarch64: Support INDEX_op_extract2_{i32, i64}
[PULL 2/4] target/avr: Call avr_cpu_do_interrupt directly
1
There is no need to go through cc->tcg_ops when
2
we know what value that must have.
3
4
Reviewed-by: Michael Rolnik <mrolnik@gmail.com>
1
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
7
---
4
tcg/aarch64/tcg-target.h | 4 ++--
8
target/avr/helper.c | 5 ++---
5
tcg/aarch64/tcg-target.inc.c | 11 +++++++++++
9
1 file changed, 2 insertions(+), 3 deletions(-)
6
2 files changed, 13 insertions(+), 2 deletions(-)
7
10
8
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
11
diff --git a/target/avr/helper.c b/target/avr/helper.c
9
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
10
--- a/tcg/aarch64/tcg-target.h
13
--- a/target/avr/helper.c
11
+++ b/tcg/aarch64/tcg-target.h
14
+++ b/target/avr/helper.c
12
@@ -XXX,XX +XXX,XX @@ typedef enum {
15
@@ -XXX,XX +XXX,XX @@
13
#define TCG_TARGET_HAS_deposit_i32 1
16
bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
14
#define TCG_TARGET_HAS_extract_i32 1
17
{
15
#define TCG_TARGET_HAS_sextract_i32 1
18
bool ret = false;
16
-#define TCG_TARGET_HAS_extract2_i32 0
19
- CPUClass *cc = CPU_GET_CLASS(cs);
17
+#define TCG_TARGET_HAS_extract2_i32 1
20
AVRCPU *cpu = AVR_CPU(cs);
18
#define TCG_TARGET_HAS_movcond_i32 1
21
CPUAVRState *env = &cpu->env;
19
#define TCG_TARGET_HAS_add2_i32 1
22
20
#define TCG_TARGET_HAS_sub2_i32 1
23
if (interrupt_request & CPU_INTERRUPT_RESET) {
21
@@ -XXX,XX +XXX,XX @@ typedef enum {
24
if (cpu_interrupts_enabled(env)) {
22
#define TCG_TARGET_HAS_deposit_i64 1
25
cs->exception_index = EXCP_RESET;
23
#define TCG_TARGET_HAS_extract_i64 1
26
- cc->tcg_ops->do_interrupt(cs);
24
#define TCG_TARGET_HAS_sextract_i64 1
27
+ avr_cpu_do_interrupt(cs);
25
-#define TCG_TARGET_HAS_extract2_i64 0
28
26
+#define TCG_TARGET_HAS_extract2_i64 1
29
cs->interrupt_request &= ~CPU_INTERRUPT_RESET;
27
#define TCG_TARGET_HAS_movcond_i64 1
30
28
#define TCG_TARGET_HAS_add2_i64 1
31
@@ -XXX,XX +XXX,XX @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
29
#define TCG_TARGET_HAS_sub2_i64 1
32
if (cpu_interrupts_enabled(env) && env->intsrc != 0) {
30
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
33
int index = ctz32(env->intsrc);
31
index XXXXXXX..XXXXXXX 100644
34
cs->exception_index = EXCP_INT(index);
32
--- a/tcg/aarch64/tcg-target.inc.c
35
- cc->tcg_ops->do_interrupt(cs);
33
+++ b/tcg/aarch64/tcg-target.inc.c
36
+ avr_cpu_do_interrupt(cs);
34
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
37
35
tcg_out_sbfm(s, ext, a0, a1, a2, a2 + args[3] - 1);
38
env->intsrc &= env->intsrc - 1; /* clear the interrupt */
36
break;
39
if (!env->intsrc) {
37
38
+ case INDEX_op_extract2_i64:
39
+ case INDEX_op_extract2_i32:
40
+ tcg_out_extr(s, ext, a0, a1, a2, args[3]);
41
+ break;
42
+
43
case INDEX_op_add2_i32:
44
tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, REG0(2), REG0(3),
45
(int32_t)args[4], args[5], const_args[4],
46
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
47
= { .args_ct_str = { "r", "r", "rAL" } };
48
static const TCGTargetOpDef dep
49
= { .args_ct_str = { "r", "0", "rZ" } };
50
+ static const TCGTargetOpDef ext2
51
+ = { .args_ct_str = { "r", "rZ", "rZ" } };
52
static const TCGTargetOpDef movc
53
= { .args_ct_str = { "r", "r", "rA", "rZ", "rZ" } };
54
static const TCGTargetOpDef add2
55
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
56
case INDEX_op_deposit_i64:
57
return &dep;
58
59
+ case INDEX_op_extract2_i32:
60
+ case INDEX_op_extract2_i64:
61
+ return &ext2;
62
+
63
case INDEX_op_add2_i32:
64
case INDEX_op_add2_i64:
65
case INDEX_op_sub2_i32:
66
--
40
--
67
2.17.1
41
2.34.1
68
42
69
43
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/15] tcg: Restart TB generation after out-of-line ldst overflow
[PULL 02/20] linux-user/hppa: Allocate page zero as a commpage
1
This is part c of relocation overflow handling.
1
We're about to start validating PAGE_EXEC, which means that we've
2
got to mark page zero executable. We had been special casing this
3
entirely within translate.
2
4
5
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
6
Tested-by: Ilya Leoshkevich <iii@linux.ibm.com>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
8
---
5
tcg/aarch64/tcg-target.inc.c | 16 ++++++++++------
9
linux-user/elfload.c | 34 +++++++++++++++++++++++++++++++---
6
tcg/arm/tcg-target.inc.c | 16 ++++++++++------
10
1 file changed, 31 insertions(+), 3 deletions(-)
7
tcg/i386/tcg-target.inc.c | 6 ++++--
8
tcg/mips/tcg-target.inc.c | 6 ++++--
9
tcg/ppc/tcg-target.inc.c | 14 ++++++++++----
10
tcg/riscv/tcg-target.inc.c | 16 ++++++++++++----
11
tcg/s390/tcg-target.inc.c | 20 ++++++++++++--------
12
tcg/tcg-ldst.inc.c | 18 +++++++++---------
13
tcg/tcg.c | 7 ++++---
14
9 files changed, 75 insertions(+), 44 deletions(-)
15
11
16
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
12
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
17
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
18
--- a/tcg/aarch64/tcg-target.inc.c
14
--- a/linux-user/elfload.c
19
+++ b/tcg/aarch64/tcg-target.inc.c
15
+++ b/linux-user/elfload.c
20
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_adr(TCGContext *s, TCGReg rd, void *target)
16
@@ -XXX,XX +XXX,XX @@ static inline void init_thread(struct target_pt_regs *regs,
21
tcg_out_insn(s, 3406, ADR, rd, offset);
17
regs->gr[31] = infop->entry;
22
}
18
}
23
19
24
-static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
20
+#define LO_COMMPAGE 0
25
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
21
+
26
{
22
+static bool init_guest_commpage(void)
27
TCGMemOpIdx oi = lb->oi;
23
+{
28
TCGMemOp opc = get_memop(oi);
24
+ void *want = g2h_untagged(LO_COMMPAGE);
29
TCGMemOp size = opc & MO_SIZE;
25
+ void *addr = mmap(want, qemu_host_page_size, PROT_NONE,
30
26
+ MAP_ANONYMOUS | MAP_PRIVATE | MAP_FIXED, -1, 0);
31
- bool ok = reloc_pc19(lb->label_ptr[0], s->code_ptr);
27
+
32
- tcg_debug_assert(ok);
28
+ if (addr == MAP_FAILED) {
33
+ if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) {
29
+ perror("Allocating guest commpage");
30
+ exit(EXIT_FAILURE);
31
+ }
32
+ if (addr != want) {
34
+ return false;
33
+ return false;
35
+ }
34
+ }
36
35
+
37
tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0);
36
+ /*
38
tcg_out_mov(s, TARGET_LONG_BITS == 64, TCG_REG_X1, lb->addrlo_reg);
37
+ * On Linux, page zero is normally marked execute only + gateway.
39
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
38
+ * Normal read or write is supposed to fail (thus PROT_NONE above),
39
+ * but specific offsets have kernel code mapped to raise permissions
40
+ * and implement syscalls. Here, simply mark the page executable.
41
+ * Special case the entry points during translation (see do_page_zero).
42
+ */
43
+ page_set_flags(LO_COMMPAGE, LO_COMMPAGE + TARGET_PAGE_SIZE,
44
+ PAGE_EXEC | PAGE_VALID);
45
+ return true;
46
+}
47
+
48
#endif /* TARGET_HPPA */
49
50
#ifdef TARGET_XTENSA
51
@@ -XXX,XX +XXX,XX @@ static abi_ulong create_elf_tables(abi_ulong p, int argc, int envc,
52
}
53
54
#if defined(HI_COMMPAGE)
55
-#define LO_COMMPAGE 0
56
+#define LO_COMMPAGE -1
57
#elif defined(LO_COMMPAGE)
58
#define HI_COMMPAGE 0
59
#else
60
#define HI_COMMPAGE 0
61
-#define LO_COMMPAGE 0
62
+#define LO_COMMPAGE -1
63
#define init_guest_commpage() true
64
#endif
65
66
@@ -XXX,XX +XXX,XX @@ static void pgb_static(const char *image_name, abi_ulong orig_loaddr,
67
} else {
68
offset = -(HI_COMMPAGE & -align);
69
}
70
- } else if (LO_COMMPAGE != 0) {
71
+ } else if (LO_COMMPAGE != -1) {
72
loaddr = MIN(loaddr, LO_COMMPAGE & -align);
40
}
73
}
41
74
42
tcg_out_goto(s, lb->raddr);
43
+ return true;
44
}
45
46
-static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
47
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
48
{
49
TCGMemOpIdx oi = lb->oi;
50
TCGMemOp opc = get_memop(oi);
51
TCGMemOp size = opc & MO_SIZE;
52
53
- bool ok = reloc_pc19(lb->label_ptr[0], s->code_ptr);
54
- tcg_debug_assert(ok);
55
+ if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) {
56
+ return false;
57
+ }
58
59
tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0);
60
tcg_out_mov(s, TARGET_LONG_BITS == 64, TCG_REG_X1, lb->addrlo_reg);
61
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
62
tcg_out_adr(s, TCG_REG_X4, lb->raddr);
63
tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
64
tcg_out_goto(s, lb->raddr);
65
+ return true;
66
}
67
68
static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
69
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
70
index XXXXXXX..XXXXXXX 100644
71
--- a/tcg/arm/tcg-target.inc.c
72
+++ b/tcg/arm/tcg-target.inc.c
73
@@ -XXX,XX +XXX,XX @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
74
label->label_ptr[0] = label_ptr;
75
}
76
77
-static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
78
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
79
{
80
TCGReg argreg, datalo, datahi;
81
TCGMemOpIdx oi = lb->oi;
82
TCGMemOp opc = get_memop(oi);
83
void *func;
84
85
- bool ok = reloc_pc24(lb->label_ptr[0], s->code_ptr);
86
- tcg_debug_assert(ok);
87
+ if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) {
88
+ return false;
89
+ }
90
91
argreg = tcg_out_arg_reg32(s, TCG_REG_R0, TCG_AREG0);
92
if (TARGET_LONG_BITS == 64) {
93
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
94
}
95
96
tcg_out_goto(s, COND_AL, lb->raddr);
97
+ return true;
98
}
99
100
-static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
101
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
102
{
103
TCGReg argreg, datalo, datahi;
104
TCGMemOpIdx oi = lb->oi;
105
TCGMemOp opc = get_memop(oi);
106
107
- bool ok = reloc_pc24(lb->label_ptr[0], s->code_ptr);
108
- tcg_debug_assert(ok);
109
+ if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) {
110
+ return false;
111
+ }
112
113
argreg = TCG_REG_R0;
114
argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0);
115
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
116
117
/* Tail-call to the helper, which will return to the fast path. */
118
tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
119
+ return true;
120
}
121
#endif /* SOFTMMU */
122
123
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
124
index XXXXXXX..XXXXXXX 100644
125
--- a/tcg/i386/tcg-target.inc.c
126
+++ b/tcg/i386/tcg-target.inc.c
127
@@ -XXX,XX +XXX,XX @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64,
128
/*
129
* Generate code for the slow path for a load at the end of block
130
*/
131
-static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
132
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
133
{
134
TCGMemOpIdx oi = l->oi;
135
TCGMemOp opc = get_memop(oi);
136
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
137
138
/* Jump to the code corresponding to next IR of qemu_st */
139
tcg_out_jmp(s, l->raddr);
140
+ return true;
141
}
142
143
/*
144
* Generate code for the slow path for a store at the end of block
145
*/
146
-static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
147
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
148
{
149
TCGMemOpIdx oi = l->oi;
150
TCGMemOp opc = get_memop(oi);
151
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
152
/* "Tail call" to the helper, with the return address back inline. */
153
tcg_out_push(s, retaddr);
154
tcg_out_jmp(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
155
+ return true;
156
}
157
#elif TCG_TARGET_REG_BITS == 32
158
# define x86_guest_base_seg 0
159
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
160
index XXXXXXX..XXXXXXX 100644
161
--- a/tcg/mips/tcg-target.inc.c
162
+++ b/tcg/mips/tcg-target.inc.c
163
@@ -XXX,XX +XXX,XX @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
164
}
165
}
166
167
-static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
168
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
169
{
170
TCGMemOpIdx oi = l->oi;
171
TCGMemOp opc = get_memop(oi);
172
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
173
} else {
174
tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO);
175
}
176
+ return true;
177
}
178
179
-static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
180
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
181
{
182
TCGMemOpIdx oi = l->oi;
183
TCGMemOp opc = get_memop(oi);
184
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
185
tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true);
186
/* delay slot */
187
tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
188
+ return true;
189
}
190
#endif
191
192
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
193
index XXXXXXX..XXXXXXX 100644
194
--- a/tcg/ppc/tcg-target.inc.c
195
+++ b/tcg/ppc/tcg-target.inc.c
196
@@ -XXX,XX +XXX,XX @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
197
label->label_ptr[0] = lptr;
198
}
199
200
-static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
201
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
202
{
203
TCGMemOpIdx oi = lb->oi;
204
TCGMemOp opc = get_memop(oi);
205
TCGReg hi, lo, arg = TCG_REG_R3;
206
207
- **lb->label_ptr |= reloc_pc14_val(*lb->label_ptr, s->code_ptr);
208
+ if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) {
209
+ return false;
210
+ }
211
212
tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
213
214
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
215
}
216
217
tcg_out_b(s, 0, lb->raddr);
218
+ return true;
219
}
220
221
-static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
222
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
223
{
224
TCGMemOpIdx oi = lb->oi;
225
TCGMemOp opc = get_memop(oi);
226
TCGMemOp s_bits = opc & MO_SIZE;
227
TCGReg hi, lo, arg = TCG_REG_R3;
228
229
- **lb->label_ptr |= reloc_pc14_val(*lb->label_ptr, s->code_ptr);
230
+ if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) {
231
+ return false;
232
+ }
233
234
tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
235
236
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
237
tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
238
239
tcg_out_b(s, 0, lb->raddr);
240
+ return true;
241
}
242
#endif /* SOFTMMU */
243
244
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
245
index XXXXXXX..XXXXXXX 100644
246
--- a/tcg/riscv/tcg-target.inc.c
247
+++ b/tcg/riscv/tcg-target.inc.c
248
@@ -XXX,XX +XXX,XX @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
249
label->label_ptr[0] = label_ptr[0];
250
}
251
252
-static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
253
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
254
{
255
TCGMemOpIdx oi = l->oi;
256
TCGMemOp opc = get_memop(oi);
257
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
258
}
259
260
/* resolve label address */
261
- patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, (intptr_t) s->code_ptr, 0);
262
+ if (!patch_reloc(l->label_ptr[0], R_RISCV_BRANCH,
263
+ (intptr_t) s->code_ptr, 0)) {
264
+ return false;
265
+ }
266
267
/* call load helper */
268
tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0);
269
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
270
tcg_out_mov(s, (opc & MO_SIZE) == MO_64, l->datalo_reg, a0);
271
272
tcg_out_goto(s, l->raddr);
273
+ return true;
274
}
275
276
-static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
277
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
278
{
279
TCGMemOpIdx oi = l->oi;
280
TCGMemOp opc = get_memop(oi);
281
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
282
}
283
284
/* resolve label address */
285
- patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, (intptr_t) s->code_ptr, 0);
286
+ if (!patch_reloc(l->label_ptr[0], R_RISCV_BRANCH,
287
+ (intptr_t) s->code_ptr, 0)) {
288
+ return false;
289
+ }
290
291
/* call store helper */
292
tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0);
293
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
294
tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SSIZE)]);
295
296
tcg_out_goto(s, l->raddr);
297
+ return true;
298
}
299
#endif /* CONFIG_SOFTMMU */
300
301
diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
302
index XXXXXXX..XXXXXXX 100644
303
--- a/tcg/s390/tcg-target.inc.c
304
+++ b/tcg/s390/tcg-target.inc.c
305
@@ -XXX,XX +XXX,XX @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
306
label->label_ptr[0] = label_ptr;
307
}
308
309
-static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
310
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
311
{
312
TCGReg addr_reg = lb->addrlo_reg;
313
TCGReg data_reg = lb->datalo_reg;
314
TCGMemOpIdx oi = lb->oi;
315
TCGMemOp opc = get_memop(oi);
316
317
- bool ok = patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
318
- (intptr_t)s->code_ptr, 2);
319
- tcg_debug_assert(ok);
320
+ if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
321
+ (intptr_t)s->code_ptr, 2)) {
322
+ return false;
323
+ }
324
325
tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0);
326
if (TARGET_LONG_BITS == 64) {
327
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
328
tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_R2);
329
330
tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr);
331
+ return true;
332
}
333
334
-static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
335
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
336
{
337
TCGReg addr_reg = lb->addrlo_reg;
338
TCGReg data_reg = lb->datalo_reg;
339
TCGMemOpIdx oi = lb->oi;
340
TCGMemOp opc = get_memop(oi);
341
342
- bool ok = patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
343
- (intptr_t)s->code_ptr, 2);
344
- tcg_debug_assert(ok);
345
+ if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
346
+ (intptr_t)s->code_ptr, 2)) {
347
+ return false;
348
+ }
349
350
tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0);
351
if (TARGET_LONG_BITS == 64) {
352
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
353
tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
354
355
tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr);
356
+ return true;
357
}
358
#else
359
static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg,
360
diff --git a/tcg/tcg-ldst.inc.c b/tcg/tcg-ldst.inc.c
361
index XXXXXXX..XXXXXXX 100644
362
--- a/tcg/tcg-ldst.inc.c
363
+++ b/tcg/tcg-ldst.inc.c
364
@@ -XXX,XX +XXX,XX @@ typedef struct TCGLabelQemuLdst {
365
* Generate TB finalization at the end of block
366
*/
367
368
-static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l);
369
-static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l);
370
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l);
371
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l);
372
373
-static bool tcg_out_ldst_finalize(TCGContext *s)
374
+static int tcg_out_ldst_finalize(TCGContext *s)
375
{
376
TCGLabelQemuLdst *lb;
377
378
/* qemu_ld/st slow paths */
379
QSIMPLEQ_FOREACH(lb, &s->ldst_labels, next) {
380
- if (lb->is_ld) {
381
- tcg_out_qemu_ld_slow_path(s, lb);
382
- } else {
383
- tcg_out_qemu_st_slow_path(s, lb);
384
+ if (lb->is_ld
385
+ ? !tcg_out_qemu_ld_slow_path(s, lb)
386
+ : !tcg_out_qemu_st_slow_path(s, lb)) {
387
+ return -2;
388
}
389
390
/* Test for (pending) buffer overflow. The assumption is that any
391
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_ldst_finalize(TCGContext *s)
392
the buffer completely. Thus we can test for overflow after
393
generating code without having to check during generation. */
394
if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) {
395
- return false;
396
+ return -1;
397
}
398
}
399
- return true;
400
+ return 0;
401
}
402
403
/*
404
diff --git a/tcg/tcg.c b/tcg/tcg.c
405
index XXXXXXX..XXXXXXX 100644
406
--- a/tcg/tcg.c
407
+++ b/tcg/tcg.c
408
@@ -XXX,XX +XXX,XX @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *target);
409
static int tcg_target_const_match(tcg_target_long val, TCGType type,
410
const TCGArgConstraint *arg_ct);
411
#ifdef TCG_TARGET_NEED_LDST_LABELS
412
-static bool tcg_out_ldst_finalize(TCGContext *s);
413
+static int tcg_out_ldst_finalize(TCGContext *s);
414
#endif
415
416
#define TCG_HIGHWATER 1024
417
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
418
419
/* Generate TB finalization at the end of block */
420
#ifdef TCG_TARGET_NEED_LDST_LABELS
421
- if (!tcg_out_ldst_finalize(s)) {
422
- return -1;
423
+ i = tcg_out_ldst_finalize(s);
424
+ if (i < 0) {
425
+ return i;
426
}
427
#endif
428
#ifdef TCG_TARGET_NEED_POOL_LABELS
429
--
75
--
430
2.17.1
76
2.34.1
431
432
diff view generated by jsdifflib
New patch
[PULL 03/20] linux-user/x86_64: Allocate vsyscall page as a commpage
1
We're about to start validating PAGE_EXEC, which means that we've
2
got to mark the vsyscall page executable. We had been special
3
casing this entirely within translate.
1
4
5
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
6
Tested-by: Ilya Leoshkevich <iii@linux.ibm.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
9
linux-user/elfload.c | 23 +++++++++++++++++++++++
10
1 file changed, 23 insertions(+)
11
12
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/linux-user/elfload.c
15
+++ b/linux-user/elfload.c
16
@@ -XXX,XX +XXX,XX @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUX86State *en
17
(*regs)[26] = tswapreg(env->segs[R_GS].selector & 0xffff);
18
}
19
20
+#if ULONG_MAX >= TARGET_VSYSCALL_PAGE
21
+#define INIT_GUEST_COMMPAGE
22
+static bool init_guest_commpage(void)
23
+{
24
+ /*
25
+ * The vsyscall page is at a high negative address aka kernel space,
26
+ * which means that we cannot actually allocate it with target_mmap.
27
+ * We still should be able to use page_set_flags, unless the user
28
+ * has specified -R reserved_va, which would trigger an assert().
29
+ */
30
+ if (reserved_va != 0 &&
31
+ TARGET_VSYSCALL_PAGE + TARGET_PAGE_SIZE >= reserved_va) {
32
+ error_report("Cannot allocate vsyscall page");
33
+ exit(EXIT_FAILURE);
34
+ }
35
+ page_set_flags(TARGET_VSYSCALL_PAGE,
36
+ TARGET_VSYSCALL_PAGE + TARGET_PAGE_SIZE,
37
+ PAGE_EXEC | PAGE_VALID);
38
+ return true;
39
+}
40
+#endif
41
#else
42
43
#define ELF_START_MMAP 0x80000000
44
@@ -XXX,XX +XXX,XX @@ static abi_ulong create_elf_tables(abi_ulong p, int argc, int envc,
45
#else
46
#define HI_COMMPAGE 0
47
#define LO_COMMPAGE -1
48
+#ifndef INIT_GUEST_COMMPAGE
49
#define init_guest_commpage() true
50
#endif
51
+#endif
52
53
static void pgb_fail_in_use(const char *image_name)
54
{
55
--
56
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/15] tcg/arm: Support INDEX_op_extract2_i32
[PULL 3/4] target/avr: Only execute one interrupt at a time
1
We cannot deliver two interrupts simultaneously;
2
the first interrupt handler must execute first.
3
4
Reviewed-by: Michael Rolnik <mrolnik@gmail.com>
1
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
7
---
4
tcg/arm/tcg-target.h | 2 +-
8
target/avr/helper.c | 9 +++------
5
tcg/arm/tcg-target.inc.c | 25 +++++++++++++++++++++++++
9
1 file changed, 3 insertions(+), 6 deletions(-)
6
2 files changed, 26 insertions(+), 1 deletion(-)
7
10
8
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
11
diff --git a/target/avr/helper.c b/target/avr/helper.c
9
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
10
--- a/tcg/arm/tcg-target.h
13
--- a/target/avr/helper.c
11
+++ b/tcg/arm/tcg-target.h
14
+++ b/target/avr/helper.c
12
@@ -XXX,XX +XXX,XX @@ extern bool use_idiv_instructions;
15
@@ -XXX,XX +XXX,XX @@
13
#define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions
16
14
#define TCG_TARGET_HAS_extract_i32 use_armv7_instructions
17
bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
15
#define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions
18
{
16
-#define TCG_TARGET_HAS_extract2_i32 0
19
- bool ret = false;
17
+#define TCG_TARGET_HAS_extract2_i32 1
20
AVRCPU *cpu = AVR_CPU(cs);
18
#define TCG_TARGET_HAS_movcond_i32 1
21
CPUAVRState *env = &cpu->env;
19
#define TCG_TARGET_HAS_mulu2_i32 1
22
20
#define TCG_TARGET_HAS_muls2_i32 1
23
@@ -XXX,XX +XXX,XX @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
21
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
24
avr_cpu_do_interrupt(cs);
22
index XXXXXXX..XXXXXXX 100644
25
23
--- a/tcg/arm/tcg-target.inc.c
26
cs->interrupt_request &= ~CPU_INTERRUPT_RESET;
24
+++ b/tcg/arm/tcg-target.inc.c
27
-
25
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
28
- ret = true;
26
case INDEX_op_sextract_i32:
29
+ return true;
27
tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]);
30
}
28
break;
31
}
29
+ case INDEX_op_extract2_i32:
32
if (interrupt_request & CPU_INTERRUPT_HARD) {
30
+ /* ??? These optimization vs zero should be generic. */
33
@@ -XXX,XX +XXX,XX @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
31
+ /* ??? But we can't substitute 2 for 1 in the opcode stream yet. */
34
if (!env->intsrc) {
32
+ if (const_args[1]) {
35
cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
33
+ if (const_args[2]) {
36
}
34
+ tcg_out_movi(s, TCG_TYPE_REG, args[0], 0);
37
-
35
+ } else {
38
- ret = true;
36
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0,
39
+ return true;
37
+ args[2], SHIFT_IMM_LSL(32 - args[3]));
40
}
38
+ }
41
}
39
+ } else if (const_args[2]) {
42
- return ret;
40
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0,
43
+ return false;
41
+ args[1], SHIFT_IMM_LSR(args[3]));
44
}
42
+ } else {
45
43
+ /* We can do extract2 in 2 insns, vs the 3 required otherwise. */
46
void avr_cpu_do_interrupt(CPUState *cs)
44
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0,
45
+ args[2], SHIFT_IMM_LSL(32 - args[3]));
46
+ tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP,
47
+ args[1], SHIFT_IMM_LSR(args[3]));
48
+ }
49
+ break;
50
51
case INDEX_op_div_i32:
52
tcg_out_sdiv(s, COND_AL, args[0], args[1], args[2]);
53
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
54
= { .args_ct_str = { "s", "s", "s", "s" } };
55
static const TCGTargetOpDef br
56
= { .args_ct_str = { "r", "rIN" } };
57
+ static const TCGTargetOpDef ext2
58
+ = { .args_ct_str = { "r", "rZ", "rZ" } };
59
static const TCGTargetOpDef dep
60
= { .args_ct_str = { "r", "0", "rZ" } };
61
static const TCGTargetOpDef movc
62
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
63
return &br;
64
case INDEX_op_deposit_i32:
65
return &dep;
66
+ case INDEX_op_extract2_i32:
67
+ return &ext2;
68
case INDEX_op_movcond_i32:
69
return &movc;
70
case INDEX_op_add2_i32:
71
--
47
--
72
2.17.1
48
2.34.1
73
49
74
50
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/15] tcg: Use extract2 in tcg_gen_deposit_{i32, i64}
[PULL 4/4] target/avr: Disable interrupts when env->skip set
1
This bit is not saved across interrupts, so we must
2
delay delivering the interrupt until the skip has
3
been processed.
4
5
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1118
6
Reviewed-by: Michael Rolnik <mrolnik@gmail.com>
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2
---
9
---
3
tcg/tcg-op.c | 34 ++++++++++++++++++++++++++++++----
10
target/avr/helper.c | 9 +++++++++
4
1 file changed, 30 insertions(+), 4 deletions(-)
11
target/avr/translate.c | 26 ++++++++++++++++++++++----
12
2 files changed, 31 insertions(+), 4 deletions(-)
5
13
6
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
14
diff --git a/target/avr/helper.c b/target/avr/helper.c
7
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
8
--- a/tcg/tcg-op.c
16
--- a/target/avr/helper.c
9
+++ b/tcg/tcg-op.c
17
+++ b/target/avr/helper.c
10
@@ -XXX,XX +XXX,XX @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
18
@@ -XXX,XX +XXX,XX @@ bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
11
return;
19
AVRCPU *cpu = AVR_CPU(cs);
12
}
20
CPUAVRState *env = &cpu->env;
13
21
14
- mask = (1u << len) - 1;
22
+ /*
15
t1 = tcg_temp_new_i32();
23
+ * We cannot separate a skip from the next instruction,
16
24
+ * as the skip would not be preserved across the interrupt.
17
+ if (TCG_TARGET_HAS_extract2_i32) {
25
+ * Separating the two insn normally only happens at page boundaries.
18
+ if (ofs + len == 32) {
26
+ */
19
+ tcg_gen_shli_i32(t1, arg1, len);
27
+ if (env->skip) {
20
+ tcg_gen_extract2_i32(ret, t1, arg2, len);
28
+ return false;
21
+ goto done;
22
+ }
23
+ if (ofs == 0) {
24
+ tcg_gen_extract2_i32(ret, arg1, arg2, len);
25
+ tcg_gen_rotli_i32(ret, ret, len);
26
+ goto done;
27
+ }
28
+ }
29
+ }
29
+
30
+
30
+ mask = (1u << len) - 1;
31
if (interrupt_request & CPU_INTERRUPT_RESET) {
31
if (ofs + len < 32) {
32
if (cpu_interrupts_enabled(env)) {
32
tcg_gen_andi_i32(t1, arg2, mask);
33
cs->exception_index = EXCP_RESET;
33
tcg_gen_shli_i32(t1, t1, ofs);
34
diff --git a/target/avr/translate.c b/target/avr/translate.c
34
@@ -XXX,XX +XXX,XX @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
35
index XXXXXXX..XXXXXXX 100644
35
}
36
--- a/target/avr/translate.c
36
tcg_gen_andi_i32(ret, arg1, ~(mask << ofs));
37
+++ b/target/avr/translate.c
37
tcg_gen_or_i32(ret, ret, t1);
38
@@ -XXX,XX +XXX,XX @@ static void avr_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
38
-
39
if (skip_label) {
39
+ done:
40
canonicalize_skip(ctx);
40
tcg_temp_free_i32(t1);
41
gen_set_label(skip_label);
41
}
42
- if (ctx->base.is_jmp == DISAS_NORETURN) {
42
43
+
43
@@ -XXX,XX +XXX,XX @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
44
+ switch (ctx->base.is_jmp) {
45
+ case DISAS_NORETURN:
46
ctx->base.is_jmp = DISAS_CHAIN;
47
+ break;
48
+ case DISAS_NEXT:
49
+ if (ctx->base.tb->flags & TB_FLAGS_SKIP) {
50
+ ctx->base.is_jmp = DISAS_TOO_MANY;
51
+ }
52
+ break;
53
+ default:
54
+ break;
44
}
55
}
45
}
56
}
46
57
47
- mask = (1ull << len) - 1;
58
@@ -XXX,XX +XXX,XX @@ static void avr_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
48
t1 = tcg_temp_new_i64();
59
{
49
60
DisasContext *ctx = container_of(dcbase, DisasContext, base);
50
+ if (TCG_TARGET_HAS_extract2_i64) {
61
bool nonconst_skip = canonicalize_skip(ctx);
51
+ if (ofs + len == 64) {
62
+ /*
52
+ tcg_gen_shli_i64(t1, arg1, len);
63
+ * Because we disable interrupts while env->skip is set,
53
+ tcg_gen_extract2_i64(ret, t1, arg2, len);
64
+ * we must return to the main loop to re-evaluate afterward.
54
+ goto done;
65
+ */
66
+ bool force_exit = ctx->base.tb->flags & TB_FLAGS_SKIP;
67
68
switch (ctx->base.is_jmp) {
69
case DISAS_NORETURN:
70
@@ -XXX,XX +XXX,XX @@ static void avr_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
71
case DISAS_NEXT:
72
case DISAS_TOO_MANY:
73
case DISAS_CHAIN:
74
- if (!nonconst_skip) {
75
+ if (!nonconst_skip && !force_exit) {
76
/* Note gen_goto_tb checks singlestep. */
77
gen_goto_tb(ctx, 1, ctx->npc);
78
break;
79
@@ -XXX,XX +XXX,XX @@ static void avr_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
80
tcg_gen_movi_tl(cpu_pc, ctx->npc);
81
/* fall through */
82
case DISAS_LOOKUP:
83
- tcg_gen_lookup_and_goto_ptr();
84
- break;
85
+ if (!force_exit) {
86
+ tcg_gen_lookup_and_goto_ptr();
87
+ break;
55
+ }
88
+ }
56
+ if (ofs == 0) {
89
+ /* fall through */
57
+ tcg_gen_extract2_i64(ret, arg1, arg2, len);
90
case DISAS_EXIT:
58
+ tcg_gen_rotli_i64(ret, ret, len);
91
tcg_gen_exit_tb(NULL, 0);
59
+ goto done;
92
break;
60
+ }
61
+ }
62
+
63
+ mask = (1ull << len) - 1;
64
if (ofs + len < 64) {
65
tcg_gen_andi_i64(t1, arg2, mask);
66
tcg_gen_shli_i64(t1, t1, ofs);
67
@@ -XXX,XX +XXX,XX @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
68
}
69
tcg_gen_andi_i64(ret, arg1, ~(mask << ofs));
70
tcg_gen_or_i64(ret, ret, t1);
71
-
72
+ done:
73
tcg_temp_free_i64(t1);
74
}
75
76
--
93
--
77
2.17.1
94
2.34.1
78
95
79
96
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/15] tcg/ppc: Allow the constant pool to overflow at 32k
[PULL 04/20] linux-user: Honor PT_GNU_STACK
1
There is no point in coding for a 2GB offset when the max TB size
1
Map the stack executable if required by default or on demand.
2
is already limited to 64k. If we further restrict to 32k then we
3
can eliminate the extra ADDIS instruction.
4
2
3
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
4
Tested-by: Ilya Leoshkevich <iii@linux.ibm.com>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
6
---
7
tcg/ppc/tcg-target.inc.c | 28 ++++++++++------------------
7
include/elf.h | 1 +
8
1 file changed, 10 insertions(+), 18 deletions(-)
8
linux-user/qemu.h | 1 +
9
linux-user/elfload.c | 19 ++++++++++++++++++-
10
3 files changed, 20 insertions(+), 1 deletion(-)
9
11
10
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
12
diff --git a/include/elf.h b/include/elf.h
11
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/ppc/tcg-target.inc.c
14
--- a/include/elf.h
13
+++ b/tcg/ppc/tcg-target.inc.c
15
+++ b/include/elf.h
14
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
16
@@ -XXX,XX +XXX,XX @@ typedef int64_t Elf64_Sxword;
15
intptr_t value, intptr_t addend)
17
#define PT_LOPROC 0x70000000
18
#define PT_HIPROC 0x7fffffff
19
20
+#define PT_GNU_STACK (PT_LOOS + 0x474e551)
21
#define PT_GNU_PROPERTY (PT_LOOS + 0x474e553)
22
23
#define PT_MIPS_REGINFO 0x70000000
24
diff --git a/linux-user/qemu.h b/linux-user/qemu.h
25
index XXXXXXX..XXXXXXX 100644
26
--- a/linux-user/qemu.h
27
+++ b/linux-user/qemu.h
28
@@ -XXX,XX +XXX,XX @@ struct image_info {
29
uint32_t elf_flags;
30
int personality;
31
abi_ulong alignment;
32
+ bool exec_stack;
33
34
/* Generic semihosting knows about these pointers. */
35
abi_ulong arg_strings; /* strings for argv */
36
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/linux-user/elfload.c
39
+++ b/linux-user/elfload.c
40
@@ -XXX,XX +XXX,XX @@ static bool init_guest_commpage(void)
41
#define ELF_ARCH EM_386
42
43
#define ELF_PLATFORM get_elf_platform()
44
+#define EXSTACK_DEFAULT true
45
46
static const char *get_elf_platform(void)
16
{
47
{
17
tcg_insn_unit *target;
48
@@ -XXX,XX +XXX,XX @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUX86State *en
18
- tcg_insn_unit old;
49
19
50
#define ELF_ARCH EM_ARM
20
value += addend;
51
#define ELF_CLASS ELFCLASS32
21
target = (tcg_insn_unit *)value;
52
+#define EXSTACK_DEFAULT true
22
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
53
23
case R_PPC_REL24:
54
static inline void init_thread(struct target_pt_regs *regs,
24
return reloc_pc24(code_ptr, target);
55
struct image_info *infop)
25
case R_PPC_ADDR16:
56
@@ -XXX,XX +XXX,XX @@ static inline void init_thread(struct target_pt_regs *regs,
26
- /* We are abusing this relocation type. This points to a pair
57
#else
27
- of insns, addis + load. If the displacement is small, we
58
28
- can nop out the addis. */
59
#define ELF_CLASS ELFCLASS32
29
- if (value == (int16_t)value) {
60
+#define EXSTACK_DEFAULT true
30
- code_ptr[0] = NOP;
61
31
- old = deposit32(code_ptr[1], 0, 16, value);
62
#endif
32
- code_ptr[1] = deposit32(old, 16, 5, TCG_REG_TB);
63
33
- } else {
64
@@ -XXX,XX +XXX,XX @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUPPCState *en
34
- int16_t lo = value;
65
35
- int hi = value - lo;
66
#define ELF_CLASS ELFCLASS64
36
- if (hi + lo != value) {
67
#define ELF_ARCH EM_LOONGARCH
37
- return false;
68
+#define EXSTACK_DEFAULT true
38
- }
69
39
- code_ptr[0] = deposit32(code_ptr[0], 0, 16, hi >> 16);
70
#define elf_check_arch(x) ((x) == EM_LOONGARCH)
40
- code_ptr[1] = deposit32(code_ptr[1], 0, 16, lo);
71
41
+ /*
72
@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void)
42
+ * We are (slightly) abusing this relocation type. In particular,
73
#define ELF_CLASS ELFCLASS32
43
+ * assert that the low 2 bits are zero, and do not modify them.
74
#endif
44
+ * That way we can use this with LD et al that have opcode bits
75
#define ELF_ARCH EM_MIPS
45
+ * in the low 2 bits of the insn.
76
+#define EXSTACK_DEFAULT true
46
+ */
77
47
+ if ((value & 3) || value != (int16_t)value) {
78
#ifdef TARGET_ABI_MIPSN32
48
+ return false;
79
#define elf_check_abi(x) ((x) & EF_MIPS_ABI2)
80
@@ -XXX,XX +XXX,XX @@ static inline void init_thread(struct target_pt_regs *regs,
81
#define bswaptls(ptr) bswap32s(ptr)
82
#endif
83
84
+#ifndef EXSTACK_DEFAULT
85
+#define EXSTACK_DEFAULT false
86
+#endif
87
+
88
#include "elf.h"
89
90
/* We must delay the following stanzas until after "elf.h". */
91
@@ -XXX,XX +XXX,XX @@ static abi_ulong setup_arg_pages(struct linux_binprm *bprm,
92
struct image_info *info)
93
{
94
abi_ulong size, error, guard;
95
+ int prot;
96
97
size = guest_stack_size;
98
if (size < STACK_LOWER_LIMIT) {
99
@@ -XXX,XX +XXX,XX @@ static abi_ulong setup_arg_pages(struct linux_binprm *bprm,
100
guard = qemu_real_host_page_size();
101
}
102
103
- error = target_mmap(0, size + guard, PROT_READ | PROT_WRITE,
104
+ prot = PROT_READ | PROT_WRITE;
105
+ if (info->exec_stack) {
106
+ prot |= PROT_EXEC;
107
+ }
108
+ error = target_mmap(0, size + guard, prot,
109
MAP_PRIVATE | MAP_ANONYMOUS, -1, 0);
110
if (error == -1) {
111
perror("mmap stack");
112
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
113
*/
114
loaddr = -1, hiaddr = 0;
115
info->alignment = 0;
116
+ info->exec_stack = EXSTACK_DEFAULT;
117
for (i = 0; i < ehdr->e_phnum; ++i) {
118
struct elf_phdr *eppnt = phdr + i;
119
if (eppnt->p_type == PT_LOAD) {
120
@@ -XXX,XX +XXX,XX @@ static void load_elf_image(const char *image_name, int image_fd,
121
if (!parse_elf_properties(image_fd, info, eppnt, bprm_buf, &err)) {
122
goto exit_errmsg;
123
}
124
+ } else if (eppnt->p_type == PT_GNU_STACK) {
125
+ info->exec_stack = eppnt->p_flags & PF_X;
49
}
126
}
50
+ *code_ptr = (*code_ptr & ~0xfffc) | (value & 0xfffc);
51
break;
52
default:
53
g_assert_not_reached();
54
@@ -XXX,XX +XXX,XX @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
55
if (!in_prologue && USE_REG_TB) {
56
new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr,
57
-(intptr_t)s->code_gen_ptr);
58
- tcg_out32(s, ADDIS | TAI(ret, TCG_REG_TB, 0));
59
- tcg_out32(s, LD | TAI(ret, ret, 0));
60
+ tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0));
61
return;
62
}
127
}
63
128
64
--
129
--
65
2.17.1
130
2.34.1
66
67
diff view generated by jsdifflib
New patch
[PULL 05/20] linux-user: Clear translations on mprotect()
1
From: Ilya Leoshkevich <iii@linux.ibm.com>
1
2
3
Currently it's possible to execute pages that do not have PAGE_EXEC
4
if there is an existing translation block. Fix by invalidating TBs
5
that touch the affected pages.
6
7
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
8
Message-Id: <20220817150506.592862-2-iii@linux.ibm.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
11
linux-user/mmap.c | 6 ++++--
12
1 file changed, 4 insertions(+), 2 deletions(-)
13
14
diff --git a/linux-user/mmap.c b/linux-user/mmap.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/linux-user/mmap.c
17
+++ b/linux-user/mmap.c
18
@@ -XXX,XX +XXX,XX @@ int target_mprotect(abi_ulong start, abi_ulong len, int target_prot)
19
goto error;
20
}
21
}
22
+
23
page_set_flags(start, start + len, page_flags);
24
- mmap_unlock();
25
- return 0;
26
+ tb_invalidate_phys_range(start, start + len);
27
+ ret = 0;
28
+
29
error:
30
mmap_unlock();
31
return ret;
32
--
33
2.34.1
diff view generated by jsdifflib
New patch
[PULL 06/20] tests/tcg/i386: Move smc_code2 to an executable section
1
We're about to start validating PAGE_EXEC, which means
2
that we've got to put this code into a section that is
3
both writable and executable.
1
4
5
Note that this test did not run on hardware beforehand either.
6
7
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
8
Tested-by: Ilya Leoshkevich <iii@linux.ibm.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
11
tests/tcg/i386/test-i386.c | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
13
14
diff --git a/tests/tcg/i386/test-i386.c b/tests/tcg/i386/test-i386.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/tests/tcg/i386/test-i386.c
17
+++ b/tests/tcg/i386/test-i386.c
18
@@ -XXX,XX +XXX,XX @@ uint8_t code[] = {
19
0xc3, /* ret */
20
};
21
22
-asm(".section \".data\"\n"
23
+asm(".section \".data_x\",\"awx\"\n"
24
"smc_code2:\n"
25
"movl 4(%esp), %eax\n"
26
"movl %eax, smc_patch_addr2 + 1\n"
27
--
28
2.34.1
diff view generated by jsdifflib
New patch
[PULL 07/20] accel/tcg: Introduce is_same_page()
1
From: Ilya Leoshkevich <iii@linux.ibm.com>
1
2
3
Introduce a function that checks whether a given address is on the same
4
page as where disassembly started. Having it improves readability of
5
the following patches.
6
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
9
Message-Id: <20220811095534.241224-3-iii@linux.ibm.com>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
[rth: Make the DisasContextBase parameter const.]
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
---
14
include/exec/translator.h | 10 ++++++++++
15
1 file changed, 10 insertions(+)
16
17
diff --git a/include/exec/translator.h b/include/exec/translator.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/exec/translator.h
20
+++ b/include/exec/translator.h
21
@@ -XXX,XX +XXX,XX @@ FOR_EACH_TRANSLATOR_LD(GEN_TRANSLATOR_LD)
22
23
#undef GEN_TRANSLATOR_LD
24
25
+/*
26
+ * Return whether addr is on the same page as where disassembly started.
27
+ * Translators can use this to enforce the rule that only single-insn
28
+ * translation blocks are allowed to cross page boundaries.
29
+ */
30
+static inline bool is_same_page(const DisasContextBase *db, target_ulong addr)
31
+{
32
+ return ((addr ^ db->pc_first) & TARGET_PAGE_MASK) == 0;
33
+}
34
+
35
#endif /* EXEC__TRANSLATOR_H */
36
--
37
2.34.1
diff view generated by jsdifflib
New patch
[PULL 08/20] accel/tcg: Properly implement get_page_addr_code for user-only
1
The current implementation is a no-op, simply returning addr.
2
This is incorrect, because we ought to be checking the page
3
permissions for execution.
1
4
5
Make get_page_addr_code inline for both implementations.
6
7
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
8
Tested-by: Ilya Leoshkevich <iii@linux.ibm.com>
9
Acked-by: Alistair Francis <alistair.francis@wdc.com>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
12
include/exec/exec-all.h | 85 ++++++++++++++---------------------------
13
accel/tcg/cputlb.c | 5 ---
14
accel/tcg/user-exec.c | 14 +++++++
15
3 files changed, 42 insertions(+), 62 deletions(-)
16
17
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
18
index XXXXXXX..XXXXXXX 100644
19
--- a/include/exec/exec-all.h
20
+++ b/include/exec/exec-all.h
21
@@ -XXX,XX +XXX,XX @@ struct MemoryRegionSection *iotlb_to_section(CPUState *cpu,
22
hwaddr index, MemTxAttrs attrs);
23
#endif
24
25
-#if defined(CONFIG_USER_ONLY)
26
-void mmap_lock(void);
27
-void mmap_unlock(void);
28
-bool have_mmap_lock(void);
29
-
30
/**
31
- * get_page_addr_code() - user-mode version
32
+ * get_page_addr_code_hostp()
33
* @env: CPUArchState
34
* @addr: guest virtual address of guest code
35
*
36
- * Returns @addr.
37
+ * See get_page_addr_code() (full-system version) for documentation on the
38
+ * return value.
39
+ *
40
+ * Sets *@hostp (when @hostp is non-NULL) as follows.
41
+ * If the return value is -1, sets *@hostp to NULL. Otherwise, sets *@hostp
42
+ * to the host address where @addr's content is kept.
43
+ *
44
+ * Note: this function can trigger an exception.
45
+ */
46
+tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr,
47
+ void **hostp);
48
+
49
+/**
50
+ * get_page_addr_code()
51
+ * @env: CPUArchState
52
+ * @addr: guest virtual address of guest code
53
+ *
54
+ * If we cannot translate and execute from the entire RAM page, or if
55
+ * the region is not backed by RAM, returns -1. Otherwise, returns the
56
+ * ram_addr_t corresponding to the guest code at @addr.
57
+ *
58
+ * Note: this function can trigger an exception.
59
*/
60
static inline tb_page_addr_t get_page_addr_code(CPUArchState *env,
61
target_ulong addr)
62
{
63
- return addr;
64
+ return get_page_addr_code_hostp(env, addr, NULL);
65
}
66
67
-/**
68
- * get_page_addr_code_hostp() - user-mode version
69
- * @env: CPUArchState
70
- * @addr: guest virtual address of guest code
71
- *
72
- * Returns @addr.
73
- *
74
- * If @hostp is non-NULL, sets *@hostp to the host address where @addr's content
75
- * is kept.
76
- */
77
-static inline tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env,
78
- target_ulong addr,
79
- void **hostp)
80
-{
81
- if (hostp) {
82
- *hostp = g2h_untagged(addr);
83
- }
84
- return addr;
85
-}
86
+#if defined(CONFIG_USER_ONLY)
87
+void mmap_lock(void);
88
+void mmap_unlock(void);
89
+bool have_mmap_lock(void);
90
91
/**
92
* adjust_signal_pc:
93
@@ -XXX,XX +XXX,XX @@ G_NORETURN void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr,
94
static inline void mmap_lock(void) {}
95
static inline void mmap_unlock(void) {}
96
97
-/**
98
- * get_page_addr_code() - full-system version
99
- * @env: CPUArchState
100
- * @addr: guest virtual address of guest code
101
- *
102
- * If we cannot translate and execute from the entire RAM page, or if
103
- * the region is not backed by RAM, returns -1. Otherwise, returns the
104
- * ram_addr_t corresponding to the guest code at @addr.
105
- *
106
- * Note: this function can trigger an exception.
107
- */
108
-tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr);
109
-
110
-/**
111
- * get_page_addr_code_hostp() - full-system version
112
- * @env: CPUArchState
113
- * @addr: guest virtual address of guest code
114
- *
115
- * See get_page_addr_code() (full-system version) for documentation on the
116
- * return value.
117
- *
118
- * Sets *@hostp (when @hostp is non-NULL) as follows.
119
- * If the return value is -1, sets *@hostp to NULL. Otherwise, sets *@hostp
120
- * to the host address where @addr's content is kept.
121
- *
122
- * Note: this function can trigger an exception.
123
- */
124
-tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr,
125
- void **hostp);
126
-
127
void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
128
void tlb_set_dirty(CPUState *cpu, target_ulong vaddr);
129
130
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
131
index XXXXXXX..XXXXXXX 100644
132
--- a/accel/tcg/cputlb.c
133
+++ b/accel/tcg/cputlb.c
134
@@ -XXX,XX +XXX,XX @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr,
135
return qemu_ram_addr_from_host_nofail(p);
136
}
137
138
-tb_page_addr_t get_page_addr_code(CPUArchState *env, target_ulong addr)
139
-{
140
- return get_page_addr_code_hostp(env, addr, NULL);
141
-}
142
-
143
static void notdirty_write(CPUState *cpu, vaddr mem_vaddr, unsigned size,
144
CPUIOTLBEntry *iotlbentry, uintptr_t retaddr)
145
{
146
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
147
index XXXXXXX..XXXXXXX 100644
148
--- a/accel/tcg/user-exec.c
149
+++ b/accel/tcg/user-exec.c
150
@@ -XXX,XX +XXX,XX @@ void *probe_access(CPUArchState *env, target_ulong addr, int size,
151
return size ? g2h(env_cpu(env), addr) : NULL;
152
}
153
154
+tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr,
155
+ void **hostp)
156
+{
157
+ int flags;
158
+
159
+ flags = probe_access_internal(env, addr, 1, MMU_INST_FETCH, false, 0);
160
+ g_assert(flags == 0);
161
+
162
+ if (hostp) {
163
+ *hostp = g2h_untagged(addr);
164
+ }
165
+ return addr;
166
+}
167
+
168
/* The softmmu versions of these helpers are in cputlb.c. */
169
170
/*
171
--
172
2.34.1
diff view generated by jsdifflib
New patch
[PULL 09/20] accel/tcg: Unlock mmap_lock after longjmp
1
The mmap_lock is held around tb_gen_code. While the comment
2
is correct that the lock is dropped when tb_gen_code runs out
3
of memory, the lock is *not* dropped when an exception is
4
raised reading code for translation.
1
5
6
Acked-by: Alistair Francis <alistair.francis@wdc.com>
7
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
8
Tested-by: Ilya Leoshkevich <iii@linux.ibm.com>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
---
11
accel/tcg/cpu-exec.c | 12 ++++++------
12
accel/tcg/user-exec.c | 3 ---
13
2 files changed, 6 insertions(+), 9 deletions(-)
14
15
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/accel/tcg/cpu-exec.c
18
+++ b/accel/tcg/cpu-exec.c
19
@@ -XXX,XX +XXX,XX @@ void cpu_exec_step_atomic(CPUState *cpu)
20
cpu_tb_exec(cpu, tb, &tb_exit);
21
cpu_exec_exit(cpu);
22
} else {
23
- /*
24
- * The mmap_lock is dropped by tb_gen_code if it runs out of
25
- * memory.
26
- */
27
#ifndef CONFIG_SOFTMMU
28
clear_helper_retaddr();
29
- tcg_debug_assert(!have_mmap_lock());
30
+ if (have_mmap_lock()) {
31
+ mmap_unlock();
32
+ }
33
#endif
34
if (qemu_mutex_iothread_locked()) {
35
qemu_mutex_unlock_iothread();
36
@@ -XXX,XX +XXX,XX @@ int cpu_exec(CPUState *cpu)
37
38
#ifndef CONFIG_SOFTMMU
39
clear_helper_retaddr();
40
- tcg_debug_assert(!have_mmap_lock());
41
+ if (have_mmap_lock()) {
42
+ mmap_unlock();
43
+ }
44
#endif
45
if (qemu_mutex_iothread_locked()) {
46
qemu_mutex_unlock_iothread();
47
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
48
index XXXXXXX..XXXXXXX 100644
49
--- a/accel/tcg/user-exec.c
50
+++ b/accel/tcg/user-exec.c
51
@@ -XXX,XX +XXX,XX @@ MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write)
52
* (and if the translator doesn't handle page boundaries correctly
53
* there's little we can do about that here). Therefore, do not
54
* trigger the unwinder.
55
- *
56
- * Like tb_gen_code, release the memory lock before cpu_loop_exit.
57
*/
58
- mmap_unlock();
59
*pc = 0;
60
return MMU_INST_FETCH;
61
}
62
--
63
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/15] tcg/arm: Restrict constant pool displacement to 12 bits
[PULL 10/20] accel/tcg: Make tb_htable_lookup static
1
This will not necessarily restrict the size of the TB, since for v7
1
The function is not used outside of cpu-exec.c. Move it and
2
the majority of constant pool usage is for calls from the out-of-line
2
its subroutines up in the file, before the first use.
3
ldst code, which is already at the end of the TB. But this does
4
allow us to save one insn per reference on the off-chance.
5
3
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
6
Tested-by: Ilya Leoshkevich <iii@linux.ibm.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
---
8
tcg/arm/tcg-target.inc.c | 57 +++++++++++++++-------------------------
9
include/exec/exec-all.h | 3 -
9
1 file changed, 21 insertions(+), 36 deletions(-)
10
accel/tcg/cpu-exec.c | 122 ++++++++++++++++++++--------------------
11
2 files changed, 61 insertions(+), 64 deletions(-)
10
12
11
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
13
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
12
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/arm/tcg-target.inc.c
15
--- a/include/exec/exec-all.h
14
+++ b/tcg/arm/tcg-target.inc.c
16
+++ b/include/exec/exec-all.h
15
@@ -XXX,XX +XXX,XX @@ static inline bool reloc_pc24(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
17
@@ -XXX,XX +XXX,XX @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);
16
return false;
18
#endif
19
void tb_flush(CPUState *cpu);
20
void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
21
-TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
22
- target_ulong cs_base, uint32_t flags,
23
- uint32_t cflags);
24
void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr);
25
26
/* GETPC is the true target of the return instruction that we'll execute. */
27
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/accel/tcg/cpu-exec.c
30
+++ b/accel/tcg/cpu-exec.c
31
@@ -XXX,XX +XXX,XX @@ uint32_t curr_cflags(CPUState *cpu)
32
return cflags;
17
}
33
}
18
34
19
+static inline bool reloc_pc13(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
35
+struct tb_desc {
36
+ target_ulong pc;
37
+ target_ulong cs_base;
38
+ CPUArchState *env;
39
+ tb_page_addr_t phys_page1;
40
+ uint32_t flags;
41
+ uint32_t cflags;
42
+ uint32_t trace_vcpu_dstate;
43
+};
44
+
45
+static bool tb_lookup_cmp(const void *p, const void *d)
20
+{
46
+{
21
+ ptrdiff_t offset = tcg_ptr_byte_diff(target, code_ptr) - 8;
47
+ const TranslationBlock *tb = p;
48
+ const struct tb_desc *desc = d;
22
+
49
+
23
+ if (offset >= -0xfff && offset <= 0xfff) {
50
+ if (tb->pc == desc->pc &&
24
+ tcg_insn_unit insn = *code_ptr;
51
+ tb->page_addr[0] == desc->phys_page1 &&
25
+ bool u = (offset >= 0);
52
+ tb->cs_base == desc->cs_base &&
26
+ if (!u) {
53
+ tb->flags == desc->flags &&
27
+ offset = -offset;
54
+ tb->trace_vcpu_dstate == desc->trace_vcpu_dstate &&
55
+ tb_cflags(tb) == desc->cflags) {
56
+ /* check next page if needed */
57
+ if (tb->page_addr[1] == -1) {
58
+ return true;
59
+ } else {
60
+ tb_page_addr_t phys_page2;
61
+ target_ulong virt_page2;
62
+
63
+ virt_page2 = (desc->pc & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
64
+ phys_page2 = get_page_addr_code(desc->env, virt_page2);
65
+ if (tb->page_addr[1] == phys_page2) {
66
+ return true;
67
+ }
28
+ }
68
+ }
29
+ insn = deposit32(insn, 23, 1, u);
30
+ insn = deposit32(insn, 0, 12, offset);
31
+ *code_ptr = insn;
32
+ return true;
33
+ }
69
+ }
34
+ return false;
70
+ return false;
35
+}
71
+}
36
+
72
+
37
static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
73
+static TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
38
intptr_t value, intptr_t addend)
74
+ target_ulong cs_base, uint32_t flags,
75
+ uint32_t cflags)
76
+{
77
+ tb_page_addr_t phys_pc;
78
+ struct tb_desc desc;
79
+ uint32_t h;
80
+
81
+ desc.env = cpu->env_ptr;
82
+ desc.cs_base = cs_base;
83
+ desc.flags = flags;
84
+ desc.cflags = cflags;
85
+ desc.trace_vcpu_dstate = *cpu->trace_dstate;
86
+ desc.pc = pc;
87
+ phys_pc = get_page_addr_code(desc.env, pc);
88
+ if (phys_pc == -1) {
89
+ return NULL;
90
+ }
91
+ desc.phys_page1 = phys_pc & TARGET_PAGE_MASK;
92
+ h = tb_hash_func(phys_pc, pc, flags, cflags, *cpu->trace_dstate);
93
+ return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp);
94
+}
95
+
96
/* Might cause an exception, so have a longjmp destination ready */
97
static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc,
98
target_ulong cs_base,
99
@@ -XXX,XX +XXX,XX @@ void cpu_exec_step_atomic(CPUState *cpu)
100
end_exclusive();
101
}
102
103
-struct tb_desc {
104
- target_ulong pc;
105
- target_ulong cs_base;
106
- CPUArchState *env;
107
- tb_page_addr_t phys_page1;
108
- uint32_t flags;
109
- uint32_t cflags;
110
- uint32_t trace_vcpu_dstate;
111
-};
112
-
113
-static bool tb_lookup_cmp(const void *p, const void *d)
114
-{
115
- const TranslationBlock *tb = p;
116
- const struct tb_desc *desc = d;
117
-
118
- if (tb->pc == desc->pc &&
119
- tb->page_addr[0] == desc->phys_page1 &&
120
- tb->cs_base == desc->cs_base &&
121
- tb->flags == desc->flags &&
122
- tb->trace_vcpu_dstate == desc->trace_vcpu_dstate &&
123
- tb_cflags(tb) == desc->cflags) {
124
- /* check next page if needed */
125
- if (tb->page_addr[1] == -1) {
126
- return true;
127
- } else {
128
- tb_page_addr_t phys_page2;
129
- target_ulong virt_page2;
130
-
131
- virt_page2 = (desc->pc & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
132
- phys_page2 = get_page_addr_code(desc->env, virt_page2);
133
- if (tb->page_addr[1] == phys_page2) {
134
- return true;
135
- }
136
- }
137
- }
138
- return false;
139
-}
140
-
141
-TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc,
142
- target_ulong cs_base, uint32_t flags,
143
- uint32_t cflags)
144
-{
145
- tb_page_addr_t phys_pc;
146
- struct tb_desc desc;
147
- uint32_t h;
148
-
149
- desc.env = cpu->env_ptr;
150
- desc.cs_base = cs_base;
151
- desc.flags = flags;
152
- desc.cflags = cflags;
153
- desc.trace_vcpu_dstate = *cpu->trace_dstate;
154
- desc.pc = pc;
155
- phys_pc = get_page_addr_code(desc.env, pc);
156
- if (phys_pc == -1) {
157
- return NULL;
158
- }
159
- desc.phys_page1 = phys_pc & TARGET_PAGE_MASK;
160
- h = tb_hash_func(phys_pc, pc, flags, cflags, *cpu->trace_dstate);
161
- return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp);
162
-}
163
-
164
void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr)
39
{
165
{
40
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
166
if (TCG_TARGET_HAS_direct_jump) {
41
if (type == R_ARM_PC24) {
42
return reloc_pc24(code_ptr, (tcg_insn_unit *)value);
43
} else if (type == R_ARM_PC13) {
44
- intptr_t diff = value - (uintptr_t)(code_ptr + 2);
45
- tcg_insn_unit insn = *code_ptr;
46
- bool u;
47
-
48
- if (diff >= -0xfff && diff <= 0xfff) {
49
- u = (diff >= 0);
50
- if (!u) {
51
- diff = -diff;
52
- }
53
- } else {
54
- int rd = extract32(insn, 12, 4);
55
- int rt = rd == TCG_REG_PC ? TCG_REG_TMP : rd;
56
-
57
- if (diff < 0x1000 || diff >= 0x100000) {
58
- return false;
59
- }
60
-
61
- /* add rt, pc, #high */
62
- *code_ptr++ = ((insn & 0xf0000000) | (1 << 25) | ARITH_ADD
63
- | (TCG_REG_PC << 16) | (rt << 12)
64
- | (20 << 7) | (diff >> 12));
65
- /* ldr rd, [rt, #low] */
66
- insn = deposit32(insn, 12, 4, rt);
67
- diff &= 0xfff;
68
- u = 1;
69
- }
70
- insn = deposit32(insn, 23, 1, u);
71
- insn = deposit32(insn, 0, 12, diff);
72
- *code_ptr = insn;
73
+ return reloc_pc13(code_ptr, (tcg_insn_unit *)value);
74
} else {
75
g_assert_not_reached();
76
}
77
- return true;
78
}
79
80
#define TCG_CT_CONST_ARM 0x100
81
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_ld8s_r(TCGContext *s, int cond, TCGReg rt,
82
83
static void tcg_out_movi_pool(TCGContext *s, int cond, int rd, uint32_t arg)
84
{
85
- /* The 12-bit range on the ldr insn is sometimes a bit too small.
86
- In order to get around that we require two insns, one of which
87
- will usually be a nop, but may be replaced in patch_reloc. */
88
new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0);
89
tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0);
90
- tcg_out_nop(s);
91
}
92
93
static void tcg_out_movi32(TCGContext *s, int cond, int rd, uint32_t arg)
94
@@ -XXX,XX +XXX,XX @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *addr)
95
tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri);
96
tcg_out_blx(s, COND_AL, TCG_REG_TMP);
97
} else {
98
- /* ??? Know that movi_pool emits exactly 2 insns. */
99
- tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 4);
100
+ /* ??? Know that movi_pool emits exactly 1 insn. */
101
+ tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 0);
102
tcg_out_movi_pool(s, COND_AL, TCG_REG_PC, addri);
103
}
104
}
105
--
167
--
106
2.17.1
168
2.34.1
107
108
diff view generated by jsdifflib
New patch
[PULL 11/20] accel/tcg: Move qemu_ram_addr_from_host_nofail to physmem.c
1
The base qemu_ram_addr_from_host function is already in
2
softmmu/physmem.c; move the nofail version to be adjacent.
1
3
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
6
Tested-by: Ilya Leoshkevich <iii@linux.ibm.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
9
include/exec/cpu-common.h | 1 +
10
accel/tcg/cputlb.c | 12 ------------
11
softmmu/physmem.c | 12 ++++++++++++
12
3 files changed, 13 insertions(+), 12 deletions(-)
13
14
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/include/exec/cpu-common.h
17
+++ b/include/exec/cpu-common.h
18
@@ -XXX,XX +XXX,XX @@ typedef uintptr_t ram_addr_t;
19
void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
20
/* This should not be used by devices. */
21
ram_addr_t qemu_ram_addr_from_host(void *ptr);
22
+ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr);
23
RAMBlock *qemu_ram_block_by_name(const char *name);
24
RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
25
ram_addr_t *offset);
26
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/accel/tcg/cputlb.c
29
+++ b/accel/tcg/cputlb.c
30
@@ -XXX,XX +XXX,XX @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr,
31
prot, mmu_idx, size);
32
}
33
34
-static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr)
35
-{
36
- ram_addr_t ram_addr;
37
-
38
- ram_addr = qemu_ram_addr_from_host(ptr);
39
- if (ram_addr == RAM_ADDR_INVALID) {
40
- error_report("Bad ram pointer %p", ptr);
41
- abort();
42
- }
43
- return ram_addr;
44
-}
45
-
46
/*
47
* Note: tlb_fill() can trigger a resize of the TLB. This means that all of the
48
* caller's prior references to the TLB table (e.g. CPUTLBEntry pointers) must
49
diff --git a/softmmu/physmem.c b/softmmu/physmem.c
50
index XXXXXXX..XXXXXXX 100644
51
--- a/softmmu/physmem.c
52
+++ b/softmmu/physmem.c
53
@@ -XXX,XX +XXX,XX @@ ram_addr_t qemu_ram_addr_from_host(void *ptr)
54
return block->offset + offset;
55
}
56
57
+ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr)
58
+{
59
+ ram_addr_t ram_addr;
60
+
61
+ ram_addr = qemu_ram_addr_from_host(ptr);
62
+ if (ram_addr == RAM_ADDR_INVALID) {
63
+ error_report("Bad ram pointer %p", ptr);
64
+ abort();
65
+ }
66
+ return ram_addr;
67
+}
68
+
69
static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
70
MemTxAttrs attrs, void *buf, hwaddr len);
71
static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
72
--
73
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/15] cputlb: Fix io_readx() to respect the access_type
[PULL 12/20] accel/tcg: Use probe_access_internal for softmmu get_page_addr_code_hostp
1
From: Shahab Vahedi <shahab.vahedi@gmail.com>
1
Simplify the implementation of get_page_addr_code_hostp
2
by reusing the existing probe_access infrastructure.
2
3
3
This change adapts io_readx() to its input access_type. Currently
4
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
4
io_readx() treats any memory access as a read, although it has an
5
Tested-by: Ilya Leoshkevich <iii@linux.ibm.com>
5
input argument "MMUAccessType access_type". This results in:
6
7
1) Calling the tlb_fill() only with MMU_DATA_LOAD
8
2) Considering only entry->addr_read as the tlb_addr
9
10
Buglink: https://bugs.launchpad.net/qemu/+bug/1825359
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Shahab Vahedi <shahab.vahedi@gmail.com>
13
Message-Id: <20190420072236.12347-1-shahab.vahedi@gmail.com>
14
[rth: Remove assert; fix expression formatting.]
15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16
---
7
---
17
accel/tcg/cputlb.c | 5 +++--
8
accel/tcg/cputlb.c | 76 ++++++++++++++++------------------------------
18
1 file changed, 3 insertions(+), 2 deletions(-)
9
1 file changed, 26 insertions(+), 50 deletions(-)
19
10
20
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
11
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
21
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
22
--- a/accel/tcg/cputlb.c
13
--- a/accel/tcg/cputlb.c
23
+++ b/accel/tcg/cputlb.c
14
+++ b/accel/tcg/cputlb.c
24
@@ -XXX,XX +XXX,XX @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
15
@@ -XXX,XX +XXX,XX @@ static bool victim_tlb_hit(CPUArchState *env, size_t mmu_idx, size_t index,
25
CPUTLBEntry *entry;
16
victim_tlb_hit(env, mmu_idx, index, offsetof(CPUTLBEntry, TY), \
26
target_ulong tlb_addr;
17
(ADDR) & TARGET_PAGE_MASK)
27
18
28
- tlb_fill(cpu, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr);
19
-/*
29
+ tlb_fill(cpu, addr, size, access_type, mmu_idx, retaddr);
20
- * Return a ram_addr_t for the virtual address for execution.
30
21
- *
31
entry = tlb_entry(env, mmu_idx, addr);
22
- * Return -1 if we can't translate and execute from an entire page
32
- tlb_addr = entry->addr_read;
23
- * of RAM. This will force us to execute by loading and translating
33
+ tlb_addr = (access_type == MMU_DATA_LOAD ?
24
- * one insn at a time, without caching.
34
+ entry->addr_read : entry->addr_code);
25
- *
35
if (!(tlb_addr & ~(TARGET_PAGE_MASK | TLB_RECHECK))) {
26
- * NOTE: This function will trigger an exception if the page is
36
/* RAM access */
27
- * not executable.
37
uintptr_t haddr = addr + entry->addend;
28
- */
29
-tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr,
30
- void **hostp)
31
-{
32
- uintptr_t mmu_idx = cpu_mmu_index(env, true);
33
- uintptr_t index = tlb_index(env, mmu_idx, addr);
34
- CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr);
35
- void *p;
36
-
37
- if (unlikely(!tlb_hit(entry->addr_code, addr))) {
38
- if (!VICTIM_TLB_HIT(addr_code, addr)) {
39
- tlb_fill(env_cpu(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0);
40
- index = tlb_index(env, mmu_idx, addr);
41
- entry = tlb_entry(env, mmu_idx, addr);
42
-
43
- if (unlikely(entry->addr_code & TLB_INVALID_MASK)) {
44
- /*
45
- * The MMU protection covers a smaller range than a target
46
- * page, so we must redo the MMU check for every insn.
47
- */
48
- return -1;
49
- }
50
- }
51
- assert(tlb_hit(entry->addr_code, addr));
52
- }
53
-
54
- if (unlikely(entry->addr_code & TLB_MMIO)) {
55
- /* The region is not backed by RAM. */
56
- if (hostp) {
57
- *hostp = NULL;
58
- }
59
- return -1;
60
- }
61
-
62
- p = (void *)((uintptr_t)addr + entry->addend);
63
- if (hostp) {
64
- *hostp = p;
65
- }
66
- return qemu_ram_addr_from_host_nofail(p);
67
-}
68
-
69
static void notdirty_write(CPUState *cpu, vaddr mem_vaddr, unsigned size,
70
CPUIOTLBEntry *iotlbentry, uintptr_t retaddr)
71
{
72
@@ -XXX,XX +XXX,XX @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
73
return flags ? NULL : host;
74
}
75
76
+/*
77
+ * Return a ram_addr_t for the virtual address for execution.
78
+ *
79
+ * Return -1 if we can't translate and execute from an entire page
80
+ * of RAM. This will force us to execute by loading and translating
81
+ * one insn at a time, without caching.
82
+ *
83
+ * NOTE: This function will trigger an exception if the page is
84
+ * not executable.
85
+ */
86
+tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr,
87
+ void **hostp)
88
+{
89
+ void *p;
90
+
91
+ (void)probe_access_internal(env, addr, 1, MMU_INST_FETCH,
92
+ cpu_mmu_index(env, true), false, &p, 0);
93
+ if (p == NULL) {
94
+ return -1;
95
+ }
96
+ if (hostp) {
97
+ *hostp = p;
98
+ }
99
+ return qemu_ram_addr_from_host_nofail(p);
100
+}
101
+
102
#ifdef CONFIG_PLUGIN
103
/*
104
* Perform a TLB lookup and populate the qemu_plugin_hwaddr structure.
38
--
105
--
39
2.17.1
106
2.34.1
40
41
diff view generated by jsdifflib
New patch
[PULL 13/20] accel/tcg: Document the faulting lookup in tb_lookup_cmp
1
It was non-obvious to me why we can raise an exception in
2
the middle of a comparison function, but it works.
3
While nearby, use TARGET_PAGE_ALIGN instead of open-coding.
1
4
5
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
accel/tcg/cpu-exec.c | 11 ++++++++++-
9
1 file changed, 10 insertions(+), 1 deletion(-)
10
11
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/accel/tcg/cpu-exec.c
14
+++ b/accel/tcg/cpu-exec.c
15
@@ -XXX,XX +XXX,XX @@ static bool tb_lookup_cmp(const void *p, const void *d)
16
tb_page_addr_t phys_page2;
17
target_ulong virt_page2;
18
19
- virt_page2 = (desc->pc & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
20
+ /*
21
+ * We know that the first page matched, and an otherwise valid TB
22
+ * encountered an incomplete instruction at the end of that page,
23
+ * therefore we know that generating a new TB from the current PC
24
+ * must also require reading from the next page -- even if the
25
+ * second pages do not match, and therefore the resulting insn
26
+ * is different for the new TB. Therefore any exception raised
27
+ * here by the faulting lookup is not premature.
28
+ */
29
+ virt_page2 = TARGET_PAGE_ALIGN(desc->pc);
30
phys_page2 = get_page_addr_code(desc->env, virt_page2);
31
if (tb->page_addr[1] == phys_page2) {
32
return true;
33
--
34
2.34.1
diff view generated by jsdifflib
New patch
[PULL 14/20] accel/tcg: Remove translator_ldsw
1
The only user can easily use translator_lduw and
2
adjust the type to signed during the return.
1
3
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
6
Tested-by: Ilya Leoshkevich <iii@linux.ibm.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
9
include/exec/translator.h | 1 -
10
target/i386/tcg/translate.c | 2 +-
11
2 files changed, 1 insertion(+), 2 deletions(-)
12
13
diff --git a/include/exec/translator.h b/include/exec/translator.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/include/exec/translator.h
16
+++ b/include/exec/translator.h
17
@@ -XXX,XX +XXX,XX @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest);
18
19
#define FOR_EACH_TRANSLATOR_LD(F) \
20
F(translator_ldub, uint8_t, cpu_ldub_code, /* no swap */) \
21
- F(translator_ldsw, int16_t, cpu_ldsw_code, bswap16) \
22
F(translator_lduw, uint16_t, cpu_lduw_code, bswap16) \
23
F(translator_ldl, uint32_t, cpu_ldl_code, bswap32) \
24
F(translator_ldq, uint64_t, cpu_ldq_code, bswap64)
25
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/target/i386/tcg/translate.c
28
+++ b/target/i386/tcg/translate.c
29
@@ -XXX,XX +XXX,XX @@ static inline uint8_t x86_ldub_code(CPUX86State *env, DisasContext *s)
30
31
static inline int16_t x86_ldsw_code(CPUX86State *env, DisasContext *s)
32
{
33
- return translator_ldsw(env, &s->base, advance_pc(env, s, 2));
34
+ return translator_lduw(env, &s->base, advance_pc(env, s, 2));
35
}
36
37
static inline uint16_t x86_lduw_code(CPUX86State *env, DisasContext *s)
38
--
39
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/15] tcg: Hoist max_insns computation to tb_gen_code
[PULL 15/20] accel/tcg: Add pc and host_pc params to gen_intermediate_code
1
In order to handle TB's that translate to too much code, we
1
Pass these along to translator_loop -- pc may be used instead
2
need to place the control of the length of the translation
2
of tb->pc, and host_pc is currently unused. Adjust all targets
3
in the hands of the code gen master loop.
3
at one time.
4
4
5
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
Acked-by: Alistair Francis <alistair.francis@wdc.com>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
6
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
7
Tested-by: Ilya Leoshkevich <iii@linux.ibm.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
9
---
9
include/exec/exec-all.h | 4 ++--
10
include/exec/exec-all.h | 1 -
10
include/exec/translator.h | 3 ++-
11
include/exec/translator.h | 24 ++++++++++++++++++++----
11
accel/tcg/translate-all.c | 15 +++++++++++++--
12
accel/tcg/translate-all.c | 6 ++++--
12
accel/tcg/translator.c | 15 ++-------------
13
accel/tcg/translator.c | 9 +++++----
13
target/alpha/translate.c | 4 ++--
14
target/alpha/translate.c | 5 +++--
14
target/arm/translate.c | 4 ++--
15
target/arm/translate.c | 5 +++--
15
target/cris/translate.c | 10 +---------
16
target/avr/translate.c | 5 +++--
16
target/hppa/translate.c | 5 ++---
17
target/cris/translate.c | 5 +++--
17
target/i386/translate.c | 4 ++--
18
target/hexagon/translate.c | 6 ++++--
18
target/lm32/translate.c | 10 +---------
19
target/hppa/translate.c | 5 +++--
19
target/m68k/translate.c | 4 ++--
20
target/i386/tcg/translate.c | 5 +++--
20
target/microblaze/translate.c | 10 +---------
21
target/loongarch/translate.c | 6 ++++--
21
target/mips/translate.c | 4 ++--
22
target/m68k/translate.c | 5 +++--
22
target/moxie/translate.c | 11 ++---------
23
target/microblaze/translate.c | 5 +++--
23
target/nios2/translate.c | 14 ++------------
24
target/mips/tcg/translate.c | 5 +++--
24
target/openrisc/translate.c | 4 ++--
25
target/nios2/translate.c | 5 +++--
25
target/ppc/translate.c | 4 ++--
26
target/openrisc/translate.c | 6 ++++--
26
target/riscv/translate.c | 4 ++--
27
target/ppc/translate.c | 5 +++--
27
target/s390x/translate.c | 4 ++--
28
target/riscv/translate.c | 5 +++--
28
target/sh4/translate.c | 4 ++--
29
target/rx/translate.c | 5 +++--
29
target/sparc/translate.c | 4 ++--
30
target/s390x/tcg/translate.c | 5 +++--
30
target/tilegx/translate.c | 12 +-----------
31
target/sh4/translate.c | 5 +++--
31
target/tricore/translate.c | 16 ++--------------
32
target/sparc/translate.c | 5 +++--
32
target/unicore32/translate.c | 10 +---------
33
target/tricore/translate.c | 6 ++++--
33
target/xtensa/translate.c | 4 ++--
34
target/xtensa/translate.c | 6 ++++--
34
25 files changed, 56 insertions(+), 127 deletions(-)
35
25 files changed, 97 insertions(+), 53 deletions(-)
35
36
36
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
37
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
37
index XXXXXXX..XXXXXXX 100644
38
index XXXXXXX..XXXXXXX 100644
38
--- a/include/exec/exec-all.h
39
--- a/include/exec/exec-all.h
39
+++ b/include/exec/exec-all.h
40
+++ b/include/exec/exec-all.h
40
@@ -XXX,XX +XXX,XX @@ typedef ram_addr_t tb_page_addr_t;
41
@@ -XXX,XX +XXX,XX @@ typedef ram_addr_t tb_page_addr_t;
41
42
#define TB_PAGE_ADDR_FMT RAM_ADDR_FMT
42
#include "qemu/log.h"
43
#endif
43
44
44
-void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb);
45
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns);
45
-void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
46
void restore_state_to_opc(CPUArchState *env, TranslationBlock *tb,
46
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns);
47
+void restore_state_to_opc(CPUArchState *env, TranslationBlock *tb,
48
target_ulong *data);
47
target_ulong *data);
49
48
50
void cpu_gen_init(void);
51
diff --git a/include/exec/translator.h b/include/exec/translator.h
49
diff --git a/include/exec/translator.h b/include/exec/translator.h
52
index XXXXXXX..XXXXXXX 100644
50
index XXXXXXX..XXXXXXX 100644
53
--- a/include/exec/translator.h
51
--- a/include/exec/translator.h
54
+++ b/include/exec/translator.h
52
+++ b/include/exec/translator.h
53
@@ -XXX,XX +XXX,XX @@
54
#include "exec/translate-all.h"
55
#include "tcg/tcg.h"
56
57
+/**
58
+ * gen_intermediate_code
59
+ * @cpu: cpu context
60
+ * @tb: translation block
61
+ * @max_insns: max number of instructions to translate
62
+ * @pc: guest virtual program counter address
63
+ * @host_pc: host physical program counter address
64
+ *
65
+ * This function must be provided by the target, which should create
66
+ * the target-specific DisasContext, and then invoke translator_loop.
67
+ */
68
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns,
69
+ target_ulong pc, void *host_pc);
70
71
/**
72
* DisasJumpType:
55
@@ -XXX,XX +XXX,XX @@ typedef struct TranslatorOps {
73
@@ -XXX,XX +XXX,XX @@ typedef struct TranslatorOps {
56
* @db: Disassembly context.
74
75
/**
76
* translator_loop:
77
- * @ops: Target-specific operations.
78
- * @db: Disassembly context.
57
* @cpu: Target vCPU.
79
* @cpu: Target vCPU.
58
* @tb: Translation block.
80
* @tb: Translation block.
59
+ * @max_insns: Maximum number of insns to translate.
81
* @max_insns: Maximum number of insns to translate.
82
+ * @pc: guest virtual program counter address
83
+ * @host_pc: host physical program counter address
84
+ * @ops: Target-specific operations.
85
+ * @db: Disassembly context.
60
*
86
*
61
* Generic translator loop.
87
* Generic translator loop.
62
*
88
*
63
@@ -XXX,XX +XXX,XX @@ typedef struct TranslatorOps {
89
@@ -XXX,XX +XXX,XX @@ typedef struct TranslatorOps {
90
* - When single-stepping is enabled (system-wide or on the current vCPU).
64
* - When too many instructions have been translated.
91
* - When too many instructions have been translated.
65
*/
92
*/
66
void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
93
-void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
67
- CPUState *cpu, TranslationBlock *tb);
94
- CPUState *cpu, TranslationBlock *tb, int max_insns);
68
+ CPUState *cpu, TranslationBlock *tb, int max_insns);
95
+void translator_loop(CPUState *cpu, TranslationBlock *tb, int max_insns,
96
+ target_ulong pc, void *host_pc,
97
+ const TranslatorOps *ops, DisasContextBase *db);
69
98
70
void translator_loop_temp_check(DisasContextBase *db);
99
void translator_loop_temp_check(DisasContextBase *db);
71
100
72
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
101
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
73
index XXXXXXX..XXXXXXX 100644
102
index XXXXXXX..XXXXXXX 100644
74
--- a/accel/tcg/translate-all.c
103
--- a/accel/tcg/translate-all.c
75
+++ b/accel/tcg/translate-all.c
104
+++ b/accel/tcg/translate-all.c
105
@@ -XXX,XX +XXX,XX @@
106
107
#include "exec/cputlb.h"
108
#include "exec/translate-all.h"
109
+#include "exec/translator.h"
110
#include "qemu/bitmap.h"
111
#include "qemu/qemu-print.h"
112
#include "qemu/timer.h"
76
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
113
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
77
tb_page_addr_t phys_pc, phys_page2;
78
target_ulong virt_page2;
79
tcg_insn_unit *gen_code_buf;
80
- int gen_code_size, search_size;
81
+ int gen_code_size, search_size, max_insns;
82
#ifdef CONFIG_PROFILER
83
TCGProfile *prof = &tcg_ctx->prof;
114
TCGProfile *prof = &tcg_ctx->prof;
84
int64_t ti;
115
int64_t ti;
85
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
116
#endif
86
cflags &= ~CF_CLUSTER_MASK;
117
+ void *host_pc;
87
cflags |= cpu->cluster_index << CF_CLUSTER_SHIFT;
118
88
119
assert_memory_lock();
89
+ max_insns = cflags & CF_COUNT_MASK;
120
qemu_thread_jit_write();
90
+ if (max_insns == 0) {
121
91
+ max_insns = CF_COUNT_MASK;
122
- phys_pc = get_page_addr_code(env, pc);
92
+ }
123
+ phys_pc = get_page_addr_code_hostp(env, pc, &host_pc);
93
+ if (max_insns > TCG_MAX_INSNS) {
124
94
+ max_insns = TCG_MAX_INSNS;
125
if (phys_pc == -1) {
95
+ }
126
/* Generate a one-shot TB with 1 insn in it */
96
+ if (cpu->singlestep_enabled || singlestep) {
97
+ max_insns = 1;
98
+ }
99
+
100
buffer_overflow:
101
tb = tb_alloc(pc);
102
if (unlikely(!tb)) {
103
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
127
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
104
tcg_func_start(tcg_ctx);
128
tcg_func_start(tcg_ctx);
105
129
106
tcg_ctx->cpu = ENV_GET_CPU(env);
130
tcg_ctx->cpu = env_cpu(env);
107
- gen_intermediate_code(cpu, tb);
131
- gen_intermediate_code(cpu, tb, max_insns);
108
+ gen_intermediate_code(cpu, tb, max_insns);
132
+ gen_intermediate_code(cpu, tb, max_insns, pc, host_pc);
133
assert(tb->size != 0);
109
tcg_ctx->cpu = NULL;
134
tcg_ctx->cpu = NULL;
110
135
max_insns = tb->icount;
111
trace_translate_block(tb, tb->pc, tb->tc.ptr);
112
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
136
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
113
index XXXXXXX..XXXXXXX 100644
137
index XXXXXXX..XXXXXXX 100644
114
--- a/accel/tcg/translator.c
138
--- a/accel/tcg/translator.c
115
+++ b/accel/tcg/translator.c
139
+++ b/accel/tcg/translator.c
116
@@ -XXX,XX +XXX,XX @@ void translator_loop_temp_check(DisasContextBase *db)
140
@@ -XXX,XX +XXX,XX @@ static inline void translator_page_protect(DisasContextBase *dcbase,
117
}
141
#endif
118
142
}
119
void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
143
120
- CPUState *cpu, TranslationBlock *tb)
144
-void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
121
+ CPUState *cpu, TranslationBlock *tb, int max_insns)
145
- CPUState *cpu, TranslationBlock *tb, int max_insns)
122
{
146
+void translator_loop(CPUState *cpu, TranslationBlock *tb, int max_insns,
123
int bp_insn = 0;
147
+ target_ulong pc, void *host_pc,
124
148
+ const TranslatorOps *ops, DisasContextBase *db)
125
@@ -XXX,XX +XXX,XX @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
149
{
126
db->pc_next = db->pc_first;
150
uint32_t cflags = tb_cflags(tb);
151
bool plugin_enabled;
152
153
/* Initialize DisasContext */
154
db->tb = tb;
155
- db->pc_first = tb->pc;
156
- db->pc_next = db->pc_first;
157
+ db->pc_first = pc;
158
+ db->pc_next = pc;
127
db->is_jmp = DISAS_NEXT;
159
db->is_jmp = DISAS_NEXT;
128
db->num_insns = 0;
160
db->num_insns = 0;
129
+ db->max_insns = max_insns;
161
db->max_insns = max_insns;
130
db->singlestep_enabled = cpu->singlestep_enabled;
131
132
- /* Instruction counting */
133
- db->max_insns = tb_cflags(db->tb) & CF_COUNT_MASK;
134
- if (db->max_insns == 0) {
135
- db->max_insns = CF_COUNT_MASK;
136
- }
137
- if (db->max_insns > TCG_MAX_INSNS) {
138
- db->max_insns = TCG_MAX_INSNS;
139
- }
140
- if (db->singlestep_enabled || singlestep) {
141
- db->max_insns = 1;
142
- }
143
-
144
ops->init_disas_context(db, cpu);
145
tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */
146
147
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
162
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
148
index XXXXXXX..XXXXXXX 100644
163
index XXXXXXX..XXXXXXX 100644
149
--- a/target/alpha/translate.c
164
--- a/target/alpha/translate.c
150
+++ b/target/alpha/translate.c
165
+++ b/target/alpha/translate.c
151
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps alpha_tr_ops = {
166
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps alpha_tr_ops = {
152
.disas_log = alpha_tr_disas_log,
167
.disas_log = alpha_tr_disas_log,
153
};
168
};
154
169
155
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
170
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
156
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
171
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns,
157
{
172
+ target_ulong pc, void *host_pc)
158
DisasContext dc;
173
{
159
- translator_loop(&alpha_tr_ops, &dc.base, cpu, tb);
174
DisasContext dc;
160
+ translator_loop(&alpha_tr_ops, &dc.base, cpu, tb, max_insns);
175
- translator_loop(&alpha_tr_ops, &dc.base, cpu, tb, max_insns);
161
}
176
+ translator_loop(cpu, tb, max_insns, pc, host_pc, &alpha_tr_ops, &dc.base);
177
}
162
178
163
void restore_state_to_opc(CPUAlphaState *env, TranslationBlock *tb,
179
void restore_state_to_opc(CPUAlphaState *env, TranslationBlock *tb,
164
diff --git a/target/arm/translate.c b/target/arm/translate.c
180
diff --git a/target/arm/translate.c b/target/arm/translate.c
165
index XXXXXXX..XXXXXXX 100644
181
index XXXXXXX..XXXXXXX 100644
166
--- a/target/arm/translate.c
182
--- a/target/arm/translate.c
167
+++ b/target/arm/translate.c
183
+++ b/target/arm/translate.c
168
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps thumb_translator_ops = {
184
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps thumb_translator_ops = {
169
};
185
};
170
186
171
/* generate intermediate code for basic block 'tb'. */
187
/* generate intermediate code for basic block 'tb'. */
172
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
188
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
173
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
189
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns,
174
{
190
+ target_ulong pc, void *host_pc)
175
DisasContext dc;
191
{
192
DisasContext dc = { };
176
const TranslatorOps *ops = &arm_translator_ops;
193
const TranslatorOps *ops = &arm_translator_ops;
177
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
194
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
178
}
195
}
179
#endif
196
#endif
180
197
181
- translator_loop(ops, &dc.base, cpu, tb);
198
- translator_loop(ops, &dc.base, cpu, tb, max_insns);
182
+ translator_loop(ops, &dc.base, cpu, tb, max_insns);
199
+ translator_loop(cpu, tb, max_insns, pc, host_pc, ops, &dc.base);
183
}
200
}
184
201
185
void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
202
void restore_state_to_opc(CPUARMState *env, TranslationBlock *tb,
203
diff --git a/target/avr/translate.c b/target/avr/translate.c
204
index XXXXXXX..XXXXXXX 100644
205
--- a/target/avr/translate.c
206
+++ b/target/avr/translate.c
207
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps avr_tr_ops = {
208
.disas_log = avr_tr_disas_log,
209
};
210
211
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
212
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
213
+ target_ulong pc, void *host_pc)
214
{
215
DisasContext dc = { };
216
- translator_loop(&avr_tr_ops, &dc.base, cs, tb, max_insns);
217
+ translator_loop(cs, tb, max_insns, pc, host_pc, &avr_tr_ops, &dc.base);
218
}
219
220
void restore_state_to_opc(CPUAVRState *env, TranslationBlock *tb,
186
diff --git a/target/cris/translate.c b/target/cris/translate.c
221
diff --git a/target/cris/translate.c b/target/cris/translate.c
187
index XXXXXXX..XXXXXXX 100644
222
index XXXXXXX..XXXXXXX 100644
188
--- a/target/cris/translate.c
223
--- a/target/cris/translate.c
189
+++ b/target/cris/translate.c
224
+++ b/target/cris/translate.c
190
@@ -XXX,XX +XXX,XX @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
225
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps cris_tr_ops = {
191
*/
226
.disas_log = cris_tr_disas_log,
192
227
};
193
/* generate intermediate code for basic block 'tb'. */
228
194
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
229
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
195
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
230
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
196
{
231
+ target_ulong pc, void *host_pc)
197
CPUCRISState *env = cs->env_ptr;
232
{
198
uint32_t pc_start;
233
DisasContext dc;
199
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
234
- translator_loop(&cris_tr_ops, &dc.base, cs, tb, max_insns);
200
uint32_t page_start;
235
+ translator_loop(cs, tb, max_insns, pc, host_pc, &cris_tr_ops, &dc.base);
201
target_ulong npc;
236
}
202
int num_insns;
237
203
- int max_insns;
238
void cris_cpu_dump_state(CPUState *cs, FILE *f, int flags)
204
239
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
205
if (env->pregs[PR_VR] == 32) {
240
index XXXXXXX..XXXXXXX 100644
206
dc->decoder = crisv32_decoder;
241
--- a/target/hexagon/translate.c
207
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
242
+++ b/target/hexagon/translate.c
208
243
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps hexagon_tr_ops = {
209
page_start = pc_start & TARGET_PAGE_MASK;
244
.disas_log = hexagon_tr_disas_log,
210
num_insns = 0;
245
};
211
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
246
212
- if (max_insns == 0) {
247
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
213
- max_insns = CF_COUNT_MASK;
248
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
214
- }
249
+ target_ulong pc, void *host_pc)
215
- if (max_insns > TCG_MAX_INSNS) {
250
{
216
- max_insns = TCG_MAX_INSNS;
251
DisasContext ctx;
217
- }
252
218
253
- translator_loop(&hexagon_tr_ops, &ctx.base, cs, tb, max_insns);
219
gen_tb_start(tb);
254
+ translator_loop(cs, tb, max_insns, pc, host_pc,
220
do {
255
+ &hexagon_tr_ops, &ctx.base);
256
}
257
258
#define NAME_LEN 64
221
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
259
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
222
index XXXXXXX..XXXXXXX 100644
260
index XXXXXXX..XXXXXXX 100644
223
--- a/target/hppa/translate.c
261
--- a/target/hppa/translate.c
224
+++ b/target/hppa/translate.c
262
+++ b/target/hppa/translate.c
225
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps hppa_tr_ops = {
263
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps hppa_tr_ops = {
226
.disas_log = hppa_tr_disas_log,
264
.disas_log = hppa_tr_disas_log,
227
};
265
};
228
266
229
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
267
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
230
-
268
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
231
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
269
+ target_ulong pc, void *host_pc)
232
{
270
{
233
DisasContext ctx;
271
DisasContext ctx;
234
- translator_loop(&hppa_tr_ops, &ctx.base, cs, tb);
272
- translator_loop(&hppa_tr_ops, &ctx.base, cs, tb, max_insns);
235
+ translator_loop(&hppa_tr_ops, &ctx.base, cs, tb, max_insns);
273
+ translator_loop(cs, tb, max_insns, pc, host_pc, &hppa_tr_ops, &ctx.base);
236
}
274
}
237
275
238
void restore_state_to_opc(CPUHPPAState *env, TranslationBlock *tb,
276
void restore_state_to_opc(CPUHPPAState *env, TranslationBlock *tb,
239
diff --git a/target/i386/translate.c b/target/i386/translate.c
277
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
240
index XXXXXXX..XXXXXXX 100644
278
index XXXXXXX..XXXXXXX 100644
241
--- a/target/i386/translate.c
279
--- a/target/i386/tcg/translate.c
242
+++ b/target/i386/translate.c
280
+++ b/target/i386/tcg/translate.c
243
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps i386_tr_ops = {
281
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps i386_tr_ops = {
244
};
282
};
245
283
246
/* generate intermediate code for basic block 'tb'. */
284
/* generate intermediate code for basic block 'tb'. */
247
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
285
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
248
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
286
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns,
249
{
287
+ target_ulong pc, void *host_pc)
250
DisasContext dc;
288
{
251
289
DisasContext dc;
252
- translator_loop(&i386_tr_ops, &dc.base, cpu, tb);
290
253
+ translator_loop(&i386_tr_ops, &dc.base, cpu, tb, max_insns);
291
- translator_loop(&i386_tr_ops, &dc.base, cpu, tb, max_insns);
254
}
292
+ translator_loop(cpu, tb, max_insns, pc, host_pc, &i386_tr_ops, &dc.base);
293
}
255
294
256
void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb,
295
void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb,
257
diff --git a/target/lm32/translate.c b/target/lm32/translate.c
296
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
258
index XXXXXXX..XXXXXXX 100644
297
index XXXXXXX..XXXXXXX 100644
259
--- a/target/lm32/translate.c
298
--- a/target/loongarch/translate.c
260
+++ b/target/lm32/translate.c
299
+++ b/target/loongarch/translate.c
261
@@ -XXX,XX +XXX,XX @@ static inline void decode(DisasContext *dc, uint32_t ir)
300
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps loongarch_tr_ops = {
262
}
301
.disas_log = loongarch_tr_disas_log,
263
302
};
264
/* generate intermediate code for basic block 'tb'. */
303
265
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
304
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
266
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
305
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
267
{
306
+ target_ulong pc, void *host_pc)
268
CPULM32State *env = cs->env_ptr;
307
{
269
LM32CPU *cpu = lm32_env_get_cpu(env);
308
DisasContext ctx;
270
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
309
271
uint32_t pc_start;
310
- translator_loop(&loongarch_tr_ops, &ctx.base, cs, tb, max_insns);
272
uint32_t page_start;
311
+ translator_loop(cs, tb, max_insns, pc, host_pc,
273
int num_insns;
312
+ &loongarch_tr_ops, &ctx.base);
274
- int max_insns;
313
}
275
314
276
pc_start = tb->pc;
315
void loongarch_translate_init(void)
277
dc->features = cpu->features;
278
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
279
280
page_start = pc_start & TARGET_PAGE_MASK;
281
num_insns = 0;
282
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
283
- if (max_insns == 0) {
284
- max_insns = CF_COUNT_MASK;
285
- }
286
- if (max_insns > TCG_MAX_INSNS) {
287
- max_insns = TCG_MAX_INSNS;
288
- }
289
290
gen_tb_start(tb);
291
do {
292
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
316
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
293
index XXXXXXX..XXXXXXX 100644
317
index XXXXXXX..XXXXXXX 100644
294
--- a/target/m68k/translate.c
318
--- a/target/m68k/translate.c
295
+++ b/target/m68k/translate.c
319
+++ b/target/m68k/translate.c
296
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps m68k_tr_ops = {
320
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps m68k_tr_ops = {
297
.disas_log = m68k_tr_disas_log,
321
.disas_log = m68k_tr_disas_log,
298
};
322
};
299
323
300
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
324
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
301
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
325
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns,
302
{
326
+ target_ulong pc, void *host_pc)
303
DisasContext dc;
327
{
304
- translator_loop(&m68k_tr_ops, &dc.base, cpu, tb);
328
DisasContext dc;
305
+ translator_loop(&m68k_tr_ops, &dc.base, cpu, tb, max_insns);
329
- translator_loop(&m68k_tr_ops, &dc.base, cpu, tb, max_insns);
306
}
330
+ translator_loop(cpu, tb, max_insns, pc, host_pc, &m68k_tr_ops, &dc.base);
331
}
307
332
308
static double floatx80_to_double(CPUM68KState *env, uint16_t high, uint64_t low)
333
static double floatx80_to_double(CPUM68KState *env, uint16_t high, uint64_t low)
309
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
334
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
310
index XXXXXXX..XXXXXXX 100644
335
index XXXXXXX..XXXXXXX 100644
311
--- a/target/microblaze/translate.c
336
--- a/target/microblaze/translate.c
312
+++ b/target/microblaze/translate.c
337
+++ b/target/microblaze/translate.c
313
@@ -XXX,XX +XXX,XX @@ static inline void decode(DisasContext *dc, uint32_t ir)
338
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps mb_tr_ops = {
314
}
339
.disas_log = mb_tr_disas_log,
315
340
};
316
/* generate intermediate code for basic block 'tb'. */
341
317
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
342
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
318
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
343
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns,
319
{
344
+ target_ulong pc, void *host_pc)
320
CPUMBState *env = cs->env_ptr;
345
{
321
MicroBlazeCPU *cpu = mb_env_get_cpu(env);
346
DisasContext dc;
322
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
347
- translator_loop(&mb_tr_ops, &dc.base, cpu, tb, max_insns);
323
uint32_t page_start, org_flags;
348
+ translator_loop(cpu, tb, max_insns, pc, host_pc, &mb_tr_ops, &dc.base);
324
uint32_t npc;
349
}
325
int num_insns;
350
326
- int max_insns;
351
void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)
327
352
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
328
pc_start = tb->pc;
353
index XXXXXXX..XXXXXXX 100644
329
dc->cpu = cpu;
354
--- a/target/mips/tcg/translate.c
330
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
355
+++ b/target/mips/tcg/translate.c
331
332
page_start = pc_start & TARGET_PAGE_MASK;
333
num_insns = 0;
334
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
335
- if (max_insns == 0) {
336
- max_insns = CF_COUNT_MASK;
337
- }
338
- if (max_insns > TCG_MAX_INSNS) {
339
- max_insns = TCG_MAX_INSNS;
340
- }
341
342
gen_tb_start(tb);
343
do
344
diff --git a/target/mips/translate.c b/target/mips/translate.c
345
index XXXXXXX..XXXXXXX 100644
346
--- a/target/mips/translate.c
347
+++ b/target/mips/translate.c
348
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps mips_tr_ops = {
356
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps mips_tr_ops = {
349
.disas_log = mips_tr_disas_log,
357
.disas_log = mips_tr_disas_log,
350
};
358
};
351
359
352
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
360
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
353
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
361
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
354
{
362
+ target_ulong pc, void *host_pc)
355
DisasContext ctx;
363
{
356
364
DisasContext ctx;
357
- translator_loop(&mips_tr_ops, &ctx.base, cs, tb);
365
358
+ translator_loop(&mips_tr_ops, &ctx.base, cs, tb, max_insns);
366
- translator_loop(&mips_tr_ops, &ctx.base, cs, tb, max_insns);
359
}
367
+ translator_loop(cs, tb, max_insns, pc, host_pc, &mips_tr_ops, &ctx.base);
360
368
}
361
static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags)
369
362
diff --git a/target/moxie/translate.c b/target/moxie/translate.c
370
void mips_tcg_init(void)
363
index XXXXXXX..XXXXXXX 100644
364
--- a/target/moxie/translate.c
365
+++ b/target/moxie/translate.c
366
@@ -XXX,XX +XXX,XX @@ static int decode_opc(MoxieCPU *cpu, DisasContext *ctx)
367
}
368
369
/* generate intermediate code for basic block 'tb'. */
370
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
371
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
372
{
373
CPUMoxieState *env = cs->env_ptr;
374
MoxieCPU *cpu = moxie_env_get_cpu(env);
375
DisasContext ctx;
376
target_ulong pc_start;
377
- int num_insns, max_insns;
378
+ int num_insns;
379
380
pc_start = tb->pc;
381
ctx.pc = pc_start;
382
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
383
ctx.singlestep_enabled = 0;
384
ctx.bstate = BS_NONE;
385
num_insns = 0;
386
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
387
- if (max_insns == 0) {
388
- max_insns = CF_COUNT_MASK;
389
- }
390
- if (max_insns > TCG_MAX_INSNS) {
391
- max_insns = TCG_MAX_INSNS;
392
- }
393
394
gen_tb_start(tb);
395
do {
396
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
371
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
397
index XXXXXXX..XXXXXXX 100644
372
index XXXXXXX..XXXXXXX 100644
398
--- a/target/nios2/translate.c
373
--- a/target/nios2/translate.c
399
+++ b/target/nios2/translate.c
374
+++ b/target/nios2/translate.c
400
@@ -XXX,XX +XXX,XX @@ static void gen_exception(DisasContext *dc, uint32_t excp)
375
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps nios2_tr_ops = {
401
}
376
.disas_log = nios2_tr_disas_log,
402
377
};
403
/* generate intermediate code for basic block 'tb'. */
378
404
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
379
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
405
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
380
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
406
{
381
+ target_ulong pc, void *host_pc)
407
CPUNios2State *env = cs->env_ptr;
382
{
408
DisasContext dc1, *dc = &dc1;
383
DisasContext dc;
409
int num_insns;
384
- translator_loop(&nios2_tr_ops, &dc.base, cs, tb, max_insns);
410
- int max_insns;
385
+ translator_loop(cs, tb, max_insns, pc, host_pc, &nios2_tr_ops, &dc.base);
411
386
}
412
/* Initialize DC */
387
413
dc->cpu_env = cpu_env;
388
void nios2_cpu_dump_state(CPUState *cs, FILE *f, int flags)
414
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
415
416
/* Set up instruction counts */
417
num_insns = 0;
418
- if (cs->singlestep_enabled || singlestep) {
419
- max_insns = 1;
420
- } else {
421
+ if (max_insns > 1) {
422
int page_insns = (TARGET_PAGE_SIZE - (tb->pc & TARGET_PAGE_MASK)) / 4;
423
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
424
- if (max_insns == 0) {
425
- max_insns = CF_COUNT_MASK;
426
- }
427
if (max_insns > page_insns) {
428
max_insns = page_insns;
429
}
430
- if (max_insns > TCG_MAX_INSNS) {
431
- max_insns = TCG_MAX_INSNS;
432
- }
433
}
434
435
gen_tb_start(tb);
436
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
389
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
437
index XXXXXXX..XXXXXXX 100644
390
index XXXXXXX..XXXXXXX 100644
438
--- a/target/openrisc/translate.c
391
--- a/target/openrisc/translate.c
439
+++ b/target/openrisc/translate.c
392
+++ b/target/openrisc/translate.c
440
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps openrisc_tr_ops = {
393
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps openrisc_tr_ops = {
441
.disas_log = openrisc_tr_disas_log,
394
.disas_log = openrisc_tr_disas_log,
442
};
395
};
443
396
444
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
397
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
445
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
398
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
446
{
399
+ target_ulong pc, void *host_pc)
447
DisasContext ctx;
400
{
448
401
DisasContext ctx;
449
- translator_loop(&openrisc_tr_ops, &ctx.base, cs, tb);
402
450
+ translator_loop(&openrisc_tr_ops, &ctx.base, cs, tb, max_insns);
403
- translator_loop(&openrisc_tr_ops, &ctx.base, cs, tb, max_insns);
451
}
404
+ translator_loop(cs, tb, max_insns, pc, host_pc,
405
+ &openrisc_tr_ops, &ctx.base);
406
}
452
407
453
void openrisc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
408
void openrisc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
454
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
409
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
455
index XXXXXXX..XXXXXXX 100644
410
index XXXXXXX..XXXXXXX 100644
456
--- a/target/ppc/translate.c
411
--- a/target/ppc/translate.c
457
+++ b/target/ppc/translate.c
412
+++ b/target/ppc/translate.c
458
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps ppc_tr_ops = {
413
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps ppc_tr_ops = {
459
.disas_log = ppc_tr_disas_log,
414
.disas_log = ppc_tr_disas_log,
460
};
415
};
461
416
462
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
417
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
463
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
418
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
464
{
419
+ target_ulong pc, void *host_pc)
465
DisasContext ctx;
420
{
466
421
DisasContext ctx;
467
- translator_loop(&ppc_tr_ops, &ctx.base, cs, tb);
422
468
+ translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns);
423
- translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns);
469
}
424
+ translator_loop(cs, tb, max_insns, pc, host_pc, &ppc_tr_ops, &ctx.base);
425
}
470
426
471
void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
427
void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
472
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
428
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
473
index XXXXXXX..XXXXXXX 100644
429
index XXXXXXX..XXXXXXX 100644
474
--- a/target/riscv/translate.c
430
--- a/target/riscv/translate.c
475
+++ b/target/riscv/translate.c
431
+++ b/target/riscv/translate.c
476
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps riscv_tr_ops = {
432
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps riscv_tr_ops = {
477
.disas_log = riscv_tr_disas_log,
433
.disas_log = riscv_tr_disas_log,
478
};
434
};
479
435
480
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
436
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
481
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
437
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
482
{
438
+ target_ulong pc, void *host_pc)
483
DisasContext ctx;
439
{
484
440
DisasContext ctx;
485
- translator_loop(&riscv_tr_ops, &ctx.base, cs, tb);
441
486
+ translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns);
442
- translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns);
487
}
443
+ translator_loop(cs, tb, max_insns, pc, host_pc, &riscv_tr_ops, &ctx.base);
444
}
488
445
489
void riscv_translate_init(void)
446
void riscv_translate_init(void)
490
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
447
diff --git a/target/rx/translate.c b/target/rx/translate.c
491
index XXXXXXX..XXXXXXX 100644
448
index XXXXXXX..XXXXXXX 100644
492
--- a/target/s390x/translate.c
449
--- a/target/rx/translate.c
493
+++ b/target/s390x/translate.c
450
+++ b/target/rx/translate.c
451
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps rx_tr_ops = {
452
.disas_log = rx_tr_disas_log,
453
};
454
455
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
456
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
457
+ target_ulong pc, void *host_pc)
458
{
459
DisasContext dc;
460
461
- translator_loop(&rx_tr_ops, &dc.base, cs, tb, max_insns);
462
+ translator_loop(cs, tb, max_insns, pc, host_pc, &rx_tr_ops, &dc.base);
463
}
464
465
void restore_state_to_opc(CPURXState *env, TranslationBlock *tb,
466
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
467
index XXXXXXX..XXXXXXX 100644
468
--- a/target/s390x/tcg/translate.c
469
+++ b/target/s390x/tcg/translate.c
494
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps s390x_tr_ops = {
470
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps s390x_tr_ops = {
495
.disas_log = s390x_tr_disas_log,
471
.disas_log = s390x_tr_disas_log,
496
};
472
};
497
473
498
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
474
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
499
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
475
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
500
{
476
+ target_ulong pc, void *host_pc)
501
DisasContext dc;
477
{
502
478
DisasContext dc;
503
- translator_loop(&s390x_tr_ops, &dc.base, cs, tb);
479
504
+ translator_loop(&s390x_tr_ops, &dc.base, cs, tb, max_insns);
480
- translator_loop(&s390x_tr_ops, &dc.base, cs, tb, max_insns);
505
}
481
+ translator_loop(cs, tb, max_insns, pc, host_pc, &s390x_tr_ops, &dc.base);
482
}
506
483
507
void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb,
484
void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb,
508
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
485
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
509
index XXXXXXX..XXXXXXX 100644
486
index XXXXXXX..XXXXXXX 100644
510
--- a/target/sh4/translate.c
487
--- a/target/sh4/translate.c
511
+++ b/target/sh4/translate.c
488
+++ b/target/sh4/translate.c
512
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps sh4_tr_ops = {
489
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps sh4_tr_ops = {
513
.disas_log = sh4_tr_disas_log,
490
.disas_log = sh4_tr_disas_log,
514
};
491
};
515
492
516
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
493
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
517
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
494
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
518
{
495
+ target_ulong pc, void *host_pc)
519
DisasContext ctx;
496
{
520
497
DisasContext ctx;
521
- translator_loop(&sh4_tr_ops, &ctx.base, cs, tb);
498
522
+ translator_loop(&sh4_tr_ops, &ctx.base, cs, tb, max_insns);
499
- translator_loop(&sh4_tr_ops, &ctx.base, cs, tb, max_insns);
523
}
500
+ translator_loop(cs, tb, max_insns, pc, host_pc, &sh4_tr_ops, &ctx.base);
501
}
524
502
525
void restore_state_to_opc(CPUSH4State *env, TranslationBlock *tb,
503
void restore_state_to_opc(CPUSH4State *env, TranslationBlock *tb,
526
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
504
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
527
index XXXXXXX..XXXXXXX 100644
505
index XXXXXXX..XXXXXXX 100644
528
--- a/target/sparc/translate.c
506
--- a/target/sparc/translate.c
529
+++ b/target/sparc/translate.c
507
+++ b/target/sparc/translate.c
530
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps sparc_tr_ops = {
508
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps sparc_tr_ops = {
531
.disas_log = sparc_tr_disas_log,
509
.disas_log = sparc_tr_disas_log,
532
};
510
};
533
511
534
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
512
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
535
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
513
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
514
+ target_ulong pc, void *host_pc)
536
{
515
{
537
DisasContext dc = {};
516
DisasContext dc = {};
538
517
539
- translator_loop(&sparc_tr_ops, &dc.base, cs, tb);
518
- translator_loop(&sparc_tr_ops, &dc.base, cs, tb, max_insns);
540
+ translator_loop(&sparc_tr_ops, &dc.base, cs, tb, max_insns);
519
+ translator_loop(cs, tb, max_insns, pc, host_pc, &sparc_tr_ops, &dc.base);
541
}
520
}
542
521
543
void sparc_tcg_init(void)
522
void sparc_tcg_init(void)
544
diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c
545
index XXXXXXX..XXXXXXX 100644
546
--- a/target/tilegx/translate.c
547
+++ b/target/tilegx/translate.c
548
@@ -XXX,XX +XXX,XX @@ static void translate_one_bundle(DisasContext *dc, uint64_t bundle)
549
}
550
}
551
552
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
553
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
554
{
555
CPUTLGState *env = cs->env_ptr;
556
DisasContext ctx;
557
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
558
uint64_t pc_start = tb->pc;
559
uint64_t page_start = pc_start & TARGET_PAGE_MASK;
560
int num_insns = 0;
561
- int max_insns = tb_cflags(tb) & CF_COUNT_MASK;
562
563
dc->pc = pc_start;
564
dc->mmuidx = 0;
565
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
566
qemu_log_lock();
567
qemu_log("IN: %s\n", lookup_symbol(pc_start));
568
}
569
- if (!max_insns) {
570
- max_insns = CF_COUNT_MASK;
571
- }
572
- if (cs->singlestep_enabled || singlestep) {
573
- max_insns = 1;
574
- }
575
- if (max_insns > TCG_MAX_INSNS) {
576
- max_insns = TCG_MAX_INSNS;
577
- }
578
gen_tb_start(tb);
579
580
while (1) {
581
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
523
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
582
index XXXXXXX..XXXXXXX 100644
524
index XXXXXXX..XXXXXXX 100644
583
--- a/target/tricore/translate.c
525
--- a/target/tricore/translate.c
584
+++ b/target/tricore/translate.c
526
+++ b/target/tricore/translate.c
585
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch)
527
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps tricore_tr_ops = {
586
}
528
};
587
}
529
588
530
589
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
531
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
590
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
532
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns,
591
{
533
+ target_ulong pc, void *host_pc)
592
CPUTriCoreState *env = cs->env_ptr;
534
{
593
DisasContext ctx;
535
DisasContext ctx;
594
target_ulong pc_start;
536
- translator_loop(&tricore_tr_ops, &ctx.base, cs, tb, max_insns);
595
- int num_insns, max_insns;
537
+ translator_loop(cs, tb, max_insns, pc, host_pc,
596
-
538
+ &tricore_tr_ops, &ctx.base);
597
- num_insns = 0;
539
}
598
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
540
599
- if (max_insns == 0) {
541
void
600
- max_insns = CF_COUNT_MASK;
601
- }
602
- if (singlestep) {
603
- max_insns = 1;
604
- }
605
- if (max_insns > TCG_MAX_INSNS) {
606
- max_insns = TCG_MAX_INSNS;
607
- }
608
+ int num_insns = 0;
609
610
pc_start = tb->pc;
611
ctx.pc = pc_start;
612
diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c
613
index XXXXXXX..XXXXXXX 100644
614
--- a/target/unicore32/translate.c
615
+++ b/target/unicore32/translate.c
616
@@ -XXX,XX +XXX,XX @@ static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
617
}
618
619
/* generate intermediate code for basic block 'tb'. */
620
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
621
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
622
{
623
CPUUniCore32State *env = cs->env_ptr;
624
DisasContext dc1, *dc = &dc1;
625
target_ulong pc_start;
626
uint32_t page_start;
627
int num_insns;
628
- int max_insns;
629
630
/* generate intermediate code */
631
num_temps = 0;
632
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
633
cpu_F1d = tcg_temp_new_i64();
634
page_start = pc_start & TARGET_PAGE_MASK;
635
num_insns = 0;
636
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
637
- if (max_insns == 0) {
638
- max_insns = CF_COUNT_MASK;
639
- }
640
- if (max_insns > TCG_MAX_INSNS) {
641
- max_insns = TCG_MAX_INSNS;
642
- }
643
644
#ifndef CONFIG_USER_ONLY
645
if ((env->uncached_asr & ASR_M) == ASR_MODE_USER) {
646
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
542
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
647
index XXXXXXX..XXXXXXX 100644
543
index XXXXXXX..XXXXXXX 100644
648
--- a/target/xtensa/translate.c
544
--- a/target/xtensa/translate.c
649
+++ b/target/xtensa/translate.c
545
+++ b/target/xtensa/translate.c
650
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps xtensa_translator_ops = {
546
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps xtensa_translator_ops = {
651
.disas_log = xtensa_tr_disas_log,
547
.disas_log = xtensa_tr_disas_log,
652
};
548
};
653
549
654
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
550
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
655
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
551
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns,
552
+ target_ulong pc, void *host_pc)
656
{
553
{
657
DisasContext dc = {};
554
DisasContext dc = {};
658
- translator_loop(&xtensa_translator_ops, &dc.base, cpu, tb);
555
- translator_loop(&xtensa_translator_ops, &dc.base, cpu, tb, max_insns);
659
+ translator_loop(&xtensa_translator_ops, &dc.base, cpu, tb, max_insns);
556
+ translator_loop(cpu, tb, max_insns, pc, host_pc,
660
}
557
+ &xtensa_translator_ops, &dc.base);
558
}
661
559
662
void xtensa_cpu_dump_state(CPUState *cs, FILE *f, int flags)
560
void xtensa_cpu_dump_state(CPUState *cs, FILE *f, int flags)
663
--
561
--
664
2.17.1
562
2.34.1
665
666
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/15] tcg: Restart after TB code generation overflow
[PULL 16/20] accel/tcg: Add fast path for translator_ld*
1
If a TB generates too much code, try again with fewer insns.
1
Cache the translation from guest to host address, so we may
2
use direct loads when we hit on the primary translation page.
2
3
3
Fixes: https://bugs.launchpad.net/bugs/1824853
4
Look up the second translation page only once, during translation.
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
This obviates another lookup of the second page within tb_gen_code
6
after translation.
7
8
Fixes a bug in that plugin_insn_append should be passed the bytes
9
in the original memory order, not bswapped by pieces.
10
11
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
12
Tested-by: Ilya Leoshkevich <iii@linux.ibm.com>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
14
---
7
accel/tcg/translate-all.c | 38 ++++++++++++++++++++++++++++++++------
15
include/exec/translator.h | 63 +++++++++++--------
8
tcg/tcg.c | 4 ++++
16
accel/tcg/translate-all.c | 23 +++----
9
2 files changed, 36 insertions(+), 6 deletions(-)
17
accel/tcg/translator.c | 126 +++++++++++++++++++++++++++++---------
18
3 files changed, 141 insertions(+), 71 deletions(-)
10
19
20
diff --git a/include/exec/translator.h b/include/exec/translator.h
21
index XXXXXXX..XXXXXXX 100644
22
--- a/include/exec/translator.h
23
+++ b/include/exec/translator.h
24
@@ -XXX,XX +XXX,XX @@ typedef enum DisasJumpType {
25
* Architecture-agnostic disassembly context.
26
*/
27
typedef struct DisasContextBase {
28
- const TranslationBlock *tb;
29
+ TranslationBlock *tb;
30
target_ulong pc_first;
31
target_ulong pc_next;
32
DisasJumpType is_jmp;
33
int num_insns;
34
int max_insns;
35
bool singlestep_enabled;
36
-#ifdef CONFIG_USER_ONLY
37
- /*
38
- * Guest address of the last byte of the last protected page.
39
- *
40
- * Pages containing the translated instructions are made non-writable in
41
- * order to achieve consistency in case another thread is modifying the
42
- * code while translate_insn() fetches the instruction bytes piecemeal.
43
- * Such writer threads are blocked on mmap_lock() in page_unprotect().
44
- */
45
- target_ulong page_protect_end;
46
-#endif
47
+ void *host_addr[2];
48
} DisasContextBase;
49
50
/**
51
@@ -XXX,XX +XXX,XX @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest);
52
* the relevant information at translation time.
53
*/
54
55
-#define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn) \
56
- type fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \
57
- abi_ptr pc, bool do_swap); \
58
- static inline type fullname(CPUArchState *env, \
59
- DisasContextBase *dcbase, abi_ptr pc) \
60
- { \
61
- return fullname ## _swap(env, dcbase, pc, false); \
62
+uint8_t translator_ldub(CPUArchState *env, DisasContextBase *db, abi_ptr pc);
63
+uint16_t translator_lduw(CPUArchState *env, DisasContextBase *db, abi_ptr pc);
64
+uint32_t translator_ldl(CPUArchState *env, DisasContextBase *db, abi_ptr pc);
65
+uint64_t translator_ldq(CPUArchState *env, DisasContextBase *db, abi_ptr pc);
66
+
67
+static inline uint16_t
68
+translator_lduw_swap(CPUArchState *env, DisasContextBase *db,
69
+ abi_ptr pc, bool do_swap)
70
+{
71
+ uint16_t ret = translator_lduw(env, db, pc);
72
+ if (do_swap) {
73
+ ret = bswap16(ret);
74
}
75
+ return ret;
76
+}
77
78
-#define FOR_EACH_TRANSLATOR_LD(F) \
79
- F(translator_ldub, uint8_t, cpu_ldub_code, /* no swap */) \
80
- F(translator_lduw, uint16_t, cpu_lduw_code, bswap16) \
81
- F(translator_ldl, uint32_t, cpu_ldl_code, bswap32) \
82
- F(translator_ldq, uint64_t, cpu_ldq_code, bswap64)
83
+static inline uint32_t
84
+translator_ldl_swap(CPUArchState *env, DisasContextBase *db,
85
+ abi_ptr pc, bool do_swap)
86
+{
87
+ uint32_t ret = translator_ldl(env, db, pc);
88
+ if (do_swap) {
89
+ ret = bswap32(ret);
90
+ }
91
+ return ret;
92
+}
93
94
-FOR_EACH_TRANSLATOR_LD(GEN_TRANSLATOR_LD)
95
-
96
-#undef GEN_TRANSLATOR_LD
97
+static inline uint64_t
98
+translator_ldq_swap(CPUArchState *env, DisasContextBase *db,
99
+ abi_ptr pc, bool do_swap)
100
+{
101
+ uint64_t ret = translator_ldq_swap(env, db, pc, false);
102
+ if (do_swap) {
103
+ ret = bswap64(ret);
104
+ }
105
+ return ret;
106
+}
107
108
/*
109
* Return whether addr is on the same page as where disassembly started.
11
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
110
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
12
index XXXXXXX..XXXXXXX 100644
111
index XXXXXXX..XXXXXXX 100644
13
--- a/accel/tcg/translate-all.c
112
--- a/accel/tcg/translate-all.c
14
+++ b/accel/tcg/translate-all.c
113
+++ b/accel/tcg/translate-all.c
15
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
114
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
115
{
116
CPUArchState *env = cpu->env_ptr;
117
TranslationBlock *tb, *existing_tb;
118
- tb_page_addr_t phys_pc, phys_page2;
119
- target_ulong virt_page2;
120
+ tb_page_addr_t phys_pc;
121
tcg_insn_unit *gen_code_buf;
122
int gen_code_size, search_size, max_insns;
123
#ifdef CONFIG_PROFILER
124
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
125
tb->flags = flags;
16
tb->cflags = cflags;
126
tb->cflags = cflags;
17
tb->trace_vcpu_dstate = *cpu->trace_dstate;
127
tb->trace_vcpu_dstate = *cpu->trace_dstate;
128
+ tb->page_addr[0] = phys_pc;
129
+ tb->page_addr[1] = -1;
18
tcg_ctx->tb_cflags = cflags;
130
tcg_ctx->tb_cflags = cflags;
19
+ tb_overflow:
131
tb_overflow:
20
132
21
#ifdef CONFIG_PROFILER
22
/* includes aborted translations because of exceptions */
23
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
133
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
24
ti = profile_getclock();
134
}
135
136
/*
137
- * If the TB is not associated with a physical RAM page then
138
- * it must be a temporary one-insn TB, and we have nothing to do
139
- * except fill in the page_addr[] fields. Return early before
140
- * attempting to link to other TBs or add to the lookup table.
141
+ * If the TB is not associated with a physical RAM page then it must be
142
+ * a temporary one-insn TB, and we have nothing left to do. Return early
143
+ * before attempting to link to other TBs or add to the lookup table.
144
*/
145
- if (phys_pc == -1) {
146
- tb->page_addr[0] = tb->page_addr[1] = -1;
147
+ if (tb->page_addr[0] == -1) {
148
return tb;
149
}
150
151
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
152
*/
153
tcg_tb_insert(tb);
154
155
- /* check next page if needed */
156
- virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
157
- phys_page2 = -1;
158
- if ((pc & TARGET_PAGE_MASK) != virt_page2) {
159
- phys_page2 = get_page_addr_code(env, virt_page2);
160
- }
161
/*
162
* No explicit memory barrier is required -- tb_link_page() makes the
163
* TB visible in a consistent state.
164
*/
165
- existing_tb = tb_link_page(tb, phys_pc, phys_page2);
166
+ existing_tb = tb_link_page(tb, tb->page_addr[0], tb->page_addr[1]);
167
/* if the TB already exists, discard what we just translated */
168
if (unlikely(existing_tb != tb)) {
169
uintptr_t orig_aligned = (uintptr_t)gen_code_buf;
170
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
171
index XXXXXXX..XXXXXXX 100644
172
--- a/accel/tcg/translator.c
173
+++ b/accel/tcg/translator.c
174
@@ -XXX,XX +XXX,XX @@ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest)
175
return ((db->pc_first ^ dest) & TARGET_PAGE_MASK) == 0;
176
}
177
178
-static inline void translator_page_protect(DisasContextBase *dcbase,
179
- target_ulong pc)
180
-{
181
-#ifdef CONFIG_USER_ONLY
182
- dcbase->page_protect_end = pc | ~TARGET_PAGE_MASK;
183
- page_protect(pc);
184
-#endif
185
-}
186
-
187
void translator_loop(CPUState *cpu, TranslationBlock *tb, int max_insns,
188
target_ulong pc, void *host_pc,
189
const TranslatorOps *ops, DisasContextBase *db)
190
@@ -XXX,XX +XXX,XX @@ void translator_loop(CPUState *cpu, TranslationBlock *tb, int max_insns,
191
db->num_insns = 0;
192
db->max_insns = max_insns;
193
db->singlestep_enabled = cflags & CF_SINGLE_STEP;
194
- translator_page_protect(db, db->pc_next);
195
+ db->host_addr[0] = host_pc;
196
+ db->host_addr[1] = NULL;
197
+
198
+#ifdef CONFIG_USER_ONLY
199
+ page_protect(pc);
200
+#endif
201
202
ops->init_disas_context(db, cpu);
203
tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */
204
@@ -XXX,XX +XXX,XX @@ void translator_loop(CPUState *cpu, TranslationBlock *tb, int max_insns,
25
#endif
205
#endif
26
206
}
27
- /* ??? Overflow could be handled better here. In particular, we
207
28
- don't need to re-do gen_intermediate_code, nor should we re-do
208
-static inline void translator_maybe_page_protect(DisasContextBase *dcbase,
29
- the tcg optimization currently hidden inside tcg_gen_code. All
209
- target_ulong pc, size_t len)
30
- that should be required is to flush the TBs, allocate a new TB,
210
+static void *translator_access(CPUArchState *env, DisasContextBase *db,
31
- re-initialize it per above, and re-do the actual code generation. */
211
+ target_ulong pc, size_t len)
32
gen_code_size = tcg_gen_code(tcg_ctx, tb);
212
{
33
if (unlikely(gen_code_size < 0)) {
213
-#ifdef CONFIG_USER_ONLY
34
- goto buffer_overflow;
214
- target_ulong end = pc + len - 1;
35
+ switch (gen_code_size) {
215
+ void *host;
36
+ case -1:
216
+ target_ulong base, end;
37
+ /*
217
+ TranslationBlock *tb;
38
+ * Overflow of code_gen_buffer, or the current slice of it.
218
39
+ *
219
- if (end > dcbase->page_protect_end) {
40
+ * TODO: We don't need to re-do gen_intermediate_code, nor
220
- translator_page_protect(dcbase, end);
41
+ * should we re-do the tcg optimization currently hidden
221
+ tb = db->tb;
42
+ * inside tcg_gen_code. All that should be required is to
222
+
43
+ * flush the TBs, allocate a new TB, re-initialize it per
223
+ /* Use slow path if first page is MMIO. */
44
+ * above, and re-do the actual code generation.
224
+ if (unlikely(tb->page_addr[0] == -1)) {
45
+ */
225
+ return NULL;
46
+ goto buffer_overflow;
226
}
47
+
227
+
48
+ case -2:
228
+ end = pc + len - 1;
49
+ /*
229
+ if (likely(is_same_page(db, end))) {
50
+ * The code generated for the TranslationBlock is too large.
230
+ host = db->host_addr[0];
51
+ * The maximum size allowed by the unwind info is 64k.
231
+ base = db->pc_first;
52
+ * There may be stricter constraints from relocations
232
+ } else {
53
+ * in the tcg backend.
233
+ host = db->host_addr[1];
54
+ *
234
+ base = TARGET_PAGE_ALIGN(db->pc_first);
55
+ * Try again with half as many insns as we attempted this time.
235
+ if (host == NULL) {
56
+ * If a single insn overflows, there's a bug somewhere...
236
+ tb->page_addr[1] =
57
+ */
237
+ get_page_addr_code_hostp(env, base, &db->host_addr[1]);
58
+ max_insns = tb->icount;
238
+#ifdef CONFIG_USER_ONLY
59
+ assert(max_insns > 1);
239
+ page_protect(end);
60
+ max_insns /= 2;
240
#endif
61
+ goto tb_overflow;
241
+ /* We cannot handle MMIO as second page. */
62
+
242
+ assert(tb->page_addr[1] != -1);
63
+ default:
243
+ host = db->host_addr[1];
64
+ g_assert_not_reached();
65
+ }
244
+ }
66
}
245
+
67
search_size = encode_search(tb, (void *)gen_code_buf + gen_code_size);
246
+ /* Use slow path when crossing pages. */
68
if (unlikely(search_size < 0)) {
247
+ if (is_same_page(db, pc)) {
69
diff --git a/tcg/tcg.c b/tcg/tcg.c
248
+ return NULL;
70
index XXXXXXX..XXXXXXX 100644
71
--- a/tcg/tcg.c
72
+++ b/tcg/tcg.c
73
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
74
if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) {
75
return -1;
76
}
77
+ /* Test for TB overflow, as seen by gen_insn_end_off. */
78
+ if (unlikely(tcg_current_code_size(s) > UINT16_MAX)) {
79
+ return -2;
80
+ }
249
+ }
81
}
250
+ }
82
tcg_debug_assert(num_insns >= 0);
251
+
83
s->gen_insn_end_off[num_insns] = tcg_current_code_size(s);
252
+ tcg_debug_assert(pc >= base);
253
+ return host + (pc - base);
254
}
255
256
-#define GEN_TRANSLATOR_LD(fullname, type, load_fn, swap_fn) \
257
- type fullname ## _swap(CPUArchState *env, DisasContextBase *dcbase, \
258
- abi_ptr pc, bool do_swap) \
259
- { \
260
- translator_maybe_page_protect(dcbase, pc, sizeof(type)); \
261
- type ret = load_fn(env, pc); \
262
- if (do_swap) { \
263
- ret = swap_fn(ret); \
264
- } \
265
- plugin_insn_append(pc, &ret, sizeof(ret)); \
266
- return ret; \
267
+uint8_t translator_ldub(CPUArchState *env, DisasContextBase *db, abi_ptr pc)
268
+{
269
+ uint8_t ret;
270
+ void *p = translator_access(env, db, pc, sizeof(ret));
271
+
272
+ if (p) {
273
+ plugin_insn_append(pc, p, sizeof(ret));
274
+ return ldub_p(p);
275
}
276
+ ret = cpu_ldub_code(env, pc);
277
+ plugin_insn_append(pc, &ret, sizeof(ret));
278
+ return ret;
279
+}
280
281
-FOR_EACH_TRANSLATOR_LD(GEN_TRANSLATOR_LD)
282
+uint16_t translator_lduw(CPUArchState *env, DisasContextBase *db, abi_ptr pc)
283
+{
284
+ uint16_t ret, plug;
285
+ void *p = translator_access(env, db, pc, sizeof(ret));
286
287
-#undef GEN_TRANSLATOR_LD
288
+ if (p) {
289
+ plugin_insn_append(pc, p, sizeof(ret));
290
+ return lduw_p(p);
291
+ }
292
+ ret = cpu_lduw_code(env, pc);
293
+ plug = tswap16(ret);
294
+ plugin_insn_append(pc, &plug, sizeof(ret));
295
+ return ret;
296
+}
297
+
298
+uint32_t translator_ldl(CPUArchState *env, DisasContextBase *db, abi_ptr pc)
299
+{
300
+ uint32_t ret, plug;
301
+ void *p = translator_access(env, db, pc, sizeof(ret));
302
+
303
+ if (p) {
304
+ plugin_insn_append(pc, p, sizeof(ret));
305
+ return ldl_p(p);
306
+ }
307
+ ret = cpu_ldl_code(env, pc);
308
+ plug = tswap32(ret);
309
+ plugin_insn_append(pc, &plug, sizeof(ret));
310
+ return ret;
311
+}
312
+
313
+uint64_t translator_ldq(CPUArchState *env, DisasContextBase *db, abi_ptr pc)
314
+{
315
+ uint64_t ret, plug;
316
+ void *p = translator_access(env, db, pc, sizeof(ret));
317
+
318
+ if (p) {
319
+ plugin_insn_append(pc, p, sizeof(ret));
320
+ return ldq_p(p);
321
+ }
322
+ ret = cpu_ldq_code(env, pc);
323
+ plug = tswap64(ret);
324
+ plugin_insn_append(pc, &plug, sizeof(ret));
325
+ return ret;
326
+}
84
--
327
--
85
2.17.1
328
2.34.1
86
87
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/15] tcg/i386: Support INDEX_op_extract2_{i32, i64}
[PULL 17/20] target/s390x: Make translator stop before the end of a page
1
From: Ilya Leoshkevich <iii@linux.ibm.com>
2
3
Right now translator stops right *after* the end of a page, which
4
breaks reporting of fault locations when the last instruction of a
5
multi-insn translation block crosses a page boundary.
6
7
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-Id: <20220817150506.592862-3-iii@linux.ibm.com>
1
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2
---
11
---
3
tcg/i386/tcg-target.h | 4 ++--
12
target/s390x/tcg/translate.c | 15 +++-
4
tcg/i386/tcg-target.inc.c | 11 +++++++++++
13
tests/tcg/s390x/noexec.c | 106 +++++++++++++++++++++++
5
2 files changed, 13 insertions(+), 2 deletions(-)
14
tests/tcg/multiarch/noexec.c.inc | 139 +++++++++++++++++++++++++++++++
15
tests/tcg/s390x/Makefile.target | 1 +
16
4 files changed, 257 insertions(+), 4 deletions(-)
17
create mode 100644 tests/tcg/s390x/noexec.c
18
create mode 100644 tests/tcg/multiarch/noexec.c.inc
6
19
7
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
20
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
8
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
9
--- a/tcg/i386/tcg-target.h
22
--- a/target/s390x/tcg/translate.c
10
+++ b/tcg/i386/tcg-target.h
23
+++ b/target/s390x/tcg/translate.c
11
@@ -XXX,XX +XXX,XX @@ extern bool have_avx2;
24
@@ -XXX,XX +XXX,XX @@ static void s390x_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
12
#define TCG_TARGET_HAS_deposit_i32 1
25
dc->insn_start = tcg_last_op();
13
#define TCG_TARGET_HAS_extract_i32 1
26
}
14
#define TCG_TARGET_HAS_sextract_i32 1
27
15
-#define TCG_TARGET_HAS_extract2_i32 0
28
+static target_ulong get_next_pc(CPUS390XState *env, DisasContext *s,
16
+#define TCG_TARGET_HAS_extract2_i32 1
29
+ uint64_t pc)
17
#define TCG_TARGET_HAS_movcond_i32 1
30
+{
18
#define TCG_TARGET_HAS_add2_i32 1
31
+ uint64_t insn = ld_code2(env, s, pc);
19
#define TCG_TARGET_HAS_sub2_i32 1
32
+
20
@@ -XXX,XX +XXX,XX @@ extern bool have_avx2;
33
+ return pc + get_ilen((insn >> 8) & 0xff);
21
#define TCG_TARGET_HAS_deposit_i64 1
34
+}
22
#define TCG_TARGET_HAS_extract_i64 1
35
+
23
#define TCG_TARGET_HAS_sextract_i64 0
36
static void s390x_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
24
-#define TCG_TARGET_HAS_extract2_i64 0
37
{
25
+#define TCG_TARGET_HAS_extract2_i64 1
38
CPUS390XState *env = cs->env_ptr;
26
#define TCG_TARGET_HAS_movcond_i64 1
39
@@ -XXX,XX +XXX,XX @@ static void s390x_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
27
#define TCG_TARGET_HAS_add2_i64 1
40
28
#define TCG_TARGET_HAS_sub2_i64 1
41
dc->base.is_jmp = translate_one(env, dc);
29
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
42
if (dc->base.is_jmp == DISAS_NEXT) {
43
- uint64_t page_start;
44
-
45
- page_start = dc->base.pc_first & TARGET_PAGE_MASK;
46
- if (dc->base.pc_next - page_start >= TARGET_PAGE_SIZE || dc->ex_value) {
47
+ if (!is_same_page(dcbase, dc->base.pc_next) ||
48
+ !is_same_page(dcbase, get_next_pc(env, dc, dc->base.pc_next)) ||
49
+ dc->ex_value) {
50
dc->base.is_jmp = DISAS_TOO_MANY;
51
}
52
}
53
diff --git a/tests/tcg/s390x/noexec.c b/tests/tcg/s390x/noexec.c
54
new file mode 100644
55
index XXXXXXX..XXXXXXX
56
--- /dev/null
57
+++ b/tests/tcg/s390x/noexec.c
58
@@ -XXX,XX +XXX,XX @@
59
+#include "../multiarch/noexec.c.inc"
60
+
61
+static void *arch_mcontext_pc(const mcontext_t *ctx)
62
+{
63
+ return (void *)ctx->psw.addr;
64
+}
65
+
66
+static int arch_mcontext_arg(const mcontext_t *ctx)
67
+{
68
+ return ctx->gregs[2];
69
+}
70
+
71
+static void arch_flush(void *p, int len)
72
+{
73
+}
74
+
75
+extern char noexec_1[];
76
+extern char noexec_2[];
77
+extern char noexec_end[];
78
+
79
+asm("noexec_1:\n"
80
+ " lgfi %r2,1\n" /* %r2 is 0 on entry, set 1. */
81
+ "noexec_2:\n"
82
+ " lgfi %r2,2\n" /* %r2 is 0/1; set 2. */
83
+ " br %r14\n" /* return */
84
+ "noexec_end:");
85
+
86
+extern char exrl_1[];
87
+extern char exrl_2[];
88
+extern char exrl_end[];
89
+
90
+asm("exrl_1:\n"
91
+ " exrl %r0, exrl_2\n"
92
+ " br %r14\n"
93
+ "exrl_2:\n"
94
+ " lgfi %r2,2\n"
95
+ "exrl_end:");
96
+
97
+int main(void)
98
+{
99
+ struct noexec_test noexec_tests[] = {
100
+ {
101
+ .name = "fallthrough",
102
+ .test_code = noexec_1,
103
+ .test_len = noexec_end - noexec_1,
104
+ .page_ofs = noexec_1 - noexec_2,
105
+ .entry_ofs = noexec_1 - noexec_2,
106
+ .expected_si_ofs = 0,
107
+ .expected_pc_ofs = 0,
108
+ .expected_arg = 1,
109
+ },
110
+ {
111
+ .name = "jump",
112
+ .test_code = noexec_1,
113
+ .test_len = noexec_end - noexec_1,
114
+ .page_ofs = noexec_1 - noexec_2,
115
+ .entry_ofs = 0,
116
+ .expected_si_ofs = 0,
117
+ .expected_pc_ofs = 0,
118
+ .expected_arg = 0,
119
+ },
120
+ {
121
+ .name = "exrl",
122
+ .test_code = exrl_1,
123
+ .test_len = exrl_end - exrl_1,
124
+ .page_ofs = exrl_1 - exrl_2,
125
+ .entry_ofs = exrl_1 - exrl_2,
126
+ .expected_si_ofs = 0,
127
+ .expected_pc_ofs = exrl_1 - exrl_2,
128
+ .expected_arg = 0,
129
+ },
130
+ {
131
+ .name = "fallthrough [cross]",
132
+ .test_code = noexec_1,
133
+ .test_len = noexec_end - noexec_1,
134
+ .page_ofs = noexec_1 - noexec_2 - 2,
135
+ .entry_ofs = noexec_1 - noexec_2 - 2,
136
+ .expected_si_ofs = 0,
137
+ .expected_pc_ofs = -2,
138
+ .expected_arg = 1,
139
+ },
140
+ {
141
+ .name = "jump [cross]",
142
+ .test_code = noexec_1,
143
+ .test_len = noexec_end - noexec_1,
144
+ .page_ofs = noexec_1 - noexec_2 - 2,
145
+ .entry_ofs = -2,
146
+ .expected_si_ofs = 0,
147
+ .expected_pc_ofs = -2,
148
+ .expected_arg = 0,
149
+ },
150
+ {
151
+ .name = "exrl [cross]",
152
+ .test_code = exrl_1,
153
+ .test_len = exrl_end - exrl_1,
154
+ .page_ofs = exrl_1 - exrl_2 - 2,
155
+ .entry_ofs = exrl_1 - exrl_2 - 2,
156
+ .expected_si_ofs = 0,
157
+ .expected_pc_ofs = exrl_1 - exrl_2 - 2,
158
+ .expected_arg = 0,
159
+ },
160
+ };
161
+
162
+ return test_noexec(noexec_tests,
163
+ sizeof(noexec_tests) / sizeof(noexec_tests[0]));
164
+}
165
diff --git a/tests/tcg/multiarch/noexec.c.inc b/tests/tcg/multiarch/noexec.c.inc
166
new file mode 100644
167
index XXXXXXX..XXXXXXX
168
--- /dev/null
169
+++ b/tests/tcg/multiarch/noexec.c.inc
170
@@ -XXX,XX +XXX,XX @@
171
+/*
172
+ * Common code for arch-specific MMU_INST_FETCH fault testing.
173
+ */
174
+
175
+#define _GNU_SOURCE
176
+
177
+#include <assert.h>
178
+#include <signal.h>
179
+#include <stdio.h>
180
+#include <stdlib.h>
181
+#include <string.h>
182
+#include <errno.h>
183
+#include <unistd.h>
184
+#include <sys/mman.h>
185
+#include <sys/ucontext.h>
186
+
187
+/* Forward declarations. */
188
+
189
+static void *arch_mcontext_pc(const mcontext_t *ctx);
190
+static int arch_mcontext_arg(const mcontext_t *ctx);
191
+static void arch_flush(void *p, int len);
192
+
193
+/* Testing infrastructure. */
194
+
195
+struct noexec_test {
196
+ const char *name;
197
+ const char *test_code;
198
+ int test_len;
199
+ int page_ofs;
200
+ int entry_ofs;
201
+ int expected_si_ofs;
202
+ int expected_pc_ofs;
203
+ int expected_arg;
204
+};
205
+
206
+static void *page_base;
207
+static int page_size;
208
+static const struct noexec_test *current_noexec_test;
209
+
210
+static void handle_err(const char *syscall)
211
+{
212
+ printf("[ FAILED ] %s: %s\n", syscall, strerror(errno));
213
+ exit(EXIT_FAILURE);
214
+}
215
+
216
+static void handle_segv(int sig, siginfo_t *info, void *ucontext)
217
+{
218
+ const struct noexec_test *test = current_noexec_test;
219
+ const mcontext_t *mc = &((ucontext_t *)ucontext)->uc_mcontext;
220
+ void *expected_si;
221
+ void *expected_pc;
222
+ void *pc;
223
+ int arg;
224
+
225
+ if (test == NULL) {
226
+ printf("[ FAILED ] unexpected SEGV\n");
227
+ exit(EXIT_FAILURE);
228
+ }
229
+ current_noexec_test = NULL;
230
+
231
+ expected_si = page_base + test->expected_si_ofs;
232
+ if (info->si_addr != expected_si) {
233
+ printf("[ FAILED ] wrong si_addr (%p != %p)\n",
234
+ info->si_addr, expected_si);
235
+ exit(EXIT_FAILURE);
236
+ }
237
+
238
+ pc = arch_mcontext_pc(mc);
239
+ expected_pc = page_base + test->expected_pc_ofs;
240
+ if (pc != expected_pc) {
241
+ printf("[ FAILED ] wrong pc (%p != %p)\n", pc, expected_pc);
242
+ exit(EXIT_FAILURE);
243
+ }
244
+
245
+ arg = arch_mcontext_arg(mc);
246
+ if (arg != test->expected_arg) {
247
+ printf("[ FAILED ] wrong arg (%d != %d)\n", arg, test->expected_arg);
248
+ exit(EXIT_FAILURE);
249
+ }
250
+
251
+ if (mprotect(page_base, page_size,
252
+ PROT_READ | PROT_WRITE | PROT_EXEC) < 0) {
253
+ handle_err("mprotect");
254
+ }
255
+}
256
+
257
+static void test_noexec_1(const struct noexec_test *test)
258
+{
259
+ void *start = page_base + test->page_ofs;
260
+ void (*fn)(int arg) = page_base + test->entry_ofs;
261
+
262
+ memcpy(start, test->test_code, test->test_len);
263
+ arch_flush(start, test->test_len);
264
+
265
+ /* Trigger TB creation in order to test invalidation. */
266
+ fn(0);
267
+
268
+ if (mprotect(page_base, page_size, PROT_NONE) < 0) {
269
+ handle_err("mprotect");
270
+ }
271
+
272
+ /* Trigger SEGV and check that handle_segv() ran. */
273
+ current_noexec_test = test;
274
+ fn(0);
275
+ assert(current_noexec_test == NULL);
276
+}
277
+
278
+static int test_noexec(struct noexec_test *tests, size_t n_tests)
279
+{
280
+ struct sigaction act;
281
+ size_t i;
282
+
283
+ memset(&act, 0, sizeof(act));
284
+ act.sa_sigaction = handle_segv;
285
+ act.sa_flags = SA_SIGINFO;
286
+ if (sigaction(SIGSEGV, &act, NULL) < 0) {
287
+ handle_err("sigaction");
288
+ }
289
+
290
+ page_size = getpagesize();
291
+ page_base = mmap(NULL, 2 * page_size,
292
+ PROT_READ | PROT_WRITE | PROT_EXEC,
293
+ MAP_ANONYMOUS | MAP_PRIVATE, -1, 0);
294
+ if (page_base == MAP_FAILED) {
295
+ handle_err("mmap");
296
+ }
297
+ page_base += page_size;
298
+
299
+ for (i = 0; i < n_tests; i++) {
300
+ struct noexec_test *test = &tests[i];
301
+
302
+ printf("[ RUN ] %s\n", test->name);
303
+ test_noexec_1(test);
304
+ printf("[ OK ]\n");
305
+ }
306
+
307
+ printf("[ PASSED ]\n");
308
+ return EXIT_SUCCESS;
309
+}
310
diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.target
30
index XXXXXXX..XXXXXXX 100644
311
index XXXXXXX..XXXXXXX 100644
31
--- a/tcg/i386/tcg-target.inc.c
312
--- a/tests/tcg/s390x/Makefile.target
32
+++ b/tcg/i386/tcg-target.inc.c
313
+++ b/tests/tcg/s390x/Makefile.target
33
@@ -XXX,XX +XXX,XX @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
314
@@ -XXX,XX +XXX,XX @@ TESTS+=shift
34
#define OPC_SHUFPS (0xc6 | P_EXT)
315
TESTS+=trap
35
#define OPC_SHLX (0xf7 | P_EXT38 | P_DATA16)
316
TESTS+=signals-s390x
36
#define OPC_SHRX (0xf7 | P_EXT38 | P_SIMDF2)
317
TESTS+=branch-relative-long
37
+#define OPC_SHRD_Ib (0xac | P_EXT)
318
+TESTS+=noexec
38
#define OPC_TESTL    (0x85)
319
39
#define OPC_TZCNT (0xbc | P_EXT | P_SIMDF3)
320
Z14_TESTS=vfminmax
40
#define OPC_UD2 (0x0b | P_EXT)
321
vfminmax: LDFLAGS+=-lm
41
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
42
}
43
break;
44
45
+ OP_32_64(extract2):
46
+ /* Note that SHRD outputs to the r/m operand. */
47
+ tcg_out_modrm(s, OPC_SHRD_Ib + rexw, a2, a0);
48
+ tcg_out8(s, args[3]);
49
+ break;
50
+
51
case INDEX_op_mb:
52
tcg_out_mb(s, a0);
53
break;
54
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
55
static const TCGTargetOpDef r_0 = { .args_ct_str = { "r", "0" } };
56
static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
57
static const TCGTargetOpDef r_r_re = { .args_ct_str = { "r", "r", "re" } };
58
+ static const TCGTargetOpDef r_0_r = { .args_ct_str = { "r", "0", "r" } };
59
static const TCGTargetOpDef r_0_re = { .args_ct_str = { "r", "0", "re" } };
60
static const TCGTargetOpDef r_0_ci = { .args_ct_str = { "r", "0", "ci" } };
61
static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
62
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
63
case INDEX_op_ctpop_i32:
64
case INDEX_op_ctpop_i64:
65
return &r_r;
66
+ case INDEX_op_extract2_i32:
67
+ case INDEX_op_extract2_i64:
68
+ return &r_0_r;
69
70
case INDEX_op_deposit_i32:
71
case INDEX_op_deposit_i64:
72
--
322
--
73
2.17.1
323
2.34.1
74
75
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/15] tcg: Restart TB generation after relocation overflow
[PULL 18/20] target/i386: Make translator stop before the end of a page
1
If the TB generates too much code, such that backend relocations
1
From: Ilya Leoshkevich <iii@linux.ibm.com>
2
overflow, try again with a smaller TB. In support of this, move
2
3
relocation processing from a random place within tcg_out_op, in
3
Right now translator stops right *after* the end of a page, which
4
the handling of branch opcodes, to a new function at the end of
4
breaks reporting of fault locations when the last instruction of a
5
tcg_gen_code.
5
multi-insn translation block crosses a page boundary.
6
6
7
This is not a complete solution, as there are additional relocs
7
An implementation, like the one arm and s390x have, would require an
8
generated for out-of-line ldst handling and constant pools.
8
i386 length disassembler, which is burdensome to maintain. Another
9
9
alternative would be to single-step at the end of a guest page, but
10
this may come with a performance impact.
11
12
Fix by snapshotting disassembly state and restoring it after we figure
13
out we crossed a page boundary. This includes rolling back cc_op
14
updates and emitted ops.
15
16
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
18
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1143
19
Message-Id: <20220817150506.592862-4-iii@linux.ibm.com>
20
[rth: Simplify end-of-insn cross-page checks.]
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
21
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
22
---
12
tcg/tcg.h | 15 +++++++-------
23
target/i386/tcg/translate.c | 64 ++++++++++++++++-----------
13
tcg/tcg.c | 61 ++++++++++++++++++++++++++-----------------------------
24
tests/tcg/x86_64/noexec.c | 75 ++++++++++++++++++++++++++++++++
14
2 files changed, 36 insertions(+), 40 deletions(-)
25
tests/tcg/x86_64/Makefile.target | 3 +-
15
26
3 files changed, 116 insertions(+), 26 deletions(-)
16
diff --git a/tcg/tcg.h b/tcg/tcg.h
27
create mode 100644 tests/tcg/x86_64/noexec.c
28
29
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
17
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
18
--- a/tcg/tcg.h
31
--- a/target/i386/tcg/translate.c
19
+++ b/tcg/tcg.h
32
+++ b/target/i386/tcg/translate.c
20
@@ -XXX,XX +XXX,XX @@ typedef uint64_t tcg_insn_unit;
33
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
21
do { if (!(X)) { __builtin_unreachable(); } } while (0)
34
TCGv_i64 tmp1_i64;
35
36
sigjmp_buf jmpbuf;
37
+ TCGOp *prev_insn_end;
38
} DisasContext;
39
40
/* The environment in which user-only runs is constrained. */
41
@@ -XXX,XX +XXX,XX @@ static uint64_t advance_pc(CPUX86State *env, DisasContext *s, int num_bytes)
42
{
43
uint64_t pc = s->pc;
44
45
+ /* This is a subsequent insn that crosses a page boundary. */
46
+ if (s->base.num_insns > 1 &&
47
+ !is_same_page(&s->base, s->pc + num_bytes - 1)) {
48
+ siglongjmp(s->jmpbuf, 2);
49
+ }
50
+
51
s->pc += num_bytes;
52
if (unlikely(s->pc - s->pc_start > X86_MAX_INSN_LENGTH)) {
53
/* If the instruction's 16th byte is on a different page than the 1st, a
54
@@ -XXX,XX +XXX,XX @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
55
int modrm, reg, rm, mod, op, opreg, val;
56
target_ulong next_eip, tval;
57
target_ulong pc_start = s->base.pc_next;
58
+ bool orig_cc_op_dirty = s->cc_op_dirty;
59
+ CCOp orig_cc_op = s->cc_op;
60
61
s->pc_start = s->pc = pc_start;
62
s->override = -1;
63
@@ -XXX,XX +XXX,XX @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu)
64
s->rip_offset = 0; /* for relative ip address */
65
s->vex_l = 0;
66
s->vex_v = 0;
67
- if (sigsetjmp(s->jmpbuf, 0) != 0) {
68
+ switch (sigsetjmp(s->jmpbuf, 0)) {
69
+ case 0:
70
+ break;
71
+ case 1:
72
gen_exception_gpf(s);
73
return s->pc;
74
+ case 2:
75
+ /* Restore state that may affect the next instruction. */
76
+ s->cc_op_dirty = orig_cc_op_dirty;
77
+ s->cc_op = orig_cc_op;
78
+ s->base.num_insns--;
79
+ tcg_remove_ops_after(s->prev_insn_end);
80
+ s->base.is_jmp = DISAS_TOO_MANY;
81
+ return pc_start;
82
+ default:
83
+ g_assert_not_reached();
84
}
85
86
prefixes = 0;
87
@@ -XXX,XX +XXX,XX @@ static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
88
{
89
DisasContext *dc = container_of(dcbase, DisasContext, base);
90
91
+ dc->prev_insn_end = tcg_last_op();
92
tcg_gen_insn_start(dc->base.pc_next, dc->cc_op);
93
}
94
95
@@ -XXX,XX +XXX,XX @@ static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
22
#endif
96
#endif
23
97
24
-typedef struct TCGRelocation {
98
pc_next = disas_insn(dc, cpu);
25
- struct TCGRelocation *next;
26
- int type;
27
+typedef struct TCGRelocation TCGRelocation;
28
+struct TCGRelocation {
29
+ QSIMPLEQ_ENTRY(TCGRelocation) next;
30
tcg_insn_unit *ptr;
31
intptr_t addend;
32
-} TCGRelocation;
33
+ int type;
34
+};
35
36
typedef struct TCGLabel TCGLabel;
37
struct TCGLabel {
38
@@ -XXX,XX +XXX,XX @@ struct TCGLabel {
39
union {
40
uintptr_t value;
41
tcg_insn_unit *value_ptr;
42
- TCGRelocation *first_reloc;
43
} u;
44
-#ifdef CONFIG_DEBUG_TCG
45
+ QSIMPLEQ_HEAD(, TCGRelocation) relocs;
46
QSIMPLEQ_ENTRY(TCGLabel) next;
47
-#endif
48
};
49
50
typedef struct TCGPool {
51
@@ -XXX,XX +XXX,XX @@ struct TCGContext {
52
#endif
53
54
#ifdef CONFIG_DEBUG_TCG
55
- QSIMPLEQ_HEAD(, TCGLabel) labels;
56
int temps_in_use;
57
int goto_tb_issue_mask;
58
#endif
59
@@ -XXX,XX +XXX,XX @@ struct TCGContext {
60
TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */
61
62
QTAILQ_HEAD(, TCGOp) ops, free_ops;
63
+ QSIMPLEQ_HEAD(, TCGLabel) labels;
64
65
/* Tells which temporary holds a given register.
66
It does not take into account fixed registers */
67
diff --git a/tcg/tcg.c b/tcg/tcg.c
68
index XXXXXXX..XXXXXXX 100644
69
--- a/tcg/tcg.c
70
+++ b/tcg/tcg.c
71
@@ -XXX,XX +XXX,XX @@ static __attribute__((unused)) inline void tcg_patch64(tcg_insn_unit *p,
72
static void tcg_out_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type,
73
TCGLabel *l, intptr_t addend)
74
{
75
- TCGRelocation *r;
76
+ TCGRelocation *r = tcg_malloc(sizeof(TCGRelocation));
77
78
- if (l->has_value) {
79
- /* FIXME: This may break relocations on RISC targets that
80
- modify instruction fields in place. The caller may not have
81
- written the initial value. */
82
- bool ok = patch_reloc(code_ptr, type, l->u.value, addend);
83
- tcg_debug_assert(ok);
84
- } else {
85
- /* add a new relocation entry */
86
- r = tcg_malloc(sizeof(TCGRelocation));
87
- r->type = type;
88
- r->ptr = code_ptr;
89
- r->addend = addend;
90
- r->next = l->u.first_reloc;
91
- l->u.first_reloc = r;
92
- }
93
+ r->type = type;
94
+ r->ptr = code_ptr;
95
+ r->addend = addend;
96
+ QSIMPLEQ_INSERT_TAIL(&l->relocs, r, next);
97
}
98
99
static void tcg_out_label(TCGContext *s, TCGLabel *l, tcg_insn_unit *ptr)
100
{
101
- intptr_t value = (intptr_t)ptr;
102
- TCGRelocation *r;
103
-
99
-
104
tcg_debug_assert(!l->has_value);
100
- if (dc->flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK)) {
105
-
101
- /* if single step mode, we generate only one instruction and
106
- for (r = l->u.first_reloc; r != NULL; r = r->next) {
102
- generate an exception */
107
- bool ok = patch_reloc(r->ptr, r->type, value, r->addend);
103
- /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
108
- tcg_debug_assert(ok);
104
- the flag and abort the translation to give the irqs a
105
- chance to happen */
106
- dc->base.is_jmp = DISAS_TOO_MANY;
107
- } else if ((tb_cflags(dc->base.tb) & CF_USE_ICOUNT)
108
- && ((pc_next & TARGET_PAGE_MASK)
109
- != ((pc_next + TARGET_MAX_INSN_SIZE - 1)
110
- & TARGET_PAGE_MASK)
111
- || (pc_next & ~TARGET_PAGE_MASK) == 0)) {
112
- /* Do not cross the boundary of the pages in icount mode,
113
- it can cause an exception. Do it only when boundary is
114
- crossed by the first instruction in the block.
115
- If current instruction already crossed the bound - it's ok,
116
- because an exception hasn't stopped this code.
117
- */
118
- dc->base.is_jmp = DISAS_TOO_MANY;
119
- } else if ((pc_next - dc->base.pc_first) >= (TARGET_PAGE_SIZE - 32)) {
120
- dc->base.is_jmp = DISAS_TOO_MANY;
109
- }
121
- }
110
-
122
-
111
l->has_value = 1;
123
dc->base.pc_next = pc_next;
112
l->u.value_ptr = ptr;
124
+
113
}
125
+ if (dc->base.is_jmp == DISAS_NEXT) {
114
@@ -XXX,XX +XXX,XX @@ TCGLabel *gen_new_label(void)
126
+ if (dc->flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK)) {
115
TCGContext *s = tcg_ctx;
127
+ /*
116
TCGLabel *l = tcg_malloc(sizeof(TCGLabel));
128
+ * If single step mode, we generate only one instruction and
117
129
+ * generate an exception.
118
- *l = (TCGLabel){
130
+ * If irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
119
- .id = s->nb_labels++
131
+ * the flag and abort the translation to give the irqs a
120
- };
132
+ * chance to happen.
121
-#ifdef CONFIG_DEBUG_TCG
133
+ */
122
+ memset(l, 0, sizeof(TCGLabel));
134
+ dc->base.is_jmp = DISAS_TOO_MANY;
123
+ l->id = s->nb_labels++;
135
+ } else if (!is_same_page(&dc->base, pc_next)) {
124
+ QSIMPLEQ_INIT(&l->relocs);
136
+ dc->base.is_jmp = DISAS_TOO_MANY;
125
+
126
QSIMPLEQ_INSERT_TAIL(&s->labels, l, next);
127
-#endif
128
129
return l;
130
}
131
132
+static bool tcg_resolve_relocs(TCGContext *s)
133
+{
134
+ TCGLabel *l;
135
+
136
+ QSIMPLEQ_FOREACH(l, &s->labels, next) {
137
+ TCGRelocation *r;
138
+ uintptr_t value = l->u.value;
139
+
140
+ QSIMPLEQ_FOREACH(r, &l->relocs, next) {
141
+ if (!patch_reloc(r->ptr, r->type, value, r->addend)) {
142
+ return false;
143
+ }
144
+ }
137
+ }
145
+ }
138
+ }
146
+ return true;
147
+}
148
+
149
static void set_jmp_reset_offset(TCGContext *s, int which)
150
{
151
size_t off = tcg_current_code_size(s);
152
@@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s)
153
154
QTAILQ_INIT(&s->ops);
155
QTAILQ_INIT(&s->free_ops);
156
-#ifdef CONFIG_DEBUG_TCG
157
QSIMPLEQ_INIT(&s->labels);
158
-#endif
159
}
139
}
160
140
161
static inline TCGTemp *tcg_temp_alloc(TCGContext *s)
141
static void i386_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
162
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
142
diff --git a/tests/tcg/x86_64/noexec.c b/tests/tcg/x86_64/noexec.c
163
return -1;
143
new file mode 100644
164
}
144
index XXXXXXX..XXXXXXX
165
#endif
145
--- /dev/null
166
+ if (!tcg_resolve_relocs(s)) {
146
+++ b/tests/tcg/x86_64/noexec.c
167
+ return -2;
147
@@ -XXX,XX +XXX,XX @@
168
+ }
148
+#include "../multiarch/noexec.c.inc"
169
149
+
170
/* flush instruction cache */
150
+static void *arch_mcontext_pc(const mcontext_t *ctx)
171
flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr);
151
+{
152
+ return (void *)ctx->gregs[REG_RIP];
153
+}
154
+
155
+int arch_mcontext_arg(const mcontext_t *ctx)
156
+{
157
+ return ctx->gregs[REG_RDI];
158
+}
159
+
160
+static void arch_flush(void *p, int len)
161
+{
162
+}
163
+
164
+extern char noexec_1[];
165
+extern char noexec_2[];
166
+extern char noexec_end[];
167
+
168
+asm("noexec_1:\n"
169
+ " movq $1,%rdi\n" /* %rdi is 0 on entry, set 1. */
170
+ "noexec_2:\n"
171
+ " movq $2,%rdi\n" /* %rdi is 0/1; set 2. */
172
+ " ret\n"
173
+ "noexec_end:");
174
+
175
+int main(void)
176
+{
177
+ struct noexec_test noexec_tests[] = {
178
+ {
179
+ .name = "fallthrough",
180
+ .test_code = noexec_1,
181
+ .test_len = noexec_end - noexec_1,
182
+ .page_ofs = noexec_1 - noexec_2,
183
+ .entry_ofs = noexec_1 - noexec_2,
184
+ .expected_si_ofs = 0,
185
+ .expected_pc_ofs = 0,
186
+ .expected_arg = 1,
187
+ },
188
+ {
189
+ .name = "jump",
190
+ .test_code = noexec_1,
191
+ .test_len = noexec_end - noexec_1,
192
+ .page_ofs = noexec_1 - noexec_2,
193
+ .entry_ofs = 0,
194
+ .expected_si_ofs = 0,
195
+ .expected_pc_ofs = 0,
196
+ .expected_arg = 0,
197
+ },
198
+ {
199
+ .name = "fallthrough [cross]",
200
+ .test_code = noexec_1,
201
+ .test_len = noexec_end - noexec_1,
202
+ .page_ofs = noexec_1 - noexec_2 - 2,
203
+ .entry_ofs = noexec_1 - noexec_2 - 2,
204
+ .expected_si_ofs = 0,
205
+ .expected_pc_ofs = -2,
206
+ .expected_arg = 1,
207
+ },
208
+ {
209
+ .name = "jump [cross]",
210
+ .test_code = noexec_1,
211
+ .test_len = noexec_end - noexec_1,
212
+ .page_ofs = noexec_1 - noexec_2 - 2,
213
+ .entry_ofs = -2,
214
+ .expected_si_ofs = 0,
215
+ .expected_pc_ofs = -2,
216
+ .expected_arg = 0,
217
+ },
218
+ };
219
+
220
+ return test_noexec(noexec_tests,
221
+ sizeof(noexec_tests) / sizeof(noexec_tests[0]));
222
+}
223
diff --git a/tests/tcg/x86_64/Makefile.target b/tests/tcg/x86_64/Makefile.target
224
index XXXXXXX..XXXXXXX 100644
225
--- a/tests/tcg/x86_64/Makefile.target
226
+++ b/tests/tcg/x86_64/Makefile.target
227
@@ -XXX,XX +XXX,XX @@ include $(SRC_PATH)/tests/tcg/i386/Makefile.target
228
229
ifeq ($(filter %-linux-user, $(TARGET)),$(TARGET))
230
X86_64_TESTS += vsyscall
231
+X86_64_TESTS += noexec
232
TESTS=$(MULTIARCH_TESTS) $(X86_64_TESTS) test-x86_64
233
else
234
TESTS=$(MULTIARCH_TESTS)
235
@@ -XXX,XX +XXX,XX @@ test-x86_64: LDFLAGS+=-lm -lc
236
test-x86_64: test-i386.c test-i386.h test-i386-shift.h test-i386-muldiv.h
237
    $(CC) $(CFLAGS) $< -o $@ $(LDFLAGS)
238
239
-vsyscall: $(SRC_PATH)/tests/tcg/x86_64/vsyscall.c
240
+%: $(SRC_PATH)/tests/tcg/x86_64/%.c
241
    $(CC) $(CFLAGS) $< -o $@ $(LDFLAGS)
172
--
242
--
173
2.17.1
243
2.34.1
174
175
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/15] tcg: Add INDEX_op_extract2_{i32,i64}
[PULL 19/20] target/riscv: Add MAX_INSN_LEN and insn_len
1
This will let backends implement the double-word shift operation.
1
These will be useful in properly ending the TB.
2
2
3
Reviewed-by: David Hildenbrand <david@redhat.com>
3
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
4
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
5
Tested-by: Ilya Leoshkevich <iii@linux.ibm.com>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
7
---
6
tcg/aarch64/tcg-target.h | 2 ++
8
target/riscv/translate.c | 10 +++++++++-
7
tcg/arm/tcg-target.h | 1 +
9
1 file changed, 9 insertions(+), 1 deletion(-)
8
tcg/i386/tcg-target.h | 2 ++
9
tcg/mips/tcg-target.h | 2 ++
10
tcg/ppc/tcg-target.h | 2 ++
11
tcg/riscv/tcg-target.h | 2 ++
12
tcg/s390/tcg-target.h | 2 ++
13
tcg/sparc/tcg-target.h | 2 ++
14
tcg/tcg-opc.h | 2 ++
15
tcg/tcg.h | 1 +
16
tcg/tci/tcg-target.h | 2 ++
17
tcg/optimize.c | 16 ++++++++++++++++
18
tcg/tcg-op.c | 4 ++++
19
tcg/tcg.c | 4 ++++
20
tcg/README | 7 +++++++
21
15 files changed, 51 insertions(+)
22
10
23
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
11
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
24
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
25
--- a/tcg/aarch64/tcg-target.h
13
--- a/target/riscv/translate.c
26
+++ b/tcg/aarch64/tcg-target.h
14
+++ b/target/riscv/translate.c
27
@@ -XXX,XX +XXX,XX @@ typedef enum {
15
@@ -XXX,XX +XXX,XX @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
28
#define TCG_TARGET_HAS_deposit_i32 1
16
/* Include decoders for factored-out extensions */
29
#define TCG_TARGET_HAS_extract_i32 1
17
#include "decode-XVentanaCondOps.c.inc"
30
#define TCG_TARGET_HAS_sextract_i32 1
18
31
+#define TCG_TARGET_HAS_extract2_i32 0
19
+/* The specification allows for longer insns, but not supported by qemu. */
32
#define TCG_TARGET_HAS_movcond_i32 1
20
+#define MAX_INSN_LEN 4
33
#define TCG_TARGET_HAS_add2_i32 1
34
#define TCG_TARGET_HAS_sub2_i32 1
35
@@ -XXX,XX +XXX,XX @@ typedef enum {
36
#define TCG_TARGET_HAS_deposit_i64 1
37
#define TCG_TARGET_HAS_extract_i64 1
38
#define TCG_TARGET_HAS_sextract_i64 1
39
+#define TCG_TARGET_HAS_extract2_i64 0
40
#define TCG_TARGET_HAS_movcond_i64 1
41
#define TCG_TARGET_HAS_add2_i64 1
42
#define TCG_TARGET_HAS_sub2_i64 1
43
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
44
index XXXXXXX..XXXXXXX 100644
45
--- a/tcg/arm/tcg-target.h
46
+++ b/tcg/arm/tcg-target.h
47
@@ -XXX,XX +XXX,XX @@ extern bool use_idiv_instructions;
48
#define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions
49
#define TCG_TARGET_HAS_extract_i32 use_armv7_instructions
50
#define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions
51
+#define TCG_TARGET_HAS_extract2_i32 0
52
#define TCG_TARGET_HAS_movcond_i32 1
53
#define TCG_TARGET_HAS_mulu2_i32 1
54
#define TCG_TARGET_HAS_muls2_i32 1
55
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
56
index XXXXXXX..XXXXXXX 100644
57
--- a/tcg/i386/tcg-target.h
58
+++ b/tcg/i386/tcg-target.h
59
@@ -XXX,XX +XXX,XX @@ extern bool have_avx2;
60
#define TCG_TARGET_HAS_deposit_i32 1
61
#define TCG_TARGET_HAS_extract_i32 1
62
#define TCG_TARGET_HAS_sextract_i32 1
63
+#define TCG_TARGET_HAS_extract2_i32 0
64
#define TCG_TARGET_HAS_movcond_i32 1
65
#define TCG_TARGET_HAS_add2_i32 1
66
#define TCG_TARGET_HAS_sub2_i32 1
67
@@ -XXX,XX +XXX,XX @@ extern bool have_avx2;
68
#define TCG_TARGET_HAS_deposit_i64 1
69
#define TCG_TARGET_HAS_extract_i64 1
70
#define TCG_TARGET_HAS_sextract_i64 0
71
+#define TCG_TARGET_HAS_extract2_i64 0
72
#define TCG_TARGET_HAS_movcond_i64 1
73
#define TCG_TARGET_HAS_add2_i64 1
74
#define TCG_TARGET_HAS_sub2_i64 1
75
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
76
index XXXXXXX..XXXXXXX 100644
77
--- a/tcg/mips/tcg-target.h
78
+++ b/tcg/mips/tcg-target.h
79
@@ -XXX,XX +XXX,XX @@ extern bool use_mips32r2_instructions;
80
#define TCG_TARGET_HAS_deposit_i32 use_mips32r2_instructions
81
#define TCG_TARGET_HAS_extract_i32 use_mips32r2_instructions
82
#define TCG_TARGET_HAS_sextract_i32 0
83
+#define TCG_TARGET_HAS_extract2_i32 0
84
#define TCG_TARGET_HAS_ext8s_i32 use_mips32r2_instructions
85
#define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions
86
#define TCG_TARGET_HAS_rot_i32 use_mips32r2_instructions
87
@@ -XXX,XX +XXX,XX @@ extern bool use_mips32r2_instructions;
88
#define TCG_TARGET_HAS_deposit_i64 use_mips32r2_instructions
89
#define TCG_TARGET_HAS_extract_i64 use_mips32r2_instructions
90
#define TCG_TARGET_HAS_sextract_i64 0
91
+#define TCG_TARGET_HAS_extract2_i64 0
92
#define TCG_TARGET_HAS_ext8s_i64 use_mips32r2_instructions
93
#define TCG_TARGET_HAS_ext16s_i64 use_mips32r2_instructions
94
#define TCG_TARGET_HAS_rot_i64 use_mips32r2_instructions
95
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
96
index XXXXXXX..XXXXXXX 100644
97
--- a/tcg/ppc/tcg-target.h
98
+++ b/tcg/ppc/tcg-target.h
99
@@ -XXX,XX +XXX,XX @@ extern bool have_isa_3_00;
100
#define TCG_TARGET_HAS_deposit_i32 1
101
#define TCG_TARGET_HAS_extract_i32 1
102
#define TCG_TARGET_HAS_sextract_i32 0
103
+#define TCG_TARGET_HAS_extract2_i32 0
104
#define TCG_TARGET_HAS_movcond_i32 1
105
#define TCG_TARGET_HAS_mulu2_i32 0
106
#define TCG_TARGET_HAS_muls2_i32 0
107
@@ -XXX,XX +XXX,XX @@ extern bool have_isa_3_00;
108
#define TCG_TARGET_HAS_deposit_i64 1
109
#define TCG_TARGET_HAS_extract_i64 1
110
#define TCG_TARGET_HAS_sextract_i64 0
111
+#define TCG_TARGET_HAS_extract2_i64 0
112
#define TCG_TARGET_HAS_movcond_i64 1
113
#define TCG_TARGET_HAS_add2_i64 1
114
#define TCG_TARGET_HAS_sub2_i64 1
115
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
116
index XXXXXXX..XXXXXXX 100644
117
--- a/tcg/riscv/tcg-target.h
118
+++ b/tcg/riscv/tcg-target.h
119
@@ -XXX,XX +XXX,XX @@ typedef enum {
120
#define TCG_TARGET_HAS_deposit_i32 0
121
#define TCG_TARGET_HAS_extract_i32 0
122
#define TCG_TARGET_HAS_sextract_i32 0
123
+#define TCG_TARGET_HAS_extract2_i32 0
124
#define TCG_TARGET_HAS_add2_i32 1
125
#define TCG_TARGET_HAS_sub2_i32 1
126
#define TCG_TARGET_HAS_mulu2_i32 0
127
@@ -XXX,XX +XXX,XX @@ typedef enum {
128
#define TCG_TARGET_HAS_deposit_i64 0
129
#define TCG_TARGET_HAS_extract_i64 0
130
#define TCG_TARGET_HAS_sextract_i64 0
131
+#define TCG_TARGET_HAS_extract2_i64 0
132
#define TCG_TARGET_HAS_extrl_i64_i32 1
133
#define TCG_TARGET_HAS_extrh_i64_i32 1
134
#define TCG_TARGET_HAS_ext8s_i64 1
135
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
136
index XXXXXXX..XXXXXXX 100644
137
--- a/tcg/s390/tcg-target.h
138
+++ b/tcg/s390/tcg-target.h
139
@@ -XXX,XX +XXX,XX @@ extern uint64_t s390_facilities;
140
#define TCG_TARGET_HAS_deposit_i32 (s390_facilities & FACILITY_GEN_INST_EXT)
141
#define TCG_TARGET_HAS_extract_i32 (s390_facilities & FACILITY_GEN_INST_EXT)
142
#define TCG_TARGET_HAS_sextract_i32 0
143
+#define TCG_TARGET_HAS_extract2_i32 0
144
#define TCG_TARGET_HAS_movcond_i32 1
145
#define TCG_TARGET_HAS_add2_i32 1
146
#define TCG_TARGET_HAS_sub2_i32 1
147
@@ -XXX,XX +XXX,XX @@ extern uint64_t s390_facilities;
148
#define TCG_TARGET_HAS_deposit_i64 (s390_facilities & FACILITY_GEN_INST_EXT)
149
#define TCG_TARGET_HAS_extract_i64 (s390_facilities & FACILITY_GEN_INST_EXT)
150
#define TCG_TARGET_HAS_sextract_i64 0
151
+#define TCG_TARGET_HAS_extract2_i64 0
152
#define TCG_TARGET_HAS_movcond_i64 1
153
#define TCG_TARGET_HAS_add2_i64 1
154
#define TCG_TARGET_HAS_sub2_i64 1
155
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
156
index XXXXXXX..XXXXXXX 100644
157
--- a/tcg/sparc/tcg-target.h
158
+++ b/tcg/sparc/tcg-target.h
159
@@ -XXX,XX +XXX,XX @@ extern bool use_vis3_instructions;
160
#define TCG_TARGET_HAS_deposit_i32 0
161
#define TCG_TARGET_HAS_extract_i32 0
162
#define TCG_TARGET_HAS_sextract_i32 0
163
+#define TCG_TARGET_HAS_extract2_i32 0
164
#define TCG_TARGET_HAS_movcond_i32 1
165
#define TCG_TARGET_HAS_add2_i32 1
166
#define TCG_TARGET_HAS_sub2_i32 1
167
@@ -XXX,XX +XXX,XX @@ extern bool use_vis3_instructions;
168
#define TCG_TARGET_HAS_deposit_i64 0
169
#define TCG_TARGET_HAS_extract_i64 0
170
#define TCG_TARGET_HAS_sextract_i64 0
171
+#define TCG_TARGET_HAS_extract2_i64 0
172
#define TCG_TARGET_HAS_movcond_i64 1
173
#define TCG_TARGET_HAS_add2_i64 1
174
#define TCG_TARGET_HAS_sub2_i64 1
175
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
176
index XXXXXXX..XXXXXXX 100644
177
--- a/tcg/tcg-opc.h
178
+++ b/tcg/tcg-opc.h
179
@@ -XXX,XX +XXX,XX @@ DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
180
DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32))
181
DEF(extract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_extract_i32))
182
DEF(sextract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_sextract_i32))
183
+DEF(extract2_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_extract2_i32))
184
185
DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END)
186
187
@@ -XXX,XX +XXX,XX @@ DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
188
DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64))
189
DEF(extract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_extract_i64))
190
DEF(sextract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_sextract_i64))
191
+DEF(extract2_i64, 1, 2, 1, IMPL64 | IMPL(TCG_TARGET_HAS_extract2_i64))
192
193
/* size changing ops */
194
DEF(ext_i32_i64, 1, 1, 0, IMPL64)
195
diff --git a/tcg/tcg.h b/tcg/tcg.h
196
index XXXXXXX..XXXXXXX 100644
197
--- a/tcg/tcg.h
198
+++ b/tcg/tcg.h
199
@@ -XXX,XX +XXX,XX @@ typedef uint64_t TCGRegSet;
200
#define TCG_TARGET_HAS_deposit_i64 0
201
#define TCG_TARGET_HAS_extract_i64 0
202
#define TCG_TARGET_HAS_sextract_i64 0
203
+#define TCG_TARGET_HAS_extract2_i64 0
204
#define TCG_TARGET_HAS_movcond_i64 0
205
#define TCG_TARGET_HAS_add2_i64 0
206
#define TCG_TARGET_HAS_sub2_i64 0
207
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
208
index XXXXXXX..XXXXXXX 100644
209
--- a/tcg/tci/tcg-target.h
210
+++ b/tcg/tci/tcg-target.h
211
@@ -XXX,XX +XXX,XX @@
212
#define TCG_TARGET_HAS_deposit_i32 1
213
#define TCG_TARGET_HAS_extract_i32 0
214
#define TCG_TARGET_HAS_sextract_i32 0
215
+#define TCG_TARGET_HAS_extract2_i32 0
216
#define TCG_TARGET_HAS_eqv_i32 0
217
#define TCG_TARGET_HAS_nand_i32 0
218
#define TCG_TARGET_HAS_nor_i32 0
219
@@ -XXX,XX +XXX,XX @@
220
#define TCG_TARGET_HAS_deposit_i64 1
221
#define TCG_TARGET_HAS_extract_i64 0
222
#define TCG_TARGET_HAS_sextract_i64 0
223
+#define TCG_TARGET_HAS_extract2_i64 0
224
#define TCG_TARGET_HAS_div_i64 0
225
#define TCG_TARGET_HAS_rem_i64 0
226
#define TCG_TARGET_HAS_ext8s_i64 1
227
diff --git a/tcg/optimize.c b/tcg/optimize.c
228
index XXXXXXX..XXXXXXX 100644
229
--- a/tcg/optimize.c
230
+++ b/tcg/optimize.c
231
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
232
}
233
goto do_default;
234
235
+ CASE_OP_32_64(extract2):
236
+ if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
237
+ TCGArg v1 = arg_info(op->args[1])->val;
238
+ TCGArg v2 = arg_info(op->args[2])->val;
239
+
21
+
240
+ if (opc == INDEX_op_extract2_i64) {
22
+static inline int insn_len(uint16_t first_word)
241
+ tmp = (v1 >> op->args[3]) | (v2 << (64 - op->args[3]));
23
+{
242
+ } else {
24
+ return (first_word & 3) == 3 ? 4 : 2;
243
+ tmp = (v1 >> op->args[3]) | (v2 << (32 - op->args[3]));
25
+}
244
+ tmp = (int32_t)tmp;
245
+ }
246
+ tcg_opt_gen_movi(s, op, op->args[0], tmp);
247
+ break;
248
+ }
249
+ goto do_default;
250
+
26
+
251
CASE_OP_32_64(setcond):
27
static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
252
tmp = do_constant_folding_cond(opc, op->args[1],
28
{
253
op->args[2], op->args[3]);
29
/*
254
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
30
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
255
index XXXXXXX..XXXXXXX 100644
31
};
256
--- a/tcg/tcg-op.c
32
257
+++ b/tcg/tcg-op.c
33
/* Check for compressed insn */
258
@@ -XXX,XX +XXX,XX @@ void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah,
34
- if (extract16(opcode, 0, 2) != 3) {
259
tcg_gen_mov_i32(ret, ah);
35
+ if (insn_len(opcode) == 2) {
260
} else if (al == ah) {
36
if (!has_ext(ctx, RVC)) {
261
tcg_gen_rotri_i32(ret, al, ofs);
37
gen_exception_illegal(ctx);
262
+ } else if (TCG_TARGET_HAS_extract2_i32) {
38
} else {
263
+ tcg_gen_op4i_i32(INDEX_op_extract2_i32, ret, al, ah, ofs);
264
} else {
265
TCGv_i32 t0 = tcg_temp_new_i32();
266
tcg_gen_shri_i32(t0, al, ofs);
267
@@ -XXX,XX +XXX,XX @@ void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah,
268
tcg_gen_mov_i64(ret, ah);
269
} else if (al == ah) {
270
tcg_gen_rotri_i64(ret, al, ofs);
271
+ } else if (TCG_TARGET_HAS_extract2_i64) {
272
+ tcg_gen_op4i_i64(INDEX_op_extract2_i64, ret, al, ah, ofs);
273
} else {
274
TCGv_i64 t0 = tcg_temp_new_i64();
275
tcg_gen_shri_i64(t0, al, ofs);
276
diff --git a/tcg/tcg.c b/tcg/tcg.c
277
index XXXXXXX..XXXXXXX 100644
278
--- a/tcg/tcg.c
279
+++ b/tcg/tcg.c
280
@@ -XXX,XX +XXX,XX @@ bool tcg_op_supported(TCGOpcode op)
281
return TCG_TARGET_HAS_extract_i32;
282
case INDEX_op_sextract_i32:
283
return TCG_TARGET_HAS_sextract_i32;
284
+ case INDEX_op_extract2_i32:
285
+ return TCG_TARGET_HAS_extract2_i32;
286
case INDEX_op_add2_i32:
287
return TCG_TARGET_HAS_add2_i32;
288
case INDEX_op_sub2_i32:
289
@@ -XXX,XX +XXX,XX @@ bool tcg_op_supported(TCGOpcode op)
290
return TCG_TARGET_HAS_extract_i64;
291
case INDEX_op_sextract_i64:
292
return TCG_TARGET_HAS_sextract_i64;
293
+ case INDEX_op_extract2_i64:
294
+ return TCG_TARGET_HAS_extract2_i64;
295
case INDEX_op_extrl_i64_i32:
296
return TCG_TARGET_HAS_extrl_i64_i32;
297
case INDEX_op_extrh_i64_i32:
298
diff --git a/tcg/README b/tcg/README
299
index XXXXXXX..XXXXXXX 100644
300
--- a/tcg/README
301
+++ b/tcg/README
302
@@ -XXX,XX +XXX,XX @@ at bit 8. This operation would be equivalent to
303
304
(using an arithmetic right shift).
305
306
+* extract2_i32/i64 dest, t1, t2, pos
307
+
308
+For N = {32,64}, extract an N-bit quantity from the concatenation
309
+of t2:t1, beginning at pos. The tcg_gen_extract2_{i32,i64} expander
310
+accepts 0 <= pos <= N as inputs. The backend code generator will
311
+not see either 0 or N as inputs for these opcodes.
312
+
313
* extrl_i64_i32 t0, t1
314
315
For 64-bit hosts only, extract the low 32-bits of input T1 and place it
316
--
39
--
317
2.17.1
40
2.34.1
318
319
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/15] tcg: Implement tcg_gen_extract2_{i32, i64}
[PULL 20/20] target/riscv: Make translator stop before the end of a page
1
From: David Hildenbrand <david@redhat.com>
1
Right now the translator stops right *after* the end of a page, which
2
breaks reporting of fault locations when the last instruction of a
3
multi-insn translation block crosses a page boundary.
2
4
3
Will be helpful for s390x. Input 128 bit and output 64 bit only,
5
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1155
4
which is sufficient for now.
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
5
7
Acked-by: Ilya Leoshkevich <iii@linux.ibm.com>
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Tested-by: Ilya Leoshkevich <iii@linux.ibm.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: David Hildenbrand <david@redhat.com>
9
Message-Id: <20190225154204.26751-1-david@redhat.com>
10
[rth: Add matching tcg_gen_extract2_i32.]
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
---
10
---
13
tcg/tcg-op.h | 6 ++++++
11
target/riscv/translate.c | 17 +++++--
14
tcg/tcg-op.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
12
tests/tcg/riscv64/noexec.c | 79 +++++++++++++++++++++++++++++++
15
2 files changed, 50 insertions(+)
13
tests/tcg/riscv64/Makefile.target | 1 +
14
3 files changed, 93 insertions(+), 4 deletions(-)
15
create mode 100644 tests/tcg/riscv64/noexec.c
16
16
17
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
17
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
18
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
19
--- a/tcg/tcg-op.h
19
--- a/target/riscv/translate.c
20
+++ b/tcg/tcg-op.h
20
+++ b/target/riscv/translate.c
21
@@ -XXX,XX +XXX,XX @@ void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg,
21
@@ -XXX,XX +XXX,XX @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
22
unsigned int ofs, unsigned int len);
22
}
23
void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg,
23
ctx->nftemp = 0;
24
unsigned int ofs, unsigned int len);
24
25
+void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah,
25
+ /* Only the first insn within a TB is allowed to cross a page boundary. */
26
+ unsigned int ofs);
26
if (ctx->base.is_jmp == DISAS_NEXT) {
27
void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *);
27
- target_ulong page_start;
28
void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *);
28
-
29
void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
29
- page_start = ctx->base.pc_first & TARGET_PAGE_MASK;
30
@@ -XXX,XX +XXX,XX @@ void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg,
30
- if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) {
31
unsigned int ofs, unsigned int len);
31
+ if (!is_same_page(&ctx->base, ctx->base.pc_next)) {
32
void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg,
32
ctx->base.is_jmp = DISAS_TOO_MANY;
33
unsigned int ofs, unsigned int len);
33
+ } else {
34
+void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah,
34
+ unsigned page_ofs = ctx->base.pc_next & ~TARGET_PAGE_MASK;
35
+ unsigned int ofs);
35
+
36
void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *);
36
+ if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) {
37
void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *);
37
+ uint16_t next_insn = cpu_lduw_code(env, ctx->base.pc_next);
38
void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
38
+ int len = insn_len(next_insn);
39
@@ -XXX,XX +XXX,XX @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
39
+
40
#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64
40
+ if (!is_same_page(&ctx->base, ctx->base.pc_next + len)) {
41
#define tcg_gen_extract_tl tcg_gen_extract_i64
41
+ ctx->base.is_jmp = DISAS_TOO_MANY;
42
#define tcg_gen_sextract_tl tcg_gen_sextract_i64
42
+ }
43
+#define tcg_gen_extract2_tl tcg_gen_extract2_i64
43
+ }
44
#define tcg_const_tl tcg_const_i64
44
}
45
#define tcg_const_local_tl tcg_const_local_i64
45
}
46
#define tcg_gen_movcond_tl tcg_gen_movcond_i64
47
@@ -XXX,XX +XXX,XX @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
48
#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32
49
#define tcg_gen_extract_tl tcg_gen_extract_i32
50
#define tcg_gen_sextract_tl tcg_gen_sextract_i32
51
+#define tcg_gen_extract2_tl tcg_gen_extract2_i32
52
#define tcg_const_tl tcg_const_i32
53
#define tcg_const_local_tl tcg_const_local_i32
54
#define tcg_gen_movcond_tl tcg_gen_movcond_i32
55
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
56
index XXXXXXX..XXXXXXX 100644
57
--- a/tcg/tcg-op.c
58
+++ b/tcg/tcg-op.c
59
@@ -XXX,XX +XXX,XX @@ void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg,
60
tcg_gen_sari_i32(ret, ret, 32 - len);
61
}
46
}
62
47
diff --git a/tests/tcg/riscv64/noexec.c b/tests/tcg/riscv64/noexec.c
63
+/*
48
new file mode 100644
64
+ * Extract 32-bits from a 64-bit input, ah:al, starting from ofs.
49
index XXXXXXX..XXXXXXX
65
+ * Unlike tcg_gen_extract_i32 above, len is fixed at 32.
50
--- /dev/null
66
+ */
51
+++ b/tests/tcg/riscv64/noexec.c
67
+void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah,
52
@@ -XXX,XX +XXX,XX @@
68
+ unsigned int ofs)
53
+#include "../multiarch/noexec.c.inc"
54
+
55
+static void *arch_mcontext_pc(const mcontext_t *ctx)
69
+{
56
+{
70
+ tcg_debug_assert(ofs <= 32);
57
+ return (void *)ctx->__gregs[REG_PC];
71
+ if (ofs == 0) {
72
+ tcg_gen_mov_i32(ret, al);
73
+ } else if (ofs == 32) {
74
+ tcg_gen_mov_i32(ret, ah);
75
+ } else if (al == ah) {
76
+ tcg_gen_rotri_i32(ret, al, ofs);
77
+ } else {
78
+ TCGv_i32 t0 = tcg_temp_new_i32();
79
+ tcg_gen_shri_i32(t0, al, ofs);
80
+ tcg_gen_deposit_i32(ret, t0, ah, 32 - ofs, ofs);
81
+ tcg_temp_free_i32(t0);
82
+ }
83
+}
58
+}
84
+
59
+
85
void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1,
60
+static int arch_mcontext_arg(const mcontext_t *ctx)
86
TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2)
87
{
88
@@ -XXX,XX +XXX,XX @@ void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg,
89
tcg_gen_sari_i64(ret, ret, 64 - len);
90
}
91
92
+/*
93
+ * Extract 64 bits from a 128-bit input, ah:al, starting from ofs.
94
+ * Unlike tcg_gen_extract_i64 above, len is fixed at 64.
95
+ */
96
+void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah,
97
+ unsigned int ofs)
98
+{
61
+{
99
+ tcg_debug_assert(ofs <= 64);
62
+ return ctx->__gregs[REG_A0];
100
+ if (ofs == 0) {
101
+ tcg_gen_mov_i64(ret, al);
102
+ } else if (ofs == 64) {
103
+ tcg_gen_mov_i64(ret, ah);
104
+ } else if (al == ah) {
105
+ tcg_gen_rotri_i64(ret, al, ofs);
106
+ } else {
107
+ TCGv_i64 t0 = tcg_temp_new_i64();
108
+ tcg_gen_shri_i64(t0, al, ofs);
109
+ tcg_gen_deposit_i64(ret, t0, ah, 64 - ofs, ofs);
110
+ tcg_temp_free_i64(t0);
111
+ }
112
+}
63
+}
113
+
64
+
114
void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1,
65
+static void arch_flush(void *p, int len)
115
TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2)
66
+{
116
{
67
+ __builtin___clear_cache(p, p + len);
68
+}
69
+
70
+extern char noexec_1[];
71
+extern char noexec_2[];
72
+extern char noexec_end[];
73
+
74
+asm(".option push\n"
75
+ ".option norvc\n"
76
+ "noexec_1:\n"
77
+ " li a0,1\n" /* a0 is 0 on entry, set 1. */
78
+ "noexec_2:\n"
79
+ " li a0,2\n" /* a0 is 0/1; set 2. */
80
+ " ret\n"
81
+ "noexec_end:\n"
82
+ ".option pop");
83
+
84
+int main(void)
85
+{
86
+ struct noexec_test noexec_tests[] = {
87
+ {
88
+ .name = "fallthrough",
89
+ .test_code = noexec_1,
90
+ .test_len = noexec_end - noexec_1,
91
+ .page_ofs = noexec_1 - noexec_2,
92
+ .entry_ofs = noexec_1 - noexec_2,
93
+ .expected_si_ofs = 0,
94
+ .expected_pc_ofs = 0,
95
+ .expected_arg = 1,
96
+ },
97
+ {
98
+ .name = "jump",
99
+ .test_code = noexec_1,
100
+ .test_len = noexec_end - noexec_1,
101
+ .page_ofs = noexec_1 - noexec_2,
102
+ .entry_ofs = 0,
103
+ .expected_si_ofs = 0,
104
+ .expected_pc_ofs = 0,
105
+ .expected_arg = 0,
106
+ },
107
+ {
108
+ .name = "fallthrough [cross]",
109
+ .test_code = noexec_1,
110
+ .test_len = noexec_end - noexec_1,
111
+ .page_ofs = noexec_1 - noexec_2 - 2,
112
+ .entry_ofs = noexec_1 - noexec_2 - 2,
113
+ .expected_si_ofs = 0,
114
+ .expected_pc_ofs = -2,
115
+ .expected_arg = 1,
116
+ },
117
+ {
118
+ .name = "jump [cross]",
119
+ .test_code = noexec_1,
120
+ .test_len = noexec_end - noexec_1,
121
+ .page_ofs = noexec_1 - noexec_2 - 2,
122
+ .entry_ofs = -2,
123
+ .expected_si_ofs = 0,
124
+ .expected_pc_ofs = -2,
125
+ .expected_arg = 0,
126
+ },
127
+ };
128
+
129
+ return test_noexec(noexec_tests,
130
+ sizeof(noexec_tests) / sizeof(noexec_tests[0]));
131
+}
132
diff --git a/tests/tcg/riscv64/Makefile.target b/tests/tcg/riscv64/Makefile.target
133
index XXXXXXX..XXXXXXX 100644
134
--- a/tests/tcg/riscv64/Makefile.target
135
+++ b/tests/tcg/riscv64/Makefile.target
136
@@ -XXX,XX +XXX,XX @@
137
138
VPATH += $(SRC_PATH)/tests/tcg/riscv64
139
TESTS += test-div
140
+TESTS += noexec
117
--
141
--
118
2.17.1
142
2.34.1
119
120
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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