[Qemu-devel] [PULL 00/15] tcg patch queue
[PULL 00/24] tcg patch queue
1
The following changes since commit 3284aa128153750f14a61e8a96fd085e6f2999b6:
1
The following changes since commit 6587b0c1331d427b0939c37e763842550ed581db:
2
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3
Merge remote-tracking branch 'remotes/lersek/tags/edk2-pull-2019-04-22' into staging (2019-04-24 13:19:41 +0100)
3
Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2021-10-15' into staging (2021-10-15 14:16:28 -0700)
4
4
5
are available in the Git repository at:
5
are available in the Git repository at:
6
6
7
https://github.com/rth7680/qemu.git tags/pull-tcg-20190426
7
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20211016
8
8
9
for you to fetch changes up to ef5dae6805cce7b59d129d801bdc5db71bcbd60d:
9
for you to fetch changes up to 995b87dedc78b0467f5f18bbc3546072ba97516a:
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10
11
cputlb: Fix io_readx() to respect the access_type (2019-04-25 10:40:06 -0700)
11
Revert "cpu: Move cpu_common_props to hw/core/cpu.c" (2021-10-15 16:39:15 -0700)
12
12
13
----------------------------------------------------------------
13
----------------------------------------------------------------
14
Add tcg_gen_extract2_*.
14
Move gdb singlestep to generic code
15
Deal with overflow of TranslationBlocks.
15
Fix cpu_common_props
16
Respect access_type in io_readx.
17
16
18
----------------------------------------------------------------
17
----------------------------------------------------------------
19
David Hildenbrand (1):
18
Richard Henderson (24):
20
tcg: Implement tcg_gen_extract2_{i32,i64}
19
accel/tcg: Handle gdb singlestep in cpu_tb_exec
20
target/alpha: Drop checks for singlestep_enabled
21
target/avr: Drop checks for singlestep_enabled
22
target/cris: Drop checks for singlestep_enabled
23
target/hexagon: Drop checks for singlestep_enabled
24
target/arm: Drop checks for singlestep_enabled
25
target/hppa: Drop checks for singlestep_enabled
26
target/i386: Check CF_NO_GOTO_TB for dc->jmp_opt
27
target/i386: Drop check for singlestep_enabled
28
target/m68k: Drop checks for singlestep_enabled
29
target/microblaze: Check CF_NO_GOTO_TB for DISAS_JUMP
30
target/microblaze: Drop checks for singlestep_enabled
31
target/mips: Fix single stepping
32
target/mips: Drop exit checks for singlestep_enabled
33
target/openrisc: Drop checks for singlestep_enabled
34
target/ppc: Drop exit checks for singlestep_enabled
35
target/riscv: Remove dead code after exception
36
target/riscv: Remove exit_tb and lookup_and_goto_ptr
37
target/rx: Drop checks for singlestep_enabled
38
target/s390x: Drop check for singlestep_enabled
39
target/sh4: Drop check for singlestep_enabled
40
target/tricore: Drop check for singlestep_enabled
41
target/xtensa: Drop check for singlestep_enabled
42
Revert "cpu: Move cpu_common_props to hw/core/cpu.c"
21
43
22
Richard Henderson (13):
44
include/hw/core/cpu.h | 1 +
23
tcg: Add INDEX_op_extract2_{i32,i64}
45
target/i386/helper.h | 1 -
24
tcg: Use deposit and extract2 in tcg_gen_shifti_i64
46
target/rx/helper.h | 1 -
25
tcg: Use extract2 in tcg_gen_deposit_{i32,i64}
47
target/sh4/helper.h | 1 -
26
tcg/i386: Support INDEX_op_extract2_{i32,i64}
48
target/tricore/helper.h | 1 -
27
tcg/arm: Support INDEX_op_extract2_i32
49
accel/tcg/cpu-exec.c | 11 ++++
28
tcg/aarch64: Support INDEX_op_extract2_{i32,i64}
50
cpu.c | 21 ++++++++
29
tcg: Hoist max_insns computation to tb_gen_code
51
hw/core/cpu-common.c | 17 +-----
30
tcg: Restart after TB code generation overflow
52
target/alpha/translate.c | 13 ++---
31
tcg: Restart TB generation after relocation overflow
53
target/arm/translate-a64.c | 10 +---
32
tcg: Restart TB generation after constant pool overflow
54
target/arm/translate.c | 36 +++----------
33
tcg: Restart TB generation after out-of-line ldst overflow
55
target/avr/translate.c | 19 ++-----
34
tcg/ppc: Allow the constant pool to overflow at 32k
56
target/cris/translate.c | 16 ------
35
tcg/arm: Restrict constant pool displacement to 12 bits
57
target/hexagon/translate.c | 12 +----
58
target/hppa/translate.c | 17 ++----
59
target/i386/tcg/misc_helper.c | 8 ---
60
target/i386/tcg/translate.c | 9 ++--
61
target/m68k/translate.c | 44 ++++-----------
62
target/microblaze/translate.c | 18 ++-----
63
target/mips/tcg/translate.c | 75 ++++++++++++--------------
64
target/openrisc/translate.c | 18 ++-----
65
target/ppc/translate.c | 38 +++----------
66
target/riscv/translate.c | 27 +---------
67
target/rx/op_helper.c | 8 ---
68
target/rx/translate.c | 12 +----
69
target/s390x/tcg/translate.c | 8 +--
70
target/sh4/op_helper.c | 5 --
71
target/sh4/translate.c | 14 ++---
72
target/tricore/op_helper.c | 7 ---
73
target/tricore/translate.c | 14 +----
74
target/xtensa/translate.c | 25 +++------
75
target/riscv/insn_trans/trans_privileged.c.inc | 10 ++--
76
target/riscv/insn_trans/trans_rvi.c.inc | 8 ++-
77
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
78
34 files changed, 141 insertions(+), 386 deletions(-)
36
79
37
Shahab Vahedi (1):
38
cputlb: Fix io_readx() to respect the access_type
39
40
include/exec/exec-all.h | 4 +-
41
include/exec/translator.h | 3 +-
42
tcg/aarch64/tcg-target.h | 2 +
43
tcg/arm/tcg-target.h | 1 +
44
tcg/i386/tcg-target.h | 2 +
45
tcg/mips/tcg-target.h | 2 +
46
tcg/ppc/tcg-target.h | 2 +
47
tcg/riscv/tcg-target.h | 2 +
48
tcg/s390/tcg-target.h | 2 +
49
tcg/sparc/tcg-target.h | 2 +
50
tcg/tcg-op.h | 6 ++
51
tcg/tcg-opc.h | 2 +
52
tcg/tcg.h | 16 +++---
53
tcg/tci/tcg-target.h | 2 +
54
accel/tcg/cputlb.c | 5 +-
55
accel/tcg/translate-all.c | 53 ++++++++++++++---
56
accel/tcg/translator.c | 15 +----
57
target/alpha/translate.c | 4 +-
58
target/arm/translate.c | 4 +-
59
target/cris/translate.c | 10 +---
60
target/hppa/translate.c | 5 +-
61
target/i386/translate.c | 4 +-
62
target/lm32/translate.c | 10 +---
63
target/m68k/translate.c | 4 +-
64
target/microblaze/translate.c | 10 +---
65
target/mips/translate.c | 4 +-
66
target/moxie/translate.c | 11 +---
67
target/nios2/translate.c | 14 +----
68
target/openrisc/translate.c | 4 +-
69
target/ppc/translate.c | 4 +-
70
target/riscv/translate.c | 4 +-
71
target/s390x/translate.c | 4 +-
72
target/sh4/translate.c | 4 +-
73
target/sparc/translate.c | 4 +-
74
target/tilegx/translate.c | 12 +---
75
target/tricore/translate.c | 16 +-----
76
target/unicore32/translate.c | 10 +---
77
target/xtensa/translate.c | 4 +-
78
tcg/aarch64/tcg-target.inc.c | 27 +++++++--
79
tcg/arm/tcg-target.inc.c | 98 ++++++++++++++++++--------------
80
tcg/i386/tcg-target.inc.c | 17 +++++-
81
tcg/mips/tcg-target.inc.c | 6 +-
82
tcg/optimize.c | 16 ++++++
83
tcg/ppc/tcg-target.inc.c | 42 +++++++-------
84
tcg/riscv/tcg-target.inc.c | 16 ++++--
85
tcg/s390/tcg-target.inc.c | 20 ++++---
86
tcg/tcg-ldst.inc.c | 18 +++---
87
tcg/tcg-op.c | 129 +++++++++++++++++++++++++++++++++---------
88
tcg/tcg-pool.inc.c | 12 ++--
89
tcg/tcg.c | 85 +++++++++++++++-------------
90
tcg/README | 7 +++
91
51 files changed, 451 insertions(+), 309 deletions(-)
92
diff view generated by jsdifflib
New patch
[PULL 01/24] accel/tcg: Handle gdb singlestep in cpu_tb_exec
1
Currently the change in cpu_tb_exec is masked by the debug exception
2
being raised by the translators. But this allows us to remove that code.
1
3
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
accel/tcg/cpu-exec.c | 11 +++++++++++
7
1 file changed, 11 insertions(+)
8
9
diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/accel/tcg/cpu-exec.c
12
+++ b/accel/tcg/cpu-exec.c
13
@@ -XXX,XX +XXX,XX @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
14
cc->set_pc(cpu, last_tb->pc);
15
}
16
}
17
+
18
+ /*
19
+ * If gdb single-step, and we haven't raised another exception,
20
+ * raise a debug exception. Single-step with another exception
21
+ * is handled in cpu_handle_exception.
22
+ */
23
+ if (unlikely(cpu->singlestep_enabled) && cpu->exception_index == -1) {
24
+ cpu->exception_index = EXCP_DEBUG;
25
+ cpu_loop_exit(cpu);
26
+ }
27
+
28
return last_tb;
29
}
30
31
--
32
2.25.1
33
34
diff view generated by jsdifflib
New patch
[PULL 02/24] target/alpha: Drop checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/alpha/translate.c | 13 +++----------
7
1 file changed, 3 insertions(+), 10 deletions(-)
8
9
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/alpha/translate.c
12
+++ b/target/alpha/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void alpha_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
14
tcg_gen_movi_i64(cpu_pc, ctx->base.pc_next);
15
/* FALLTHRU */
16
case DISAS_PC_UPDATED:
17
- if (!ctx->base.singlestep_enabled) {
18
- tcg_gen_lookup_and_goto_ptr();
19
- break;
20
- }
21
- /* FALLTHRU */
22
+ tcg_gen_lookup_and_goto_ptr();
23
+ break;
24
case DISAS_PC_UPDATED_NOCHAIN:
25
- if (ctx->base.singlestep_enabled) {
26
- gen_excp_1(EXCP_DEBUG, 0);
27
- } else {
28
- tcg_gen_exit_tb(NULL, 0);
29
- }
30
+ tcg_gen_exit_tb(NULL, 0);
31
break;
32
default:
33
g_assert_not_reached();
34
--
35
2.25.1
36
37
diff view generated by jsdifflib
New patch
[PULL 03/24] target/avr: Drop checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Tested-by: Michael Rolnik <mrolnik@gmail.com>
4
Reviewed-by: Michael Rolnik <mrolnik@gmail.com>
5
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
target/avr/translate.c | 19 ++++---------------
9
1 file changed, 4 insertions(+), 15 deletions(-)
10
11
diff --git a/target/avr/translate.c b/target/avr/translate.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/avr/translate.c
14
+++ b/target/avr/translate.c
15
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
16
tcg_gen_exit_tb(tb, n);
17
} else {
18
tcg_gen_movi_i32(cpu_pc, dest);
19
- if (ctx->base.singlestep_enabled) {
20
- gen_helper_debug(cpu_env);
21
- } else {
22
- tcg_gen_lookup_and_goto_ptr();
23
- }
24
+ tcg_gen_lookup_and_goto_ptr();
25
}
26
ctx->base.is_jmp = DISAS_NORETURN;
27
}
28
@@ -XXX,XX +XXX,XX @@ static void avr_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
29
tcg_gen_movi_tl(cpu_pc, ctx->npc);
30
/* fall through */
31
case DISAS_LOOKUP:
32
- if (!ctx->base.singlestep_enabled) {
33
- tcg_gen_lookup_and_goto_ptr();
34
- break;
35
- }
36
- /* fall through */
37
+ tcg_gen_lookup_and_goto_ptr();
38
+ break;
39
case DISAS_EXIT:
40
- if (ctx->base.singlestep_enabled) {
41
- gen_helper_debug(cpu_env);
42
- } else {
43
- tcg_gen_exit_tb(NULL, 0);
44
- }
45
+ tcg_gen_exit_tb(NULL, 0);
46
break;
47
default:
48
g_assert_not_reached();
49
--
50
2.25.1
51
52
diff view generated by jsdifflib
New patch
[PULL 04/24] target/cris: Drop checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
target/cris/translate.c | 16 ----------------
6
1 file changed, 16 deletions(-)
7
8
diff --git a/target/cris/translate.c b/target/cris/translate.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/target/cris/translate.c
11
+++ b/target/cris/translate.c
12
@@ -XXX,XX +XXX,XX @@ static void cris_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
13
}
14
}
15
16
- if (unlikely(dc->base.singlestep_enabled)) {
17
- switch (is_jmp) {
18
- case DISAS_TOO_MANY:
19
- case DISAS_UPDATE_NEXT:
20
- tcg_gen_movi_tl(env_pc, npc);
21
- /* fall through */
22
- case DISAS_JUMP:
23
- case DISAS_UPDATE:
24
- t_gen_raise_exception(EXCP_DEBUG);
25
- return;
26
- default:
27
- break;
28
- }
29
- g_assert_not_reached();
30
- }
31
-
32
switch (is_jmp) {
33
case DISAS_TOO_MANY:
34
gen_goto_tb(dc, 0, npc);
35
--
36
2.25.1
37
38
diff view generated by jsdifflib
New patch
[PULL 05/24] target/hexagon: Drop checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/hexagon/translate.c | 12 ++----------
7
1 file changed, 2 insertions(+), 10 deletions(-)
8
9
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/hexagon/translate.c
12
+++ b/target/hexagon/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void gen_end_tb(DisasContext *ctx)
14
{
15
gen_exec_counters(ctx);
16
tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC);
17
- if (ctx->base.singlestep_enabled) {
18
- gen_exception_raw(EXCP_DEBUG);
19
- } else {
20
- tcg_gen_exit_tb(NULL, 0);
21
- }
22
+ tcg_gen_exit_tb(NULL, 0);
23
ctx->base.is_jmp = DISAS_NORETURN;
24
}
25
26
@@ -XXX,XX +XXX,XX @@ static void hexagon_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
27
case DISAS_TOO_MANY:
28
gen_exec_counters(ctx);
29
tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next);
30
- if (ctx->base.singlestep_enabled) {
31
- gen_exception_raw(EXCP_DEBUG);
32
- } else {
33
- tcg_gen_exit_tb(NULL, 0);
34
- }
35
+ tcg_gen_exit_tb(NULL, 0);
36
break;
37
case DISAS_NORETURN:
38
break;
39
--
40
2.25.1
41
42
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/15] tcg: Restart TB generation after constant pool overflow
[PULL 06/24] target/arm: Drop checks for singlestep_enabled
1
This is part b of relocation overflow handling.
1
GDB single-stepping is now handled generically.
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
4
---
5
tcg/tcg-pool.inc.c | 12 +++++++-----
5
target/arm/translate-a64.c | 10 ++--------
6
tcg/tcg.c | 9 +++++----
6
target/arm/translate.c | 36 ++++++------------------------------
7
2 files changed, 12 insertions(+), 9 deletions(-)
7
2 files changed, 8 insertions(+), 38 deletions(-)
8
8
9
diff --git a/tcg/tcg-pool.inc.c b/tcg/tcg-pool.inc.c
9
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
10
index XXXXXXX..XXXXXXX 100644
10
index XXXXXXX..XXXXXXX 100644
11
--- a/tcg/tcg-pool.inc.c
11
--- a/target/arm/translate-a64.c
12
+++ b/tcg/tcg-pool.inc.c
12
+++ b/target/arm/translate-a64.c
13
@@ -XXX,XX +XXX,XX @@ static inline void new_pool_l8(TCGContext *s, int rtype, tcg_insn_unit *label,
13
@@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
14
/* To be provided by cpu/tcg-target.inc.c. */
14
gen_a64_set_pc_im(dest);
15
static void tcg_out_nop_fill(tcg_insn_unit *p, int count);
15
if (s->ss_active) {
16
16
gen_step_complete_exception(s);
17
-static bool tcg_out_pool_finalize(TCGContext *s)
17
- } else if (s->base.singlestep_enabled) {
18
+static int tcg_out_pool_finalize(TCGContext *s)
18
- gen_exception_internal(EXCP_DEBUG);
19
} else {
20
tcg_gen_lookup_and_goto_ptr();
21
s->base.is_jmp = DISAS_NORETURN;
22
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
19
{
23
{
20
TCGLabelPoolData *p = s->pool_labels;
24
DisasContext *dc = container_of(dcbase, DisasContext, base);
21
TCGLabelPoolData *l = NULL;
25
22
void *a;
26
- if (unlikely(dc->base.singlestep_enabled || dc->ss_active)) {
23
27
+ if (unlikely(dc->ss_active)) {
24
if (p == NULL) {
28
/* Note that this means single stepping WFI doesn't halt the CPU.
25
- return true;
29
* For conditional branch insns this is harmless unreachable code as
26
+ return 0;
30
* gen_goto_tb() has already handled emitting the debug exception
31
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
32
/* fall through */
33
case DISAS_EXIT:
34
case DISAS_JUMP:
35
- if (dc->base.singlestep_enabled) {
36
- gen_exception_internal(EXCP_DEBUG);
37
- } else {
38
- gen_step_complete_exception(dc);
39
- }
40
+ gen_step_complete_exception(dc);
41
break;
42
case DISAS_NORETURN:
43
break;
44
diff --git a/target/arm/translate.c b/target/arm/translate.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/translate.c
47
+++ b/target/arm/translate.c
48
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal(int excp)
49
tcg_temp_free_i32(tcg_excp);
50
}
51
52
-static void gen_step_complete_exception(DisasContext *s)
53
+static void gen_singlestep_exception(DisasContext *s)
54
{
55
/* We just completed step of an insn. Move from Active-not-pending
56
* to Active-pending, and then also take the swstep exception.
57
@@ -XXX,XX +XXX,XX @@ static void gen_step_complete_exception(DisasContext *s)
58
s->base.is_jmp = DISAS_NORETURN;
59
}
60
61
-static void gen_singlestep_exception(DisasContext *s)
62
-{
63
- /* Generate the right kind of exception for singlestep, which is
64
- * either the architectural singlestep or EXCP_DEBUG for QEMU's
65
- * gdb singlestepping.
66
- */
67
- if (s->ss_active) {
68
- gen_step_complete_exception(s);
69
- } else {
70
- gen_exception_internal(EXCP_DEBUG);
71
- }
72
-}
73
-
74
-static inline bool is_singlestepping(DisasContext *s)
75
-{
76
- /* Return true if we are singlestepping either because of
77
- * architectural singlestep or QEMU gdbstub singlestep. This does
78
- * not include the command line '-singlestep' mode which is rather
79
- * misnamed as it only means "one instruction per TB" and doesn't
80
- * affect the code we generate.
81
- */
82
- return s->base.singlestep_enabled || s->ss_active;
83
-}
84
-
85
void clear_eci_state(DisasContext *s)
86
{
87
/*
88
@@ -XXX,XX +XXX,XX @@ static inline void gen_bx_excret_final_code(DisasContext *s)
89
/* Is the new PC value in the magic range indicating exception return? */
90
tcg_gen_brcondi_i32(TCG_COND_GEU, cpu_R[15], min_magic, excret_label);
91
/* No: end the TB as we would for a DISAS_JMP */
92
- if (is_singlestepping(s)) {
93
+ if (s->ss_active) {
94
gen_singlestep_exception(s);
95
} else {
96
tcg_gen_exit_tb(NULL, 0);
97
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *s, int n, target_ulong dest)
98
/* Jump, specifying which TB number to use if we gen_goto_tb() */
99
static inline void gen_jmp_tb(DisasContext *s, uint32_t dest, int tbno)
100
{
101
- if (unlikely(is_singlestepping(s))) {
102
+ if (unlikely(s->ss_active)) {
103
/* An indirect jump so that we still trigger the debug exception. */
104
gen_set_pc_im(s, dest);
105
s->base.is_jmp = DISAS_JUMP;
106
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
107
dc->page_start = dc->base.pc_first & TARGET_PAGE_MASK;
108
109
/* If architectural single step active, limit to 1. */
110
- if (is_singlestepping(dc)) {
111
+ if (dc->ss_active) {
112
dc->base.max_insns = 1;
27
}
113
}
28
114
29
/* ??? Round up to qemu_icache_linesize, but then do not round
115
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
30
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_pool_finalize(TCGContext *s)
116
* insn codepath itself.
31
size_t size = sizeof(tcg_target_ulong) * p->nlong;
117
*/
32
if (!l || l->nlong != p->nlong || memcmp(l->data, p->data, size)) {
118
gen_bx_excret_final_code(dc);
33
if (unlikely(a > s->code_gen_highwater)) {
119
- } else if (unlikely(is_singlestepping(dc))) {
34
- return false;
120
+ } else if (unlikely(dc->ss_active)) {
35
+ return -1;
121
/* Unconditional and "condition passed" instruction codepath. */
36
}
122
switch (dc->base.is_jmp) {
37
memcpy(a, p->data, size);
123
case DISAS_SWI:
38
a += size;
124
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
39
l = p;
125
/* "Condition failed" instruction codepath for the branch/trap insn */
40
}
126
gen_set_label(dc->condlabel);
41
- patch_reloc(p->label, p->rtype, (intptr_t)a - size, p->addend);
127
gen_set_condexec(dc);
42
+ if (!patch_reloc(p->label, p->rtype, (intptr_t)a - size, p->addend)) {
128
- if (unlikely(is_singlestepping(dc))) {
43
+ return -2;
129
+ if (unlikely(dc->ss_active)) {
44
+ }
130
gen_set_pc_im(dc, dc->base.pc_next);
45
}
131
gen_singlestep_exception(dc);
46
132
} else {
47
s->code_ptr = a;
48
- return true;
49
+ return 0;
50
}
51
diff --git a/tcg/tcg.c b/tcg/tcg.c
52
index XXXXXXX..XXXXXXX 100644
53
--- a/tcg/tcg.c
54
+++ b/tcg/tcg.c
55
@@ -XXX,XX +XXX,XX @@ void tcg_prologue_init(TCGContext *s)
56
#ifdef TCG_TARGET_NEED_POOL_LABELS
57
/* Allow the prologue to put e.g. guest_base into a pool entry. */
58
{
59
- bool ok = tcg_out_pool_finalize(s);
60
- tcg_debug_assert(ok);
61
+ int result = tcg_out_pool_finalize(s);
62
+ tcg_debug_assert(result == 0);
63
}
64
#endif
65
66
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
67
}
68
#endif
69
#ifdef TCG_TARGET_NEED_POOL_LABELS
70
- if (!tcg_out_pool_finalize(s)) {
71
- return -1;
72
+ i = tcg_out_pool_finalize(s);
73
+ if (i < 0) {
74
+ return i;
75
}
76
#endif
77
if (!tcg_resolve_relocs(s)) {
78
--
133
--
79
2.17.1
134
2.25.1
80
135
81
136
diff view generated by jsdifflib
New patch
[PULL 07/24] target/hppa: Drop checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/hppa/translate.c | 17 ++++-------------
7
1 file changed, 4 insertions(+), 13 deletions(-)
8
9
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/hppa/translate.c
12
+++ b/target/hppa/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int which,
14
} else {
15
copy_iaoq_entry(cpu_iaoq_f, f, cpu_iaoq_b);
16
copy_iaoq_entry(cpu_iaoq_b, b, ctx->iaoq_n_var);
17
- if (ctx->base.singlestep_enabled) {
18
- gen_excp_1(EXCP_DEBUG);
19
- } else {
20
- tcg_gen_lookup_and_goto_ptr();
21
- }
22
+ tcg_gen_lookup_and_goto_ptr();
23
}
24
}
25
26
@@ -XXX,XX +XXX,XX @@ static bool do_rfi(DisasContext *ctx, bool rfi_r)
27
gen_helper_rfi(cpu_env);
28
}
29
/* Exit the TB to recognize new interrupts. */
30
- if (ctx->base.singlestep_enabled) {
31
- gen_excp_1(EXCP_DEBUG);
32
- } else {
33
- tcg_gen_exit_tb(NULL, 0);
34
- }
35
+ tcg_gen_exit_tb(NULL, 0);
36
ctx->base.is_jmp = DISAS_NORETURN;
37
38
return nullify_end(ctx);
39
@@ -XXX,XX +XXX,XX @@ static void hppa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
40
nullify_save(ctx);
41
/* FALLTHRU */
42
case DISAS_IAQ_N_UPDATED:
43
- if (ctx->base.singlestep_enabled) {
44
- gen_excp_1(EXCP_DEBUG);
45
- } else if (is_jmp != DISAS_IAQ_N_STALE_EXIT) {
46
+ if (is_jmp != DISAS_IAQ_N_STALE_EXIT) {
47
tcg_gen_lookup_and_goto_ptr();
48
+ break;
49
}
50
/* FALLTHRU */
51
case DISAS_EXIT:
52
--
53
2.25.1
54
55
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/15] cputlb: Fix io_readx() to respect the access_type
[PULL 08/24] target/i386: Check CF_NO_GOTO_TB for dc->jmp_opt
1
From: Shahab Vahedi <shahab.vahedi@gmail.com>
1
We were using singlestep_enabled as a proxy for whether
2
translator_use_goto_tb would always return false.
2
3
3
This change adapts io_readx() to its input access_type. Currently
4
io_readx() treats any memory access as a read, although it has an
5
input argument "MMUAccessType access_type". This results in:
6
7
1) Calling the tlb_fill() only with MMU_DATA_LOAD
8
2) Considering only entry->addr_read as the tlb_addr
9
10
Buglink: https://bugs.launchpad.net/qemu/+bug/1825359
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Shahab Vahedi <shahab.vahedi@gmail.com>
13
Message-Id: <20190420072236.12347-1-shahab.vahedi@gmail.com>
14
[rth: Remove assert; fix expression formatting.]
15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
16
---
5
---
17
accel/tcg/cputlb.c | 5 +++--
6
target/i386/tcg/translate.c | 5 +++--
18
1 file changed, 3 insertions(+), 2 deletions(-)
7
1 file changed, 3 insertions(+), 2 deletions(-)
19
8
20
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
9
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
21
index XXXXXXX..XXXXXXX 100644
10
index XXXXXXX..XXXXXXX 100644
22
--- a/accel/tcg/cputlb.c
11
--- a/target/i386/tcg/translate.c
23
+++ b/accel/tcg/cputlb.c
12
+++ b/target/i386/tcg/translate.c
24
@@ -XXX,XX +XXX,XX @@ static uint64_t io_readx(CPUArchState *env, CPUIOTLBEntry *iotlbentry,
13
@@ -XXX,XX +XXX,XX @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
25
CPUTLBEntry *entry;
14
DisasContext *dc = container_of(dcbase, DisasContext, base);
26
target_ulong tlb_addr;
15
CPUX86State *env = cpu->env_ptr;
27
16
uint32_t flags = dc->base.tb->flags;
28
- tlb_fill(cpu, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr);
17
+ uint32_t cflags = tb_cflags(dc->base.tb);
29
+ tlb_fill(cpu, addr, size, access_type, mmu_idx, retaddr);
18
int cpl = (flags >> HF_CPL_SHIFT) & 3;
30
19
int iopl = (flags >> IOPL_SHIFT) & 3;
31
entry = tlb_entry(env, mmu_idx, addr);
20
32
- tlb_addr = entry->addr_read;
21
@@ -XXX,XX +XXX,XX @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
33
+ tlb_addr = (access_type == MMU_DATA_LOAD ?
22
dc->cpuid_ext3_features = env->features[FEAT_8000_0001_ECX];
34
+ entry->addr_read : entry->addr_code);
23
dc->cpuid_7_0_ebx_features = env->features[FEAT_7_0_EBX];
35
if (!(tlb_addr & ~(TARGET_PAGE_MASK | TLB_RECHECK))) {
24
dc->cpuid_xsave_features = env->features[FEAT_XSAVE];
36
/* RAM access */
25
- dc->jmp_opt = !(dc->base.singlestep_enabled ||
37
uintptr_t haddr = addr + entry->addend;
26
+ dc->jmp_opt = !((cflags & CF_NO_GOTO_TB) ||
27
(flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK)));
28
/*
29
* If jmp_opt, we want to handle each string instruction individually.
30
* For icount also disable repz optimization so that each iteration
31
* is accounted separately.
32
*/
33
- dc->repz_opt = !dc->jmp_opt && !(tb_cflags(dc->base.tb) & CF_USE_ICOUNT);
34
+ dc->repz_opt = !dc->jmp_opt && !(cflags & CF_USE_ICOUNT);
35
36
dc->T0 = tcg_temp_new();
37
dc->T1 = tcg_temp_new();
38
--
38
--
39
2.17.1
39
2.25.1
40
40
41
41
diff view generated by jsdifflib
New patch
[PULL 09/24] target/i386: Drop check for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
target/i386/helper.h | 1 -
6
target/i386/tcg/misc_helper.c | 8 --------
7
target/i386/tcg/translate.c | 4 +---
8
3 files changed, 1 insertion(+), 12 deletions(-)
9
10
diff --git a/target/i386/helper.h b/target/i386/helper.h
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/i386/helper.h
13
+++ b/target/i386/helper.h
14
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(syscall, void, env, int)
15
DEF_HELPER_2(sysret, void, env, int)
16
#endif
17
DEF_HELPER_FLAGS_2(pause, TCG_CALL_NO_WG, noreturn, env, int)
18
-DEF_HELPER_FLAGS_1(debug, TCG_CALL_NO_WG, noreturn, env)
19
DEF_HELPER_1(reset_rf, void, env)
20
DEF_HELPER_FLAGS_3(raise_interrupt, TCG_CALL_NO_WG, noreturn, env, int, int)
21
DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, int)
22
diff --git a/target/i386/tcg/misc_helper.c b/target/i386/tcg/misc_helper.c
23
index XXXXXXX..XXXXXXX 100644
24
--- a/target/i386/tcg/misc_helper.c
25
+++ b/target/i386/tcg/misc_helper.c
26
@@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN helper_pause(CPUX86State *env, int next_eip_addend)
27
do_pause(env);
28
}
29
30
-void QEMU_NORETURN helper_debug(CPUX86State *env)
31
-{
32
- CPUState *cs = env_cpu(env);
33
-
34
- cs->exception_index = EXCP_DEBUG;
35
- cpu_loop_exit(cs);
36
-}
37
-
38
uint64_t helper_rdpkru(CPUX86State *env, uint32_t ecx)
39
{
40
if ((env->cr[4] & CR4_PKE_MASK) == 0) {
41
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/i386/tcg/translate.c
44
+++ b/target/i386/tcg/translate.c
45
@@ -XXX,XX +XXX,XX @@ do_gen_eob_worker(DisasContext *s, bool inhibit, bool recheck_tf, bool jr)
46
if (s->base.tb->flags & HF_RF_MASK) {
47
gen_helper_reset_rf(cpu_env);
48
}
49
- if (s->base.singlestep_enabled) {
50
- gen_helper_debug(cpu_env);
51
- } else if (recheck_tf) {
52
+ if (recheck_tf) {
53
gen_helper_rechecking_single_step(cpu_env);
54
tcg_gen_exit_tb(NULL, 0);
55
} else if (s->flags & HF_TF_MASK) {
56
--
57
2.25.1
58
59
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/15] tcg/i386: Support INDEX_op_extract2_{i32, i64}
[PULL 10/24] target/m68k: Drop checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
2
3
Acked-by: Laurent Vivier <laurent@vivier.eu>
1
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2
---
5
---
3
tcg/i386/tcg-target.h | 4 ++--
6
target/m68k/translate.c | 44 +++++++++--------------------------------
4
tcg/i386/tcg-target.inc.c | 11 +++++++++++
7
1 file changed, 9 insertions(+), 35 deletions(-)
5
2 files changed, 13 insertions(+), 2 deletions(-)
6
8
7
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
9
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
8
index XXXXXXX..XXXXXXX 100644
10
index XXXXXXX..XXXXXXX 100644
9
--- a/tcg/i386/tcg-target.h
11
--- a/target/m68k/translate.c
10
+++ b/tcg/i386/tcg-target.h
12
+++ b/target/m68k/translate.c
11
@@ -XXX,XX +XXX,XX @@ extern bool have_avx2;
13
@@ -XXX,XX +XXX,XX @@ static void do_writebacks(DisasContext *s)
12
#define TCG_TARGET_HAS_deposit_i32 1
14
}
13
#define TCG_TARGET_HAS_extract_i32 1
15
}
14
#define TCG_TARGET_HAS_sextract_i32 1
16
15
-#define TCG_TARGET_HAS_extract2_i32 0
17
-static bool is_singlestepping(DisasContext *s)
16
+#define TCG_TARGET_HAS_extract2_i32 1
18
-{
17
#define TCG_TARGET_HAS_movcond_i32 1
19
- /*
18
#define TCG_TARGET_HAS_add2_i32 1
20
- * Return true if we are singlestepping either because of
19
#define TCG_TARGET_HAS_sub2_i32 1
21
- * architectural singlestep or QEMU gdbstub singlestep. This does
20
@@ -XXX,XX +XXX,XX @@ extern bool have_avx2;
22
- * not include the command line '-singlestep' mode which is rather
21
#define TCG_TARGET_HAS_deposit_i64 1
23
- * misnamed as it only means "one instruction per TB" and doesn't
22
#define TCG_TARGET_HAS_extract_i64 1
24
- * affect the code we generate.
23
#define TCG_TARGET_HAS_sextract_i64 0
25
- */
24
-#define TCG_TARGET_HAS_extract2_i64 0
26
- return s->base.singlestep_enabled || s->ss_active;
25
+#define TCG_TARGET_HAS_extract2_i64 1
27
-}
26
#define TCG_TARGET_HAS_movcond_i64 1
28
-
27
#define TCG_TARGET_HAS_add2_i64 1
29
/* is_jmp field values */
28
#define TCG_TARGET_HAS_sub2_i64 1
30
#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
29
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
31
#define DISAS_EXIT DISAS_TARGET_1 /* cpu state was modified dynamically */
30
index XXXXXXX..XXXXXXX 100644
32
@@ -XXX,XX +XXX,XX @@ static void gen_exception(DisasContext *s, uint32_t dest, int nr)
31
--- a/tcg/i386/tcg-target.inc.c
33
s->base.is_jmp = DISAS_NORETURN;
32
+++ b/tcg/i386/tcg-target.inc.c
34
}
33
@@ -XXX,XX +XXX,XX @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
35
34
#define OPC_SHUFPS (0xc6 | P_EXT)
36
-static void gen_singlestep_exception(DisasContext *s)
35
#define OPC_SHLX (0xf7 | P_EXT38 | P_DATA16)
37
-{
36
#define OPC_SHRX (0xf7 | P_EXT38 | P_SIMDF2)
38
- /*
37
+#define OPC_SHRD_Ib (0xac | P_EXT)
39
- * Generate the right kind of exception for singlestep, which is
38
#define OPC_TESTL    (0x85)
40
- * either the architectural singlestep or EXCP_DEBUG for QEMU's
39
#define OPC_TZCNT (0xbc | P_EXT | P_SIMDF3)
41
- * gdb singlestepping.
40
#define OPC_UD2 (0x0b | P_EXT)
42
- */
41
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
43
- if (s->ss_active) {
44
- gen_raise_exception(EXCP_TRACE);
45
- } else {
46
- gen_raise_exception(EXCP_DEBUG);
47
- }
48
-}
49
-
50
static inline void gen_addr_fault(DisasContext *s)
51
{
52
gen_exception(s, s->base.pc_next, EXCP_ADDRESS);
53
@@ -XXX,XX +XXX,XX @@ static void gen_exit_tb(DisasContext *s)
54
/* Generate a jump to an immediate address. */
55
static void gen_jmp_tb(DisasContext *s, int n, uint32_t dest)
56
{
57
- if (unlikely(is_singlestepping(s))) {
58
+ if (unlikely(s->ss_active)) {
59
update_cc_op(s);
60
tcg_gen_movi_i32(QREG_PC, dest);
61
- gen_singlestep_exception(s);
62
+ gen_raise_exception(EXCP_TRACE);
63
} else if (translator_use_goto_tb(&s->base, dest)) {
64
tcg_gen_goto_tb(n);
65
tcg_gen_movi_i32(QREG_PC, dest);
66
@@ -XXX,XX +XXX,XX @@ static void m68k_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu)
67
68
dc->ss_active = (M68K_SR_TRACE(env->sr) == M68K_SR_TRACE_ANY_INS);
69
/* If architectural single step active, limit to 1 */
70
- if (is_singlestepping(dc)) {
71
+ if (dc->ss_active) {
72
dc->base.max_insns = 1;
73
}
74
}
75
@@ -XXX,XX +XXX,XX @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
76
break;
77
case DISAS_TOO_MANY:
78
update_cc_op(dc);
79
- if (is_singlestepping(dc)) {
80
+ if (dc->ss_active) {
81
tcg_gen_movi_i32(QREG_PC, dc->pc);
82
- gen_singlestep_exception(dc);
83
+ gen_raise_exception(EXCP_TRACE);
84
} else {
85
gen_jmp_tb(dc, 0, dc->pc);
42
}
86
}
43
break;
87
break;
44
88
case DISAS_JUMP:
45
+ OP_32_64(extract2):
89
/* We updated CC_OP and PC in gen_jmp/gen_jmp_im. */
46
+ /* Note that SHRD outputs to the r/m operand. */
90
- if (is_singlestepping(dc)) {
47
+ tcg_out_modrm(s, OPC_SHRD_Ib + rexw, a2, a0);
91
- gen_singlestep_exception(dc);
48
+ tcg_out8(s, args[3]);
92
+ if (dc->ss_active) {
49
+ break;
93
+ gen_raise_exception(EXCP_TRACE);
50
+
94
} else {
51
case INDEX_op_mb:
95
tcg_gen_lookup_and_goto_ptr();
52
tcg_out_mb(s, a0);
96
}
53
break;
97
@@ -XXX,XX +XXX,XX @@ static void m68k_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
54
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
98
* We updated CC_OP and PC in gen_exit_tb, but also modified
55
static const TCGTargetOpDef r_0 = { .args_ct_str = { "r", "0" } };
99
* other state that may require returning to the main loop.
56
static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } };
100
*/
57
static const TCGTargetOpDef r_r_re = { .args_ct_str = { "r", "r", "re" } };
101
- if (is_singlestepping(dc)) {
58
+ static const TCGTargetOpDef r_0_r = { .args_ct_str = { "r", "0", "r" } };
102
- gen_singlestep_exception(dc);
59
static const TCGTargetOpDef r_0_re = { .args_ct_str = { "r", "0", "re" } };
103
+ if (dc->ss_active) {
60
static const TCGTargetOpDef r_0_ci = { .args_ct_str = { "r", "0", "ci" } };
104
+ gen_raise_exception(EXCP_TRACE);
61
static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } };
105
} else {
62
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
106
tcg_gen_exit_tb(NULL, 0);
63
case INDEX_op_ctpop_i32:
107
}
64
case INDEX_op_ctpop_i64:
65
return &r_r;
66
+ case INDEX_op_extract2_i32:
67
+ case INDEX_op_extract2_i64:
68
+ return &r_0_r;
69
70
case INDEX_op_deposit_i32:
71
case INDEX_op_deposit_i64:
72
--
108
--
73
2.17.1
109
2.25.1
74
110
75
111
diff view generated by jsdifflib
New patch
[PULL 11/24] target/microblaze: Check CF_NO_GOTO_TB for DISAS_JUMP
1
We were using singlestep_enabled as a proxy for whether
2
translator_use_goto_tb would always return false.
1
3
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
6
target/microblaze/translate.c | 4 ++--
7
1 file changed, 2 insertions(+), 2 deletions(-)
8
9
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
10
index XXXXXXX..XXXXXXX 100644
11
--- a/target/microblaze/translate.c
12
+++ b/target/microblaze/translate.c
13
@@ -XXX,XX +XXX,XX @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)
14
break;
15
16
case DISAS_JUMP:
17
- if (dc->jmp_dest != -1 && !cs->singlestep_enabled) {
18
+ if (dc->jmp_dest != -1 && !(tb_cflags(dc->base.tb) & CF_NO_GOTO_TB)) {
19
/* Direct jump. */
20
tcg_gen_discard_i32(cpu_btarget);
21
22
@@ -XXX,XX +XXX,XX @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)
23
return;
24
}
25
26
- /* Indirect jump (or direct jump w/ singlestep) */
27
+ /* Indirect jump (or direct jump w/ goto_tb disabled) */
28
tcg_gen_mov_i32(cpu_pc, cpu_btarget);
29
tcg_gen_discard_i32(cpu_btarget);
30
31
--
32
2.25.1
33
34
diff view generated by jsdifflib
New patch
[PULL 12/24] target/microblaze: Drop checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
1
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
target/microblaze/translate.c | 14 ++------------
6
1 file changed, 2 insertions(+), 12 deletions(-)
7
8
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
9
index XXXXXXX..XXXXXXX 100644
10
--- a/target/microblaze/translate.c
11
+++ b/target/microblaze/translate.c
12
@@ -XXX,XX +XXX,XX @@ static void gen_raise_hw_excp(DisasContext *dc, uint32_t esr_ec)
13
14
static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
15
{
16
- if (dc->base.singlestep_enabled) {
17
- TCGv_i32 tmp = tcg_const_i32(EXCP_DEBUG);
18
- tcg_gen_movi_i32(cpu_pc, dest);
19
- gen_helper_raise_exception(cpu_env, tmp);
20
- tcg_temp_free_i32(tmp);
21
- } else if (translator_use_goto_tb(&dc->base, dest)) {
22
+ if (translator_use_goto_tb(&dc->base, dest)) {
23
tcg_gen_goto_tb(n);
24
tcg_gen_movi_i32(cpu_pc, dest);
25
tcg_gen_exit_tb(dc->base.tb, n);
26
@@ -XXX,XX +XXX,XX @@ static void mb_tr_tb_stop(DisasContextBase *dcb, CPUState *cs)
27
/* Indirect jump (or direct jump w/ goto_tb disabled) */
28
tcg_gen_mov_i32(cpu_pc, cpu_btarget);
29
tcg_gen_discard_i32(cpu_btarget);
30
-
31
- if (unlikely(cs->singlestep_enabled)) {
32
- gen_raise_exception(dc, EXCP_DEBUG);
33
- } else {
34
- tcg_gen_lookup_and_goto_ptr();
35
- }
36
+ tcg_gen_lookup_and_goto_ptr();
37
return;
38
39
default:
40
--
41
2.25.1
42
43
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/15] tcg/arm: Restrict constant pool displacement to 12 bits
[PULL 13/24] target/mips: Fix single stepping
1
This will not necessarily restrict the size of the TB, since for v7
1
As per an ancient comment in mips_tr_translate_insn about the
2
the majority of constant pool usage is for calls from the out-of-line
2
expectations of gdb, when restarting the insn in a delay slot
3
ldst code, which is already at the end of the TB. But this does
3
we also re-execute the branch. Which means that we are
4
allow us to save one insn per reference on the off-chance.
4
expected to execute two insns in this case.
5
5
6
This has been broken since 8b86d6d2580, where we forced max_insns
7
to 1 while single-stepping. This resulted in an exit from the
8
translator loop after the branch but before the delay slot is
9
translated.
10
11
Increase the max_insns to 2 for this case. In addition, bypass
12
the end-of-page check, for when the branch itself ends the page.
13
14
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
16
---
8
tcg/arm/tcg-target.inc.c | 57 +++++++++++++++-------------------------
17
target/mips/tcg/translate.c | 25 ++++++++++++++++---------
9
1 file changed, 21 insertions(+), 36 deletions(-)
18
1 file changed, 16 insertions(+), 9 deletions(-)
10
19
11
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
20
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
12
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/arm/tcg-target.inc.c
22
--- a/target/mips/tcg/translate.c
14
+++ b/tcg/arm/tcg-target.inc.c
23
+++ b/target/mips/tcg/translate.c
15
@@ -XXX,XX +XXX,XX @@ static inline bool reloc_pc24(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
24
@@ -XXX,XX +XXX,XX @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
16
return false;
25
ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS_R6 |
26
INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN;
27
28
+ /*
29
+ * Execute a branch and its delay slot as a single instruction.
30
+ * This is what GDB expects and is consistent with what the
31
+ * hardware does (e.g. if a delay slot instruction faults, the
32
+ * reported PC is the PC of the branch).
33
+ */
34
+ if (ctx->base.singlestep_enabled && (ctx->hflags & MIPS_HFLAG_BMASK)) {
35
+ ctx->base.max_insns = 2;
36
+ }
37
+
38
LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx,
39
ctx->hflags);
17
}
40
}
18
41
@@ -XXX,XX +XXX,XX @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
19
+static inline bool reloc_pc13(tcg_insn_unit *code_ptr, tcg_insn_unit *target)
42
if (ctx->base.is_jmp != DISAS_NEXT) {
20
+{
43
return;
21
+ ptrdiff_t offset = tcg_ptr_byte_diff(target, code_ptr) - 8;
44
}
22
+
45
+
23
+ if (offset >= -0xfff && offset <= 0xfff) {
46
/*
24
+ tcg_insn_unit insn = *code_ptr;
47
- * Execute a branch and its delay slot as a single instruction.
25
+ bool u = (offset >= 0);
48
- * This is what GDB expects and is consistent with what the
26
+ if (!u) {
49
- * hardware does (e.g. if a delay slot instruction faults, the
27
+ offset = -offset;
50
- * reported PC is the PC of the branch).
28
+ }
51
+ * End the TB on (most) page crossings.
29
+ insn = deposit32(insn, 23, 1, u);
52
+ * See mips_tr_init_disas_context about single-stepping a branch
30
+ insn = deposit32(insn, 0, 12, offset);
53
+ * together with its delay slot.
31
+ *code_ptr = insn;
54
*/
32
+ return true;
55
- if (ctx->base.singlestep_enabled &&
33
+ }
56
- (ctx->hflags & MIPS_HFLAG_BMASK) == 0) {
34
+ return false;
57
- ctx->base.is_jmp = DISAS_TOO_MANY;
35
+}
58
- }
36
+
59
- if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE) {
37
static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
60
+ if (ctx->base.pc_next - ctx->page_start >= TARGET_PAGE_SIZE
38
intptr_t value, intptr_t addend)
61
+ && !ctx->base.singlestep_enabled) {
39
{
62
ctx->base.is_jmp = DISAS_TOO_MANY;
40
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
41
if (type == R_ARM_PC24) {
42
return reloc_pc24(code_ptr, (tcg_insn_unit *)value);
43
} else if (type == R_ARM_PC13) {
44
- intptr_t diff = value - (uintptr_t)(code_ptr + 2);
45
- tcg_insn_unit insn = *code_ptr;
46
- bool u;
47
-
48
- if (diff >= -0xfff && diff <= 0xfff) {
49
- u = (diff >= 0);
50
- if (!u) {
51
- diff = -diff;
52
- }
53
- } else {
54
- int rd = extract32(insn, 12, 4);
55
- int rt = rd == TCG_REG_PC ? TCG_REG_TMP : rd;
56
-
57
- if (diff < 0x1000 || diff >= 0x100000) {
58
- return false;
59
- }
60
-
61
- /* add rt, pc, #high */
62
- *code_ptr++ = ((insn & 0xf0000000) | (1 << 25) | ARITH_ADD
63
- | (TCG_REG_PC << 16) | (rt << 12)
64
- | (20 << 7) | (diff >> 12));
65
- /* ldr rd, [rt, #low] */
66
- insn = deposit32(insn, 12, 4, rt);
67
- diff &= 0xfff;
68
- u = 1;
69
- }
70
- insn = deposit32(insn, 23, 1, u);
71
- insn = deposit32(insn, 0, 12, diff);
72
- *code_ptr = insn;
73
+ return reloc_pc13(code_ptr, (tcg_insn_unit *)value);
74
} else {
75
g_assert_not_reached();
76
}
77
- return true;
78
}
79
80
#define TCG_CT_CONST_ARM 0x100
81
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_ld8s_r(TCGContext *s, int cond, TCGReg rt,
82
83
static void tcg_out_movi_pool(TCGContext *s, int cond, int rd, uint32_t arg)
84
{
85
- /* The 12-bit range on the ldr insn is sometimes a bit too small.
86
- In order to get around that we require two insns, one of which
87
- will usually be a nop, but may be replaced in patch_reloc. */
88
new_pool_label(s, arg, R_ARM_PC13, s->code_ptr, 0);
89
tcg_out_ld32_12(s, cond, rd, TCG_REG_PC, 0);
90
- tcg_out_nop(s);
91
}
92
93
static void tcg_out_movi32(TCGContext *s, int cond, int rd, uint32_t arg)
94
@@ -XXX,XX +XXX,XX @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *addr)
95
tcg_out_movi32(s, COND_AL, TCG_REG_TMP, addri);
96
tcg_out_blx(s, COND_AL, TCG_REG_TMP);
97
} else {
98
- /* ??? Know that movi_pool emits exactly 2 insns. */
99
- tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 4);
100
+ /* ??? Know that movi_pool emits exactly 1 insn. */
101
+ tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R14, TCG_REG_PC, 0);
102
tcg_out_movi_pool(s, COND_AL, TCG_REG_PC, addri);
103
}
63
}
104
}
64
}
105
--
65
--
106
2.17.1
66
2.25.1
107
67
108
68
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/15] tcg: Restart after TB code generation overflow
[PULL 14/24] target/mips: Drop exit checks for singlestep_enabled
1
If a TB generates too much code, try again with fewer insns.
1
GDB single-stepping is now handled generically.
2
2
3
Fixes: https://bugs.launchpad.net/bugs/1824853
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
5
---
7
accel/tcg/translate-all.c | 38 ++++++++++++++++++++++++++++++++------
6
target/mips/tcg/translate.c | 50 +++++++++++++------------------------
8
tcg/tcg.c | 4 ++++
7
1 file changed, 18 insertions(+), 32 deletions(-)
9
2 files changed, 36 insertions(+), 6 deletions(-)
10
8
11
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
9
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
12
index XXXXXXX..XXXXXXX 100644
10
index XXXXXXX..XXXXXXX 100644
13
--- a/accel/tcg/translate-all.c
11
--- a/target/mips/tcg/translate.c
14
+++ b/accel/tcg/translate-all.c
12
+++ b/target/mips/tcg/translate.c
15
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
13
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
16
tb->cflags = cflags;
14
tcg_gen_exit_tb(ctx->base.tb, n);
17
tb->trace_vcpu_dstate = *cpu->trace_dstate;
15
} else {
18
tcg_ctx->tb_cflags = cflags;
16
gen_save_pc(dest);
19
+ tb_overflow:
17
- if (ctx->base.singlestep_enabled) {
20
18
- save_cpu_state(ctx, 0);
21
#ifdef CONFIG_PROFILER
19
- gen_helper_raise_exception_debug(cpu_env);
22
/* includes aborted translations because of exceptions */
20
- } else {
23
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
21
- tcg_gen_lookup_and_goto_ptr();
24
ti = profile_getclock();
22
- }
25
#endif
23
+ tcg_gen_lookup_and_goto_ptr();
26
27
- /* ??? Overflow could be handled better here. In particular, we
28
- don't need to re-do gen_intermediate_code, nor should we re-do
29
- the tcg optimization currently hidden inside tcg_gen_code. All
30
- that should be required is to flush the TBs, allocate a new TB,
31
- re-initialize it per above, and re-do the actual code generation. */
32
gen_code_size = tcg_gen_code(tcg_ctx, tb);
33
if (unlikely(gen_code_size < 0)) {
34
- goto buffer_overflow;
35
+ switch (gen_code_size) {
36
+ case -1:
37
+ /*
38
+ * Overflow of code_gen_buffer, or the current slice of it.
39
+ *
40
+ * TODO: We don't need to re-do gen_intermediate_code, nor
41
+ * should we re-do the tcg optimization currently hidden
42
+ * inside tcg_gen_code. All that should be required is to
43
+ * flush the TBs, allocate a new TB, re-initialize it per
44
+ * above, and re-do the actual code generation.
45
+ */
46
+ goto buffer_overflow;
47
+
48
+ case -2:
49
+ /*
50
+ * The code generated for the TranslationBlock is too large.
51
+ * The maximum size allowed by the unwind info is 64k.
52
+ * There may be stricter constraints from relocations
53
+ * in the tcg backend.
54
+ *
55
+ * Try again with half as many insns as we attempted this time.
56
+ * If a single insn overflows, there's a bug somewhere...
57
+ */
58
+ max_insns = tb->icount;
59
+ assert(max_insns > 1);
60
+ max_insns /= 2;
61
+ goto tb_overflow;
62
+
63
+ default:
64
+ g_assert_not_reached();
65
+ }
66
}
24
}
67
search_size = encode_search(tb, (void *)gen_code_buf + gen_code_size);
25
}
68
if (unlikely(search_size < 0)) {
26
69
diff --git a/tcg/tcg.c b/tcg/tcg.c
27
@@ -XXX,XX +XXX,XX @@ static void gen_branch(DisasContext *ctx, int insn_bytes)
70
index XXXXXXX..XXXXXXX 100644
28
} else {
71
--- a/tcg/tcg.c
29
tcg_gen_mov_tl(cpu_PC, btarget);
72
+++ b/tcg/tcg.c
30
}
73
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
31
- if (ctx->base.singlestep_enabled) {
74
if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) {
32
- save_cpu_state(ctx, 0);
75
return -1;
33
- gen_helper_raise_exception_debug(cpu_env);
76
}
34
- }
77
+ /* Test for TB overflow, as seen by gen_insn_end_off. */
35
tcg_gen_lookup_and_goto_ptr();
78
+ if (unlikely(tcg_current_code_size(s) > UINT16_MAX)) {
36
break;
79
+ return -2;
37
default:
80
+ }
38
@@ -XXX,XX +XXX,XX @@ static void mips_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
39
{
40
DisasContext *ctx = container_of(dcbase, DisasContext, base);
41
42
- if (ctx->base.singlestep_enabled && ctx->base.is_jmp != DISAS_NORETURN) {
43
- save_cpu_state(ctx, ctx->base.is_jmp != DISAS_EXIT);
44
- gen_helper_raise_exception_debug(cpu_env);
45
- } else {
46
- switch (ctx->base.is_jmp) {
47
- case DISAS_STOP:
48
- gen_save_pc(ctx->base.pc_next);
49
- tcg_gen_lookup_and_goto_ptr();
50
- break;
51
- case DISAS_NEXT:
52
- case DISAS_TOO_MANY:
53
- save_cpu_state(ctx, 0);
54
- gen_goto_tb(ctx, 0, ctx->base.pc_next);
55
- break;
56
- case DISAS_EXIT:
57
- tcg_gen_exit_tb(NULL, 0);
58
- break;
59
- case DISAS_NORETURN:
60
- break;
61
- default:
62
- g_assert_not_reached();
63
- }
64
+ switch (ctx->base.is_jmp) {
65
+ case DISAS_STOP:
66
+ gen_save_pc(ctx->base.pc_next);
67
+ tcg_gen_lookup_and_goto_ptr();
68
+ break;
69
+ case DISAS_NEXT:
70
+ case DISAS_TOO_MANY:
71
+ save_cpu_state(ctx, 0);
72
+ gen_goto_tb(ctx, 0, ctx->base.pc_next);
73
+ break;
74
+ case DISAS_EXIT:
75
+ tcg_gen_exit_tb(NULL, 0);
76
+ break;
77
+ case DISAS_NORETURN:
78
+ break;
79
+ default:
80
+ g_assert_not_reached();
81
}
81
}
82
tcg_debug_assert(num_insns >= 0);
82
}
83
s->gen_insn_end_off[num_insns] = tcg_current_code_size(s);
83
84
--
84
--
85
2.17.1
85
2.25.1
86
86
87
87
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/15] tcg/aarch64: Support INDEX_op_extract2_{i32, i64}
[PULL 15/24] target/openrisc: Drop checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
2
1
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
5
---
4
tcg/aarch64/tcg-target.h | 4 ++--
6
target/openrisc/translate.c | 18 +++---------------
5
tcg/aarch64/tcg-target.inc.c | 11 +++++++++++
7
1 file changed, 3 insertions(+), 15 deletions(-)
6
2 files changed, 13 insertions(+), 2 deletions(-)
7
8
8
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
9
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
9
index XXXXXXX..XXXXXXX 100644
10
index XXXXXXX..XXXXXXX 100644
10
--- a/tcg/aarch64/tcg-target.h
11
--- a/target/openrisc/translate.c
11
+++ b/tcg/aarch64/tcg-target.h
12
+++ b/target/openrisc/translate.c
12
@@ -XXX,XX +XXX,XX @@ typedef enum {
13
@@ -XXX,XX +XXX,XX @@ static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
13
#define TCG_TARGET_HAS_deposit_i32 1
14
/* The jump destination is indirect/computed; use jmp_pc. */
14
#define TCG_TARGET_HAS_extract_i32 1
15
tcg_gen_mov_tl(cpu_pc, jmp_pc);
15
#define TCG_TARGET_HAS_sextract_i32 1
16
tcg_gen_discard_tl(jmp_pc);
16
-#define TCG_TARGET_HAS_extract2_i32 0
17
- if (unlikely(dc->base.singlestep_enabled)) {
17
+#define TCG_TARGET_HAS_extract2_i32 1
18
- gen_exception(dc, EXCP_DEBUG);
18
#define TCG_TARGET_HAS_movcond_i32 1
19
- } else {
19
#define TCG_TARGET_HAS_add2_i32 1
20
- tcg_gen_lookup_and_goto_ptr();
20
#define TCG_TARGET_HAS_sub2_i32 1
21
- }
21
@@ -XXX,XX +XXX,XX @@ typedef enum {
22
+ tcg_gen_lookup_and_goto_ptr();
22
#define TCG_TARGET_HAS_deposit_i64 1
23
break;
23
#define TCG_TARGET_HAS_extract_i64 1
24
}
24
#define TCG_TARGET_HAS_sextract_i64 1
25
/* The jump destination is direct; use jmp_pc_imm.
25
-#define TCG_TARGET_HAS_extract2_i64 0
26
@@ -XXX,XX +XXX,XX @@ static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
26
+#define TCG_TARGET_HAS_extract2_i64 1
27
break;
27
#define TCG_TARGET_HAS_movcond_i64 1
28
}
28
#define TCG_TARGET_HAS_add2_i64 1
29
tcg_gen_movi_tl(cpu_pc, jmp_dest);
29
#define TCG_TARGET_HAS_sub2_i64 1
30
- if (unlikely(dc->base.singlestep_enabled)) {
30
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
31
- gen_exception(dc, EXCP_DEBUG);
31
index XXXXXXX..XXXXXXX 100644
32
- } else {
32
--- a/tcg/aarch64/tcg-target.inc.c
33
- tcg_gen_lookup_and_goto_ptr();
33
+++ b/tcg/aarch64/tcg-target.inc.c
34
- }
34
@@ -XXX,XX +XXX,XX @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
35
+ tcg_gen_lookup_and_goto_ptr();
35
tcg_out_sbfm(s, ext, a0, a1, a2, a2 + args[3] - 1);
36
break;
36
break;
37
37
38
+ case INDEX_op_extract2_i64:
38
case DISAS_EXIT:
39
+ case INDEX_op_extract2_i32:
39
- if (unlikely(dc->base.singlestep_enabled)) {
40
+ tcg_out_extr(s, ext, a0, a1, a2, args[3]);
40
- gen_exception(dc, EXCP_DEBUG);
41
+ break;
41
- } else {
42
+
42
- tcg_gen_exit_tb(NULL, 0);
43
case INDEX_op_add2_i32:
43
- }
44
tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, REG0(2), REG0(3),
44
+ tcg_gen_exit_tb(NULL, 0);
45
(int32_t)args[4], args[5], const_args[4],
45
break;
46
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
46
default:
47
= { .args_ct_str = { "r", "r", "rAL" } };
47
g_assert_not_reached();
48
static const TCGTargetOpDef dep
49
= { .args_ct_str = { "r", "0", "rZ" } };
50
+ static const TCGTargetOpDef ext2
51
+ = { .args_ct_str = { "r", "rZ", "rZ" } };
52
static const TCGTargetOpDef movc
53
= { .args_ct_str = { "r", "r", "rA", "rZ", "rZ" } };
54
static const TCGTargetOpDef add2
55
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
56
case INDEX_op_deposit_i64:
57
return &dep;
58
59
+ case INDEX_op_extract2_i32:
60
+ case INDEX_op_extract2_i64:
61
+ return &ext2;
62
+
63
case INDEX_op_add2_i32:
64
case INDEX_op_add2_i64:
65
case INDEX_op_sub2_i32:
66
--
48
--
67
2.17.1
49
2.25.1
68
50
69
51
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/15] tcg: Restart TB generation after out-of-line ldst overflow
[PULL 16/24] target/ppc: Drop exit checks for singlestep_enabled
1
This is part c of relocation overflow handling.
1
GDB single-stepping is now handled generically.
2
Reuse gen_debug_exception to handle architectural debug exceptions.
2
3
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
---
5
---
5
tcg/aarch64/tcg-target.inc.c | 16 ++++++++++------
6
target/ppc/translate.c | 38 ++++++++------------------------------
6
tcg/arm/tcg-target.inc.c | 16 ++++++++++------
7
1 file changed, 8 insertions(+), 30 deletions(-)
7
tcg/i386/tcg-target.inc.c | 6 ++++--
8
tcg/mips/tcg-target.inc.c | 6 ++++--
9
tcg/ppc/tcg-target.inc.c | 14 ++++++++++----
10
tcg/riscv/tcg-target.inc.c | 16 ++++++++++++----
11
tcg/s390/tcg-target.inc.c | 20 ++++++++++++--------
12
tcg/tcg-ldst.inc.c | 18 +++++++++---------
13
tcg/tcg.c | 7 ++++---
14
9 files changed, 75 insertions(+), 44 deletions(-)
15
8
16
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
9
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
17
index XXXXXXX..XXXXXXX 100644
10
index XXXXXXX..XXXXXXX 100644
18
--- a/tcg/aarch64/tcg-target.inc.c
11
--- a/target/ppc/translate.c
19
+++ b/tcg/aarch64/tcg-target.inc.c
12
+++ b/target/ppc/translate.c
20
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_adr(TCGContext *s, TCGReg rd, void *target)
13
@@ -XXX,XX +XXX,XX @@
21
tcg_out_insn(s, 3406, ADR, rd, offset);
14
15
#define CPU_SINGLE_STEP 0x1
16
#define CPU_BRANCH_STEP 0x2
17
-#define GDBSTUB_SINGLE_STEP 0x4
18
19
/* Include definitions for instructions classes and implementations flags */
20
/* #define PPC_DEBUG_DISAS */
21
@@ -XXX,XX +XXX,XX @@ static uint32_t gen_prep_dbgex(DisasContext *ctx)
22
23
static void gen_debug_exception(DisasContext *ctx)
24
{
25
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG));
26
+ gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx)));
27
ctx->base.is_jmp = DISAS_NORETURN;
22
}
28
}
23
29
24
-static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
30
@@ -XXX,XX +XXX,XX @@ static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest)
25
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
31
32
static void gen_lookup_and_goto_ptr(DisasContext *ctx)
26
{
33
{
27
TCGMemOpIdx oi = lb->oi;
34
- int sse = ctx->singlestep_enabled;
28
TCGMemOp opc = get_memop(oi);
35
- if (unlikely(sse)) {
29
TCGMemOp size = opc & MO_SIZE;
36
- if (sse & GDBSTUB_SINGLE_STEP) {
30
37
- gen_debug_exception(ctx);
31
- bool ok = reloc_pc19(lb->label_ptr[0], s->code_ptr);
38
- } else if (sse & (CPU_SINGLE_STEP | CPU_BRANCH_STEP)) {
32
- tcg_debug_assert(ok);
39
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx)));
33
+ if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) {
40
- } else {
34
+ return false;
41
- tcg_gen_exit_tb(NULL, 0);
35
+ }
42
- }
36
43
+ if (unlikely(ctx->singlestep_enabled)) {
37
tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0);
44
+ gen_debug_exception(ctx);
38
tcg_out_mov(s, TARGET_LONG_BITS == 64, TCG_REG_X1, lb->addrlo_reg);
45
} else {
39
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
46
tcg_gen_lookup_and_goto_ptr();
40
}
47
}
41
48
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
42
tcg_out_goto(s, lb->raddr);
49
ctx->singlestep_enabled = 0;
43
+ return true;
50
if ((hflags >> HFLAGS_SE) & 1) {
51
ctx->singlestep_enabled |= CPU_SINGLE_STEP;
52
+ ctx->base.max_insns = 1;
53
}
54
if ((hflags >> HFLAGS_BE) & 1) {
55
ctx->singlestep_enabled |= CPU_BRANCH_STEP;
56
}
57
- if (unlikely(ctx->base.singlestep_enabled)) {
58
- ctx->singlestep_enabled |= GDBSTUB_SINGLE_STEP;
59
- }
60
-
61
- if (ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP)) {
62
- ctx->base.max_insns = 1;
63
- }
44
}
64
}
45
65
46
-static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
66
static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
47
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
67
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
48
{
68
DisasContext *ctx = container_of(dcbase, DisasContext, base);
49
TCGMemOpIdx oi = lb->oi;
69
DisasJumpType is_jmp = ctx->base.is_jmp;
50
TCGMemOp opc = get_memop(oi);
70
target_ulong nip = ctx->base.pc_next;
51
TCGMemOp size = opc & MO_SIZE;
71
- int sse;
52
72
53
- bool ok = reloc_pc19(lb->label_ptr[0], s->code_ptr);
73
if (is_jmp == DISAS_NORETURN) {
54
- tcg_debug_assert(ok);
74
/* We have already exited the TB. */
55
+ if (!reloc_pc19(lb->label_ptr[0], s->code_ptr)) {
75
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
56
+ return false;
57
+ }
58
59
tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_X0, TCG_AREG0);
60
tcg_out_mov(s, TARGET_LONG_BITS == 64, TCG_REG_X1, lb->addrlo_reg);
61
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
62
tcg_out_adr(s, TCG_REG_X4, lb->raddr);
63
tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
64
tcg_out_goto(s, lb->raddr);
65
+ return true;
66
}
67
68
static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
69
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
70
index XXXXXXX..XXXXXXX 100644
71
--- a/tcg/arm/tcg-target.inc.c
72
+++ b/tcg/arm/tcg-target.inc.c
73
@@ -XXX,XX +XXX,XX @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
74
label->label_ptr[0] = label_ptr;
75
}
76
77
-static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
78
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
79
{
80
TCGReg argreg, datalo, datahi;
81
TCGMemOpIdx oi = lb->oi;
82
TCGMemOp opc = get_memop(oi);
83
void *func;
84
85
- bool ok = reloc_pc24(lb->label_ptr[0], s->code_ptr);
86
- tcg_debug_assert(ok);
87
+ if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) {
88
+ return false;
89
+ }
90
91
argreg = tcg_out_arg_reg32(s, TCG_REG_R0, TCG_AREG0);
92
if (TARGET_LONG_BITS == 64) {
93
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
94
}
76
}
95
77
96
tcg_out_goto(s, COND_AL, lb->raddr);
78
/* Honor single stepping. */
97
+ return true;
79
- sse = ctx->singlestep_enabled & (CPU_SINGLE_STEP | GDBSTUB_SINGLE_STEP);
98
}
80
- if (unlikely(sse)) {
99
81
+ if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)
100
-static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
82
+ && (nip <= 0x100 || nip > 0xf00)) {
101
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
83
switch (is_jmp) {
102
{
84
case DISAS_TOO_MANY:
103
TCGReg argreg, datalo, datahi;
85
case DISAS_EXIT_UPDATE:
104
TCGMemOpIdx oi = lb->oi;
86
@@ -XXX,XX +XXX,XX @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
105
TCGMemOp opc = get_memop(oi);
87
g_assert_not_reached();
106
88
}
107
- bool ok = reloc_pc24(lb->label_ptr[0], s->code_ptr);
89
108
- tcg_debug_assert(ok);
90
- if (sse & GDBSTUB_SINGLE_STEP) {
109
+ if (!reloc_pc24(lb->label_ptr[0], s->code_ptr)) {
91
- gen_debug_exception(ctx);
110
+ return false;
92
- return;
111
+ }
93
- }
112
94
- /* else CPU_SINGLE_STEP... */
113
argreg = TCG_REG_R0;
95
- if (nip <= 0x100 || nip > 0xf00) {
114
argreg = tcg_out_arg_reg32(s, argreg, TCG_AREG0);
96
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx)));
115
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
97
- return;
116
98
- }
117
/* Tail-call to the helper, which will return to the fast path. */
99
+ gen_debug_exception(ctx);
118
tcg_out_goto(s, COND_AL, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
100
+ return;
119
+ return true;
120
}
121
#endif /* SOFTMMU */
122
123
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
124
index XXXXXXX..XXXXXXX 100644
125
--- a/tcg/i386/tcg-target.inc.c
126
+++ b/tcg/i386/tcg-target.inc.c
127
@@ -XXX,XX +XXX,XX @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, bool is_64,
128
/*
129
* Generate code for the slow path for a load at the end of block
130
*/
131
-static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
132
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
133
{
134
TCGMemOpIdx oi = l->oi;
135
TCGMemOp opc = get_memop(oi);
136
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
137
138
/* Jump to the code corresponding to next IR of qemu_st */
139
tcg_out_jmp(s, l->raddr);
140
+ return true;
141
}
142
143
/*
144
* Generate code for the slow path for a store at the end of block
145
*/
146
-static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
147
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
148
{
149
TCGMemOpIdx oi = l->oi;
150
TCGMemOp opc = get_memop(oi);
151
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
152
/* "Tail call" to the helper, with the return address back inline. */
153
tcg_out_push(s, retaddr);
154
tcg_out_jmp(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
155
+ return true;
156
}
157
#elif TCG_TARGET_REG_BITS == 32
158
# define x86_guest_base_seg 0
159
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
160
index XXXXXXX..XXXXXXX 100644
161
--- a/tcg/mips/tcg-target.inc.c
162
+++ b/tcg/mips/tcg-target.inc.c
163
@@ -XXX,XX +XXX,XX @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
164
}
101
}
165
}
102
166
103
switch (is_jmp) {
167
-static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
168
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
169
{
170
TCGMemOpIdx oi = l->oi;
171
TCGMemOp opc = get_memop(oi);
172
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
173
} else {
174
tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO);
175
}
176
+ return true;
177
}
178
179
-static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
180
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
181
{
182
TCGMemOpIdx oi = l->oi;
183
TCGMemOp opc = get_memop(oi);
184
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
185
tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true);
186
/* delay slot */
187
tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0);
188
+ return true;
189
}
190
#endif
191
192
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
193
index XXXXXXX..XXXXXXX 100644
194
--- a/tcg/ppc/tcg-target.inc.c
195
+++ b/tcg/ppc/tcg-target.inc.c
196
@@ -XXX,XX +XXX,XX @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
197
label->label_ptr[0] = lptr;
198
}
199
200
-static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
201
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
202
{
203
TCGMemOpIdx oi = lb->oi;
204
TCGMemOp opc = get_memop(oi);
205
TCGReg hi, lo, arg = TCG_REG_R3;
206
207
- **lb->label_ptr |= reloc_pc14_val(*lb->label_ptr, s->code_ptr);
208
+ if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) {
209
+ return false;
210
+ }
211
212
tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
213
214
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
215
}
216
217
tcg_out_b(s, 0, lb->raddr);
218
+ return true;
219
}
220
221
-static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
222
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
223
{
224
TCGMemOpIdx oi = lb->oi;
225
TCGMemOp opc = get_memop(oi);
226
TCGMemOp s_bits = opc & MO_SIZE;
227
TCGReg hi, lo, arg = TCG_REG_R3;
228
229
- **lb->label_ptr |= reloc_pc14_val(*lb->label_ptr, s->code_ptr);
230
+ if (!reloc_pc14(lb->label_ptr[0], s->code_ptr)) {
231
+ return false;
232
+ }
233
234
tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0);
235
236
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
237
tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
238
239
tcg_out_b(s, 0, lb->raddr);
240
+ return true;
241
}
242
#endif /* SOFTMMU */
243
244
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
245
index XXXXXXX..XXXXXXX 100644
246
--- a/tcg/riscv/tcg-target.inc.c
247
+++ b/tcg/riscv/tcg-target.inc.c
248
@@ -XXX,XX +XXX,XX @@ static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi,
249
label->label_ptr[0] = label_ptr[0];
250
}
251
252
-static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
253
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
254
{
255
TCGMemOpIdx oi = l->oi;
256
TCGMemOp opc = get_memop(oi);
257
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
258
}
259
260
/* resolve label address */
261
- patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, (intptr_t) s->code_ptr, 0);
262
+ if (!patch_reloc(l->label_ptr[0], R_RISCV_BRANCH,
263
+ (intptr_t) s->code_ptr, 0)) {
264
+ return false;
265
+ }
266
267
/* call load helper */
268
tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0);
269
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
270
tcg_out_mov(s, (opc & MO_SIZE) == MO_64, l->datalo_reg, a0);
271
272
tcg_out_goto(s, l->raddr);
273
+ return true;
274
}
275
276
-static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
277
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
278
{
279
TCGMemOpIdx oi = l->oi;
280
TCGMemOp opc = get_memop(oi);
281
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
282
}
283
284
/* resolve label address */
285
- patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, (intptr_t) s->code_ptr, 0);
286
+ if (!patch_reloc(l->label_ptr[0], R_RISCV_BRANCH,
287
+ (intptr_t) s->code_ptr, 0)) {
288
+ return false;
289
+ }
290
291
/* call store helper */
292
tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0);
293
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
294
tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SSIZE)]);
295
296
tcg_out_goto(s, l->raddr);
297
+ return true;
298
}
299
#endif /* CONFIG_SOFTMMU */
300
301
diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
302
index XXXXXXX..XXXXXXX 100644
303
--- a/tcg/s390/tcg-target.inc.c
304
+++ b/tcg/s390/tcg-target.inc.c
305
@@ -XXX,XX +XXX,XX @@ static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOpIdx oi,
306
label->label_ptr[0] = label_ptr;
307
}
308
309
-static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
310
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
311
{
312
TCGReg addr_reg = lb->addrlo_reg;
313
TCGReg data_reg = lb->datalo_reg;
314
TCGMemOpIdx oi = lb->oi;
315
TCGMemOp opc = get_memop(oi);
316
317
- bool ok = patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
318
- (intptr_t)s->code_ptr, 2);
319
- tcg_debug_assert(ok);
320
+ if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
321
+ (intptr_t)s->code_ptr, 2)) {
322
+ return false;
323
+ }
324
325
tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0);
326
if (TARGET_LONG_BITS == 64) {
327
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
328
tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_R2);
329
330
tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr);
331
+ return true;
332
}
333
334
-static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
335
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
336
{
337
TCGReg addr_reg = lb->addrlo_reg;
338
TCGReg data_reg = lb->datalo_reg;
339
TCGMemOpIdx oi = lb->oi;
340
TCGMemOp opc = get_memop(oi);
341
342
- bool ok = patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
343
- (intptr_t)s->code_ptr, 2);
344
- tcg_debug_assert(ok);
345
+ if (!patch_reloc(lb->label_ptr[0], R_390_PC16DBL,
346
+ (intptr_t)s->code_ptr, 2)) {
347
+ return false;
348
+ }
349
350
tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_AREG0);
351
if (TARGET_LONG_BITS == 64) {
352
@@ -XXX,XX +XXX,XX @@ static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
353
tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]);
354
355
tgen_gotoi(s, S390_CC_ALWAYS, lb->raddr);
356
+ return true;
357
}
358
#else
359
static void tcg_prepare_user_ldst(TCGContext *s, TCGReg *addr_reg,
360
diff --git a/tcg/tcg-ldst.inc.c b/tcg/tcg-ldst.inc.c
361
index XXXXXXX..XXXXXXX 100644
362
--- a/tcg/tcg-ldst.inc.c
363
+++ b/tcg/tcg-ldst.inc.c
364
@@ -XXX,XX +XXX,XX @@ typedef struct TCGLabelQemuLdst {
365
* Generate TB finalization at the end of block
366
*/
367
368
-static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l);
369
-static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l);
370
+static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l);
371
+static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l);
372
373
-static bool tcg_out_ldst_finalize(TCGContext *s)
374
+static int tcg_out_ldst_finalize(TCGContext *s)
375
{
376
TCGLabelQemuLdst *lb;
377
378
/* qemu_ld/st slow paths */
379
QSIMPLEQ_FOREACH(lb, &s->ldst_labels, next) {
380
- if (lb->is_ld) {
381
- tcg_out_qemu_ld_slow_path(s, lb);
382
- } else {
383
- tcg_out_qemu_st_slow_path(s, lb);
384
+ if (lb->is_ld
385
+ ? !tcg_out_qemu_ld_slow_path(s, lb)
386
+ : !tcg_out_qemu_st_slow_path(s, lb)) {
387
+ return -2;
388
}
389
390
/* Test for (pending) buffer overflow. The assumption is that any
391
@@ -XXX,XX +XXX,XX @@ static bool tcg_out_ldst_finalize(TCGContext *s)
392
the buffer completely. Thus we can test for overflow after
393
generating code without having to check during generation. */
394
if (unlikely((void *)s->code_ptr > s->code_gen_highwater)) {
395
- return false;
396
+ return -1;
397
}
398
}
399
- return true;
400
+ return 0;
401
}
402
403
/*
404
diff --git a/tcg/tcg.c b/tcg/tcg.c
405
index XXXXXXX..XXXXXXX 100644
406
--- a/tcg/tcg.c
407
+++ b/tcg/tcg.c
408
@@ -XXX,XX +XXX,XX @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *target);
409
static int tcg_target_const_match(tcg_target_long val, TCGType type,
410
const TCGArgConstraint *arg_ct);
411
#ifdef TCG_TARGET_NEED_LDST_LABELS
412
-static bool tcg_out_ldst_finalize(TCGContext *s);
413
+static int tcg_out_ldst_finalize(TCGContext *s);
414
#endif
415
416
#define TCG_HIGHWATER 1024
417
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
418
419
/* Generate TB finalization at the end of block */
420
#ifdef TCG_TARGET_NEED_LDST_LABELS
421
- if (!tcg_out_ldst_finalize(s)) {
422
- return -1;
423
+ i = tcg_out_ldst_finalize(s);
424
+ if (i < 0) {
425
+ return i;
426
}
427
#endif
428
#ifdef TCG_TARGET_NEED_POOL_LABELS
429
--
104
--
430
2.17.1
105
2.25.1
431
106
432
107
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/15] tcg: Use extract2 in tcg_gen_deposit_{i32, i64}
[PULL 17/24] target/riscv: Remove dead code after exception
1
We have already set DISAS_NORETURN in generate_exception,
2
which makes the exit_tb unreachable.
3
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
1
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2
---
6
---
3
tcg/tcg-op.c | 34 ++++++++++++++++++++++++++++++----
7
target/riscv/insn_trans/trans_privileged.c.inc | 6 +-----
4
1 file changed, 30 insertions(+), 4 deletions(-)
8
1 file changed, 1 insertion(+), 5 deletions(-)
5
9
6
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
10
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
7
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
8
--- a/tcg/tcg-op.c
12
--- a/target/riscv/insn_trans/trans_privileged.c.inc
9
+++ b/tcg/tcg-op.c
13
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
10
@@ -XXX,XX +XXX,XX @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
14
@@ -XXX,XX +XXX,XX @@ static bool trans_ecall(DisasContext *ctx, arg_ecall *a)
11
return;
15
{
16
/* always generates U-level ECALL, fixed in do_interrupt handler */
17
generate_exception(ctx, RISCV_EXCP_U_ECALL);
18
- exit_tb(ctx); /* no chaining */
19
- ctx->base.is_jmp = DISAS_NORETURN;
20
return true;
21
}
22
23
@@ -XXX,XX +XXX,XX @@ static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a)
24
post = opcode_at(&ctx->base, post_addr);
12
}
25
}
13
26
14
- mask = (1u << len) - 1;
27
- if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
15
t1 = tcg_temp_new_i32();
28
+ if (pre == 0x01f01013 && ebreak == 0x00100073 && post == 0x40705013) {
16
29
generate_exception(ctx, RISCV_EXCP_SEMIHOST);
17
+ if (TCG_TARGET_HAS_extract2_i32) {
30
} else {
18
+ if (ofs + len == 32) {
31
generate_exception(ctx, RISCV_EXCP_BREAKPOINT);
19
+ tcg_gen_shli_i32(t1, arg1, len);
20
+ tcg_gen_extract2_i32(ret, t1, arg2, len);
21
+ goto done;
22
+ }
23
+ if (ofs == 0) {
24
+ tcg_gen_extract2_i32(ret, arg1, arg2, len);
25
+ tcg_gen_rotli_i32(ret, ret, len);
26
+ goto done;
27
+ }
28
+ }
29
+
30
+ mask = (1u << len) - 1;
31
if (ofs + len < 32) {
32
tcg_gen_andi_i32(t1, arg2, mask);
33
tcg_gen_shli_i32(t1, t1, ofs);
34
@@ -XXX,XX +XXX,XX @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
35
}
32
}
36
tcg_gen_andi_i32(ret, arg1, ~(mask << ofs));
33
- exit_tb(ctx); /* no chaining */
37
tcg_gen_or_i32(ret, ret, t1);
34
- ctx->base.is_jmp = DISAS_NORETURN;
38
-
35
return true;
39
+ done:
40
tcg_temp_free_i32(t1);
41
}
36
}
42
37
43
@@ -XXX,XX +XXX,XX @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
44
}
45
}
46
47
- mask = (1ull << len) - 1;
48
t1 = tcg_temp_new_i64();
49
50
+ if (TCG_TARGET_HAS_extract2_i64) {
51
+ if (ofs + len == 64) {
52
+ tcg_gen_shli_i64(t1, arg1, len);
53
+ tcg_gen_extract2_i64(ret, t1, arg2, len);
54
+ goto done;
55
+ }
56
+ if (ofs == 0) {
57
+ tcg_gen_extract2_i64(ret, arg1, arg2, len);
58
+ tcg_gen_rotli_i64(ret, ret, len);
59
+ goto done;
60
+ }
61
+ }
62
+
63
+ mask = (1ull << len) - 1;
64
if (ofs + len < 64) {
65
tcg_gen_andi_i64(t1, arg2, mask);
66
tcg_gen_shli_i64(t1, t1, ofs);
67
@@ -XXX,XX +XXX,XX @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
68
}
69
tcg_gen_andi_i64(ret, arg1, ~(mask << ofs));
70
tcg_gen_or_i64(ret, ret, t1);
71
-
72
+ done:
73
tcg_temp_free_i64(t1);
74
}
75
76
--
38
--
77
2.17.1
39
2.25.1
78
40
79
41
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/15] tcg: Hoist max_insns computation to tb_gen_code
[PULL 18/24] target/riscv: Remove exit_tb and lookup_and_goto_ptr
1
In order to handle TB's that translate to too much code, we
1
GDB single-stepping is now handled generically, which means
2
need to place the control of the length of the translation
2
we don't need to do anything in the wrappers.
3
in the hands of the code gen master loop.
4
3
5
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
4
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
6
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
---
6
---
9
include/exec/exec-all.h | 4 ++--
7
target/riscv/translate.c | 27 +------------------
10
include/exec/translator.h | 3 ++-
8
.../riscv/insn_trans/trans_privileged.c.inc | 4 +--
11
accel/tcg/translate-all.c | 15 +++++++++++++--
9
target/riscv/insn_trans/trans_rvi.c.inc | 8 +++---
12
accel/tcg/translator.c | 15 ++-------------
10
target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
13
target/alpha/translate.c | 4 ++--
11
4 files changed, 7 insertions(+), 34 deletions(-)
14
target/arm/translate.c | 4 ++--
15
target/cris/translate.c | 10 +---------
16
target/hppa/translate.c | 5 ++---
17
target/i386/translate.c | 4 ++--
18
target/lm32/translate.c | 10 +---------
19
target/m68k/translate.c | 4 ++--
20
target/microblaze/translate.c | 10 +---------
21
target/mips/translate.c | 4 ++--
22
target/moxie/translate.c | 11 ++---------
23
target/nios2/translate.c | 14 ++------------
24
target/openrisc/translate.c | 4 ++--
25
target/ppc/translate.c | 4 ++--
26
target/riscv/translate.c | 4 ++--
27
target/s390x/translate.c | 4 ++--
28
target/sh4/translate.c | 4 ++--
29
target/sparc/translate.c | 4 ++--
30
target/tilegx/translate.c | 12 +-----------
31
target/tricore/translate.c | 16 ++--------------
32
target/unicore32/translate.c | 10 +---------
33
target/xtensa/translate.c | 4 ++--
34
25 files changed, 56 insertions(+), 127 deletions(-)
35
12
36
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
37
index XXXXXXX..XXXXXXX 100644
38
--- a/include/exec/exec-all.h
39
+++ b/include/exec/exec-all.h
40
@@ -XXX,XX +XXX,XX @@ typedef ram_addr_t tb_page_addr_t;
41
42
#include "qemu/log.h"
43
44
-void gen_intermediate_code(CPUState *cpu, struct TranslationBlock *tb);
45
-void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb,
46
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns);
47
+void restore_state_to_opc(CPUArchState *env, TranslationBlock *tb,
48
target_ulong *data);
49
50
void cpu_gen_init(void);
51
diff --git a/include/exec/translator.h b/include/exec/translator.h
52
index XXXXXXX..XXXXXXX 100644
53
--- a/include/exec/translator.h
54
+++ b/include/exec/translator.h
55
@@ -XXX,XX +XXX,XX @@ typedef struct TranslatorOps {
56
* @db: Disassembly context.
57
* @cpu: Target vCPU.
58
* @tb: Translation block.
59
+ * @max_insns: Maximum number of insns to translate.
60
*
61
* Generic translator loop.
62
*
63
@@ -XXX,XX +XXX,XX @@ typedef struct TranslatorOps {
64
* - When too many instructions have been translated.
65
*/
66
void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
67
- CPUState *cpu, TranslationBlock *tb);
68
+ CPUState *cpu, TranslationBlock *tb, int max_insns);
69
70
void translator_loop_temp_check(DisasContextBase *db);
71
72
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
73
index XXXXXXX..XXXXXXX 100644
74
--- a/accel/tcg/translate-all.c
75
+++ b/accel/tcg/translate-all.c
76
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
77
tb_page_addr_t phys_pc, phys_page2;
78
target_ulong virt_page2;
79
tcg_insn_unit *gen_code_buf;
80
- int gen_code_size, search_size;
81
+ int gen_code_size, search_size, max_insns;
82
#ifdef CONFIG_PROFILER
83
TCGProfile *prof = &tcg_ctx->prof;
84
int64_t ti;
85
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
86
cflags &= ~CF_CLUSTER_MASK;
87
cflags |= cpu->cluster_index << CF_CLUSTER_SHIFT;
88
89
+ max_insns = cflags & CF_COUNT_MASK;
90
+ if (max_insns == 0) {
91
+ max_insns = CF_COUNT_MASK;
92
+ }
93
+ if (max_insns > TCG_MAX_INSNS) {
94
+ max_insns = TCG_MAX_INSNS;
95
+ }
96
+ if (cpu->singlestep_enabled || singlestep) {
97
+ max_insns = 1;
98
+ }
99
+
100
buffer_overflow:
101
tb = tb_alloc(pc);
102
if (unlikely(!tb)) {
103
@@ -XXX,XX +XXX,XX @@ TranslationBlock *tb_gen_code(CPUState *cpu,
104
tcg_func_start(tcg_ctx);
105
106
tcg_ctx->cpu = ENV_GET_CPU(env);
107
- gen_intermediate_code(cpu, tb);
108
+ gen_intermediate_code(cpu, tb, max_insns);
109
tcg_ctx->cpu = NULL;
110
111
trace_translate_block(tb, tb->pc, tb->tc.ptr);
112
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
113
index XXXXXXX..XXXXXXX 100644
114
--- a/accel/tcg/translator.c
115
+++ b/accel/tcg/translator.c
116
@@ -XXX,XX +XXX,XX @@ void translator_loop_temp_check(DisasContextBase *db)
117
}
118
119
void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
120
- CPUState *cpu, TranslationBlock *tb)
121
+ CPUState *cpu, TranslationBlock *tb, int max_insns)
122
{
123
int bp_insn = 0;
124
125
@@ -XXX,XX +XXX,XX @@ void translator_loop(const TranslatorOps *ops, DisasContextBase *db,
126
db->pc_next = db->pc_first;
127
db->is_jmp = DISAS_NEXT;
128
db->num_insns = 0;
129
+ db->max_insns = max_insns;
130
db->singlestep_enabled = cpu->singlestep_enabled;
131
132
- /* Instruction counting */
133
- db->max_insns = tb_cflags(db->tb) & CF_COUNT_MASK;
134
- if (db->max_insns == 0) {
135
- db->max_insns = CF_COUNT_MASK;
136
- }
137
- if (db->max_insns > TCG_MAX_INSNS) {
138
- db->max_insns = TCG_MAX_INSNS;
139
- }
140
- if (db->singlestep_enabled || singlestep) {
141
- db->max_insns = 1;
142
- }
143
-
144
ops->init_disas_context(db, cpu);
145
tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */
146
147
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
148
index XXXXXXX..XXXXXXX 100644
149
--- a/target/alpha/translate.c
150
+++ b/target/alpha/translate.c
151
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps alpha_tr_ops = {
152
.disas_log = alpha_tr_disas_log,
153
};
154
155
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
156
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
157
{
158
DisasContext dc;
159
- translator_loop(&alpha_tr_ops, &dc.base, cpu, tb);
160
+ translator_loop(&alpha_tr_ops, &dc.base, cpu, tb, max_insns);
161
}
162
163
void restore_state_to_opc(CPUAlphaState *env, TranslationBlock *tb,
164
diff --git a/target/arm/translate.c b/target/arm/translate.c
165
index XXXXXXX..XXXXXXX 100644
166
--- a/target/arm/translate.c
167
+++ b/target/arm/translate.c
168
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps thumb_translator_ops = {
169
};
170
171
/* generate intermediate code for basic block 'tb'. */
172
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
173
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
174
{
175
DisasContext dc;
176
const TranslatorOps *ops = &arm_translator_ops;
177
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
178
}
179
#endif
180
181
- translator_loop(ops, &dc.base, cpu, tb);
182
+ translator_loop(ops, &dc.base, cpu, tb, max_insns);
183
}
184
185
void arm_cpu_dump_state(CPUState *cs, FILE *f, int flags)
186
diff --git a/target/cris/translate.c b/target/cris/translate.c
187
index XXXXXXX..XXXXXXX 100644
188
--- a/target/cris/translate.c
189
+++ b/target/cris/translate.c
190
@@ -XXX,XX +XXX,XX @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
191
*/
192
193
/* generate intermediate code for basic block 'tb'. */
194
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
195
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
196
{
197
CPUCRISState *env = cs->env_ptr;
198
uint32_t pc_start;
199
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
200
uint32_t page_start;
201
target_ulong npc;
202
int num_insns;
203
- int max_insns;
204
205
if (env->pregs[PR_VR] == 32) {
206
dc->decoder = crisv32_decoder;
207
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
208
209
page_start = pc_start & TARGET_PAGE_MASK;
210
num_insns = 0;
211
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
212
- if (max_insns == 0) {
213
- max_insns = CF_COUNT_MASK;
214
- }
215
- if (max_insns > TCG_MAX_INSNS) {
216
- max_insns = TCG_MAX_INSNS;
217
- }
218
219
gen_tb_start(tb);
220
do {
221
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
222
index XXXXXXX..XXXXXXX 100644
223
--- a/target/hppa/translate.c
224
+++ b/target/hppa/translate.c
225
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps hppa_tr_ops = {
226
.disas_log = hppa_tr_disas_log,
227
};
228
229
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
230
-
231
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
232
{
233
DisasContext ctx;
234
- translator_loop(&hppa_tr_ops, &ctx.base, cs, tb);
235
+ translator_loop(&hppa_tr_ops, &ctx.base, cs, tb, max_insns);
236
}
237
238
void restore_state_to_opc(CPUHPPAState *env, TranslationBlock *tb,
239
diff --git a/target/i386/translate.c b/target/i386/translate.c
240
index XXXXXXX..XXXXXXX 100644
241
--- a/target/i386/translate.c
242
+++ b/target/i386/translate.c
243
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps i386_tr_ops = {
244
};
245
246
/* generate intermediate code for basic block 'tb'. */
247
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
248
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
249
{
250
DisasContext dc;
251
252
- translator_loop(&i386_tr_ops, &dc.base, cpu, tb);
253
+ translator_loop(&i386_tr_ops, &dc.base, cpu, tb, max_insns);
254
}
255
256
void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb,
257
diff --git a/target/lm32/translate.c b/target/lm32/translate.c
258
index XXXXXXX..XXXXXXX 100644
259
--- a/target/lm32/translate.c
260
+++ b/target/lm32/translate.c
261
@@ -XXX,XX +XXX,XX @@ static inline void decode(DisasContext *dc, uint32_t ir)
262
}
263
264
/* generate intermediate code for basic block 'tb'. */
265
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
266
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
267
{
268
CPULM32State *env = cs->env_ptr;
269
LM32CPU *cpu = lm32_env_get_cpu(env);
270
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
271
uint32_t pc_start;
272
uint32_t page_start;
273
int num_insns;
274
- int max_insns;
275
276
pc_start = tb->pc;
277
dc->features = cpu->features;
278
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
279
280
page_start = pc_start & TARGET_PAGE_MASK;
281
num_insns = 0;
282
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
283
- if (max_insns == 0) {
284
- max_insns = CF_COUNT_MASK;
285
- }
286
- if (max_insns > TCG_MAX_INSNS) {
287
- max_insns = TCG_MAX_INSNS;
288
- }
289
290
gen_tb_start(tb);
291
do {
292
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
293
index XXXXXXX..XXXXXXX 100644
294
--- a/target/m68k/translate.c
295
+++ b/target/m68k/translate.c
296
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps m68k_tr_ops = {
297
.disas_log = m68k_tr_disas_log,
298
};
299
300
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
301
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
302
{
303
DisasContext dc;
304
- translator_loop(&m68k_tr_ops, &dc.base, cpu, tb);
305
+ translator_loop(&m68k_tr_ops, &dc.base, cpu, tb, max_insns);
306
}
307
308
static double floatx80_to_double(CPUM68KState *env, uint16_t high, uint64_t low)
309
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
310
index XXXXXXX..XXXXXXX 100644
311
--- a/target/microblaze/translate.c
312
+++ b/target/microblaze/translate.c
313
@@ -XXX,XX +XXX,XX @@ static inline void decode(DisasContext *dc, uint32_t ir)
314
}
315
316
/* generate intermediate code for basic block 'tb'. */
317
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
318
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
319
{
320
CPUMBState *env = cs->env_ptr;
321
MicroBlazeCPU *cpu = mb_env_get_cpu(env);
322
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
323
uint32_t page_start, org_flags;
324
uint32_t npc;
325
int num_insns;
326
- int max_insns;
327
328
pc_start = tb->pc;
329
dc->cpu = cpu;
330
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
331
332
page_start = pc_start & TARGET_PAGE_MASK;
333
num_insns = 0;
334
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
335
- if (max_insns == 0) {
336
- max_insns = CF_COUNT_MASK;
337
- }
338
- if (max_insns > TCG_MAX_INSNS) {
339
- max_insns = TCG_MAX_INSNS;
340
- }
341
342
gen_tb_start(tb);
343
do
344
diff --git a/target/mips/translate.c b/target/mips/translate.c
345
index XXXXXXX..XXXXXXX 100644
346
--- a/target/mips/translate.c
347
+++ b/target/mips/translate.c
348
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps mips_tr_ops = {
349
.disas_log = mips_tr_disas_log,
350
};
351
352
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
353
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
354
{
355
DisasContext ctx;
356
357
- translator_loop(&mips_tr_ops, &ctx.base, cs, tb);
358
+ translator_loop(&mips_tr_ops, &ctx.base, cs, tb, max_insns);
359
}
360
361
static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags)
362
diff --git a/target/moxie/translate.c b/target/moxie/translate.c
363
index XXXXXXX..XXXXXXX 100644
364
--- a/target/moxie/translate.c
365
+++ b/target/moxie/translate.c
366
@@ -XXX,XX +XXX,XX @@ static int decode_opc(MoxieCPU *cpu, DisasContext *ctx)
367
}
368
369
/* generate intermediate code for basic block 'tb'. */
370
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
371
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
372
{
373
CPUMoxieState *env = cs->env_ptr;
374
MoxieCPU *cpu = moxie_env_get_cpu(env);
375
DisasContext ctx;
376
target_ulong pc_start;
377
- int num_insns, max_insns;
378
+ int num_insns;
379
380
pc_start = tb->pc;
381
ctx.pc = pc_start;
382
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
383
ctx.singlestep_enabled = 0;
384
ctx.bstate = BS_NONE;
385
num_insns = 0;
386
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
387
- if (max_insns == 0) {
388
- max_insns = CF_COUNT_MASK;
389
- }
390
- if (max_insns > TCG_MAX_INSNS) {
391
- max_insns = TCG_MAX_INSNS;
392
- }
393
394
gen_tb_start(tb);
395
do {
396
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
397
index XXXXXXX..XXXXXXX 100644
398
--- a/target/nios2/translate.c
399
+++ b/target/nios2/translate.c
400
@@ -XXX,XX +XXX,XX @@ static void gen_exception(DisasContext *dc, uint32_t excp)
401
}
402
403
/* generate intermediate code for basic block 'tb'. */
404
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
405
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
406
{
407
CPUNios2State *env = cs->env_ptr;
408
DisasContext dc1, *dc = &dc1;
409
int num_insns;
410
- int max_insns;
411
412
/* Initialize DC */
413
dc->cpu_env = cpu_env;
414
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
415
416
/* Set up instruction counts */
417
num_insns = 0;
418
- if (cs->singlestep_enabled || singlestep) {
419
- max_insns = 1;
420
- } else {
421
+ if (max_insns > 1) {
422
int page_insns = (TARGET_PAGE_SIZE - (tb->pc & TARGET_PAGE_MASK)) / 4;
423
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
424
- if (max_insns == 0) {
425
- max_insns = CF_COUNT_MASK;
426
- }
427
if (max_insns > page_insns) {
428
max_insns = page_insns;
429
}
430
- if (max_insns > TCG_MAX_INSNS) {
431
- max_insns = TCG_MAX_INSNS;
432
- }
433
}
434
435
gen_tb_start(tb);
436
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
437
index XXXXXXX..XXXXXXX 100644
438
--- a/target/openrisc/translate.c
439
+++ b/target/openrisc/translate.c
440
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps openrisc_tr_ops = {
441
.disas_log = openrisc_tr_disas_log,
442
};
443
444
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
445
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
446
{
447
DisasContext ctx;
448
449
- translator_loop(&openrisc_tr_ops, &ctx.base, cs, tb);
450
+ translator_loop(&openrisc_tr_ops, &ctx.base, cs, tb, max_insns);
451
}
452
453
void openrisc_cpu_dump_state(CPUState *cs, FILE *f, int flags)
454
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
455
index XXXXXXX..XXXXXXX 100644
456
--- a/target/ppc/translate.c
457
+++ b/target/ppc/translate.c
458
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps ppc_tr_ops = {
459
.disas_log = ppc_tr_disas_log,
460
};
461
462
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
463
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
464
{
465
DisasContext ctx;
466
467
- translator_loop(&ppc_tr_ops, &ctx.base, cs, tb);
468
+ translator_loop(&ppc_tr_ops, &ctx.base, cs, tb, max_insns);
469
}
470
471
void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb,
472
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
13
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
473
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
474
--- a/target/riscv/translate.c
15
--- a/target/riscv/translate.c
475
+++ b/target/riscv/translate.c
16
+++ b/target/riscv/translate.c
476
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps riscv_tr_ops = {
17
@@ -XXX,XX +XXX,XX @@ static void generate_exception_mtval(DisasContext *ctx, int excp)
477
.disas_log = riscv_tr_disas_log,
18
ctx->base.is_jmp = DISAS_NORETURN;
478
};
19
}
479
20
480
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
21
-static void gen_exception_debug(void)
481
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
22
-{
23
- gen_helper_raise_exception(cpu_env, tcg_constant_i32(EXCP_DEBUG));
24
-}
25
-
26
-/* Wrapper around tcg_gen_exit_tb that handles single stepping */
27
-static void exit_tb(DisasContext *ctx)
28
-{
29
- if (ctx->base.singlestep_enabled) {
30
- gen_exception_debug();
31
- } else {
32
- tcg_gen_exit_tb(NULL, 0);
33
- }
34
-}
35
-
36
-/* Wrapper around tcg_gen_lookup_and_goto_ptr that handles single stepping */
37
-static void lookup_and_goto_ptr(DisasContext *ctx)
38
-{
39
- if (ctx->base.singlestep_enabled) {
40
- gen_exception_debug();
41
- } else {
42
- tcg_gen_lookup_and_goto_ptr();
43
- }
44
-}
45
-
46
static void gen_exception_illegal(DisasContext *ctx)
482
{
47
{
483
DisasContext ctx;
48
generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST);
484
49
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
485
- translator_loop(&riscv_tr_ops, &ctx.base, cs, tb);
50
tcg_gen_exit_tb(ctx->base.tb, n);
486
+ translator_loop(&riscv_tr_ops, &ctx.base, cs, tb, max_insns);
51
} else {
487
}
52
tcg_gen_movi_tl(cpu_pc, dest);
488
53
- lookup_and_goto_ptr(ctx);
489
void riscv_translate_init(void)
54
+ tcg_gen_lookup_and_goto_ptr();
490
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
491
index XXXXXXX..XXXXXXX 100644
492
--- a/target/s390x/translate.c
493
+++ b/target/s390x/translate.c
494
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps s390x_tr_ops = {
495
.disas_log = s390x_tr_disas_log,
496
};
497
498
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
499
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
500
{
501
DisasContext dc;
502
503
- translator_loop(&s390x_tr_ops, &dc.base, cs, tb);
504
+ translator_loop(&s390x_tr_ops, &dc.base, cs, tb, max_insns);
505
}
506
507
void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb,
508
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
509
index XXXXXXX..XXXXXXX 100644
510
--- a/target/sh4/translate.c
511
+++ b/target/sh4/translate.c
512
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps sh4_tr_ops = {
513
.disas_log = sh4_tr_disas_log,
514
};
515
516
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
517
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
518
{
519
DisasContext ctx;
520
521
- translator_loop(&sh4_tr_ops, &ctx.base, cs, tb);
522
+ translator_loop(&sh4_tr_ops, &ctx.base, cs, tb, max_insns);
523
}
524
525
void restore_state_to_opc(CPUSH4State *env, TranslationBlock *tb,
526
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
527
index XXXXXXX..XXXXXXX 100644
528
--- a/target/sparc/translate.c
529
+++ b/target/sparc/translate.c
530
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps sparc_tr_ops = {
531
.disas_log = sparc_tr_disas_log,
532
};
533
534
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
535
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
536
{
537
DisasContext dc = {};
538
539
- translator_loop(&sparc_tr_ops, &dc.base, cs, tb);
540
+ translator_loop(&sparc_tr_ops, &dc.base, cs, tb, max_insns);
541
}
542
543
void sparc_tcg_init(void)
544
diff --git a/target/tilegx/translate.c b/target/tilegx/translate.c
545
index XXXXXXX..XXXXXXX 100644
546
--- a/target/tilegx/translate.c
547
+++ b/target/tilegx/translate.c
548
@@ -XXX,XX +XXX,XX @@ static void translate_one_bundle(DisasContext *dc, uint64_t bundle)
549
}
55
}
550
}
56
}
551
57
552
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
58
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc
553
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
59
index XXXXXXX..XXXXXXX 100644
60
--- a/target/riscv/insn_trans/trans_privileged.c.inc
61
+++ b/target/riscv/insn_trans/trans_privileged.c.inc
62
@@ -XXX,XX +XXX,XX @@ static bool trans_sret(DisasContext *ctx, arg_sret *a)
63
64
if (has_ext(ctx, RVS)) {
65
gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
66
- exit_tb(ctx); /* no chaining */
67
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
68
ctx->base.is_jmp = DISAS_NORETURN;
69
} else {
70
return false;
71
@@ -XXX,XX +XXX,XX @@ static bool trans_mret(DisasContext *ctx, arg_mret *a)
72
#ifndef CONFIG_USER_ONLY
73
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
74
gen_helper_mret(cpu_pc, cpu_env, cpu_pc);
75
- exit_tb(ctx); /* no chaining */
76
+ tcg_gen_exit_tb(NULL, 0); /* no chaining */
77
ctx->base.is_jmp = DISAS_NORETURN;
78
return true;
79
#else
80
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc
81
index XXXXXXX..XXXXXXX 100644
82
--- a/target/riscv/insn_trans/trans_rvi.c.inc
83
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
84
@@ -XXX,XX +XXX,XX @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
85
if (a->rd != 0) {
86
tcg_gen_movi_tl(cpu_gpr[a->rd], ctx->pc_succ_insn);
87
}
88
-
89
- /* No chaining with JALR. */
90
- lookup_and_goto_ptr(ctx);
91
+ tcg_gen_lookup_and_goto_ptr();
92
93
if (misaligned) {
94
gen_set_label(misaligned);
95
@@ -XXX,XX +XXX,XX @@ static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
96
* however we need to end the translation block
97
*/
98
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
99
- exit_tb(ctx);
100
+ tcg_gen_exit_tb(NULL, 0);
101
ctx->base.is_jmp = DISAS_NORETURN;
102
return true;
103
}
104
@@ -XXX,XX +XXX,XX @@ static bool do_csr_post(DisasContext *ctx)
554
{
105
{
555
CPUTLGState *env = cs->env_ptr;
106
/* We may have changed important cpu state -- exit to main loop. */
556
DisasContext ctx;
107
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
557
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
108
- exit_tb(ctx);
558
uint64_t pc_start = tb->pc;
109
+ tcg_gen_exit_tb(NULL, 0);
559
uint64_t page_start = pc_start & TARGET_PAGE_MASK;
110
ctx->base.is_jmp = DISAS_NORETURN;
560
int num_insns = 0;
111
return true;
561
- int max_insns = tb_cflags(tb) & CF_COUNT_MASK;
112
}
562
113
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
563
dc->pc = pc_start;
564
dc->mmuidx = 0;
565
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
566
qemu_log_lock();
567
qemu_log("IN: %s\n", lookup_symbol(pc_start));
568
}
569
- if (!max_insns) {
570
- max_insns = CF_COUNT_MASK;
571
- }
572
- if (cs->singlestep_enabled || singlestep) {
573
- max_insns = 1;
574
- }
575
- if (max_insns > TCG_MAX_INSNS) {
576
- max_insns = TCG_MAX_INSNS;
577
- }
578
gen_tb_start(tb);
579
580
while (1) {
581
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
582
index XXXXXXX..XXXXXXX 100644
114
index XXXXXXX..XXXXXXX 100644
583
--- a/target/tricore/translate.c
115
--- a/target/riscv/insn_trans/trans_rvv.c.inc
584
+++ b/target/tricore/translate.c
116
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
585
@@ -XXX,XX +XXX,XX @@ static void decode_opc(CPUTriCoreState *env, DisasContext *ctx, int *is_branch)
117
@@ -XXX,XX +XXX,XX @@ static bool trans_vsetvl(DisasContext *ctx, arg_vsetvl *a)
586
}
118
gen_set_gpr(ctx, a->rd, dst);
119
120
tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
121
- lookup_and_goto_ptr(ctx);
122
+ tcg_gen_lookup_and_goto_ptr();
123
ctx->base.is_jmp = DISAS_NORETURN;
124
return true;
587
}
125
}
588
589
-void gen_intermediate_code(CPUState *cs, struct TranslationBlock *tb)
590
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
591
{
592
CPUTriCoreState *env = cs->env_ptr;
593
DisasContext ctx;
594
target_ulong pc_start;
595
- int num_insns, max_insns;
596
-
597
- num_insns = 0;
598
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
599
- if (max_insns == 0) {
600
- max_insns = CF_COUNT_MASK;
601
- }
602
- if (singlestep) {
603
- max_insns = 1;
604
- }
605
- if (max_insns > TCG_MAX_INSNS) {
606
- max_insns = TCG_MAX_INSNS;
607
- }
608
+ int num_insns = 0;
609
610
pc_start = tb->pc;
611
ctx.pc = pc_start;
612
diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c
613
index XXXXXXX..XXXXXXX 100644
614
--- a/target/unicore32/translate.c
615
+++ b/target/unicore32/translate.c
616
@@ -XXX,XX +XXX,XX @@ static void disas_uc32_insn(CPUUniCore32State *env, DisasContext *s)
617
}
618
619
/* generate intermediate code for basic block 'tb'. */
620
-void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
621
+void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns)
622
{
623
CPUUniCore32State *env = cs->env_ptr;
624
DisasContext dc1, *dc = &dc1;
625
target_ulong pc_start;
626
uint32_t page_start;
627
int num_insns;
628
- int max_insns;
629
630
/* generate intermediate code */
631
num_temps = 0;
632
@@ -XXX,XX +XXX,XX @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb)
633
cpu_F1d = tcg_temp_new_i64();
634
page_start = pc_start & TARGET_PAGE_MASK;
635
num_insns = 0;
636
- max_insns = tb_cflags(tb) & CF_COUNT_MASK;
637
- if (max_insns == 0) {
638
- max_insns = CF_COUNT_MASK;
639
- }
640
- if (max_insns > TCG_MAX_INSNS) {
641
- max_insns = TCG_MAX_INSNS;
642
- }
643
644
#ifndef CONFIG_USER_ONLY
645
if ((env->uncached_asr & ASR_M) == ASR_MODE_USER) {
646
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
647
index XXXXXXX..XXXXXXX 100644
648
--- a/target/xtensa/translate.c
649
+++ b/target/xtensa/translate.c
650
@@ -XXX,XX +XXX,XX @@ static const TranslatorOps xtensa_translator_ops = {
651
.disas_log = xtensa_tr_disas_log,
652
};
653
654
-void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb)
655
+void gen_intermediate_code(CPUState *cpu, TranslationBlock *tb, int max_insns)
656
{
657
DisasContext dc = {};
658
- translator_loop(&xtensa_translator_ops, &dc.base, cpu, tb);
659
+ translator_loop(&xtensa_translator_ops, &dc.base, cpu, tb, max_insns);
660
}
661
662
void xtensa_cpu_dump_state(CPUState *cs, FILE *f, int flags)
663
--
126
--
664
2.17.1
127
2.25.1
665
128
666
129
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/15] tcg/arm: Support INDEX_op_extract2_i32
[PULL 19/24] target/rx: Drop checks for singlestep_enabled
1
GDB single-stepping is now handled generically.
2
1
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
2
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
---
5
---
4
tcg/arm/tcg-target.h | 2 +-
6
target/rx/helper.h | 1 -
5
tcg/arm/tcg-target.inc.c | 25 +++++++++++++++++++++++++
7
target/rx/op_helper.c | 8 --------
6
2 files changed, 26 insertions(+), 1 deletion(-)
8
target/rx/translate.c | 12 ++----------
9
3 files changed, 2 insertions(+), 19 deletions(-)
7
10
8
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
11
diff --git a/target/rx/helper.h b/target/rx/helper.h
9
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
10
--- a/tcg/arm/tcg-target.h
13
--- a/target/rx/helper.h
11
+++ b/tcg/arm/tcg-target.h
14
+++ b/target/rx/helper.h
12
@@ -XXX,XX +XXX,XX @@ extern bool use_idiv_instructions;
15
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(raise_illegal_instruction, noreturn, env)
13
#define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions
16
DEF_HELPER_1(raise_access_fault, noreturn, env)
14
#define TCG_TARGET_HAS_extract_i32 use_armv7_instructions
17
DEF_HELPER_1(raise_privilege_violation, noreturn, env)
15
#define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions
18
DEF_HELPER_1(wait, noreturn, env)
16
-#define TCG_TARGET_HAS_extract2_i32 0
19
-DEF_HELPER_1(debug, noreturn, env)
17
+#define TCG_TARGET_HAS_extract2_i32 1
20
DEF_HELPER_2(rxint, noreturn, env, i32)
18
#define TCG_TARGET_HAS_movcond_i32 1
21
DEF_HELPER_1(rxbrk, noreturn, env)
19
#define TCG_TARGET_HAS_mulu2_i32 1
22
DEF_HELPER_FLAGS_3(fadd, TCG_CALL_NO_WG, f32, env, f32, f32)
20
#define TCG_TARGET_HAS_muls2_i32 1
23
diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c
21
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
22
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
23
--- a/tcg/arm/tcg-target.inc.c
25
--- a/target/rx/op_helper.c
24
+++ b/tcg/arm/tcg-target.inc.c
26
+++ b/target/rx/op_helper.c
25
@@ -XXX,XX +XXX,XX @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
27
@@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN helper_wait(CPURXState *env)
26
case INDEX_op_sextract_i32:
28
raise_exception(env, EXCP_HLT, 0);
27
tcg_out_sextract(s, COND_AL, args[0], args[1], args[2], args[3]);
29
}
30
31
-void QEMU_NORETURN helper_debug(CPURXState *env)
32
-{
33
- CPUState *cs = env_cpu(env);
34
-
35
- cs->exception_index = EXCP_DEBUG;
36
- cpu_loop_exit(cs);
37
-}
38
-
39
void QEMU_NORETURN helper_rxint(CPURXState *env, uint32_t vec)
40
{
41
raise_exception(env, 0x100 + vec, 0);
42
diff --git a/target/rx/translate.c b/target/rx/translate.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/target/rx/translate.c
45
+++ b/target/rx/translate.c
46
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
47
tcg_gen_exit_tb(dc->base.tb, n);
48
} else {
49
tcg_gen_movi_i32(cpu_pc, dest);
50
- if (dc->base.singlestep_enabled) {
51
- gen_helper_debug(cpu_env);
52
- } else {
53
- tcg_gen_lookup_and_goto_ptr();
54
- }
55
+ tcg_gen_lookup_and_goto_ptr();
56
}
57
dc->base.is_jmp = DISAS_NORETURN;
58
}
59
@@ -XXX,XX +XXX,XX @@ static void rx_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
60
gen_goto_tb(ctx, 0, dcbase->pc_next);
28
break;
61
break;
29
+ case INDEX_op_extract2_i32:
62
case DISAS_JUMP:
30
+ /* ??? These optimization vs zero should be generic. */
63
- if (ctx->base.singlestep_enabled) {
31
+ /* ??? But we can't substitute 2 for 1 in the opcode stream yet. */
64
- gen_helper_debug(cpu_env);
32
+ if (const_args[1]) {
65
- } else {
33
+ if (const_args[2]) {
66
- tcg_gen_lookup_and_goto_ptr();
34
+ tcg_out_movi(s, TCG_TYPE_REG, args[0], 0);
67
- }
35
+ } else {
68
+ tcg_gen_lookup_and_goto_ptr();
36
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0,
69
break;
37
+ args[2], SHIFT_IMM_LSL(32 - args[3]));
70
case DISAS_UPDATE:
38
+ }
71
tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
39
+ } else if (const_args[2]) {
40
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0,
41
+ args[1], SHIFT_IMM_LSR(args[3]));
42
+ } else {
43
+ /* We can do extract2 in 2 insns, vs the 3 required otherwise. */
44
+ tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0,
45
+ args[2], SHIFT_IMM_LSL(32 - args[3]));
46
+ tcg_out_dat_reg(s, COND_AL, ARITH_ORR, args[0], TCG_REG_TMP,
47
+ args[1], SHIFT_IMM_LSR(args[3]));
48
+ }
49
+ break;
50
51
case INDEX_op_div_i32:
52
tcg_out_sdiv(s, COND_AL, args[0], args[1], args[2]);
53
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
54
= { .args_ct_str = { "s", "s", "s", "s" } };
55
static const TCGTargetOpDef br
56
= { .args_ct_str = { "r", "rIN" } };
57
+ static const TCGTargetOpDef ext2
58
+ = { .args_ct_str = { "r", "rZ", "rZ" } };
59
static const TCGTargetOpDef dep
60
= { .args_ct_str = { "r", "0", "rZ" } };
61
static const TCGTargetOpDef movc
62
@@ -XXX,XX +XXX,XX @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
63
return &br;
64
case INDEX_op_deposit_i32:
65
return &dep;
66
+ case INDEX_op_extract2_i32:
67
+ return &ext2;
68
case INDEX_op_movcond_i32:
69
return &movc;
70
case INDEX_op_add2_i32:
71
--
72
--
72
2.17.1
73
2.25.1
73
74
74
75
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/15] tcg: Restart TB generation after relocation overflow
[PULL 20/24] target/s390x: Drop check for singlestep_enabled
1
If the TB generates too much code, such that backend relocations
1
GDB single-stepping is now handled generically.
2
overflow, try again with a smaller TB. In support of this, move
3
relocation processing from a random place within tcg_out_op, in
4
the handling of branch opcodes, to a new function at the end of
5
tcg_gen_code.
6
7
This is not a complete solution, as there are additional relocs
8
generated for out-of-line ldst handling and constant pools.
9
2
10
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
11
---
4
---
12
tcg/tcg.h | 15 +++++++-------
5
target/s390x/tcg/translate.c | 8 ++------
13
tcg/tcg.c | 61 ++++++++++++++++++++++++++-----------------------------
6
1 file changed, 2 insertions(+), 6 deletions(-)
14
2 files changed, 36 insertions(+), 40 deletions(-)
15
7
16
diff --git a/tcg/tcg.h b/tcg/tcg.h
8
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c
17
index XXXXXXX..XXXXXXX 100644
9
index XXXXXXX..XXXXXXX 100644
18
--- a/tcg/tcg.h
10
--- a/target/s390x/tcg/translate.c
19
+++ b/tcg/tcg.h
11
+++ b/target/s390x/tcg/translate.c
20
@@ -XXX,XX +XXX,XX @@ typedef uint64_t tcg_insn_unit;
12
@@ -XXX,XX +XXX,XX @@ struct DisasContext {
21
do { if (!(X)) { __builtin_unreachable(); } } while (0)
13
uint64_t pc_tmp;
22
#endif
14
uint32_t ilen;
23
15
enum cc_op cc_op;
24
-typedef struct TCGRelocation {
16
- bool do_debug;
25
- struct TCGRelocation *next;
26
- int type;
27
+typedef struct TCGRelocation TCGRelocation;
28
+struct TCGRelocation {
29
+ QSIMPLEQ_ENTRY(TCGRelocation) next;
30
tcg_insn_unit *ptr;
31
intptr_t addend;
32
-} TCGRelocation;
33
+ int type;
34
+};
35
36
typedef struct TCGLabel TCGLabel;
37
struct TCGLabel {
38
@@ -XXX,XX +XXX,XX @@ struct TCGLabel {
39
union {
40
uintptr_t value;
41
tcg_insn_unit *value_ptr;
42
- TCGRelocation *first_reloc;
43
} u;
44
-#ifdef CONFIG_DEBUG_TCG
45
+ QSIMPLEQ_HEAD(, TCGRelocation) relocs;
46
QSIMPLEQ_ENTRY(TCGLabel) next;
47
-#endif
48
};
17
};
49
18
50
typedef struct TCGPool {
19
/* Information carried about a condition to be evaluated. */
51
@@ -XXX,XX +XXX,XX @@ struct TCGContext {
20
@@ -XXX,XX +XXX,XX @@ static void s390x_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
52
#endif
21
53
22
dc->cc_op = CC_OP_DYNAMIC;
54
#ifdef CONFIG_DEBUG_TCG
23
dc->ex_value = dc->base.tb->cs_base;
55
- QSIMPLEQ_HEAD(, TCGLabel) labels;
24
- dc->do_debug = dc->base.singlestep_enabled;
56
int temps_in_use;
57
int goto_tb_issue_mask;
58
#endif
59
@@ -XXX,XX +XXX,XX @@ struct TCGContext {
60
TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */
61
62
QTAILQ_HEAD(, TCGOp) ops, free_ops;
63
+ QSIMPLEQ_HEAD(, TCGLabel) labels;
64
65
/* Tells which temporary holds a given register.
66
It does not take into account fixed registers */
67
diff --git a/tcg/tcg.c b/tcg/tcg.c
68
index XXXXXXX..XXXXXXX 100644
69
--- a/tcg/tcg.c
70
+++ b/tcg/tcg.c
71
@@ -XXX,XX +XXX,XX @@ static __attribute__((unused)) inline void tcg_patch64(tcg_insn_unit *p,
72
static void tcg_out_reloc(TCGContext *s, tcg_insn_unit *code_ptr, int type,
73
TCGLabel *l, intptr_t addend)
74
{
75
- TCGRelocation *r;
76
+ TCGRelocation *r = tcg_malloc(sizeof(TCGRelocation));
77
78
- if (l->has_value) {
79
- /* FIXME: This may break relocations on RISC targets that
80
- modify instruction fields in place. The caller may not have
81
- written the initial value. */
82
- bool ok = patch_reloc(code_ptr, type, l->u.value, addend);
83
- tcg_debug_assert(ok);
84
- } else {
85
- /* add a new relocation entry */
86
- r = tcg_malloc(sizeof(TCGRelocation));
87
- r->type = type;
88
- r->ptr = code_ptr;
89
- r->addend = addend;
90
- r->next = l->u.first_reloc;
91
- l->u.first_reloc = r;
92
- }
93
+ r->type = type;
94
+ r->ptr = code_ptr;
95
+ r->addend = addend;
96
+ QSIMPLEQ_INSERT_TAIL(&l->relocs, r, next);
97
}
25
}
98
26
99
static void tcg_out_label(TCGContext *s, TCGLabel *l, tcg_insn_unit *ptr)
27
static void s390x_tr_tb_start(DisasContextBase *db, CPUState *cs)
100
{
28
@@ -XXX,XX +XXX,XX @@ static void s390x_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
101
- intptr_t value = (intptr_t)ptr;
29
/* FALLTHRU */
102
- TCGRelocation *r;
30
case DISAS_PC_CC_UPDATED:
103
-
31
/* Exit the TB, either by raising a debug exception or by return. */
104
tcg_debug_assert(!l->has_value);
32
- if (dc->do_debug) {
105
-
33
- gen_exception(EXCP_DEBUG);
106
- for (r = l->u.first_reloc; r != NULL; r = r->next) {
34
- } else if ((dc->base.tb->flags & FLAG_MASK_PER) ||
107
- bool ok = patch_reloc(r->ptr, r->type, value, r->addend);
35
- dc->base.is_jmp == DISAS_PC_STALE_NOCHAIN) {
108
- tcg_debug_assert(ok);
36
+ if ((dc->base.tb->flags & FLAG_MASK_PER) ||
109
- }
37
+ dc->base.is_jmp == DISAS_PC_STALE_NOCHAIN) {
110
-
38
tcg_gen_exit_tb(NULL, 0);
111
l->has_value = 1;
39
} else {
112
l->u.value_ptr = ptr;
40
tcg_gen_lookup_and_goto_ptr();
113
}
114
@@ -XXX,XX +XXX,XX @@ TCGLabel *gen_new_label(void)
115
TCGContext *s = tcg_ctx;
116
TCGLabel *l = tcg_malloc(sizeof(TCGLabel));
117
118
- *l = (TCGLabel){
119
- .id = s->nb_labels++
120
- };
121
-#ifdef CONFIG_DEBUG_TCG
122
+ memset(l, 0, sizeof(TCGLabel));
123
+ l->id = s->nb_labels++;
124
+ QSIMPLEQ_INIT(&l->relocs);
125
+
126
QSIMPLEQ_INSERT_TAIL(&s->labels, l, next);
127
-#endif
128
129
return l;
130
}
131
132
+static bool tcg_resolve_relocs(TCGContext *s)
133
+{
134
+ TCGLabel *l;
135
+
136
+ QSIMPLEQ_FOREACH(l, &s->labels, next) {
137
+ TCGRelocation *r;
138
+ uintptr_t value = l->u.value;
139
+
140
+ QSIMPLEQ_FOREACH(r, &l->relocs, next) {
141
+ if (!patch_reloc(r->ptr, r->type, value, r->addend)) {
142
+ return false;
143
+ }
144
+ }
145
+ }
146
+ return true;
147
+}
148
+
149
static void set_jmp_reset_offset(TCGContext *s, int which)
150
{
151
size_t off = tcg_current_code_size(s);
152
@@ -XXX,XX +XXX,XX @@ void tcg_func_start(TCGContext *s)
153
154
QTAILQ_INIT(&s->ops);
155
QTAILQ_INIT(&s->free_ops);
156
-#ifdef CONFIG_DEBUG_TCG
157
QSIMPLEQ_INIT(&s->labels);
158
-#endif
159
}
160
161
static inline TCGTemp *tcg_temp_alloc(TCGContext *s)
162
@@ -XXX,XX +XXX,XX @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb)
163
return -1;
164
}
165
#endif
166
+ if (!tcg_resolve_relocs(s)) {
167
+ return -2;
168
+ }
169
170
/* flush instruction cache */
171
flush_icache_range((uintptr_t)s->code_buf, (uintptr_t)s->code_ptr);
172
--
41
--
173
2.17.1
42
2.25.1
174
43
175
44
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/15] tcg: Add INDEX_op_extract2_{i32,i64}
[PULL 21/24] target/sh4: Drop check for singlestep_enabled
1
This will let backends implement the double-word shift operation.
1
GDB single-stepping is now handled generically.
2
2
3
Reviewed-by: David Hildenbrand <david@redhat.com>
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
---
5
---
6
tcg/aarch64/tcg-target.h | 2 ++
6
target/sh4/helper.h | 1 -
7
tcg/arm/tcg-target.h | 1 +
7
target/sh4/op_helper.c | 5 -----
8
tcg/i386/tcg-target.h | 2 ++
8
target/sh4/translate.c | 14 +++-----------
9
tcg/mips/tcg-target.h | 2 ++
9
3 files changed, 3 insertions(+), 17 deletions(-)
10
tcg/ppc/tcg-target.h | 2 ++
11
tcg/riscv/tcg-target.h | 2 ++
12
tcg/s390/tcg-target.h | 2 ++
13
tcg/sparc/tcg-target.h | 2 ++
14
tcg/tcg-opc.h | 2 ++
15
tcg/tcg.h | 1 +
16
tcg/tci/tcg-target.h | 2 ++
17
tcg/optimize.c | 16 ++++++++++++++++
18
tcg/tcg-op.c | 4 ++++
19
tcg/tcg.c | 4 ++++
20
tcg/README | 7 +++++++
21
15 files changed, 51 insertions(+)
22
10
23
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
11
diff --git a/target/sh4/helper.h b/target/sh4/helper.h
24
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
25
--- a/tcg/aarch64/tcg-target.h
13
--- a/target/sh4/helper.h
26
+++ b/tcg/aarch64/tcg-target.h
14
+++ b/target/sh4/helper.h
27
@@ -XXX,XX +XXX,XX @@ typedef enum {
15
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_1(raise_illegal_instruction, noreturn, env)
28
#define TCG_TARGET_HAS_deposit_i32 1
16
DEF_HELPER_1(raise_slot_illegal_instruction, noreturn, env)
29
#define TCG_TARGET_HAS_extract_i32 1
17
DEF_HELPER_1(raise_fpu_disable, noreturn, env)
30
#define TCG_TARGET_HAS_sextract_i32 1
18
DEF_HELPER_1(raise_slot_fpu_disable, noreturn, env)
31
+#define TCG_TARGET_HAS_extract2_i32 0
19
-DEF_HELPER_1(debug, noreturn, env)
32
#define TCG_TARGET_HAS_movcond_i32 1
20
DEF_HELPER_1(sleep, noreturn, env)
33
#define TCG_TARGET_HAS_add2_i32 1
21
DEF_HELPER_2(trapa, noreturn, env, i32)
34
#define TCG_TARGET_HAS_sub2_i32 1
22
DEF_HELPER_1(exclusive, noreturn, env)
35
@@ -XXX,XX +XXX,XX @@ typedef enum {
23
diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
36
#define TCG_TARGET_HAS_deposit_i64 1
37
#define TCG_TARGET_HAS_extract_i64 1
38
#define TCG_TARGET_HAS_sextract_i64 1
39
+#define TCG_TARGET_HAS_extract2_i64 0
40
#define TCG_TARGET_HAS_movcond_i64 1
41
#define TCG_TARGET_HAS_add2_i64 1
42
#define TCG_TARGET_HAS_sub2_i64 1
43
diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
44
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
45
--- a/tcg/arm/tcg-target.h
25
--- a/target/sh4/op_helper.c
46
+++ b/tcg/arm/tcg-target.h
26
+++ b/target/sh4/op_helper.c
47
@@ -XXX,XX +XXX,XX @@ extern bool use_idiv_instructions;
27
@@ -XXX,XX +XXX,XX @@ void helper_raise_slot_fpu_disable(CPUSH4State *env)
48
#define TCG_TARGET_HAS_deposit_i32 use_armv7_instructions
28
raise_exception(env, 0x820, 0);
49
#define TCG_TARGET_HAS_extract_i32 use_armv7_instructions
29
}
50
#define TCG_TARGET_HAS_sextract_i32 use_armv7_instructions
30
51
+#define TCG_TARGET_HAS_extract2_i32 0
31
-void helper_debug(CPUSH4State *env)
52
#define TCG_TARGET_HAS_movcond_i32 1
32
-{
53
#define TCG_TARGET_HAS_mulu2_i32 1
33
- raise_exception(env, EXCP_DEBUG, 0);
54
#define TCG_TARGET_HAS_muls2_i32 1
34
-}
55
diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
35
-
36
void helper_sleep(CPUSH4State *env)
37
{
38
CPUState *cs = env_cpu(env);
39
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
56
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
57
--- a/tcg/i386/tcg-target.h
41
--- a/target/sh4/translate.c
58
+++ b/tcg/i386/tcg-target.h
42
+++ b/target/sh4/translate.c
59
@@ -XXX,XX +XXX,XX @@ extern bool have_avx2;
43
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
60
#define TCG_TARGET_HAS_deposit_i32 1
44
tcg_gen_exit_tb(ctx->base.tb, n);
61
#define TCG_TARGET_HAS_extract_i32 1
62
#define TCG_TARGET_HAS_sextract_i32 1
63
+#define TCG_TARGET_HAS_extract2_i32 0
64
#define TCG_TARGET_HAS_movcond_i32 1
65
#define TCG_TARGET_HAS_add2_i32 1
66
#define TCG_TARGET_HAS_sub2_i32 1
67
@@ -XXX,XX +XXX,XX @@ extern bool have_avx2;
68
#define TCG_TARGET_HAS_deposit_i64 1
69
#define TCG_TARGET_HAS_extract_i64 1
70
#define TCG_TARGET_HAS_sextract_i64 0
71
+#define TCG_TARGET_HAS_extract2_i64 0
72
#define TCG_TARGET_HAS_movcond_i64 1
73
#define TCG_TARGET_HAS_add2_i64 1
74
#define TCG_TARGET_HAS_sub2_i64 1
75
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
76
index XXXXXXX..XXXXXXX 100644
77
--- a/tcg/mips/tcg-target.h
78
+++ b/tcg/mips/tcg-target.h
79
@@ -XXX,XX +XXX,XX @@ extern bool use_mips32r2_instructions;
80
#define TCG_TARGET_HAS_deposit_i32 use_mips32r2_instructions
81
#define TCG_TARGET_HAS_extract_i32 use_mips32r2_instructions
82
#define TCG_TARGET_HAS_sextract_i32 0
83
+#define TCG_TARGET_HAS_extract2_i32 0
84
#define TCG_TARGET_HAS_ext8s_i32 use_mips32r2_instructions
85
#define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions
86
#define TCG_TARGET_HAS_rot_i32 use_mips32r2_instructions
87
@@ -XXX,XX +XXX,XX @@ extern bool use_mips32r2_instructions;
88
#define TCG_TARGET_HAS_deposit_i64 use_mips32r2_instructions
89
#define TCG_TARGET_HAS_extract_i64 use_mips32r2_instructions
90
#define TCG_TARGET_HAS_sextract_i64 0
91
+#define TCG_TARGET_HAS_extract2_i64 0
92
#define TCG_TARGET_HAS_ext8s_i64 use_mips32r2_instructions
93
#define TCG_TARGET_HAS_ext16s_i64 use_mips32r2_instructions
94
#define TCG_TARGET_HAS_rot_i64 use_mips32r2_instructions
95
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
96
index XXXXXXX..XXXXXXX 100644
97
--- a/tcg/ppc/tcg-target.h
98
+++ b/tcg/ppc/tcg-target.h
99
@@ -XXX,XX +XXX,XX @@ extern bool have_isa_3_00;
100
#define TCG_TARGET_HAS_deposit_i32 1
101
#define TCG_TARGET_HAS_extract_i32 1
102
#define TCG_TARGET_HAS_sextract_i32 0
103
+#define TCG_TARGET_HAS_extract2_i32 0
104
#define TCG_TARGET_HAS_movcond_i32 1
105
#define TCG_TARGET_HAS_mulu2_i32 0
106
#define TCG_TARGET_HAS_muls2_i32 0
107
@@ -XXX,XX +XXX,XX @@ extern bool have_isa_3_00;
108
#define TCG_TARGET_HAS_deposit_i64 1
109
#define TCG_TARGET_HAS_extract_i64 1
110
#define TCG_TARGET_HAS_sextract_i64 0
111
+#define TCG_TARGET_HAS_extract2_i64 0
112
#define TCG_TARGET_HAS_movcond_i64 1
113
#define TCG_TARGET_HAS_add2_i64 1
114
#define TCG_TARGET_HAS_sub2_i64 1
115
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
116
index XXXXXXX..XXXXXXX 100644
117
--- a/tcg/riscv/tcg-target.h
118
+++ b/tcg/riscv/tcg-target.h
119
@@ -XXX,XX +XXX,XX @@ typedef enum {
120
#define TCG_TARGET_HAS_deposit_i32 0
121
#define TCG_TARGET_HAS_extract_i32 0
122
#define TCG_TARGET_HAS_sextract_i32 0
123
+#define TCG_TARGET_HAS_extract2_i32 0
124
#define TCG_TARGET_HAS_add2_i32 1
125
#define TCG_TARGET_HAS_sub2_i32 1
126
#define TCG_TARGET_HAS_mulu2_i32 0
127
@@ -XXX,XX +XXX,XX @@ typedef enum {
128
#define TCG_TARGET_HAS_deposit_i64 0
129
#define TCG_TARGET_HAS_extract_i64 0
130
#define TCG_TARGET_HAS_sextract_i64 0
131
+#define TCG_TARGET_HAS_extract2_i64 0
132
#define TCG_TARGET_HAS_extrl_i64_i32 1
133
#define TCG_TARGET_HAS_extrh_i64_i32 1
134
#define TCG_TARGET_HAS_ext8s_i64 1
135
diff --git a/tcg/s390/tcg-target.h b/tcg/s390/tcg-target.h
136
index XXXXXXX..XXXXXXX 100644
137
--- a/tcg/s390/tcg-target.h
138
+++ b/tcg/s390/tcg-target.h
139
@@ -XXX,XX +XXX,XX @@ extern uint64_t s390_facilities;
140
#define TCG_TARGET_HAS_deposit_i32 (s390_facilities & FACILITY_GEN_INST_EXT)
141
#define TCG_TARGET_HAS_extract_i32 (s390_facilities & FACILITY_GEN_INST_EXT)
142
#define TCG_TARGET_HAS_sextract_i32 0
143
+#define TCG_TARGET_HAS_extract2_i32 0
144
#define TCG_TARGET_HAS_movcond_i32 1
145
#define TCG_TARGET_HAS_add2_i32 1
146
#define TCG_TARGET_HAS_sub2_i32 1
147
@@ -XXX,XX +XXX,XX @@ extern uint64_t s390_facilities;
148
#define TCG_TARGET_HAS_deposit_i64 (s390_facilities & FACILITY_GEN_INST_EXT)
149
#define TCG_TARGET_HAS_extract_i64 (s390_facilities & FACILITY_GEN_INST_EXT)
150
#define TCG_TARGET_HAS_sextract_i64 0
151
+#define TCG_TARGET_HAS_extract2_i64 0
152
#define TCG_TARGET_HAS_movcond_i64 1
153
#define TCG_TARGET_HAS_add2_i64 1
154
#define TCG_TARGET_HAS_sub2_i64 1
155
diff --git a/tcg/sparc/tcg-target.h b/tcg/sparc/tcg-target.h
156
index XXXXXXX..XXXXXXX 100644
157
--- a/tcg/sparc/tcg-target.h
158
+++ b/tcg/sparc/tcg-target.h
159
@@ -XXX,XX +XXX,XX @@ extern bool use_vis3_instructions;
160
#define TCG_TARGET_HAS_deposit_i32 0
161
#define TCG_TARGET_HAS_extract_i32 0
162
#define TCG_TARGET_HAS_sextract_i32 0
163
+#define TCG_TARGET_HAS_extract2_i32 0
164
#define TCG_TARGET_HAS_movcond_i32 1
165
#define TCG_TARGET_HAS_add2_i32 1
166
#define TCG_TARGET_HAS_sub2_i32 1
167
@@ -XXX,XX +XXX,XX @@ extern bool use_vis3_instructions;
168
#define TCG_TARGET_HAS_deposit_i64 0
169
#define TCG_TARGET_HAS_extract_i64 0
170
#define TCG_TARGET_HAS_sextract_i64 0
171
+#define TCG_TARGET_HAS_extract2_i64 0
172
#define TCG_TARGET_HAS_movcond_i64 1
173
#define TCG_TARGET_HAS_add2_i64 1
174
#define TCG_TARGET_HAS_sub2_i64 1
175
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
176
index XXXXXXX..XXXXXXX 100644
177
--- a/tcg/tcg-opc.h
178
+++ b/tcg/tcg-opc.h
179
@@ -XXX,XX +XXX,XX @@ DEF(rotr_i32, 1, 2, 0, IMPL(TCG_TARGET_HAS_rot_i32))
180
DEF(deposit_i32, 1, 2, 2, IMPL(TCG_TARGET_HAS_deposit_i32))
181
DEF(extract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_extract_i32))
182
DEF(sextract_i32, 1, 1, 2, IMPL(TCG_TARGET_HAS_sextract_i32))
183
+DEF(extract2_i32, 1, 2, 1, IMPL(TCG_TARGET_HAS_extract2_i32))
184
185
DEF(brcond_i32, 0, 2, 2, TCG_OPF_BB_END)
186
187
@@ -XXX,XX +XXX,XX @@ DEF(rotr_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_rot_i64))
188
DEF(deposit_i64, 1, 2, 2, IMPL64 | IMPL(TCG_TARGET_HAS_deposit_i64))
189
DEF(extract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_extract_i64))
190
DEF(sextract_i64, 1, 1, 2, IMPL64 | IMPL(TCG_TARGET_HAS_sextract_i64))
191
+DEF(extract2_i64, 1, 2, 1, IMPL64 | IMPL(TCG_TARGET_HAS_extract2_i64))
192
193
/* size changing ops */
194
DEF(ext_i32_i64, 1, 1, 0, IMPL64)
195
diff --git a/tcg/tcg.h b/tcg/tcg.h
196
index XXXXXXX..XXXXXXX 100644
197
--- a/tcg/tcg.h
198
+++ b/tcg/tcg.h
199
@@ -XXX,XX +XXX,XX @@ typedef uint64_t TCGRegSet;
200
#define TCG_TARGET_HAS_deposit_i64 0
201
#define TCG_TARGET_HAS_extract_i64 0
202
#define TCG_TARGET_HAS_sextract_i64 0
203
+#define TCG_TARGET_HAS_extract2_i64 0
204
#define TCG_TARGET_HAS_movcond_i64 0
205
#define TCG_TARGET_HAS_add2_i64 0
206
#define TCG_TARGET_HAS_sub2_i64 0
207
diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h
208
index XXXXXXX..XXXXXXX 100644
209
--- a/tcg/tci/tcg-target.h
210
+++ b/tcg/tci/tcg-target.h
211
@@ -XXX,XX +XXX,XX @@
212
#define TCG_TARGET_HAS_deposit_i32 1
213
#define TCG_TARGET_HAS_extract_i32 0
214
#define TCG_TARGET_HAS_sextract_i32 0
215
+#define TCG_TARGET_HAS_extract2_i32 0
216
#define TCG_TARGET_HAS_eqv_i32 0
217
#define TCG_TARGET_HAS_nand_i32 0
218
#define TCG_TARGET_HAS_nor_i32 0
219
@@ -XXX,XX +XXX,XX @@
220
#define TCG_TARGET_HAS_deposit_i64 1
221
#define TCG_TARGET_HAS_extract_i64 0
222
#define TCG_TARGET_HAS_sextract_i64 0
223
+#define TCG_TARGET_HAS_extract2_i64 0
224
#define TCG_TARGET_HAS_div_i64 0
225
#define TCG_TARGET_HAS_rem_i64 0
226
#define TCG_TARGET_HAS_ext8s_i64 1
227
diff --git a/tcg/optimize.c b/tcg/optimize.c
228
index XXXXXXX..XXXXXXX 100644
229
--- a/tcg/optimize.c
230
+++ b/tcg/optimize.c
231
@@ -XXX,XX +XXX,XX @@ void tcg_optimize(TCGContext *s)
232
}
233
goto do_default;
234
235
+ CASE_OP_32_64(extract2):
236
+ if (arg_is_const(op->args[1]) && arg_is_const(op->args[2])) {
237
+ TCGArg v1 = arg_info(op->args[1])->val;
238
+ TCGArg v2 = arg_info(op->args[2])->val;
239
+
240
+ if (opc == INDEX_op_extract2_i64) {
241
+ tmp = (v1 >> op->args[3]) | (v2 << (64 - op->args[3]));
242
+ } else {
243
+ tmp = (v1 >> op->args[3]) | (v2 << (32 - op->args[3]));
244
+ tmp = (int32_t)tmp;
245
+ }
246
+ tcg_opt_gen_movi(s, op, op->args[0], tmp);
247
+ break;
248
+ }
249
+ goto do_default;
250
+
251
CASE_OP_32_64(setcond):
252
tmp = do_constant_folding_cond(opc, op->args[1],
253
op->args[2], op->args[3]);
254
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
255
index XXXXXXX..XXXXXXX 100644
256
--- a/tcg/tcg-op.c
257
+++ b/tcg/tcg-op.c
258
@@ -XXX,XX +XXX,XX @@ void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah,
259
tcg_gen_mov_i32(ret, ah);
260
} else if (al == ah) {
261
tcg_gen_rotri_i32(ret, al, ofs);
262
+ } else if (TCG_TARGET_HAS_extract2_i32) {
263
+ tcg_gen_op4i_i32(INDEX_op_extract2_i32, ret, al, ah, ofs);
264
} else {
45
} else {
265
TCGv_i32 t0 = tcg_temp_new_i32();
46
tcg_gen_movi_i32(cpu_pc, dest);
266
tcg_gen_shri_i32(t0, al, ofs);
47
- if (ctx->base.singlestep_enabled) {
267
@@ -XXX,XX +XXX,XX @@ void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah,
48
- gen_helper_debug(cpu_env);
268
tcg_gen_mov_i64(ret, ah);
49
- } else if (use_exit_tb(ctx)) {
269
} else if (al == ah) {
50
+ if (use_exit_tb(ctx)) {
270
tcg_gen_rotri_i64(ret, al, ofs);
51
tcg_gen_exit_tb(NULL, 0);
271
+ } else if (TCG_TARGET_HAS_extract2_i64) {
52
} else {
272
+ tcg_gen_op4i_i64(INDEX_op_extract2_i64, ret, al, ah, ofs);
53
tcg_gen_lookup_and_goto_ptr();
273
} else {
54
@@ -XXX,XX +XXX,XX @@ static void gen_jump(DisasContext * ctx)
274
TCGv_i64 t0 = tcg_temp_new_i64();
55
     delayed jump as immediate jump are conditinal jumps */
275
tcg_gen_shri_i64(t0, al, ofs);
56
    tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc);
276
diff --git a/tcg/tcg.c b/tcg/tcg.c
57
tcg_gen_discard_i32(cpu_delayed_pc);
277
index XXXXXXX..XXXXXXX 100644
58
- if (ctx->base.singlestep_enabled) {
278
--- a/tcg/tcg.c
59
- gen_helper_debug(cpu_env);
279
+++ b/tcg/tcg.c
60
- } else if (use_exit_tb(ctx)) {
280
@@ -XXX,XX +XXX,XX @@ bool tcg_op_supported(TCGOpcode op)
61
+ if (use_exit_tb(ctx)) {
281
return TCG_TARGET_HAS_extract_i32;
62
tcg_gen_exit_tb(NULL, 0);
282
case INDEX_op_sextract_i32:
63
} else {
283
return TCG_TARGET_HAS_sextract_i32;
64
tcg_gen_lookup_and_goto_ptr();
284
+ case INDEX_op_extract2_i32:
65
@@ -XXX,XX +XXX,XX @@ static void sh4_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
285
+ return TCG_TARGET_HAS_extract2_i32;
66
switch (ctx->base.is_jmp) {
286
case INDEX_op_add2_i32:
67
case DISAS_STOP:
287
return TCG_TARGET_HAS_add2_i32;
68
gen_save_cpu_state(ctx, true);
288
case INDEX_op_sub2_i32:
69
- if (ctx->base.singlestep_enabled) {
289
@@ -XXX,XX +XXX,XX @@ bool tcg_op_supported(TCGOpcode op)
70
- gen_helper_debug(cpu_env);
290
return TCG_TARGET_HAS_extract_i64;
71
- } else {
291
case INDEX_op_sextract_i64:
72
- tcg_gen_exit_tb(NULL, 0);
292
return TCG_TARGET_HAS_sextract_i64;
73
- }
293
+ case INDEX_op_extract2_i64:
74
+ tcg_gen_exit_tb(NULL, 0);
294
+ return TCG_TARGET_HAS_extract2_i64;
75
break;
295
case INDEX_op_extrl_i64_i32:
76
case DISAS_NEXT:
296
return TCG_TARGET_HAS_extrl_i64_i32;
77
case DISAS_TOO_MANY:
297
case INDEX_op_extrh_i64_i32:
298
diff --git a/tcg/README b/tcg/README
299
index XXXXXXX..XXXXXXX 100644
300
--- a/tcg/README
301
+++ b/tcg/README
302
@@ -XXX,XX +XXX,XX @@ at bit 8. This operation would be equivalent to
303
304
(using an arithmetic right shift).
305
306
+* extract2_i32/i64 dest, t1, t2, pos
307
+
308
+For N = {32,64}, extract an N-bit quantity from the concatenation
309
+of t2:t1, beginning at pos. The tcg_gen_extract2_{i32,i64} expander
310
+accepts 0 <= pos <= N as inputs. The backend code generator will
311
+not see either 0 or N as inputs for these opcodes.
312
+
313
* extrl_i64_i32 t0, t1
314
315
For 64-bit hosts only, extract the low 32-bits of input T1 and place it
316
--
78
--
317
2.17.1
79
2.25.1
318
80
319
81
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/15] tcg: Use deposit and extract2 in tcg_gen_shifti_i64
[PULL 22/24] target/tricore: Drop check for singlestep_enabled
1
GDB single-stepping is now handled generically.
2
3
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
1
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2
---
5
---
3
tcg/tcg-op.c | 47 ++++++++++++++++++++++++-----------------------
6
target/tricore/helper.h | 1 -
4
1 file changed, 24 insertions(+), 23 deletions(-)
7
target/tricore/op_helper.c | 7 -------
8
target/tricore/translate.c | 14 +-------------
9
3 files changed, 1 insertion(+), 21 deletions(-)
5
10
6
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
11
diff --git a/target/tricore/helper.h b/target/tricore/helper.h
7
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
8
--- a/tcg/tcg-op.c
13
--- a/target/tricore/helper.h
9
+++ b/tcg/tcg-op.c
14
+++ b/target/tricore/helper.h
10
@@ -XXX,XX +XXX,XX @@ static inline void tcg_gen_shifti_i64(TCGv_i64 ret, TCGv_i64 arg1,
15
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(psw_write, void, env, i32)
11
tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_LOW(arg1), c);
16
DEF_HELPER_1(psw_read, i32, env)
12
tcg_gen_movi_i32(TCGV_LOW(ret), 0);
17
/* Exceptions */
13
}
18
DEF_HELPER_3(raise_exception_sync, noreturn, env, i32, i32)
14
- } else {
19
-DEF_HELPER_2(qemu_excp, noreturn, env, i32)
15
- TCGv_i32 t0, t1;
20
diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/tricore/op_helper.c
23
+++ b/target/tricore/op_helper.c
24
@@ -XXX,XX +XXX,XX @@ static void raise_exception_sync_helper(CPUTriCoreState *env, uint32_t class,
25
raise_exception_sync_internal(env, class, tin, pc, 0);
26
}
27
28
-void helper_qemu_excp(CPUTriCoreState *env, uint32_t excp)
29
-{
30
- CPUState *cs = env_cpu(env);
31
- cs->exception_index = excp;
32
- cpu_loop_exit(cs);
33
-}
16
-
34
-
17
- t0 = tcg_temp_new_i32();
35
/* Addressing mode helper */
18
- t1 = tcg_temp_new_i32();
36
19
- if (right) {
37
static uint16_t reverse16(uint16_t val)
20
- tcg_gen_shli_i32(t0, TCGV_HIGH(arg1), 32 - c);
38
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
21
- if (arith) {
39
index XXXXXXX..XXXXXXX 100644
22
- tcg_gen_sari_i32(t1, TCGV_HIGH(arg1), c);
40
--- a/target/tricore/translate.c
23
- } else {
41
+++ b/target/tricore/translate.c
24
- tcg_gen_shri_i32(t1, TCGV_HIGH(arg1), c);
42
@@ -XXX,XX +XXX,XX @@ static inline void gen_save_pc(target_ulong pc)
25
- }
43
tcg_gen_movi_tl(cpu_PC, pc);
26
- tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
44
}
27
- tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t0);
45
28
- tcg_gen_mov_i32(TCGV_HIGH(ret), t1);
46
-static void generate_qemu_excp(DisasContext *ctx, int excp)
29
+ } else if (right) {
47
-{
30
+ if (TCG_TARGET_HAS_extract2_i32) {
48
- TCGv_i32 tmp = tcg_const_i32(excp);
31
+ tcg_gen_extract2_i32(TCGV_LOW(ret),
49
- gen_helper_qemu_excp(cpu_env, tmp);
32
+ TCGV_LOW(arg1), TCGV_HIGH(arg1), c);
50
- ctx->base.is_jmp = DISAS_NORETURN;
33
} else {
51
- tcg_temp_free(tmp);
34
- tcg_gen_shri_i32(t0, TCGV_LOW(arg1), 32 - c);
52
-}
35
- /* Note: ret can be the same as arg1, so we use t1 */
53
-
36
- tcg_gen_shli_i32(t1, TCGV_LOW(arg1), c);
54
static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
37
- tcg_gen_shli_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
55
{
38
- tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t0);
56
if (translator_use_goto_tb(&ctx->base, dest)) {
39
- tcg_gen_mov_i32(TCGV_LOW(ret), t1);
57
@@ -XXX,XX +XXX,XX @@ static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
40
+ tcg_gen_shri_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
58
tcg_gen_exit_tb(ctx->base.tb, n);
41
+ tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(ret),
59
} else {
42
+ TCGV_HIGH(arg1), 32 - c, c);
60
gen_save_pc(dest);
43
}
61
- if (ctx->base.singlestep_enabled) {
44
- tcg_temp_free_i32(t0);
62
- generate_qemu_excp(ctx, EXCP_DEBUG);
45
- tcg_temp_free_i32(t1);
63
- } else {
46
+ if (arith) {
64
- tcg_gen_lookup_and_goto_ptr();
47
+ tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
65
- }
48
+ } else {
66
+ tcg_gen_lookup_and_goto_ptr();
49
+ tcg_gen_shri_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
50
+ }
51
+ } else {
52
+ if (TCG_TARGET_HAS_extract2_i32) {
53
+ tcg_gen_extract2_i32(TCGV_HIGH(ret),
54
+ TCGV_LOW(arg1), TCGV_HIGH(arg1), 32 - c);
55
+ } else {
56
+ TCGv_i32 t0 = tcg_temp_new_i32();
57
+ tcg_gen_shri_i32(t0, TCGV_LOW(arg1), 32 - c);
58
+ tcg_gen_deposit_i32(TCGV_HIGH(ret), t0,
59
+ TCGV_HIGH(arg1), c, 32 - c);
60
+ tcg_temp_free_i32(t0);
61
+ }
62
+ tcg_gen_shli_i32(TCGV_LOW(ret), TCGV_LOW(arg1), c);
63
}
67
}
64
}
68
}
65
69
66
--
70
--
67
2.17.1
71
2.25.1
68
72
69
73
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/15] tcg/ppc: Allow the constant pool to overflow at 32k
[PULL 23/24] target/xtensa: Drop check for singlestep_enabled
1
There is no point in coding for a 2GB offset when the max TB size
1
GDB single-stepping is now handled generically.
2
is already limited to 64k. If we further restrict to 32k then we
3
can eliminate the extra ADDIS instruction.
4
2
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
---
4
---
7
tcg/ppc/tcg-target.inc.c | 28 ++++++++++------------------
5
target/xtensa/translate.c | 25 ++++++++-----------------
8
1 file changed, 10 insertions(+), 18 deletions(-)
6
1 file changed, 8 insertions(+), 17 deletions(-)
9
7
10
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
8
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
11
index XXXXXXX..XXXXXXX 100644
9
index XXXXXXX..XXXXXXX 100644
12
--- a/tcg/ppc/tcg-target.inc.c
10
--- a/target/xtensa/translate.c
13
+++ b/tcg/ppc/tcg-target.inc.c
11
+++ b/target/xtensa/translate.c
14
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
12
@@ -XXX,XX +XXX,XX @@ static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
15
intptr_t value, intptr_t addend)
13
if (dc->icount) {
16
{
14
tcg_gen_mov_i32(cpu_SR[ICOUNT], dc->next_icount);
17
tcg_insn_unit *target;
15
}
18
- tcg_insn_unit old;
16
- if (dc->base.singlestep_enabled) {
19
17
- gen_exception(dc, EXCP_DEBUG);
20
value += addend;
18
+ if (dc->op_flags & XTENSA_OP_POSTPROCESS) {
21
target = (tcg_insn_unit *)value;
19
+ slot = gen_postprocess(dc, slot);
22
@@ -XXX,XX +XXX,XX @@ static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
20
+ }
23
case R_PPC_REL24:
21
+ if (slot >= 0) {
24
return reloc_pc24(code_ptr, target);
22
+ tcg_gen_goto_tb(slot);
25
case R_PPC_ADDR16:
23
+ tcg_gen_exit_tb(dc->base.tb, slot);
26
- /* We are abusing this relocation type. This points to a pair
24
} else {
27
- of insns, addis + load. If the displacement is small, we
25
- if (dc->op_flags & XTENSA_OP_POSTPROCESS) {
28
- can nop out the addis. */
26
- slot = gen_postprocess(dc, slot);
29
- if (value == (int16_t)value) {
27
- }
30
- code_ptr[0] = NOP;
28
- if (slot >= 0) {
31
- old = deposit32(code_ptr[1], 0, 16, value);
29
- tcg_gen_goto_tb(slot);
32
- code_ptr[1] = deposit32(old, 16, 5, TCG_REG_TB);
30
- tcg_gen_exit_tb(dc->base.tb, slot);
33
- } else {
31
- } else {
34
- int16_t lo = value;
32
- tcg_gen_exit_tb(NULL, 0);
35
- int hi = value - lo;
33
- }
36
- if (hi + lo != value) {
34
+ tcg_gen_exit_tb(NULL, 0);
37
- return false;
35
}
38
- }
36
dc->base.is_jmp = DISAS_NORETURN;
39
- code_ptr[0] = deposit32(code_ptr[0], 0, 16, hi >> 16);
37
}
40
- code_ptr[1] = deposit32(code_ptr[1], 0, 16, lo);
38
@@ -XXX,XX +XXX,XX @@ static void xtensa_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
41
+ /*
39
case DISAS_NORETURN:
42
+ * We are (slightly) abusing this relocation type. In particular,
40
break;
43
+ * assert that the low 2 bits are zero, and do not modify them.
41
case DISAS_TOO_MANY:
44
+ * That way we can use this with LD et al that have opcode bits
42
- if (dc->base.singlestep_enabled) {
45
+ * in the low 2 bits of the insn.
43
- tcg_gen_movi_i32(cpu_pc, dc->pc);
46
+ */
44
- gen_exception(dc, EXCP_DEBUG);
47
+ if ((value & 3) || value != (int16_t)value) {
45
- } else {
48
+ return false;
46
- gen_jumpi(dc, dc->pc, 0);
49
}
47
- }
50
+ *code_ptr = (*code_ptr & ~0xfffc) | (value & 0xfffc);
48
+ gen_jumpi(dc, dc->pc, 0);
51
break;
49
break;
52
default:
50
default:
53
g_assert_not_reached();
51
g_assert_not_reached();
54
@@ -XXX,XX +XXX,XX @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
55
if (!in_prologue && USE_REG_TB) {
56
new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr,
57
-(intptr_t)s->code_gen_ptr);
58
- tcg_out32(s, ADDIS | TAI(ret, TCG_REG_TB, 0));
59
- tcg_out32(s, LD | TAI(ret, ret, 0));
60
+ tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0));
61
return;
62
}
63
64
--
52
--
65
2.17.1
53
2.25.1
66
54
67
55
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/15] tcg: Implement tcg_gen_extract2_{i32, i64}
[PULL 24/24] Revert "cpu: Move cpu_common_props to hw/core/cpu.c"
1
From: David Hildenbrand <david@redhat.com>
1
This reverts commit 1b36e4f5a5de585210ea95f2257839c2312be28f.
2
2
3
Will be helpful for s390x. Input 128 bit and output 64 bit only,
3
Despite a comment saying why cpu_common_props cannot be placed in
4
which is sufficient for now.
4
a file that is compiled once, it was moved anyway. Revert that.
5
5
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Since then, Property is not defined in hw/core/cpu.h, so it is now
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
easier to declare a function to install the properties rather than
8
Signed-off-by: David Hildenbrand <david@redhat.com>
8
the Property array itself.
9
Message-Id: <20190225154204.26751-1-david@redhat.com>
9
10
[rth: Add matching tcg_gen_extract2_i32.]
10
Cc: Eduardo Habkost <ehabkost@redhat.com>
11
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
---
13
---
13
tcg/tcg-op.h | 6 ++++++
14
include/hw/core/cpu.h | 1 +
14
tcg/tcg-op.c | 44 ++++++++++++++++++++++++++++++++++++++++++++
15
cpu.c | 21 +++++++++++++++++++++
15
2 files changed, 50 insertions(+)
16
hw/core/cpu-common.c | 17 +----------------
17
3 files changed, 23 insertions(+), 16 deletions(-)
16
18
17
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
19
diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h
18
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
19
--- a/tcg/tcg-op.h
21
--- a/include/hw/core/cpu.h
20
+++ b/tcg/tcg-op.h
22
+++ b/include/hw/core/cpu.h
21
@@ -XXX,XX +XXX,XX @@ void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg,
23
@@ -XXX,XX +XXX,XX @@ void QEMU_NORETURN cpu_abort(CPUState *cpu, const char *fmt, ...)
22
unsigned int ofs, unsigned int len);
24
GCC_FMT_ATTR(2, 3);
23
void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg,
25
24
unsigned int ofs, unsigned int len);
26
/* $(top_srcdir)/cpu.c */
25
+void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah,
27
+void cpu_class_init_props(DeviceClass *dc);
26
+ unsigned int ofs);
28
void cpu_exec_initfn(CPUState *cpu);
27
void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *);
29
void cpu_exec_realizefn(CPUState *cpu, Error **errp);
28
void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *);
30
void cpu_exec_unrealizefn(CPUState *cpu);
29
void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
31
diff --git a/cpu.c b/cpu.c
30
@@ -XXX,XX +XXX,XX @@ void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg,
31
unsigned int ofs, unsigned int len);
32
void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg,
33
unsigned int ofs, unsigned int len);
34
+void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah,
35
+ unsigned int ofs);
36
void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *);
37
void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *);
38
void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
39
@@ -XXX,XX +XXX,XX @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
40
#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64
41
#define tcg_gen_extract_tl tcg_gen_extract_i64
42
#define tcg_gen_sextract_tl tcg_gen_sextract_i64
43
+#define tcg_gen_extract2_tl tcg_gen_extract2_i64
44
#define tcg_const_tl tcg_const_i64
45
#define tcg_const_local_tl tcg_const_local_i64
46
#define tcg_gen_movcond_tl tcg_gen_movcond_i64
47
@@ -XXX,XX +XXX,XX @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
48
#define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32
49
#define tcg_gen_extract_tl tcg_gen_extract_i32
50
#define tcg_gen_sextract_tl tcg_gen_sextract_i32
51
+#define tcg_gen_extract2_tl tcg_gen_extract2_i32
52
#define tcg_const_tl tcg_const_i32
53
#define tcg_const_local_tl tcg_const_local_i32
54
#define tcg_gen_movcond_tl tcg_gen_movcond_i32
55
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
56
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
57
--- a/tcg/tcg-op.c
33
--- a/cpu.c
58
+++ b/tcg/tcg-op.c
34
+++ b/cpu.c
59
@@ -XXX,XX +XXX,XX @@ void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg,
35
@@ -XXX,XX +XXX,XX @@ void cpu_exec_unrealizefn(CPUState *cpu)
60
tcg_gen_sari_i32(ret, ret, 32 - len);
36
cpu_list_remove(cpu);
61
}
37
}
62
38
63
+/*
39
+static Property cpu_common_props[] = {
64
+ * Extract 32-bits from a 64-bit input, ah:al, starting from ofs.
40
+#ifndef CONFIG_USER_ONLY
65
+ * Unlike tcg_gen_extract_i32 above, len is fixed at 32.
41
+ /*
66
+ */
42
+ * Create a memory property for softmmu CPU object,
67
+void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah,
43
+ * so users can wire up its memory. (This can't go in hw/core/cpu.c
68
+ unsigned int ofs)
44
+ * because that file is compiled only once for both user-mode
45
+ * and system builds.) The default if no link is set up is to use
46
+ * the system address space.
47
+ */
48
+ DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
49
+ MemoryRegion *),
50
+#endif
51
+ DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),
52
+ DEFINE_PROP_END_OF_LIST(),
53
+};
54
+
55
+void cpu_class_init_props(DeviceClass *dc)
69
+{
56
+{
70
+ tcg_debug_assert(ofs <= 32);
57
+ device_class_set_props(dc, cpu_common_props);
71
+ if (ofs == 0) {
72
+ tcg_gen_mov_i32(ret, al);
73
+ } else if (ofs == 32) {
74
+ tcg_gen_mov_i32(ret, ah);
75
+ } else if (al == ah) {
76
+ tcg_gen_rotri_i32(ret, al, ofs);
77
+ } else {
78
+ TCGv_i32 t0 = tcg_temp_new_i32();
79
+ tcg_gen_shri_i32(t0, al, ofs);
80
+ tcg_gen_deposit_i32(ret, t0, ah, 32 - ofs, ofs);
81
+ tcg_temp_free_i32(t0);
82
+ }
83
+}
58
+}
84
+
59
+
85
void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1,
60
void cpu_exec_initfn(CPUState *cpu)
86
TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2)
87
{
61
{
88
@@ -XXX,XX +XXX,XX @@ void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg,
62
cpu->as = NULL;
89
tcg_gen_sari_i64(ret, ret, 64 - len);
63
diff --git a/hw/core/cpu-common.c b/hw/core/cpu-common.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/hw/core/cpu-common.c
66
+++ b/hw/core/cpu-common.c
67
@@ -XXX,XX +XXX,XX @@ static int64_t cpu_common_get_arch_id(CPUState *cpu)
68
return cpu->cpu_index;
90
}
69
}
91
70
92
+/*
71
-static Property cpu_common_props[] = {
93
+ * Extract 64 bits from a 128-bit input, ah:al, starting from ofs.
72
-#ifndef CONFIG_USER_ONLY
94
+ * Unlike tcg_gen_extract_i64 above, len is fixed at 64.
73
- /* Create a memory property for softmmu CPU object,
95
+ */
74
- * so users can wire up its memory. (This can't go in hw/core/cpu.c
96
+void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah,
75
- * because that file is compiled only once for both user-mode
97
+ unsigned int ofs)
76
- * and system builds.) The default if no link is set up is to use
98
+{
77
- * the system address space.
99
+ tcg_debug_assert(ofs <= 64);
78
- */
100
+ if (ofs == 0) {
79
- DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION,
101
+ tcg_gen_mov_i64(ret, al);
80
- MemoryRegion *),
102
+ } else if (ofs == 64) {
81
-#endif
103
+ tcg_gen_mov_i64(ret, ah);
82
- DEFINE_PROP_BOOL("start-powered-off", CPUState, start_powered_off, false),
104
+ } else if (al == ah) {
83
- DEFINE_PROP_END_OF_LIST(),
105
+ tcg_gen_rotri_i64(ret, al, ofs);
84
-};
106
+ } else {
85
-
107
+ TCGv_i64 t0 = tcg_temp_new_i64();
86
static void cpu_class_init(ObjectClass *klass, void *data)
108
+ tcg_gen_shri_i64(t0, al, ofs);
109
+ tcg_gen_deposit_i64(ret, t0, ah, 64 - ofs, ofs);
110
+ tcg_temp_free_i64(t0);
111
+ }
112
+}
113
+
114
void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1,
115
TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2)
116
{
87
{
88
DeviceClass *dc = DEVICE_CLASS(klass);
89
@@ -XXX,XX +XXX,XX @@ static void cpu_class_init(ObjectClass *klass, void *data)
90
dc->realize = cpu_common_realizefn;
91
dc->unrealize = cpu_common_unrealizefn;
92
dc->reset = cpu_common_reset;
93
- device_class_set_props(dc, cpu_common_props);
94
+ cpu_class_init_props(dc);
95
/*
96
* Reason: CPUs still need special care by board code: wiring up
97
* IRQs, adding reset handlers, halting non-first CPUs, ...
117
--
98
--
118
2.17.1
99
2.25.1
119
100
120
101
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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