1 | Two last-minute regression fixes that I thought we might as well | 1 | Only thing for Arm for rc1 is RTH's fix for the KVM SVE probe code. |
---|---|---|---|
2 | squeeze in before rc1. | ||
3 | 2 | ||
4 | thanks | ||
5 | -- PMM | 3 | -- PMM |
6 | 4 | ||
7 | The following changes since commit d37bfe142382fa8258531c47b4519387c77cd169: | 5 | The following changes since commit 4e06b3fc1b5e1ec03f22190eabe56891dc9c2236: |
8 | 6 | ||
9 | Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.0-rc1-v2' into staging (2019-03-26 10:27:20 +0000) | 7 | Merge tag 'pull-hex-20220731' of https://github.com/quic/qemu into staging (2022-07-31 21:38:54 -0700) |
10 | 8 | ||
11 | are available in the Git repository at: | 9 | are available in the Git repository at: |
12 | 10 | ||
13 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190326 | 11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220801 |
14 | 12 | ||
15 | for you to fetch changes up to c99ef792dc9ec6d8a5061428faf396ea9ceb8f57: | 13 | for you to fetch changes up to 5265d24c981dfdda8d29b44f7e84a514da75eedc: |
16 | 14 | ||
17 | gdbstub: fix vCont packet handling when no thread is specified (2019-03-26 12:53:26 +0000) | 15 | target/arm: Move sve probe inside kvm >= 4.15 branch (2022-08-01 16:21:18 +0100) |
18 | 16 | ||
19 | ---------------------------------------------------------------- | 17 | ---------------------------------------------------------------- |
20 | target-arm queue: | 18 | target-arm queue: |
21 | * Set SIMDMISC and FPMISC for 32-bit -cpu max | 19 | * Fix KVM SVE ID register probe code |
22 | (fixes regression from 3.1) | ||
23 | * fix vCont packet handling when no thread is specified | ||
24 | 20 | ||
25 | ---------------------------------------------------------------- | 21 | ---------------------------------------------------------------- |
26 | Luc Michel (1): | 22 | Richard Henderson (3): |
27 | gdbstub: fix vCont packet handling when no thread is specified | 23 | target/arm: Use kvm_arm_sve_supported in kvm_arm_get_host_cpu_features |
24 | target/arm: Set KVM_ARM_VCPU_SVE while probing the host | ||
25 | target/arm: Move sve probe inside kvm >= 4.15 branch | ||
28 | 26 | ||
29 | Richard Henderson (1): | 27 | target/arm/kvm64.c | 45 ++++++++++++++++++++++----------------------- |
30 | target/arm: Set SIMDMISC and FPMISC for 32-bit -cpu max | 28 | 1 file changed, 22 insertions(+), 23 deletions(-) |
31 | |||
32 | gdbstub.c | 14 ++++++++++++-- | ||
33 | target/arm/cpu.c | 5 +++++ | ||
34 | 2 files changed, 17 insertions(+), 2 deletions(-) | ||
35 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | Indication for support for SVE will not depend on whether we | ||
4 | perform the query on the main kvm_state or the temp vcpu. | ||
5 | |||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20220726045828.53697-2-richard.henderson@linaro.org | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/kvm64.c | 2 +- | ||
12 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
13 | |||
14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/kvm64.c | ||
17 | +++ b/target/arm/kvm64.c | ||
18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
19 | } | ||
20 | } | ||
21 | |||
22 | - sve_supported = ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_SVE) > 0; | ||
23 | + sve_supported = kvm_arm_sve_supported(); | ||
24 | |||
25 | /* Add feature bits that can't appear until after VCPU init. */ | ||
26 | if (sve_supported) { | ||
27 | -- | ||
28 | 2.25.1 | diff view generated by jsdifflib |
1 | From: Luc Michel <luc.michel@greensocs.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | The vCont packet accepts a series of actions, each being applied on a | 3 | Because we weren't setting this flag, our probe of ID_AA64ZFR0 |
4 | given thread ID. Giving no thread ID for an action is valid and means | 4 | was always returning zero. This also obviates the adjustment |
5 | "all threads". | 5 | of ID_AA64PFR0, which had sanitized the SVE field. |
6 | 6 | ||
7 | This commit fixes vCont packets being incorrectly rejected when no | 7 | The effects of the bug are not visible, because the only thing that |
8 | thread ID was given for an action. | 8 | ID_AA64ZFR0 is used for within qemu at present is tcg translation. |
9 | The other tests for SVE within KVM are via ID_AA64PFR0.SVE. | ||
9 | 10 | ||
10 | In multiprocess mode, the GDB Remote Protocol specification is unclear | 11 | Reported-by: Zenghui Yu <yuzenghui@huawei.com> |
11 | on what "all threads" means. We choose to apply the action on all | 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
12 | threads of all attached processes. | 13 | Message-id: 20220726045828.53697-3-richard.henderson@linaro.org |
13 | 14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | |
14 | This commit is based on the initial fix by Lucien Murray-Pitts. | ||
15 | |||
16 | Fixes: e40e5204af8388 | ||
17 | Reported-by: Lucien Murray-Pitts <lucienmp_antispam@yahoo.com> | ||
18 | Reported-by: Jan Kiszka <jan.kiszka@siemens.com> | ||
19 | Signed-off-by: Luc Michel <luc.michel@greensocs.com> | ||
20 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
21 | Message-id: 20190325110452.6756-1-luc.michel@greensocs.com | ||
22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
23 | --- | 16 | --- |
24 | gdbstub.c | 14 ++++++++++++-- | 17 | target/arm/kvm64.c | 27 +++++++++++++-------------- |
25 | 1 file changed, 12 insertions(+), 2 deletions(-) | 18 | 1 file changed, 13 insertions(+), 14 deletions(-) |
26 | 19 | ||
27 | diff --git a/gdbstub.c b/gdbstub.c | 20 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c |
28 | index XXXXXXX..XXXXXXX 100644 | 21 | index XXXXXXX..XXXXXXX 100644 |
29 | --- a/gdbstub.c | 22 | --- a/target/arm/kvm64.c |
30 | +++ b/gdbstub.c | 23 | +++ b/target/arm/kvm64.c |
31 | @@ -XXX,XX +XXX,XX @@ static int gdb_handle_vcont(GDBState *s, const char *p) | 24 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) |
32 | uint32_t pid, tid; | 25 | bool sve_supported; |
33 | GDBProcess *process; | 26 | bool pmu_supported = false; |
34 | CPUState *cpu; | 27 | uint64_t features = 0; |
35 | + GDBThreadIdKind kind; | 28 | - uint64_t t; |
36 | #ifdef CONFIG_USER_ONLY | 29 | int err; |
37 | int max_cpus = 1; /* global variable max_cpus exists only in system mode */ | 30 | |
38 | 31 | /* Old kernels may not know about the PREFERRED_TARGET ioctl: however | |
39 | @@ -XXX,XX +XXX,XX @@ static int gdb_handle_vcont(GDBState *s, const char *p) | 32 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) |
40 | goto out; | 33 | struct kvm_vcpu_init init = { .target = -1, }; |
34 | |||
35 | /* | ||
36 | - * Ask for Pointer Authentication if supported. We can't play the | ||
37 | - * SVE trick of synthesising the ID reg as KVM won't tell us | ||
38 | - * whether we have the architected or IMPDEF version of PAuth, so | ||
39 | - * we have to use the actual ID regs. | ||
40 | + * Ask for SVE if supported, so that we can query ID_AA64ZFR0, | ||
41 | + * which is otherwise RAZ. | ||
42 | + */ | ||
43 | + sve_supported = kvm_arm_sve_supported(); | ||
44 | + if (sve_supported) { | ||
45 | + init.features[0] |= 1 << KVM_ARM_VCPU_SVE; | ||
46 | + } | ||
47 | + | ||
48 | + /* | ||
49 | + * Ask for Pointer Authentication if supported, so that we get | ||
50 | + * the unsanitized field values for AA64ISAR1_EL1. | ||
51 | */ | ||
52 | if (kvm_arm_pauth_supported()) { | ||
53 | init.features[0] |= (1 << KVM_ARM_VCPU_PTRAUTH_ADDRESS | | ||
54 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) | ||
41 | } | 55 | } |
42 | 56 | } | |
43 | - if (*p++ != ':') { | 57 | |
44 | + if (*p == '\0' || *p == ';') { | 58 | - sve_supported = kvm_arm_sve_supported(); |
45 | + /* | 59 | - |
46 | + * No thread specifier, action is on "all threads". The | 60 | - /* Add feature bits that can't appear until after VCPU init. */ |
47 | + * specification is unclear regarding the process to act on. We | 61 | if (sve_supported) { |
48 | + * choose all processes. | 62 | - t = ahcf->isar.id_aa64pfr0; |
49 | + */ | 63 | - t = FIELD_DP64(t, ID_AA64PFR0, SVE, 1); |
50 | + kind = GDB_ALL_PROCESSES; | 64 | - ahcf->isar.id_aa64pfr0 = t; |
51 | + } else if (*p++ == ':') { | 65 | - |
52 | + kind = read_thread_id(p, &p, &pid, &tid); | 66 | /* |
53 | + } else { | 67 | * There is a range of kernels between kernel commit 73433762fcae |
54 | res = -ENOTSUP; | 68 | * and f81cb2c3ad41 which have a bug where the kernel doesn't expose |
55 | goto out; | 69 | * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled |
56 | } | 70 | - * SVE support, so we only read it here, rather than together with all |
57 | 71 | - * the other ID registers earlier. | |
58 | - switch (read_thread_id(p, &p, &pid, &tid)) { | 72 | + * SVE support, which resulted in an error rather than RAZ. |
59 | + switch (kind) { | 73 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. |
60 | case GDB_READ_THREAD_ERR: | 74 | */ |
61 | res = -EINVAL; | 75 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, |
62 | goto out; | 76 | ARM64_SYS_REG(3, 0, 0, 4, 4)); |
63 | -- | 77 | -- |
64 | 2.20.1 | 78 | 2.25.1 |
65 | |||
66 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Fixes: https://bugs.launchpad.net/bugs/1821430 | 3 | The test for the IF block indicates no ID registers are exposed, much |
4 | less host support for SVE. Move the SVE probe into the ELSE block. | ||
5 | |||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> | 7 | Message-id: 20220726045828.53697-4-richard.henderson@linaro.org |
6 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Message-id: 20190325161338.6536-1-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 10 | --- |
10 | target/arm/cpu.c | 5 +++++ | 11 | target/arm/kvm64.c | 22 +++++++++++----------- |
11 | 1 file changed, 5 insertions(+) | 12 | 1 file changed, 11 insertions(+), 11 deletions(-) |
12 | 13 | ||
13 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | 14 | diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c |
14 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
15 | --- a/target/arm/cpu.c | 16 | --- a/target/arm/kvm64.c |
16 | +++ b/target/arm/cpu.c | 17 | +++ b/target/arm/kvm64.c |
17 | @@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj) | 18 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf) |
18 | t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); | 19 | err |= read_sys_reg64(fdarray[2], &ahcf->isar.reset_pmcr_el0, |
19 | cpu->isar.id_isar6 = t; | 20 | ARM64_SYS_REG(3, 3, 9, 12, 0)); |
20 | 21 | } | |
21 | + t = cpu->isar.mvfr2; | 22 | - } |
22 | + t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ | 23 | |
23 | + t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ | 24 | - if (sve_supported) { |
24 | + cpu->isar.mvfr2 = t; | 25 | - /* |
25 | + | 26 | - * There is a range of kernels between kernel commit 73433762fcae |
26 | t = cpu->id_mmfr4; | 27 | - * and f81cb2c3ad41 which have a bug where the kernel doesn't expose |
27 | t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ | 28 | - * SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has enabled |
28 | cpu->id_mmfr4 = t; | 29 | - * SVE support, which resulted in an error rather than RAZ. |
30 | - * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
31 | - */ | ||
32 | - err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
33 | - ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
34 | + if (sve_supported) { | ||
35 | + /* | ||
36 | + * There is a range of kernels between kernel commit 73433762fcae | ||
37 | + * and f81cb2c3ad41 which have a bug where the kernel doesn't | ||
38 | + * expose SYS_ID_AA64ZFR0_EL1 via the ONE_REG API unless the VM has | ||
39 | + * enabled SVE support, which resulted in an error rather than RAZ. | ||
40 | + * So only read the register if we set KVM_ARM_VCPU_SVE above. | ||
41 | + */ | ||
42 | + err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64zfr0, | ||
43 | + ARM64_SYS_REG(3, 0, 0, 4, 4)); | ||
44 | + } | ||
45 | } | ||
46 | |||
47 | kvm_arm_destroy_scratch_host_vcpu(fdarray); | ||
29 | -- | 48 | -- |
30 | 2.20.1 | 49 | 2.25.1 |
31 | |||
32 | diff view generated by jsdifflib |