Patches for rc1: nothing major, just some minor bugfixes and

code cleanups.

The following changes since commit f7e1914adad8885a5d4c70239ab90d901ed97e9f:

Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201109' into staging (2020-11-10 09:24:56 +0000)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201110

for you to fetch changes up to b6c56c8a9a4064ea783f352f43c5df6231a110fa:

target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check (2020-11-10 11:03:48 +0000)

* hw/arm/Kconfig: ARM_V7M depends on PTIMER

* Minor coding style fixes

* docs: add some notes on the sbsa-ref machine

* hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals

* target/arm: Fix neon VTBL/VTBX for len > 1

* hw/arm/armsse: Correct expansion MPC interrupt lines

* hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ

* hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup()

* hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input

* hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary

* hw/arm/nseries: Check return value from load_image_targphys()

* tests/qtest/npcm7xx_rng-test: count runs properly

* target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check

Alex Bennée (1):

docs: add some notes on the sbsa-ref machine

AlexChen (1):

ssi: Fix bad printf format specifiers

Andrew Jones (1):

hw/arm/Kconfig: ARM_V7M depends on PTIMER

Havard Skinnemoen (1):

tests/qtest/npcm7xx_rng-test: count runs properly

Peter Maydell (2):

hw/arm/nseries: Check return value from load_image_targphys()

target/arm/translate-neon.c: Handle VTBL UNDEF case before VFP access check

Philippe Mathieu-Daudé (6):

hw/arm/virt: Remove dependency on Cortex-A15 MPCore peripherals

hw/arm/armsse: Correct expansion MPC interrupt lines

hw/misc/stm32f2xx_syscfg: Remove extraneous IRQ

hw/arm/nseries: Remove invalid/unnecessary n8x0_uart_setup()

hw/arm/musicpal: Don't connect two qemu_irqs directly to the same input

hw/arm/musicpal: Only use qdev_get_gpio_in() when necessary

target/arm: Fix neon VTBL/VTBX for len > 1

Xinhao Zhang (3):

target/arm: add spaces around operator

target/arm: Don't use '#' flag of printf format

target/arm: add space before the open parenthesis '('

The helper function did not get updated when we reorganized

the vector register file for SVE. Since then, the neon dregs

are non-sequential and cannot be simply indexed.

At the same time, make the helper function operate on 64-bit

quantities so that we do not have to call it twice.

Fixes: c39c2b9043e

Reported-by: Ard Biesheuvel <ardb@kernel.org>

[PMM: use aa32_vfp_dreg() rather than opencoding]

Message-id: 20201105171126.88014-1-richard.henderson@linaro.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

target/arm/helper.h | 2 +-

target/arm/op_helper.c | 23 +++++++++--------

target/arm/translate-neon.c.inc | 44 +++++++++++----------------------

3 files changed, 29 insertions(+), 40 deletions(-)

diff --git a/target/arm/helper.h b/target/arm/helper.h

--- a/target/arm/helper.h

+++ b/target/arm/helper.h

@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr)

DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr)

DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32)

DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32)

-DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i32, i32, i32, ptr, i32)

+DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64)

DEF_HELPER_3(shl_cc, i32, env, i32, i32)

DEF_HELPER_3(shr_cc, i32, env, i32, i32)

diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/op_helper.c

+++ b/target/arm/op_helper.c

@@ -XXX,XX +XXX,XX @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome,

cpu_loop_exit_restore(cs, ra);

}

-uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn,

- uint32_t maxindex)

+uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc,

+ uint64_t ireg, uint64_t def)

{

- uint32_t val, shift;

- uint64_t *table = vn;

+ uint64_t tmp, val = 0;

+ uint32_t maxindex = ((desc & 3) + 1) * 8;

+ uint32_t base_reg = desc >> 2;

+ uint32_t shift, index, reg;

- val = 0;

- for (shift = 0; shift < 32; shift += 8) {

- uint32_t index = (ireg >> shift) & 0xff;

+ for (shift = 0; shift < 64; shift += 8) {

+ index = (ireg >> shift) & 0xff;

if (index < maxindex) {

- uint32_t tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff;

- val |= tmp << shift;

+ reg = base_reg + (index >> 3);

+ tmp = *aa32_vfp_dreg(env, reg);

+ tmp = ((tmp >> ((index & 7) << 3)) & 0xff) << shift;

} else {

- val |= def & (0xff << shift);

+ tmp = def & (0xffull << shift);

}

+ val |= tmp;

}

return val;

}

diff --git a/target/arm/translate-neon.c.inc b/target/arm/translate-neon.c.inc

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-neon.c.inc

+++ b/target/arm/translate-neon.c.inc

@@ -XXX,XX +XXX,XX @@ static bool trans_VEXT(DisasContext *s, arg_VEXT *a)

static bool trans_VTBL(DisasContext *s, arg_VTBL *a)

{

- int n;

- TCGv_i32 tmp, tmp2, tmp3, tmp4;

- TCGv_ptr ptr1;

+ TCGv_i64 val, def;

+ TCGv_i32 desc;

if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {

return false;

@@ -XXX,XX +XXX,XX @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a)

return true;

}

- n = a->len + 1;

- if ((a->vn + n) > 32) {

+ if ((a->vn + a->len + 1) > 32) {

/*

* This is UNPREDICTABLE; we choose to UNDEF to avoid the

* helper function running off the end of the register file.

*/

return false;

}

- n <<= 3;

- tmp = tcg_temp_new_i32();

- if (a->op) {

- read_neon_element32(tmp, a->vd, 0, MO_32);

- } else {

- tcg_gen_movi_i32(tmp, 0);

- }

- tmp2 = tcg_temp_new_i32();

- read_neon_element32(tmp2, a->vm, 0, MO_32);

- ptr1 = vfp_reg_ptr(true, a->vn);

- tmp4 = tcg_const_i32(n);

- gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp4);

+ desc = tcg_const_i32((a->vn << 2) | a->len);

+ def = tcg_temp_new_i64();

if (a->op) {

- read_neon_element32(tmp, a->vd, 1, MO_32);

+ read_neon_element64(def, a->vd, 0, MO_64);

} else {

- tcg_gen_movi_i32(tmp, 0);

+ tcg_gen_movi_i64(def, 0);

}

- tmp3 = tcg_temp_new_i32();

- read_neon_element32(tmp3, a->vm, 1, MO_32);

- gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp4);

- tcg_temp_free_i32(tmp);

- tcg_temp_free_i32(tmp4);

- tcg_temp_free_ptr(ptr1);

+ val = tcg_temp_new_i64();

+ read_neon_element64(val, a->vm, 0, MO_64);

- write_neon_element32(tmp2, a->vd, 0, MO_32);

- write_neon_element32(tmp3, a->vd, 1, MO_32);

- tcg_temp_free_i32(tmp2);

- tcg_temp_free_i32(tmp3);

+ gen_helper_neon_tbl(val, cpu_env, desc, val, def);

+ write_neon_element64(val, a->vd, 0, MO_64);

+ tcg_temp_free_i64(def);

+ tcg_temp_free_i64(val);

+ tcg_temp_free_i32(desc);

return true;

}

From: Philippe Mathieu-Daudé <f4bug@amsat.org>

We can use one MPC per SRAM bank, but we currently only wire the

IRQ from the first expansion MPC to the IRQ splitter. Fix that.

Fixes: bb75e16d5e6 ("hw/arm/iotkit: Wire up MPC interrupt lines")

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

Message-id: 20201107193403.436146-2-f4bug@amsat.org

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

hw/arm/armsse.c | 3 ++-

1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c

--- a/hw/arm/armsse.c

+++ b/hw/arm/armsse.c

@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)

qdev_get_gpio_in(dev_splitter, 0));

qdev_connect_gpio_out(dev_splitter, 0,

qdev_get_gpio_in_named(dev_secctl,

- "mpc_status", 0));

+ "mpc_status",

+ i - IOTS_NUM_EXP_MPC));

qdev_connect_gpio_out(dev_splitter, 1,