[v1] target/riscv: Fix wrong expanding for c.fswsp

[Qemu-devel] [PULL] target/riscv: Fix wrong expanding for c.fswsp

Palmer Dabbelt posted 1 patch 6 years, 10 months ago

Diff against v1
Download mbox

Test asan passed

Test docker-mingw@fedora passed

Test docker-clang@ubuntu passed

Test checkpatch passed

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20190326102515.7071-2-palmer@sifive.com

Maintainers: Sagar Karandikar <sagark@eecs.berkeley.edu>, Alistair Francis <Alistair.Francis@wdc.com>, Palmer Dabbelt <palmer@sifive.com>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

target/riscv/insn_trans/trans_rvc.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

Expand all Fold all

[Qemu-devel] [PULL] target/riscv: Fix wrong expanding for c.fswsp

Posted by Palmer Dabbelt 6 years, 10 months ago

From: Kito Cheng <kito.cheng@gmail.com>

base register is no rs1 not rs2 for fsw.

Signed-off-by: Kito Cheng <kito.cheng@gmail.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
---
 target/riscv/insn_trans/trans_rvc.inc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/riscv/insn_trans/trans_rvc.inc.c b/target/riscv/insn_trans/trans_rvc.inc.c
index 5819f53f900e..ebcd977b2f94 100644
--- a/target/riscv/insn_trans/trans_rvc.inc.c
+++ b/target/riscv/insn_trans/trans_rvc.inc.c
@@ -337,7 +337,7 @@ static bool trans_c_fswsp_sdsp(DisasContext *ctx, arg_c_fswsp_sdsp *a)
 {
 #ifdef TARGET_RISCV32
     /* C.FSWSP */
-    arg_fsw a_fsw = { .rs1 = a->rs2, .rs2 = 2, .imm = a->uimm_fswsp };
+    arg_fsw a_fsw = { .rs1 = 2, .rs2 = a->rs2, .imm = a->uimm_fswsp };
     return trans_fsw(ctx, &a_fsw);
 #else
     /* C.SDSP */
-- 
2.19.2