target/arm: Set SIMDMISC and FPMISC for 32-bit -cpu max

[Qemu-devel] [PATCH] target/arm: Set SIMDMISC and FPMISC for 32-bit -cpu max

Posted by Richard Henderson 5 years, 1 month ago

Fixes: https://bugs.launchpad.net/bugs/1821430
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpu.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 96f0ff0ec7..d9b8658921 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2025,6 +2025,11 @@ static void arm_max_initfn(Object *obj)
             t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
             cpu->isar.id_isar6 = t;
 
+            t = cpu->isar.mvfr2;
+            t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
+            t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
+            cpu->isar.mvfr2 = t;
+
             t = cpu->id_mmfr4;
             t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
             cpu->id_mmfr4 = t;
-- 
2.17.1

Re: [Qemu-devel] [PATCH] target/arm: Set SIMDMISC and FPMISC for 32-bit -cpu max

Posted by Philippe Mathieu-Daudé 5 years, 1 month ago

Le lun. 25 mars 2019 17:17, Richard Henderson <richard.henderson@linaro.org>
a écrit :

> Fixes: https://bugs.launchpad.net/bugs/1821430
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/cpu.c | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 96f0ff0ec7..d9b8658921 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -2025,6 +2025,11 @@ static void arm_max_initfn(Object *obj)
>              t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
>              cpu->isar.id_isar6 = t;
>
> +            t = cpu->isar.mvfr2;
> +            t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
> +            t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
> +            cpu->isar.mvfr2 = t;
> +
>              t = cpu->id_mmfr4;
>              t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
>              cpu->id_mmfr4 = t;
> --
> 2.17.1
>

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

>

Re: [Qemu-devel] [PATCH] target/arm: Set SIMDMISC and FPMISC for 32-bit -cpu max

Posted by Alex Bennée 5 years, 1 month ago

Richard Henderson <richard.henderson@linaro.org> writes:

> Fixes: https://bugs.launchpad.net/bugs/1821430
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/cpu.c | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 96f0ff0ec7..d9b8658921 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -2025,6 +2025,11 @@ static void arm_max_initfn(Object *obj)
>              t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
>              cpu->isar.id_isar6 = t;
>
> +            t = cpu->isar.mvfr2;
> +            t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
> +            t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
> +            cpu->isar.mvfr2 = t;
> +

heh:

  In ARMv8-A, the permitted values are 0b0000 and 0b0100

and similar for SIMDMisc. I guess you might see the others in some none
A profile setup? Anyway:

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>

--
Alex Bennée

Re: [Qemu-devel] [PATCH] target/arm: Set SIMDMISC and FPMISC for 32-bit -cpu max

Posted by Peter Maydell 5 years, 1 month ago

On Mon, 25 Mar 2019 at 16:13, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Fixes: https://bugs.launchpad.net/bugs/1821430
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/arm/cpu.c | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/target/arm/cpu.c b/target/arm/cpu.c
> index 96f0ff0ec7..d9b8658921 100644
> --- a/target/arm/cpu.c
> +++ b/target/arm/cpu.c
> @@ -2025,6 +2025,11 @@ static void arm_max_initfn(Object *obj)
>              t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
>              cpu->isar.id_isar6 = t;
>
> +            t = cpu->isar.mvfr2;
> +            t = FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */
> +            t = FIELD_DP32(t, MVFR2, FPMISC, 4);   /* FP MaxNum */
> +            cpu->isar.mvfr2 = t;
> +
>              t = cpu->id_mmfr4;
>              t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
>              cpu->id_mmfr4 = t;
> --
> 2.17.1



Applied to target-arm.next, thanks.

-- PMM