1 | A small set of arm bugfixes for rc1 tomorrow. | 1 | Couple of last-minute things for rc3... |
---|---|---|---|
2 | 2 | ||
3 | thanks | ||
4 | -- PMM | 3 | -- PMM |
5 | 4 | ||
6 | The following changes since commit c442b7b4a7ae8696bcdf46091d781bd9052731be: | 5 | The following changes since commit d15532d91be177e7528310e0110e39f915779a99: |
7 | 6 | ||
8 | Merge remote-tracking branch 'remotes/elmarco/tags/slirp-pull-request' into staging (2019-03-25 07:59:40 +0000) | 7 | Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20200804' into staging (2020-08-04 11:53:20 +0100) |
9 | 8 | ||
10 | are available in the Git repository at: | 9 | are available in the Git repository at: |
11 | 10 | ||
12 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190325 | 11 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20200804 |
13 | 12 | ||
14 | for you to fetch changes up to f2b2f53f6429b5abd7cd86bd65747f5f13e195eb: | 13 | for you to fetch changes up to d250bb19ced3b702c7c37731855f6876d0cc7995: |
15 | 14 | ||
16 | target/arm: make pmccntr_op_start/finish static (2019-03-25 14:16:47 +0000) | 15 | target/arm: Fix decode of LDRA[AB] instructions (2020-08-04 16:40:19 +0100) |
17 | 16 | ||
18 | ---------------------------------------------------------------- | 17 | ---------------------------------------------------------------- |
19 | target-arm queue: | 18 | target-arm queue: |
20 | * Fix non-parallel expansion of CASP | 19 | * Fix decode of LDRA[AB] instructions |
21 | * nrf51_gpio: reflect pull-up/pull-down to IRQs | 20 | * docs/devel: Document decodetree no-overlap groups |
22 | * Fix crash if guest tries to enable non-existent PMU counters | ||
23 | * Add PMUv2 to the Cortex-A15 and Cortex-A7 | ||
24 | * Make pmccntr_op_start/finish static | ||
25 | 21 | ||
26 | ---------------------------------------------------------------- | 22 | ---------------------------------------------------------------- |
27 | Andrew Jones (4): | 23 | Peter Collingbourne (1): |
28 | target/arm: add PCI_TESTDEV back to default config | 24 | target/arm: Fix decode of LDRA[AB] instructions |
29 | target/arm: fix crash on pmu register access | ||
30 | target/arm: cortex-a7 and cortex-a15 have pmus | ||
31 | target/arm: make pmccntr_op_start/finish static | ||
32 | |||
33 | Paolo Bonzini (1): | ||
34 | nrf51_gpio: reflect pull-up/pull-down to IRQs | ||
35 | 25 | ||
36 | Richard Henderson (1): | 26 | Richard Henderson (1): |
37 | target/arm: Fix non-parallel expansion of CASP | 27 | docs/devel: Document decodetree no-overlap groups |
38 | 28 | ||
39 | target/arm/cpu.h | 11 ------- | 29 | docs/devel/decodetree.rst | 29 ++++++++++++++++++----------- |
40 | hw/gpio/nrf51_gpio.c | 65 +++++++++++++++++++++++++---------------- | 30 | target/arm/translate-a64.c | 6 ++++-- |
41 | target/arm/cpu.c | 3 ++ | 31 | 2 files changed, 22 insertions(+), 13 deletions(-) |
42 | target/arm/helper.c | 8 +++-- | ||
43 | target/arm/translate-a64.c | 2 +- | ||
44 | default-configs/arm-softmmu.mak | 1 + | ||
45 | 6 files changed, 51 insertions(+), 39 deletions(-) | ||
46 | 32 | diff view generated by jsdifflib |
1 | From: Andrew Jones <drjones@redhat.com> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | These functions are not used outside helper.c | 3 | When support for this feature went in, the update to the |
4 | documentation was forgotten. | ||
4 | 5 | ||
5 | Signed-off-by: Andrew Jones <drjones@redhat.com> | 6 | Fixes: 067e8b0f45d6 |
6 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reported-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Message-id: 20190322162333.17159-4-drjones@redhat.com | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | Message-id: 20200803205708.315829-1-richard.henderson@linaro.org | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 12 | --- |
10 | target/arm/cpu.h | 11 ----------- | 13 | docs/devel/decodetree.rst | 29 ++++++++++++++++++----------- |
11 | target/arm/helper.c | 4 ++-- | 14 | 1 file changed, 18 insertions(+), 11 deletions(-) |
12 | 2 files changed, 2 insertions(+), 13 deletions(-) | ||
13 | 15 | ||
14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 16 | diff --git a/docs/devel/decodetree.rst b/docs/devel/decodetree.rst |
15 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/cpu.h | 18 | --- a/docs/devel/decodetree.rst |
17 | +++ b/target/arm/cpu.h | 19 | +++ b/docs/devel/decodetree.rst |
18 | @@ -XXX,XX +XXX,XX @@ static inline bool is_a64(CPUARMState *env) | 20 | @@ -XXX,XX +XXX,XX @@ Pattern Groups |
19 | int cpu_arm_signal_handler(int host_signum, void *pinfo, | 21 | |
20 | void *puc); | 22 | Syntax:: |
21 | 23 | ||
22 | -/** | 24 | - group := '{' ( pat_def | group )+ '}' |
23 | - * pmccntr_op_start/finish | 25 | + group := overlap_group | no_overlap_group |
24 | - * @env: CPUARMState | 26 | + overlap_group := '{' ( pat_def | group )+ '}' |
25 | - * | 27 | + no_overlap_group := '[' ( pat_def | group )+ ']' |
26 | - * Convert the counter in the PMCCNTR between its delta form (the typical mode | 28 | |
27 | - * when it's enabled) and the guest-visible value. These two calls must always | 29 | -A *group* begins with a lone open-brace, with all subsequent lines |
28 | - * surround any action which might affect the counter. | 30 | -indented two spaces, and ending with a lone close-brace. Groups |
29 | - */ | 31 | -may be nested, increasing the required indentation of the lines |
30 | -void pmccntr_op_start(CPUARMState *env); | 32 | -within the nested group to two spaces per nesting level. |
31 | -void pmccntr_op_finish(CPUARMState *env); | 33 | +A *group* begins with a lone open-brace or open-bracket, with all |
32 | - | 34 | +subsequent lines indented two spaces, and ending with a lone |
33 | /** | 35 | +close-brace or close-bracket. Groups may be nested, increasing the |
34 | * pmu_op_start/finish | 36 | +required indentation of the lines within the nested group to two |
35 | * @env: CPUARMState | 37 | +spaces per nesting level. |
36 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 38 | |
37 | index XXXXXXX..XXXXXXX 100644 | 39 | -Unlike ungrouped patterns, grouped patterns are allowed to overlap. |
38 | --- a/target/arm/helper.c | 40 | -Conflicts are resolved by selecting the patterns in order. If all |
39 | +++ b/target/arm/helper.c | 41 | -of the fixedbits for a pattern match, its translate function will |
40 | @@ -XXX,XX +XXX,XX @@ static void pmu_update_irq(CPUARMState *env) | 42 | -be called. If the translate function returns false, then subsequent |
41 | * etc. can be done logically. This is essentially a no-op if the counter is | 43 | -patterns within the group will be matched. |
42 | * not enabled at the time of the call. | 44 | +Patterns within overlap groups are allowed to overlap. Conflicts are |
43 | */ | 45 | +resolved by selecting the patterns in order. If all of the fixedbits |
44 | -void pmccntr_op_start(CPUARMState *env) | 46 | +for a pattern match, its translate function will be called. If the |
45 | +static void pmccntr_op_start(CPUARMState *env) | 47 | +translate function returns false, then subsequent patterns within the |
46 | { | 48 | +group will be matched. |
47 | uint64_t cycles = cycles_get_count(env); | 49 | + |
48 | 50 | +Patterns within no-overlap groups are not allowed to overlap, just | |
49 | @@ -XXX,XX +XXX,XX @@ void pmccntr_op_start(CPUARMState *env) | 51 | +the same as ungrouped patterns. Thus no-overlap groups are intended |
50 | * guest-visible count. A call to pmccntr_op_finish should follow every call to | 52 | +to be nested inside overlap groups. |
51 | * pmccntr_op_start. | 53 | |
52 | */ | 54 | The following example from PA-RISC shows specialization of the *or* |
53 | -void pmccntr_op_finish(CPUARMState *env) | 55 | instruction:: |
54 | +static void pmccntr_op_finish(CPUARMState *env) | 56 | @@ -XXX,XX +XXX,XX @@ instruction:: |
55 | { | 57 | When the *cf* field is zero, the instruction has no side effects, |
56 | if (pmu_counter_enabled(env, 31)) { | 58 | and may be specialized. When the *rt* field is zero, the output |
57 | #ifndef CONFIG_USER_ONLY | 59 | is discarded and so the instruction has no effect. When the *rt2* |
60 | -field is zero, the operation is ``reg[rt] | 0`` and so encodes | ||
61 | +field is zero, the operation is ``reg[r1] | 0`` and so encodes | ||
62 | the canonical register copy operation. | ||
63 | |||
64 | The output from the generator might look like:: | ||
58 | -- | 65 | -- |
59 | 2.20.1 | 66 | 2.20.1 |
60 | 67 | ||
61 | 68 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Peter Collingbourne <pcc@google.com> |
---|---|---|---|
2 | 2 | ||
3 | The second word has been loaded from the unincremented | 3 | These instructions use zero as the discriminator, not SP. |
4 | address since the first commit. | ||
5 | 4 | ||
6 | Fixes: 44ac14b06fa | 5 | Signed-off-by: Peter Collingbourne <pcc@google.com> |
7 | Reported-by: Alex Bennée <alex.bennee@linaro.org> | 6 | Message-id: 20200804002849.30268-1-pcc@google.com |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Reviewed-by: Alex Bennée <alex.bennee@linaro.org> | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Tested-by: Alex Bennée <alex.bennee@linaro.org> | ||
11 | Message-id: 20190322234302.12770-1-richard.henderson@linaro.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
13 | --- | 10 | --- |
14 | target/arm/translate-a64.c | 2 +- | 11 | target/arm/translate-a64.c | 6 ++++-- |
15 | 1 file changed, 1 insertion(+), 1 deletion(-) | 12 | 1 file changed, 4 insertions(+), 2 deletions(-) |
16 | 13 | ||
17 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 14 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c |
18 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
19 | --- a/target/arm/translate-a64.c | 16 | --- a/target/arm/translate-a64.c |
20 | +++ b/target/arm/translate-a64.c | 17 | +++ b/target/arm/translate-a64.c |
21 | @@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt, | 18 | @@ -XXX,XX +XXX,XX @@ static void disas_ldst_pac(DisasContext *s, uint32_t insn, |
22 | tcg_gen_qemu_ld_i64(d1, clean_addr, memidx, | 19 | |
23 | MO_64 | MO_ALIGN_16 | s->be_data); | 20 | if (s->pauth_active) { |
24 | tcg_gen_addi_i64(a2, clean_addr, 8); | 21 | if (use_key_a) { |
25 | - tcg_gen_qemu_ld_i64(d2, clean_addr, memidx, MO_64 | s->be_data); | 22 | - gen_helper_autda(dirty_addr, cpu_env, dirty_addr, cpu_X[31]); |
26 | + tcg_gen_qemu_ld_i64(d2, a2, memidx, MO_64 | s->be_data); | 23 | + gen_helper_autda(dirty_addr, cpu_env, dirty_addr, |
27 | 24 | + new_tmp_a64_zero(s)); | |
28 | /* Compare the two words, also in memory order. */ | 25 | } else { |
29 | tcg_gen_setcond_i64(TCG_COND_EQ, c1, d1, s1); | 26 | - gen_helper_autdb(dirty_addr, cpu_env, dirty_addr, cpu_X[31]); |
27 | + gen_helper_autdb(dirty_addr, cpu_env, dirty_addr, | ||
28 | + new_tmp_a64_zero(s)); | ||
29 | } | ||
30 | } | ||
31 | |||
30 | -- | 32 | -- |
31 | 2.20.1 | 33 | 2.20.1 |
32 | 34 | ||
33 | 35 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Paolo Bonzini <pbonzini@redhat.com> | ||
2 | 1 | ||
3 | Some drivers do I2C bitbanging by keeping the output to 0 and flipping | ||
4 | the GPIO direction between input and output (see for example in Linux | ||
5 | gpio_set_open_drain_value_commit, in drivers/gpio/gpiolib.c). | ||
6 | When the GPIO is set to input, the pull-up resistor brings the output | ||
7 | to 1, while when the GPIO is set to output, the output driver brings | ||
8 | the output to 0. | ||
9 | |||
10 | Implement this for the nRF51 GPIO device model. First, if both input and | ||
11 | output are floating, and there is a pull-up or pull-down resistor | ||
12 | configured, do not just set s->in, but also make any devices listening | ||
13 | on the output qemu_irq receive that value. Second, if the pin is | ||
14 | driven both internally (output pin) and externally you don't get a | ||
15 | short circuit if both sides drive the pin to the same value. | ||
16 | |||
17 | Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> | ||
18 | Acked-by: Stefan Hajnoczi <stefanha@redhat.com> | ||
19 | Message-id: 20190317141001.3346-1-pbonzini@redhat.com | ||
20 | [PMM: wrapped long line] | ||
21 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
23 | --- | ||
24 | hw/gpio/nrf51_gpio.c | 65 +++++++++++++++++++++++++++----------------- | ||
25 | 1 file changed, 40 insertions(+), 25 deletions(-) | ||
26 | |||
27 | diff --git a/hw/gpio/nrf51_gpio.c b/hw/gpio/nrf51_gpio.c | ||
28 | index XXXXXXX..XXXXXXX 100644 | ||
29 | --- a/hw/gpio/nrf51_gpio.c | ||
30 | +++ b/hw/gpio/nrf51_gpio.c | ||
31 | @@ -XXX,XX +XXX,XX @@ static bool is_connected(uint32_t config, uint32_t level) | ||
32 | return state; | ||
33 | } | ||
34 | |||
35 | +static int pull_value(uint32_t config) | ||
36 | +{ | ||
37 | + int pull = extract32(config, 2, 2); | ||
38 | + if (pull == NRF51_GPIO_PULLDOWN) { | ||
39 | + return 0; | ||
40 | + } else if (pull == NRF51_GPIO_PULLUP) { | ||
41 | + return 1; | ||
42 | + } | ||
43 | + return -1; | ||
44 | +} | ||
45 | + | ||
46 | static void update_output_irq(NRF51GPIOState *s, size_t i, | ||
47 | bool connected, bool level) | ||
48 | { | ||
49 | @@ -XXX,XX +XXX,XX @@ static void update_output_irq(NRF51GPIOState *s, size_t i, | ||
50 | |||
51 | static void update_state(NRF51GPIOState *s) | ||
52 | { | ||
53 | - uint32_t pull; | ||
54 | + int pull; | ||
55 | size_t i; | ||
56 | - bool connected_out, dir, connected_in, out, input; | ||
57 | + bool connected_out, dir, connected_in, out, in, input; | ||
58 | |||
59 | for (i = 0; i < NRF51_GPIO_PINS; i++) { | ||
60 | - pull = extract32(s->cnf[i], 2, 2); | ||
61 | + pull = pull_value(s->cnf[i]); | ||
62 | dir = extract32(s->cnf[i], 0, 1); | ||
63 | connected_in = extract32(s->in_mask, i, 1); | ||
64 | out = extract32(s->out, i, 1); | ||
65 | + in = extract32(s->in, i, 1); | ||
66 | input = !extract32(s->cnf[i], 1, 1); | ||
67 | connected_out = is_connected(s->cnf[i], out) && dir; | ||
68 | |||
69 | - update_output_irq(s, i, connected_out, out); | ||
70 | - | ||
71 | - /* Pin both driven externally and internally */ | ||
72 | - if (connected_out && connected_in) { | ||
73 | - qemu_log_mask(LOG_GUEST_ERROR, "GPIO pin %zu short circuited\n", i); | ||
74 | - } | ||
75 | - | ||
76 | - /* | ||
77 | - * Input buffer disconnected from internal/external drives, so | ||
78 | - * pull-up/pull-down becomes relevant | ||
79 | - */ | ||
80 | - if (!input || (input && !connected_in && !connected_out)) { | ||
81 | - if (pull == NRF51_GPIO_PULLDOWN) { | ||
82 | - s->in = deposit32(s->in, i, 1, 0); | ||
83 | - } else if (pull == NRF51_GPIO_PULLUP) { | ||
84 | - s->in = deposit32(s->in, i, 1, 1); | ||
85 | + if (!input) { | ||
86 | + if (pull >= 0) { | ||
87 | + /* Input buffer disconnected from external drives */ | ||
88 | + s->in = deposit32(s->in, i, 1, pull); | ||
89 | + } | ||
90 | + } else { | ||
91 | + if (connected_out && connected_in && out != in) { | ||
92 | + /* Pin both driven externally and internally */ | ||
93 | + qemu_log_mask(LOG_GUEST_ERROR, | ||
94 | + "GPIO pin %zu short circuited\n", i); | ||
95 | + } | ||
96 | + if (!connected_in) { | ||
97 | + /* | ||
98 | + * Floating input: the output stimulates IN if connected, | ||
99 | + * otherwise pull-up/pull-down resistors put a value on both | ||
100 | + * IN and OUT. | ||
101 | + */ | ||
102 | + if (pull >= 0 && !connected_out) { | ||
103 | + connected_out = true; | ||
104 | + out = pull; | ||
105 | + } | ||
106 | + if (connected_out) { | ||
107 | + s->in = deposit32(s->in, i, 1, out); | ||
108 | + } | ||
109 | } | ||
110 | } | ||
111 | - | ||
112 | - /* Self stimulation through internal output driver */ | ||
113 | - if (connected_out && !connected_in && input) { | ||
114 | - s->in = deposit32(s->in, i, 1, out); | ||
115 | - } | ||
116 | + update_output_irq(s, i, connected_out, out); | ||
117 | } | ||
118 | - | ||
119 | } | ||
120 | |||
121 | /* | ||
122 | -- | ||
123 | 2.20.1 | ||
124 | |||
125 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Andrew Jones <drjones@redhat.com> | ||
2 | 1 | ||
3 | In the kconfig shuffle arm lost pci-testdev which is used by | ||
4 | kvm-unit-tests. Let's add it back. | ||
5 | |||
6 | Signed-off-by: Andrew Jones <drjones@redhat.com> | ||
7 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
8 | Message-id: 20190322163059.9716-1-drjones@redhat.com | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | default-configs/arm-softmmu.mak | 1 + | ||
12 | 1 file changed, 1 insertion(+) | ||
13 | |||
14 | diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/default-configs/arm-softmmu.mak | ||
17 | +++ b/default-configs/arm-softmmu.mak | ||
18 | @@ -XXX,XX +XXX,XX @@ | ||
19 | |||
20 | CONFIG_PCI=y | ||
21 | CONFIG_PCI_DEVICES=y | ||
22 | +CONFIG_PCI_TESTDEV=y | ||
23 | CONFIG_VGA=y | ||
24 | CONFIG_NAND=y | ||
25 | CONFIG_ECC=y | ||
26 | -- | ||
27 | 2.20.1 | ||
28 | |||
29 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Andrew Jones <drjones@redhat.com> | ||
2 | 1 | ||
3 | Fix a QEMU NULL derefence that occurs when the guest attempts to | ||
4 | enable PMU counters with a non-v8 cpu model or a v8 cpu model | ||
5 | which has not configured a PMU. | ||
6 | |||
7 | Fixes: 4e7beb0cc0f3 ("target/arm: Add a timer to predict PMU counter overflow") | ||
8 | Signed-off-by: Andrew Jones <drjones@redhat.com> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20190322162333.17159-2-drjones@redhat.com | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | target/arm/helper.c | 4 ++++ | ||
14 | 1 file changed, 4 insertions(+) | ||
15 | |||
16 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/arm/helper.c | ||
19 | +++ b/target/arm/helper.c | ||
20 | @@ -XXX,XX +XXX,XX @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) | ||
21 | int el = arm_current_el(env); | ||
22 | uint8_t hpmn = env->cp15.mdcr_el2 & MDCR_HPMN; | ||
23 | |||
24 | + if (!arm_feature(env, ARM_FEATURE_PMU)) { | ||
25 | + return false; | ||
26 | + } | ||
27 | + | ||
28 | if (!arm_feature(env, ARM_FEATURE_EL2) || | ||
29 | (counter < hpmn || counter == 31)) { | ||
30 | e = env->cp15.c9_pmcr & PMCRE; | ||
31 | -- | ||
32 | 2.20.1 | ||
33 | |||
34 | diff view generated by jsdifflib |
Deleted patch | |||
---|---|---|---|
1 | From: Andrew Jones <drjones@redhat.com> | ||
2 | 1 | ||
3 | cortex-a7 and cortex-a15 have pmus (PMUv2) and they advertise | ||
4 | them in ID_DFR0. Let's allow them to function. This also enables | ||
5 | the pmu cpu property to work with these cpu types, i.e. we can | ||
6 | now do '-cpu cortex-a15,pmu=off' to remove the pmu. | ||
7 | |||
8 | Signed-off-by: Andrew Jones <drjones@redhat.com> | ||
9 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Message-id: 20190322162333.17159-3-drjones@redhat.com | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
12 | --- | ||
13 | target/arm/cpu.c | 3 +++ | ||
14 | 1 file changed, 3 insertions(+) | ||
15 | |||
16 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
17 | index XXXXXXX..XXXXXXX 100644 | ||
18 | --- a/target/arm/cpu.c | ||
19 | +++ b/target/arm/cpu.c | ||
20 | @@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) | ||
21 | #endif | ||
22 | } else { | ||
23 | cpu->id_aa64dfr0 &= ~0xf00; | ||
24 | + cpu->id_dfr0 &= ~(0xf << 24); | ||
25 | cpu->pmceid0 = 0; | ||
26 | cpu->pmceid1 = 0; | ||
27 | } | ||
28 | @@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj) | ||
29 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
30 | set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
31 | set_feature(&cpu->env, ARM_FEATURE_EL3); | ||
32 | + set_feature(&cpu->env, ARM_FEATURE_PMU); | ||
33 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; | ||
34 | cpu->midr = 0x410fc075; | ||
35 | cpu->reset_fpsid = 0x41023075; | ||
36 | @@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj) | ||
37 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
38 | set_feature(&cpu->env, ARM_FEATURE_EL2); | ||
39 | set_feature(&cpu->env, ARM_FEATURE_EL3); | ||
40 | + set_feature(&cpu->env, ARM_FEATURE_PMU); | ||
41 | cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; | ||
42 | cpu->midr = 0x412fc0f1; | ||
43 | cpu->reset_fpsid = 0x410430f0; | ||
44 | -- | ||
45 | 2.20.1 | ||
46 | |||
47 | diff view generated by jsdifflib |