[Qemu-devel] [PULL 0/6] target-arm queue
[Qemu-devel] [PULL v2 00/48] target-arm queue
1
A small set of arm bugfixes for rc1 tomorrow.
1
v1->v2 changes: fix a clang warning about bitfields;
2
drop a patch from Julia that I accidentally included
3
(it will likely be in a future series).
2
4
3
thanks
5
The following changes since commit a8d2b0685681e2f291faaa501efbbd76875f8ec8:
4
-- PMM
5
6
6
The following changes since commit c442b7b4a7ae8696bcdf46091d781bd9052731be:
7
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190118' into staging (2019-01-18 16:56:15 +0000)
7
8
Merge remote-tracking branch 'remotes/elmarco/tags/slirp-pull-request' into staging (2019-03-25 07:59:40 +0000)
9
8
10
are available in the Git repository at:
9
are available in the Git repository at:
11
10
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190325
11
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190121
13
12
14
for you to fetch changes up to f2b2f53f6429b5abd7cd86bd65747f5f13e195eb:
13
for you to fetch changes up to 0d4bfd7df809863b1f45fad35229fb9419527d06:
15
14
16
target/arm: make pmccntr_op_start/finish static (2019-03-25 14:16:47 +0000)
15
target/arm: Implement PMSWINC (2019-01-21 10:38:56 +0000)
17
16
18
----------------------------------------------------------------
17
----------------------------------------------------------------
19
target-arm queue:
18
target-arm queue:
20
* Fix non-parallel expansion of CASP
19
* hw/char/stm32f2xx_usart: Do not update data register when device is disabled
21
* nrf51_gpio: reflect pull-up/pull-down to IRQs
20
* hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node
22
* Fix crash if guest tries to enable non-existent PMU counters
21
* target/arm: Allow Aarch32 exception return to switch from Mon->Hyp
23
* Add PMUv2 to the Cortex-A15 and Cortex-A7
22
* ftgmac100: implement the new MDIO interface on Aspeed SoC
24
* Make pmccntr_op_start/finish static
23
* implement the ARMv8.3-PAuth extension
24
* improve emulation of the ARM PMU
25
25
26
----------------------------------------------------------------
26
----------------------------------------------------------------
27
Andrew Jones (4):
27
Aaron Lindsay (13):
28
target/arm: add PCI_TESTDEV back to default config
28
migration: Add post_save function to VMStateDescription
29
target/arm: fix crash on pmu register access
29
target/arm: Reorganize PMCCNTR accesses
30
target/arm: cortex-a7 and cortex-a15 have pmus
30
target/arm: Swap PMU values before/after migrations
31
target/arm: make pmccntr_op_start/finish static
31
target/arm: Filter cycle counter based on PMCCFILTR_EL0
32
target/arm: Allow AArch32 access for PMCCFILTR
33
target/arm: Implement PMOVSSET
34
target/arm: Define FIELDs for ID_DFR0
35
target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23]
36
target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0
37
target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER
38
target/arm: PMU: Add instruction and cycle events
39
target/arm: PMU: Set PMCR.N to 4
40
target/arm: Implement PMSWINC
32
41
33
Paolo Bonzini (1):
42
Alexander Graf (1):
34
nrf51_gpio: reflect pull-up/pull-down to IRQs
43
target/arm: Allow Aarch32 exception return to switch from Mon->Hyp
35
44
36
Richard Henderson (1):
45
Cédric Le Goater (1):
37
target/arm: Fix non-parallel expansion of CASP
46
ftgmac100: implement the new MDIO interface on Aspeed SoC
38
47
39
target/arm/cpu.h | 11 -------
48
Eric Auger (1):
40
hw/gpio/nrf51_gpio.c | 65 +++++++++++++++++++++++++----------------
49
hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node
41
target/arm/cpu.c | 3 ++
42
target/arm/helper.c | 8 +++--
43
target/arm/translate-a64.c | 2 +-
44
default-configs/arm-softmmu.mak | 1 +
45
6 files changed, 51 insertions(+), 39 deletions(-)
46
50
51
Philippe Mathieu-Daudé (1):
52
hw/char/stm32f2xx_usart: Do not update data register when device is disabled
53
54
Richard Henderson (31):
55
target/arm: Add state for the ARMv8.3-PAuth extension
56
target/arm: Add SCTLR bits through ARMv8.5
57
target/arm: Add PAuth active bit to tbflags
58
target/arm: Introduce raise_exception_ra
59
target/arm: Add PAuth helpers
60
target/arm: Decode PAuth within system hint space
61
target/arm: Rearrange decode in disas_data_proc_1src
62
target/arm: Decode PAuth within disas_data_proc_1src
63
target/arm: Decode PAuth within disas_data_proc_2src
64
target/arm: Move helper_exception_return to helper-a64.c
65
target/arm: Add new_pc argument to helper_exception_return
66
target/arm: Rearrange decode in disas_uncond_b_reg
67
target/arm: Decode PAuth within disas_uncond_b_reg
68
target/arm: Decode Load/store register (pac)
69
target/arm: Move cpu_mmu_index out of line
70
target/arm: Introduce arm_mmu_idx
71
target/arm: Introduce arm_stage1_mmu_idx
72
target/arm: Create ARMVAParameters and helpers
73
target/arm: Merge TBFLAG_AA_TB{0, 1} to TBII
74
target/arm: Export aa64_va_parameters to internals.h
75
target/arm: Add aa64_va_parameters_both
76
target/arm: Decode TBID from TCR
77
target/arm: Reuse aa64_va_parameters for setting tbflags
78
target/arm: Implement pauth_strip
79
target/arm: Implement pauth_auth
80
target/arm: Implement pauth_addpac
81
target/arm: Implement pauth_computepac
82
target/arm: Add PAuth system registers
83
target/arm: Enable PAuth for -cpu max
84
target/arm: Enable PAuth for user-only
85
target/arm: Tidy TBI handling in gen_a64_set_pc
86
87
target/arm/Makefile.objs | 1 +
88
include/hw/acpi/acpi-defs.h | 2 +
89
include/migration/vmstate.h | 1 +
90
target/arm/cpu.h | 244 +++++----
91
target/arm/helper-a64.h | 14 +
92
target/arm/helper.h | 1 -
93
target/arm/internals.h | 77 +++
94
target/arm/translate.h | 5 +-
95
hw/arm/virt-acpi-build.c | 1 +
96
hw/char/stm32f2xx_usart.c | 3 +-
97
hw/net/ftgmac100.c | 80 ++-
98
migration/vmstate.c | 13 +-
99
target/arm/cpu.c | 19 +-
100
target/arm/cpu64.c | 68 ++-
101
target/arm/helper-a64.c | 155 ++++++
102
target/arm/helper.c | 1222 +++++++++++++++++++++++++++++++++----------
103
target/arm/machine.c | 24 +
104
target/arm/op_helper.c | 174 +-----
105
target/arm/pauth_helper.c | 497 ++++++++++++++++++
106
target/arm/translate-a64.c | 537 ++++++++++++++++---
107
docs/devel/migration.rst | 9 +-
108
21 files changed, 2515 insertions(+), 632 deletions(-)
109
create mode 100644 target/arm/pauth_helper.c
110
diff view generated by jsdifflib
[Qemu-devel] [PULL 1/6] target/arm: Fix non-parallel expansion of CASP
Deleted patch
1
From: Richard Henderson <richard.henderson@linaro.org>
2
1
3
The second word has been loaded from the unincremented
4
address since the first commit.
5
6
Fixes: 44ac14b06fa
7
Reported-by: Alex Bennée <alex.bennee@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
10
Tested-by: Alex Bennée <alex.bennee@linaro.org>
11
Message-id: 20190322234302.12770-1-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/translate-a64.c | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
16
17
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/translate-a64.c
20
+++ b/target/arm/translate-a64.c
21
@@ -XXX,XX +XXX,XX @@ static void gen_compare_and_swap_pair(DisasContext *s, int rs, int rt,
22
tcg_gen_qemu_ld_i64(d1, clean_addr, memidx,
23
MO_64 | MO_ALIGN_16 | s->be_data);
24
tcg_gen_addi_i64(a2, clean_addr, 8);
25
- tcg_gen_qemu_ld_i64(d2, clean_addr, memidx, MO_64 | s->be_data);
26
+ tcg_gen_qemu_ld_i64(d2, a2, memidx, MO_64 | s->be_data);
27
28
/* Compare the two words, also in memory order. */
29
tcg_gen_setcond_i64(TCG_COND_EQ, c1, d1, s1);
30
--
31
2.20.1
32
33
diff view generated by jsdifflib
[Qemu-devel] [PULL 2/6] nrf51_gpio: reflect pull-up/pull-down to IRQs
Deleted patch
1
From: Paolo Bonzini <pbonzini@redhat.com>
2
1
3
Some drivers do I2C bitbanging by keeping the output to 0 and flipping
4
the GPIO direction between input and output (see for example in Linux
5
gpio_set_open_drain_value_commit, in drivers/gpio/gpiolib.c).
6
When the GPIO is set to input, the pull-up resistor brings the output
7
to 1, while when the GPIO is set to output, the output driver brings
8
the output to 0.
9
10
Implement this for the nRF51 GPIO device model. First, if both input and
11
output are floating, and there is a pull-up or pull-down resistor
12
configured, do not just set s->in, but also make any devices listening
13
on the output qemu_irq receive that value. Second, if the pin is
14
driven both internally (output pin) and externally you don't get a
15
short circuit if both sides drive the pin to the same value.
16
17
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
18
Acked-by: Stefan Hajnoczi <stefanha@redhat.com>
19
Message-id: 20190317141001.3346-1-pbonzini@redhat.com
20
[PMM: wrapped long line]
21
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23
---
24
hw/gpio/nrf51_gpio.c | 65 +++++++++++++++++++++++++++-----------------
25
1 file changed, 40 insertions(+), 25 deletions(-)
26
27
diff --git a/hw/gpio/nrf51_gpio.c b/hw/gpio/nrf51_gpio.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/hw/gpio/nrf51_gpio.c
30
+++ b/hw/gpio/nrf51_gpio.c
31
@@ -XXX,XX +XXX,XX @@ static bool is_connected(uint32_t config, uint32_t level)
32
return state;
33
}
34
35
+static int pull_value(uint32_t config)
36
+{
37
+ int pull = extract32(config, 2, 2);
38
+ if (pull == NRF51_GPIO_PULLDOWN) {
39
+ return 0;
40
+ } else if (pull == NRF51_GPIO_PULLUP) {
41
+ return 1;
42
+ }
43
+ return -1;
44
+}
45
+
46
static void update_output_irq(NRF51GPIOState *s, size_t i,
47
bool connected, bool level)
48
{
49
@@ -XXX,XX +XXX,XX @@ static void update_output_irq(NRF51GPIOState *s, size_t i,
50
51
static void update_state(NRF51GPIOState *s)
52
{
53
- uint32_t pull;
54
+ int pull;
55
size_t i;
56
- bool connected_out, dir, connected_in, out, input;
57
+ bool connected_out, dir, connected_in, out, in, input;
58
59
for (i = 0; i < NRF51_GPIO_PINS; i++) {
60
- pull = extract32(s->cnf[i], 2, 2);
61
+ pull = pull_value(s->cnf[i]);
62
dir = extract32(s->cnf[i], 0, 1);
63
connected_in = extract32(s->in_mask, i, 1);
64
out = extract32(s->out, i, 1);
65
+ in = extract32(s->in, i, 1);
66
input = !extract32(s->cnf[i], 1, 1);
67
connected_out = is_connected(s->cnf[i], out) && dir;
68
69
- update_output_irq(s, i, connected_out, out);
70
-
71
- /* Pin both driven externally and internally */
72
- if (connected_out && connected_in) {
73
- qemu_log_mask(LOG_GUEST_ERROR, "GPIO pin %zu short circuited\n", i);
74
- }
75
-
76
- /*
77
- * Input buffer disconnected from internal/external drives, so
78
- * pull-up/pull-down becomes relevant
79
- */
80
- if (!input || (input && !connected_in && !connected_out)) {
81
- if (pull == NRF51_GPIO_PULLDOWN) {
82
- s->in = deposit32(s->in, i, 1, 0);
83
- } else if (pull == NRF51_GPIO_PULLUP) {
84
- s->in = deposit32(s->in, i, 1, 1);
85
+ if (!input) {
86
+ if (pull >= 0) {
87
+ /* Input buffer disconnected from external drives */
88
+ s->in = deposit32(s->in, i, 1, pull);
89
+ }
90
+ } else {
91
+ if (connected_out && connected_in && out != in) {
92
+ /* Pin both driven externally and internally */
93
+ qemu_log_mask(LOG_GUEST_ERROR,
94
+ "GPIO pin %zu short circuited\n", i);
95
+ }
96
+ if (!connected_in) {
97
+ /*
98
+ * Floating input: the output stimulates IN if connected,
99
+ * otherwise pull-up/pull-down resistors put a value on both
100
+ * IN and OUT.
101
+ */
102
+ if (pull >= 0 && !connected_out) {
103
+ connected_out = true;
104
+ out = pull;
105
+ }
106
+ if (connected_out) {
107
+ s->in = deposit32(s->in, i, 1, out);
108
+ }
109
}
110
}
111
-
112
- /* Self stimulation through internal output driver */
113
- if (connected_out && !connected_in && input) {
114
- s->in = deposit32(s->in, i, 1, out);
115
- }
116
+ update_output_irq(s, i, connected_out, out);
117
}
118
-
119
}
120
121
/*
122
--
123
2.20.1
124
125
diff view generated by jsdifflib
[Qemu-devel] [PULL 3/6] target/arm: add PCI_TESTDEV back to default config
Deleted patch
1
From: Andrew Jones <drjones@redhat.com>
2
1
3
In the kconfig shuffle arm lost pci-testdev which is used by
4
kvm-unit-tests. Let's add it back.
5
6
Signed-off-by: Andrew Jones <drjones@redhat.com>
7
Reviewed-by: Thomas Huth <thuth@redhat.com>
8
Message-id: 20190322163059.9716-1-drjones@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
default-configs/arm-softmmu.mak | 1 +
12
1 file changed, 1 insertion(+)
13
14
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
15
index XXXXXXX..XXXXXXX 100644
16
--- a/default-configs/arm-softmmu.mak
17
+++ b/default-configs/arm-softmmu.mak
18
@@ -XXX,XX +XXX,XX @@
19
20
CONFIG_PCI=y
21
CONFIG_PCI_DEVICES=y
22
+CONFIG_PCI_TESTDEV=y
23
CONFIG_VGA=y
24
CONFIG_NAND=y
25
CONFIG_ECC=y
26
--
27
2.20.1
28
29
diff view generated by jsdifflib
[Qemu-devel] [PULL 4/6] target/arm: fix crash on pmu register access
Deleted patch
1
From: Andrew Jones <drjones@redhat.com>
2
1
3
Fix a QEMU NULL derefence that occurs when the guest attempts to
4
enable PMU counters with a non-v8 cpu model or a v8 cpu model
5
which has not configured a PMU.
6
7
Fixes: 4e7beb0cc0f3 ("target/arm: Add a timer to predict PMU counter overflow")
8
Signed-off-by: Andrew Jones <drjones@redhat.com>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20190322162333.17159-2-drjones@redhat.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/helper.c | 4 ++++
14
1 file changed, 4 insertions(+)
15
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper.c
19
+++ b/target/arm/helper.c
20
@@ -XXX,XX +XXX,XX @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
21
int el = arm_current_el(env);
22
uint8_t hpmn = env->cp15.mdcr_el2 & MDCR_HPMN;
23
24
+ if (!arm_feature(env, ARM_FEATURE_PMU)) {
25
+ return false;
26
+ }
27
+
28
if (!arm_feature(env, ARM_FEATURE_EL2) ||
29
(counter < hpmn || counter == 31)) {
30
e = env->cp15.c9_pmcr & PMCRE;
31
--
32
2.20.1
33
34
diff view generated by jsdifflib
[Qemu-devel] [PULL 5/6] target/arm: cortex-a7 and cortex-a15 have pmus
Deleted patch
1
From: Andrew Jones <drjones@redhat.com>
2
1
3
cortex-a7 and cortex-a15 have pmus (PMUv2) and they advertise
4
them in ID_DFR0. Let's allow them to function. This also enables
5
the pmu cpu property to work with these cpu types, i.e. we can
6
now do '-cpu cortex-a15,pmu=off' to remove the pmu.
7
8
Signed-off-by: Andrew Jones <drjones@redhat.com>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20190322162333.17159-3-drjones@redhat.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/cpu.c | 3 +++
14
1 file changed, 3 insertions(+)
15
16
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.c
19
+++ b/target/arm/cpu.c
20
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
21
#endif
22
} else {
23
cpu->id_aa64dfr0 &= ~0xf00;
24
+ cpu->id_dfr0 &= ~(0xf << 24);
25
cpu->pmceid0 = 0;
26
cpu->pmceid1 = 0;
27
}
28
@@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj)
29
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
30
set_feature(&cpu->env, ARM_FEATURE_EL2);
31
set_feature(&cpu->env, ARM_FEATURE_EL3);
32
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
33
cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7;
34
cpu->midr = 0x410fc075;
35
cpu->reset_fpsid = 0x41023075;
36
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
37
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
38
set_feature(&cpu->env, ARM_FEATURE_EL2);
39
set_feature(&cpu->env, ARM_FEATURE_EL3);
40
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
41
cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
42
cpu->midr = 0x412fc0f1;
43
cpu->reset_fpsid = 0x410430f0;
44
--
45
2.20.1
46
47
diff view generated by jsdifflib
[Qemu-devel] [PULL 6/6] target/arm: make pmccntr_op_start/finish static
Deleted patch
1
From: Andrew Jones <drjones@redhat.com>
2
1
3
These functions are not used outside helper.c
4
5
Signed-off-by: Andrew Jones <drjones@redhat.com>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20190322162333.17159-4-drjones@redhat.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/cpu.h | 11 -----------
11
target/arm/helper.c | 4 ++--
12
2 files changed, 2 insertions(+), 13 deletions(-)
13
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.h
17
+++ b/target/arm/cpu.h
18
@@ -XXX,XX +XXX,XX @@ static inline bool is_a64(CPUARMState *env)
19
int cpu_arm_signal_handler(int host_signum, void *pinfo,
20
void *puc);
21
22
-/**
23
- * pmccntr_op_start/finish
24
- * @env: CPUARMState
25
- *
26
- * Convert the counter in the PMCCNTR between its delta form (the typical mode
27
- * when it's enabled) and the guest-visible value. These two calls must always
28
- * surround any action which might affect the counter.
29
- */
30
-void pmccntr_op_start(CPUARMState *env);
31
-void pmccntr_op_finish(CPUARMState *env);
32
-
33
/**
34
* pmu_op_start/finish
35
* @env: CPUARMState
36
diff --git a/target/arm/helper.c b/target/arm/helper.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/helper.c
39
+++ b/target/arm/helper.c
40
@@ -XXX,XX +XXX,XX @@ static void pmu_update_irq(CPUARMState *env)
41
* etc. can be done logically. This is essentially a no-op if the counter is
42
* not enabled at the time of the call.
43
*/
44
-void pmccntr_op_start(CPUARMState *env)
45
+static void pmccntr_op_start(CPUARMState *env)
46
{
47
uint64_t cycles = cycles_get_count(env);
48
49
@@ -XXX,XX +XXX,XX @@ void pmccntr_op_start(CPUARMState *env)
50
* guest-visible count. A call to pmccntr_op_finish should follow every call to
51
* pmccntr_op_start.
52
*/
53
-void pmccntr_op_finish(CPUARMState *env)
54
+static void pmccntr_op_finish(CPUARMState *env)
55
{
56
if (pmu_counter_enabled(env, 31)) {
57
#ifndef CONFIG_USER_ONLY
58
--
59
2.20.1
60
61
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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