1 | target-arm queue for softfreeze: | 1 | The following changes since commit 5767815218efd3cbfd409505ed824d5f356044ae: |
---|---|---|---|
2 | This has all the big stuff I want to get in for softfreeze; | ||
3 | there may be one or two smaller patches I pick up later in | ||
4 | the week. | ||
5 | 2 | ||
6 | thanks | 3 | Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging (2024-02-14 15:45:52 +0000) |
7 | -- PMM | ||
8 | |||
9 | The following changes since commit 0984a157c1c053394adbf64ed7de97f1aebe6a2d: | ||
10 | |||
11 | Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging (2019-03-05 09:33:20 +0000) | ||
12 | 4 | ||
13 | are available in the Git repository at: | 5 | are available in the Git repository at: |
14 | 6 | ||
15 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190305 | 7 | https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20240215 |
16 | 8 | ||
17 | for you to fetch changes up to 566528f823d1a2e9eb2d7b2ed839547cb31bfc34: | 9 | for you to fetch changes up to f780e63fe731b058fe52d43653600d8729a1b5f2: |
18 | 10 | ||
19 | hw/arm/stellaris: Implement watchdog timer (2019-03-05 15:55:09 +0000) | 11 | docs: Add documentation for the mps3-an536 board (2024-02-15 14:32:39 +0000) |
20 | 12 | ||
21 | ---------------------------------------------------------------- | 13 | ---------------------------------------------------------------- |
22 | target-arm queue: | 14 | target-arm queue: |
23 | * Fix PC test for LDM (exception return) | 15 | * hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC |
24 | * Implement ARMv8.0-SB | 16 | * linux-user/aarch64: Choose SYNC as the preferred MTE mode |
25 | * Implement ARMv8.0-PredInv | 17 | * Fix some errors in SVE/SME handling of MTE tags |
26 | * Implement ARMv8.4-CondM | 18 | * hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses |
27 | * Implement ARMv8.5-CondM | 19 | * hw/block/tc58128: Don't emit deprecation warning under qtest |
28 | * Implement ARMv8.5-FRINT | 20 | * tests/qtest: Fix handling of npcm7xx and GMAC tests |
29 | * hw/arm/stellaris: Implement watchdog timer | 21 | * hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ |
30 | * virt: support more than 255GB of RAM | 22 | * tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend |
23 | * Don't assert on vmload/vmsave of M-profile CPUs | ||
24 | * hw/arm/smmuv3: add support for stage 1 access fault | ||
25 | * hw/arm/stellaris: QOM cleanups | ||
26 | * Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs | ||
27 | * Improve Cortex_R52 IMPDEF sysreg modelling | ||
28 | * Allow access to SPSR_hyp from hyp mode | ||
29 | * New board model mps3-an536 (Cortex-R52) | ||
31 | 30 | ||
32 | ---------------------------------------------------------------- | 31 | ---------------------------------------------------------------- |
33 | Eric Auger (9): | 32 | Luc Michel (1): |
34 | hw/arm/virt: Rename highmem IO regions | 33 | hw/arm/smmuv3: add support for stage 1 access fault |
35 | hw/arm/virt: Split the memory map description | ||
36 | hw/boards: Add a MachineState parameter to kvm_type callback | ||
37 | kvm: add kvm_arm_get_max_vm_ipa_size | ||
38 | vl: Set machine ram_size, maxram_size and ram_slots earlier | ||
39 | hw/arm/virt: Dynamic memory map depending on RAM requirements | ||
40 | hw/arm/virt: Implement kvm_type function for 4.0 machine | ||
41 | hw/arm/virt: Check the VCPU PA range in TCG mode | ||
42 | hw/arm/virt: Bump the 255GB initial RAM limit | ||
43 | 34 | ||
44 | Michel Heily (1): | 35 | Nabih Estefan (1): |
45 | hw/arm/stellaris: Implement watchdog timer | 36 | tests/qtest: Fix GMAC test to run on a machine in upstream QEMU |
46 | 37 | ||
47 | Richard Henderson (11): | 38 | Peter Maydell (22): |
48 | target/arm: Fix PC test for LDM (exception return) | 39 | hw/pci-host/raven.c: Mark raven_io_ops as implementing unaligned accesses |
49 | target/arm: Split out arm_sctlr | 40 | hw/block/tc58128: Don't emit deprecation warning under qtest |
50 | target/arm: Implement ARMv8.0-SB | 41 | tests/qtest/meson.build: Don't include qtests_npcm7xx in qtests_aarch64 |
51 | target/arm: Implement ARMv8.0-PredInv | 42 | tests/qtest/bios-tables-test: Allow changes to virt GTDT |
52 | target/arm: Split helper_msr_i_pstate into 3 | 43 | hw/arm/virt: Wire up non-secure EL2 virtual timer IRQ |
53 | target/arm: Add set/clear_pstate_bits, share gen_ss_advance | 44 | tests/qtest/bios-tables-tests: Update virt golden reference |
54 | target/arm: Rearrange disas_data_proc_reg | 45 | hw/arm/npcm7xx: Call qemu_configure_nic_device() for GMAC modules |
55 | target/arm: Implement ARMv8.4-CondM | 46 | tests/qtest/npcm7xx_emc-test: Connect all NICs to a backend |
56 | target/arm: Implement ARMv8.5-CondM | 47 | target/arm: Don't get MDCR_EL2 in pmu_counter_enabled() before checking ARM_FEATURE_PMU |
57 | target/arm: Restructure handle_fp_1src_{single, double} | 48 | target/arm: Use new CBAR encoding for all v8 CPUs, not all aarch64 CPUs |
58 | target/arm: Implement ARMv8.5-FRINT | 49 | target/arm: The Cortex-R52 has a read-only CBAR |
50 | target/arm: Add Cortex-R52 IMPDEF sysregs | ||
51 | target/arm: Allow access to SPSR_hyp from hyp mode | ||
52 | hw/misc/mps2-scc: Fix condition for CFG3 register | ||
53 | hw/misc/mps2-scc: Factor out which-board conditionals | ||
54 | hw/misc/mps2-scc: Make changes needed for AN536 FPGA image | ||
55 | hw/arm/mps3r: Initial skeleton for mps3-an536 board | ||
56 | hw/arm/mps3r: Add CPUs, GIC, and per-CPU RAM | ||
57 | hw/arm/mps3r: Add UARTs | ||
58 | hw/arm/mps3r: Add GPIO, watchdog, dual-timer, I2C devices | ||
59 | hw/arm/mps3r: Add remaining devices | ||
60 | docs: Add documentation for the mps3-an536 board | ||
59 | 61 | ||
60 | Shameer Kolothum (1): | 62 | Philippe Mathieu-Daudé (5): |
61 | hw/arm/boot: introduce fdt_add_memory_node helper | 63 | hw/arm/xilinx_zynq: Wire FIQ between CPU <> GIC |
64 | hw/arm/stellaris: Convert ADC controller to Resettable interface | ||
65 | hw/arm/stellaris: Convert I2C controller to Resettable interface | ||
66 | hw/arm/stellaris: Add missing QOM 'machine' parent | ||
67 | hw/arm/stellaris: Add missing QOM 'SoC' parent | ||
62 | 68 | ||
63 | include/hw/arm/virt.h | 16 +- | 69 | Richard Henderson (6): |
64 | include/hw/boards.h | 5 +- | 70 | linux-user/aarch64: Choose SYNC as the preferred MTE mode |
65 | include/hw/watchdog/cmsdk-apb-watchdog.h | 8 + | 71 | target/arm: Fix nregs computation in do_{ld,st}_zpa |
66 | target/arm/cpu.h | 64 ++++- | 72 | target/arm: Adjust and validate mtedesc sizem1 |
67 | target/arm/helper-a64.h | 3 + | 73 | target/arm: Split out make_svemte_desc |
68 | target/arm/helper.h | 8 +- | 74 | target/arm: Handle mte in do_ldrq, do_ldro |
69 | target/arm/internals.h | 15 + | 75 | target/arm: Fix SVE/SME gross MTE suppression checks |
70 | target/arm/kvm_arm.h | 13 + | ||
71 | target/arm/translate.h | 34 +++ | ||
72 | accel/kvm/kvm-all.c | 2 +- | ||
73 | hw/arm/boot.c | 54 ++-- | ||
74 | hw/arm/stellaris.c | 22 +- | ||
75 | hw/arm/virt-acpi-build.c | 10 +- | ||
76 | hw/arm/virt.c | 196 ++++++++++--- | ||
77 | hw/ppc/mac_newworld.c | 3 +- | ||
78 | hw/ppc/mac_oldworld.c | 2 +- | ||
79 | hw/ppc/spapr.c | 2 +- | ||
80 | hw/watchdog/cmsdk-apb-watchdog.c | 74 ++++- | ||
81 | linux-user/elfload.c | 2 + | ||
82 | target/arm/cpu.c | 2 + | ||
83 | target/arm/cpu64.c | 6 + | ||
84 | target/arm/helper-a64.c | 30 ++ | ||
85 | target/arm/helper.c | 63 +++- | ||
86 | target/arm/kvm.c | 10 + | ||
87 | target/arm/op_helper.c | 47 --- | ||
88 | target/arm/translate-a64.c | 478 +++++++++++++++++++++++-------- | ||
89 | target/arm/translate.c | 35 ++- | ||
90 | target/arm/vfp_helper.c | 96 +++++++ | ||
91 | vl.c | 6 +- | ||
92 | 29 files changed, 1032 insertions(+), 274 deletions(-) | ||
93 | 76 | ||
77 | MAINTAINERS | 3 +- | ||
78 | docs/system/arm/mps2.rst | 37 +- | ||
79 | configs/devices/arm-softmmu/default.mak | 1 + | ||
80 | hw/arm/smmuv3-internal.h | 1 + | ||
81 | include/hw/arm/smmu-common.h | 1 + | ||
82 | include/hw/arm/virt.h | 2 + | ||
83 | include/hw/misc/mps2-scc.h | 1 + | ||
84 | linux-user/aarch64/target_prctl.h | 29 +- | ||
85 | target/arm/internals.h | 2 +- | ||
86 | target/arm/tcg/translate-a64.h | 2 + | ||
87 | hw/arm/mps3r.c | 640 ++++++++++++++++++++++++++++++++ | ||
88 | hw/arm/npcm7xx.c | 1 + | ||
89 | hw/arm/smmu-common.c | 11 + | ||
90 | hw/arm/smmuv3.c | 1 + | ||
91 | hw/arm/stellaris.c | 47 ++- | ||
92 | hw/arm/virt-acpi-build.c | 20 +- | ||
93 | hw/arm/virt.c | 60 ++- | ||
94 | hw/arm/xilinx_zynq.c | 2 + | ||
95 | hw/block/tc58128.c | 4 +- | ||
96 | hw/misc/mps2-scc.c | 138 ++++++- | ||
97 | hw/pci-host/raven.c | 1 + | ||
98 | target/arm/helper.c | 14 +- | ||
99 | target/arm/tcg/cpu32.c | 109 ++++++ | ||
100 | target/arm/tcg/op_helper.c | 43 ++- | ||
101 | target/arm/tcg/sme_helper.c | 8 +- | ||
102 | target/arm/tcg/sve_helper.c | 12 +- | ||
103 | target/arm/tcg/translate-sme.c | 15 +- | ||
104 | target/arm/tcg/translate-sve.c | 83 +++-- | ||
105 | target/arm/tcg/translate.c | 19 +- | ||
106 | tests/qtest/npcm7xx_emc-test.c | 5 +- | ||
107 | tests/qtest/npcm_gmac-test.c | 84 +---- | ||
108 | hw/arm/Kconfig | 5 + | ||
109 | hw/arm/meson.build | 1 + | ||
110 | tests/data/acpi/virt/FACP | Bin 276 -> 276 bytes | ||
111 | tests/data/acpi/virt/GTDT | Bin 96 -> 104 bytes | ||
112 | tests/qtest/meson.build | 4 +- | ||
113 | 36 files changed, 1184 insertions(+), 222 deletions(-) | ||
114 | create mode 100644 hw/arm/mps3r.c | ||
115 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Now we have the extended memory map (high IO regions beyond the | 3 | Similarly to commits dadbb58f59..5ae79fe825 for other ARM boards, |
4 | scalable RAM) and dynamic IPA range support at KVM/ARM level | 4 | connect FIQ output of the GIC CPU interfaces to the CPU. |
5 | we can bump the legacy 255GB initial RAM limit. The actual maximum | ||
6 | RAM size now depends on the physical CPU and host kernel, in | ||
7 | accelerated mode. In TCG mode, it depends on the VCPU | ||
8 | AA64MMFR0.PARANGE. | ||
9 | 5 | ||
10 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | 6 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
11 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | 7 | Message-id: 20240130152548.17855-1-philmd@linaro.org |
12 | Message-id: 20190304101339.25970-11-eric.auger@redhat.com | 8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | --- | 10 | --- |
15 | hw/arm/virt.c | 21 +-------------------- | 11 | hw/arm/xilinx_zynq.c | 2 ++ |
16 | 1 file changed, 1 insertion(+), 20 deletions(-) | 12 | 1 file changed, 2 insertions(+) |
17 | 13 | ||
18 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 14 | diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c |
19 | index XXXXXXX..XXXXXXX 100644 | 15 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/hw/arm/virt.c | 16 | --- a/hw/arm/xilinx_zynq.c |
21 | +++ b/hw/arm/virt.c | 17 | +++ b/hw/arm/xilinx_zynq.c |
22 | @@ -XXX,XX +XXX,XX @@ | 18 | @@ -XXX,XX +XXX,XX @@ static void zynq_init(MachineState *machine) |
23 | 19 | sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); | |
24 | #define PLATFORM_BUS_NUM_IRQS 64 | 20 | sysbus_connect_irq(busdev, 0, |
25 | 21 | qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); | |
26 | -/* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means | 22 | + sysbus_connect_irq(busdev, 1, |
27 | - * RAM can go up to the 256GB mark, leaving 256GB of the physical | 23 | + qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ)); |
28 | - * address space unallocated and free for future use between 256G and 512G. | 24 | |
29 | - * If we need to provide more RAM to VMs in the future then we need to: | 25 | for (n = 0; n < 64; n++) { |
30 | - * * allocate a second bank of RAM starting at 2TB and working up | 26 | pic[n] = qdev_get_gpio_in(dev, n); |
31 | - * * fix the DT and ACPI table generation code in QEMU to correctly | ||
32 | - * report two split lumps of RAM to the guest | ||
33 | - * * fix KVM in the host kernel to allow guests with >40 bit address spaces | ||
34 | - * (We don't want to fill all the way up to 512GB with RAM because | ||
35 | - * we might want it for non-RAM purposes later. Conversely it seems | ||
36 | - * reasonable to assume that anybody configuring a VM with a quarter | ||
37 | - * of a terabyte of RAM will be doing it on a host with more than a | ||
38 | - * terabyte of physical address space.) | ||
39 | - */ | ||
40 | +/* Legacy RAM limit in GB (< version 4.0) */ | ||
41 | #define LEGACY_RAMLIMIT_GB 255 | ||
42 | #define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) | ||
43 | |||
44 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | ||
45 | |||
46 | vms->smp_cpus = smp_cpus; | ||
47 | |||
48 | - if (machine->ram_size > vms->memmap[VIRT_MEM].size) { | ||
49 | - error_report("mach-virt: cannot model more than %dGB RAM", | ||
50 | - LEGACY_RAMLIMIT_GB); | ||
51 | - exit(1); | ||
52 | - } | ||
53 | - | ||
54 | if (vms->virt && kvm_enabled()) { | ||
55 | error_report("mach-virt: KVM does not support providing " | ||
56 | "Virtualization extensions to the guest CPU"); | ||
57 | -- | 27 | -- |
58 | 2.20.1 | 28 | 2.34.1 |
59 | 29 | ||
60 | 30 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Richard Henderson <richard.henderson@linaro.org> | ||
1 | 2 | ||
3 | The API does not generate an error for setting ASYNC | SYNC; that merely | ||
4 | constrains the selection vs the per-cpu default. For qemu linux-user, | ||
5 | choose SYNC as the default. | ||
6 | |||
7 | Cc: qemu-stable@nongnu.org | ||
8 | Reported-by: Gustavo Romero <gustavo.romero@linaro.org> | ||
9 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
10 | Tested-by: Gustavo Romero <gustavo.romero@linaro.org> | ||
11 | Message-id: 20240207025210.8837-2-richard.henderson@linaro.org | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | linux-user/aarch64/target_prctl.h | 29 +++++++++++++++++------------ | ||
15 | 1 file changed, 17 insertions(+), 12 deletions(-) | ||
16 | |||
17 | diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_prctl.h | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/linux-user/aarch64/target_prctl.h | ||
20 | +++ b/linux-user/aarch64/target_prctl.h | ||
21 | @@ -XXX,XX +XXX,XX @@ static abi_long do_prctl_set_tagged_addr_ctrl(CPUArchState *env, abi_long arg2) | ||
22 | env->tagged_addr_enable = arg2 & PR_TAGGED_ADDR_ENABLE; | ||
23 | |||
24 | if (cpu_isar_feature(aa64_mte, cpu)) { | ||
25 | - switch (arg2 & PR_MTE_TCF_MASK) { | ||
26 | - case PR_MTE_TCF_NONE: | ||
27 | - case PR_MTE_TCF_SYNC: | ||
28 | - case PR_MTE_TCF_ASYNC: | ||
29 | - break; | ||
30 | - default: | ||
31 | - return -EINVAL; | ||
32 | - } | ||
33 | - | ||
34 | /* | ||
35 | * Write PR_MTE_TCF to SCTLR_EL1[TCF0]. | ||
36 | - * Note that the syscall values are consistent with hw. | ||
37 | + * | ||
38 | + * The kernel has a per-cpu configuration for the sysadmin, | ||
39 | + * /sys/devices/system/cpu/cpu<N>/mte_tcf_preferred, | ||
40 | + * which qemu does not implement. | ||
41 | + * | ||
42 | + * Because there is no performance difference between the modes, and | ||
43 | + * because SYNC is most useful for debugging MTE errors, choose SYNC | ||
44 | + * as the preferred mode. With this preference, and the way the API | ||
45 | + * uses only two bits, there is no way for the program to select | ||
46 | + * ASYMM mode. | ||
47 | */ | ||
48 | - env->cp15.sctlr_el[1] = | ||
49 | - deposit64(env->cp15.sctlr_el[1], 38, 2, arg2 >> PR_MTE_TCF_SHIFT); | ||
50 | + unsigned tcf = 0; | ||
51 | + if (arg2 & PR_MTE_TCF_SYNC) { | ||
52 | + tcf = 1; | ||
53 | + } else if (arg2 & PR_MTE_TCF_ASYNC) { | ||
54 | + tcf = 2; | ||
55 | + } | ||
56 | + env->cp15.sctlr_el[1] = deposit64(env->cp15.sctlr_el[1], 38, 2, tcf); | ||
57 | |||
58 | /* | ||
59 | * Write PR_MTE_TAG to GCR_EL1[Exclude]. | ||
60 | -- | ||
61 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> | 3 | The field is encoded as [0-3], which is convenient for |
4 | indexing our array of function pointers, but the true | ||
5 | value is [1-4]. Adjust before calling do_mem_zpa. | ||
6 | |||
7 | Add an assert, and move the comment re passing ZT to | ||
8 | the helper back next to the relevant code. | ||
9 | |||
10 | Cc: qemu-stable@nongnu.org | ||
11 | Fixes: 206adacfb8d ("target/arm: Add mte helpers for sve scalar + int loads") | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 12 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 20190301200501.16533-9-richard.henderson@linaro.org | 13 | Tested-by: Gustavo Romero <gustavo.romero@linaro.org> |
14 | Message-id: 20240207025210.8837-3-richard.henderson@linaro.org | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 15 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | --- | 17 | --- |
9 | target/arm/cpu.h | 5 ++++ | 18 | target/arm/tcg/translate-sve.c | 16 ++++++++-------- |
10 | target/arm/cpu64.c | 2 +- | 19 | 1 file changed, 8 insertions(+), 8 deletions(-) |
11 | target/arm/translate-a64.c | 58 ++++++++++++++++++++++++++++++++++++++ | ||
12 | 3 files changed, 64 insertions(+), 1 deletion(-) | ||
13 | 20 | ||
14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 21 | diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c |
15 | index XXXXXXX..XXXXXXX 100644 | 22 | index XXXXXXX..XXXXXXX 100644 |
16 | --- a/target/arm/cpu.h | 23 | --- a/target/arm/tcg/translate-sve.c |
17 | +++ b/target/arm/cpu.h | 24 | +++ b/target/arm/tcg/translate-sve.c |
18 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) | 25 | @@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, |
19 | return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; | 26 | TCGv_ptr t_pg; |
27 | int desc = 0; | ||
28 | |||
29 | - /* | ||
30 | - * For e.g. LD4, there are not enough arguments to pass all 4 | ||
31 | - * registers as pointers, so encode the regno into the data field. | ||
32 | - * For consistency, do this even for LD1. | ||
33 | - */ | ||
34 | + assert(mte_n >= 1 && mte_n <= 4); | ||
35 | if (s->mte_active[0]) { | ||
36 | int msz = dtype_msz(dtype); | ||
37 | |||
38 | @@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, | ||
39 | addr = clean_data_tbi(s, addr); | ||
40 | } | ||
41 | |||
42 | + /* | ||
43 | + * For e.g. LD4, there are not enough arguments to pass all 4 | ||
44 | + * registers as pointers, so encode the regno into the data field. | ||
45 | + * For consistency, do this even for LD1. | ||
46 | + */ | ||
47 | desc = simd_desc(vsz, vsz, zt | desc); | ||
48 | t_pg = tcg_temp_new_ptr(); | ||
49 | |||
50 | @@ -XXX,XX +XXX,XX @@ static void do_ld_zpa(DisasContext *s, int zt, int pg, | ||
51 | * accessible via the instruction encoding. | ||
52 | */ | ||
53 | assert(fn != NULL); | ||
54 | - do_mem_zpa(s, zt, pg, addr, dtype, nreg, false, fn); | ||
55 | + do_mem_zpa(s, zt, pg, addr, dtype, nreg + 1, false, fn); | ||
20 | } | 56 | } |
21 | 57 | ||
22 | +static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id) | 58 | static bool trans_LD_zprr(DisasContext *s, arg_rprr_load *a) |
23 | +{ | 59 | @@ -XXX,XX +XXX,XX @@ static void do_st_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, |
24 | + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2; | 60 | if (nreg == 0) { |
25 | +} | 61 | /* ST1 */ |
26 | + | 62 | fn = fn_single[s->mte_active[0]][be][msz][esz]; |
27 | static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) | 63 | - nreg = 1; |
28 | { | 64 | } else { |
29 | return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; | 65 | /* ST2, ST3, ST4 -- msz == esz, enforced by encoding */ |
30 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | 66 | assert(msz == esz); |
31 | index XXXXXXX..XXXXXXX 100644 | 67 | fn = fn_multiple[s->mte_active[0]][be][nreg - 1][msz]; |
32 | --- a/target/arm/cpu64.c | ||
33 | +++ b/target/arm/cpu64.c | ||
34 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
35 | t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); | ||
36 | t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); | ||
37 | t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); | ||
38 | - t = FIELD_DP64(t, ID_AA64ISAR0, TS, 1); | ||
39 | + t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ | ||
40 | cpu->isar.id_aa64isar0 = t; | ||
41 | |||
42 | t = cpu->isar.id_aa64isar1; | ||
43 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
44 | index XXXXXXX..XXXXXXX 100644 | ||
45 | --- a/target/arm/translate-a64.c | ||
46 | +++ b/target/arm/translate-a64.c | ||
47 | @@ -XXX,XX +XXX,XX @@ static void handle_sync(DisasContext *s, uint32_t insn, | ||
48 | } | 68 | } |
69 | assert(fn != NULL); | ||
70 | - do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg, true, fn); | ||
71 | + do_mem_zpa(s, zt, pg, addr, msz_dtype(s, msz), nreg + 1, true, fn); | ||
49 | } | 72 | } |
50 | 73 | ||
51 | +static void gen_xaflag(void) | 74 | static bool trans_ST_zprr(DisasContext *s, arg_rprr_store *a) |
52 | +{ | ||
53 | + TCGv_i32 z = tcg_temp_new_i32(); | ||
54 | + | ||
55 | + tcg_gen_setcondi_i32(TCG_COND_EQ, z, cpu_ZF, 0); | ||
56 | + | ||
57 | + /* | ||
58 | + * (!C & !Z) << 31 | ||
59 | + * (!(C | Z)) << 31 | ||
60 | + * ~((C | Z) << 31) | ||
61 | + * ~-(C | Z) | ||
62 | + * (C | Z) - 1 | ||
63 | + */ | ||
64 | + tcg_gen_or_i32(cpu_NF, cpu_CF, z); | ||
65 | + tcg_gen_subi_i32(cpu_NF, cpu_NF, 1); | ||
66 | + | ||
67 | + /* !(Z & C) */ | ||
68 | + tcg_gen_and_i32(cpu_ZF, z, cpu_CF); | ||
69 | + tcg_gen_xori_i32(cpu_ZF, cpu_ZF, 1); | ||
70 | + | ||
71 | + /* (!C & Z) << 31 -> -(Z & ~C) */ | ||
72 | + tcg_gen_andc_i32(cpu_VF, z, cpu_CF); | ||
73 | + tcg_gen_neg_i32(cpu_VF, cpu_VF); | ||
74 | + | ||
75 | + /* C | Z */ | ||
76 | + tcg_gen_or_i32(cpu_CF, cpu_CF, z); | ||
77 | + | ||
78 | + tcg_temp_free_i32(z); | ||
79 | +} | ||
80 | + | ||
81 | +static void gen_axflag(void) | ||
82 | +{ | ||
83 | + tcg_gen_sari_i32(cpu_VF, cpu_VF, 31); /* V ? -1 : 0 */ | ||
84 | + tcg_gen_andc_i32(cpu_CF, cpu_CF, cpu_VF); /* C & !V */ | ||
85 | + | ||
86 | + /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */ | ||
87 | + tcg_gen_andc_i32(cpu_ZF, cpu_ZF, cpu_VF); | ||
88 | + | ||
89 | + tcg_gen_movi_i32(cpu_NF, 0); | ||
90 | + tcg_gen_movi_i32(cpu_VF, 0); | ||
91 | +} | ||
92 | + | ||
93 | /* MSR (immediate) - move immediate to processor state field */ | ||
94 | static void handle_msr_i(DisasContext *s, uint32_t insn, | ||
95 | unsigned int op1, unsigned int op2, unsigned int crm) | ||
96 | @@ -XXX,XX +XXX,XX @@ static void handle_msr_i(DisasContext *s, uint32_t insn, | ||
97 | s->base.is_jmp = DISAS_NEXT; | ||
98 | break; | ||
99 | |||
100 | + case 0x01: /* XAFlag */ | ||
101 | + if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) { | ||
102 | + goto do_unallocated; | ||
103 | + } | ||
104 | + gen_xaflag(); | ||
105 | + s->base.is_jmp = DISAS_NEXT; | ||
106 | + break; | ||
107 | + | ||
108 | + case 0x02: /* AXFlag */ | ||
109 | + if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) { | ||
110 | + goto do_unallocated; | ||
111 | + } | ||
112 | + gen_axflag(); | ||
113 | + s->base.is_jmp = DISAS_NEXT; | ||
114 | + break; | ||
115 | + | ||
116 | case 0x05: /* SPSel */ | ||
117 | if (s->current_el == 0) { | ||
118 | goto do_unallocated; | ||
119 | -- | 75 | -- |
120 | 2.20.1 | 76 | 2.34.1 |
121 | |||
122 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | The EL0+UMA check is unique to DAIF. While SPSel had avoided the | 3 | When we added SVE_MTEDESC_SHIFT, we effectively limited the |
4 | check by nature of already checking EL >= 1, the other post v8.0 | 4 | maximum size of MTEDESC. Adjust SIZEM1 to consume the remaining |
5 | extensions to MSR (imm) allow EL0 and do not require UMA. Avoid | 5 | bits (32 - 10 - 5 - 12 == 5). Assert that the data to be stored |
6 | the unconditional write to pc and use raise_exception_ra to unwind. | 6 | fits within the field (expecting 8 * 4 - 1 == 31, exact fit). |
7 | 7 | ||
8 | Cc: qemu-stable@nongnu.org | ||
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 10 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
9 | Message-id: 20190301200501.16533-5-richard.henderson@linaro.org | 11 | Tested-by: Gustavo Romero <gustavo.romero@linaro.org> |
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Message-id: 20240207025210.8837-4-richard.henderson@linaro.org |
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 14 | --- |
13 | target/arm/helper-a64.h | 3 +++ | 15 | target/arm/internals.h | 2 +- |
14 | target/arm/helper.h | 1 - | 16 | target/arm/tcg/translate-sve.c | 7 ++++--- |
15 | target/arm/internals.h | 15 ++++++++++++++ | 17 | 2 files changed, 5 insertions(+), 4 deletions(-) |
16 | target/arm/helper-a64.c | 30 +++++++++++++++++++++++++++ | ||
17 | target/arm/op_helper.c | 42 -------------------------------------- | ||
18 | target/arm/translate-a64.c | 41 ++++++++++++++++++++++--------------- | ||
19 | 6 files changed, 73 insertions(+), 59 deletions(-) | ||
20 | 18 | ||
21 | diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h | ||
22 | index XXXXXXX..XXXXXXX 100644 | ||
23 | --- a/target/arm/helper-a64.h | ||
24 | +++ b/target/arm/helper-a64.h | ||
25 | @@ -XXX,XX +XXX,XX @@ | ||
26 | DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64) | ||
27 | DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64) | ||
28 | DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64) | ||
29 | +DEF_HELPER_2(msr_i_spsel, void, env, i32) | ||
30 | +DEF_HELPER_2(msr_i_daifset, void, env, i32) | ||
31 | +DEF_HELPER_2(msr_i_daifclear, void, env, i32) | ||
32 | DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr) | ||
33 | DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr) | ||
34 | DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr) | ||
35 | diff --git a/target/arm/helper.h b/target/arm/helper.h | ||
36 | index XXXXXXX..XXXXXXX 100644 | ||
37 | --- a/target/arm/helper.h | ||
38 | +++ b/target/arm/helper.h | ||
39 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(get_cp_reg, i32, env, ptr) | ||
40 | DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64) | ||
41 | DEF_HELPER_2(get_cp_reg64, i64, env, ptr) | ||
42 | |||
43 | -DEF_HELPER_3(msr_i_pstate, void, env, i32, i32) | ||
44 | DEF_HELPER_1(clear_pstate_ss, void, env) | ||
45 | |||
46 | DEF_HELPER_2(get_r13_banked, i32, env, i32) | ||
47 | diff --git a/target/arm/internals.h b/target/arm/internals.h | 19 | diff --git a/target/arm/internals.h b/target/arm/internals.h |
48 | index XXXXXXX..XXXXXXX 100644 | 20 | index XXXXXXX..XXXXXXX 100644 |
49 | --- a/target/arm/internals.h | 21 | --- a/target/arm/internals.h |
50 | +++ b/target/arm/internals.h | 22 | +++ b/target/arm/internals.h |
51 | @@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, | 23 | @@ -XXX,XX +XXX,XX @@ FIELD(MTEDESC, TBI, 4, 2) |
52 | ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, | 24 | FIELD(MTEDESC, TCMA, 6, 2) |
53 | ARMMMUIdx mmu_idx, bool data); | 25 | FIELD(MTEDESC, WRITE, 8, 1) |
54 | 26 | FIELD(MTEDESC, ALIGN, 9, 3) | |
55 | +static inline int exception_target_el(CPUARMState *env) | 27 | -FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - 12) /* size - 1 */ |
56 | +{ | 28 | +FIELD(MTEDESC, SIZEM1, 12, SIMD_DATA_BITS - SVE_MTEDESC_SHIFT - 12) /* size - 1 */ |
57 | + int target_el = MAX(1, arm_current_el(env)); | 29 | |
58 | + | 30 | bool mte_probe(CPUARMState *env, uint32_t desc, uint64_t ptr); |
59 | + /* | 31 | uint64_t mte_check(CPUARMState *env, uint32_t desc, uint64_t ptr, uintptr_t ra); |
60 | + * No such thing as secure EL1 if EL3 is aarch32, | 32 | diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c |
61 | + * so update the target EL to EL3 in this case. | ||
62 | + */ | ||
63 | + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) { | ||
64 | + target_el = 3; | ||
65 | + } | ||
66 | + | ||
67 | + return target_el; | ||
68 | +} | ||
69 | + | ||
70 | #endif | ||
71 | diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c | ||
72 | index XXXXXXX..XXXXXXX 100644 | 33 | index XXXXXXX..XXXXXXX 100644 |
73 | --- a/target/arm/helper-a64.c | 34 | --- a/target/arm/tcg/translate-sve.c |
74 | +++ b/target/arm/helper-a64.c | 35 | +++ b/target/arm/tcg/translate-sve.c |
75 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(rbit64)(uint64_t x) | 36 | @@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, |
76 | return revbit64(x); | 37 | { |
77 | } | 38 | unsigned vsz = vec_full_reg_size(s); |
78 | 39 | TCGv_ptr t_pg; | |
79 | +void HELPER(msr_i_spsel)(CPUARMState *env, uint32_t imm) | 40 | + uint32_t sizem1; |
80 | +{ | 41 | int desc = 0; |
81 | + update_spsel(env, imm); | 42 | |
82 | +} | 43 | assert(mte_n >= 1 && mte_n <= 4); |
83 | + | 44 | + sizem1 = (mte_n << dtype_msz(dtype)) - 1; |
84 | +static void daif_check(CPUARMState *env, uint32_t op, | 45 | + assert(sizem1 <= R_MTEDESC_SIZEM1_MASK >> R_MTEDESC_SIZEM1_SHIFT); |
85 | + uint32_t imm, uintptr_t ra) | 46 | if (s->mte_active[0]) { |
86 | +{ | 47 | - int msz = dtype_msz(dtype); |
87 | + /* DAIF update to PSTATE. This is OK from EL0 only if UMA is set. */ | ||
88 | + if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) { | ||
89 | + raise_exception_ra(env, EXCP_UDEF, | ||
90 | + syn_aa64_sysregtrap(0, extract32(op, 0, 3), | ||
91 | + extract32(op, 3, 3), 4, | ||
92 | + imm, 0x1f, 0), | ||
93 | + exception_target_el(env), ra); | ||
94 | + } | ||
95 | +} | ||
96 | + | ||
97 | +void HELPER(msr_i_daifset)(CPUARMState *env, uint32_t imm) | ||
98 | +{ | ||
99 | + daif_check(env, 0x1e, imm, GETPC()); | ||
100 | + env->daif |= (imm << 6) & PSTATE_DAIF; | ||
101 | +} | ||
102 | + | ||
103 | +void HELPER(msr_i_daifclear)(CPUARMState *env, uint32_t imm) | ||
104 | +{ | ||
105 | + daif_check(env, 0x1f, imm, GETPC()); | ||
106 | + env->daif &= ~((imm << 6) & PSTATE_DAIF); | ||
107 | +} | ||
108 | + | ||
109 | /* Convert a softfloat float_relation_ (as returned by | ||
110 | * the float*_compare functions) to the correct ARM | ||
111 | * NZCV flag state. | ||
112 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
113 | index XXXXXXX..XXXXXXX 100644 | ||
114 | --- a/target/arm/op_helper.c | ||
115 | +++ b/target/arm/op_helper.c | ||
116 | @@ -XXX,XX +XXX,XX @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, | ||
117 | cpu_loop_exit_restore(cs, ra); | ||
118 | } | ||
119 | |||
120 | -static int exception_target_el(CPUARMState *env) | ||
121 | -{ | ||
122 | - int target_el = MAX(1, arm_current_el(env)); | ||
123 | - | 48 | - |
124 | - /* No such thing as secure EL1 if EL3 is aarch32, so update the target EL | 49 | desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); |
125 | - * to EL3 in this case. | 50 | desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); |
126 | - */ | 51 | desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); |
127 | - if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) { | 52 | desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); |
128 | - target_el = 3; | 53 | - desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (mte_n << msz) - 1); |
129 | - } | 54 | + desc = FIELD_DP32(desc, MTEDESC, SIZEM1, sizem1); |
130 | - | 55 | desc <<= SVE_MTEDESC_SHIFT; |
131 | - return target_el; | 56 | } else { |
132 | -} | 57 | addr = clean_data_tbi(s, addr); |
133 | - | ||
134 | uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn, | ||
135 | uint32_t maxindex) | ||
136 | { | ||
137 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip) | ||
138 | return res; | ||
139 | } | ||
140 | |||
141 | -void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm) | ||
142 | -{ | ||
143 | - /* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set. | ||
144 | - * Note that SPSel is never OK from EL0; we rely on handle_msr_i() | ||
145 | - * to catch that case at translate time. | ||
146 | - */ | ||
147 | - if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) { | ||
148 | - uint32_t syndrome = syn_aa64_sysregtrap(0, extract32(op, 0, 3), | ||
149 | - extract32(op, 3, 3), 4, | ||
150 | - imm, 0x1f, 0); | ||
151 | - raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env)); | ||
152 | - } | ||
153 | - | ||
154 | - switch (op) { | ||
155 | - case 0x05: /* SPSel */ | ||
156 | - update_spsel(env, imm); | ||
157 | - break; | ||
158 | - case 0x1e: /* DAIFSet */ | ||
159 | - env->daif |= (imm << 6) & PSTATE_DAIF; | ||
160 | - break; | ||
161 | - case 0x1f: /* DAIFClear */ | ||
162 | - env->daif &= ~((imm << 6) & PSTATE_DAIF); | ||
163 | - break; | ||
164 | - default: | ||
165 | - g_assert_not_reached(); | ||
166 | - } | ||
167 | -} | ||
168 | - | ||
169 | void HELPER(clear_pstate_ss)(CPUARMState *env) | ||
170 | { | ||
171 | env->pstate &= ~PSTATE_SS; | ||
172 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
173 | index XXXXXXX..XXXXXXX 100644 | ||
174 | --- a/target/arm/translate-a64.c | ||
175 | +++ b/target/arm/translate-a64.c | ||
176 | @@ -XXX,XX +XXX,XX @@ static void handle_sync(DisasContext *s, uint32_t insn, | ||
177 | static void handle_msr_i(DisasContext *s, uint32_t insn, | ||
178 | unsigned int op1, unsigned int op2, unsigned int crm) | ||
179 | { | ||
180 | + TCGv_i32 t1; | ||
181 | int op = op1 << 3 | op2; | ||
182 | + | ||
183 | + /* End the TB by default, chaining is ok. */ | ||
184 | + s->base.is_jmp = DISAS_TOO_MANY; | ||
185 | + | ||
186 | switch (op) { | ||
187 | case 0x05: /* SPSel */ | ||
188 | if (s->current_el == 0) { | ||
189 | - unallocated_encoding(s); | ||
190 | - return; | ||
191 | + goto do_unallocated; | ||
192 | } | ||
193 | - /* fall through */ | ||
194 | - case 0x1e: /* DAIFSet */ | ||
195 | - case 0x1f: /* DAIFClear */ | ||
196 | - { | ||
197 | - TCGv_i32 tcg_imm = tcg_const_i32(crm); | ||
198 | - TCGv_i32 tcg_op = tcg_const_i32(op); | ||
199 | - gen_a64_set_pc_im(s->pc - 4); | ||
200 | - gen_helper_msr_i_pstate(cpu_env, tcg_op, tcg_imm); | ||
201 | - tcg_temp_free_i32(tcg_imm); | ||
202 | - tcg_temp_free_i32(tcg_op); | ||
203 | - /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */ | ||
204 | - gen_a64_set_pc_im(s->pc); | ||
205 | - s->base.is_jmp = (op == 0x1f ? DISAS_EXIT : DISAS_JUMP); | ||
206 | + t1 = tcg_const_i32(crm & PSTATE_SP); | ||
207 | + gen_helper_msr_i_spsel(cpu_env, t1); | ||
208 | + tcg_temp_free_i32(t1); | ||
209 | break; | ||
210 | - } | ||
211 | + | ||
212 | + case 0x1e: /* DAIFSet */ | ||
213 | + t1 = tcg_const_i32(crm); | ||
214 | + gen_helper_msr_i_daifset(cpu_env, t1); | ||
215 | + tcg_temp_free_i32(t1); | ||
216 | + break; | ||
217 | + | ||
218 | + case 0x1f: /* DAIFClear */ | ||
219 | + t1 = tcg_const_i32(crm); | ||
220 | + gen_helper_msr_i_daifclear(cpu_env, t1); | ||
221 | + tcg_temp_free_i32(t1); | ||
222 | + /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */ | ||
223 | + s->base.is_jmp = DISAS_UPDATE; | ||
224 | + break; | ||
225 | + | ||
226 | default: | ||
227 | + do_unallocated: | ||
228 | unallocated_encoding(s); | ||
229 | return; | ||
230 | } | ||
231 | -- | 58 | -- |
232 | 2.20.1 | 59 | 2.34.1 |
233 | |||
234 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Share code that creates mtedesc and embeds within simd_desc. | ||
4 | |||
5 | Cc: qemu-stable@nongnu.org | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
4 | Message-id: 20190301200501.16533-3-richard.henderson@linaro.org | 8 | Tested-by: Gustavo Romero <gustavo.romero@linaro.org> |
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Message-id: 20240207025210.8837-5-richard.henderson@linaro.org |
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | --- | 11 | --- |
8 | target/arm/cpu.h | 10 ++++++++++ | 12 | target/arm/tcg/translate-a64.h | 2 ++ |
9 | linux-user/elfload.c | 1 + | 13 | target/arm/tcg/translate-sme.c | 15 +++-------- |
10 | target/arm/cpu.c | 1 + | 14 | target/arm/tcg/translate-sve.c | 47 ++++++++++++++++++---------------- |
11 | target/arm/cpu64.c | 2 ++ | 15 | 3 files changed, 31 insertions(+), 33 deletions(-) |
12 | target/arm/translate-a64.c | 14 ++++++++++++++ | ||
13 | target/arm/translate.c | 22 ++++++++++++++++++++++ | ||
14 | 6 files changed, 50 insertions(+) | ||
15 | 16 | ||
16 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 17 | diff --git a/target/arm/tcg/translate-a64.h b/target/arm/tcg/translate-a64.h |
17 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/cpu.h | 19 | --- a/target/arm/tcg/translate-a64.h |
19 | +++ b/target/arm/cpu.h | 20 | +++ b/target/arm/tcg/translate-a64.h |
20 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) | 21 | @@ -XXX,XX +XXX,XX @@ bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, |
21 | return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; | 22 | bool sve_access_check(DisasContext *s); |
22 | } | 23 | bool sme_enabled_check(DisasContext *s); |
23 | 24 | bool sme_enabled_check_with_svcr(DisasContext *s, unsigned); | |
24 | +static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) | 25 | +uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs, |
25 | +{ | 26 | + uint32_t msz, bool is_write, uint32_t data); |
26 | + return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; | 27 | |
28 | /* This function corresponds to CheckStreamingSVEEnabled. */ | ||
29 | static inline bool sme_sm_enabled_check(DisasContext *s) | ||
30 | diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c | ||
31 | index XXXXXXX..XXXXXXX 100644 | ||
32 | --- a/target/arm/tcg/translate-sme.c | ||
33 | +++ b/target/arm/tcg/translate-sme.c | ||
34 | @@ -XXX,XX +XXX,XX @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a) | ||
35 | |||
36 | TCGv_ptr t_za, t_pg; | ||
37 | TCGv_i64 addr; | ||
38 | - int svl, desc = 0; | ||
39 | + uint32_t desc; | ||
40 | bool be = s->be_data == MO_BE; | ||
41 | bool mte = s->mte_active[0]; | ||
42 | |||
43 | @@ -XXX,XX +XXX,XX @@ static bool trans_LDST1(DisasContext *s, arg_LDST1 *a) | ||
44 | tcg_gen_shli_i64(addr, cpu_reg(s, a->rm), a->esz); | ||
45 | tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, a->rn)); | ||
46 | |||
47 | - if (mte) { | ||
48 | - desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); | ||
49 | - desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); | ||
50 | - desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); | ||
51 | - desc = FIELD_DP32(desc, MTEDESC, WRITE, a->st); | ||
52 | - desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << a->esz) - 1); | ||
53 | - desc <<= SVE_MTEDESC_SHIFT; | ||
54 | - } else { | ||
55 | + if (!mte) { | ||
56 | addr = clean_data_tbi(s, addr); | ||
57 | } | ||
58 | - svl = streaming_vec_reg_size(s); | ||
59 | - desc = simd_desc(svl, svl, desc); | ||
60 | + | ||
61 | + desc = make_svemte_desc(s, streaming_vec_reg_size(s), 1, a->esz, a->st, 0); | ||
62 | |||
63 | fns[a->esz][be][a->v][mte][a->st](tcg_env, t_za, t_pg, addr, | ||
64 | tcg_constant_i32(desc)); | ||
65 | diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c | ||
66 | index XXXXXXX..XXXXXXX 100644 | ||
67 | --- a/target/arm/tcg/translate-sve.c | ||
68 | +++ b/target/arm/tcg/translate-sve.c | ||
69 | @@ -XXX,XX +XXX,XX @@ static const uint8_t dtype_esz[16] = { | ||
70 | 3, 2, 1, 3 | ||
71 | }; | ||
72 | |||
73 | -static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, | ||
74 | - int dtype, uint32_t mte_n, bool is_write, | ||
75 | - gen_helper_gvec_mem *fn) | ||
76 | +uint32_t make_svemte_desc(DisasContext *s, unsigned vsz, uint32_t nregs, | ||
77 | + uint32_t msz, bool is_write, uint32_t data) | ||
78 | { | ||
79 | - unsigned vsz = vec_full_reg_size(s); | ||
80 | - TCGv_ptr t_pg; | ||
81 | uint32_t sizem1; | ||
82 | - int desc = 0; | ||
83 | + uint32_t desc = 0; | ||
84 | |||
85 | - assert(mte_n >= 1 && mte_n <= 4); | ||
86 | - sizem1 = (mte_n << dtype_msz(dtype)) - 1; | ||
87 | + /* Assert all of the data fits, with or without MTE enabled. */ | ||
88 | + assert(nregs >= 1 && nregs <= 4); | ||
89 | + sizem1 = (nregs << msz) - 1; | ||
90 | assert(sizem1 <= R_MTEDESC_SIZEM1_MASK >> R_MTEDESC_SIZEM1_SHIFT); | ||
91 | + assert(data < 1u << SVE_MTEDESC_SHIFT); | ||
92 | + | ||
93 | if (s->mte_active[0]) { | ||
94 | desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); | ||
95 | desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); | ||
96 | @@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, | ||
97 | desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); | ||
98 | desc = FIELD_DP32(desc, MTEDESC, SIZEM1, sizem1); | ||
99 | desc <<= SVE_MTEDESC_SHIFT; | ||
100 | - } else { | ||
101 | + } | ||
102 | + return simd_desc(vsz, vsz, desc | data); | ||
27 | +} | 103 | +} |
28 | + | 104 | + |
29 | static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) | 105 | +static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, |
106 | + int dtype, uint32_t nregs, bool is_write, | ||
107 | + gen_helper_gvec_mem *fn) | ||
108 | +{ | ||
109 | + TCGv_ptr t_pg; | ||
110 | + uint32_t desc; | ||
111 | + | ||
112 | + if (!s->mte_active[0]) { | ||
113 | addr = clean_data_tbi(s, addr); | ||
114 | } | ||
115 | |||
116 | @@ -XXX,XX +XXX,XX @@ static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, | ||
117 | * registers as pointers, so encode the regno into the data field. | ||
118 | * For consistency, do this even for LD1. | ||
119 | */ | ||
120 | - desc = simd_desc(vsz, vsz, zt | desc); | ||
121 | + desc = make_svemte_desc(s, vec_full_reg_size(s), nregs, | ||
122 | + dtype_msz(dtype), is_write, zt); | ||
123 | t_pg = tcg_temp_new_ptr(); | ||
124 | |||
125 | tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg)); | ||
126 | @@ -XXX,XX +XXX,XX @@ static void do_mem_zpz(DisasContext *s, int zt, int pg, int zm, | ||
127 | int scale, TCGv_i64 scalar, int msz, bool is_write, | ||
128 | gen_helper_gvec_mem_scatter *fn) | ||
30 | { | 129 | { |
31 | /* | 130 | - unsigned vsz = vec_full_reg_size(s); |
32 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id) | 131 | TCGv_ptr t_zm = tcg_temp_new_ptr(); |
33 | FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0; | 132 | TCGv_ptr t_pg = tcg_temp_new_ptr(); |
133 | TCGv_ptr t_zt = tcg_temp_new_ptr(); | ||
134 | - int desc = 0; | ||
135 | - | ||
136 | - if (s->mte_active[0]) { | ||
137 | - desc = FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); | ||
138 | - desc = FIELD_DP32(desc, MTEDESC, TBI, s->tbid); | ||
139 | - desc = FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); | ||
140 | - desc = FIELD_DP32(desc, MTEDESC, WRITE, is_write); | ||
141 | - desc = FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << msz) - 1); | ||
142 | - desc <<= SVE_MTEDESC_SHIFT; | ||
143 | - } | ||
144 | - desc = simd_desc(vsz, vsz, desc | scale); | ||
145 | + uint32_t desc; | ||
146 | |||
147 | tcg_gen_addi_ptr(t_pg, tcg_env, pred_full_reg_offset(s, pg)); | ||
148 | tcg_gen_addi_ptr(t_zm, tcg_env, vec_full_reg_offset(s, zm)); | ||
149 | tcg_gen_addi_ptr(t_zt, tcg_env, vec_full_reg_offset(s, zt)); | ||
150 | + | ||
151 | + desc = make_svemte_desc(s, vec_full_reg_size(s), 1, msz, is_write, scale); | ||
152 | fn(tcg_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc)); | ||
34 | } | 153 | } |
35 | 154 | ||
36 | +static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) | ||
37 | +{ | ||
38 | + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; | ||
39 | +} | ||
40 | + | ||
41 | static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) | ||
42 | { | ||
43 | /* We always set the AdvSIMD and FP fields identically wrt FP16. */ | ||
44 | diff --git a/linux-user/elfload.c b/linux-user/elfload.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/linux-user/elfload.c | ||
47 | +++ b/linux-user/elfload.c | ||
48 | @@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void) | ||
49 | GET_FEATURE_ID(aa64_pauth, ARM_HWCAP_A64_PACA | ARM_HWCAP_A64_PACG); | ||
50 | GET_FEATURE_ID(aa64_fhm, ARM_HWCAP_A64_ASIMDFHM); | ||
51 | GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT); | ||
52 | + GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB); | ||
53 | |||
54 | #undef GET_FEATURE_ID | ||
55 | |||
56 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
57 | index XXXXXXX..XXXXXXX 100644 | ||
58 | --- a/target/arm/cpu.c | ||
59 | +++ b/target/arm/cpu.c | ||
60 | @@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj) | ||
61 | t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1); | ||
62 | t = FIELD_DP32(t, ID_ISAR6, DP, 1); | ||
63 | t = FIELD_DP32(t, ID_ISAR6, FHM, 1); | ||
64 | + t = FIELD_DP32(t, ID_ISAR6, SB, 1); | ||
65 | cpu->isar.id_isar6 = t; | ||
66 | |||
67 | t = cpu->id_mmfr4; | ||
68 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
69 | index XXXXXXX..XXXXXXX 100644 | ||
70 | --- a/target/arm/cpu64.c | ||
71 | +++ b/target/arm/cpu64.c | ||
72 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
73 | t = FIELD_DP64(t, ID_AA64ISAR1, API, 0); | ||
74 | t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1); | ||
75 | t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0); | ||
76 | + t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); | ||
77 | cpu->isar.id_aa64isar1 = t; | ||
78 | |||
79 | t = cpu->isar.id_aa64pfr0; | ||
80 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
81 | u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1); | ||
82 | u = FIELD_DP32(u, ID_ISAR6, DP, 1); | ||
83 | u = FIELD_DP32(u, ID_ISAR6, FHM, 1); | ||
84 | + u = FIELD_DP32(u, ID_ISAR6, SB, 1); | ||
85 | cpu->isar.id_isar6 = u; | ||
86 | |||
87 | /* | ||
88 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
89 | index XXXXXXX..XXXXXXX 100644 | ||
90 | --- a/target/arm/translate-a64.c | ||
91 | +++ b/target/arm/translate-a64.c | ||
92 | @@ -XXX,XX +XXX,XX @@ static void handle_sync(DisasContext *s, uint32_t insn, | ||
93 | reset_btype(s); | ||
94 | gen_goto_tb(s, 0, s->pc); | ||
95 | return; | ||
96 | + | ||
97 | + case 7: /* SB */ | ||
98 | + if (crm != 0 || !dc_isar_feature(aa64_sb, s)) { | ||
99 | + goto do_unallocated; | ||
100 | + } | ||
101 | + /* | ||
102 | + * TODO: There is no speculation barrier opcode for TCG; | ||
103 | + * MB and end the TB instead. | ||
104 | + */ | ||
105 | + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); | ||
106 | + gen_goto_tb(s, 0, s->pc); | ||
107 | + return; | ||
108 | + | ||
109 | default: | ||
110 | + do_unallocated: | ||
111 | unallocated_encoding(s); | ||
112 | return; | ||
113 | } | ||
114 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
115 | index XXXXXXX..XXXXXXX 100644 | ||
116 | --- a/target/arm/translate.c | ||
117 | +++ b/target/arm/translate.c | ||
118 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | ||
119 | */ | ||
120 | gen_goto_tb(s, 0, s->pc & ~1); | ||
121 | return; | ||
122 | + case 7: /* sb */ | ||
123 | + if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) { | ||
124 | + goto illegal_op; | ||
125 | + } | ||
126 | + /* | ||
127 | + * TODO: There is no speculation barrier opcode | ||
128 | + * for TCG; MB and end the TB instead. | ||
129 | + */ | ||
130 | + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); | ||
131 | + gen_goto_tb(s, 0, s->pc & ~1); | ||
132 | + return; | ||
133 | default: | ||
134 | goto illegal_op; | ||
135 | } | ||
136 | @@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn) | ||
137 | */ | ||
138 | gen_goto_tb(s, 0, s->pc & ~1); | ||
139 | break; | ||
140 | + case 7: /* sb */ | ||
141 | + if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) { | ||
142 | + goto illegal_op; | ||
143 | + } | ||
144 | + /* | ||
145 | + * TODO: There is no speculation barrier opcode | ||
146 | + * for TCG; MB and end the TB instead. | ||
147 | + */ | ||
148 | + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); | ||
149 | + gen_goto_tb(s, 0, s->pc & ~1); | ||
150 | + break; | ||
151 | default: | ||
152 | goto illegal_op; | ||
153 | } | ||
154 | -- | 155 | -- |
155 | 2.20.1 | 156 | 2.34.1 |
156 | |||
157 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> | 3 | These functions "use the standard load helpers", but |
4 | fail to clean_data_tbi or populate mtedesc. | ||
5 | |||
6 | Cc: qemu-stable@nongnu.org | ||
7 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
5 | Message-id: 20190301200501.16533-8-richard.henderson@linaro.org | 9 | Tested-by: Gustavo Romero <gustavo.romero@linaro.org> |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Message-id: 20240207025210.8837-6-richard.henderson@linaro.org |
7 | [PMM: fixed up block comment style] | ||
8 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
9 | --- | 12 | --- |
10 | target/arm/cpu.h | 5 ++ | 13 | target/arm/tcg/translate-sve.c | 15 +++++++++++++-- |
11 | linux-user/elfload.c | 1 + | 14 | 1 file changed, 13 insertions(+), 2 deletions(-) |
12 | target/arm/cpu64.c | 1 + | ||
13 | target/arm/translate-a64.c | 99 +++++++++++++++++++++++++++++++++++++- | ||
14 | 4 files changed, 105 insertions(+), 1 deletion(-) | ||
15 | 15 | ||
16 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 16 | diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c |
17 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/cpu.h | 18 | --- a/target/arm/tcg/translate-sve.c |
19 | +++ b/target/arm/cpu.h | 19 | +++ b/target/arm/tcg/translate-sve.c |
20 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) | 20 | @@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype) |
21 | return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; | 21 | unsigned vsz = vec_full_reg_size(s); |
22 | } | 22 | TCGv_ptr t_pg; |
23 | 23 | int poff; | |
24 | +static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id) | 24 | + uint32_t desc; |
25 | +{ | 25 | |
26 | + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0; | 26 | /* Load the first quadword using the normal predicated load helpers. */ |
27 | +} | 27 | + if (!s->mte_active[0]) { |
28 | + | 28 | + addr = clean_data_tbi(s, addr); |
29 | static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id) | ||
30 | { | ||
31 | return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0; | ||
32 | diff --git a/linux-user/elfload.c b/linux-user/elfload.c | ||
33 | index XXXXXXX..XXXXXXX 100644 | ||
34 | --- a/linux-user/elfload.c | ||
35 | +++ b/linux-user/elfload.c | ||
36 | @@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void) | ||
37 | GET_FEATURE_ID(aa64_fhm, ARM_HWCAP_A64_ASIMDFHM); | ||
38 | GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT); | ||
39 | GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB); | ||
40 | + GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM); | ||
41 | |||
42 | #undef GET_FEATURE_ID | ||
43 | |||
44 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/target/arm/cpu64.c | ||
47 | +++ b/target/arm/cpu64.c | ||
48 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
49 | t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); | ||
50 | t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); | ||
51 | t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); | ||
52 | + t = FIELD_DP64(t, ID_AA64ISAR0, TS, 1); | ||
53 | cpu->isar.id_aa64isar0 = t; | ||
54 | |||
55 | t = cpu->isar.id_aa64isar1; | ||
56 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
57 | index XXXXXXX..XXXXXXX 100644 | ||
58 | --- a/target/arm/translate-a64.c | ||
59 | +++ b/target/arm/translate-a64.c | ||
60 | @@ -XXX,XX +XXX,XX @@ static void handle_msr_i(DisasContext *s, uint32_t insn, | ||
61 | s->base.is_jmp = DISAS_TOO_MANY; | ||
62 | |||
63 | switch (op) { | ||
64 | + case 0x00: /* CFINV */ | ||
65 | + if (crm != 0 || !dc_isar_feature(aa64_condm_4, s)) { | ||
66 | + goto do_unallocated; | ||
67 | + } | ||
68 | + tcg_gen_xori_i32(cpu_CF, cpu_CF, 1); | ||
69 | + s->base.is_jmp = DISAS_NEXT; | ||
70 | + break; | ||
71 | + | ||
72 | case 0x05: /* SPSel */ | ||
73 | if (s->current_el == 0) { | ||
74 | goto do_unallocated; | ||
75 | @@ -XXX,XX +XXX,XX @@ static void gen_get_nzcv(TCGv_i64 tcg_rt) | ||
76 | } | ||
77 | |||
78 | static void gen_set_nzcv(TCGv_i64 tcg_rt) | ||
79 | - | ||
80 | { | ||
81 | TCGv_i32 nzcv = tcg_temp_new_i32(); | ||
82 | |||
83 | @@ -XXX,XX +XXX,XX @@ static void disas_adc_sbc(DisasContext *s, uint32_t insn) | ||
84 | } | ||
85 | } | ||
86 | |||
87 | +/* | ||
88 | + * Rotate right into flags | ||
89 | + * 31 30 29 21 15 10 5 4 0 | ||
90 | + * +--+--+--+-----------------+--------+-----------+------+--+------+ | ||
91 | + * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask | | ||
92 | + * +--+--+--+-----------------+--------+-----------+------+--+------+ | ||
93 | + */ | ||
94 | +static void disas_rotate_right_into_flags(DisasContext *s, uint32_t insn) | ||
95 | +{ | ||
96 | + int mask = extract32(insn, 0, 4); | ||
97 | + int o2 = extract32(insn, 4, 1); | ||
98 | + int rn = extract32(insn, 5, 5); | ||
99 | + int imm6 = extract32(insn, 15, 6); | ||
100 | + int sf_op_s = extract32(insn, 29, 3); | ||
101 | + TCGv_i64 tcg_rn; | ||
102 | + TCGv_i32 nzcv; | ||
103 | + | ||
104 | + if (sf_op_s != 5 || o2 != 0 || !dc_isar_feature(aa64_condm_4, s)) { | ||
105 | + unallocated_encoding(s); | ||
106 | + return; | ||
107 | + } | 29 | + } |
108 | + | 30 | + |
109 | + tcg_rn = read_cpu_reg(s, rn, 1); | 31 | poff = pred_full_reg_offset(s, pg); |
110 | + tcg_gen_rotri_i64(tcg_rn, tcg_rn, imm6); | 32 | if (vsz > 16) { |
111 | + | 33 | /* |
112 | + nzcv = tcg_temp_new_i32(); | 34 | @@ -XXX,XX +XXX,XX @@ static void do_ldrq(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype) |
113 | + tcg_gen_extrl_i64_i32(nzcv, tcg_rn); | 35 | |
114 | + | 36 | gen_helper_gvec_mem *fn |
115 | + if (mask & 8) { /* N */ | 37 | = ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0]; |
116 | + tcg_gen_shli_i32(cpu_NF, nzcv, 31 - 3); | 38 | - fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(16, 16, zt))); |
39 | + desc = make_svemte_desc(s, 16, 1, dtype_msz(dtype), false, zt); | ||
40 | + fn(tcg_env, t_pg, addr, tcg_constant_i32(desc)); | ||
41 | |||
42 | /* Replicate that first quadword. */ | ||
43 | if (vsz > 16) { | ||
44 | @@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype) | ||
45 | unsigned vsz_r32; | ||
46 | TCGv_ptr t_pg; | ||
47 | int poff, doff; | ||
48 | + uint32_t desc; | ||
49 | |||
50 | if (vsz < 32) { | ||
51 | /* | ||
52 | @@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype) | ||
53 | } | ||
54 | |||
55 | /* Load the first octaword using the normal predicated load helpers. */ | ||
56 | + if (!s->mte_active[0]) { | ||
57 | + addr = clean_data_tbi(s, addr); | ||
117 | + } | 58 | + } |
118 | + if (mask & 4) { /* Z */ | 59 | |
119 | + tcg_gen_not_i32(cpu_ZF, nzcv); | 60 | poff = pred_full_reg_offset(s, pg); |
120 | + tcg_gen_andi_i32(cpu_ZF, cpu_ZF, 4); | 61 | if (vsz > 32) { |
121 | + } | 62 | @@ -XXX,XX +XXX,XX @@ static void do_ldro(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype) |
122 | + if (mask & 2) { /* C */ | 63 | |
123 | + tcg_gen_extract_i32(cpu_CF, nzcv, 1, 1); | 64 | gen_helper_gvec_mem *fn |
124 | + } | 65 | = ldr_fns[s->mte_active[0]][s->be_data == MO_BE][dtype][0]; |
125 | + if (mask & 1) { /* V */ | 66 | - fn(tcg_env, t_pg, addr, tcg_constant_i32(simd_desc(32, 32, zt))); |
126 | + tcg_gen_shli_i32(cpu_VF, nzcv, 31 - 0); | 67 | + desc = make_svemte_desc(s, 32, 1, dtype_msz(dtype), false, zt); |
127 | + } | 68 | + fn(tcg_env, t_pg, addr, tcg_constant_i32(desc)); |
128 | + | 69 | |
129 | + tcg_temp_free_i32(nzcv); | 70 | /* |
130 | +} | 71 | * Replicate that first octaword. |
131 | + | ||
132 | +/* | ||
133 | + * Evaluate into flags | ||
134 | + * 31 30 29 21 15 14 10 5 4 0 | ||
135 | + * +--+--+--+-----------------+---------+----+---------+------+--+------+ | ||
136 | + * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask | | ||
137 | + * +--+--+--+-----------------+---------+----+---------+------+--+------+ | ||
138 | + */ | ||
139 | +static void disas_evaluate_into_flags(DisasContext *s, uint32_t insn) | ||
140 | +{ | ||
141 | + int o3_mask = extract32(insn, 0, 5); | ||
142 | + int rn = extract32(insn, 5, 5); | ||
143 | + int o2 = extract32(insn, 15, 6); | ||
144 | + int sz = extract32(insn, 14, 1); | ||
145 | + int sf_op_s = extract32(insn, 29, 3); | ||
146 | + TCGv_i32 tmp; | ||
147 | + int shift; | ||
148 | + | ||
149 | + if (sf_op_s != 1 || o2 != 0 || o3_mask != 0xd || | ||
150 | + !dc_isar_feature(aa64_condm_4, s)) { | ||
151 | + unallocated_encoding(s); | ||
152 | + return; | ||
153 | + } | ||
154 | + shift = sz ? 16 : 24; /* SETF16 or SETF8 */ | ||
155 | + | ||
156 | + tmp = tcg_temp_new_i32(); | ||
157 | + tcg_gen_extrl_i64_i32(tmp, cpu_reg(s, rn)); | ||
158 | + tcg_gen_shli_i32(cpu_NF, tmp, shift); | ||
159 | + tcg_gen_shli_i32(cpu_VF, tmp, shift - 1); | ||
160 | + tcg_gen_mov_i32(cpu_ZF, cpu_NF); | ||
161 | + tcg_gen_xor_i32(cpu_VF, cpu_VF, cpu_NF); | ||
162 | + tcg_temp_free_i32(tmp); | ||
163 | +} | ||
164 | + | ||
165 | /* Conditional compare (immediate / register) | ||
166 | * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0 | ||
167 | * +--+--+--+------------------------+--------+------+----+--+------+--+-----+ | ||
168 | @@ -XXX,XX +XXX,XX @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn) | ||
169 | disas_adc_sbc(s, insn); | ||
170 | break; | ||
171 | |||
172 | + case 0x01: /* Rotate right into flags */ | ||
173 | + case 0x21: | ||
174 | + disas_rotate_right_into_flags(s, insn); | ||
175 | + break; | ||
176 | + | ||
177 | + case 0x02: /* Evaluate into flags */ | ||
178 | + case 0x12: | ||
179 | + case 0x22: | ||
180 | + case 0x32: | ||
181 | + disas_evaluate_into_flags(s, insn); | ||
182 | + break; | ||
183 | + | ||
184 | default: | ||
185 | goto do_unallocated; | ||
186 | } | ||
187 | -- | 72 | -- |
188 | 2.20.1 | 73 | 2.34.1 |
189 | |||
190 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Richard Henderson <richard.henderson@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This will allow sharing code that adjusts rmode beyond | 3 | The TBI and TCMA bits are located within mtedesc, not desc. |
4 | the existing users. | ||
5 | 4 | ||
6 | Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> | 5 | Cc: qemu-stable@nongnu.org |
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20190301200501.16533-10-richard.henderson@linaro.org | 8 | Tested-by: Gustavo Romero <gustavo.romero@linaro.org> |
9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Message-id: 20240207025210.8837-7-richard.henderson@linaro.org |
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | --- | 11 | --- |
12 | target/arm/translate-a64.c | 90 +++++++++++++++++++++----------------- | 12 | target/arm/tcg/sme_helper.c | 8 ++++---- |
13 | 1 file changed, 49 insertions(+), 41 deletions(-) | 13 | target/arm/tcg/sve_helper.c | 12 ++++++------ |
14 | 2 files changed, 10 insertions(+), 10 deletions(-) | ||
14 | 15 | ||
15 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 16 | diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c |
16 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/translate-a64.c | 18 | --- a/target/arm/tcg/sme_helper.c |
18 | +++ b/target/arm/translate-a64.c | 19 | +++ b/target/arm/tcg/sme_helper.c |
19 | @@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn) | 20 | @@ -XXX,XX +XXX,XX @@ void sme_ld1_mte(CPUARMState *env, void *za, uint64_t *vg, |
20 | /* Floating-point data-processing (1 source) - single precision */ | 21 | desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); |
21 | static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn) | 22 | |
22 | { | 23 | /* Perform gross MTE suppression early. */ |
23 | + void (*gen_fpst)(TCGv_i32, TCGv_i32, TCGv_ptr); | 24 | - if (!tbi_check(desc, bit55) || |
24 | + TCGv_i32 tcg_op, tcg_res; | 25 | - tcma_check(desc, bit55, allocation_tag_from_addr(addr))) { |
25 | TCGv_ptr fpst; | 26 | + if (!tbi_check(mtedesc, bit55) || |
26 | - TCGv_i32 tcg_op; | 27 | + tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) { |
27 | - TCGv_i32 tcg_res; | 28 | mtedesc = 0; |
28 | + int rmode = -1; | ||
29 | |||
30 | - fpst = get_fpstatus_ptr(false); | ||
31 | tcg_op = read_fp_sreg(s, rn); | ||
32 | tcg_res = tcg_temp_new_i32(); | ||
33 | |||
34 | switch (opcode) { | ||
35 | case 0x0: /* FMOV */ | ||
36 | tcg_gen_mov_i32(tcg_res, tcg_op); | ||
37 | - break; | ||
38 | + goto done; | ||
39 | case 0x1: /* FABS */ | ||
40 | gen_helper_vfp_abss(tcg_res, tcg_op); | ||
41 | - break; | ||
42 | + goto done; | ||
43 | case 0x2: /* FNEG */ | ||
44 | gen_helper_vfp_negs(tcg_res, tcg_op); | ||
45 | - break; | ||
46 | + goto done; | ||
47 | case 0x3: /* FSQRT */ | ||
48 | gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env); | ||
49 | - break; | ||
50 | + goto done; | ||
51 | case 0x8: /* FRINTN */ | ||
52 | case 0x9: /* FRINTP */ | ||
53 | case 0xa: /* FRINTM */ | ||
54 | case 0xb: /* FRINTZ */ | ||
55 | case 0xc: /* FRINTA */ | ||
56 | - { | ||
57 | - TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7)); | ||
58 | - | ||
59 | - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | ||
60 | - gen_helper_rints(tcg_res, tcg_op, fpst); | ||
61 | - | ||
62 | - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | ||
63 | - tcg_temp_free_i32(tcg_rmode); | ||
64 | + rmode = arm_rmode_to_sf(opcode & 7); | ||
65 | + gen_fpst = gen_helper_rints; | ||
66 | break; | ||
67 | - } | ||
68 | case 0xe: /* FRINTX */ | ||
69 | - gen_helper_rints_exact(tcg_res, tcg_op, fpst); | ||
70 | + gen_fpst = gen_helper_rints_exact; | ||
71 | break; | ||
72 | case 0xf: /* FRINTI */ | ||
73 | - gen_helper_rints(tcg_res, tcg_op, fpst); | ||
74 | + gen_fpst = gen_helper_rints; | ||
75 | break; | ||
76 | default: | ||
77 | - abort(); | ||
78 | + g_assert_not_reached(); | ||
79 | } | 29 | } |
80 | 30 | ||
81 | - write_fp_sreg(s, rd, tcg_res); | 31 | @@ -XXX,XX +XXX,XX @@ void sme_st1_mte(CPUARMState *env, void *za, uint64_t *vg, target_ulong addr, |
82 | - | 32 | desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); |
83 | + fpst = get_fpstatus_ptr(false); | 33 | |
84 | + if (rmode >= 0) { | 34 | /* Perform gross MTE suppression early. */ |
85 | + TCGv_i32 tcg_rmode = tcg_const_i32(rmode); | 35 | - if (!tbi_check(desc, bit55) || |
86 | + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | 36 | - tcma_check(desc, bit55, allocation_tag_from_addr(addr))) { |
87 | + gen_fpst(tcg_res, tcg_op, fpst); | 37 | + if (!tbi_check(mtedesc, bit55) || |
88 | + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | 38 | + tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) { |
89 | + tcg_temp_free_i32(tcg_rmode); | 39 | mtedesc = 0; |
90 | + } else { | ||
91 | + gen_fpst(tcg_res, tcg_op, fpst); | ||
92 | + } | ||
93 | tcg_temp_free_ptr(fpst); | ||
94 | + | ||
95 | + done: | ||
96 | + write_fp_sreg(s, rd, tcg_res); | ||
97 | tcg_temp_free_i32(tcg_op); | ||
98 | tcg_temp_free_i32(tcg_res); | ||
99 | } | ||
100 | @@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn) | ||
101 | /* Floating-point data-processing (1 source) - double precision */ | ||
102 | static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn) | ||
103 | { | ||
104 | + void (*gen_fpst)(TCGv_i64, TCGv_i64, TCGv_ptr); | ||
105 | + TCGv_i64 tcg_op, tcg_res; | ||
106 | TCGv_ptr fpst; | ||
107 | - TCGv_i64 tcg_op; | ||
108 | - TCGv_i64 tcg_res; | ||
109 | + int rmode = -1; | ||
110 | |||
111 | switch (opcode) { | ||
112 | case 0x0: /* FMOV */ | ||
113 | @@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn) | ||
114 | return; | ||
115 | } | 40 | } |
116 | 41 | ||
117 | - fpst = get_fpstatus_ptr(false); | 42 | diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c |
118 | tcg_op = read_fp_dreg(s, rn); | 43 | index XXXXXXX..XXXXXXX 100644 |
119 | tcg_res = tcg_temp_new_i64(); | 44 | --- a/target/arm/tcg/sve_helper.c |
120 | 45 | +++ b/target/arm/tcg/sve_helper.c | |
121 | switch (opcode) { | 46 | @@ -XXX,XX +XXX,XX @@ void sve_ldN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr, |
122 | case 0x1: /* FABS */ | 47 | desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); |
123 | gen_helper_vfp_absd(tcg_res, tcg_op); | 48 | |
124 | - break; | 49 | /* Perform gross MTE suppression early. */ |
125 | + goto done; | 50 | - if (!tbi_check(desc, bit55) || |
126 | case 0x2: /* FNEG */ | 51 | - tcma_check(desc, bit55, allocation_tag_from_addr(addr))) { |
127 | gen_helper_vfp_negd(tcg_res, tcg_op); | 52 | + if (!tbi_check(mtedesc, bit55) || |
128 | - break; | 53 | + tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) { |
129 | + goto done; | 54 | mtedesc = 0; |
130 | case 0x3: /* FSQRT */ | ||
131 | gen_helper_vfp_sqrtd(tcg_res, tcg_op, cpu_env); | ||
132 | - break; | ||
133 | + goto done; | ||
134 | case 0x8: /* FRINTN */ | ||
135 | case 0x9: /* FRINTP */ | ||
136 | case 0xa: /* FRINTM */ | ||
137 | case 0xb: /* FRINTZ */ | ||
138 | case 0xc: /* FRINTA */ | ||
139 | - { | ||
140 | - TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7)); | ||
141 | - | ||
142 | - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | ||
143 | - gen_helper_rintd(tcg_res, tcg_op, fpst); | ||
144 | - | ||
145 | - gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | ||
146 | - tcg_temp_free_i32(tcg_rmode); | ||
147 | + rmode = arm_rmode_to_sf(opcode & 7); | ||
148 | + gen_fpst = gen_helper_rintd; | ||
149 | break; | ||
150 | - } | ||
151 | case 0xe: /* FRINTX */ | ||
152 | - gen_helper_rintd_exact(tcg_res, tcg_op, fpst); | ||
153 | + gen_fpst = gen_helper_rintd_exact; | ||
154 | break; | ||
155 | case 0xf: /* FRINTI */ | ||
156 | - gen_helper_rintd(tcg_res, tcg_op, fpst); | ||
157 | + gen_fpst = gen_helper_rintd; | ||
158 | break; | ||
159 | default: | ||
160 | - abort(); | ||
161 | + g_assert_not_reached(); | ||
162 | } | 55 | } |
163 | 56 | ||
164 | - write_fp_dreg(s, rd, tcg_res); | 57 | @@ -XXX,XX +XXX,XX @@ void sve_ldnfff1_r_mte(CPUARMState *env, void *vg, target_ulong addr, |
165 | - | 58 | desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); |
166 | + fpst = get_fpstatus_ptr(false); | 59 | |
167 | + if (rmode >= 0) { | 60 | /* Perform gross MTE suppression early. */ |
168 | + TCGv_i32 tcg_rmode = tcg_const_i32(rmode); | 61 | - if (!tbi_check(desc, bit55) || |
169 | + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | 62 | - tcma_check(desc, bit55, allocation_tag_from_addr(addr))) { |
170 | + gen_fpst(tcg_res, tcg_op, fpst); | 63 | + if (!tbi_check(mtedesc, bit55) || |
171 | + gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); | 64 | + tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) { |
172 | + tcg_temp_free_i32(tcg_rmode); | 65 | mtedesc = 0; |
173 | + } else { | 66 | } |
174 | + gen_fpst(tcg_res, tcg_op, fpst); | 67 | |
175 | + } | 68 | @@ -XXX,XX +XXX,XX @@ void sve_stN_r_mte(CPUARMState *env, uint64_t *vg, target_ulong addr, |
176 | tcg_temp_free_ptr(fpst); | 69 | desc = extract32(desc, 0, SIMD_DATA_SHIFT + SVE_MTEDESC_SHIFT); |
177 | + | 70 | |
178 | + done: | 71 | /* Perform gross MTE suppression early. */ |
179 | + write_fp_dreg(s, rd, tcg_res); | 72 | - if (!tbi_check(desc, bit55) || |
180 | tcg_temp_free_i64(tcg_op); | 73 | - tcma_check(desc, bit55, allocation_tag_from_addr(addr))) { |
181 | tcg_temp_free_i64(tcg_res); | 74 | + if (!tbi_check(mtedesc, bit55) || |
182 | } | 75 | + tcma_check(mtedesc, bit55, allocation_tag_from_addr(addr))) { |
76 | mtedesc = 0; | ||
77 | } | ||
78 | |||
183 | -- | 79 | -- |
184 | 2.20.1 | 80 | 2.34.1 |
185 | |||
186 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The raven_io_ops MemoryRegionOps is the only one in the source tree | ||
2 | which sets .valid.unaligned to indicate that it should support | ||
3 | unaligned accesses and which does not also set .impl.unaligned to | ||
4 | indicate that its read and write functions can do the unaligned | ||
5 | handling themselves. This is a problem, because at the moment the | ||
6 | core memory system does not implement the support for handling | ||
7 | unaligned accesses by doing a series of aligned accesses and | ||
8 | combining them (system/memory.c:access_with_adjusted_size() has a | ||
9 | TODO comment noting this). | ||
1 | 10 | ||
11 | Fortunately raven_io_read() and raven_io_write() will correctly deal | ||
12 | with the case of being passed an unaligned address, so we can fix the | ||
13 | missing unaligned access support by setting .impl.unaligned in the | ||
14 | MemoryRegionOps struct. | ||
15 | |||
16 | Fixes: 9a1839164c9c8f06 ("raven: Implement non-contiguous I/O region") | ||
17 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
18 | Tested-by: Cédric Le Goater <clg@redhat.com> | ||
19 | Reviewed-by: Cédric Le Goater <clg@redhat.com> | ||
20 | Message-id: 20240112134640.1775041-1-peter.maydell@linaro.org | ||
21 | --- | ||
22 | hw/pci-host/raven.c | 1 + | ||
23 | 1 file changed, 1 insertion(+) | ||
24 | |||
25 | diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c | ||
26 | index XXXXXXX..XXXXXXX 100644 | ||
27 | --- a/hw/pci-host/raven.c | ||
28 | +++ b/hw/pci-host/raven.c | ||
29 | @@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps raven_io_ops = { | ||
30 | .write = raven_io_write, | ||
31 | .endianness = DEVICE_LITTLE_ENDIAN, | ||
32 | .impl.max_access_size = 4, | ||
33 | + .impl.unaligned = true, | ||
34 | .valid.unaligned = true, | ||
35 | }; | ||
36 | |||
37 | -- | ||
38 | 2.34.1 | ||
39 | |||
40 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Suppress the deprecation warning when we're running under qtest, | ||
2 | to avoid "make check" including warning messages in its output. | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
6 | Message-id: 20240206154151.155620-1-peter.maydell@linaro.org | ||
7 | --- | ||
8 | hw/block/tc58128.c | 4 +++- | ||
9 | 1 file changed, 3 insertions(+), 1 deletion(-) | ||
10 | |||
11 | diff --git a/hw/block/tc58128.c b/hw/block/tc58128.c | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/hw/block/tc58128.c | ||
14 | +++ b/hw/block/tc58128.c | ||
15 | @@ -XXX,XX +XXX,XX @@ static sh7750_io_device tc58128 = { | ||
16 | |||
17 | int tc58128_init(struct SH7750State *s, const char *zone1, const char *zone2) | ||
18 | { | ||
19 | - warn_report_once("The TC58128 flash device is deprecated"); | ||
20 | + if (!qtest_enabled()) { | ||
21 | + warn_report_once("The TC58128 flash device is deprecated"); | ||
22 | + } | ||
23 | init_dev(&tc58128_devs[0], zone1); | ||
24 | init_dev(&tc58128_devs[1], zone2); | ||
25 | return sh7750_register_io_device(s, &tc58128); | ||
26 | -- | ||
27 | 2.34.1 | ||
28 | |||
29 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | We deliberately don't include qtests_npcm7xx in qtests_aarch64, |
---|---|---|---|
2 | because we already get the coverage of those tests via qtests_arm, | ||
3 | and we don't want to use extra CI minutes testing them twice. | ||
2 | 4 | ||
3 | We are about to allow the memory map to grow beyond 1TB and | 5 | In commit 327b680877b79c4b we added it to qtests_aarch64; revert |
4 | potentially overshoot the VCPU AA64MMFR0.PARANGE. | 6 | that change. |
5 | 7 | ||
6 | In aarch64 mode and when highmem is set, let's check the VCPU | 8 | Fixes: 327b680877b79c4b ("tests/qtest: Creating qtest for GMAC Module") |
7 | PA range is sufficient to address the highest GPA of the memory | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
8 | map. | 10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
11 | Message-id: 20240206163043.315535-1-peter.maydell@linaro.org | ||
12 | --- | ||
13 | tests/qtest/meson.build | 1 - | ||
14 | 1 file changed, 1 deletion(-) | ||
9 | 15 | ||
10 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | 16 | diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build |
11 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | ||
12 | Message-id: 20190304101339.25970-10-eric.auger@redhat.com | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | ||
15 | hw/arm/virt.c | 17 +++++++++++++++++ | ||
16 | 1 file changed, 17 insertions(+) | ||
17 | |||
18 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
19 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/hw/arm/virt.c | 18 | --- a/tests/qtest/meson.build |
21 | +++ b/hw/arm/virt.c | 19 | +++ b/tests/qtest/meson.build |
22 | @@ -XXX,XX +XXX,XX @@ | 20 | @@ -XXX,XX +XXX,XX @@ qtests_aarch64 = \ |
23 | #include "standard-headers/linux/input.h" | 21 | (config_all_devices.has_key('CONFIG_RASPI') ? ['bcm2835-dma-test'] : []) + \ |
24 | #include "hw/arm/smmuv3.h" | 22 | (config_all_accel.has_key('CONFIG_TCG') and \ |
25 | #include "hw/acpi/acpi.h" | 23 | config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test'] : []) + \ |
26 | +#include "target/arm/internals.h" | 24 | - (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \ |
27 | 25 | ['arm-cpu-features', | |
28 | #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ | 26 | 'numa-test', |
29 | static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ | 27 | 'boot-serial-test', |
30 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | ||
31 | fdt_add_timer_nodes(vms); | ||
32 | fdt_add_cpu_nodes(vms); | ||
33 | |||
34 | + if (!kvm_enabled()) { | ||
35 | + ARMCPU *cpu = ARM_CPU(first_cpu); | ||
36 | + bool aarch64 = object_property_get_bool(OBJECT(cpu), "aarch64", NULL); | ||
37 | + | ||
38 | + if (aarch64 && vms->highmem) { | ||
39 | + int requested_pa_size, pamax = arm_pamax(cpu); | ||
40 | + | ||
41 | + requested_pa_size = 64 - clz64(vms->highest_gpa); | ||
42 | + if (pamax < requested_pa_size) { | ||
43 | + error_report("VCPU supports less PA bits (%d) than requested " | ||
44 | + "by the memory map (%d)", pamax, requested_pa_size); | ||
45 | + exit(1); | ||
46 | + } | ||
47 | + } | ||
48 | + } | ||
49 | + | ||
50 | memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", | ||
51 | machine->ram_size); | ||
52 | memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram); | ||
53 | -- | 28 | -- |
54 | 2.20.1 | 29 | 2.34.1 |
55 | 30 | ||
56 | 31 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Allow changes to the virt GTDT -- we are going to add the IRQ | ||
2 | entry for a new timer to it. | ||
1 | 3 | ||
4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
5 | Reviewed-by: Ard Biesheuvel <ardb@kernel.org> | ||
6 | Message-id: 20240122143537.233498-2-peter.maydell@linaro.org | ||
7 | --- | ||
8 | tests/qtest/bios-tables-test-allowed-diff.h | 2 ++ | ||
9 | 1 file changed, 2 insertions(+) | ||
10 | |||
11 | diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h | ||
12 | index XXXXXXX..XXXXXXX 100644 | ||
13 | --- a/tests/qtest/bios-tables-test-allowed-diff.h | ||
14 | +++ b/tests/qtest/bios-tables-test-allowed-diff.h | ||
15 | @@ -1 +1,3 @@ | ||
16 | /* List of comma-separated changed AML files to ignore */ | ||
17 | +"tests/data/acpi/virt/FACP", | ||
18 | +"tests/data/acpi/virt/GTDT", | ||
19 | -- | ||
20 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | Armv8.1+ CPUs have the Virtual Host Extension (VHE) which adds a |
---|---|---|---|
2 | 2 | non-secure EL2 virtual timer. We implemented the timer itself in the | |
3 | In preparation for a split of the memory map into a static | 3 | CPU model, but never wired up its IRQ line to the GIC. |
4 | part and a dynamic part floating after the RAM, let's rename the | 4 | |
5 | regions located after the RAM | 5 | Wire up the IRQ line (this is always safe whether the CPU has the |
6 | 6 | interrupt or not, since it always creates the outbound IRQ line). | |
7 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | 7 | Report it to the guest via dtb and ACPI if the CPU has the feature. |
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 8 | |
9 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | 9 | The DTB binding is documented in the kernel's |
10 | Message-id: 20190304101339.25970-3-eric.auger@redhat.com | 10 | Documentation/devicetree/bindings/timer/arm\,arch_timer.yaml |
11 | and the ACPI table entries are documented in the ACPI specification | ||
12 | version 6.3 or later. | ||
13 | |||
14 | Because the IRQ line ACPI binding is new in 6.3, we need to bump the | ||
15 | FADT table rev to show that we might be using 6.3 features. | ||
16 | |||
17 | Note that exposing this IRQ in the DTB will trigger a bug in EDK2 | ||
18 | versions prior to edk2-stable202311, for users who use the virt board | ||
19 | with 'virtualization=on' to enable EL2 emulation and are booting an | ||
20 | EDK2 guest BIOS, if that EDK2 has assertions enabled. The effect is | ||
21 | that EDK2 will assert on bootup: | ||
22 | |||
23 | ASSERT [ArmTimerDxe] /home/kraxel/projects/qemu/roms/edk2/ArmVirtPkg/Library/ArmVirtTimerFdtClientLib/ArmVirtTimerFdtClientLib.c(72): PropSize == 36 || PropSize == 48 | ||
24 | |||
25 | If you see that assertion you should do one of: | ||
26 | * update your EDK2 binaries to edk2-stable202311 or newer | ||
27 | * use the 'virt-8.2' versioned machine type | ||
28 | * not use 'virtualization=on' | ||
29 | |||
30 | (The versions shipped with QEMU itself have the fix.) | ||
31 | |||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 32 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
33 | Reviewed-by: Ard Biesheuvel <ardb@kernel.org> | ||
34 | Message-id: 20240122143537.233498-3-peter.maydell@linaro.org | ||
12 | --- | 35 | --- |
13 | include/hw/arm/virt.h | 8 ++++---- | 36 | include/hw/arm/virt.h | 2 ++ |
14 | hw/arm/virt-acpi-build.c | 10 ++++++---- | 37 | hw/arm/virt-acpi-build.c | 20 ++++++++++---- |
15 | hw/arm/virt.c | 33 ++++++++++++++++++--------------- | 38 | hw/arm/virt.c | 60 ++++++++++++++++++++++++++++++++++------ |
16 | 3 files changed, 28 insertions(+), 23 deletions(-) | 39 | 3 files changed, 67 insertions(+), 15 deletions(-) |
17 | 40 | ||
18 | diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h | 41 | diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h |
19 | index XXXXXXX..XXXXXXX 100644 | 42 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/include/hw/arm/virt.h | 43 | --- a/include/hw/arm/virt.h |
21 | +++ b/include/hw/arm/virt.h | 44 | +++ b/include/hw/arm/virt.h |
22 | @@ -XXX,XX +XXX,XX @@ enum { | 45 | @@ -XXX,XX +XXX,XX @@ struct VirtMachineClass { |
23 | VIRT_GIC_VCPU, | 46 | /* Machines < 6.2 have no support for describing cpu topology to guest */ |
24 | VIRT_GIC_ITS, | 47 | bool no_cpu_topology; |
25 | VIRT_GIC_REDIST, | 48 | bool no_tcg_lpa2; |
26 | - VIRT_GIC_REDIST2, | 49 | + bool no_ns_el2_virt_timer_irq; |
27 | + VIRT_HIGH_GIC_REDIST2, | 50 | }; |
28 | VIRT_SMMU, | 51 | |
29 | VIRT_UART, | 52 | struct VirtMachineState { |
30 | VIRT_MMIO, | 53 | @@ -XXX,XX +XXX,XX @@ struct VirtMachineState { |
31 | @@ -XXX,XX +XXX,XX @@ enum { | 54 | PCIBus *bus; |
32 | VIRT_PCIE_MMIO, | 55 | char *oem_id; |
33 | VIRT_PCIE_PIO, | 56 | char *oem_table_id; |
34 | VIRT_PCIE_ECAM, | 57 | + bool ns_el2_virt_timer_irq; |
35 | - VIRT_PCIE_ECAM_HIGH, | 58 | }; |
36 | + VIRT_HIGH_PCIE_ECAM, | 59 | |
37 | VIRT_PLATFORM_BUS, | 60 | #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM) |
38 | - VIRT_PCIE_MMIO_HIGH, | ||
39 | + VIRT_HIGH_PCIE_MMIO, | ||
40 | VIRT_GPIO, | ||
41 | VIRT_SECURE_UART, | ||
42 | VIRT_SECURE_MEM, | ||
43 | @@ -XXX,XX +XXX,XX @@ typedef struct { | ||
44 | int psci_conduit; | ||
45 | } VirtMachineState; | ||
46 | |||
47 | -#define VIRT_ECAM_ID(high) (high ? VIRT_PCIE_ECAM_HIGH : VIRT_PCIE_ECAM) | ||
48 | +#define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM) | ||
49 | |||
50 | #define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt") | ||
51 | #define VIRT_MACHINE(obj) \ | ||
52 | diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c | 61 | diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c |
53 | index XXXXXXX..XXXXXXX 100644 | 62 | index XXXXXXX..XXXXXXX 100644 |
54 | --- a/hw/arm/virt-acpi-build.c | 63 | --- a/hw/arm/virt-acpi-build.c |
55 | +++ b/hw/arm/virt-acpi-build.c | 64 | +++ b/hw/arm/virt-acpi-build.c |
56 | @@ -XXX,XX +XXX,XX @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, | 65 | @@ -XXX,XX +XXX,XX @@ build_srat(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
57 | size_pio)); | 66 | } |
58 | 67 | ||
59 | if (use_highmem) { | 68 | /* |
60 | - hwaddr base_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].base; | 69 | - * ACPI spec, Revision 5.1 |
61 | - hwaddr size_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].size; | 70 | - * 5.2.24 Generic Timer Description Table (GTDT) |
62 | + hwaddr base_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].base; | 71 | + * ACPI spec, Revision 6.5 |
63 | + hwaddr size_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].size; | 72 | + * 5.2.25 Generic Timer Description Table (GTDT) |
64 | 73 | */ | |
65 | aml_append(rbuf, | 74 | static void |
66 | aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, | 75 | build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
76 | @@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) | ||
77 | uint32_t irqflags = vmc->claim_edge_triggered_timers ? | ||
78 | 1 : /* Interrupt is Edge triggered */ | ||
79 | 0; /* Interrupt is Level triggered */ | ||
80 | - AcpiTable table = { .sig = "GTDT", .rev = 2, .oem_id = vms->oem_id, | ||
81 | + AcpiTable table = { .sig = "GTDT", .rev = 3, .oem_id = vms->oem_id, | ||
82 | .oem_table_id = vms->oem_table_id }; | ||
83 | |||
84 | acpi_table_begin(&table, table_data); | ||
85 | @@ -XXX,XX +XXX,XX @@ build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) | ||
86 | build_append_int_noprefix(table_data, 0, 4); | ||
87 | /* Platform Timer Offset */ | ||
88 | build_append_int_noprefix(table_data, 0, 4); | ||
89 | - | ||
90 | + if (vms->ns_el2_virt_timer_irq) { | ||
91 | + /* Virtual EL2 Timer GSIV */ | ||
92 | + build_append_int_noprefix(table_data, ARCH_TIMER_NS_EL2_VIRT_IRQ, 4); | ||
93 | + /* Virtual EL2 Timer Flags */ | ||
94 | + build_append_int_noprefix(table_data, irqflags, 4); | ||
95 | + } else { | ||
96 | + build_append_int_noprefix(table_data, 0, 4); | ||
97 | + build_append_int_noprefix(table_data, 0, 4); | ||
98 | + } | ||
99 | acpi_table_end(linker, &table); | ||
100 | } | ||
101 | |||
67 | @@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) | 102 | @@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) |
68 | gicr = acpi_data_push(table_data, sizeof(*gicr)); | 103 | static void build_fadt_rev6(GArray *table_data, BIOSLinker *linker, |
69 | gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR; | 104 | VirtMachineState *vms, unsigned dsdt_tbl_offset) |
70 | gicr->length = sizeof(*gicr); | 105 | { |
71 | - gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST2].base); | 106 | - /* ACPI v6.0 */ |
72 | - gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST2].size); | 107 | + /* ACPI v6.3 */ |
73 | + gicr->base_address = | 108 | AcpiFadtData fadt = { |
74 | + cpu_to_le64(memmap[VIRT_HIGH_GIC_REDIST2].base); | 109 | .rev = 6, |
75 | + gicr->range_length = | 110 | - .minor_ver = 0, |
76 | + cpu_to_le32(memmap[VIRT_HIGH_GIC_REDIST2].size); | 111 | + .minor_ver = 3, |
77 | } | 112 | .flags = 1 << ACPI_FADT_F_HW_REDUCED_ACPI, |
78 | 113 | .xdsdt_tbl_offset = &dsdt_tbl_offset, | |
79 | if (its_class_name() && !vmc->no_its) { | 114 | }; |
80 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 115 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c |
81 | index XXXXXXX..XXXXXXX 100644 | 116 | index XXXXXXX..XXXXXXX 100644 |
82 | --- a/hw/arm/virt.c | 117 | --- a/hw/arm/virt.c |
83 | +++ b/hw/arm/virt.c | 118 | +++ b/hw/arm/virt.c |
84 | @@ -XXX,XX +XXX,XX @@ static const MemMapEntry a15memmap[] = { | 119 | @@ -XXX,XX +XXX,XX @@ static void create_randomness(MachineState *ms, const char *node) |
85 | [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, | 120 | qemu_fdt_setprop(ms->fdt, node, "rng-seed", seed.rng, sizeof(seed.rng)); |
86 | [VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES }, | 121 | } |
87 | /* Additional 64 MB redist region (can contain up to 512 redistributors) */ | 122 | |
88 | - [VIRT_GIC_REDIST2] = { 0x4000000000ULL, 0x4000000 }, | 123 | +/* |
89 | - [VIRT_PCIE_ECAM_HIGH] = { 0x4010000000ULL, 0x10000000 }, | 124 | + * The CPU object always exposes the NS EL2 virt timer IRQ line, |
90 | + [VIRT_HIGH_GIC_REDIST2] = { 0x4000000000ULL, 0x4000000 }, | 125 | + * but we don't want to advertise it to the guest in the dtb or ACPI |
91 | + [VIRT_HIGH_PCIE_ECAM] = { 0x4010000000ULL, 0x10000000 }, | 126 | + * table unless it's really going to do something. |
92 | /* Second PCIe window, 512GB wide at the 512GB boundary */ | 127 | + */ |
93 | - [VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL }, | 128 | +static bool ns_el2_virt_timer_present(void) |
94 | + [VIRT_HIGH_PCIE_MMIO] = { 0x8000000000ULL, 0x8000000000ULL }, | 129 | +{ |
95 | }; | 130 | + ARMCPU *cpu = ARM_CPU(qemu_get_cpu(0)); |
96 | 131 | + CPUARMState *env = &cpu->env; | |
97 | static const int a15irqmap[] = { | 132 | + |
98 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_gic_node(VirtMachineState *vms) | 133 | + return arm_feature(env, ARM_FEATURE_AARCH64) && |
99 | 2, vms->memmap[VIRT_GIC_REDIST].size); | 134 | + arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu); |
100 | } else { | 135 | +} |
101 | qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", | 136 | + |
102 | - 2, vms->memmap[VIRT_GIC_DIST].base, | 137 | static void create_fdt(VirtMachineState *vms) |
103 | - 2, vms->memmap[VIRT_GIC_DIST].size, | ||
104 | - 2, vms->memmap[VIRT_GIC_REDIST].base, | ||
105 | - 2, vms->memmap[VIRT_GIC_REDIST].size, | ||
106 | - 2, vms->memmap[VIRT_GIC_REDIST2].base, | ||
107 | - 2, vms->memmap[VIRT_GIC_REDIST2].size); | ||
108 | + 2, vms->memmap[VIRT_GIC_DIST].base, | ||
109 | + 2, vms->memmap[VIRT_GIC_DIST].size, | ||
110 | + 2, vms->memmap[VIRT_GIC_REDIST].base, | ||
111 | + 2, vms->memmap[VIRT_GIC_REDIST].size, | ||
112 | + 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base, | ||
113 | + 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size); | ||
114 | } | ||
115 | |||
116 | if (vms->virt) { | ||
117 | @@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, qemu_irq *pic) | ||
118 | |||
119 | if (nb_redist_regions == 2) { | ||
120 | uint32_t redist1_capacity = | ||
121 | - vms->memmap[VIRT_GIC_REDIST2].size / GICV3_REDIST_SIZE; | ||
122 | + vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; | ||
123 | |||
124 | qdev_prop_set_uint32(gicdev, "redist-region-count[1]", | ||
125 | MIN(smp_cpus - redist0_count, redist1_capacity)); | ||
126 | @@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, qemu_irq *pic) | ||
127 | if (type == 3) { | ||
128 | sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); | ||
129 | if (nb_redist_regions == 2) { | ||
130 | - sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_REDIST2].base); | ||
131 | + sysbus_mmio_map(gicbusdev, 2, | ||
132 | + vms->memmap[VIRT_HIGH_GIC_REDIST2].base); | ||
133 | } | ||
134 | } else { | ||
135 | sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); | ||
136 | @@ -XXX,XX +XXX,XX @@ static void create_pcie(VirtMachineState *vms, qemu_irq *pic) | ||
137 | { | 138 | { |
138 | hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base; | 139 | MachineState *ms = MACHINE(vms); |
139 | hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size; | 140 | @@ -XXX,XX +XXX,XX @@ static void fdt_add_timer_nodes(const VirtMachineState *vms) |
140 | - hwaddr base_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].base; | 141 | "arm,armv7-timer"); |
141 | - hwaddr size_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].size; | 142 | } |
142 | + hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base; | 143 | qemu_fdt_setprop(ms->fdt, "/timer", "always-on", NULL, 0); |
143 | + hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size; | 144 | - qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", |
144 | hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base; | 145 | - GIC_FDT_IRQ_TYPE_PPI, |
145 | hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size; | 146 | - INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags, |
146 | hwaddr base_ecam, size_ecam; | 147 | - GIC_FDT_IRQ_TYPE_PPI, |
148 | - INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags, | ||
149 | - GIC_FDT_IRQ_TYPE_PPI, | ||
150 | - INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags, | ||
151 | - GIC_FDT_IRQ_TYPE_PPI, | ||
152 | - INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags); | ||
153 | + if (vms->ns_el2_virt_timer_irq) { | ||
154 | + qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", | ||
155 | + GIC_FDT_IRQ_TYPE_PPI, | ||
156 | + INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags, | ||
157 | + GIC_FDT_IRQ_TYPE_PPI, | ||
158 | + INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags, | ||
159 | + GIC_FDT_IRQ_TYPE_PPI, | ||
160 | + INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags, | ||
161 | + GIC_FDT_IRQ_TYPE_PPI, | ||
162 | + INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags, | ||
163 | + GIC_FDT_IRQ_TYPE_PPI, | ||
164 | + INTID_TO_PPI(ARCH_TIMER_NS_EL2_VIRT_IRQ), irqflags); | ||
165 | + } else { | ||
166 | + qemu_fdt_setprop_cells(ms->fdt, "/timer", "interrupts", | ||
167 | + GIC_FDT_IRQ_TYPE_PPI, | ||
168 | + INTID_TO_PPI(ARCH_TIMER_S_EL1_IRQ), irqflags, | ||
169 | + GIC_FDT_IRQ_TYPE_PPI, | ||
170 | + INTID_TO_PPI(ARCH_TIMER_NS_EL1_IRQ), irqflags, | ||
171 | + GIC_FDT_IRQ_TYPE_PPI, | ||
172 | + INTID_TO_PPI(ARCH_TIMER_VIRT_IRQ), irqflags, | ||
173 | + GIC_FDT_IRQ_TYPE_PPI, | ||
174 | + INTID_TO_PPI(ARCH_TIMER_NS_EL2_IRQ), irqflags); | ||
175 | + } | ||
176 | } | ||
177 | |||
178 | static void fdt_add_cpu_nodes(const VirtMachineState *vms) | ||
179 | @@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, MemoryRegion *mem) | ||
180 | [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, | ||
181 | [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, | ||
182 | [GTIMER_SEC] = ARCH_TIMER_S_EL1_IRQ, | ||
183 | + [GTIMER_HYPVIRT] = ARCH_TIMER_NS_EL2_VIRT_IRQ, | ||
184 | }; | ||
185 | |||
186 | for (unsigned irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { | ||
147 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | 187 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) |
148 | * many redistributors we can fit into the memory map. | 188 | qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); |
149 | */ | 189 | object_unref(cpuobj); |
150 | if (vms->gic_version == 3) { | ||
151 | - virt_max_cpus = vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; | ||
152 | - virt_max_cpus += vms->memmap[VIRT_GIC_REDIST2].size / GICV3_REDIST_SIZE; | ||
153 | + virt_max_cpus = | ||
154 | + vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; | ||
155 | + virt_max_cpus += | ||
156 | + vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; | ||
157 | } else { | ||
158 | virt_max_cpus = GIC_NCPU; | ||
159 | } | 190 | } |
191 | + | ||
192 | + /* Now we've created the CPUs we can see if they have the hypvirt timer */ | ||
193 | + vms->ns_el2_virt_timer_irq = ns_el2_virt_timer_present() && | ||
194 | + !vmc->no_ns_el2_virt_timer_irq; | ||
195 | + | ||
196 | fdt_add_timer_nodes(vms); | ||
197 | fdt_add_cpu_nodes(vms); | ||
198 | |||
199 | @@ -XXX,XX +XXX,XX @@ DEFINE_VIRT_MACHINE_AS_LATEST(9, 0) | ||
200 | |||
201 | static void virt_machine_8_2_options(MachineClass *mc) | ||
202 | { | ||
203 | + VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); | ||
204 | + | ||
205 | virt_machine_9_0_options(mc); | ||
206 | compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len); | ||
207 | + /* | ||
208 | + * Don't expose NS_EL2_VIRT timer IRQ in DTB on ACPI on 8.2 and | ||
209 | + * earlier machines. (Exposing it tickles a bug in older EDK2 | ||
210 | + * guest BIOS binaries.) | ||
211 | + */ | ||
212 | + vmc->no_ns_el2_virt_timer_irq = true; | ||
213 | } | ||
214 | DEFINE_VIRT_MACHINE(8, 2) | ||
215 | |||
160 | -- | 216 | -- |
161 | 2.20.1 | 217 | 2.34.1 |
162 | |||
163 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | Update the virt golden reference files to say that the FACP is ACPI | |
2 | v6.3, and the GTDT table is a revision 3 table with space for the | ||
3 | virtual EL2 timer. | ||
4 | |||
5 | Diffs from iasl: | ||
6 | |||
7 | @@ -XXX,XX +XXX,XX @@ | ||
8 | /* | ||
9 | * Intel ACPI Component Architecture | ||
10 | * AML/ASL+ Disassembler version 20200925 (64-bit version) | ||
11 | * Copyright (c) 2000 - 2020 Intel Corporation | ||
12 | * | ||
13 | - * Disassembly of tests/data/acpi/virt/FACP, Mon Jan 22 13:48:40 2024 | ||
14 | + * Disassembly of /tmp/aml-W8RZH2, Mon Jan 22 13:48:40 2024 | ||
15 | * | ||
16 | * ACPI Data Table [FACP] | ||
17 | * | ||
18 | * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue | ||
19 | */ | ||
20 | |||
21 | [000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] | ||
22 | [004h 0004 4] Table Length : 00000114 | ||
23 | [008h 0008 1] Revision : 06 | ||
24 | -[009h 0009 1] Checksum : 15 | ||
25 | +[009h 0009 1] Checksum : 12 | ||
26 | [00Ah 0010 6] Oem ID : "BOCHS " | ||
27 | [010h 0016 8] Oem Table ID : "BXPC " | ||
28 | [018h 0024 4] Oem Revision : 00000001 | ||
29 | [01Ch 0028 4] Asl Compiler ID : "BXPC" | ||
30 | [020h 0032 4] Asl Compiler Revision : 00000001 | ||
31 | |||
32 | [024h 0036 4] FACS Address : 00000000 | ||
33 | [028h 0040 4] DSDT Address : 00000000 | ||
34 | [02Ch 0044 1] Model : 00 | ||
35 | [02Dh 0045 1] PM Profile : 00 [Unspecified] | ||
36 | [02Eh 0046 2] SCI Interrupt : 0000 | ||
37 | [030h 0048 4] SMI Command Port : 00000000 | ||
38 | [034h 0052 1] ACPI Enable Value : 00 | ||
39 | [035h 0053 1] ACPI Disable Value : 00 | ||
40 | [036h 0054 1] S4BIOS Command : 00 | ||
41 | [037h 0055 1] P-State Control : 00 | ||
42 | @@ -XXX,XX +XXX,XX @@ | ||
43 | Use APIC Physical Destination Mode (V4) : 0 | ||
44 | Hardware Reduced (V5) : 1 | ||
45 | Low Power S0 Idle (V5) : 0 | ||
46 | |||
47 | [074h 0116 12] Reset Register : [Generic Address Structure] | ||
48 | [074h 0116 1] Space ID : 00 [SystemMemory] | ||
49 | [075h 0117 1] Bit Width : 00 | ||
50 | [076h 0118 1] Bit Offset : 00 | ||
51 | [077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] | ||
52 | [078h 0120 8] Address : 0000000000000000 | ||
53 | |||
54 | [080h 0128 1] Value to cause reset : 00 | ||
55 | [081h 0129 2] ARM Flags (decoded below) : 0003 | ||
56 | PSCI Compliant : 1 | ||
57 | Must use HVC for PSCI : 1 | ||
58 | |||
59 | -[083h 0131 1] FADT Minor Revision : 00 | ||
60 | +[083h 0131 1] FADT Minor Revision : 03 | ||
61 | [084h 0132 8] FACS Address : 0000000000000000 | ||
62 | [08Ch 0140 8] DSDT Address : 0000000000000000 | ||
63 | [094h 0148 12] PM1A Event Block : [Generic Address Structure] | ||
64 | [094h 0148 1] Space ID : 00 [SystemMemory] | ||
65 | [095h 0149 1] Bit Width : 00 | ||
66 | [096h 0150 1] Bit Offset : 00 | ||
67 | [097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] | ||
68 | [098h 0152 8] Address : 0000000000000000 | ||
69 | |||
70 | [0A0h 0160 12] PM1B Event Block : [Generic Address Structure] | ||
71 | [0A0h 0160 1] Space ID : 00 [SystemMemory] | ||
72 | [0A1h 0161 1] Bit Width : 00 | ||
73 | [0A2h 0162 1] Bit Offset : 00 | ||
74 | [0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] | ||
75 | [0A4h 0164 8] Address : 0000000000000000 | ||
76 | |||
77 | @@ -XXX,XX +XXX,XX @@ | ||
78 | [0F5h 0245 1] Bit Width : 00 | ||
79 | [0F6h 0246 1] Bit Offset : 00 | ||
80 | [0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy] | ||
81 | [0F8h 0248 8] Address : 0000000000000000 | ||
82 | |||
83 | [100h 0256 12] Sleep Status Register : [Generic Address Structure] | ||
84 | [100h 0256 1] Space ID : 00 [SystemMemory] | ||
85 | [101h 0257 1] Bit Width : 00 | ||
86 | [102h 0258 1] Bit Offset : 00 | ||
87 | [103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy] | ||
88 | [104h 0260 8] Address : 0000000000000000 | ||
89 | |||
90 | [10Ch 0268 8] Hypervisor ID : 00000000554D4551 | ||
91 | |||
92 | Raw Table Data: Length 276 (0x114) | ||
93 | |||
94 | - 0000: 46 41 43 50 14 01 00 00 06 15 42 4F 43 48 53 20 // FACP......BOCHS | ||
95 | + 0000: 46 41 43 50 14 01 00 00 06 12 42 4F 43 48 53 20 // FACP......BOCHS | ||
96 | 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC | ||
97 | 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
98 | 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
99 | 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
100 | 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
101 | 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
102 | 0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
103 | - 0080: 00 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
104 | + 0080: 00 03 00 03 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
105 | 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
106 | 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
107 | 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
108 | 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
109 | 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
110 | 00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
111 | 00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ | ||
112 | 0100: 00 00 00 00 00 00 00 00 00 00 00 00 51 45 4D 55 // ............QEMU | ||
113 | 0110: 00 00 00 00 // .... | ||
114 | |||
115 | @@ -XXX,XX +XXX,XX @@ | ||
116 | /* | ||
117 | * Intel ACPI Component Architecture | ||
118 | * AML/ASL+ Disassembler version 20200925 (64-bit version) | ||
119 | * Copyright (c) 2000 - 2020 Intel Corporation | ||
120 | * | ||
121 | - * Disassembly of tests/data/acpi/virt/GTDT, Mon Jan 22 13:48:40 2024 | ||
122 | + * Disassembly of /tmp/aml-XDSZH2, Mon Jan 22 13:48:40 2024 | ||
123 | * | ||
124 | * ACPI Data Table [GTDT] | ||
125 | * | ||
126 | * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue | ||
127 | */ | ||
128 | |||
129 | [000h 0000 4] Signature : "GTDT" [Generic Timer Description Table] | ||
130 | -[004h 0004 4] Table Length : 00000060 | ||
131 | -[008h 0008 1] Revision : 02 | ||
132 | -[009h 0009 1] Checksum : 9C | ||
133 | +[004h 0004 4] Table Length : 00000068 | ||
134 | +[008h 0008 1] Revision : 03 | ||
135 | +[009h 0009 1] Checksum : 93 | ||
136 | [00Ah 0010 6] Oem ID : "BOCHS " | ||
137 | [010h 0016 8] Oem Table ID : "BXPC " | ||
138 | [018h 0024 4] Oem Revision : 00000001 | ||
139 | [01Ch 0028 4] Asl Compiler ID : "BXPC" | ||
140 | [020h 0032 4] Asl Compiler Revision : 00000001 | ||
141 | |||
142 | [024h 0036 8] Counter Block Address : FFFFFFFFFFFFFFFF | ||
143 | [02Ch 0044 4] Reserved : 00000000 | ||
144 | |||
145 | [030h 0048 4] Secure EL1 Interrupt : 0000001D | ||
146 | [034h 0052 4] EL1 Flags (decoded below) : 00000000 | ||
147 | Trigger Mode : 0 | ||
148 | Polarity : 0 | ||
149 | Always On : 0 | ||
150 | |||
151 | [038h 0056 4] Non-Secure EL1 Interrupt : 0000001E | ||
152 | @@ -XXX,XX +XXX,XX @@ | ||
153 | |||
154 | [040h 0064 4] Virtual Timer Interrupt : 0000001B | ||
155 | [044h 0068 4] VT Flags (decoded below) : 00000000 | ||
156 | Trigger Mode : 0 | ||
157 | Polarity : 0 | ||
158 | Always On : 0 | ||
159 | |||
160 | [048h 0072 4] Non-Secure EL2 Interrupt : 0000001A | ||
161 | [04Ch 0076 4] NEL2 Flags (decoded below) : 00000000 | ||
162 | Trigger Mode : 0 | ||
163 | Polarity : 0 | ||
164 | Always On : 0 | ||
165 | [050h 0080 8] Counter Read Block Address : FFFFFFFFFFFFFFFF | ||
166 | |||
167 | [058h 0088 4] Platform Timer Count : 00000000 | ||
168 | [05Ch 0092 4] Platform Timer Offset : 00000000 | ||
169 | +[060h 0096 4] Virtual EL2 Timer GSIV : 00000000 | ||
170 | +[064h 0100 4] Virtual EL2 Timer Flags : 00000000 | ||
171 | |||
172 | -Raw Table Data: Length 96 (0x60) | ||
173 | +Raw Table Data: Length 104 (0x68) | ||
174 | |||
175 | - 0000: 47 54 44 54 60 00 00 00 02 9C 42 4F 43 48 53 20 // GTDT`.....BOCHS | ||
176 | + 0000: 47 54 44 54 68 00 00 00 03 93 42 4F 43 48 53 20 // GTDTh.....BOCHS | ||
177 | 0010: 42 58 50 43 20 20 20 20 01 00 00 00 42 58 50 43 // BXPC ....BXPC | ||
178 | 0020: 01 00 00 00 FF FF FF FF FF FF FF FF 00 00 00 00 // ................ | ||
179 | 0030: 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00 // ................ | ||
180 | 0040: 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 // ................ | ||
181 | 0050: FF FF FF FF FF FF FF FF 00 00 00 00 00 00 00 00 // ................ | ||
182 | + 0060: 00 00 00 00 00 00 00 00 // ........ | ||
183 | |||
184 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
185 | Reviewed-by: Ard Biesheuvel <ardb@kernel.org> | ||
186 | Message-id: 20240122143537.233498-4-peter.maydell@linaro.org | ||
187 | --- | ||
188 | tests/qtest/bios-tables-test-allowed-diff.h | 2 -- | ||
189 | tests/data/acpi/virt/FACP | Bin 276 -> 276 bytes | ||
190 | tests/data/acpi/virt/GTDT | Bin 96 -> 104 bytes | ||
191 | 3 files changed, 2 deletions(-) | ||
192 | |||
193 | diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h | ||
194 | index XXXXXXX..XXXXXXX 100644 | ||
195 | --- a/tests/qtest/bios-tables-test-allowed-diff.h | ||
196 | +++ b/tests/qtest/bios-tables-test-allowed-diff.h | ||
197 | @@ -1,3 +1 @@ | ||
198 | /* List of comma-separated changed AML files to ignore */ | ||
199 | -"tests/data/acpi/virt/FACP", | ||
200 | -"tests/data/acpi/virt/GTDT", | ||
201 | diff --git a/tests/data/acpi/virt/FACP b/tests/data/acpi/virt/FACP | ||
202 | index XXXXXXX..XXXXXXX 100644 | ||
203 | GIT binary patch | ||
204 | delta 25 | ||
205 | gcmbQjG=+)F&CxkPgpq-PO=u!l<;2F$$vli407<0<)c^nh | ||
206 | |||
207 | delta 28 | ||
208 | kcmbQjG=+)F&CxkPgpq-PO>`nx<-|!<6Akz$^DuG%0AAS!ssI20 | ||
209 | |||
210 | diff --git a/tests/data/acpi/virt/GTDT b/tests/data/acpi/virt/GTDT | ||
211 | index XXXXXXX..XXXXXXX 100644 | ||
212 | GIT binary patch | ||
213 | delta 25 | ||
214 | bcmYeu;BpUf3CUn!U|^m+kt>V?$N&QXMtB4L | ||
215 | |||
216 | delta 16 | ||
217 | Xcmc~u;BpUf2}xjJU|^avkt+-UB60)u | ||
218 | |||
219 | -- | ||
220 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The patchset adding the GMAC ethernet to this SoC crossed in the | ||
2 | mail with the patchset cleaning up the NIC handling. When we | ||
3 | create the GMAC modules we must call qemu_configure_nic_device() | ||
4 | so that the user has the opportunity to use the -nic commandline | ||
5 | option to create a network backend and connect it to the GMACs. | ||
1 | 6 | ||
7 | Add the missing call. | ||
8 | |||
9 | Fixes: 21e5326a7c ("hw/arm: Add GMAC devices to NPCM7XX SoC") | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Reviewed-by: David Woodhouse <dwmw@amazon.co.uk> | ||
12 | Message-id: 20240206171231.396392-2-peter.maydell@linaro.org | ||
13 | --- | ||
14 | hw/arm/npcm7xx.c | 1 + | ||
15 | 1 file changed, 1 insertion(+) | ||
16 | |||
17 | diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c | ||
18 | index XXXXXXX..XXXXXXX 100644 | ||
19 | --- a/hw/arm/npcm7xx.c | ||
20 | +++ b/hw/arm/npcm7xx.c | ||
21 | @@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) | ||
22 | for (i = 0; i < ARRAY_SIZE(s->gmac); i++) { | ||
23 | SysBusDevice *sbd = SYS_BUS_DEVICE(&s->gmac[i]); | ||
24 | |||
25 | + qemu_configure_nic_device(DEVICE(sbd), false, NULL); | ||
26 | /* | ||
27 | * The device exists regardless of whether it's connected to a QEMU | ||
28 | * netdev backend. So always instantiate it even if there is no | ||
29 | -- | ||
30 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Currently QEMU will warn if there is a NIC on the board that | ||
2 | is not connected to a backend. By default the '-nic user' will | ||
3 | get used for all NICs, but if you manually connect a specific | ||
4 | NIC to a specific backend, then the other NICs on the board | ||
5 | have no backend and will be warned about: | ||
1 | 6 | ||
7 | qemu-system-arm: warning: nic npcm7xx-emc.1 has no peer | ||
8 | qemu-system-arm: warning: nic npcm-gmac.0 has no peer | ||
9 | qemu-system-arm: warning: nic npcm-gmac.1 has no peer | ||
10 | |||
11 | So suppress those warnings by manually connecting every NIC | ||
12 | on the board to some backend. | ||
13 | |||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | Reviewed-by: David Woodhouse <dwmw@amazon.co.uk> | ||
16 | Reviewed-by: Thomas Huth <thuth@redhat.com> | ||
17 | Message-id: 20240206171231.396392-3-peter.maydell@linaro.org | ||
18 | --- | ||
19 | tests/qtest/npcm7xx_emc-test.c | 5 ++++- | ||
20 | 1 file changed, 4 insertions(+), 1 deletion(-) | ||
21 | |||
22 | diff --git a/tests/qtest/npcm7xx_emc-test.c b/tests/qtest/npcm7xx_emc-test.c | ||
23 | index XXXXXXX..XXXXXXX 100644 | ||
24 | --- a/tests/qtest/npcm7xx_emc-test.c | ||
25 | +++ b/tests/qtest/npcm7xx_emc-test.c | ||
26 | @@ -XXX,XX +XXX,XX @@ static int *packet_test_init(int module_num, GString *cmd_line) | ||
27 | * KISS and use -nic. The driver accepts 'emc0' and 'emc1' as aliases | ||
28 | * in the 'model' field to specify the device to match. | ||
29 | */ | ||
30 | - g_string_append_printf(cmd_line, " -nic socket,fd=%d,model=emc%d ", | ||
31 | + g_string_append_printf(cmd_line, " -nic socket,fd=%d,model=emc%d " | ||
32 | + "-nic user,model=npcm7xx-emc " | ||
33 | + "-nic user,model=npcm-gmac " | ||
34 | + "-nic user,model=npcm-gmac", | ||
35 | test_sockets[1], module_num); | ||
36 | |||
37 | g_test_queue_destroy(packet_test_clear, test_sockets); | ||
38 | -- | ||
39 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | It doesn't make sense to read the value of MDCR_EL2 on a non-A-profile |
---|---|---|---|
2 | CPU, and in fact if you try to do it we will assert: | ||
2 | 3 | ||
3 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 4 | #6 0x00007ffff4b95e96 in __GI___assert_fail |
4 | Message-id: 20190301200501.16533-4-richard.henderson@linaro.org | 5 | (assertion=0x5555565a8c70 "!arm_feature(env, ARM_FEATURE_M)", file=0x5555565a6e5c "../../target/arm/helper.c", line=12600, function=0x5555565a9560 <__PRETTY_FUNCTION__.0> "arm_security_space_below_el3") at ./assert/assert.c:101 |
5 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | #7 0x0000555555ebf412 in arm_security_space_below_el3 (env=0x555557bc8190) at ../../target/arm/helper.c:12600 |
7 | #8 0x0000555555ea6f89 in arm_is_el2_enabled (env=0x555557bc8190) at ../../target/arm/cpu.h:2595 | ||
8 | #9 0x0000555555ea942f in arm_mdcr_el2_eff (env=0x555557bc8190) at ../../target/arm/internals.h:1512 | ||
9 | |||
10 | We might call pmu_counter_enabled() on an M-profile CPU (for example | ||
11 | from the migration pre/post hooks in machine.c); this should always | ||
12 | return false because these CPUs don't set ARM_FEATURE_PMU. | ||
13 | |||
14 | Avoid the assertion by not calling arm_mdcr_el2_eff() before we | ||
15 | have done the early return for "PMU not present". | ||
16 | |||
17 | This fixes an assertion failure if you try to do a loadvm or | ||
18 | savevm for an M-profile board. | ||
19 | |||
20 | Cc: qemu-stable@nongnu.org | ||
21 | Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2155 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 22 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
23 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
24 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
25 | Message-id: 20240208153346.970021-1-peter.maydell@linaro.org | ||
7 | --- | 26 | --- |
8 | target/arm/cpu.h | 13 ++++++++++- | 27 | target/arm/helper.c | 12 ++++++++++-- |
9 | target/arm/cpu.c | 1 + | 28 | 1 file changed, 10 insertions(+), 2 deletions(-) |
10 | target/arm/cpu64.c | 2 ++ | ||
11 | target/arm/helper.c | 55 +++++++++++++++++++++++++++++++++++++++++++++ | ||
12 | 4 files changed, 70 insertions(+), 1 deletion(-) | ||
13 | 29 | ||
14 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
15 | index XXXXXXX..XXXXXXX 100644 | ||
16 | --- a/target/arm/cpu.h | ||
17 | +++ b/target/arm/cpu.h | ||
18 | @@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu); | ||
19 | #define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */ | ||
20 | #define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */ | ||
21 | #define SCTLR_F (1U << 10) /* up to v6 */ | ||
22 | -#define SCTLR_SW (1U << 10) /* v7, RES0 in v8 */ | ||
23 | +#define SCTLR_SW (1U << 10) /* v7 */ | ||
24 | +#define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */ | ||
25 | #define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */ | ||
26 | #define SCTLR_EOS (1U << 11) /* v8.5-ExS */ | ||
27 | #define SCTLR_I (1U << 12) | ||
28 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_sb(const ARMISARegisters *id) | ||
29 | return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0; | ||
30 | } | ||
31 | |||
32 | +static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id) | ||
33 | +{ | ||
34 | + return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0; | ||
35 | +} | ||
36 | + | ||
37 | static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) | ||
38 | { | ||
39 | /* | ||
40 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_sb(const ARMISARegisters *id) | ||
41 | return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0; | ||
42 | } | ||
43 | |||
44 | +static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) | ||
45 | +{ | ||
46 | + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; | ||
47 | +} | ||
48 | + | ||
49 | static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) | ||
50 | { | ||
51 | /* We always set the AdvSIMD and FP fields identically wrt FP16. */ | ||
52 | diff --git a/target/arm/cpu.c b/target/arm/cpu.c | ||
53 | index XXXXXXX..XXXXXXX 100644 | ||
54 | --- a/target/arm/cpu.c | ||
55 | +++ b/target/arm/cpu.c | ||
56 | @@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj) | ||
57 | t = FIELD_DP32(t, ID_ISAR6, DP, 1); | ||
58 | t = FIELD_DP32(t, ID_ISAR6, FHM, 1); | ||
59 | t = FIELD_DP32(t, ID_ISAR6, SB, 1); | ||
60 | + t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1); | ||
61 | cpu->isar.id_isar6 = t; | ||
62 | |||
63 | t = cpu->id_mmfr4; | ||
64 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
65 | index XXXXXXX..XXXXXXX 100644 | ||
66 | --- a/target/arm/cpu64.c | ||
67 | +++ b/target/arm/cpu64.c | ||
68 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
69 | t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1); | ||
70 | t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0); | ||
71 | t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); | ||
72 | + t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); | ||
73 | cpu->isar.id_aa64isar1 = t; | ||
74 | |||
75 | t = cpu->isar.id_aa64pfr0; | ||
76 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
77 | u = FIELD_DP32(u, ID_ISAR6, DP, 1); | ||
78 | u = FIELD_DP32(u, ID_ISAR6, FHM, 1); | ||
79 | u = FIELD_DP32(u, ID_ISAR6, SB, 1); | ||
80 | + u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1); | ||
81 | cpu->isar.id_isar6 = u; | ||
82 | |||
83 | /* | ||
84 | diff --git a/target/arm/helper.c b/target/arm/helper.c | 30 | diff --git a/target/arm/helper.c b/target/arm/helper.c |
85 | index XXXXXXX..XXXXXXX 100644 | 31 | index XXXXXXX..XXXXXXX 100644 |
86 | --- a/target/arm/helper.c | 32 | --- a/target/arm/helper.c |
87 | +++ b/target/arm/helper.c | 33 | +++ b/target/arm/helper.c |
88 | @@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pauth_reginfo[] = { | 34 | @@ -XXX,XX +XXX,XX @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) |
89 | }; | 35 | bool enabled, prohibited = false, filtered; |
90 | #endif | 36 | bool secure = arm_is_secure(env); |
91 | 37 | int el = arm_current_el(env); | |
92 | +static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri, | 38 | - uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); |
93 | + bool isread) | 39 | - uint8_t hpmn = mdcr_el2 & MDCR_HPMN; |
94 | +{ | 40 | + uint64_t mdcr_el2; |
95 | + int el = arm_current_el(env); | 41 | + uint8_t hpmn; |
42 | |||
43 | + /* | ||
44 | + * We might be called for M-profile cores where MDCR_EL2 doesn't | ||
45 | + * exist and arm_mdcr_el2_eff() will assert, so this early-exit check | ||
46 | + * must be before we read that value. | ||
47 | + */ | ||
48 | if (!arm_feature(env, ARM_FEATURE_PMU)) { | ||
49 | return false; | ||
50 | } | ||
51 | |||
52 | + mdcr_el2 = arm_mdcr_el2_eff(env); | ||
53 | + hpmn = mdcr_el2 & MDCR_HPMN; | ||
96 | + | 54 | + |
97 | + if (el == 0) { | 55 | if (!arm_feature(env, ARM_FEATURE_EL2) || |
98 | + uint64_t sctlr = arm_sctlr(env, el); | 56 | (counter < hpmn || counter == 31)) { |
99 | + if (!(sctlr & SCTLR_EnRCTX)) { | 57 | e = env->cp15.c9_pmcr & PMCRE; |
100 | + return CP_ACCESS_TRAP; | ||
101 | + } | ||
102 | + } else if (el == 1) { | ||
103 | + uint64_t hcr = arm_hcr_el2_eff(env); | ||
104 | + if (hcr & HCR_NV) { | ||
105 | + return CP_ACCESS_TRAP_EL2; | ||
106 | + } | ||
107 | + } | ||
108 | + return CP_ACCESS_OK; | ||
109 | +} | ||
110 | + | ||
111 | +static const ARMCPRegInfo predinv_reginfo[] = { | ||
112 | + { .name = "CFP_RCTX", .state = ARM_CP_STATE_AA64, | ||
113 | + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 4, | ||
114 | + .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | ||
115 | + { .name = "DVP_RCTX", .state = ARM_CP_STATE_AA64, | ||
116 | + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 5, | ||
117 | + .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | ||
118 | + { .name = "CPP_RCTX", .state = ARM_CP_STATE_AA64, | ||
119 | + .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 7, | ||
120 | + .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | ||
121 | + /* | ||
122 | + * Note the AArch32 opcodes have a different OPC1. | ||
123 | + */ | ||
124 | + { .name = "CFPRCTX", .state = ARM_CP_STATE_AA32, | ||
125 | + .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 4, | ||
126 | + .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | ||
127 | + { .name = "DVPRCTX", .state = ARM_CP_STATE_AA32, | ||
128 | + .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 5, | ||
129 | + .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | ||
130 | + { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32, | ||
131 | + .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7, | ||
132 | + .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv }, | ||
133 | + REGINFO_SENTINEL | ||
134 | +}; | ||
135 | + | ||
136 | void register_cp_regs_for_features(ARMCPU *cpu) | ||
137 | { | ||
138 | /* Register all the coprocessor registers based on feature bits */ | ||
139 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
140 | define_arm_cp_regs(cpu, pauth_reginfo); | ||
141 | } | ||
142 | #endif | ||
143 | + | ||
144 | + /* | ||
145 | + * While all v8.0 cpus support aarch64, QEMU does have configurations | ||
146 | + * that do not set ID_AA64ISAR1, e.g. user-only qemu-arm -cpu max, | ||
147 | + * which will set ID_ISAR6. | ||
148 | + */ | ||
149 | + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) | ||
150 | + ? cpu_isar_feature(aa64_predinv, cpu) | ||
151 | + : cpu_isar_feature(aa32_predinv, cpu)) { | ||
152 | + define_arm_cp_regs(cpu, predinv_reginfo); | ||
153 | + } | ||
154 | } | ||
155 | |||
156 | void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) | ||
157 | -- | 58 | -- |
158 | 2.20.1 | 59 | 2.34.1 |
159 | 60 | ||
160 | 61 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Nabih Estefan <nabihestefan@google.com> |
---|---|---|---|
2 | 2 | ||
3 | This decoding more closely matches the ARMv8.4 Table C4-6, | 3 | Fix the nocm_gmac-test.c file to run on a nuvoton 7xx machine instead |
4 | Encoding table for Data Processing - Register Group. | 4 | of 8xx. Also fix comments referencing this and values expecting 8xx. |
5 | 5 | ||
6 | In particular, op2 == 0 is now more than just Add/sub (with carry). | 6 | Change-Id: Iabd0fba14910c3f1e883c4a9521350f3db9ffab8 |
7 | 7 | Signed-Off-By: Nabih Estefan <nabihestefan@google.com> | |
8 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Reviewed-by: Tyrone Ting <kfting@nuvoton.com> |
9 | Message-id: 20190301200501.16533-7-richard.henderson@linaro.org | 9 | Message-id: 20240208194759.2858582-2-nabihestefan@google.com |
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
11 | [PMM: commit message tweaks] | ||
11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
12 | --- | 13 | --- |
13 | target/arm/translate-a64.c | 98 ++++++++++++++++++++++---------------- | 14 | tests/qtest/npcm_gmac-test.c | 84 +----------------------------------- |
14 | 1 file changed, 57 insertions(+), 41 deletions(-) | 15 | tests/qtest/meson.build | 3 +- |
16 | 2 files changed, 4 insertions(+), 83 deletions(-) | ||
15 | 17 | ||
16 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 18 | diff --git a/tests/qtest/npcm_gmac-test.c b/tests/qtest/npcm_gmac-test.c |
17 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/translate-a64.c | 20 | --- a/tests/qtest/npcm_gmac-test.c |
19 | +++ b/target/arm/translate-a64.c | 21 | +++ b/tests/qtest/npcm_gmac-test.c |
20 | @@ -XXX,XX +XXX,XX @@ static void disas_data_proc_3src(DisasContext *s, uint32_t insn) | 22 | @@ -XXX,XX +XXX,XX @@ typedef struct TestData { |
23 | const GMACModule *module; | ||
24 | } TestData; | ||
25 | |||
26 | -/* Values extracted from hw/arm/npcm8xx.c */ | ||
27 | +/* Values extracted from hw/arm/npcm7xx.c */ | ||
28 | static const GMACModule gmac_module_list[] = { | ||
29 | { | ||
30 | .irq = 14, | ||
31 | @@ -XXX,XX +XXX,XX @@ static const GMACModule gmac_module_list[] = { | ||
32 | .irq = 15, | ||
33 | .base_addr = 0xf0804000 | ||
34 | }, | ||
35 | - { | ||
36 | - .irq = 16, | ||
37 | - .base_addr = 0xf0806000 | ||
38 | - }, | ||
39 | - { | ||
40 | - .irq = 17, | ||
41 | - .base_addr = 0xf0808000 | ||
42 | - } | ||
43 | }; | ||
44 | |||
45 | /* Returns the index of the GMAC module. */ | ||
46 | @@ -XXX,XX +XXX,XX @@ static uint32_t gmac_read(QTestState *qts, const GMACModule *mod, | ||
47 | return qtest_readl(qts, mod->base_addr + regno); | ||
21 | } | 48 | } |
22 | 49 | ||
23 | /* Add/subtract (with carry) | 50 | -static uint16_t pcs_read(QTestState *qts, const GMACModule *mod, |
24 | - * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0 | 51 | - NPCMRegister regno) |
25 | - * +--+--+--+------------------------+------+---------+------+-----+ | 52 | -{ |
26 | - * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd | | 53 | - uint32_t write_value = (regno & 0x3ffe00) >> 9; |
27 | - * +--+--+--+------------------------+------+---------+------+-----+ | 54 | - qtest_writel(qts, PCS_BASE_ADDRESS + NPCM_PCS_IND_AC_BA, write_value); |
28 | - * [000000] | 55 | - uint32_t read_offset = regno & 0x1ff; |
29 | + * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0 | 56 | - return qtest_readl(qts, PCS_BASE_ADDRESS + read_offset); |
30 | + * +--+--+--+------------------------+------+-------------+------+-----+ | 57 | -} |
31 | + * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd | | 58 | - |
32 | + * +--+--+--+------------------------+------+-------------+------+-----+ | 59 | /* Check that GMAC registers are reset to default value */ |
33 | */ | 60 | static void test_init(gconstpointer test_data) |
34 | 61 | { | |
35 | static void disas_adc_sbc(DisasContext *s, uint32_t insn) | 62 | const TestData *td = test_data; |
36 | @@ -XXX,XX +XXX,XX @@ static void disas_adc_sbc(DisasContext *s, uint32_t insn) | 63 | const GMACModule *mod = td->module; |
37 | unsigned int sf, op, setflags, rm, rn, rd; | 64 | - QTestState *qts = qtest_init("-machine npcm845-evb"); |
38 | TCGv_i64 tcg_y, tcg_rn, tcg_rd; | 65 | + QTestState *qts = qtest_init("-machine npcm750-evb"); |
39 | 66 | ||
40 | - if (extract32(insn, 10, 6) != 0) { | 67 | #define CHECK_REG32(regno, value) \ |
41 | - unallocated_encoding(s); | 68 | do { \ |
42 | - return; | 69 | g_assert_cmphex(gmac_read(qts, mod, (regno)), ==, (value)); \ |
70 | } while (0) | ||
71 | |||
72 | -#define CHECK_REG_PCS(regno, value) \ | ||
73 | - do { \ | ||
74 | - g_assert_cmphex(pcs_read(qts, mod, (regno)), ==, (value)); \ | ||
75 | - } while (0) | ||
76 | - | ||
77 | CHECK_REG32(NPCM_DMA_BUS_MODE, 0x00020100); | ||
78 | CHECK_REG32(NPCM_DMA_XMT_POLL_DEMAND, 0); | ||
79 | CHECK_REG32(NPCM_DMA_RCV_POLL_DEMAND, 0); | ||
80 | @@ -XXX,XX +XXX,XX @@ static void test_init(gconstpointer test_data) | ||
81 | CHECK_REG32(NPCM_GMAC_PTP_TAR, 0); | ||
82 | CHECK_REG32(NPCM_GMAC_PTP_TTSR, 0); | ||
83 | |||
84 | - /* TODO Add registers PCS */ | ||
85 | - if (mod->base_addr == 0xf0802000) { | ||
86 | - CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID1, 0x699e); | ||
87 | - CHECK_REG_PCS(NPCM_PCS_SR_CTL_ID2, 0); | ||
88 | - CHECK_REG_PCS(NPCM_PCS_SR_CTL_STS, 0x8000); | ||
89 | - | ||
90 | - CHECK_REG_PCS(NPCM_PCS_SR_MII_CTRL, 0x1140); | ||
91 | - CHECK_REG_PCS(NPCM_PCS_SR_MII_STS, 0x0109); | ||
92 | - CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID1, 0x699e); | ||
93 | - CHECK_REG_PCS(NPCM_PCS_SR_MII_DEV_ID2, 0x0ced0); | ||
94 | - CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_ADV, 0x0020); | ||
95 | - CHECK_REG_PCS(NPCM_PCS_SR_MII_LP_BABL, 0); | ||
96 | - CHECK_REG_PCS(NPCM_PCS_SR_MII_AN_EXPN, 0); | ||
97 | - CHECK_REG_PCS(NPCM_PCS_SR_MII_EXT_STS, 0xc000); | ||
98 | - | ||
99 | - CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_ABL, 0x0003); | ||
100 | - CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_LWR, 0x0038); | ||
101 | - CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MAX_DLY_UPR, 0); | ||
102 | - CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_LWR, 0x0038); | ||
103 | - CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_TX_MIN_DLY_UPR, 0); | ||
104 | - CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_LWR, 0x0058); | ||
105 | - CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MAX_DLY_UPR, 0); | ||
106 | - CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_LWR, 0x0048); | ||
107 | - CHECK_REG_PCS(NPCM_PCS_SR_TIM_SYNC_RX_MIN_DLY_UPR, 0); | ||
108 | - | ||
109 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MMD_DIG_CTRL1, 0x2400); | ||
110 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_CTRL, 0); | ||
111 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_AN_INTR_STS, 0x000a); | ||
112 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_TC, 0); | ||
113 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_DBG_CTRL, 0); | ||
114 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL0, 0x899c); | ||
115 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_TXTIMER, 0); | ||
116 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_RXTIMER, 0); | ||
117 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_LINK_TIMER_CTRL, 0); | ||
118 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_EEE_MCTRL1, 0); | ||
119 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_STS, 0x0010); | ||
120 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_ICG_ERRCNT1, 0); | ||
121 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MISC_STS, 0); | ||
122 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_RX_LSTS, 0); | ||
123 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_BSTCTRL0, 0x00a); | ||
124 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_LVLCTRL0, 0x007f); | ||
125 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL0, 0x0001); | ||
126 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_GENCTRL1, 0); | ||
127 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_TX_STS, 0); | ||
128 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL0, 0x0100); | ||
129 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_GENCTRL1, 0x1100); | ||
130 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_RX_LOS_CTRL0, 0x000e); | ||
131 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL0, 0x0100); | ||
132 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_CTRL1, 0x0032); | ||
133 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MPLL_STS, 0x0001); | ||
134 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL2, 0); | ||
135 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_LVL_CTRL, 0x0019); | ||
136 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL0, 0); | ||
137 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_MP_MISC_CTRL1, 0); | ||
138 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_CTRL2, 0); | ||
139 | - CHECK_REG_PCS(NPCM_PCS_VR_MII_DIG_ERRCNT_SEL, 0); | ||
43 | - } | 140 | - } |
44 | - | 141 | - |
45 | sf = extract32(insn, 31, 1); | 142 | qtest_quit(qts); |
46 | op = extract32(insn, 30, 1); | ||
47 | setflags = extract32(insn, 29, 1); | ||
48 | @@ -XXX,XX +XXX,XX @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn) | ||
49 | } | ||
50 | } | 143 | } |
51 | 144 | ||
52 | -/* Data processing - register */ | 145 | diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build |
53 | +/* | 146 | index XXXXXXX..XXXXXXX 100644 |
54 | + * Data processing - register | 147 | --- a/tests/qtest/meson.build |
55 | + * 31 30 29 28 25 21 20 16 10 0 | 148 | +++ b/tests/qtest/meson.build |
56 | + * +--+---+--+---+-------+-----+-------+-------+---------+ | 149 | @@ -XXX,XX +XXX,XX @@ qtests_npcm7xx = \ |
57 | + * | |op0| |op1| 1 0 1 | op2 | | op3 | | | 150 | 'npcm7xx_sdhci-test', |
58 | + * +--+---+--+---+-------+-----+-------+-------+---------+ | 151 | 'npcm7xx_smbus-test', |
59 | + */ | 152 | 'npcm7xx_timer-test', |
60 | static void disas_data_proc_reg(DisasContext *s, uint32_t insn) | 153 | - 'npcm7xx_watchdog_timer-test'] + \ |
61 | { | 154 | + 'npcm7xx_watchdog_timer-test', |
62 | - switch (extract32(insn, 24, 5)) { | 155 | + 'npcm_gmac-test'] + \ |
63 | - case 0x0a: /* Logical (shifted register) */ | 156 | (slirp.found() ? ['npcm7xx_emc-test'] : []) |
64 | - disas_logic_reg(s, insn); | 157 | qtests_aspeed = \ |
65 | - break; | 158 | ['aspeed_hace-test', |
66 | - case 0x0b: /* Add/subtract */ | ||
67 | - if (insn & (1 << 21)) { /* (extended register) */ | ||
68 | - disas_add_sub_ext_reg(s, insn); | ||
69 | + int op0 = extract32(insn, 30, 1); | ||
70 | + int op1 = extract32(insn, 28, 1); | ||
71 | + int op2 = extract32(insn, 21, 4); | ||
72 | + int op3 = extract32(insn, 10, 6); | ||
73 | + | ||
74 | + if (!op1) { | ||
75 | + if (op2 & 8) { | ||
76 | + if (op2 & 1) { | ||
77 | + /* Add/sub (extended register) */ | ||
78 | + disas_add_sub_ext_reg(s, insn); | ||
79 | + } else { | ||
80 | + /* Add/sub (shifted register) */ | ||
81 | + disas_add_sub_reg(s, insn); | ||
82 | + } | ||
83 | } else { | ||
84 | - disas_add_sub_reg(s, insn); | ||
85 | + /* Logical (shifted register) */ | ||
86 | + disas_logic_reg(s, insn); | ||
87 | } | ||
88 | - break; | ||
89 | - case 0x1b: /* Data-processing (3 source) */ | ||
90 | - disas_data_proc_3src(s, insn); | ||
91 | - break; | ||
92 | - case 0x1a: | ||
93 | - switch (extract32(insn, 21, 3)) { | ||
94 | - case 0x0: /* Add/subtract (with carry) */ | ||
95 | + return; | ||
96 | + } | ||
97 | + | ||
98 | + switch (op2) { | ||
99 | + case 0x0: | ||
100 | + switch (op3) { | ||
101 | + case 0x00: /* Add/subtract (with carry) */ | ||
102 | disas_adc_sbc(s, insn); | ||
103 | break; | ||
104 | - case 0x2: /* Conditional compare */ | ||
105 | - disas_cc(s, insn); /* both imm and reg forms */ | ||
106 | - break; | ||
107 | - case 0x4: /* Conditional select */ | ||
108 | - disas_cond_select(s, insn); | ||
109 | - break; | ||
110 | - case 0x6: /* Data-processing */ | ||
111 | - if (insn & (1 << 30)) { /* (1 source) */ | ||
112 | - disas_data_proc_1src(s, insn); | ||
113 | - } else { /* (2 source) */ | ||
114 | - disas_data_proc_2src(s, insn); | ||
115 | - } | ||
116 | - break; | ||
117 | + | ||
118 | default: | ||
119 | - unallocated_encoding(s); | ||
120 | - break; | ||
121 | + goto do_unallocated; | ||
122 | } | ||
123 | break; | ||
124 | + | ||
125 | + case 0x2: /* Conditional compare */ | ||
126 | + disas_cc(s, insn); /* both imm and reg forms */ | ||
127 | + break; | ||
128 | + | ||
129 | + case 0x4: /* Conditional select */ | ||
130 | + disas_cond_select(s, insn); | ||
131 | + break; | ||
132 | + | ||
133 | + case 0x6: /* Data-processing */ | ||
134 | + if (op0) { /* (1 source) */ | ||
135 | + disas_data_proc_1src(s, insn); | ||
136 | + } else { /* (2 source) */ | ||
137 | + disas_data_proc_2src(s, insn); | ||
138 | + } | ||
139 | + break; | ||
140 | + case 0x8 ... 0xf: /* (3 source) */ | ||
141 | + disas_data_proc_3src(s, insn); | ||
142 | + break; | ||
143 | + | ||
144 | default: | ||
145 | + do_unallocated: | ||
146 | unallocated_encoding(s); | ||
147 | break; | ||
148 | } | ||
149 | -- | 159 | -- |
150 | 2.20.1 | 160 | 2.34.1 |
151 | |||
152 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | From: Luc Michel <luc.michel@amd.com> | ||
1 | 2 | ||
3 | An access fault is raised when the Access Flag is not set in the | ||
4 | looked-up PTE and the AFFD field is not set in the corresponding context | ||
5 | descriptor. This was already implemented for stage 2. Implement it for | ||
6 | stage 1 as well. | ||
7 | |||
8 | Signed-off-by: Luc Michel <luc.michel@amd.com> | ||
9 | Reviewed-by: Mostafa Saleh <smostafa@google.com> | ||
10 | Reviewed-by: Eric Auger <eric.auger@redhat.com> | ||
11 | Tested-by: Mostafa Saleh <smostafa@google.com> | ||
12 | Message-id: 20240213082211.3330400-1-luc.michel@amd.com | ||
13 | [PMM: tweaked comment text] | ||
14 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | --- | ||
16 | hw/arm/smmuv3-internal.h | 1 + | ||
17 | include/hw/arm/smmu-common.h | 1 + | ||
18 | hw/arm/smmu-common.c | 11 +++++++++++ | ||
19 | hw/arm/smmuv3.c | 1 + | ||
20 | 4 files changed, 14 insertions(+) | ||
21 | |||
22 | diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h | ||
23 | index XXXXXXX..XXXXXXX 100644 | ||
24 | --- a/hw/arm/smmuv3-internal.h | ||
25 | +++ b/hw/arm/smmuv3-internal.h | ||
26 | @@ -XXX,XX +XXX,XX @@ static inline int pa_range(STE *ste) | ||
27 | #define CD_EPD(x, sel) extract32((x)->word[0], (16 * (sel)) + 14, 1) | ||
28 | #define CD_ENDI(x) extract32((x)->word[0], 15, 1) | ||
29 | #define CD_IPS(x) extract32((x)->word[1], 0 , 3) | ||
30 | +#define CD_AFFD(x) extract32((x)->word[1], 3 , 1) | ||
31 | #define CD_TBI(x) extract32((x)->word[1], 6 , 2) | ||
32 | #define CD_HD(x) extract32((x)->word[1], 10 , 1) | ||
33 | #define CD_HA(x) extract32((x)->word[1], 11 , 1) | ||
34 | diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h | ||
35 | index XXXXXXX..XXXXXXX 100644 | ||
36 | --- a/include/hw/arm/smmu-common.h | ||
37 | +++ b/include/hw/arm/smmu-common.h | ||
38 | @@ -XXX,XX +XXX,XX @@ typedef struct SMMUTransCfg { | ||
39 | bool disabled; /* smmu is disabled */ | ||
40 | bool bypassed; /* translation is bypassed */ | ||
41 | bool aborted; /* translation is aborted */ | ||
42 | + bool affd; /* AF fault disable */ | ||
43 | uint32_t iotlb_hits; /* counts IOTLB hits */ | ||
44 | uint32_t iotlb_misses; /* counts IOTLB misses*/ | ||
45 | /* Used by stage-1 only. */ | ||
46 | diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c | ||
47 | index XXXXXXX..XXXXXXX 100644 | ||
48 | --- a/hw/arm/smmu-common.c | ||
49 | +++ b/hw/arm/smmu-common.c | ||
50 | @@ -XXX,XX +XXX,XX @@ static int smmu_ptw_64_s1(SMMUTransCfg *cfg, | ||
51 | pte_addr, pte, iova, gpa, | ||
52 | block_size >> 20); | ||
53 | } | ||
54 | + | ||
55 | + /* | ||
56 | + * QEMU does not currently implement HTTU, so if AFFD and PTE.AF | ||
57 | + * are 0 we take an Access flag fault. (5.4. Context Descriptor) | ||
58 | + * An Access flag fault takes priority over a Permission fault. | ||
59 | + */ | ||
60 | + if (!PTE_AF(pte) && !cfg->affd) { | ||
61 | + info->type = SMMU_PTW_ERR_ACCESS; | ||
62 | + goto error; | ||
63 | + } | ||
64 | + | ||
65 | ap = PTE_AP(pte); | ||
66 | if (is_permission_fault(ap, perm)) { | ||
67 | info->type = SMMU_PTW_ERR_PERMISSION; | ||
68 | diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c | ||
69 | index XXXXXXX..XXXXXXX 100644 | ||
70 | --- a/hw/arm/smmuv3.c | ||
71 | +++ b/hw/arm/smmuv3.c | ||
72 | @@ -XXX,XX +XXX,XX @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event) | ||
73 | cfg->oas = MIN(oas2bits(SMMU_IDR5_OAS), cfg->oas); | ||
74 | cfg->tbi = CD_TBI(cd); | ||
75 | cfg->asid = CD_ASID(cd); | ||
76 | + cfg->affd = CD_AFFD(cd); | ||
77 | |||
78 | trace_smmuv3_decode_cd(cfg->oas); | ||
79 | |||
80 | -- | ||
81 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | On ARM, the kvm_type will be resolved by querying the KVMState. | 3 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
4 | Let's add the MachineState handle to the callback so that we | ||
5 | can retrieve the KVMState handle. in kvm_init, when the callback | ||
6 | is called, the kvm_state variable is not yet set. | ||
7 | |||
8 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
9 | Acked-by: David Gibson <david@gibson.dropbear.id.au> | ||
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 4 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | 5 | Message-id: 20240213155214.13619-2-philmd@linaro.org |
12 | Message-id: 20190304101339.25970-5-eric.auger@redhat.com | ||
13 | [ppc parts] | ||
14 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
15 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | ||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
17 | --- | 7 | --- |
18 | include/hw/boards.h | 5 ++++- | 8 | hw/arm/stellaris.c | 6 ++++-- |
19 | accel/kvm/kvm-all.c | 2 +- | 9 | 1 file changed, 4 insertions(+), 2 deletions(-) |
20 | hw/ppc/mac_newworld.c | 3 +-- | ||
21 | hw/ppc/mac_oldworld.c | 2 +- | ||
22 | hw/ppc/spapr.c | 2 +- | ||
23 | 5 files changed, 8 insertions(+), 6 deletions(-) | ||
24 | 10 | ||
25 | diff --git a/include/hw/boards.h b/include/hw/boards.h | 11 | diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c |
26 | index XXXXXXX..XXXXXXX 100644 | 12 | index XXXXXXX..XXXXXXX 100644 |
27 | --- a/include/hw/boards.h | 13 | --- a/hw/arm/stellaris.c |
28 | +++ b/include/hw/boards.h | 14 | +++ b/hw/arm/stellaris.c |
29 | @@ -XXX,XX +XXX,XX @@ typedef struct { | 15 | @@ -XXX,XX +XXX,XX @@ static void stellaris_adc_trigger(void *opaque, int irq, int level) |
30 | * should instead use "unimplemented-device" for all memory ranges where | ||
31 | * the guest will attempt to probe for a device that QEMU doesn't | ||
32 | * implement and a stub device is required. | ||
33 | + * @kvm_type: | ||
34 | + * Return the type of KVM corresponding to the kvm-type string option or | ||
35 | + * computed based on other criteria such as the host kernel capabilities. | ||
36 | */ | ||
37 | struct MachineClass { | ||
38 | /*< private >*/ | ||
39 | @@ -XXX,XX +XXX,XX @@ struct MachineClass { | ||
40 | void (*init)(MachineState *state); | ||
41 | void (*reset)(void); | ||
42 | void (*hot_add_cpu)(const int64_t id, Error **errp); | ||
43 | - int (*kvm_type)(const char *arg); | ||
44 | + int (*kvm_type)(MachineState *machine, const char *arg); | ||
45 | |||
46 | BlockInterfaceType block_default_type; | ||
47 | int units_per_default_bus; | ||
48 | diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/accel/kvm/kvm-all.c | ||
51 | +++ b/accel/kvm/kvm-all.c | ||
52 | @@ -XXX,XX +XXX,XX @@ static int kvm_init(MachineState *ms) | ||
53 | |||
54 | kvm_type = qemu_opt_get(qemu_get_machine_opts(), "kvm-type"); | ||
55 | if (mc->kvm_type) { | ||
56 | - type = mc->kvm_type(kvm_type); | ||
57 | + type = mc->kvm_type(ms, kvm_type); | ||
58 | } else if (kvm_type) { | ||
59 | ret = -EINVAL; | ||
60 | fprintf(stderr, "Invalid argument kvm-type=%s\n", kvm_type); | ||
61 | diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c | ||
62 | index XXXXXXX..XXXXXXX 100644 | ||
63 | --- a/hw/ppc/mac_newworld.c | ||
64 | +++ b/hw/ppc/mac_newworld.c | ||
65 | @@ -XXX,XX +XXX,XX @@ static char *core99_fw_dev_path(FWPathProvider *p, BusState *bus, | ||
66 | |||
67 | return NULL; | ||
68 | } | ||
69 | - | ||
70 | -static int core99_kvm_type(const char *arg) | ||
71 | +static int core99_kvm_type(MachineState *machine, const char *arg) | ||
72 | { | ||
73 | /* Always force PR KVM */ | ||
74 | return 2; | ||
75 | diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c | ||
76 | index XXXXXXX..XXXXXXX 100644 | ||
77 | --- a/hw/ppc/mac_oldworld.c | ||
78 | +++ b/hw/ppc/mac_oldworld.c | ||
79 | @@ -XXX,XX +XXX,XX @@ static char *heathrow_fw_dev_path(FWPathProvider *p, BusState *bus, | ||
80 | return NULL; | ||
81 | } | ||
82 | |||
83 | -static int heathrow_kvm_type(const char *arg) | ||
84 | +static int heathrow_kvm_type(MachineState *machine, const char *arg) | ||
85 | { | ||
86 | /* Always force PR KVM */ | ||
87 | return 2; | ||
88 | diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c | ||
89 | index XXXXXXX..XXXXXXX 100644 | ||
90 | --- a/hw/ppc/spapr.c | ||
91 | +++ b/hw/ppc/spapr.c | ||
92 | @@ -XXX,XX +XXX,XX @@ static void spapr_machine_init(MachineState *machine) | ||
93 | } | 16 | } |
94 | } | 17 | } |
95 | 18 | ||
96 | -static int spapr_kvm_type(const char *vm_type) | 19 | -static void stellaris_adc_reset(StellarisADCState *s) |
97 | +static int spapr_kvm_type(MachineState *machine, const char *vm_type) | 20 | +static void stellaris_adc_reset_hold(Object *obj) |
98 | { | 21 | { |
99 | if (!vm_type) { | 22 | + StellarisADCState *s = STELLARIS_ADC(obj); |
100 | return 0; | 23 | int n; |
24 | |||
25 | for (n = 0; n < 4; n++) { | ||
26 | @@ -XXX,XX +XXX,XX @@ static void stellaris_adc_init(Object *obj) | ||
27 | memory_region_init_io(&s->iomem, obj, &stellaris_adc_ops, s, | ||
28 | "adc", 0x1000); | ||
29 | sysbus_init_mmio(sbd, &s->iomem); | ||
30 | - stellaris_adc_reset(s); | ||
31 | qdev_init_gpio_in(dev, stellaris_adc_trigger, 1); | ||
32 | } | ||
33 | |||
34 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo stellaris_i2c_info = { | ||
35 | static void stellaris_adc_class_init(ObjectClass *klass, void *data) | ||
36 | { | ||
37 | DeviceClass *dc = DEVICE_CLASS(klass); | ||
38 | + ResettableClass *rc = RESETTABLE_CLASS(klass); | ||
39 | |||
40 | + rc->phases.hold = stellaris_adc_reset_hold; | ||
41 | dc->vmsd = &vmstate_stellaris_adc; | ||
42 | } | ||
43 | |||
101 | -- | 44 | -- |
102 | 2.20.1 | 45 | 2.34.1 |
103 | 46 | ||
104 | 47 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | We do not need an out-of-line helper for manipulating bits in pstate. | 3 | Suggested-by: Peter Maydell <peter.maydell@linaro.org> |
4 | While changing things, share the implementation of gen_ss_advance. | 4 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
5 | 5 | Message-id: 20240213155214.13619-3-philmd@linaro.org | |
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
7 | Message-id: 20190301200501.16533-6-richard.henderson@linaro.org | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | 6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | --- | 8 | --- |
11 | target/arm/helper.h | 2 -- | 9 | hw/arm/stellaris.c | 26 ++++++++++++++++++++++---- |
12 | target/arm/translate.h | 34 ++++++++++++++++++++++++++++++++++ | 10 | 1 file changed, 22 insertions(+), 4 deletions(-) |
13 | target/arm/op_helper.c | 5 ----- | ||
14 | target/arm/translate-a64.c | 11 ----------- | ||
15 | target/arm/translate.c | 11 ----------- | ||
16 | 5 files changed, 34 insertions(+), 29 deletions(-) | ||
17 | 11 | ||
18 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 12 | diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c |
19 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/target/arm/helper.h | 14 | --- a/hw/arm/stellaris.c |
21 | +++ b/target/arm/helper.h | 15 | +++ b/hw/arm/stellaris.c |
22 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(get_cp_reg, i32, env, ptr) | 16 | @@ -XXX,XX +XXX,XX @@ static void stellaris_sys_instance_init(Object *obj) |
23 | DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64) | 17 | s->sysclk = qdev_init_clock_out(DEVICE(s), "SYSCLK"); |
24 | DEF_HELPER_2(get_cp_reg64, i64, env, ptr) | ||
25 | |||
26 | -DEF_HELPER_1(clear_pstate_ss, void, env) | ||
27 | - | ||
28 | DEF_HELPER_2(get_r13_banked, i32, env, i32) | ||
29 | DEF_HELPER_3(set_r13_banked, void, env, i32, i32) | ||
30 | |||
31 | diff --git a/target/arm/translate.h b/target/arm/translate.h | ||
32 | index XXXXXXX..XXXXXXX 100644 | ||
33 | --- a/target/arm/translate.h | ||
34 | +++ b/target/arm/translate.h | ||
35 | @@ -XXX,XX +XXX,XX @@ static inline TCGv_i32 get_ahp_flag(void) | ||
36 | return ret; | ||
37 | } | 18 | } |
38 | 19 | ||
39 | +/* Set bits within PSTATE. */ | 20 | -/* I2C controller. */ |
40 | +static inline void set_pstate_bits(uint32_t bits) | 21 | +/* |
41 | +{ | 22 | + * I2C controller. |
42 | + TCGv_i32 p = tcg_temp_new_i32(); | 23 | + * ??? For now we only implement the master interface. |
24 | + */ | ||
25 | |||
26 | #define TYPE_STELLARIS_I2C "stellaris-i2c" | ||
27 | OBJECT_DECLARE_SIMPLE_TYPE(stellaris_i2c_state, STELLARIS_I2C) | ||
28 | @@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_write(void *opaque, hwaddr offset, | ||
29 | stellaris_i2c_update(s); | ||
30 | } | ||
31 | |||
32 | -static void stellaris_i2c_reset(stellaris_i2c_state *s) | ||
33 | +static void stellaris_i2c_reset_enter(Object *obj, ResetType type) | ||
34 | { | ||
35 | + stellaris_i2c_state *s = STELLARIS_I2C(obj); | ||
43 | + | 36 | + |
44 | + tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); | 37 | if (s->mcs & STELLARIS_I2C_MCS_BUSBSY) |
45 | + | 38 | i2c_end_transfer(s->bus); |
46 | + tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); | ||
47 | + tcg_gen_ori_i32(p, p, bits); | ||
48 | + tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); | ||
49 | + tcg_temp_free_i32(p); | ||
50 | +} | 39 | +} |
51 | + | 40 | + |
52 | +/* Clear bits within PSTATE. */ | 41 | +static void stellaris_i2c_reset_hold(Object *obj) |
53 | +static inline void clear_pstate_bits(uint32_t bits) | ||
54 | +{ | 42 | +{ |
55 | + TCGv_i32 p = tcg_temp_new_i32(); | 43 | + stellaris_i2c_state *s = STELLARIS_I2C(obj); |
56 | + | 44 | |
57 | + tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); | 45 | s->msa = 0; |
58 | + | 46 | s->mcs = 0; |
59 | + tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate)); | 47 | @@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_reset(stellaris_i2c_state *s) |
60 | + tcg_gen_andi_i32(p, p, ~bits); | 48 | s->mimr = 0; |
61 | + tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate)); | 49 | s->mris = 0; |
62 | + tcg_temp_free_i32(p); | 50 | s->mcr = 0; |
63 | +} | 51 | +} |
64 | + | 52 | + |
65 | +/* If the singlestep state is Active-not-pending, advance to Active-pending. */ | 53 | +static void stellaris_i2c_reset_exit(Object *obj) |
66 | +static inline void gen_ss_advance(DisasContext *s) | ||
67 | +{ | 54 | +{ |
68 | + if (s->ss_active) { | 55 | + stellaris_i2c_state *s = STELLARIS_I2C(obj); |
69 | + s->pstate_ss = 0; | 56 | + |
70 | + clear_pstate_bits(PSTATE_SS); | 57 | stellaris_i2c_update(s); |
71 | + } | ||
72 | +} | ||
73 | |||
74 | /* Vector operations shared between ARM and AArch64. */ | ||
75 | extern const GVecGen3 bsl_op; | ||
76 | diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c | ||
77 | index XXXXXXX..XXXXXXX 100644 | ||
78 | --- a/target/arm/op_helper.c | ||
79 | +++ b/target/arm/op_helper.c | ||
80 | @@ -XXX,XX +XXX,XX @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip) | ||
81 | return res; | ||
82 | } | 58 | } |
83 | 59 | ||
84 | -void HELPER(clear_pstate_ss)(CPUARMState *env) | 60 | @@ -XXX,XX +XXX,XX @@ static void stellaris_i2c_init(Object *obj) |
85 | -{ | 61 | memory_region_init_io(&s->iomem, obj, &stellaris_i2c_ops, s, |
86 | - env->pstate &= ~PSTATE_SS; | 62 | "i2c", 0x1000); |
87 | -} | 63 | sysbus_init_mmio(sbd, &s->iomem); |
88 | - | 64 | - /* ??? For now we only implement the master interface. */ |
89 | void HELPER(pre_hvc)(CPUARMState *env) | 65 | - stellaris_i2c_reset(s); |
66 | } | ||
67 | |||
68 | /* Analogue to Digital Converter. This is only partially implemented, | ||
69 | @@ -XXX,XX +XXX,XX @@ type_init(stellaris_machine_init) | ||
70 | static void stellaris_i2c_class_init(ObjectClass *klass, void *data) | ||
90 | { | 71 | { |
91 | ARMCPU *cpu = arm_env_get_cpu(env); | 72 | DeviceClass *dc = DEVICE_CLASS(klass); |
92 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | 73 | + ResettableClass *rc = RESETTABLE_CLASS(klass); |
93 | index XXXXXXX..XXXXXXX 100644 | 74 | |
94 | --- a/target/arm/translate-a64.c | 75 | + rc->phases.enter = stellaris_i2c_reset_enter; |
95 | +++ b/target/arm/translate-a64.c | 76 | + rc->phases.hold = stellaris_i2c_reset_hold; |
96 | @@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, int offset, | 77 | + rc->phases.exit = stellaris_i2c_reset_exit; |
97 | s->base.is_jmp = DISAS_NORETURN; | 78 | dc->vmsd = &vmstate_stellaris_i2c; |
98 | } | 79 | } |
99 | 80 | ||
100 | -static void gen_ss_advance(DisasContext *s) | ||
101 | -{ | ||
102 | - /* If the singlestep state is Active-not-pending, advance to | ||
103 | - * Active-pending. | ||
104 | - */ | ||
105 | - if (s->ss_active) { | ||
106 | - s->pstate_ss = 0; | ||
107 | - gen_helper_clear_pstate_ss(cpu_env); | ||
108 | - } | ||
109 | -} | ||
110 | - | ||
111 | static void gen_step_complete_exception(DisasContext *s) | ||
112 | { | ||
113 | /* We just completed step of an insn. Move from Active-not-pending | ||
114 | diff --git a/target/arm/translate.c b/target/arm/translate.c | ||
115 | index XXXXXXX..XXXXXXX 100644 | ||
116 | --- a/target/arm/translate.c | ||
117 | +++ b/target/arm/translate.c | ||
118 | @@ -XXX,XX +XXX,XX @@ static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el) | ||
119 | tcg_temp_free_i32(tcg_excp); | ||
120 | } | ||
121 | |||
122 | -static void gen_ss_advance(DisasContext *s) | ||
123 | -{ | ||
124 | - /* If the singlestep state is Active-not-pending, advance to | ||
125 | - * Active-pending. | ||
126 | - */ | ||
127 | - if (s->ss_active) { | ||
128 | - s->pstate_ss = 0; | ||
129 | - gen_helper_clear_pstate_ss(cpu_env); | ||
130 | - } | ||
131 | -} | ||
132 | - | ||
133 | static void gen_step_complete_exception(DisasContext *s) | ||
134 | { | ||
135 | /* We just completed step of an insn. Move from Active-not-pending | ||
136 | -- | 81 | -- |
137 | 2.20.1 | 82 | 2.34.1 |
138 | 83 | ||
139 | 84 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | This patch implements the machine class kvm_type() callback. | 3 | QDev objects created with qdev_new() need to manually add |
4 | It returns the number of bits requested to implement the whole GPA | 4 | their parent relationship with object_property_add_child(). |
5 | range including the RAM and IO regions located beyond. | ||
6 | The returned value is passed though the KVM_CREATE_VM ioctl and | ||
7 | this allows KVM to set the stage2 tables dynamically. | ||
8 | 5 | ||
9 | To compute the highest GPA used in the memory map, kvm_type() | 6 | This commit plug the devices which aren't part of the SoC; |
10 | must freeze the memory map by calling virt_set_memmap(). | 7 | they will be plugged into a SoC container in the next one. |
11 | 8 | ||
12 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | 9 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
13 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | 10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
14 | Message-id: 20190304101339.25970-9-eric.auger@redhat.com | 11 | Message-id: 20240213155214.13619-4-philmd@linaro.org |
15 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
16 | --- | 13 | --- |
17 | hw/arm/virt.c | 39 ++++++++++++++++++++++++++++++++++++++- | 14 | hw/arm/stellaris.c | 4 ++++ |
18 | 1 file changed, 38 insertions(+), 1 deletion(-) | 15 | 1 file changed, 4 insertions(+) |
19 | 16 | ||
20 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 17 | diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c |
21 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
22 | --- a/hw/arm/virt.c | 19 | --- a/hw/arm/stellaris.c |
23 | +++ b/hw/arm/virt.c | 20 | +++ b/hw/arm/stellaris.c |
24 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | 21 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) |
25 | bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); | 22 | &error_fatal); |
26 | bool aarch64 = true; | 23 | |
27 | 24 | ssddev = qdev_new("ssd0323"); | |
28 | - virt_set_memmap(vms); | 25 | + object_property_add_child(OBJECT(ms), "oled", OBJECT(ssddev)); |
29 | + /* | 26 | qdev_prop_set_uint8(ssddev, "cs", 1); |
30 | + * In accelerated mode, the memory map is computed earlier in kvm_type() | 27 | qdev_realize_and_unref(ssddev, bus, &error_fatal); |
31 | + * to create a VM with the right number of IPA bits. | 28 | |
32 | + */ | 29 | gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ); |
33 | + if (!vms->memmap) { | 30 | + object_property_add_child(OBJECT(ms), "splitter", |
34 | + virt_set_memmap(vms); | 31 | + OBJECT(gpio_d_splitter)); |
35 | + } | 32 | qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2); |
36 | 33 | qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal); | |
37 | /* We can probe only here because during property set | 34 | qdev_connect_gpio_out( |
38 | * KVM is not available yet | 35 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) |
39 | @@ -XXX,XX +XXX,XX @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, | 36 | DeviceState *gpad; |
40 | return NULL; | 37 | |
41 | } | 38 | gpad = qdev_new(TYPE_STELLARIS_GAMEPAD); |
42 | 39 | + object_property_add_child(OBJECT(ms), "gamepad", OBJECT(gpad)); | |
43 | +/* | 40 | for (i = 0; i < ARRAY_SIZE(gpad_keycode); i++) { |
44 | + * for arm64 kvm_type [7-0] encodes the requested number of bits | 41 | qlist_append_int(gpad_keycode_list, gpad_keycode[i]); |
45 | + * in the IPA address space | 42 | } |
46 | + */ | ||
47 | +static int virt_kvm_type(MachineState *ms, const char *type_str) | ||
48 | +{ | ||
49 | + VirtMachineState *vms = VIRT_MACHINE(ms); | ||
50 | + int max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms); | ||
51 | + int requested_pa_size; | ||
52 | + | ||
53 | + /* we freeze the memory map to compute the highest gpa */ | ||
54 | + virt_set_memmap(vms); | ||
55 | + | ||
56 | + requested_pa_size = 64 - clz64(vms->highest_gpa); | ||
57 | + | ||
58 | + if (requested_pa_size > max_vm_pa_size) { | ||
59 | + error_report("-m and ,maxmem option values " | ||
60 | + "require an IPA range (%d bits) larger than " | ||
61 | + "the one supported by the host (%d bits)", | ||
62 | + requested_pa_size, max_vm_pa_size); | ||
63 | + exit(1); | ||
64 | + } | ||
65 | + /* | ||
66 | + * By default we return 0 which corresponds to an implicit legacy | ||
67 | + * 40b IPA setting. Otherwise we return the actual requested PA | ||
68 | + * logsize | ||
69 | + */ | ||
70 | + return requested_pa_size > 40 ? requested_pa_size : 0; | ||
71 | +} | ||
72 | + | ||
73 | static void virt_machine_class_init(ObjectClass *oc, void *data) | ||
74 | { | ||
75 | MachineClass *mc = MACHINE_CLASS(oc); | ||
76 | @@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data) | ||
77 | mc->cpu_index_to_instance_props = virt_cpu_index_to_props; | ||
78 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15"); | ||
79 | mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; | ||
80 | + mc->kvm_type = virt_kvm_type; | ||
81 | assert(!mc->get_hotplug_handler); | ||
82 | mc->get_hotplug_handler = virt_machine_get_hotplug_handler; | ||
83 | hc->plug = virt_machine_device_plug_cb; | ||
84 | -- | 43 | -- |
85 | 2.20.1 | 44 | 2.34.1 |
86 | 45 | ||
87 | 46 | diff view generated by jsdifflib |
1 | From: Michel Heily <michelheily@gmail.com> | 1 | From: Philippe Mathieu-Daudé <philmd@linaro.org> |
---|---|---|---|
2 | 2 | ||
3 | Implement the watchdog timer for the stellaris boards. | 3 | QDev objects created with qdev_new() need to manually add |
4 | This device is a close variant of the CMSDK APB watchdog | 4 | their parent relationship with object_property_add_child(). |
5 | device, so we can model it by subclassing that device and | ||
6 | tweaking the behaviour of some of its registers. | ||
7 | 5 | ||
8 | Signed-off-by: Michel Heily <michelheily@gmail.com> | 6 | Since we don't model the SoC, just use a QOM container. |
9 | Reviewed-by: Peter Maydell <petser.maydell@linaro.org> | 7 | |
10 | [PMM: rewrote commit message, fixed a few checkpatch nits, | 8 | Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
11 | added comment giving the URL of the spec for the Stellaris | 9 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> |
12 | variant of the watchdog device] | 10 | Message-id: 20240213155214.13619-5-philmd@linaro.org |
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 11 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
14 | --- | 12 | --- |
15 | include/hw/watchdog/cmsdk-apb-watchdog.h | 8 +++ | 13 | hw/arm/stellaris.c | 11 ++++++++++- |
16 | hw/arm/stellaris.c | 22 ++++++- | 14 | 1 file changed, 10 insertions(+), 1 deletion(-) |
17 | hw/watchdog/cmsdk-apb-watchdog.c | 74 +++++++++++++++++++++++- | ||
18 | 3 files changed, 100 insertions(+), 4 deletions(-) | ||
19 | 15 | ||
20 | diff --git a/include/hw/watchdog/cmsdk-apb-watchdog.h b/include/hw/watchdog/cmsdk-apb-watchdog.h | ||
21 | index XXXXXXX..XXXXXXX 100644 | ||
22 | --- a/include/hw/watchdog/cmsdk-apb-watchdog.h | ||
23 | +++ b/include/hw/watchdog/cmsdk-apb-watchdog.h | ||
24 | @@ -XXX,XX +XXX,XX @@ | ||
25 | #define CMSDK_APB_WATCHDOG(obj) OBJECT_CHECK(CMSDKAPBWatchdog, (obj), \ | ||
26 | TYPE_CMSDK_APB_WATCHDOG) | ||
27 | |||
28 | +/* | ||
29 | + * This shares the same struct (and cast macro) as the base | ||
30 | + * cmsdk-apb-watchdog device. | ||
31 | + */ | ||
32 | +#define TYPE_LUMINARY_WATCHDOG "luminary-watchdog" | ||
33 | + | ||
34 | typedef struct CMSDKAPBWatchdog { | ||
35 | /*< private >*/ | ||
36 | SysBusDevice parent_obj; | ||
37 | @@ -XXX,XX +XXX,XX @@ typedef struct CMSDKAPBWatchdog { | ||
38 | MemoryRegion iomem; | ||
39 | qemu_irq wdogint; | ||
40 | uint32_t wdogclk_frq; | ||
41 | + bool is_luminary; | ||
42 | struct ptimer_state *timer; | ||
43 | |||
44 | uint32_t control; | ||
45 | @@ -XXX,XX +XXX,XX @@ typedef struct CMSDKAPBWatchdog { | ||
46 | uint32_t itcr; | ||
47 | uint32_t itop; | ||
48 | uint32_t resetstatus; | ||
49 | + const uint32_t *id; | ||
50 | } CMSDKAPBWatchdog; | ||
51 | |||
52 | #endif | ||
53 | diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c | 16 | diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c |
54 | index XXXXXXX..XXXXXXX 100644 | 17 | index XXXXXXX..XXXXXXX 100644 |
55 | --- a/hw/arm/stellaris.c | 18 | --- a/hw/arm/stellaris.c |
56 | +++ b/hw/arm/stellaris.c | 19 | +++ b/hw/arm/stellaris.c |
57 | @@ -XXX,XX +XXX,XX @@ | ||
58 | #include "sysemu/sysemu.h" | ||
59 | #include "hw/arm/armv7m.h" | ||
60 | #include "hw/char/pl011.h" | ||
61 | +#include "hw/watchdog/cmsdk-apb-watchdog.h" | ||
62 | #include "hw/misc/unimp.h" | ||
63 | #include "cpu.h" | ||
64 | |||
65 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) | 20 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) |
66 | * Stellaris LM3S6965 Microcontroller Data Sheet (rev I) | 21 | * 400fe000 system control |
67 | * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf | 22 | */ |
68 | * | 23 | |
69 | - * 40000000 wdtimer (unimplemented) | 24 | + Object *soc_container; |
70 | + * 40000000 wdtimer | 25 | DeviceState *gpio_dev[7], *nvic; |
71 | * 40002000 i2c (unimplemented) | 26 | qemu_irq gpio_in[7][8]; |
72 | * 40004000 GPIO | 27 | qemu_irq gpio_out[7][8]; |
73 | * 40005000 GPIO | ||
74 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) | 28 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) |
75 | stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28), | 29 | flash_size = (((board->dc0 & 0xffff) + 1) << 1) * 1024; |
76 | board, nd_table[0].macaddr.a); | 30 | sram_size = ((board->dc0 >> 18) + 1) * 1024; |
77 | 31 | ||
32 | + soc_container = object_new("container"); | ||
33 | + object_property_add_child(OBJECT(ms), "soc", soc_container); | ||
78 | + | 34 | + |
79 | + if (board->dc1 & (1 << 3)) { /* watchdog present */ | 35 | /* Flash programming is done via the SCU, so pretend it is ROM. */ |
80 | + dev = qdev_create(NULL, TYPE_LUMINARY_WATCHDOG); | 36 | memory_region_init_rom(flash, NULL, "stellaris.flash", flash_size, |
81 | + | 37 | &error_fatal); |
82 | + /* system_clock_scale is valid now */ | ||
83 | + uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale; | ||
84 | + qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk); | ||
85 | + | ||
86 | + qdev_init_nofail(dev); | ||
87 | + sysbus_mmio_map(SYS_BUS_DEVICE(dev), | ||
88 | + 0, | ||
89 | + 0x40000000u); | ||
90 | + sysbus_connect_irq(SYS_BUS_DEVICE(dev), | ||
91 | + 0, | ||
92 | + qdev_get_gpio_in(nvic, 18)); | ||
93 | + } | ||
94 | + | ||
95 | + | ||
96 | for (i = 0; i < 7; i++) { | ||
97 | if (board->dc4 & (1 << i)) { | ||
98 | gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i], | ||
99 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) | 38 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) |
100 | /* Add dummy regions for the devices we don't implement yet, | 39 | * need its sysclk output. |
101 | * so guest accesses don't cause unlogged crashes. | ||
102 | */ | 40 | */ |
103 | - create_unimplemented_device("wdtimer", 0x40000000, 0x1000); | 41 | ssys_dev = qdev_new(TYPE_STELLARIS_SYS); |
104 | create_unimplemented_device("i2c-0", 0x40002000, 0x1000); | 42 | + object_property_add_child(soc_container, "sys", OBJECT(ssys_dev)); |
105 | create_unimplemented_device("i2c-2", 0x40021000, 0x1000); | 43 | |
106 | create_unimplemented_device("PWM", 0x40028000, 0x1000); | 44 | /* |
107 | diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c | 45 | * Most devices come preprogrammed with a MAC address in the user data. |
108 | index XXXXXXX..XXXXXXX 100644 | 46 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) |
109 | --- a/hw/watchdog/cmsdk-apb-watchdog.c | 47 | sysbus_realize_and_unref(SYS_BUS_DEVICE(ssys_dev), &error_fatal); |
110 | +++ b/hw/watchdog/cmsdk-apb-watchdog.c | 48 | |
111 | @@ -XXX,XX +XXX,XX @@ | 49 | nvic = qdev_new(TYPE_ARMV7M); |
112 | * System Design Kit (CMSDK) and documented in the Cortex-M System | 50 | + object_property_add_child(soc_container, "v7m", OBJECT(nvic)); |
113 | * Design Kit Technical Reference Manual (ARM DDI0479C): | 51 | qdev_prop_set_uint32(nvic, "num-irq", NUM_IRQ_LINES); |
114 | * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit | 52 | qdev_prop_set_uint8(nvic, "num-prio-bits", NUM_PRIO_BITS); |
115 | + * | 53 | qdev_prop_set_string(nvic, "cpu-type", ms->cpu_type); |
116 | + * We also support the variant of this device found in the TI | 54 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) |
117 | + * Stellaris/Luminary boards and documented in: | 55 | |
118 | + * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf | 56 | dev = qdev_new(TYPE_STELLARIS_GPTM); |
119 | */ | 57 | sbd = SYS_BUS_DEVICE(dev); |
120 | 58 | + object_property_add_child(soc_container, "gptm[*]", OBJECT(dev)); | |
121 | #include "qemu/osdep.h" | 59 | qdev_connect_clock_in(dev, "clk", |
122 | @@ -XXX,XX +XXX,XX @@ REG32(WDOGINTCLR, 0xc) | 60 | qdev_get_clock_out(ssys_dev, "SYSCLK")); |
123 | REG32(WDOGRIS, 0x10) | 61 | sysbus_realize_and_unref(sbd, &error_fatal); |
124 | FIELD(WDOGRIS, INT, 0, 1) | 62 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) |
125 | REG32(WDOGMIS, 0x14) | 63 | |
126 | +REG32(WDOGTEST, 0x418) /* only in Stellaris/Luminary version of the device */ | 64 | if (board->dc1 & (1 << 3)) { /* watchdog present */ |
127 | REG32(WDOGLOCK, 0xc00) | 65 | dev = qdev_new(TYPE_LUMINARY_WATCHDOG); |
128 | #define WDOG_UNLOCK_VALUE 0x1ACCE551 | 66 | - |
129 | REG32(WDOGITCR, 0xf00) | 67 | + object_property_add_child(soc_container, "wdg", OBJECT(dev)); |
130 | @@ -XXX,XX +XXX,XX @@ REG32(CID2, 0xff8) | 68 | qdev_connect_clock_in(dev, "WDOGCLK", |
131 | REG32(CID3, 0xffc) | 69 | qdev_get_clock_out(ssys_dev, "SYSCLK")); |
132 | 70 | ||
133 | /* PID/CID values */ | 71 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) |
134 | -static const int watchdog_id[] = { | 72 | SysBusDevice *sbd; |
135 | +static const uint32_t cmsdk_apb_watchdog_id[] = { | 73 | |
136 | 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */ | 74 | dev = qdev_new("pl011_luminary"); |
137 | 0x24, 0xb8, 0x1b, 0x00, /* PID0..PID3 */ | 75 | + object_property_add_child(soc_container, "uart[*]", OBJECT(dev)); |
138 | 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ | 76 | sbd = SYS_BUS_DEVICE(dev); |
139 | }; | 77 | qdev_prop_set_chr(dev, "chardev", serial_hd(i)); |
140 | 78 | sysbus_realize_and_unref(sbd, &error_fatal); | |
141 | +static const uint32_t luminary_watchdog_id[] = { | 79 | @@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) |
142 | + 0x00, 0x00, 0x00, 0x00, /* PID4..PID7 */ | 80 | DeviceState *enet; |
143 | + 0x05, 0x18, 0x18, 0x01, /* PID0..PID3 */ | 81 | |
144 | + 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */ | 82 | enet = qdev_new("stellaris_enet"); |
145 | +}; | 83 | + object_property_add_child(soc_container, "enet", OBJECT(enet)); |
146 | + | 84 | if (nd) { |
147 | static bool cmsdk_apb_watchdog_intstatus(CMSDKAPBWatchdog *s) | 85 | qdev_set_nic_properties(enet, nd); |
148 | { | 86 | } else { |
149 | /* Return masked interrupt status */ | ||
150 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_update(CMSDKAPBWatchdog *s) | ||
151 | bool wdogres; | ||
152 | |||
153 | if (s->itcr) { | ||
154 | + /* | ||
155 | + * Not checking that !s->is_luminary since s->itcr can't be written | ||
156 | + * when s->is_luminary in the first place. | ||
157 | + */ | ||
158 | wdogint = s->itop & R_WDOGITOP_WDOGINT_MASK; | ||
159 | wdogres = s->itop & R_WDOGITOP_WDOGRES_MASK; | ||
160 | } else { | ||
161 | @@ -XXX,XX +XXX,XX @@ static uint64_t cmsdk_apb_watchdog_read(void *opaque, hwaddr offset, | ||
162 | r = s->lock; | ||
163 | break; | ||
164 | case A_WDOGITCR: | ||
165 | + if (s->is_luminary) { | ||
166 | + goto bad_offset; | ||
167 | + } | ||
168 | r = s->itcr; | ||
169 | break; | ||
170 | case A_PID4 ... A_CID3: | ||
171 | - r = watchdog_id[(offset - A_PID4) / 4]; | ||
172 | + r = s->id[(offset - A_PID4) / 4]; | ||
173 | break; | ||
174 | case A_WDOGINTCLR: | ||
175 | case A_WDOGITOP: | ||
176 | + if (s->is_luminary) { | ||
177 | + goto bad_offset; | ||
178 | + } | ||
179 | qemu_log_mask(LOG_GUEST_ERROR, | ||
180 | "CMSDK APB watchdog read: read of WO offset %x\n", | ||
181 | (int)offset); | ||
182 | r = 0; | ||
183 | break; | ||
184 | + case A_WDOGTEST: | ||
185 | + if (!s->is_luminary) { | ||
186 | + goto bad_offset; | ||
187 | + } | ||
188 | + qemu_log_mask(LOG_UNIMP, | ||
189 | + "Luminary watchdog read: stall not implemented\n"); | ||
190 | + r = 0; | ||
191 | + break; | ||
192 | default: | ||
193 | +bad_offset: | ||
194 | qemu_log_mask(LOG_GUEST_ERROR, | ||
195 | "CMSDK APB watchdog read: bad offset %x\n", (int)offset); | ||
196 | r = 0; | ||
197 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_write(void *opaque, hwaddr offset, | ||
198 | ptimer_run(s->timer, 0); | ||
199 | break; | ||
200 | case A_WDOGCONTROL: | ||
201 | + if (s->is_luminary && 0 != (R_WDOGCONTROL_INTEN_MASK & s->control)) { | ||
202 | + /* | ||
203 | + * The Luminary version of this device ignores writes to | ||
204 | + * this register after the guest has enabled interrupts | ||
205 | + * (so they can only be disabled again via reset). | ||
206 | + */ | ||
207 | + break; | ||
208 | + } | ||
209 | s->control = value & R_WDOGCONTROL_VALID_MASK; | ||
210 | cmsdk_apb_watchdog_update(s); | ||
211 | break; | ||
212 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_write(void *opaque, hwaddr offset, | ||
213 | s->lock = (value != WDOG_UNLOCK_VALUE); | ||
214 | break; | ||
215 | case A_WDOGITCR: | ||
216 | + if (s->is_luminary) { | ||
217 | + goto bad_offset; | ||
218 | + } | ||
219 | s->itcr = value & R_WDOGITCR_VALID_MASK; | ||
220 | cmsdk_apb_watchdog_update(s); | ||
221 | break; | ||
222 | case A_WDOGITOP: | ||
223 | + if (s->is_luminary) { | ||
224 | + goto bad_offset; | ||
225 | + } | ||
226 | s->itop = value & R_WDOGITOP_VALID_MASK; | ||
227 | cmsdk_apb_watchdog_update(s); | ||
228 | break; | ||
229 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_write(void *opaque, hwaddr offset, | ||
230 | "CMSDK APB watchdog write: write to RO offset 0x%x\n", | ||
231 | (int)offset); | ||
232 | break; | ||
233 | + case A_WDOGTEST: | ||
234 | + if (!s->is_luminary) { | ||
235 | + goto bad_offset; | ||
236 | + } | ||
237 | + qemu_log_mask(LOG_UNIMP, | ||
238 | + "Luminary watchdog write: stall not implemented\n"); | ||
239 | + break; | ||
240 | default: | ||
241 | +bad_offset: | ||
242 | qemu_log_mask(LOG_GUEST_ERROR, | ||
243 | "CMSDK APB watchdog write: bad offset 0x%x\n", | ||
244 | (int)offset); | ||
245 | @@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_init(Object *obj) | ||
246 | s, "cmsdk-apb-watchdog", 0x1000); | ||
247 | sysbus_init_mmio(sbd, &s->iomem); | ||
248 | sysbus_init_irq(sbd, &s->wdogint); | ||
249 | + | ||
250 | + s->is_luminary = false; | ||
251 | + s->id = cmsdk_apb_watchdog_id; | ||
252 | } | ||
253 | |||
254 | static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp) | ||
255 | @@ -XXX,XX +XXX,XX @@ static const TypeInfo cmsdk_apb_watchdog_info = { | ||
256 | .class_init = cmsdk_apb_watchdog_class_init, | ||
257 | }; | ||
258 | |||
259 | +static void luminary_watchdog_init(Object *obj) | ||
260 | +{ | ||
261 | + CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(obj); | ||
262 | + | ||
263 | + s->is_luminary = true; | ||
264 | + s->id = luminary_watchdog_id; | ||
265 | +} | ||
266 | + | ||
267 | +static const TypeInfo luminary_watchdog_info = { | ||
268 | + .name = TYPE_LUMINARY_WATCHDOG, | ||
269 | + .parent = TYPE_CMSDK_APB_WATCHDOG, | ||
270 | + .instance_init = luminary_watchdog_init | ||
271 | +}; | ||
272 | + | ||
273 | static void cmsdk_apb_watchdog_register_types(void) | ||
274 | { | ||
275 | type_register_static(&cmsdk_apb_watchdog_info); | ||
276 | + type_register_static(&luminary_watchdog_info); | ||
277 | } | ||
278 | |||
279 | type_init(cmsdk_apb_watchdog_register_types); | ||
280 | -- | 87 | -- |
281 | 2.20.1 | 88 | 2.34.1 |
282 | 89 | ||
283 | 90 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | We support two different encodings for the AArch32 IMPDEF | ||
2 | CBAR register -- older cores like the Cortex A9, A7, A15 | ||
3 | have this at 4, c15, c0, 0; newer cores like the | ||
4 | Cortex A35, A53, A57 and A72 have it at 1 c15 c0 0. | ||
1 | 5 | ||
6 | When we implemented this we picked which encoding to | ||
7 | use based on whether the CPU set ARM_FEATURE_AARCH64. | ||
8 | However this isn't right for three cases: | ||
9 | * the qemu-system-arm 'max' CPU, which is supposed to be | ||
10 | a variant on a Cortex-A57; it ought to use the same | ||
11 | encoding the A57 does and which the AArch64 'max' | ||
12 | exposes to AArch32 guest code | ||
13 | * the Cortex-R52, which is AArch32-only but has the CBAR | ||
14 | at the newer encoding (and where we incorrectly are | ||
15 | not yet setting ARM_FEATURE_CBAR_RO anyway) | ||
16 | * any possible future support for other v8 AArch32 | ||
17 | only CPUs, or for supporting "boot the CPU into | ||
18 | AArch32 mode" on our existing cores like the A57 etc | ||
19 | |||
20 | Make the decision of the encoding be based on whether | ||
21 | the CPU implements the ARM_FEATURE_V8 flag instead. | ||
22 | |||
23 | This changes the behaviour only for the qemu-system-arm | ||
24 | '-cpu max'. We don't expect anybody to be relying on the | ||
25 | old behaviour because: | ||
26 | * it's not what the real hardware Cortex-A57 does | ||
27 | (and that's what our ID register claims we are) | ||
28 | * we don't implement the memory-mapped GICv3 support | ||
29 | which is the only thing that exists at the peripheral | ||
30 | base address pointed to by the register | ||
31 | |||
32 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
33 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
34 | Message-id: 20240206132931.38376-2-peter.maydell@linaro.org | ||
35 | --- | ||
36 | target/arm/helper.c | 2 +- | ||
37 | 1 file changed, 1 insertion(+), 1 deletion(-) | ||
38 | |||
39 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
40 | index XXXXXXX..XXXXXXX 100644 | ||
41 | --- a/target/arm/helper.c | ||
42 | +++ b/target/arm/helper.c | ||
43 | @@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu) | ||
44 | * AArch64 cores we might need to add a specific feature flag | ||
45 | * to indicate cores with "flavour 2" CBAR. | ||
46 | */ | ||
47 | - if (arm_feature(env, ARM_FEATURE_AARCH64)) { | ||
48 | + if (arm_feature(env, ARM_FEATURE_V8)) { | ||
49 | /* 32 bit view is [31:18] 0...0 [43:32]. */ | ||
50 | uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18) | ||
51 | | extract64(cpu->reset_cbar, 32, 12); | ||
52 | -- | ||
53 | 2.34.1 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | The Cortex-R52 implements the Configuration Base Address Register | ||
2 | (CBAR), as a read-only register. Add ARM_FEATURE_CBAR_RO to this CPU | ||
3 | type, so that our implementation provides the register and the | ||
4 | associated qdev property. | ||
1 | 5 | ||
6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
8 | Message-id: 20240206132931.38376-3-peter.maydell@linaro.org | ||
9 | --- | ||
10 | target/arm/tcg/cpu32.c | 1 + | ||
11 | 1 file changed, 1 insertion(+) | ||
12 | |||
13 | diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c | ||
14 | index XXXXXXX..XXXXXXX 100644 | ||
15 | --- a/target/arm/tcg/cpu32.c | ||
16 | +++ b/target/arm/tcg/cpu32.c | ||
17 | @@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj) | ||
18 | set_feature(&cpu->env, ARM_FEATURE_PMSA); | ||
19 | set_feature(&cpu->env, ARM_FEATURE_NEON); | ||
20 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); | ||
21 | + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); | ||
22 | cpu->midr = 0x411fd133; /* r1p3 */ | ||
23 | cpu->revidr = 0x00000000; | ||
24 | cpu->reset_fpsid = 0x41034023; | ||
25 | -- | ||
26 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Add the Cortex-R52 IMPDEF sysregs, by defining them here and |
---|---|---|---|
2 | also by enabling the AUXCR feature which defines the ACTLR | ||
3 | and HACTLR registers. As is our usual practice, we make these | ||
4 | simple reads-as-zero stubs for now. | ||
2 | 5 | ||
3 | Minimize the number of places that will need updating when | 6 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | the virtual host extensions are added. | 7 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> |
8 | Message-id: 20240206132931.38376-4-peter.maydell@linaro.org | ||
9 | --- | ||
10 | target/arm/tcg/cpu32.c | 108 +++++++++++++++++++++++++++++++++++++++++ | ||
11 | 1 file changed, 108 insertions(+) | ||
5 | 12 | ||
6 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 13 | diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c |
7 | Message-id: 20190301200501.16533-2-richard.henderson@linaro.org | ||
8 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
10 | --- | ||
11 | target/arm/cpu.h | 26 ++++++++++++++++---------- | ||
12 | target/arm/helper.c | 8 ++------ | ||
13 | 2 files changed, 18 insertions(+), 16 deletions(-) | ||
14 | |||
15 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | ||
16 | index XXXXXXX..XXXXXXX 100644 | 14 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/cpu.h | 15 | --- a/target/arm/tcg/cpu32.c |
18 | +++ b/target/arm/cpu.h | 16 | +++ b/target/arm/tcg/cpu32.c |
19 | @@ -XXX,XX +XXX,XX @@ static inline bool arm_sctlr_b(CPUARMState *env) | 17 | @@ -XXX,XX +XXX,XX @@ static void cortex_r5_initfn(Object *obj) |
20 | (env->cp15.sctlr_el[1] & SCTLR_B) != 0; | 18 | define_arm_cp_regs(cpu, cortexr5_cp_reginfo); |
21 | } | 19 | } |
22 | 20 | ||
23 | +static inline uint64_t arm_sctlr(CPUARMState *env, int el) | 21 | +static const ARMCPRegInfo cortex_r52_cp_reginfo[] = { |
24 | +{ | 22 | + { .name = "CPUACTLR", .cp = 15, .opc1 = 0, .crm = 15, |
25 | + if (el == 0) { | 23 | + .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_64BIT, .resetvalue = 0 }, |
26 | + /* FIXME: ARMv8.1-VHE S2 translation regime. */ | 24 | + { .name = "IMP_ATCMREGIONR", |
27 | + return env->cp15.sctlr_el[1]; | 25 | + .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0, |
28 | + } else { | 26 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
29 | + return env->cp15.sctlr_el[el]; | 27 | + { .name = "IMP_BTCMREGIONR", |
30 | + } | 28 | + .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1, |
31 | +} | 29 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, |
30 | + { .name = "IMP_CTCMREGIONR", | ||
31 | + .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 2, | ||
32 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
33 | + { .name = "IMP_CSCTLR", | ||
34 | + .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 0, | ||
35 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
36 | + { .name = "IMP_BPCTLR", | ||
37 | + .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 1, | ||
38 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
39 | + { .name = "IMP_MEMPROTCLR", | ||
40 | + .cp = 15, .opc1 = 1, .crn = 9, .crm = 1, .opc2 = 2, | ||
41 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
42 | + { .name = "IMP_SLAVEPCTLR", | ||
43 | + .cp = 15, .opc1 = 0, .crn = 11, .crm = 0, .opc2 = 0, | ||
44 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
45 | + { .name = "IMP_PERIPHREGIONR", | ||
46 | + .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 0, | ||
47 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
48 | + { .name = "IMP_FLASHIFREGIONR", | ||
49 | + .cp = 15, .opc1 = 0, .crn = 15, .crm = 0, .opc2 = 1, | ||
50 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
51 | + { .name = "IMP_BUILDOPTR", | ||
52 | + .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 0, | ||
53 | + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
54 | + { .name = "IMP_PINOPTR", | ||
55 | + .cp = 15, .opc1 = 0, .crn = 15, .crm = 2, .opc2 = 7, | ||
56 | + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
57 | + { .name = "IMP_QOSR", | ||
58 | + .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 1, | ||
59 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
60 | + { .name = "IMP_BUSTIMEOUTR", | ||
61 | + .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 2, | ||
62 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
63 | + { .name = "IMP_INTMONR", | ||
64 | + .cp = 15, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 4, | ||
65 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
66 | + { .name = "IMP_ICERR0", | ||
67 | + .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 0, | ||
68 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
69 | + { .name = "IMP_ICERR1", | ||
70 | + .cp = 15, .opc1 = 2, .crn = 15, .crm = 0, .opc2 = 1, | ||
71 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
72 | + { .name = "IMP_DCERR0", | ||
73 | + .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 0, | ||
74 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
75 | + { .name = "IMP_DCERR1", | ||
76 | + .cp = 15, .opc1 = 2, .crn = 15, .crm = 1, .opc2 = 1, | ||
77 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
78 | + { .name = "IMP_TCMERR0", | ||
79 | + .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 0, | ||
80 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
81 | + { .name = "IMP_TCMERR1", | ||
82 | + .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 1, | ||
83 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
84 | + { .name = "IMP_TCMSYNDR0", | ||
85 | + .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 2, | ||
86 | + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
87 | + { .name = "IMP_TCMSYNDR1", | ||
88 | + .cp = 15, .opc1 = 2, .crn = 15, .crm = 2, .opc2 = 3, | ||
89 | + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
90 | + { .name = "IMP_FLASHERR0", | ||
91 | + .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 0, | ||
92 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
93 | + { .name = "IMP_FLASHERR1", | ||
94 | + .cp = 15, .opc1 = 2, .crn = 15, .crm = 3, .opc2 = 1, | ||
95 | + .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
96 | + { .name = "IMP_CDBGDR0", | ||
97 | + .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 0, | ||
98 | + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
99 | + { .name = "IMP_CBDGBR1", | ||
100 | + .cp = 15, .opc1 = 3, .crn = 15, .crm = 0, .opc2 = 1, | ||
101 | + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
102 | + { .name = "IMP_TESTR0", | ||
103 | + .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 0, | ||
104 | + .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 }, | ||
105 | + { .name = "IMP_TESTR1", | ||
106 | + .cp = 15, .opc1 = 4, .crn = 15, .crm = 0, .opc2 = 1, | ||
107 | + .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 }, | ||
108 | + { .name = "IMP_CDBGDCI", | ||
109 | + .cp = 15, .opc1 = 0, .crn = 15, .crm = 15, .opc2 = 0, | ||
110 | + .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 }, | ||
111 | + { .name = "IMP_CDBGDCT", | ||
112 | + .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 0, | ||
113 | + .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 }, | ||
114 | + { .name = "IMP_CDBGICT", | ||
115 | + .cp = 15, .opc1 = 3, .crn = 15, .crm = 2, .opc2 = 1, | ||
116 | + .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 }, | ||
117 | + { .name = "IMP_CDBGDCD", | ||
118 | + .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 0, | ||
119 | + .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 }, | ||
120 | + { .name = "IMP_CDBGICD", | ||
121 | + .cp = 15, .opc1 = 3, .crn = 15, .crm = 4, .opc2 = 1, | ||
122 | + .access = PL1_W, .type = ARM_CP_NOP, .resetvalue = 0 }, | ||
123 | +}; | ||
32 | + | 124 | + |
33 | + | 125 | + |
34 | /* Return true if the processor is in big-endian mode. */ | 126 | static void cortex_r52_initfn(Object *obj) |
35 | static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) | ||
36 | { | 127 | { |
37 | - int cur_el; | 128 | ARMCPU *cpu = ARM_CPU(obj); |
38 | - | 129 | @@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj) |
39 | /* In 32bit endianness is determined by looking at CPSR's E bit */ | 130 | set_feature(&cpu->env, ARM_FEATURE_NEON); |
40 | if (!is_a64(env)) { | 131 | set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); |
41 | return | 132 | set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); |
42 | @@ -XXX,XX +XXX,XX @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) | 133 | + set_feature(&cpu->env, ARM_FEATURE_AUXCR); |
43 | arm_sctlr_b(env) || | 134 | cpu->midr = 0x411fd133; /* r1p3 */ |
44 | #endif | 135 | cpu->revidr = 0x00000000; |
45 | ((env->uncached_cpsr & CPSR_E) ? 1 : 0); | 136 | cpu->reset_fpsid = 0x41034023; |
46 | + } else { | 137 | @@ -XXX,XX +XXX,XX @@ static void cortex_r52_initfn(Object *obj) |
47 | + int cur_el = arm_current_el(env); | 138 | |
48 | + uint64_t sctlr = arm_sctlr(env, cur_el); | 139 | cpu->pmsav7_dregion = 16; |
140 | cpu->pmsav8r_hdregion = 16; | ||
49 | + | 141 | + |
50 | + return (sctlr & (cur_el ? SCTLR_EE : SCTLR_E0E)) != 0; | 142 | + define_arm_cp_regs(cpu, cortex_r52_cp_reginfo); |
51 | } | ||
52 | - | ||
53 | - cur_el = arm_current_el(env); | ||
54 | - | ||
55 | - if (cur_el == 0) { | ||
56 | - return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0; | ||
57 | - } | ||
58 | - | ||
59 | - return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0; | ||
60 | } | 143 | } |
61 | 144 | ||
62 | #include "exec/cpu-all.h" | 145 | static void cortex_r5f_initfn(Object *obj) |
63 | diff --git a/target/arm/helper.c b/target/arm/helper.c | ||
64 | index XXXXXXX..XXXXXXX 100644 | ||
65 | --- a/target/arm/helper.c | ||
66 | +++ b/target/arm/helper.c | ||
67 | @@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, | ||
68 | flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); | ||
69 | } | ||
70 | |||
71 | - if (current_el == 0) { | ||
72 | - /* FIXME: ARMv8.1-VHE S2 translation regime. */ | ||
73 | - sctlr = env->cp15.sctlr_el[1]; | ||
74 | - } else { | ||
75 | - sctlr = env->cp15.sctlr_el[current_el]; | ||
76 | - } | ||
77 | + sctlr = arm_sctlr(env, current_el); | ||
78 | + | ||
79 | if (cpu_isar_feature(aa64_pauth, cpu)) { | ||
80 | /* | ||
81 | * In order to save space in flags, we record only whether | ||
82 | -- | 146 | -- |
83 | 2.20.1 | 147 | 2.34.1 |
84 | |||
85 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | Architecturally, the AArch32 MSR/MRS to/from banked register | ||
2 | instructions are UNPREDICTABLE for attempts to access a banked | ||
3 | register that the guest could access in a more direct way (e.g. | ||
4 | using this insn to access r8_fiq when already in FIQ mode). QEMU has | ||
5 | chosen to UNDEF on all of these. | ||
1 | 6 | ||
7 | However, for the case of accessing SPSR_hyp from hyp mode, it turns | ||
8 | out that real hardware permits this, with the same effect as if the | ||
9 | guest had directly written to SPSR. Further, there is some | ||
10 | guest code out there that assumes it can do this, because it | ||
11 | happens to work on hardware: an example Cortex-R52 startup code | ||
12 | fragment uses this, and it got copied into various other places, | ||
13 | including Zephyr. Zephyr was fixed to not use this: | ||
14 | https://github.com/zephyrproject-rtos/zephyr/issues/47330 | ||
15 | but other examples are still out there, like the selftest | ||
16 | binary for the MPS3-AN536. | ||
17 | |||
18 | For convenience of being able to run guest code, permit | ||
19 | this UNPREDICTABLE access instead of UNDEFing it. | ||
20 | |||
21 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
22 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
23 | Message-id: 20240206132931.38376-5-peter.maydell@linaro.org | ||
24 | --- | ||
25 | target/arm/tcg/op_helper.c | 43 ++++++++++++++++++++++++++------------ | ||
26 | target/arm/tcg/translate.c | 19 +++++++++++------ | ||
27 | 2 files changed, 43 insertions(+), 19 deletions(-) | ||
28 | |||
29 | diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c | ||
30 | index XXXXXXX..XXXXXXX 100644 | ||
31 | --- a/target/arm/tcg/op_helper.c | ||
32 | +++ b/target/arm/tcg/op_helper.c | ||
33 | @@ -XXX,XX +XXX,XX @@ static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode, | ||
34 | */ | ||
35 | int curmode = env->uncached_cpsr & CPSR_M; | ||
36 | |||
37 | - if (regno == 17) { | ||
38 | - /* ELR_Hyp: a special case because access from tgtmode is OK */ | ||
39 | - if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) { | ||
40 | - goto undef; | ||
41 | + if (tgtmode == ARM_CPU_MODE_HYP) { | ||
42 | + /* | ||
43 | + * Handle Hyp target regs first because some are special cases | ||
44 | + * which don't want the usual "not accessible from tgtmode" check. | ||
45 | + */ | ||
46 | + switch (regno) { | ||
47 | + case 16 ... 17: /* ELR_Hyp, SPSR_Hyp */ | ||
48 | + if (curmode != ARM_CPU_MODE_HYP && curmode != ARM_CPU_MODE_MON) { | ||
49 | + goto undef; | ||
50 | + } | ||
51 | + break; | ||
52 | + case 13: | ||
53 | + if (curmode != ARM_CPU_MODE_MON) { | ||
54 | + goto undef; | ||
55 | + } | ||
56 | + break; | ||
57 | + default: | ||
58 | + g_assert_not_reached(); | ||
59 | } | ||
60 | return; | ||
61 | } | ||
62 | @@ -XXX,XX +XXX,XX @@ static void msr_mrs_banked_exc_checks(CPUARMState *env, uint32_t tgtmode, | ||
63 | } | ||
64 | } | ||
65 | |||
66 | - if (tgtmode == ARM_CPU_MODE_HYP) { | ||
67 | - /* SPSR_Hyp, r13_hyp: accessible from Monitor mode only */ | ||
68 | - if (curmode != ARM_CPU_MODE_MON) { | ||
69 | - goto undef; | ||
70 | - } | ||
71 | - } | ||
72 | - | ||
73 | return; | ||
74 | |||
75 | undef: | ||
76 | @@ -XXX,XX +XXX,XX @@ void HELPER(msr_banked)(CPUARMState *env, uint32_t value, uint32_t tgtmode, | ||
77 | |||
78 | switch (regno) { | ||
79 | case 16: /* SPSRs */ | ||
80 | - env->banked_spsr[bank_number(tgtmode)] = value; | ||
81 | + if (tgtmode == (env->uncached_cpsr & CPSR_M)) { | ||
82 | + /* Only happens for SPSR_Hyp access in Hyp mode */ | ||
83 | + env->spsr = value; | ||
84 | + } else { | ||
85 | + env->banked_spsr[bank_number(tgtmode)] = value; | ||
86 | + } | ||
87 | break; | ||
88 | case 17: /* ELR_Hyp */ | ||
89 | env->elr_el[2] = value; | ||
90 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(mrs_banked)(CPUARMState *env, uint32_t tgtmode, uint32_t regno) | ||
91 | |||
92 | switch (regno) { | ||
93 | case 16: /* SPSRs */ | ||
94 | - return env->banked_spsr[bank_number(tgtmode)]; | ||
95 | + if (tgtmode == (env->uncached_cpsr & CPSR_M)) { | ||
96 | + /* Only happens for SPSR_Hyp access in Hyp mode */ | ||
97 | + return env->spsr; | ||
98 | + } else { | ||
99 | + return env->banked_spsr[bank_number(tgtmode)]; | ||
100 | + } | ||
101 | case 17: /* ELR_Hyp */ | ||
102 | return env->elr_el[2]; | ||
103 | case 13: | ||
104 | diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c | ||
105 | index XXXXXXX..XXXXXXX 100644 | ||
106 | --- a/target/arm/tcg/translate.c | ||
107 | +++ b/target/arm/tcg/translate.c | ||
108 | @@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn, | ||
109 | break; | ||
110 | case ARM_CPU_MODE_HYP: | ||
111 | /* | ||
112 | - * SPSR_hyp and r13_hyp can only be accessed from Monitor mode | ||
113 | - * (and so we can forbid accesses from EL2 or below). elr_hyp | ||
114 | - * can be accessed also from Hyp mode, so forbid accesses from | ||
115 | - * EL0 or EL1. | ||
116 | + * r13_hyp can only be accessed from Monitor mode, and so we | ||
117 | + * can forbid accesses from EL2 or below. | ||
118 | + * elr_hyp can be accessed also from Hyp mode, so forbid | ||
119 | + * accesses from EL0 or EL1. | ||
120 | + * SPSR_hyp is supposed to be in the same category as r13_hyp | ||
121 | + * and UNPREDICTABLE if accessed from anything except Monitor | ||
122 | + * mode. However there is some real-world code that will do | ||
123 | + * it because at least some hardware happens to permit the | ||
124 | + * access. (Notably a standard Cortex-R52 startup code fragment | ||
125 | + * does this.) So we permit SPSR_hyp from Hyp mode also, to allow | ||
126 | + * this (incorrect) guest code to run. | ||
127 | */ | ||
128 | - if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 2 || | ||
129 | - (s->current_el < 3 && *regno != 17)) { | ||
130 | + if (!arm_dc_feature(s, ARM_FEATURE_EL2) || s->current_el < 2 | ||
131 | + || (s->current_el < 3 && *regno != 16 && *regno != 17)) { | ||
132 | goto undef; | ||
133 | } | ||
134 | break; | ||
135 | -- | ||
136 | 2.34.1 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | We currently guard the CFG3 register read with |
---|---|---|---|
2 | (scc_partno(s) == 0x524 && scc_partno(s) == 0x547) | ||
3 | which is clearly wrong as it is never true. | ||
2 | 4 | ||
3 | Found by inspection: Rn is the base register against which the | 5 | This register is present on all board types except AN524 |
4 | load began; I is the register within the mask being processed. | 6 | and AN527; correct the condition. |
5 | The exception return should of course be processed from the loaded PC. | ||
6 | 7 | ||
7 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | 8 | Fixes: 6ac80818941829c0 ("hw/misc/mps2-scc: Implement changes for AN547") |
8 | Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> | ||
9 | Message-id: 20190301202921.21209-1-richard.henderson@linaro.org | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 9 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
10 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
11 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
12 | Message-id: 20240206132931.38376-6-peter.maydell@linaro.org | ||
11 | --- | 13 | --- |
12 | target/arm/translate.c | 2 +- | 14 | hw/misc/mps2-scc.c | 2 +- |
13 | 1 file changed, 1 insertion(+), 1 deletion(-) | 15 | 1 file changed, 1 insertion(+), 1 deletion(-) |
14 | 16 | ||
15 | diff --git a/target/arm/translate.c b/target/arm/translate.c | 17 | diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c |
16 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/target/arm/translate.c | 19 | --- a/hw/misc/mps2-scc.c |
18 | +++ b/target/arm/translate.c | 20 | +++ b/hw/misc/mps2-scc.c |
19 | @@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) | 21 | @@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size) |
20 | } else if (i == rn) { | 22 | r = s->cfg2; |
21 | loaded_var = tmp; | 23 | break; |
22 | loaded_base = 1; | 24 | case A_CFG3: |
23 | - } else if (rn == 15 && exc_return) { | 25 | - if (scc_partno(s) == 0x524 && scc_partno(s) == 0x547) { |
24 | + } else if (i == 15 && exc_return) { | 26 | + if (scc_partno(s) == 0x524 || scc_partno(s) == 0x547) { |
25 | store_pc_exc_ret(s, tmp); | 27 | /* CFG3 reserved on AN524 */ |
26 | } else { | 28 | goto bad_offset; |
27 | store_reg_from_load(s, i, tmp); | 29 | } |
28 | -- | 30 | -- |
29 | 2.20.1 | 31 | 2.34.1 |
30 | 32 | ||
31 | 33 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | The MPS SCC device has a lot of different flavours for the various |
---|---|---|---|
2 | different MPS FPGA images, which look mostly similar but have | ||
3 | differences in how particular registers are handled. Currently we | ||
4 | deal with this with a lot of open-coded checks on scc_partno(), but | ||
5 | as we add more board types this is getting a bit hard to read. | ||
2 | 6 | ||
3 | Add the kvm_arm_get_max_vm_ipa_size() helper that returns the | 7 | Factor out the conditions into some functions which we can |
4 | number of bits in the IPA address space supported by KVM. | 8 | give more descriptive names to. |
5 | 9 | ||
6 | This capability needs to be known to create the VM with a | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
7 | specific IPA max size (kvm_type passed along KVM_CREATE_VM ioctl. | 11 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
12 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
13 | Message-id: 20240206132931.38376-7-peter.maydell@linaro.org | ||
14 | --- | ||
15 | hw/misc/mps2-scc.c | 45 +++++++++++++++++++++++++++++++-------------- | ||
16 | 1 file changed, 31 insertions(+), 14 deletions(-) | ||
8 | 17 | ||
9 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | 18 | diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c |
10 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | ||
11 | Message-id: 20190304101339.25970-6-eric.auger@redhat.com | ||
12 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
13 | --- | ||
14 | target/arm/kvm_arm.h | 13 +++++++++++++ | ||
15 | target/arm/kvm.c | 10 ++++++++++ | ||
16 | 2 files changed, 23 insertions(+) | ||
17 | |||
18 | diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h | ||
19 | index XXXXXXX..XXXXXXX 100644 | 19 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/target/arm/kvm_arm.h | 20 | --- a/hw/misc/mps2-scc.c |
21 | +++ b/target/arm/kvm_arm.h | 21 | +++ b/hw/misc/mps2-scc.c |
22 | @@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf); | 22 | @@ -XXX,XX +XXX,XX @@ static int scc_partno(MPS2SCC *s) |
23 | */ | 23 | return extract32(s->id, 4, 8); |
24 | void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu); | ||
25 | |||
26 | +/** | ||
27 | + * kvm_arm_get_max_vm_ipa_size - Returns the number of bits in the | ||
28 | + * IPA address space supported by KVM | ||
29 | + * | ||
30 | + * @ms: Machine state handle | ||
31 | + */ | ||
32 | +int kvm_arm_get_max_vm_ipa_size(MachineState *ms); | ||
33 | + | ||
34 | /** | ||
35 | * kvm_arm_sync_mpstate_to_kvm | ||
36 | * @cpu: ARMCPU | ||
37 | @@ -XXX,XX +XXX,XX @@ static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) | ||
38 | cpu->host_cpu_probe_failed = true; | ||
39 | } | 24 | } |
40 | 25 | ||
41 | +static inline int kvm_arm_get_max_vm_ipa_size(MachineState *ms) | 26 | +/* Is CFG_REG2 present? */ |
27 | +static bool have_cfg2(MPS2SCC *s) | ||
42 | +{ | 28 | +{ |
43 | + return -ENOENT; | 29 | + return scc_partno(s) == 0x524 || scc_partno(s) == 0x547; |
44 | +} | 30 | +} |
45 | + | 31 | + |
46 | static inline int kvm_arm_vgic_probe(void) | 32 | +/* Is CFG_REG3 present? */ |
47 | { | 33 | +static bool have_cfg3(MPS2SCC *s) |
48 | return 0; | ||
49 | diff --git a/target/arm/kvm.c b/target/arm/kvm.c | ||
50 | index XXXXXXX..XXXXXXX 100644 | ||
51 | --- a/target/arm/kvm.c | ||
52 | +++ b/target/arm/kvm.c | ||
53 | @@ -XXX,XX +XXX,XX @@ | ||
54 | #include "qemu/error-report.h" | ||
55 | #include "sysemu/sysemu.h" | ||
56 | #include "sysemu/kvm.h" | ||
57 | +#include "sysemu/kvm_int.h" | ||
58 | #include "kvm_arm.h" | ||
59 | #include "cpu.h" | ||
60 | #include "trace.h" | ||
61 | @@ -XXX,XX +XXX,XX @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu) | ||
62 | env->features = arm_host_cpu_features.features; | ||
63 | } | ||
64 | |||
65 | +int kvm_arm_get_max_vm_ipa_size(MachineState *ms) | ||
66 | +{ | 34 | +{ |
67 | + KVMState *s = KVM_STATE(ms->accelerator); | 35 | + return scc_partno(s) != 0x524 && scc_partno(s) != 0x547; |
68 | + int ret; | ||
69 | + | ||
70 | + ret = kvm_check_extension(s, KVM_CAP_ARM_VM_IPA_SIZE); | ||
71 | + return ret > 0 ? ret : 40; | ||
72 | +} | 36 | +} |
73 | + | 37 | + |
74 | int kvm_arch_init(MachineState *ms, KVMState *s) | 38 | +/* Is CFG_REG5 present? */ |
75 | { | 39 | +static bool have_cfg5(MPS2SCC *s) |
76 | /* For ARM interrupt delivery is always asynchronous, | 40 | +{ |
41 | + return scc_partno(s) == 0x524 || scc_partno(s) == 0x547; | ||
42 | +} | ||
43 | + | ||
44 | +/* Is CFG_REG6 present? */ | ||
45 | +static bool have_cfg6(MPS2SCC *s) | ||
46 | +{ | ||
47 | + return scc_partno(s) == 0x524; | ||
48 | +} | ||
49 | + | ||
50 | /* Handle a write via the SYS_CFG channel to the specified function/device. | ||
51 | * Return false on error (reported to guest via SYS_CFGCTRL ERROR bit). | ||
52 | */ | ||
53 | @@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size) | ||
54 | r = s->cfg1; | ||
55 | break; | ||
56 | case A_CFG2: | ||
57 | - if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) { | ||
58 | - /* CFG2 reserved on other boards */ | ||
59 | + if (!have_cfg2(s)) { | ||
60 | goto bad_offset; | ||
61 | } | ||
62 | r = s->cfg2; | ||
63 | break; | ||
64 | case A_CFG3: | ||
65 | - if (scc_partno(s) == 0x524 || scc_partno(s) == 0x547) { | ||
66 | - /* CFG3 reserved on AN524 */ | ||
67 | + if (!have_cfg3(s)) { | ||
68 | goto bad_offset; | ||
69 | } | ||
70 | /* These are user-settable DIP switches on the board. We don't | ||
71 | @@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size) | ||
72 | r = s->cfg4; | ||
73 | break; | ||
74 | case A_CFG5: | ||
75 | - if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) { | ||
76 | - /* CFG5 reserved on other boards */ | ||
77 | + if (!have_cfg5(s)) { | ||
78 | goto bad_offset; | ||
79 | } | ||
80 | r = s->cfg5; | ||
81 | break; | ||
82 | case A_CFG6: | ||
83 | - if (scc_partno(s) != 0x524) { | ||
84 | - /* CFG6 reserved on other boards */ | ||
85 | + if (!have_cfg6(s)) { | ||
86 | goto bad_offset; | ||
87 | } | ||
88 | r = s->cfg6; | ||
89 | @@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value, | ||
90 | } | ||
91 | break; | ||
92 | case A_CFG2: | ||
93 | - if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) { | ||
94 | - /* CFG2 reserved on other boards */ | ||
95 | + if (!have_cfg2(s)) { | ||
96 | goto bad_offset; | ||
97 | } | ||
98 | /* AN524: QSPI Select signal */ | ||
99 | s->cfg2 = value; | ||
100 | break; | ||
101 | case A_CFG5: | ||
102 | - if (scc_partno(s) != 0x524 && scc_partno(s) != 0x547) { | ||
103 | - /* CFG5 reserved on other boards */ | ||
104 | + if (!have_cfg5(s)) { | ||
105 | goto bad_offset; | ||
106 | } | ||
107 | /* AN524: ACLK frequency in Hz */ | ||
108 | s->cfg5 = value; | ||
109 | break; | ||
110 | case A_CFG6: | ||
111 | - if (scc_partno(s) != 0x524) { | ||
112 | - /* CFG6 reserved on other boards */ | ||
113 | + if (!have_cfg6(s)) { | ||
114 | goto bad_offset; | ||
115 | } | ||
116 | /* AN524: Clock divider for BRAM */ | ||
77 | -- | 117 | -- |
78 | 2.20.1 | 118 | 2.34.1 |
79 | 119 | ||
80 | 120 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | The MPS2 SCC device is broadly the same for all FPGA images, but has | |
2 | minor differences in the behaviour of the CFG registers depending on | ||
3 | the image. In many cases we don't really care about the functionality | ||
4 | controlled by these registers and a reads-as-written or similar | ||
5 | behaviour is sufficient for the moment. | ||
6 | |||
7 | For the AN536 the required behaviour is: | ||
8 | |||
9 | * A_CFG0 has CPU reset and halt bits | ||
10 | - implement as reads-as-written for the moment | ||
11 | * A_CFG1 has flash or ATCM address 0 remap handling | ||
12 | - QEMU doesn't model this; implement as reads-as-written | ||
13 | * A_CFG2 has QSPI select (like AN524) | ||
14 | - implemented (no behaviour, as with AN524) | ||
15 | * A_CFG3 is MCC_MSB_ADDR "additional MCC addressing bits" | ||
16 | - QEMU doesn't care about these, so use the existing | ||
17 | RAZ behaviour for convenience | ||
18 | * A_CFG4 is board rev (like all other images) | ||
19 | - no change needed | ||
20 | * A_CFG5 is ACLK frq in hz (like AN524) | ||
21 | - implemented as reads-as-written, as for other boards | ||
22 | * A_CFG6 is core 0 vector table base address | ||
23 | - implemented as reads-as-written for the moment | ||
24 | * A_CFG7 is core 1 vector table base address | ||
25 | - implemented as reads-as-written for the moment | ||
26 | |||
27 | Make the changes necessary for this; leave TODO comments where | ||
28 | appropriate to indicate where we might want to come back and | ||
29 | implement things like CPU reset. | ||
30 | |||
31 | The other aspects of the device specific to this FPGA image (like the | ||
32 | values of the board ID and similar registers) will be set via the | ||
33 | device's qdev properties. | ||
34 | |||
35 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
36 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
37 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
38 | Message-id: 20240206132931.38376-8-peter.maydell@linaro.org | ||
39 | --- | ||
40 | include/hw/misc/mps2-scc.h | 1 + | ||
41 | hw/misc/mps2-scc.c | 101 +++++++++++++++++++++++++++++++++---- | ||
42 | 2 files changed, 92 insertions(+), 10 deletions(-) | ||
43 | |||
44 | diff --git a/include/hw/misc/mps2-scc.h b/include/hw/misc/mps2-scc.h | ||
45 | index XXXXXXX..XXXXXXX 100644 | ||
46 | --- a/include/hw/misc/mps2-scc.h | ||
47 | +++ b/include/hw/misc/mps2-scc.h | ||
48 | @@ -XXX,XX +XXX,XX @@ struct MPS2SCC { | ||
49 | uint32_t cfg4; | ||
50 | uint32_t cfg5; | ||
51 | uint32_t cfg6; | ||
52 | + uint32_t cfg7; | ||
53 | uint32_t cfgdata_rtn; | ||
54 | uint32_t cfgdata_out; | ||
55 | uint32_t cfgctrl; | ||
56 | diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c | ||
57 | index XXXXXXX..XXXXXXX 100644 | ||
58 | --- a/hw/misc/mps2-scc.c | ||
59 | +++ b/hw/misc/mps2-scc.c | ||
60 | @@ -XXX,XX +XXX,XX @@ REG32(CFG3, 0xc) | ||
61 | REG32(CFG4, 0x10) | ||
62 | REG32(CFG5, 0x14) | ||
63 | REG32(CFG6, 0x18) | ||
64 | +REG32(CFG7, 0x1c) | ||
65 | REG32(CFGDATA_RTN, 0xa0) | ||
66 | REG32(CFGDATA_OUT, 0xa4) | ||
67 | REG32(CFGCTRL, 0xa8) | ||
68 | @@ -XXX,XX +XXX,XX @@ static int scc_partno(MPS2SCC *s) | ||
69 | /* Is CFG_REG2 present? */ | ||
70 | static bool have_cfg2(MPS2SCC *s) | ||
71 | { | ||
72 | - return scc_partno(s) == 0x524 || scc_partno(s) == 0x547; | ||
73 | + return scc_partno(s) == 0x524 || scc_partno(s) == 0x547 || | ||
74 | + scc_partno(s) == 0x536; | ||
75 | } | ||
76 | |||
77 | /* Is CFG_REG3 present? */ | ||
78 | static bool have_cfg3(MPS2SCC *s) | ||
79 | { | ||
80 | - return scc_partno(s) != 0x524 && scc_partno(s) != 0x547; | ||
81 | + return scc_partno(s) != 0x524 && scc_partno(s) != 0x547 && | ||
82 | + scc_partno(s) != 0x536; | ||
83 | } | ||
84 | |||
85 | /* Is CFG_REG5 present? */ | ||
86 | static bool have_cfg5(MPS2SCC *s) | ||
87 | { | ||
88 | - return scc_partno(s) == 0x524 || scc_partno(s) == 0x547; | ||
89 | + return scc_partno(s) == 0x524 || scc_partno(s) == 0x547 || | ||
90 | + scc_partno(s) == 0x536; | ||
91 | } | ||
92 | |||
93 | /* Is CFG_REG6 present? */ | ||
94 | static bool have_cfg6(MPS2SCC *s) | ||
95 | { | ||
96 | - return scc_partno(s) == 0x524; | ||
97 | + return scc_partno(s) == 0x524 || scc_partno(s) == 0x536; | ||
98 | +} | ||
99 | + | ||
100 | +/* Is CFG_REG7 present? */ | ||
101 | +static bool have_cfg7(MPS2SCC *s) | ||
102 | +{ | ||
103 | + return scc_partno(s) == 0x536; | ||
104 | +} | ||
105 | + | ||
106 | +/* Does CFG_REG0 drive the 'remap' GPIO output? */ | ||
107 | +static bool cfg0_is_remap(MPS2SCC *s) | ||
108 | +{ | ||
109 | + return scc_partno(s) != 0x536; | ||
110 | +} | ||
111 | + | ||
112 | +/* Is CFG_REG1 driving a set of LEDs? */ | ||
113 | +static bool cfg1_is_leds(MPS2SCC *s) | ||
114 | +{ | ||
115 | + return scc_partno(s) != 0x536; | ||
116 | } | ||
117 | |||
118 | /* Handle a write via the SYS_CFG channel to the specified function/device. | ||
119 | @@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size) | ||
120 | if (!have_cfg3(s)) { | ||
121 | goto bad_offset; | ||
122 | } | ||
123 | - /* These are user-settable DIP switches on the board. We don't | ||
124 | + /* | ||
125 | + * These are user-settable DIP switches on the board. We don't | ||
126 | * model that, so just return zeroes. | ||
127 | + * | ||
128 | + * TODO: for AN536 this is MCC_MSB_ADDR "additional MCC addressing | ||
129 | + * bits". These change which part of the DDR4 the motherboard | ||
130 | + * configuration controller can see in its memory map (see the | ||
131 | + * appnote section 2.4). QEMU doesn't model the MCC at all, so these | ||
132 | + * bits are not interesting to us; read-as-zero is as good as anything | ||
133 | + * else. | ||
134 | */ | ||
135 | r = 0; | ||
136 | break; | ||
137 | @@ -XXX,XX +XXX,XX @@ static uint64_t mps2_scc_read(void *opaque, hwaddr offset, unsigned size) | ||
138 | } | ||
139 | r = s->cfg6; | ||
140 | break; | ||
141 | + case A_CFG7: | ||
142 | + if (!have_cfg7(s)) { | ||
143 | + goto bad_offset; | ||
144 | + } | ||
145 | + r = s->cfg7; | ||
146 | + break; | ||
147 | case A_CFGDATA_RTN: | ||
148 | r = s->cfgdata_rtn; | ||
149 | break; | ||
150 | @@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value, | ||
151 | * we always reflect bit 0 in the 'remap' GPIO output line, | ||
152 | * and let the board wire it up or not as it chooses. | ||
153 | * TODO on some boards bit 1 is CPU_WAIT. | ||
154 | + * | ||
155 | + * TODO: on the AN536 this register controls reset and halt | ||
156 | + * for both CPUs. For the moment we don't implement this, so the | ||
157 | + * register just reads as written. | ||
158 | */ | ||
159 | s->cfg0 = value; | ||
160 | - qemu_set_irq(s->remap, s->cfg0 & 1); | ||
161 | + if (cfg0_is_remap(s)) { | ||
162 | + qemu_set_irq(s->remap, s->cfg0 & 1); | ||
163 | + } | ||
164 | break; | ||
165 | case A_CFG1: | ||
166 | s->cfg1 = value; | ||
167 | - for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) { | ||
168 | - led_set_state(s->led[i], extract32(value, i, 1)); | ||
169 | + /* | ||
170 | + * On most boards this register drives LEDs. | ||
171 | + * | ||
172 | + * TODO: for AN536 this controls whether flash and ATCM are | ||
173 | + * enabled or disabled on reset. QEMU doesn't model this, and | ||
174 | + * always wires up RAM in the ATCM area and ROM in the flash area. | ||
175 | + */ | ||
176 | + if (cfg1_is_leds(s)) { | ||
177 | + for (size_t i = 0; i < ARRAY_SIZE(s->led); i++) { | ||
178 | + led_set_state(s->led[i], extract32(value, i, 1)); | ||
179 | + } | ||
180 | } | ||
181 | break; | ||
182 | case A_CFG2: | ||
183 | if (!have_cfg2(s)) { | ||
184 | goto bad_offset; | ||
185 | } | ||
186 | - /* AN524: QSPI Select signal */ | ||
187 | + /* AN524, AN536: QSPI Select signal */ | ||
188 | s->cfg2 = value; | ||
189 | break; | ||
190 | case A_CFG5: | ||
191 | if (!have_cfg5(s)) { | ||
192 | goto bad_offset; | ||
193 | } | ||
194 | - /* AN524: ACLK frequency in Hz */ | ||
195 | + /* AN524, AN536: ACLK frequency in Hz */ | ||
196 | s->cfg5 = value; | ||
197 | break; | ||
198 | case A_CFG6: | ||
199 | @@ -XXX,XX +XXX,XX @@ static void mps2_scc_write(void *opaque, hwaddr offset, uint64_t value, | ||
200 | goto bad_offset; | ||
201 | } | ||
202 | /* AN524: Clock divider for BRAM */ | ||
203 | + /* AN536: Core 0 vector table base address */ | ||
204 | + s->cfg6 = value; | ||
205 | + break; | ||
206 | + case A_CFG7: | ||
207 | + if (!have_cfg7(s)) { | ||
208 | + goto bad_offset; | ||
209 | + } | ||
210 | + /* AN536: Core 1 vector table base address */ | ||
211 | s->cfg6 = value; | ||
212 | break; | ||
213 | case A_CFGDATA_OUT: | ||
214 | @@ -XXX,XX +XXX,XX @@ static void mps2_scc_finalize(Object *obj) | ||
215 | g_free(s->oscclk_reset); | ||
216 | } | ||
217 | |||
218 | +static bool cfg7_needed(void *opaque) | ||
219 | +{ | ||
220 | + MPS2SCC *s = opaque; | ||
221 | + | ||
222 | + return have_cfg7(s); | ||
223 | +} | ||
224 | + | ||
225 | +static const VMStateDescription vmstate_cfg7 = { | ||
226 | + .name = "mps2-scc/cfg7", | ||
227 | + .version_id = 1, | ||
228 | + .minimum_version_id = 1, | ||
229 | + .needed = cfg7_needed, | ||
230 | + .fields = (const VMStateField[]) { | ||
231 | + VMSTATE_UINT32(cfg7, MPS2SCC), | ||
232 | + VMSTATE_END_OF_LIST() | ||
233 | + } | ||
234 | +}; | ||
235 | + | ||
236 | static const VMStateDescription mps2_scc_vmstate = { | ||
237 | .name = "mps2-scc", | ||
238 | .version_id = 3, | ||
239 | @@ -XXX,XX +XXX,XX @@ static const VMStateDescription mps2_scc_vmstate = { | ||
240 | VMSTATE_VARRAY_UINT32(oscclk, MPS2SCC, num_oscclk, | ||
241 | 0, vmstate_info_uint32, uint32_t), | ||
242 | VMSTATE_END_OF_LIST() | ||
243 | + }, | ||
244 | + .subsections = (const VMStateDescription * const []) { | ||
245 | + &vmstate_cfg7, | ||
246 | + NULL | ||
247 | } | ||
248 | }; | ||
249 | |||
250 | -- | ||
251 | 2.34.1 | ||
252 | |||
253 | diff view generated by jsdifflib |
New patch | |||
---|---|---|---|
1 | 1 | The AN536 is another FPGA image for the MPS3 development board. Unlike | |
2 | the existing FPGA images we already model, this board uses a Cortex-R | ||
3 | family CPU, and it does not use any equivalent to the M-profile | ||
4 | "Subsystem for Embedded" SoC-equivalent that we model in hw/arm/armsse.c. | ||
5 | It's therefore more convenient for us to model it as a completely | ||
6 | separate C file. | ||
7 | |||
8 | This commit adds the basic skeleton of the board model, and the | ||
9 | code to create all the RAM and ROM. We assume that we're probably | ||
10 | going to want to add more images in future, so use the same | ||
11 | base class/subclass setup that mps2-tz.c uses, even though at | ||
12 | the moment there's only a single subclass. | ||
13 | |||
14 | Following commits will add the CPUs and the peripherals. | ||
15 | |||
16 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
17 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
18 | Message-id: 20240206132931.38376-9-peter.maydell@linaro.org | ||
19 | --- | ||
20 | MAINTAINERS | 3 +- | ||
21 | configs/devices/arm-softmmu/default.mak | 1 + | ||
22 | hw/arm/mps3r.c | 239 ++++++++++++++++++++++++ | ||
23 | hw/arm/Kconfig | 5 + | ||
24 | hw/arm/meson.build | 1 + | ||
25 | 5 files changed, 248 insertions(+), 1 deletion(-) | ||
26 | create mode 100644 hw/arm/mps3r.c | ||
27 | |||
28 | diff --git a/MAINTAINERS b/MAINTAINERS | ||
29 | index XXXXXXX..XXXXXXX 100644 | ||
30 | --- a/MAINTAINERS | ||
31 | +++ b/MAINTAINERS | ||
32 | @@ -XXX,XX +XXX,XX @@ F: include/hw/misc/imx7_*.h | ||
33 | F: hw/pci-host/designware.c | ||
34 | F: include/hw/pci-host/designware.h | ||
35 | |||
36 | -MPS2 | ||
37 | +MPS2 / MPS3 | ||
38 | M: Peter Maydell <peter.maydell@linaro.org> | ||
39 | L: qemu-arm@nongnu.org | ||
40 | S: Maintained | ||
41 | F: hw/arm/mps2.c | ||
42 | F: hw/arm/mps2-tz.c | ||
43 | +F: hw/arm/mps3r.c | ||
44 | F: hw/misc/mps2-*.c | ||
45 | F: include/hw/misc/mps2-*.h | ||
46 | F: hw/arm/armsse.c | ||
47 | diff --git a/configs/devices/arm-softmmu/default.mak b/configs/devices/arm-softmmu/default.mak | ||
48 | index XXXXXXX..XXXXXXX 100644 | ||
49 | --- a/configs/devices/arm-softmmu/default.mak | ||
50 | +++ b/configs/devices/arm-softmmu/default.mak | ||
51 | @@ -XXX,XX +XXX,XX @@ CONFIG_ARM_VIRT=y | ||
52 | # CONFIG_INTEGRATOR=n | ||
53 | # CONFIG_FSL_IMX31=n | ||
54 | # CONFIG_MUSICPAL=n | ||
55 | +# CONFIG_MPS3R=n | ||
56 | # CONFIG_MUSCA=n | ||
57 | # CONFIG_CHEETAH=n | ||
58 | # CONFIG_SX1=n | ||
59 | diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c | ||
60 | new file mode 100644 | ||
61 | index XXXXXXX..XXXXXXX | ||
62 | --- /dev/null | ||
63 | +++ b/hw/arm/mps3r.c | ||
64 | @@ -XXX,XX +XXX,XX @@ | ||
65 | +/* | ||
66 | + * Arm MPS3 board emulation for Cortex-R-based FPGA images. | ||
67 | + * (For M-profile images see mps2.c and mps2tz.c.) | ||
68 | + * | ||
69 | + * Copyright (c) 2017 Linaro Limited | ||
70 | + * Written by Peter Maydell | ||
71 | + * | ||
72 | + * This program is free software; you can redistribute it and/or modify | ||
73 | + * it under the terms of the GNU General Public License version 2 or | ||
74 | + * (at your option) any later version. | ||
75 | + */ | ||
76 | + | ||
77 | +/* | ||
78 | + * The MPS3 is an FPGA based dev board. This file handles FPGA images | ||
79 | + * which use the Cortex-R CPUs. We model these separately from the | ||
80 | + * M-profile images, because on M-profile the FPGA image is based on | ||
81 | + * a "Subsystem for Embedded" which is similar to an SoC, whereas | ||
82 | + * the R-profile FPGA images don't have that abstraction layer. | ||
83 | + * | ||
84 | + * We model the following FPGA images here: | ||
85 | + * "mps3-an536" -- dual Cortex-R52 as documented in Arm Application Note AN536 | ||
86 | + * | ||
87 | + * Application Note AN536: | ||
88 | + * https://developer.arm.com/documentation/dai0536/latest/ | ||
89 | + */ | ||
90 | + | ||
91 | +#include "qemu/osdep.h" | ||
92 | +#include "qemu/units.h" | ||
93 | +#include "qapi/error.h" | ||
94 | +#include "exec/address-spaces.h" | ||
95 | +#include "cpu.h" | ||
96 | +#include "hw/boards.h" | ||
97 | +#include "hw/arm/boot.h" | ||
98 | + | ||
99 | +/* Define the layout of RAM and ROM in a board */ | ||
100 | +typedef struct RAMInfo { | ||
101 | + const char *name; | ||
102 | + hwaddr base; | ||
103 | + hwaddr size; | ||
104 | + int mrindex; /* index into rams[]; -1 for the system RAM block */ | ||
105 | + int flags; | ||
106 | +} RAMInfo; | ||
107 | + | ||
108 | +/* | ||
109 | + * The MPS3 DDR is 3GiB, but on a 32-bit host QEMU doesn't permit | ||
110 | + * emulation of that much guest RAM, so artificially make it smaller. | ||
111 | + */ | ||
112 | +#if HOST_LONG_BITS == 32 | ||
113 | +#define MPS3_DDR_SIZE (1 * GiB) | ||
114 | +#else | ||
115 | +#define MPS3_DDR_SIZE (3 * GiB) | ||
116 | +#endif | ||
117 | + | ||
118 | +/* | ||
119 | + * Flag values: | ||
120 | + * IS_MAIN: this is the main machine RAM | ||
121 | + * IS_ROM: this area is read-only | ||
122 | + */ | ||
123 | +#define IS_MAIN 1 | ||
124 | +#define IS_ROM 2 | ||
125 | + | ||
126 | +#define MPS3R_RAM_MAX 9 | ||
127 | + | ||
128 | +typedef enum MPS3RFPGAType { | ||
129 | + FPGA_AN536, | ||
130 | +} MPS3RFPGAType; | ||
131 | + | ||
132 | +struct MPS3RMachineClass { | ||
133 | + MachineClass parent; | ||
134 | + MPS3RFPGAType fpga_type; | ||
135 | + const RAMInfo *raminfo; | ||
136 | +}; | ||
137 | + | ||
138 | +struct MPS3RMachineState { | ||
139 | + MachineState parent; | ||
140 | + MemoryRegion ram[MPS3R_RAM_MAX]; | ||
141 | +}; | ||
142 | + | ||
143 | +#define TYPE_MPS3R_MACHINE "mps3r" | ||
144 | +#define TYPE_MPS3R_AN536_MACHINE MACHINE_TYPE_NAME("mps3-an536") | ||
145 | + | ||
146 | +OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE) | ||
147 | + | ||
148 | +static const RAMInfo an536_raminfo[] = { | ||
149 | + { | ||
150 | + .name = "ATCM", | ||
151 | + .base = 0x00000000, | ||
152 | + .size = 0x00008000, | ||
153 | + .mrindex = 0, | ||
154 | + }, { | ||
155 | + /* We model the QSPI flash as simple ROM for now */ | ||
156 | + .name = "QSPI", | ||
157 | + .base = 0x08000000, | ||
158 | + .size = 0x00800000, | ||
159 | + .flags = IS_ROM, | ||
160 | + .mrindex = 1, | ||
161 | + }, { | ||
162 | + .name = "BRAM", | ||
163 | + .base = 0x10000000, | ||
164 | + .size = 0x00080000, | ||
165 | + .mrindex = 2, | ||
166 | + }, { | ||
167 | + .name = "DDR", | ||
168 | + .base = 0x20000000, | ||
169 | + .size = MPS3_DDR_SIZE, | ||
170 | + .mrindex = -1, | ||
171 | + }, { | ||
172 | + .name = "ATCM0", | ||
173 | + .base = 0xee000000, | ||
174 | + .size = 0x00008000, | ||
175 | + .mrindex = 3, | ||
176 | + }, { | ||
177 | + .name = "BTCM0", | ||
178 | + .base = 0xee100000, | ||
179 | + .size = 0x00008000, | ||
180 | + .mrindex = 4, | ||
181 | + }, { | ||
182 | + .name = "CTCM0", | ||
183 | + .base = 0xee200000, | ||
184 | + .size = 0x00008000, | ||
185 | + .mrindex = 5, | ||
186 | + }, { | ||
187 | + .name = "ATCM1", | ||
188 | + .base = 0xee400000, | ||
189 | + .size = 0x00008000, | ||
190 | + .mrindex = 6, | ||
191 | + }, { | ||
192 | + .name = "BTCM1", | ||
193 | + .base = 0xee500000, | ||
194 | + .size = 0x00008000, | ||
195 | + .mrindex = 7, | ||
196 | + }, { | ||
197 | + .name = "CTCM1", | ||
198 | + .base = 0xee600000, | ||
199 | + .size = 0x00008000, | ||
200 | + .mrindex = 8, | ||
201 | + }, { | ||
202 | + .name = NULL, | ||
203 | + } | ||
204 | +}; | ||
205 | + | ||
206 | +static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms, | ||
207 | + const RAMInfo *raminfo) | ||
208 | +{ | ||
209 | + /* Return an initialized MemoryRegion for the RAMInfo. */ | ||
210 | + MemoryRegion *ram; | ||
211 | + | ||
212 | + if (raminfo->mrindex < 0) { | ||
213 | + /* Means this RAMInfo is for QEMU's "system memory" */ | ||
214 | + MachineState *machine = MACHINE(mms); | ||
215 | + assert(!(raminfo->flags & IS_ROM)); | ||
216 | + return machine->ram; | ||
217 | + } | ||
218 | + | ||
219 | + assert(raminfo->mrindex < MPS3R_RAM_MAX); | ||
220 | + ram = &mms->ram[raminfo->mrindex]; | ||
221 | + | ||
222 | + memory_region_init_ram(ram, NULL, raminfo->name, | ||
223 | + raminfo->size, &error_fatal); | ||
224 | + if (raminfo->flags & IS_ROM) { | ||
225 | + memory_region_set_readonly(ram, true); | ||
226 | + } | ||
227 | + return ram; | ||
228 | +} | ||
229 | + | ||
230 | +static void mps3r_common_init(MachineState *machine) | ||
231 | +{ | ||
232 | + MPS3RMachineState *mms = MPS3R_MACHINE(machine); | ||
233 | + MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms); | ||
234 | + MemoryRegion *sysmem = get_system_memory(); | ||
235 | + | ||
236 | + for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) { | ||
237 | + MemoryRegion *mr = mr_for_raminfo(mms, ri); | ||
238 | + memory_region_add_subregion(sysmem, ri->base, mr); | ||
239 | + } | ||
240 | +} | ||
241 | + | ||
242 | +static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc) | ||
243 | +{ | ||
244 | + /* | ||
245 | + * Set mc->default_ram_size and default_ram_id from the | ||
246 | + * information in mmc->raminfo. | ||
247 | + */ | ||
248 | + MachineClass *mc = MACHINE_CLASS(mmc); | ||
249 | + const RAMInfo *p; | ||
250 | + | ||
251 | + for (p = mmc->raminfo; p->name; p++) { | ||
252 | + if (p->mrindex < 0) { | ||
253 | + /* Found the entry for "system memory" */ | ||
254 | + mc->default_ram_size = p->size; | ||
255 | + mc->default_ram_id = p->name; | ||
256 | + return; | ||
257 | + } | ||
258 | + } | ||
259 | + g_assert_not_reached(); | ||
260 | +} | ||
261 | + | ||
262 | +static void mps3r_class_init(ObjectClass *oc, void *data) | ||
263 | +{ | ||
264 | + MachineClass *mc = MACHINE_CLASS(oc); | ||
265 | + | ||
266 | + mc->init = mps3r_common_init; | ||
267 | +} | ||
268 | + | ||
269 | +static void mps3r_an536_class_init(ObjectClass *oc, void *data) | ||
270 | +{ | ||
271 | + MachineClass *mc = MACHINE_CLASS(oc); | ||
272 | + MPS3RMachineClass *mmc = MPS3R_MACHINE_CLASS(oc); | ||
273 | + static const char * const valid_cpu_types[] = { | ||
274 | + ARM_CPU_TYPE_NAME("cortex-r52"), | ||
275 | + NULL | ||
276 | + }; | ||
277 | + | ||
278 | + mc->desc = "ARM MPS3 with AN536 FPGA image for Cortex-R52"; | ||
279 | + mc->default_cpus = 2; | ||
280 | + mc->min_cpus = mc->default_cpus; | ||
281 | + mc->max_cpus = mc->default_cpus; | ||
282 | + mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r52"); | ||
283 | + mc->valid_cpu_types = valid_cpu_types; | ||
284 | + mmc->raminfo = an536_raminfo; | ||
285 | + mps3r_set_default_ram_info(mmc); | ||
286 | +} | ||
287 | + | ||
288 | +static const TypeInfo mps3r_machine_types[] = { | ||
289 | + { | ||
290 | + .name = TYPE_MPS3R_MACHINE, | ||
291 | + .parent = TYPE_MACHINE, | ||
292 | + .abstract = true, | ||
293 | + .instance_size = sizeof(MPS3RMachineState), | ||
294 | + .class_size = sizeof(MPS3RMachineClass), | ||
295 | + .class_init = mps3r_class_init, | ||
296 | + }, { | ||
297 | + .name = TYPE_MPS3R_AN536_MACHINE, | ||
298 | + .parent = TYPE_MPS3R_MACHINE, | ||
299 | + .class_init = mps3r_an536_class_init, | ||
300 | + }, | ||
301 | +}; | ||
302 | + | ||
303 | +DEFINE_TYPES(mps3r_machine_types); | ||
304 | diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig | ||
305 | index XXXXXXX..XXXXXXX 100644 | ||
306 | --- a/hw/arm/Kconfig | ||
307 | +++ b/hw/arm/Kconfig | ||
308 | @@ -XXX,XX +XXX,XX @@ config MAINSTONE | ||
309 | select PFLASH_CFI01 | ||
310 | select SMC91C111 | ||
311 | |||
312 | +config MPS3R | ||
313 | + bool | ||
314 | + default y | ||
315 | + depends on TCG && ARM | ||
316 | + | ||
317 | config MUSCA | ||
318 | bool | ||
319 | default y | ||
320 | diff --git a/hw/arm/meson.build b/hw/arm/meson.build | ||
321 | index XXXXXXX..XXXXXXX 100644 | ||
322 | --- a/hw/arm/meson.build | ||
323 | +++ b/hw/arm/meson.build | ||
324 | @@ -XXX,XX +XXX,XX @@ arm_ss.add(when: 'CONFIG_HIGHBANK', if_true: files('highbank.c')) | ||
325 | arm_ss.add(when: 'CONFIG_INTEGRATOR', if_true: files('integratorcp.c')) | ||
326 | arm_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mainstone.c')) | ||
327 | arm_ss.add(when: 'CONFIG_MICROBIT', if_true: files('microbit.c')) | ||
328 | +arm_ss.add(when: 'CONFIG_MPS3R', if_true: files('mps3r.c')) | ||
329 | arm_ss.add(when: 'CONFIG_MUSICPAL', if_true: files('musicpal.c')) | ||
330 | arm_ss.add(when: 'CONFIG_NETDUINOPLUS2', if_true: files('netduinoplus2.c')) | ||
331 | arm_ss.add(when: 'CONFIG_OLIMEX_STM32_H405', if_true: files('olimex-stm32-h405.c')) | ||
332 | -- | ||
333 | 2.34.1 | ||
334 | |||
335 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | Create the CPUs, the GIC, and the per-CPU RAM block for |
---|---|---|---|
2 | the mps3-an536 board. | ||
2 | 3 | ||
3 | In the prospect to introduce an extended memory map supporting more | 4 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | RAM, let's split the memory map array into two parts: | 5 | Message-id: 20240206132931.38376-10-peter.maydell@linaro.org |
6 | --- | ||
7 | hw/arm/mps3r.c | 180 ++++++++++++++++++++++++++++++++++++++++++++++++- | ||
8 | 1 file changed, 177 insertions(+), 3 deletions(-) | ||
5 | 9 | ||
6 | - the former a15memmap, renamed base_memmap, contains regions below | 10 | diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c |
7 | and including the RAM. MemMapEntries initialized in this array | ||
8 | have a static size and base address. | ||
9 | - extended_memmap, only initialized with entries located after the | ||
10 | RAM. MemMapEntries initialized in this array only get their size | ||
11 | initialized. Their base address is dynamically computed depending | ||
12 | on the the top of the RAM, with same alignment as their size. | ||
13 | |||
14 | Eventually base_memmap entries are copied into the extended_memmap | ||
15 | array. Using two separate arrays however clarifies which entries | ||
16 | are statically allocated and those which are dynamically allocated. | ||
17 | |||
18 | This new split will allow to grow the RAM size without changing the | ||
19 | description of the high IO entries. | ||
20 | |||
21 | We introduce a new virt_set_memmap() helper function which | ||
22 | "freezes" the memory map. We call it in machvirt_init as | ||
23 | memory attributes of the machine are not yet set when | ||
24 | virt_instance_init() gets called. | ||
25 | |||
26 | The memory map is unchanged (the top of the initial RAM still is | ||
27 | 256GiB). Then come the high IO regions with same layout as before. | ||
28 | |||
29 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
30 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | ||
31 | Message-id: 20190304101339.25970-4-eric.auger@redhat.com | ||
32 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
33 | --- | ||
34 | include/hw/arm/virt.h | 13 +++++++---- | ||
35 | hw/arm/virt.c | 50 +++++++++++++++++++++++++++++++++++++------ | ||
36 | 2 files changed, 53 insertions(+), 10 deletions(-) | ||
37 | |||
38 | diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h | ||
39 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
40 | --- a/include/hw/arm/virt.h | 12 | --- a/hw/arm/mps3r.c |
41 | +++ b/include/hw/arm/virt.h | 13 | +++ b/hw/arm/mps3r.c |
42 | @@ -XXX,XX +XXX,XX @@ enum { | 14 | @@ -XXX,XX +XXX,XX @@ |
43 | VIRT_GIC_VCPU, | 15 | #include "qemu/osdep.h" |
44 | VIRT_GIC_ITS, | 16 | #include "qemu/units.h" |
45 | VIRT_GIC_REDIST, | 17 | #include "qapi/error.h" |
46 | - VIRT_HIGH_GIC_REDIST2, | 18 | +#include "qapi/qmp/qlist.h" |
47 | VIRT_SMMU, | 19 | #include "exec/address-spaces.h" |
48 | VIRT_UART, | 20 | #include "cpu.h" |
49 | VIRT_MMIO, | 21 | #include "hw/boards.h" |
50 | @@ -XXX,XX +XXX,XX @@ enum { | 22 | +#include "hw/qdev-properties.h" |
51 | VIRT_PCIE_MMIO, | 23 | #include "hw/arm/boot.h" |
52 | VIRT_PCIE_PIO, | 24 | +#include "hw/arm/bsa.h" |
53 | VIRT_PCIE_ECAM, | 25 | +#include "hw/intc/arm_gicv3.h" |
54 | - VIRT_HIGH_PCIE_ECAM, | 26 | |
55 | VIRT_PLATFORM_BUS, | 27 | /* Define the layout of RAM and ROM in a board */ |
56 | - VIRT_HIGH_PCIE_MMIO, | 28 | typedef struct RAMInfo { |
57 | VIRT_GPIO, | 29 | @@ -XXX,XX +XXX,XX @@ typedef struct RAMInfo { |
58 | VIRT_SECURE_UART, | 30 | #define IS_ROM 2 |
59 | VIRT_SECURE_MEM, | 31 | |
60 | + VIRT_LOWMEMMAP_LAST, | 32 | #define MPS3R_RAM_MAX 9 |
61 | +}; | 33 | +#define MPS3R_CPU_MAX 2 |
62 | + | 34 | + |
63 | +/* indices of IO regions located after the RAM */ | 35 | +#define PERIPHBASE 0xf0000000 |
64 | +enum { | 36 | +#define NUM_SPIS 96 |
65 | + VIRT_HIGH_GIC_REDIST2 = VIRT_LOWMEMMAP_LAST, | 37 | |
66 | + VIRT_HIGH_PCIE_ECAM, | 38 | typedef enum MPS3RFPGAType { |
67 | + VIRT_HIGH_PCIE_MMIO, | 39 | FPGA_AN536, |
40 | @@ -XXX,XX +XXX,XX @@ struct MPS3RMachineClass { | ||
41 | MachineClass parent; | ||
42 | MPS3RFPGAType fpga_type; | ||
43 | const RAMInfo *raminfo; | ||
44 | + hwaddr loader_start; | ||
68 | }; | 45 | }; |
69 | 46 | ||
70 | typedef enum VirtIOMMUType { | 47 | struct MPS3RMachineState { |
71 | @@ -XXX,XX +XXX,XX @@ typedef struct { | 48 | MachineState parent; |
72 | int32_t gic_version; | 49 | + struct arm_boot_info bootinfo; |
73 | VirtIOMMUType iommu; | 50 | MemoryRegion ram[MPS3R_RAM_MAX]; |
74 | struct arm_boot_info bootinfo; | 51 | + Object *cpu[MPS3R_CPU_MAX]; |
75 | - const MemMapEntry *memmap; | 52 | + MemoryRegion cpu_sysmem[MPS3R_CPU_MAX]; |
76 | + MemMapEntry *memmap; | 53 | + MemoryRegion sysmem_alias[MPS3R_CPU_MAX]; |
77 | const int *irqmap; | 54 | + MemoryRegion cpu_ram[MPS3R_CPU_MAX]; |
78 | int smp_cpus; | 55 | + GICv3State gic; |
79 | void *fdt; | 56 | }; |
80 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | 57 | |
81 | index XXXXXXX..XXXXXXX 100644 | 58 | #define TYPE_MPS3R_MACHINE "mps3r" |
82 | --- a/hw/arm/virt.c | 59 | @@ -XXX,XX +XXX,XX @@ static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms, |
83 | +++ b/hw/arm/virt.c | 60 | return ram; |
84 | @@ -XXX,XX +XXX,XX @@ | 61 | } |
85 | */ | 62 | |
86 | |||
87 | #include "qemu/osdep.h" | ||
88 | +#include "qemu/units.h" | ||
89 | #include "qapi/error.h" | ||
90 | #include "hw/sysbus.h" | ||
91 | #include "hw/arm/arm.h" | ||
92 | @@ -XXX,XX +XXX,XX @@ | ||
93 | * Note that devices should generally be placed at multiples of 0x10000, | ||
94 | * to accommodate guests using 64K pages. | ||
95 | */ | ||
96 | -static const MemMapEntry a15memmap[] = { | ||
97 | +static const MemMapEntry base_memmap[] = { | ||
98 | /* Space up to 0x8000000 is reserved for a boot ROM */ | ||
99 | [VIRT_FLASH] = { 0, 0x08000000 }, | ||
100 | [VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 }, | ||
101 | @@ -XXX,XX +XXX,XX @@ static const MemMapEntry a15memmap[] = { | ||
102 | [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, | ||
103 | [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, | ||
104 | [VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES }, | ||
105 | +}; | ||
106 | + | ||
107 | +/* | 63 | +/* |
108 | + * Highmem IO Regions: This memory map is floating, located after the RAM. | 64 | + * There is no defined secondary boot protocol for Linux for the AN536, |
109 | + * Each MemMapEntry base (GPA) will be dynamically computed, depending on the | 65 | + * because real hardware has a restriction that atomic operations between |
110 | + * top of the RAM, so that its base get the same alignment as the size, | 66 | + * the two CPUs do not function correctly, and so true SMP is not |
111 | + * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is | 67 | + * possible. Therefore for cases where the user is directly booting |
112 | + * less than 256GiB of RAM, the floating area starts at the 256GiB mark. | 68 | + * a kernel, we treat the system as essentially uniprocessor, and |
113 | + * Note the extended_memmap is sized so that it eventually also includes the | 69 | + * put the secondary CPU into power-off state (as if the user on the |
114 | + * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last | 70 | + * real hardware had configured the secondary to be halted via the |
115 | + * index of base_memmap). | 71 | + * SCC config registers). |
72 | + * | ||
73 | + * Note that the default secondary boot code would not work here anyway | ||
74 | + * as it assumes a GICv2, and we have a GICv3. | ||
116 | + */ | 75 | + */ |
117 | +static MemMapEntry extended_memmap[] = { | 76 | +static void mps3r_write_secondary_boot(ARMCPU *cpu, |
118 | /* Additional 64 MB redist region (can contain up to 512 redistributors) */ | 77 | + const struct arm_boot_info *info) |
119 | - [VIRT_HIGH_GIC_REDIST2] = { 0x4000000000ULL, 0x4000000 }, | ||
120 | - [VIRT_HIGH_PCIE_ECAM] = { 0x4010000000ULL, 0x10000000 }, | ||
121 | - /* Second PCIe window, 512GB wide at the 512GB boundary */ | ||
122 | - [VIRT_HIGH_PCIE_MMIO] = { 0x8000000000ULL, 0x8000000000ULL }, | ||
123 | + [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB }, | ||
124 | + [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB }, | ||
125 | + /* Second PCIe window */ | ||
126 | + [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB }, | ||
127 | }; | ||
128 | |||
129 | static const int a15irqmap[] = { | ||
130 | @@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) | ||
131 | return arm_cpu_mp_affinity(idx, clustersz); | ||
132 | } | ||
133 | |||
134 | +static void virt_set_memmap(VirtMachineState *vms) | ||
135 | +{ | 78 | +{ |
136 | + hwaddr base; | 79 | + /* |
137 | + int i; | 80 | + * Power the secondary CPU off. This means we don't need to write any |
138 | + | 81 | + * boot code into guest memory. Note that the 'cpu' argument to this |
139 | + vms->memmap = extended_memmap; | 82 | + * function is the primary CPU we passed to arm_load_kernel(), not |
140 | + | 83 | + * the secondary. Loop around all the other CPUs, as the boot.c |
141 | + for (i = 0; i < ARRAY_SIZE(base_memmap); i++) { | 84 | + * code does for the "disable secondaries if PSCI is enabled" case. |
142 | + vms->memmap[i] = base_memmap[i]; | 85 | + */ |
143 | + } | 86 | + for (CPUState *cs = first_cpu; cs; cs = CPU_NEXT(cs)) { |
144 | + | 87 | + if (cs != first_cpu) { |
145 | + base = 256 * GiB; /* Top of the legacy initial RAM region */ | 88 | + object_property_set_bool(OBJECT(cs), "start-powered-off", true, |
146 | + | 89 | + &error_abort); |
147 | + for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { | 90 | + } |
148 | + hwaddr size = extended_memmap[i].size; | ||
149 | + | ||
150 | + base = ROUND_UP(base, size); | ||
151 | + vms->memmap[i].base = base; | ||
152 | + vms->memmap[i].size = size; | ||
153 | + base += size; | ||
154 | + } | 91 | + } |
155 | +} | 92 | +} |
156 | + | 93 | + |
157 | static void machvirt_init(MachineState *machine) | 94 | +static void mps3r_secondary_cpu_reset(ARMCPU *cpu, |
95 | + const struct arm_boot_info *info) | ||
96 | +{ | ||
97 | + /* We don't need to do anything here because the CPU will be off */ | ||
98 | +} | ||
99 | + | ||
100 | +static void create_gic(MPS3RMachineState *mms, MemoryRegion *sysmem) | ||
101 | +{ | ||
102 | + MachineState *machine = MACHINE(mms); | ||
103 | + DeviceState *gicdev; | ||
104 | + QList *redist_region_count; | ||
105 | + | ||
106 | + object_initialize_child(OBJECT(mms), "gic", &mms->gic, TYPE_ARM_GICV3); | ||
107 | + gicdev = DEVICE(&mms->gic); | ||
108 | + qdev_prop_set_uint32(gicdev, "num-cpu", machine->smp.cpus); | ||
109 | + qdev_prop_set_uint32(gicdev, "num-irq", NUM_SPIS + GIC_INTERNAL); | ||
110 | + redist_region_count = qlist_new(); | ||
111 | + qlist_append_int(redist_region_count, machine->smp.cpus); | ||
112 | + qdev_prop_set_array(gicdev, "redist-region-count", redist_region_count); | ||
113 | + object_property_set_link(OBJECT(&mms->gic), "sysmem", | ||
114 | + OBJECT(sysmem), &error_fatal); | ||
115 | + sysbus_realize(SYS_BUS_DEVICE(&mms->gic), &error_fatal); | ||
116 | + sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 0, PERIPHBASE); | ||
117 | + sysbus_mmio_map(SYS_BUS_DEVICE(&mms->gic), 1, PERIPHBASE + 0x100000); | ||
118 | + /* | ||
119 | + * Wire the outputs from each CPU's generic timer and the GICv3 | ||
120 | + * maintenance interrupt signal to the appropriate GIC PPI inputs, | ||
121 | + * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inputs. | ||
122 | + */ | ||
123 | + for (int i = 0; i < machine->smp.cpus; i++) { | ||
124 | + DeviceState *cpudev = DEVICE(mms->cpu[i]); | ||
125 | + SysBusDevice *gicsbd = SYS_BUS_DEVICE(&mms->gic); | ||
126 | + int intidbase = NUM_SPIS + i * GIC_INTERNAL; | ||
127 | + int irq; | ||
128 | + /* | ||
129 | + * Mapping from the output timer irq lines from the CPU to the | ||
130 | + * GIC PPI inputs used for this board. This isn't a BSA board, | ||
131 | + * but it uses the standard convention for the PPI numbers. | ||
132 | + */ | ||
133 | + const int timer_irq[] = { | ||
134 | + [GTIMER_PHYS] = ARCH_TIMER_NS_EL1_IRQ, | ||
135 | + [GTIMER_VIRT] = ARCH_TIMER_VIRT_IRQ, | ||
136 | + [GTIMER_HYP] = ARCH_TIMER_NS_EL2_IRQ, | ||
137 | + }; | ||
138 | + | ||
139 | + for (irq = 0; irq < ARRAY_SIZE(timer_irq); irq++) { | ||
140 | + qdev_connect_gpio_out(cpudev, irq, | ||
141 | + qdev_get_gpio_in(gicdev, | ||
142 | + intidbase + timer_irq[irq])); | ||
143 | + } | ||
144 | + | ||
145 | + qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0, | ||
146 | + qdev_get_gpio_in(gicdev, | ||
147 | + intidbase + ARCH_GIC_MAINT_IRQ)); | ||
148 | + | ||
149 | + qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, | ||
150 | + qdev_get_gpio_in(gicdev, | ||
151 | + intidbase + VIRTUAL_PMU_IRQ)); | ||
152 | + | ||
153 | + sysbus_connect_irq(gicsbd, i, | ||
154 | + qdev_get_gpio_in(cpudev, ARM_CPU_IRQ)); | ||
155 | + sysbus_connect_irq(gicsbd, i + machine->smp.cpus, | ||
156 | + qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); | ||
157 | + sysbus_connect_irq(gicsbd, i + 2 * machine->smp.cpus, | ||
158 | + qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); | ||
159 | + sysbus_connect_irq(gicsbd, i + 3 * machine->smp.cpus, | ||
160 | + qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); | ||
161 | + } | ||
162 | +} | ||
163 | + | ||
164 | static void mps3r_common_init(MachineState *machine) | ||
158 | { | 165 | { |
159 | VirtMachineState *vms = VIRT_MACHINE(machine); | 166 | MPS3RMachineState *mms = MPS3R_MACHINE(machine); |
160 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | 167 | @@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine) |
161 | bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0); | 168 | MemoryRegion *mr = mr_for_raminfo(mms, ri); |
162 | bool aarch64 = true; | 169 | memory_region_add_subregion(sysmem, ri->base, mr); |
163 | 170 | } | |
164 | + virt_set_memmap(vms); | 171 | + |
165 | + | 172 | + assert(machine->smp.cpus <= MPS3R_CPU_MAX); |
166 | /* We can probe only here because during property set | 173 | + for (int i = 0; i < machine->smp.cpus; i++) { |
167 | * KVM is not available yet | 174 | + g_autofree char *sysmem_name = g_strdup_printf("cpu-%d-memory", i); |
168 | */ | 175 | + g_autofree char *ramname = g_strdup_printf("cpu-%d-memory", i); |
169 | @@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj) | 176 | + g_autofree char *alias_name = g_strdup_printf("sysmem-alias-%d", i); |
170 | "Valid values are none and smmuv3", | 177 | + |
171 | NULL); | 178 | + /* |
172 | 179 | + * Each CPU has some private RAM/peripherals, so create the container | |
173 | - vms->memmap = a15memmap; | 180 | + * which will house those, with the whole-machine system memory being |
174 | vms->irqmap = a15irqmap; | 181 | + * used where there's no CPU-specific device. Note that we need the |
182 | + * sysmem_alias aliases because we can't put one MR (the original | ||
183 | + * 'sysmem') into more than one other MR. | ||
184 | + */ | ||
185 | + memory_region_init(&mms->cpu_sysmem[i], OBJECT(machine), | ||
186 | + sysmem_name, UINT64_MAX); | ||
187 | + memory_region_init_alias(&mms->sysmem_alias[i], OBJECT(machine), | ||
188 | + alias_name, sysmem, 0, UINT64_MAX); | ||
189 | + memory_region_add_subregion_overlap(&mms->cpu_sysmem[i], 0, | ||
190 | + &mms->sysmem_alias[i], -1); | ||
191 | + | ||
192 | + mms->cpu[i] = object_new(machine->cpu_type); | ||
193 | + object_property_set_link(mms->cpu[i], "memory", | ||
194 | + OBJECT(&mms->cpu_sysmem[i]), &error_abort); | ||
195 | + object_property_set_int(mms->cpu[i], "reset-cbar", | ||
196 | + PERIPHBASE, &error_abort); | ||
197 | + qdev_realize(DEVICE(mms->cpu[i]), NULL, &error_fatal); | ||
198 | + object_unref(mms->cpu[i]); | ||
199 | + | ||
200 | + /* Per-CPU RAM */ | ||
201 | + memory_region_init_ram(&mms->cpu_ram[i], NULL, ramname, | ||
202 | + 0x1000, &error_fatal); | ||
203 | + memory_region_add_subregion(&mms->cpu_sysmem[i], 0xe7c01000, | ||
204 | + &mms->cpu_ram[i]); | ||
205 | + } | ||
206 | + | ||
207 | + create_gic(mms, sysmem); | ||
208 | + | ||
209 | + mms->bootinfo.ram_size = machine->ram_size; | ||
210 | + mms->bootinfo.board_id = -1; | ||
211 | + mms->bootinfo.loader_start = mmc->loader_start; | ||
212 | + mms->bootinfo.write_secondary_boot = mps3r_write_secondary_boot; | ||
213 | + mms->bootinfo.secondary_cpu_reset_hook = mps3r_secondary_cpu_reset; | ||
214 | + arm_load_kernel(ARM_CPU(mms->cpu[0]), machine, &mms->bootinfo); | ||
175 | } | 215 | } |
176 | 216 | ||
217 | static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc) | ||
218 | @@ -XXX,XX +XXX,XX @@ static void mps3r_set_default_ram_info(MPS3RMachineClass *mmc) | ||
219 | /* Found the entry for "system memory" */ | ||
220 | mc->default_ram_size = p->size; | ||
221 | mc->default_ram_id = p->name; | ||
222 | + mmc->loader_start = p->base; | ||
223 | return; | ||
224 | } | ||
225 | } | ||
226 | @@ -XXX,XX +XXX,XX @@ static void mps3r_an536_class_init(ObjectClass *oc, void *data) | ||
227 | }; | ||
228 | |||
229 | mc->desc = "ARM MPS3 with AN536 FPGA image for Cortex-R52"; | ||
230 | - mc->default_cpus = 2; | ||
231 | - mc->min_cpus = mc->default_cpus; | ||
232 | - mc->max_cpus = mc->default_cpus; | ||
233 | + /* | ||
234 | + * In the real FPGA image there are always two cores, but the standard | ||
235 | + * initial setting for the SCC SYSCON 0x000 register is 0x21, meaning | ||
236 | + * that the second core is held in reset and halted. Many images built for | ||
237 | + * the board do not expect the second core to run at startup (especially | ||
238 | + * since on the real FPGA image it is not possible to use LDREX/STREX | ||
239 | + * in RAM between the two cores, so a true SMP setup isn't supported). | ||
240 | + * | ||
241 | + * As QEMU's equivalent of this, we support both -smp 1 and -smp 2, | ||
242 | + * with the default being -smp 1. This seems a more intuitive UI for | ||
243 | + * QEMU users than, for instance, having a machine property to allow | ||
244 | + * the user to set the initial value of the SYSCON 0x000 register. | ||
245 | + */ | ||
246 | + mc->default_cpus = 1; | ||
247 | + mc->min_cpus = 1; | ||
248 | + mc->max_cpus = 2; | ||
249 | mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-r52"); | ||
250 | mc->valid_cpu_types = valid_cpu_types; | ||
251 | mmc->raminfo = an536_raminfo; | ||
177 | -- | 252 | -- |
178 | 2.20.1 | 253 | 2.34.1 |
179 | |||
180 | diff view generated by jsdifflib |
1 | From: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> | 1 | This board has a lot of UARTs: there is one UART per CPU in the |
---|---|---|---|
2 | per-CPU peripheral part of the address map, whose interrupts are | ||
3 | connected as per-CPU interrupt lines. Then there are 4 UARTs in the | ||
4 | normal part of the peripheral space, whose interrupts are shared | ||
5 | peripheral interrupts. | ||
2 | 6 | ||
3 | We introduce an helper to create a memory node. | 7 | Connect and wire them all up; this involves some OR gates where |
8 | multiple overflow interrupts are wired into one GIC input. | ||
4 | 9 | ||
5 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
6 | Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com> | ||
7 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | ||
8 | Reviewed-by: Richard Henderson <richard.henderson@linaro.org> | ||
9 | Message-id: 20190304101339.25970-2-eric.auger@redhat.com | ||
10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 10 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
11 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
12 | Message-id: 20240206132931.38376-11-peter.maydell@linaro.org | ||
11 | --- | 13 | --- |
12 | hw/arm/boot.c | 54 ++++++++++++++++++++++++++++++++------------------- | 14 | hw/arm/mps3r.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++++++ |
13 | 1 file changed, 34 insertions(+), 20 deletions(-) | 15 | 1 file changed, 94 insertions(+) |
14 | 16 | ||
15 | diff --git a/hw/arm/boot.c b/hw/arm/boot.c | 17 | diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c |
16 | index XXXXXXX..XXXXXXX 100644 | 18 | index XXXXXXX..XXXXXXX 100644 |
17 | --- a/hw/arm/boot.c | 19 | --- a/hw/arm/mps3r.c |
18 | +++ b/hw/arm/boot.c | 20 | +++ b/hw/arm/mps3r.c |
19 | @@ -XXX,XX +XXX,XX @@ static void set_kernel_args_old(const struct arm_boot_info *info, | 21 | @@ -XXX,XX +XXX,XX @@ |
22 | #include "qapi/qmp/qlist.h" | ||
23 | #include "exec/address-spaces.h" | ||
24 | #include "cpu.h" | ||
25 | +#include "sysemu/sysemu.h" | ||
26 | #include "hw/boards.h" | ||
27 | +#include "hw/or-irq.h" | ||
28 | #include "hw/qdev-properties.h" | ||
29 | #include "hw/arm/boot.h" | ||
30 | #include "hw/arm/bsa.h" | ||
31 | +#include "hw/char/cmsdk-apb-uart.h" | ||
32 | #include "hw/intc/arm_gicv3.h" | ||
33 | |||
34 | /* Define the layout of RAM and ROM in a board */ | ||
35 | @@ -XXX,XX +XXX,XX @@ typedef struct RAMInfo { | ||
36 | |||
37 | #define MPS3R_RAM_MAX 9 | ||
38 | #define MPS3R_CPU_MAX 2 | ||
39 | +#define MPS3R_UART_MAX 4 /* shared UART count */ | ||
40 | |||
41 | #define PERIPHBASE 0xf0000000 | ||
42 | #define NUM_SPIS 96 | ||
43 | @@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState { | ||
44 | MemoryRegion sysmem_alias[MPS3R_CPU_MAX]; | ||
45 | MemoryRegion cpu_ram[MPS3R_CPU_MAX]; | ||
46 | GICv3State gic; | ||
47 | + /* per-CPU UARTs followed by the shared UARTs */ | ||
48 | + CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX]; | ||
49 | + OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX]; | ||
50 | + OrIRQState uart_oflow; | ||
51 | }; | ||
52 | |||
53 | #define TYPE_MPS3R_MACHINE "mps3r" | ||
54 | @@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState { | ||
55 | |||
56 | OBJECT_DECLARE_TYPE(MPS3RMachineState, MPS3RMachineClass, MPS3R_MACHINE) | ||
57 | |||
58 | +/* | ||
59 | + * Main clock frequency CLK in Hz (50MHz). In the image there are also | ||
60 | + * ACLK, MCLK, GPUCLK and PERIPHCLK at the same frequency; for our | ||
61 | + * model we just roll them all into one. | ||
62 | + */ | ||
63 | +#define CLK_FRQ 50000000 | ||
64 | + | ||
65 | static const RAMInfo an536_raminfo[] = { | ||
66 | { | ||
67 | .name = "ATCM", | ||
68 | @@ -XXX,XX +XXX,XX @@ static void create_gic(MPS3RMachineState *mms, MemoryRegion *sysmem) | ||
20 | } | 69 | } |
21 | } | 70 | } |
22 | 71 | ||
23 | +static int fdt_add_memory_node(void *fdt, uint32_t acells, hwaddr mem_base, | 72 | +/* |
24 | + uint32_t scells, hwaddr mem_len, | 73 | + * Create UART uartno, and map it into the MemoryRegion mem at address baseaddr. |
25 | + int numa_node_id) | 74 | + * The qemu_irq arguments are where we connect the various IRQs from the UART. |
75 | + */ | ||
76 | +static void create_uart(MPS3RMachineState *mms, int uartno, MemoryRegion *mem, | ||
77 | + hwaddr baseaddr, qemu_irq txirq, qemu_irq rxirq, | ||
78 | + qemu_irq txoverirq, qemu_irq rxoverirq, | ||
79 | + qemu_irq combirq) | ||
26 | +{ | 80 | +{ |
27 | + char *nodename; | 81 | + g_autofree char *s = g_strdup_printf("uart%d", uartno); |
28 | + int ret; | 82 | + SysBusDevice *sbd; |
29 | + | 83 | + |
30 | + nodename = g_strdup_printf("/memory@%" PRIx64, mem_base); | 84 | + assert(uartno < ARRAY_SIZE(mms->uart)); |
31 | + qemu_fdt_add_subnode(fdt, nodename); | 85 | + object_initialize_child(OBJECT(mms), s, &mms->uart[uartno], |
32 | + qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); | 86 | + TYPE_CMSDK_APB_UART); |
33 | + ret = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", acells, mem_base, | 87 | + qdev_prop_set_uint32(DEVICE(&mms->uart[uartno]), "pclk-frq", CLK_FRQ); |
34 | + scells, mem_len); | 88 | + qdev_prop_set_chr(DEVICE(&mms->uart[uartno]), "chardev", serial_hd(uartno)); |
35 | + if (ret < 0) { | 89 | + sbd = SYS_BUS_DEVICE(&mms->uart[uartno]); |
36 | + goto out; | 90 | + sysbus_realize(sbd, &error_fatal); |
37 | + } | 91 | + memory_region_add_subregion(mem, baseaddr, |
38 | + | 92 | + sysbus_mmio_get_region(sbd, 0)); |
39 | + /* only set the NUMA ID if it is specified */ | 93 | + sysbus_connect_irq(sbd, 0, txirq); |
40 | + if (numa_node_id >= 0) { | 94 | + sysbus_connect_irq(sbd, 1, rxirq); |
41 | + ret = qemu_fdt_setprop_cell(fdt, nodename, | 95 | + sysbus_connect_irq(sbd, 2, txoverirq); |
42 | + "numa-node-id", numa_node_id); | 96 | + sysbus_connect_irq(sbd, 3, rxoverirq); |
43 | + } | 97 | + sysbus_connect_irq(sbd, 4, combirq); |
44 | +out: | ||
45 | + g_free(nodename); | ||
46 | + return ret; | ||
47 | +} | 98 | +} |
48 | + | 99 | + |
49 | static void fdt_add_psci_node(void *fdt) | 100 | static void mps3r_common_init(MachineState *machine) |
50 | { | 101 | { |
51 | uint32_t cpu_suspend_fn; | 102 | MPS3RMachineState *mms = MPS3R_MACHINE(machine); |
52 | @@ -XXX,XX +XXX,XX @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, | 103 | MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms); |
53 | void *fdt = NULL; | 104 | MemoryRegion *sysmem = get_system_memory(); |
54 | int size, rc, n = 0; | 105 | + DeviceState *gicdev; |
55 | uint32_t acells, scells; | 106 | |
56 | - char *nodename; | 107 | for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) { |
57 | unsigned int i; | 108 | MemoryRegion *mr = mr_for_raminfo(mms, ri); |
58 | hwaddr mem_base, mem_len; | 109 | @@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine) |
59 | char **node_path; | ||
60 | @@ -XXX,XX +XXX,XX @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, | ||
61 | mem_base = binfo->loader_start; | ||
62 | for (i = 0; i < nb_numa_nodes; i++) { | ||
63 | mem_len = numa_info[i].node_mem; | ||
64 | - nodename = g_strdup_printf("/memory@%" PRIx64, mem_base); | ||
65 | - qemu_fdt_add_subnode(fdt, nodename); | ||
66 | - qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); | ||
67 | - rc = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", | ||
68 | - acells, mem_base, | ||
69 | - scells, mem_len); | ||
70 | + rc = fdt_add_memory_node(fdt, acells, mem_base, | ||
71 | + scells, mem_len, i); | ||
72 | if (rc < 0) { | ||
73 | - fprintf(stderr, "couldn't set %s/reg for node %d\n", nodename, | ||
74 | - i); | ||
75 | + fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n", | ||
76 | + mem_base); | ||
77 | goto fail; | ||
78 | } | ||
79 | |||
80 | - qemu_fdt_setprop_cell(fdt, nodename, "numa-node-id", i); | ||
81 | mem_base += mem_len; | ||
82 | - g_free(nodename); | ||
83 | } | ||
84 | } else { | ||
85 | - nodename = g_strdup_printf("/memory@%" PRIx64, binfo->loader_start); | ||
86 | - qemu_fdt_add_subnode(fdt, nodename); | ||
87 | - qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); | ||
88 | - | ||
89 | - rc = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", | ||
90 | - acells, binfo->loader_start, | ||
91 | - scells, binfo->ram_size); | ||
92 | + rc = fdt_add_memory_node(fdt, acells, binfo->loader_start, | ||
93 | + scells, binfo->ram_size, -1); | ||
94 | if (rc < 0) { | ||
95 | - fprintf(stderr, "couldn't set %s reg\n", nodename); | ||
96 | + fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n", | ||
97 | + binfo->loader_start); | ||
98 | goto fail; | ||
99 | } | ||
100 | - g_free(nodename); | ||
101 | } | 110 | } |
102 | 111 | ||
103 | rc = fdt_path_offset(fdt, "/chosen"); | 112 | create_gic(mms, sysmem); |
113 | + gicdev = DEVICE(&mms->gic); | ||
114 | + | ||
115 | + /* | ||
116 | + * UARTs 0 and 1 are per-CPU; their interrupts are wired to | ||
117 | + * the relevant CPU's PPI 0..3, aka INTID 16..19 | ||
118 | + */ | ||
119 | + for (int i = 0; i < machine->smp.cpus; i++) { | ||
120 | + int intidbase = NUM_SPIS + i * GIC_INTERNAL; | ||
121 | + g_autofree char *s = g_strdup_printf("cpu-uart-oflow-orgate%d", i); | ||
122 | + DeviceState *orgate; | ||
123 | + | ||
124 | + /* The two overflow IRQs from the UART are ORed together into PPI 3 */ | ||
125 | + object_initialize_child(OBJECT(mms), s, &mms->cpu_uart_oflow[i], | ||
126 | + TYPE_OR_IRQ); | ||
127 | + orgate = DEVICE(&mms->cpu_uart_oflow[i]); | ||
128 | + qdev_prop_set_uint32(orgate, "num-lines", 2); | ||
129 | + qdev_realize(orgate, NULL, &error_fatal); | ||
130 | + qdev_connect_gpio_out(orgate, 0, | ||
131 | + qdev_get_gpio_in(gicdev, intidbase + 19)); | ||
132 | + | ||
133 | + create_uart(mms, i, &mms->cpu_sysmem[i], 0xe7c00000, | ||
134 | + qdev_get_gpio_in(gicdev, intidbase + 17), /* tx */ | ||
135 | + qdev_get_gpio_in(gicdev, intidbase + 16), /* rx */ | ||
136 | + qdev_get_gpio_in(orgate, 0), /* txover */ | ||
137 | + qdev_get_gpio_in(orgate, 1), /* rxover */ | ||
138 | + qdev_get_gpio_in(gicdev, intidbase + 18) /* combined */); | ||
139 | + } | ||
140 | + /* | ||
141 | + * UARTs 2 to 5 are whole-system; all overflow IRQs are ORed | ||
142 | + * together into IRQ 17 | ||
143 | + */ | ||
144 | + object_initialize_child(OBJECT(mms), "uart-oflow-orgate", | ||
145 | + &mms->uart_oflow, TYPE_OR_IRQ); | ||
146 | + qdev_prop_set_uint32(DEVICE(&mms->uart_oflow), "num-lines", | ||
147 | + MPS3R_UART_MAX * 2); | ||
148 | + qdev_realize(DEVICE(&mms->uart_oflow), NULL, &error_fatal); | ||
149 | + qdev_connect_gpio_out(DEVICE(&mms->uart_oflow), 0, | ||
150 | + qdev_get_gpio_in(gicdev, 17)); | ||
151 | + | ||
152 | + for (int i = 0; i < MPS3R_UART_MAX; i++) { | ||
153 | + hwaddr baseaddr = 0xe0205000 + i * 0x1000; | ||
154 | + int rxirq = 5 + i * 2, txirq = 6 + i * 2, combirq = 13 + i; | ||
155 | + | ||
156 | + create_uart(mms, i + MPS3R_CPU_MAX, sysmem, baseaddr, | ||
157 | + qdev_get_gpio_in(gicdev, txirq), | ||
158 | + qdev_get_gpio_in(gicdev, rxirq), | ||
159 | + qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2), | ||
160 | + qdev_get_gpio_in(DEVICE(&mms->uart_oflow), i * 2 + 1), | ||
161 | + qdev_get_gpio_in(gicdev, combirq)); | ||
162 | + } | ||
163 | |||
164 | mms->bootinfo.ram_size = machine->ram_size; | ||
165 | mms->bootinfo.board_id = -1; | ||
104 | -- | 166 | -- |
105 | 2.20.1 | 167 | 2.34.1 |
106 | 168 | ||
107 | 169 | diff view generated by jsdifflib |
1 | From: Richard Henderson <richard.henderson@linaro.org> | 1 | Add the GPIO, watchdog, dual-timer and I2C devices to the mps3-an536 |
---|---|---|---|
2 | board. These are all simple devices that just need to be created and | ||
3 | wired up. | ||
2 | 4 | ||
3 | Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com> | ||
4 | Signed-off-by: Richard Henderson <richard.henderson@linaro.org> | ||
5 | Message-id: 20190301200501.16533-11-richard.henderson@linaro.org | ||
6 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
7 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
6 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> | ||
7 | Message-id: 20240206132931.38376-12-peter.maydell@linaro.org | ||
8 | --- | 8 | --- |
9 | target/arm/cpu.h | 5 ++ | 9 | hw/arm/mps3r.c | 59 ++++++++++++++++++++++++++++++++++++++++++++++++++ |
10 | target/arm/helper.h | 5 ++ | 10 | 1 file changed, 59 insertions(+) |
11 | target/arm/cpu64.c | 1 + | ||
12 | target/arm/translate-a64.c | 71 ++++++++++++++++++++++++++-- | ||
13 | target/arm/vfp_helper.c | 96 ++++++++++++++++++++++++++++++++++++++ | ||
14 | 5 files changed, 173 insertions(+), 5 deletions(-) | ||
15 | 11 | ||
16 | diff --git a/target/arm/cpu.h b/target/arm/cpu.h | 12 | diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c |
17 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
18 | --- a/target/arm/cpu.h | 14 | --- a/hw/arm/mps3r.c |
19 | +++ b/target/arm/cpu.h | 15 | +++ b/hw/arm/mps3r.c |
20 | @@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id) | 16 | @@ -XXX,XX +XXX,XX @@ |
21 | return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0; | 17 | #include "sysemu/sysemu.h" |
22 | } | 18 | #include "hw/boards.h" |
23 | 19 | #include "hw/or-irq.h" | |
24 | +static inline bool isar_feature_aa64_frint(const ARMISARegisters *id) | 20 | +#include "hw/qdev-clock.h" |
25 | +{ | 21 | #include "hw/qdev-properties.h" |
26 | + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0; | 22 | #include "hw/arm/boot.h" |
27 | +} | 23 | #include "hw/arm/bsa.h" |
24 | #include "hw/char/cmsdk-apb-uart.h" | ||
25 | +#include "hw/i2c/arm_sbcon_i2c.h" | ||
26 | #include "hw/intc/arm_gicv3.h" | ||
27 | +#include "hw/misc/unimp.h" | ||
28 | +#include "hw/timer/cmsdk-apb-dualtimer.h" | ||
29 | +#include "hw/watchdog/cmsdk-apb-watchdog.h" | ||
30 | |||
31 | /* Define the layout of RAM and ROM in a board */ | ||
32 | typedef struct RAMInfo { | ||
33 | @@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState { | ||
34 | CMSDKAPBUART uart[MPS3R_CPU_MAX + MPS3R_UART_MAX]; | ||
35 | OrIRQState cpu_uart_oflow[MPS3R_CPU_MAX]; | ||
36 | OrIRQState uart_oflow; | ||
37 | + CMSDKAPBWatchdog watchdog; | ||
38 | + CMSDKAPBDualTimer dualtimer; | ||
39 | + ArmSbconI2CState i2c[5]; | ||
40 | + Clock *clk; | ||
41 | }; | ||
42 | |||
43 | #define TYPE_MPS3R_MACHINE "mps3r" | ||
44 | @@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine) | ||
45 | MemoryRegion *sysmem = get_system_memory(); | ||
46 | DeviceState *gicdev; | ||
47 | |||
48 | + mms->clk = clock_new(OBJECT(machine), "CLK"); | ||
49 | + clock_set_hz(mms->clk, CLK_FRQ); | ||
28 | + | 50 | + |
29 | static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) | 51 | for (const RAMInfo *ri = mmc->raminfo; ri->name; ri++) { |
30 | { | 52 | MemoryRegion *mr = mr_for_raminfo(mms, ri); |
31 | /* We always set the AdvSIMD and FP fields identically wrt FP16. */ | 53 | memory_region_add_subregion(sysmem, ri->base, mr); |
32 | diff --git a/target/arm/helper.h b/target/arm/helper.h | 54 | @@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine) |
33 | index XXXXXXX..XXXXXXX 100644 | 55 | qdev_get_gpio_in(gicdev, combirq)); |
34 | --- a/target/arm/helper.h | ||
35 | +++ b/target/arm/helper.h | ||
36 | @@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a32, TCG_CALL_NO_RWG, | ||
37 | DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a64, TCG_CALL_NO_RWG, | ||
38 | void, ptr, ptr, ptr, ptr, i32) | ||
39 | |||
40 | +DEF_HELPER_FLAGS_2(frint32_s, TCG_CALL_NO_RWG, f32, f32, ptr) | ||
41 | +DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f32, ptr) | ||
42 | +DEF_HELPER_FLAGS_2(frint32_d, TCG_CALL_NO_RWG, f64, f64, ptr) | ||
43 | +DEF_HELPER_FLAGS_2(frint64_d, TCG_CALL_NO_RWG, f64, f64, ptr) | ||
44 | + | ||
45 | #ifdef TARGET_AARCH64 | ||
46 | #include "helper-a64.h" | ||
47 | #include "helper-sve.h" | ||
48 | diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c | ||
49 | index XXXXXXX..XXXXXXX 100644 | ||
50 | --- a/target/arm/cpu64.c | ||
51 | +++ b/target/arm/cpu64.c | ||
52 | @@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj) | ||
53 | t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0); | ||
54 | t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); | ||
55 | t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); | ||
56 | + t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); | ||
57 | cpu->isar.id_aa64isar1 = t; | ||
58 | |||
59 | t = cpu->isar.id_aa64pfr0; | ||
60 | diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c | ||
61 | index XXXXXXX..XXXXXXX 100644 | ||
62 | --- a/target/arm/translate-a64.c | ||
63 | +++ b/target/arm/translate-a64.c | ||
64 | @@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn) | ||
65 | case 0xf: /* FRINTI */ | ||
66 | gen_fpst = gen_helper_rints; | ||
67 | break; | ||
68 | + case 0x10: /* FRINT32Z */ | ||
69 | + rmode = float_round_to_zero; | ||
70 | + gen_fpst = gen_helper_frint32_s; | ||
71 | + break; | ||
72 | + case 0x11: /* FRINT32X */ | ||
73 | + gen_fpst = gen_helper_frint32_s; | ||
74 | + break; | ||
75 | + case 0x12: /* FRINT64Z */ | ||
76 | + rmode = float_round_to_zero; | ||
77 | + gen_fpst = gen_helper_frint64_s; | ||
78 | + break; | ||
79 | + case 0x13: /* FRINT64X */ | ||
80 | + gen_fpst = gen_helper_frint64_s; | ||
81 | + break; | ||
82 | default: | ||
83 | g_assert_not_reached(); | ||
84 | } | 56 | } |
85 | @@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn) | 57 | |
86 | case 0xf: /* FRINTI */ | 58 | + for (int i = 0; i < 4; i++) { |
87 | gen_fpst = gen_helper_rintd; | 59 | + /* CMSDK GPIO controllers */ |
88 | break; | 60 | + g_autofree char *s = g_strdup_printf("gpio%d", i); |
89 | + case 0x10: /* FRINT32Z */ | 61 | + create_unimplemented_device(s, 0xe0000000 + i * 0x1000, 0x1000); |
90 | + rmode = float_round_to_zero; | ||
91 | + gen_fpst = gen_helper_frint32_d; | ||
92 | + break; | ||
93 | + case 0x11: /* FRINT32X */ | ||
94 | + gen_fpst = gen_helper_frint32_d; | ||
95 | + break; | ||
96 | + case 0x12: /* FRINT64Z */ | ||
97 | + rmode = float_round_to_zero; | ||
98 | + gen_fpst = gen_helper_frint64_d; | ||
99 | + break; | ||
100 | + case 0x13: /* FRINT64X */ | ||
101 | + gen_fpst = gen_helper_frint64_d; | ||
102 | + break; | ||
103 | default: | ||
104 | g_assert_not_reached(); | ||
105 | } | ||
106 | @@ -XXX,XX +XXX,XX @@ static void disas_fp_1src(DisasContext *s, uint32_t insn) | ||
107 | handle_fp_fcvt(s, opcode, rd, rn, dtype, type); | ||
108 | break; | ||
109 | } | ||
110 | + | ||
111 | + case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */ | ||
112 | + if (type > 1 || !dc_isar_feature(aa64_frint, s)) { | ||
113 | + unallocated_encoding(s); | ||
114 | + return; | ||
115 | + } | ||
116 | + /* fall through */ | ||
117 | case 0x0 ... 0x3: | ||
118 | case 0x8 ... 0xc: | ||
119 | case 0xe ... 0xf: | ||
120 | @@ -XXX,XX +XXX,XX @@ static void disas_fp_1src(DisasContext *s, uint32_t insn) | ||
121 | if (!fp_access_check(s)) { | ||
122 | return; | ||
123 | } | ||
124 | - | ||
125 | handle_fp_1src_single(s, opcode, rd, rn); | ||
126 | break; | ||
127 | case 1: | ||
128 | if (!fp_access_check(s)) { | ||
129 | return; | ||
130 | } | ||
131 | - | ||
132 | handle_fp_1src_double(s, opcode, rd, rn); | ||
133 | break; | ||
134 | case 3: | ||
135 | @@ -XXX,XX +XXX,XX @@ static void disas_fp_1src(DisasContext *s, uint32_t insn) | ||
136 | if (!fp_access_check(s)) { | ||
137 | return; | ||
138 | } | ||
139 | - | ||
140 | handle_fp_1src_half(s, opcode, rd, rn); | ||
141 | break; | ||
142 | default: | ||
143 | unallocated_encoding(s); | ||
144 | } | ||
145 | break; | ||
146 | + | ||
147 | default: | ||
148 | unallocated_encoding(s); | ||
149 | break; | ||
150 | @@ -XXX,XX +XXX,XX @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u, | ||
151 | case 0x59: /* FRINTX */ | ||
152 | gen_helper_rintd_exact(tcg_rd, tcg_rn, tcg_fpstatus); | ||
153 | break; | ||
154 | + case 0x1e: /* FRINT32Z */ | ||
155 | + case 0x5e: /* FRINT32X */ | ||
156 | + gen_helper_frint32_d(tcg_rd, tcg_rn, tcg_fpstatus); | ||
157 | + break; | ||
158 | + case 0x1f: /* FRINT64Z */ | ||
159 | + case 0x5f: /* FRINT64X */ | ||
160 | + gen_helper_frint64_d(tcg_rd, tcg_rn, tcg_fpstatus); | ||
161 | + break; | ||
162 | default: | ||
163 | g_assert_not_reached(); | ||
164 | } | ||
165 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) | ||
166 | } | ||
167 | break; | ||
168 | case 0xc ... 0xf: | ||
169 | - case 0x16 ... 0x1d: | ||
170 | - case 0x1f: | ||
171 | + case 0x16 ... 0x1f: | ||
172 | { | ||
173 | /* Floating point: U, size[1] and opcode indicate operation; | ||
174 | * size[0] indicates single or double precision. | ||
175 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) | ||
176 | } | ||
177 | need_fpstatus = true; | ||
178 | break; | ||
179 | + case 0x1e: /* FRINT32Z */ | ||
180 | + case 0x1f: /* FRINT64Z */ | ||
181 | + need_rmode = true; | ||
182 | + rmode = FPROUNDING_ZERO; | ||
183 | + /* fall through */ | ||
184 | + case 0x5e: /* FRINT32X */ | ||
185 | + case 0x5f: /* FRINT64X */ | ||
186 | + need_fpstatus = true; | ||
187 | + if ((size == 3 && !is_q) || !dc_isar_feature(aa64_frint, s)) { | ||
188 | + unallocated_encoding(s); | ||
189 | + return; | ||
190 | + } | ||
191 | + break; | ||
192 | default: | ||
193 | unallocated_encoding(s); | ||
194 | return; | ||
195 | @@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) | ||
196 | case 0x7c: /* URSQRTE */ | ||
197 | gen_helper_rsqrte_u32(tcg_res, tcg_op, tcg_fpstatus); | ||
198 | break; | ||
199 | + case 0x1e: /* FRINT32Z */ | ||
200 | + case 0x5e: /* FRINT32X */ | ||
201 | + gen_helper_frint32_s(tcg_res, tcg_op, tcg_fpstatus); | ||
202 | + break; | ||
203 | + case 0x1f: /* FRINT64Z */ | ||
204 | + case 0x5f: /* FRINT64X */ | ||
205 | + gen_helper_frint64_s(tcg_res, tcg_op, tcg_fpstatus); | ||
206 | + break; | ||
207 | default: | ||
208 | g_assert_not_reached(); | ||
209 | } | ||
210 | diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c | ||
211 | index XXXXXXX..XXXXXXX 100644 | ||
212 | --- a/target/arm/vfp_helper.c | ||
213 | +++ b/target/arm/vfp_helper.c | ||
214 | @@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vjcvt)(float64 value, CPUARMState *env) | ||
215 | |||
216 | return result; | ||
217 | } | ||
218 | + | ||
219 | +/* Round a float32 to an integer that fits in int32_t or int64_t. */ | ||
220 | +static float32 frint_s(float32 f, float_status *fpst, int intsize) | ||
221 | +{ | ||
222 | + int old_flags = get_float_exception_flags(fpst); | ||
223 | + uint32_t exp = extract32(f, 23, 8); | ||
224 | + | ||
225 | + if (unlikely(exp == 0xff)) { | ||
226 | + /* NaN or Inf. */ | ||
227 | + goto overflow; | ||
228 | + } | 62 | + } |
229 | + | 63 | + |
230 | + /* Round and re-extract the exponent. */ | 64 | + object_initialize_child(OBJECT(mms), "watchdog", &mms->watchdog, |
231 | + f = float32_round_to_int(f, fpst); | 65 | + TYPE_CMSDK_APB_WATCHDOG); |
232 | + exp = extract32(f, 23, 8); | 66 | + qdev_connect_clock_in(DEVICE(&mms->watchdog), "WDOGCLK", mms->clk); |
67 | + sysbus_realize(SYS_BUS_DEVICE(&mms->watchdog), &error_fatal); | ||
68 | + sysbus_connect_irq(SYS_BUS_DEVICE(&mms->watchdog), 0, | ||
69 | + qdev_get_gpio_in(gicdev, 0)); | ||
70 | + sysbus_mmio_map(SYS_BUS_DEVICE(&mms->watchdog), 0, 0xe0100000); | ||
233 | + | 71 | + |
234 | + /* Validate the range of the result. */ | 72 | + object_initialize_child(OBJECT(mms), "dualtimer", &mms->dualtimer, |
235 | + if (exp < 126 + intsize) { | 73 | + TYPE_CMSDK_APB_DUALTIMER); |
236 | + /* abs(F) <= INT{N}_MAX */ | 74 | + qdev_connect_clock_in(DEVICE(&mms->dualtimer), "TIMCLK", mms->clk); |
237 | + return f; | 75 | + sysbus_realize(SYS_BUS_DEVICE(&mms->dualtimer), &error_fatal); |
238 | + } | 76 | + sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 0, |
239 | + if (exp == 126 + intsize) { | 77 | + qdev_get_gpio_in(gicdev, 3)); |
240 | + uint32_t sign = extract32(f, 31, 1); | 78 | + sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 1, |
241 | + uint32_t frac = extract32(f, 0, 23); | 79 | + qdev_get_gpio_in(gicdev, 1)); |
242 | + if (sign && frac == 0) { | 80 | + sysbus_connect_irq(SYS_BUS_DEVICE(&mms->dualtimer), 2, |
243 | + /* F == INT{N}_MIN */ | 81 | + qdev_get_gpio_in(gicdev, 2)); |
244 | + return f; | 82 | + sysbus_mmio_map(SYS_BUS_DEVICE(&mms->dualtimer), 0, 0xe0101000); |
83 | + | ||
84 | + for (int i = 0; i < ARRAY_SIZE(mms->i2c); i++) { | ||
85 | + static const hwaddr i2cbase[] = {0xe0102000, /* Touch */ | ||
86 | + 0xe0103000, /* Audio */ | ||
87 | + 0xe0107000, /* Shield0 */ | ||
88 | + 0xe0108000, /* Shield1 */ | ||
89 | + 0xe0109000}; /* DDR4 EEPROM */ | ||
90 | + g_autofree char *s = g_strdup_printf("i2c%d", i); | ||
91 | + | ||
92 | + object_initialize_child(OBJECT(mms), s, &mms->i2c[i], | ||
93 | + TYPE_ARM_SBCON_I2C); | ||
94 | + sysbus_realize(SYS_BUS_DEVICE(&mms->i2c[i]), &error_fatal); | ||
95 | + sysbus_mmio_map(SYS_BUS_DEVICE(&mms->i2c[i]), 0, i2cbase[i]); | ||
96 | + if (i != 2 && i != 3) { | ||
97 | + /* | ||
98 | + * internal-only bus: mark it full to avoid user-created | ||
99 | + * i2c devices being plugged into it. | ||
100 | + */ | ||
101 | + qbus_mark_full(qdev_get_child_bus(DEVICE(&mms->i2c[i]), "i2c")); | ||
245 | + } | 102 | + } |
246 | + } | 103 | + } |
247 | + | 104 | + |
248 | + overflow: | 105 | mms->bootinfo.ram_size = machine->ram_size; |
249 | + /* | 106 | mms->bootinfo.board_id = -1; |
250 | + * Raise Invalid and return INT{N}_MIN as a float. Revert any | 107 | mms->bootinfo.loader_start = mmc->loader_start; |
251 | + * inexact exception float32_round_to_int may have raised. | ||
252 | + */ | ||
253 | + set_float_exception_flags(old_flags | float_flag_invalid, fpst); | ||
254 | + return (0x100u + 126u + intsize) << 23; | ||
255 | +} | ||
256 | + | ||
257 | +float32 HELPER(frint32_s)(float32 f, void *fpst) | ||
258 | +{ | ||
259 | + return frint_s(f, fpst, 32); | ||
260 | +} | ||
261 | + | ||
262 | +float32 HELPER(frint64_s)(float32 f, void *fpst) | ||
263 | +{ | ||
264 | + return frint_s(f, fpst, 64); | ||
265 | +} | ||
266 | + | ||
267 | +/* Round a float64 to an integer that fits in int32_t or int64_t. */ | ||
268 | +static float64 frint_d(float64 f, float_status *fpst, int intsize) | ||
269 | +{ | ||
270 | + int old_flags = get_float_exception_flags(fpst); | ||
271 | + uint32_t exp = extract64(f, 52, 11); | ||
272 | + | ||
273 | + if (unlikely(exp == 0x7ff)) { | ||
274 | + /* NaN or Inf. */ | ||
275 | + goto overflow; | ||
276 | + } | ||
277 | + | ||
278 | + /* Round and re-extract the exponent. */ | ||
279 | + f = float64_round_to_int(f, fpst); | ||
280 | + exp = extract64(f, 52, 11); | ||
281 | + | ||
282 | + /* Validate the range of the result. */ | ||
283 | + if (exp < 1022 + intsize) { | ||
284 | + /* abs(F) <= INT{N}_MAX */ | ||
285 | + return f; | ||
286 | + } | ||
287 | + if (exp == 1022 + intsize) { | ||
288 | + uint64_t sign = extract64(f, 63, 1); | ||
289 | + uint64_t frac = extract64(f, 0, 52); | ||
290 | + if (sign && frac == 0) { | ||
291 | + /* F == INT{N}_MIN */ | ||
292 | + return f; | ||
293 | + } | ||
294 | + } | ||
295 | + | ||
296 | + overflow: | ||
297 | + /* | ||
298 | + * Raise Invalid and return INT{N}_MIN as a float. Revert any | ||
299 | + * inexact exception float64_round_to_int may have raised. | ||
300 | + */ | ||
301 | + set_float_exception_flags(old_flags | float_flag_invalid, fpst); | ||
302 | + return (uint64_t)(0x800 + 1022 + intsize) << 52; | ||
303 | +} | ||
304 | + | ||
305 | +float64 HELPER(frint32_d)(float64 f, void *fpst) | ||
306 | +{ | ||
307 | + return frint_d(f, fpst, 32); | ||
308 | +} | ||
309 | + | ||
310 | +float64 HELPER(frint64_d)(float64 f, void *fpst) | ||
311 | +{ | ||
312 | + return frint_d(f, fpst, 64); | ||
313 | +} | ||
314 | -- | 108 | -- |
315 | 2.20.1 | 109 | 2.34.1 |
316 | 110 | ||
317 | 111 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | Add the remaining devices (or unimplemented-device stubs) for |
---|---|---|---|
2 | this board: SPI controllers, SCC, FPGAIO, I2S, RTC, the | ||
3 | QSPI write-config block, and ethernet. | ||
2 | 4 | ||
3 | Up to now the memory map has been static and the high IO region | 5 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | base has always been 256GiB. | 6 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
7 | Message-id: 20240206132931.38376-13-peter.maydell@linaro.org | ||
8 | --- | ||
9 | hw/arm/mps3r.c | 74 ++++++++++++++++++++++++++++++++++++++++++++++++++ | ||
10 | 1 file changed, 74 insertions(+) | ||
5 | 11 | ||
6 | This patch modifies the virt_set_memmap() function, which freezes | 12 | diff --git a/hw/arm/mps3r.c b/hw/arm/mps3r.c |
7 | the memory map, so that the high IO range base becomes floating, | ||
8 | located after the initial RAM and the device memory. | ||
9 | |||
10 | The function computes | ||
11 | - the base of the device memory, | ||
12 | - the size of the device memory, | ||
13 | - the high IO region base | ||
14 | - the highest GPA used in the memory map. | ||
15 | |||
16 | Entries of the high IO region are assigned a base address. The | ||
17 | device memory is initialized. | ||
18 | |||
19 | The highest GPA used in the memory map will be used at VM creation | ||
20 | to choose the requested IPA size. | ||
21 | |||
22 | Setting all the existing highmem IO regions beyond the RAM | ||
23 | allows to have a single contiguous RAM region (initial RAM and | ||
24 | possible hotpluggable device memory). That way we do not need | ||
25 | to do invasive changes in the EDK2 FW to support a dynamic | ||
26 | RAM base. | ||
27 | |||
28 | Still the user cannot request an initial RAM size greater than 255GB. | ||
29 | |||
30 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | ||
31 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | ||
32 | Message-id: 20190304101339.25970-8-eric.auger@redhat.com | ||
33 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
34 | --- | ||
35 | include/hw/arm/virt.h | 1 + | ||
36 | hw/arm/virt.c | 52 ++++++++++++++++++++++++++++++++++++++----- | ||
37 | 2 files changed, 47 insertions(+), 6 deletions(-) | ||
38 | |||
39 | diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h | ||
40 | index XXXXXXX..XXXXXXX 100644 | 13 | index XXXXXXX..XXXXXXX 100644 |
41 | --- a/include/hw/arm/virt.h | 14 | --- a/hw/arm/mps3r.c |
42 | +++ b/include/hw/arm/virt.h | 15 | +++ b/hw/arm/mps3r.c |
43 | @@ -XXX,XX +XXX,XX @@ typedef struct { | ||
44 | uint32_t msi_phandle; | ||
45 | uint32_t iommu_phandle; | ||
46 | int psci_conduit; | ||
47 | + hwaddr highest_gpa; | ||
48 | } VirtMachineState; | ||
49 | |||
50 | #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM) | ||
51 | diff --git a/hw/arm/virt.c b/hw/arm/virt.c | ||
52 | index XXXXXXX..XXXXXXX 100644 | ||
53 | --- a/hw/arm/virt.c | ||
54 | +++ b/hw/arm/virt.c | ||
55 | @@ -XXX,XX +XXX,XX @@ | 16 | @@ -XXX,XX +XXX,XX @@ |
56 | #include "qapi/visitor.h" | 17 | #include "hw/char/cmsdk-apb-uart.h" |
57 | #include "standard-headers/linux/input.h" | 18 | #include "hw/i2c/arm_sbcon_i2c.h" |
58 | #include "hw/arm/smmuv3.h" | 19 | #include "hw/intc/arm_gicv3.h" |
59 | +#include "hw/acpi/acpi.h" | 20 | +#include "hw/misc/mps2-scc.h" |
60 | 21 | +#include "hw/misc/mps2-fpgaio.h" | |
61 | #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ | 22 | #include "hw/misc/unimp.h" |
62 | static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ | 23 | +#include "hw/net/lan9118.h" |
63 | @@ -XXX,XX +XXX,XX @@ | 24 | +#include "hw/rtc/pl031.h" |
64 | * of a terabyte of RAM will be doing it on a host with more than a | 25 | +#include "hw/ssi/pl022.h" |
65 | * terabyte of physical address space.) | 26 | #include "hw/timer/cmsdk-apb-dualtimer.h" |
66 | */ | 27 | #include "hw/watchdog/cmsdk-apb-watchdog.h" |
67 | -#define RAMLIMIT_GB 255 | 28 | |
68 | -#define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024) | 29 | @@ -XXX,XX +XXX,XX @@ struct MPS3RMachineState { |
69 | +#define LEGACY_RAMLIMIT_GB 255 | 30 | CMSDKAPBWatchdog watchdog; |
70 | +#define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) | 31 | CMSDKAPBDualTimer dualtimer; |
71 | 32 | ArmSbconI2CState i2c[5]; | |
72 | /* Addresses and sizes of our components. | 33 | + PL022State spi[3]; |
73 | * 0..128MB is space for a flash device so we can run bootrom code such as UEFI. | 34 | + MPS2SCC scc; |
74 | @@ -XXX,XX +XXX,XX @@ static const MemMapEntry base_memmap[] = { | 35 | + MPS2FPGAIO fpgaio; |
75 | [VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 }, | 36 | + UnimplementedDeviceState i2s_audio; |
76 | [VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 }, | 37 | + PL031State rtc; |
77 | [VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 }, | 38 | Clock *clk; |
78 | - [VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES }, | ||
79 | + /* Actual RAM size depends on initial RAM and device memory settings */ | ||
80 | + [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES }, | ||
81 | }; | 39 | }; |
82 | 40 | ||
83 | /* | 41 | @@ -XXX,XX +XXX,XX @@ static const RAMInfo an536_raminfo[] = { |
84 | @@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) | 42 | } |
85 | 43 | }; | |
86 | static void virt_set_memmap(VirtMachineState *vms) | 44 | |
45 | +static const int an536_oscclk[] = { | ||
46 | + 24000000, /* 24MHz reference for RTC and timers */ | ||
47 | + 50000000, /* 50MHz ACLK */ | ||
48 | + 50000000, /* 50MHz MCLK */ | ||
49 | + 50000000, /* 50MHz GPUCLK */ | ||
50 | + 24576000, /* 24.576MHz AUDCLK */ | ||
51 | + 23750000, /* 23.75MHz HDLCDCLK */ | ||
52 | + 100000000, /* 100MHz DDR4_REF_CLK */ | ||
53 | +}; | ||
54 | + | ||
55 | static MemoryRegion *mr_for_raminfo(MPS3RMachineState *mms, | ||
56 | const RAMInfo *raminfo) | ||
87 | { | 57 | { |
88 | - hwaddr base; | 58 | @@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine) |
89 | + MachineState *ms = MACHINE(vms); | 59 | MPS3RMachineClass *mmc = MPS3R_MACHINE_GET_CLASS(mms); |
90 | + hwaddr base, device_memory_base, device_memory_size; | 60 | MemoryRegion *sysmem = get_system_memory(); |
91 | int i; | 61 | DeviceState *gicdev; |
92 | 62 | + QList *oscclk; | |
93 | vms->memmap = extended_memmap; | 63 | |
94 | @@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms) | 64 | mms->clk = clock_new(OBJECT(machine), "CLK"); |
95 | vms->memmap[i] = base_memmap[i]; | 65 | clock_set_hz(mms->clk, CLK_FRQ); |
66 | @@ -XXX,XX +XXX,XX @@ static void mps3r_common_init(MachineState *machine) | ||
67 | } | ||
96 | } | 68 | } |
97 | 69 | ||
98 | - base = 256 * GiB; /* Top of the legacy initial RAM region */ | 70 | + for (int i = 0; i < ARRAY_SIZE(mms->spi); i++) { |
99 | + if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { | 71 | + g_autofree char *s = g_strdup_printf("spi%d", i); |
100 | + error_report("unsupported number of memory slots: %"PRIu64, | 72 | + hwaddr baseaddr = 0xe0104000 + i * 0x1000; |
101 | + ms->ram_slots); | 73 | + |
102 | + exit(EXIT_FAILURE); | 74 | + object_initialize_child(OBJECT(mms), s, &mms->spi[i], TYPE_PL022); |
75 | + sysbus_realize(SYS_BUS_DEVICE(&mms->spi[i]), &error_fatal); | ||
76 | + sysbus_mmio_map(SYS_BUS_DEVICE(&mms->spi[i]), 0, baseaddr); | ||
77 | + sysbus_connect_irq(SYS_BUS_DEVICE(&mms->spi[i]), 0, | ||
78 | + qdev_get_gpio_in(gicdev, 22 + i)); | ||
103 | + } | 79 | + } |
104 | + | 80 | + |
81 | + object_initialize_child(OBJECT(mms), "scc", &mms->scc, TYPE_MPS2_SCC); | ||
82 | + qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg0", 0); | ||
83 | + qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-cfg4", 0x2); | ||
84 | + qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-aid", 0x00200008); | ||
85 | + qdev_prop_set_uint32(DEVICE(&mms->scc), "scc-id", 0x41055360); | ||
86 | + oscclk = qlist_new(); | ||
87 | + for (int i = 0; i < ARRAY_SIZE(an536_oscclk); i++) { | ||
88 | + qlist_append_int(oscclk, an536_oscclk[i]); | ||
89 | + } | ||
90 | + qdev_prop_set_array(DEVICE(&mms->scc), "oscclk", oscclk); | ||
91 | + sysbus_realize(SYS_BUS_DEVICE(&mms->scc), &error_fatal); | ||
92 | + sysbus_mmio_map(SYS_BUS_DEVICE(&mms->scc), 0, 0xe0200000); | ||
93 | + | ||
94 | + create_unimplemented_device("i2s-audio", 0xe0201000, 0x1000); | ||
95 | + | ||
96 | + object_initialize_child(OBJECT(mms), "fpgaio", &mms->fpgaio, | ||
97 | + TYPE_MPS2_FPGAIO); | ||
98 | + qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "prescale-clk", an536_oscclk[1]); | ||
99 | + qdev_prop_set_uint32(DEVICE(&mms->fpgaio), "num-leds", 10); | ||
100 | + qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-switches", true); | ||
101 | + qdev_prop_set_bit(DEVICE(&mms->fpgaio), "has-dbgctrl", false); | ||
102 | + sysbus_realize(SYS_BUS_DEVICE(&mms->fpgaio), &error_fatal); | ||
103 | + sysbus_mmio_map(SYS_BUS_DEVICE(&mms->fpgaio), 0, 0xe0202000); | ||
104 | + | ||
105 | + create_unimplemented_device("clcd", 0xe0209000, 0x1000); | ||
106 | + | ||
107 | + object_initialize_child(OBJECT(mms), "rtc", &mms->rtc, TYPE_PL031); | ||
108 | + sysbus_realize(SYS_BUS_DEVICE(&mms->rtc), &error_fatal); | ||
109 | + sysbus_mmio_map(SYS_BUS_DEVICE(&mms->rtc), 0, 0xe020a000); | ||
110 | + sysbus_connect_irq(SYS_BUS_DEVICE(&mms->rtc), 0, | ||
111 | + qdev_get_gpio_in(gicdev, 4)); | ||
112 | + | ||
105 | + /* | 113 | + /* |
106 | + * We compute the base of the high IO region depending on the | 114 | + * In hardware this is a LAN9220; the LAN9118 is software compatible |
107 | + * amount of initial and device memory. The device memory start/size | 115 | + * except that it doesn't support the checksum-offload feature. |
108 | + * is aligned on 1GiB. We never put the high IO region below 256GiB | ||
109 | + * so that if maxram_size is < 255GiB we keep the legacy memory map. | ||
110 | + * The device region size assumes 1GiB page max alignment per slot. | ||
111 | + */ | 116 | + */ |
112 | + device_memory_base = | 117 | + lan9118_init(0xe0300000, |
113 | + ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); | 118 | + qdev_get_gpio_in(gicdev, 18)); |
114 | + device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB; | ||
115 | + | 119 | + |
116 | + /* Base address of the high IO region */ | 120 | + create_unimplemented_device("usb", 0xe0301000, 0x1000); |
117 | + base = device_memory_base + ROUND_UP(device_memory_size, GiB); | 121 | + create_unimplemented_device("qspi-write-config", 0xe0600000, 0x1000); |
118 | + if (base < device_memory_base) { | 122 | + |
119 | + error_report("maxmem/slots too huge"); | 123 | mms->bootinfo.ram_size = machine->ram_size; |
120 | + exit(EXIT_FAILURE); | 124 | mms->bootinfo.board_id = -1; |
121 | + } | 125 | mms->bootinfo.loader_start = mmc->loader_start; |
122 | + if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { | ||
123 | + base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; | ||
124 | + } | ||
125 | |||
126 | for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { | ||
127 | hwaddr size = extended_memmap[i].size; | ||
128 | @@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms) | ||
129 | vms->memmap[i].size = size; | ||
130 | base += size; | ||
131 | } | ||
132 | + vms->highest_gpa = base - 1; | ||
133 | + if (device_memory_size > 0) { | ||
134 | + ms->device_memory = g_malloc0(sizeof(*ms->device_memory)); | ||
135 | + ms->device_memory->base = device_memory_base; | ||
136 | + memory_region_init(&ms->device_memory->mr, OBJECT(vms), | ||
137 | + "device-memory", device_memory_size); | ||
138 | + } | ||
139 | } | ||
140 | |||
141 | static void machvirt_init(MachineState *machine) | ||
142 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | ||
143 | vms->smp_cpus = smp_cpus; | ||
144 | |||
145 | if (machine->ram_size > vms->memmap[VIRT_MEM].size) { | ||
146 | - error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB); | ||
147 | + error_report("mach-virt: cannot model more than %dGB RAM", | ||
148 | + LEGACY_RAMLIMIT_GB); | ||
149 | exit(1); | ||
150 | } | ||
151 | |||
152 | @@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine) | ||
153 | memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", | ||
154 | machine->ram_size); | ||
155 | memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram); | ||
156 | + if (machine->device_memory) { | ||
157 | + memory_region_add_subregion(sysmem, machine->device_memory->base, | ||
158 | + &machine->device_memory->mr); | ||
159 | + } | ||
160 | |||
161 | create_flash(vms, sysmem, secure_sysmem ? secure_sysmem : sysmem); | ||
162 | |||
163 | -- | 126 | -- |
164 | 2.20.1 | 127 | 2.34.1 |
165 | 128 | ||
166 | 129 | diff view generated by jsdifflib |
1 | From: Eric Auger <eric.auger@redhat.com> | 1 | Add documentation for the mps3-an536 board type. |
---|---|---|---|
2 | 2 | ||
3 | The machine RAM attributes will need to be analyzed during the | 3 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
4 | configure_accelerator() process. especially kvm_type() arm64 | 4 | Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
5 | machine callback will use them to know how many IPA/GPA bits are | 5 | Message-id: 20240206132931.38376-14-peter.maydell@linaro.org |
6 | needed to model the whole RAM range. So let's assign those machine | 6 | --- |
7 | state fields before calling configure_accelerator. | 7 | docs/system/arm/mps2.rst | 37 ++++++++++++++++++++++++++++++++++--- |
8 | 1 file changed, 34 insertions(+), 3 deletions(-) | ||
8 | 9 | ||
9 | Signed-off-by: Eric Auger <eric.auger@redhat.com> | 10 | diff --git a/docs/system/arm/mps2.rst b/docs/system/arm/mps2.rst |
10 | Reviewed-by: Peter Maydell <peter.maydell@linaro.org> | ||
11 | Reviewed-by: Igor Mammedov <imammedo@redhat.com> | ||
12 | Message-id: 20190304101339.25970-7-eric.auger@redhat.com | ||
13 | Signed-off-by: Peter Maydell <peter.maydell@linaro.org> | ||
14 | --- | ||
15 | vl.c | 6 +++--- | ||
16 | 1 file changed, 3 insertions(+), 3 deletions(-) | ||
17 | |||
18 | diff --git a/vl.c b/vl.c | ||
19 | index XXXXXXX..XXXXXXX 100644 | 11 | index XXXXXXX..XXXXXXX 100644 |
20 | --- a/vl.c | 12 | --- a/docs/system/arm/mps2.rst |
21 | +++ b/vl.c | 13 | +++ b/docs/system/arm/mps2.rst |
22 | @@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv, char **envp) | 14 | @@ -XXX,XX +XXX,XX @@ |
23 | machine_opts = qemu_get_machine_opts(); | 15 | -Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an547``) |
24 | qemu_opt_foreach(machine_opts, machine_set_property, current_machine, | 16 | -========================================================================================================================================================= |
25 | &error_fatal); | 17 | +Arm MPS2 and MPS3 boards (``mps2-an385``, ``mps2-an386``, ``mps2-an500``, ``mps2-an505``, ``mps2-an511``, ``mps2-an521``, ``mps3-an524``, ``mps3-an536``, ``mps3-an547``) |
26 | + current_machine->ram_size = ram_size; | 18 | +========================================================================================================================================================================= |
27 | + current_machine->maxram_size = maxram_size; | 19 | |
28 | + current_machine->ram_slots = ram_slots; | 20 | -These board models all use Arm M-profile CPUs. |
29 | 21 | +These board models use Arm M-profile or R-profile CPUs. | |
30 | configure_accelerator(current_machine, argv[0]); | 22 | |
31 | 23 | The Arm MPS2, MPS2+ and MPS3 dev boards are FPGA based (the 2+ has a | |
32 | @@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv, char **envp) | 24 | bigger FPGA but is otherwise the same as the 2; the 3 has a bigger |
33 | replay_checkpoint(CHECKPOINT_INIT); | 25 | @@ -XXX,XX +XXX,XX @@ FPGA image. |
34 | qdev_machine_init(); | 26 | |
35 | 27 | QEMU models the following FPGA images: | |
36 | - current_machine->ram_size = ram_size; | 28 | |
37 | - current_machine->maxram_size = maxram_size; | 29 | +FPGA images using M-profile CPUs: |
38 | - current_machine->ram_slots = ram_slots; | 30 | + |
39 | current_machine->boot_order = boot_order; | 31 | ``mps2-an385`` |
40 | 32 | Cortex-M3 as documented in Arm Application Note AN385 | |
41 | /* parse features once if machine provides default cpu_type */ | 33 | ``mps2-an386`` |
34 | @@ -XXX,XX +XXX,XX @@ QEMU models the following FPGA images: | ||
35 | ``mps3-an547`` | ||
36 | Cortex-M55 on an MPS3, as documented in Arm Application Note AN547 | ||
37 | |||
38 | +FPGA images using R-profile CPUs: | ||
39 | + | ||
40 | +``mps3-an536`` | ||
41 | + Dual Cortex-R52 on an MPS3, as documented in Arm Application Note AN536 | ||
42 | + | ||
43 | Differences between QEMU and real hardware: | ||
44 | |||
45 | - AN385/AN386 remapping of low 16K of memory to either ZBT SSRAM1 or to | ||
46 | @@ -XXX,XX +XXX,XX @@ Differences between QEMU and real hardware: | ||
47 | flash, but only as simple ROM, so attempting to rewrite the flash | ||
48 | from the guest will fail | ||
49 | - QEMU does not model the USB controller in MPS3 boards | ||
50 | +- AN536 does not support runtime control of CPU reset and halt via | ||
51 | + the SCC CFG_REG0 register. | ||
52 | +- AN536 does not support enabling or disabling the flash and ATCM | ||
53 | + interfaces via the SCC CFG_REG1 register. | ||
54 | +- AN536 does not support setting of the initial vector table | ||
55 | + base address via the SCC CFG_REG6 and CFG_REG7 register config, | ||
56 | + and does not provide a mechanism for specifying these values at | ||
57 | + startup, so all guest images must be built to start from TCM | ||
58 | + (i.e. to expect the interrupt vector base at 0 from reset). | ||
59 | +- AN536 defaults to only creating a single CPU; this is the equivalent | ||
60 | + of the way the real FPGA image usually runs with the second Cortex-R52 | ||
61 | + held in halt via the initial SCC CFG_REG0 register setting. You can | ||
62 | + create the second CPU with ``-smp 2``; both CPUs will then start | ||
63 | + execution immediately on startup. | ||
64 | + | ||
65 | +Note that for the AN536 the first UART is accessible only by | ||
66 | +CPU0, and the second UART is accessible only by CPU1. The | ||
67 | +first UART accessible shared between both CPUs is the third | ||
68 | +UART. Guest software might therefore be built to use either | ||
69 | +the first UART or the third UART; if you don't see any output | ||
70 | +from the UART you are looking at, try one of the others. | ||
71 | +(Even if the AN536 machine is started with a single CPU and so | ||
72 | +no "CPU1-only UART", the UART numbering remains the same, | ||
73 | +with the third UART being the first of the shared ones.) | ||
74 | |||
75 | Machine-specific options | ||
76 | """""""""""""""""""""""" | ||
42 | -- | 77 | -- |
43 | 2.20.1 | 78 | 2.34.1 |
44 | 79 | ||
45 | 80 | diff view generated by jsdifflib |