1
target-arm queue for softfreeze:
1
Arm queue; not huge but I figured I might as well send it out since
2
This has all the big stuff I want to get in for softfreeze;
2
I've been doing code review today and there's no queue of unprocessed
3
there may be one or two smaller patches I pick up later in
3
pullreqs...
4
the week.
5
4
6
thanks
5
thanks
7
-- PMM
6
-- PMM
8
7
9
The following changes since commit 0984a157c1c053394adbf64ed7de97f1aebe6a2d:
8
The following changes since commit b3f846c59d8405bb87c551187721fc92ff2f1b92:
10
9
11
Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging (2019-03-05 09:33:20 +0000)
10
Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-11v2' into staging (2021-01-11 15:15:35 +0000)
12
11
13
are available in the Git repository at:
12
are available in the Git repository at:
14
13
15
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190305
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210112
16
15
17
for you to fetch changes up to 566528f823d1a2e9eb2d7b2ed839547cb31bfc34:
16
for you to fetch changes up to 19d131395ccaf503db21dadd8257e6dc9fc1d7de:
18
17
19
hw/arm/stellaris: Implement watchdog timer (2019-03-05 15:55:09 +0000)
18
ui/cocoa: Fix openFile: deprecation on Big Sur (2021-01-12 11:38:37 +0000)
20
19
21
----------------------------------------------------------------
20
----------------------------------------------------------------
22
target-arm queue:
21
target-arm queue:
23
* Fix PC test for LDM (exception return)
22
* arm: Support emulation of ARMv8.4-TTST extension
24
* Implement ARMv8.0-SB
23
* arm: Update cpu.h ID register field definitions
25
* Implement ARMv8.0-PredInv
24
* arm: Fix breakage of XScale instruction emulation
26
* Implement ARMv8.4-CondM
25
* hw/net/lan9118: Fix RX Status FIFO PEEK value
27
* Implement ARMv8.5-CondM
26
* npcm7xx: Add ADC and PWM emulation
28
* Implement ARMv8.5-FRINT
27
* ui/cocoa: Make "open docs" help menu entry work again when binary
29
* hw/arm/stellaris: Implement watchdog timer
28
is run from the build tree
30
* virt: support more than 255GB of RAM
29
* ui/cocoa: Fix openFile: deprecation on Big Sur
30
* docs: Add qemu-storage-daemon(1) manpage to meson.build
31
* docs: Build and install all the docs in a single manual
31
32
32
----------------------------------------------------------------
33
----------------------------------------------------------------
33
Eric Auger (9):
34
Hao Wu (6):
34
hw/arm/virt: Rename highmem IO regions
35
hw/misc: Add clock converter in NPCM7XX CLK module
35
hw/arm/virt: Split the memory map description
36
hw/timer: Refactor NPCM7XX Timer to use CLK clock
36
hw/boards: Add a MachineState parameter to kvm_type callback
37
hw/adc: Add an ADC module for NPCM7XX
37
kvm: add kvm_arm_get_max_vm_ipa_size
38
hw/misc: Add a PWM module for NPCM7XX
38
vl: Set machine ram_size, maxram_size and ram_slots earlier
39
hw/misc: Add QTest for NPCM7XX PWM Module
39
hw/arm/virt: Dynamic memory map depending on RAM requirements
40
hw/*: Use type casting for SysBusDevice in NPCM7XX
40
hw/arm/virt: Implement kvm_type function for 4.0 machine
41
hw/arm/virt: Check the VCPU PA range in TCG mode
42
hw/arm/virt: Bump the 255GB initial RAM limit
43
41
44
Michel Heily (1):
42
Leif Lindholm (6):
45
hw/arm/stellaris: Implement watchdog timer
43
target/arm: fix typo in cpu.h ID_AA64PFR1 field name
44
target/arm: make ARMCPU.clidr 64-bit
45
target/arm: make ARMCPU.ctr 64-bit
46
target/arm: add descriptions of CLIDR_EL1, CCSIDR_EL1, CTR_EL0 to cpu.h
47
target/arm: add aarch64 ID register fields to cpu.h
48
target/arm: add aarch32 ID register fields to cpu.h
46
49
47
Richard Henderson (11):
50
Peter Maydell (5):
48
target/arm: Fix PC test for LDM (exception return)
51
docs: Add qemu-storage-daemon(1) manpage to meson.build
49
target/arm: Split out arm_sctlr
52
docs: Build and install all the docs in a single manual
50
target/arm: Implement ARMv8.0-SB
53
target/arm: Don't decode insns in the XScale/iWMMXt space as cp insns
51
target/arm: Implement ARMv8.0-PredInv
54
hw/net/lan9118: Fix RX Status FIFO PEEK value
52
target/arm: Split helper_msr_i_pstate into 3
55
hw/net/lan9118: Add symbolic constants for register offsets
53
target/arm: Add set/clear_pstate_bits, share gen_ss_advance
54
target/arm: Rearrange disas_data_proc_reg
55
target/arm: Implement ARMv8.4-CondM
56
target/arm: Implement ARMv8.5-CondM
57
target/arm: Restructure handle_fp_1src_{single, double}
58
target/arm: Implement ARMv8.5-FRINT
59
56
60
Shameer Kolothum (1):
57
Roman Bolshakov (2):
61
hw/arm/boot: introduce fdt_add_memory_node helper
58
ui/cocoa: Update path to docs in build tree
59
ui/cocoa: Fix openFile: deprecation on Big Sur
62
60
63
include/hw/arm/virt.h | 16 +-
61
Rémi Denis-Courmont (2):
64
include/hw/boards.h | 5 +-
62
target/arm: ARMv8.4-TTST extension
65
include/hw/watchdog/cmsdk-apb-watchdog.h | 8 +
63
target/arm: enable Small Translation tables in max CPU
66
target/arm/cpu.h | 64 ++++-
67
target/arm/helper-a64.h | 3 +
68
target/arm/helper.h | 8 +-
69
target/arm/internals.h | 15 +
70
target/arm/kvm_arm.h | 13 +
71
target/arm/translate.h | 34 +++
72
accel/kvm/kvm-all.c | 2 +-
73
hw/arm/boot.c | 54 ++--
74
hw/arm/stellaris.c | 22 +-
75
hw/arm/virt-acpi-build.c | 10 +-
76
hw/arm/virt.c | 196 ++++++++++---
77
hw/ppc/mac_newworld.c | 3 +-
78
hw/ppc/mac_oldworld.c | 2 +-
79
hw/ppc/spapr.c | 2 +-
80
hw/watchdog/cmsdk-apb-watchdog.c | 74 ++++-
81
linux-user/elfload.c | 2 +
82
target/arm/cpu.c | 2 +
83
target/arm/cpu64.c | 6 +
84
target/arm/helper-a64.c | 30 ++
85
target/arm/helper.c | 63 +++-
86
target/arm/kvm.c | 10 +
87
target/arm/op_helper.c | 47 ---
88
target/arm/translate-a64.c | 478 +++++++++++++++++++++++--------
89
target/arm/translate.c | 35 ++-
90
target/arm/vfp_helper.c | 96 +++++++
91
vl.c | 6 +-
92
29 files changed, 1032 insertions(+), 274 deletions(-)
93
64
65
docs/conf.py | 46 ++-
66
docs/devel/conf.py | 15 -
67
docs/index.html.in | 17 -
68
docs/interop/conf.py | 28 --
69
docs/meson.build | 65 ++--
70
docs/specs/conf.py | 16 -
71
docs/system/arm/nuvoton.rst | 4 +-
72
docs/system/conf.py | 28 --
73
docs/tools/conf.py | 37 --
74
docs/user/conf.py | 15 -
75
meson.build | 1 +
76
hw/adc/trace.h | 1 +
77
include/hw/adc/npcm7xx_adc.h | 69 ++++
78
include/hw/arm/npcm7xx.h | 4 +
79
include/hw/misc/npcm7xx_clk.h | 146 ++++++-
80
include/hw/misc/npcm7xx_pwm.h | 105 +++++
81
include/hw/timer/npcm7xx_timer.h | 1 +
82
target/arm/cpu.h | 85 ++++-
83
hw/adc/npcm7xx_adc.c | 301 +++++++++++++++
84
hw/arm/npcm7xx.c | 55 ++-
85
hw/arm/npcm7xx_boards.c | 2 +-
86
hw/mem/npcm7xx_mc.c | 2 +-
87
hw/misc/npcm7xx_clk.c | 807 ++++++++++++++++++++++++++++++++++++++-
88
hw/misc/npcm7xx_gcr.c | 2 +-
89
hw/misc/npcm7xx_pwm.c | 550 ++++++++++++++++++++++++++
90
hw/misc/npcm7xx_rng.c | 2 +-
91
hw/net/lan9118.c | 26 +-
92
hw/nvram/npcm7xx_otp.c | 2 +-
93
hw/ssi/npcm7xx_fiu.c | 2 +-
94
hw/timer/npcm7xx_timer.c | 39 +-
95
target/arm/cpu64.c | 1 +
96
target/arm/helper.c | 15 +-
97
target/arm/translate.c | 7 +
98
tests/qtest/npcm7xx_adc-test.c | 377 ++++++++++++++++++
99
tests/qtest/npcm7xx_pwm-test.c | 490 ++++++++++++++++++++++++
100
hw/adc/meson.build | 1 +
101
hw/adc/trace-events | 5 +
102
hw/misc/meson.build | 1 +
103
hw/misc/trace-events | 6 +
104
tests/qtest/meson.build | 4 +-
105
ui/cocoa.m | 7 +-
106
41 files changed, 3124 insertions(+), 263 deletions(-)
107
delete mode 100644 docs/devel/conf.py
108
delete mode 100644 docs/index.html.in
109
delete mode 100644 docs/interop/conf.py
110
delete mode 100644 docs/specs/conf.py
111
delete mode 100644 docs/system/conf.py
112
delete mode 100644 docs/tools/conf.py
113
delete mode 100644 docs/user/conf.py
114
create mode 100644 hw/adc/trace.h
115
create mode 100644 include/hw/adc/npcm7xx_adc.h
116
create mode 100644 include/hw/misc/npcm7xx_pwm.h
117
create mode 100644 hw/adc/npcm7xx_adc.c
118
create mode 100644 hw/misc/npcm7xx_pwm.c
119
create mode 100644 tests/qtest/npcm7xx_adc-test.c
120
create mode 100644 tests/qtest/npcm7xx_pwm-test.c
121
create mode 100644 hw/adc/trace-events
122
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
This adds for the Small Translation tables extension in AArch64 state.
4
Message-id: 20190301200501.16533-4-richard.henderson@linaro.org
4
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
8
---
8
target/arm/cpu.h | 13 ++++++++++-
9
target/arm/cpu.h | 5 +++++
9
target/arm/cpu.c | 1 +
10
target/arm/helper.c | 15 +++++++++++++--
10
target/arm/cpu64.c | 2 ++
11
2 files changed, 18 insertions(+), 2 deletions(-)
11
target/arm/helper.c | 55 +++++++++++++++++++++++++++++++++++++++++++++
12
4 files changed, 70 insertions(+), 1 deletion(-)
13
12
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
13
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.h
15
--- a/target/arm/cpu.h
17
+++ b/target/arm/cpu.h
16
+++ b/target/arm/cpu.h
18
@@ -XXX,XX +XXX,XX @@ void pmu_init(ARMCPU *cpu);
17
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_uao(const ARMISARegisters *id)
19
#define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */
18
return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) != 0;
20
#define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */
21
#define SCTLR_F (1U << 10) /* up to v6 */
22
-#define SCTLR_SW (1U << 10) /* v7, RES0 in v8 */
23
+#define SCTLR_SW (1U << 10) /* v7 */
24
+#define SCTLR_EnRCTX (1U << 10) /* in v8.0-PredInv */
25
#define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */
26
#define SCTLR_EOS (1U << 11) /* v8.5-ExS */
27
#define SCTLR_I (1U << 12)
28
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_sb(const ARMISARegisters *id)
29
return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0;
30
}
19
}
31
20
32
+static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
21
+static inline bool isar_feature_aa64_st(const ARMISARegisters *id)
33
+{
22
+{
34
+ return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
23
+ return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) != 0;
35
+}
24
+}
36
+
25
+
37
static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
26
static inline bool isar_feature_aa64_bti(const ARMISARegisters *id)
38
{
27
{
39
/*
28
return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) != 0;
40
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
41
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
42
}
43
44
+static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id)
45
+{
46
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0;
47
+}
48
+
49
static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
50
{
51
/* We always set the AdvSIMD and FP fields identically wrt FP16. */
52
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/cpu.c
55
+++ b/target/arm/cpu.c
56
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
57
t = FIELD_DP32(t, ID_ISAR6, DP, 1);
58
t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
59
t = FIELD_DP32(t, ID_ISAR6, SB, 1);
60
+ t = FIELD_DP32(t, ID_ISAR6, SPECRES, 1);
61
cpu->isar.id_isar6 = t;
62
63
t = cpu->id_mmfr4;
64
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
65
index XXXXXXX..XXXXXXX 100644
66
--- a/target/arm/cpu64.c
67
+++ b/target/arm/cpu64.c
68
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
69
t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1);
70
t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0);
71
t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
72
+ t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
73
cpu->isar.id_aa64isar1 = t;
74
75
t = cpu->isar.id_aa64pfr0;
76
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
77
u = FIELD_DP32(u, ID_ISAR6, DP, 1);
78
u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
79
u = FIELD_DP32(u, ID_ISAR6, SB, 1);
80
+ u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
81
cpu->isar.id_isar6 = u;
82
83
/*
84
diff --git a/target/arm/helper.c b/target/arm/helper.c
29
diff --git a/target/arm/helper.c b/target/arm/helper.c
85
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
86
--- a/target/arm/helper.c
31
--- a/target/arm/helper.c
87
+++ b/target/arm/helper.c
32
+++ b/target/arm/helper.c
88
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo pauth_reginfo[] = {
33
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
89
};
34
{
90
#endif
35
uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
91
36
bool epd, hpd, using16k, using64k;
92
+static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
37
- int select, tsz, tbi;
93
+ bool isread)
38
+ int select, tsz, tbi, max_tsz;
94
+{
39
95
+ int el = arm_current_el(env);
40
if (!regime_has_2_ranges(mmu_idx)) {
41
select = 0;
42
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
43
hpd = extract64(tcr, 42, 1);
44
}
45
}
46
- tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */
96
+
47
+
97
+ if (el == 0) {
48
+ if (cpu_isar_feature(aa64_st, env_archcpu(env))) {
98
+ uint64_t sctlr = arm_sctlr(env, el);
49
+ max_tsz = 48 - using64k;
99
+ if (!(sctlr & SCTLR_EnRCTX)) {
50
+ } else {
100
+ return CP_ACCESS_TRAP;
51
+ max_tsz = 39;
101
+ }
102
+ } else if (el == 1) {
103
+ uint64_t hcr = arm_hcr_el2_eff(env);
104
+ if (hcr & HCR_NV) {
105
+ return CP_ACCESS_TRAP_EL2;
106
+ }
107
+ }
52
+ }
108
+ return CP_ACCESS_OK;
109
+}
110
+
53
+
111
+static const ARMCPRegInfo predinv_reginfo[] = {
54
+ tsz = MIN(tsz, max_tsz);
112
+ { .name = "CFP_RCTX", .state = ARM_CP_STATE_AA64,
55
tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */
113
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 4,
56
114
+ .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
57
/* Present TBI as a composite with TBID. */
115
+ { .name = "DVP_RCTX", .state = ARM_CP_STATE_AA64,
58
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
116
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 5,
59
if (!aarch64 || stride == 9) {
117
+ .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
60
/* AArch32 or 4KB pages */
118
+ { .name = "CPP_RCTX", .state = ARM_CP_STATE_AA64,
61
startlevel = 2 - sl0;
119
+ .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 3, .opc2 = 7,
120
+ .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
121
+ /*
122
+ * Note the AArch32 opcodes have a different OPC1.
123
+ */
124
+ { .name = "CFPRCTX", .state = ARM_CP_STATE_AA32,
125
+ .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 4,
126
+ .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
127
+ { .name = "DVPRCTX", .state = ARM_CP_STATE_AA32,
128
+ .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 5,
129
+ .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
130
+ { .name = "CPPRCTX", .state = ARM_CP_STATE_AA32,
131
+ .cp = 15, .opc1 = 0, .crn = 7, .crm = 3, .opc2 = 7,
132
+ .type = ARM_CP_NOP, .access = PL0_W, .accessfn = access_predinv },
133
+ REGINFO_SENTINEL
134
+};
135
+
62
+
136
void register_cp_regs_for_features(ARMCPU *cpu)
63
+ if (cpu_isar_feature(aa64_st, cpu)) {
137
{
64
+ startlevel &= 3;
138
/* Register all the coprocessor registers based on feature bits */
65
+ }
139
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
66
} else {
140
define_arm_cp_regs(cpu, pauth_reginfo);
67
/* 16KB or 64KB pages */
141
}
68
startlevel = 3 - sl0;
142
#endif
143
+
144
+ /*
145
+ * While all v8.0 cpus support aarch64, QEMU does have configurations
146
+ * that do not set ID_AA64ISAR1, e.g. user-only qemu-arm -cpu max,
147
+ * which will set ID_ISAR6.
148
+ */
149
+ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)
150
+ ? cpu_isar_feature(aa64_predinv, cpu)
151
+ : cpu_isar_feature(aa32_predinv, cpu)) {
152
+ define_arm_cp_regs(cpu, predinv_reginfo);
153
+ }
154
}
155
156
void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
157
--
69
--
158
2.20.1
70
2.20.1
159
71
160
72
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
2
2
3
Now we have the extended memory map (high IO regions beyond the
3
Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
4
scalable RAM) and dynamic IPA range support at KVM/ARM level
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
we can bump the legacy 255GB initial RAM limit. The actual maximum
6
RAM size now depends on the physical CPU and host kernel, in
7
accelerated mode. In TCG mode, it depends on the VCPU
8
AA64MMFR0.PARANGE.
9
10
Signed-off-by: Eric Auger <eric.auger@redhat.com>
11
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
12
Message-id: 20190304101339.25970-11-eric.auger@redhat.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
6
---
15
hw/arm/virt.c | 21 +--------------------
7
target/arm/cpu64.c | 1 +
16
1 file changed, 1 insertion(+), 20 deletions(-)
8
1 file changed, 1 insertion(+)
17
9
18
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
10
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
19
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/arm/virt.c
12
--- a/target/arm/cpu64.c
21
+++ b/hw/arm/virt.c
13
+++ b/target/arm/cpu64.c
22
@@ -XXX,XX +XXX,XX @@
14
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
23
15
t = cpu->isar.id_aa64mmfr2;
24
#define PLATFORM_BUS_NUM_IRQS 64
16
t = FIELD_DP64(t, ID_AA64MMFR2, UAO, 1);
25
17
t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
26
-/* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means
18
+ t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
27
- * RAM can go up to the 256GB mark, leaving 256GB of the physical
19
cpu->isar.id_aa64mmfr2 = t;
28
- * address space unallocated and free for future use between 256G and 512G.
20
29
- * If we need to provide more RAM to VMs in the future then we need to:
21
/* Replicate the same data to the 32-bit id registers. */
30
- * * allocate a second bank of RAM starting at 2TB and working up
31
- * * fix the DT and ACPI table generation code in QEMU to correctly
32
- * report two split lumps of RAM to the guest
33
- * * fix KVM in the host kernel to allow guests with >40 bit address spaces
34
- * (We don't want to fill all the way up to 512GB with RAM because
35
- * we might want it for non-RAM purposes later. Conversely it seems
36
- * reasonable to assume that anybody configuring a VM with a quarter
37
- * of a terabyte of RAM will be doing it on a host with more than a
38
- * terabyte of physical address space.)
39
- */
40
+/* Legacy RAM limit in GB (< version 4.0) */
41
#define LEGACY_RAMLIMIT_GB 255
42
#define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
43
44
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
45
46
vms->smp_cpus = smp_cpus;
47
48
- if (machine->ram_size > vms->memmap[VIRT_MEM].size) {
49
- error_report("mach-virt: cannot model more than %dGB RAM",
50
- LEGACY_RAMLIMIT_GB);
51
- exit(1);
52
- }
53
-
54
if (vms->virt && kvm_enabled()) {
55
error_report("mach-virt: KVM does not support providing "
56
"Virtualization extensions to the guest CPU");
57
--
22
--
58
2.20.1
23
2.20.1
59
24
60
25
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Leif Lindholm <leif@nuviainc.com>
2
2
3
In the prospect to introduce an extended memory map supporting more
3
SBSS -> SSBS
4
RAM, let's split the memory map array into two parts:
5
4
6
- the former a15memmap, renamed base_memmap, contains regions below
5
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
7
and including the RAM. MemMapEntries initialized in this array
6
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
have a static size and base address.
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
- extended_memmap, only initialized with entries located after the
8
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
10
RAM. MemMapEntries initialized in this array only get their size
9
Message-id: 20210108185154.8108-2-leif@nuviainc.com
11
initialized. Their base address is dynamically computed depending
12
on the the top of the RAM, with same alignment as their size.
13
14
Eventually base_memmap entries are copied into the extended_memmap
15
array. Using two separate arrays however clarifies which entries
16
are statically allocated and those which are dynamically allocated.
17
18
This new split will allow to grow the RAM size without changing the
19
description of the high IO entries.
20
21
We introduce a new virt_set_memmap() helper function which
22
"freezes" the memory map. We call it in machvirt_init as
23
memory attributes of the machine are not yet set when
24
virt_instance_init() gets called.
25
26
The memory map is unchanged (the top of the initial RAM still is
27
256GiB). Then come the high IO regions with same layout as before.
28
29
Signed-off-by: Eric Auger <eric.auger@redhat.com>
30
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
31
Message-id: 20190304101339.25970-4-eric.auger@redhat.com
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
---
11
---
34
include/hw/arm/virt.h | 13 +++++++----
12
target/arm/cpu.h | 2 +-
35
hw/arm/virt.c | 50 +++++++++++++++++++++++++++++++++++++------
13
1 file changed, 1 insertion(+), 1 deletion(-)
36
2 files changed, 53 insertions(+), 10 deletions(-)
37
14
38
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
39
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
40
--- a/include/hw/arm/virt.h
17
--- a/target/arm/cpu.h
41
+++ b/include/hw/arm/virt.h
18
+++ b/target/arm/cpu.h
42
@@ -XXX,XX +XXX,XX @@ enum {
19
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, RAS, 28, 4)
43
VIRT_GIC_VCPU,
20
FIELD(ID_AA64PFR0, SVE, 32, 4)
44
VIRT_GIC_ITS,
21
45
VIRT_GIC_REDIST,
22
FIELD(ID_AA64PFR1, BT, 0, 4)
46
- VIRT_HIGH_GIC_REDIST2,
23
-FIELD(ID_AA64PFR1, SBSS, 4, 4)
47
VIRT_SMMU,
24
+FIELD(ID_AA64PFR1, SSBS, 4, 4)
48
VIRT_UART,
25
FIELD(ID_AA64PFR1, MTE, 8, 4)
49
VIRT_MMIO,
26
FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
50
@@ -XXX,XX +XXX,XX @@ enum {
51
VIRT_PCIE_MMIO,
52
VIRT_PCIE_PIO,
53
VIRT_PCIE_ECAM,
54
- VIRT_HIGH_PCIE_ECAM,
55
VIRT_PLATFORM_BUS,
56
- VIRT_HIGH_PCIE_MMIO,
57
VIRT_GPIO,
58
VIRT_SECURE_UART,
59
VIRT_SECURE_MEM,
60
+ VIRT_LOWMEMMAP_LAST,
61
+};
62
+
63
+/* indices of IO regions located after the RAM */
64
+enum {
65
+ VIRT_HIGH_GIC_REDIST2 = VIRT_LOWMEMMAP_LAST,
66
+ VIRT_HIGH_PCIE_ECAM,
67
+ VIRT_HIGH_PCIE_MMIO,
68
};
69
70
typedef enum VirtIOMMUType {
71
@@ -XXX,XX +XXX,XX @@ typedef struct {
72
int32_t gic_version;
73
VirtIOMMUType iommu;
74
struct arm_boot_info bootinfo;
75
- const MemMapEntry *memmap;
76
+ MemMapEntry *memmap;
77
const int *irqmap;
78
int smp_cpus;
79
void *fdt;
80
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
81
index XXXXXXX..XXXXXXX 100644
82
--- a/hw/arm/virt.c
83
+++ b/hw/arm/virt.c
84
@@ -XXX,XX +XXX,XX @@
85
*/
86
87
#include "qemu/osdep.h"
88
+#include "qemu/units.h"
89
#include "qapi/error.h"
90
#include "hw/sysbus.h"
91
#include "hw/arm/arm.h"
92
@@ -XXX,XX +XXX,XX @@
93
* Note that devices should generally be placed at multiples of 0x10000,
94
* to accommodate guests using 64K pages.
95
*/
96
-static const MemMapEntry a15memmap[] = {
97
+static const MemMapEntry base_memmap[] = {
98
/* Space up to 0x8000000 is reserved for a boot ROM */
99
[VIRT_FLASH] = { 0, 0x08000000 },
100
[VIRT_CPUPERIPHS] = { 0x08000000, 0x00020000 },
101
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry a15memmap[] = {
102
[VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
103
[VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
104
[VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES },
105
+};
106
+
107
+/*
108
+ * Highmem IO Regions: This memory map is floating, located after the RAM.
109
+ * Each MemMapEntry base (GPA) will be dynamically computed, depending on the
110
+ * top of the RAM, so that its base get the same alignment as the size,
111
+ * ie. a 512GiB entry will be aligned on a 512GiB boundary. If there is
112
+ * less than 256GiB of RAM, the floating area starts at the 256GiB mark.
113
+ * Note the extended_memmap is sized so that it eventually also includes the
114
+ * base_memmap entries (VIRT_HIGH_GIC_REDIST2 index is greater than the last
115
+ * index of base_memmap).
116
+ */
117
+static MemMapEntry extended_memmap[] = {
118
/* Additional 64 MB redist region (can contain up to 512 redistributors) */
119
- [VIRT_HIGH_GIC_REDIST2] = { 0x4000000000ULL, 0x4000000 },
120
- [VIRT_HIGH_PCIE_ECAM] = { 0x4010000000ULL, 0x10000000 },
121
- /* Second PCIe window, 512GB wide at the 512GB boundary */
122
- [VIRT_HIGH_PCIE_MMIO] = { 0x8000000000ULL, 0x8000000000ULL },
123
+ [VIRT_HIGH_GIC_REDIST2] = { 0x0, 64 * MiB },
124
+ [VIRT_HIGH_PCIE_ECAM] = { 0x0, 256 * MiB },
125
+ /* Second PCIe window */
126
+ [VIRT_HIGH_PCIE_MMIO] = { 0x0, 512 * GiB },
127
};
128
129
static const int a15irqmap[] = {
130
@@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
131
return arm_cpu_mp_affinity(idx, clustersz);
132
}
133
134
+static void virt_set_memmap(VirtMachineState *vms)
135
+{
136
+ hwaddr base;
137
+ int i;
138
+
139
+ vms->memmap = extended_memmap;
140
+
141
+ for (i = 0; i < ARRAY_SIZE(base_memmap); i++) {
142
+ vms->memmap[i] = base_memmap[i];
143
+ }
144
+
145
+ base = 256 * GiB; /* Top of the legacy initial RAM region */
146
+
147
+ for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
148
+ hwaddr size = extended_memmap[i].size;
149
+
150
+ base = ROUND_UP(base, size);
151
+ vms->memmap[i].base = base;
152
+ vms->memmap[i].size = size;
153
+ base += size;
154
+ }
155
+}
156
+
157
static void machvirt_init(MachineState *machine)
158
{
159
VirtMachineState *vms = VIRT_MACHINE(machine);
160
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
161
bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0);
162
bool aarch64 = true;
163
164
+ virt_set_memmap(vms);
165
+
166
/* We can probe only here because during property set
167
* KVM is not available yet
168
*/
169
@@ -XXX,XX +XXX,XX @@ static void virt_instance_init(Object *obj)
170
"Valid values are none and smmuv3",
171
NULL);
172
173
- vms->memmap = a15memmap;
174
vms->irqmap = a15irqmap;
175
}
176
27
177
--
28
--
178
2.20.1
29
2.20.1
179
30
180
31
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Leif Lindholm <leif@nuviainc.com>
2
2
3
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
3
The AArch64 view of CLIDR_EL1 extends the ICB field to include also bit
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
32, as well as adding a Ttype<n> field when FEAT_MTE is implemented.
5
Message-id: 20190301200501.16533-11-richard.henderson@linaro.org
5
Extend the clidr field to be able to hold this context.
6
7
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
11
Message-id: 20210108185154.8108-3-leif@nuviainc.com
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
13
---
9
target/arm/cpu.h | 5 ++
14
target/arm/cpu.h | 2 +-
10
target/arm/helper.h | 5 ++
15
1 file changed, 1 insertion(+), 1 deletion(-)
11
target/arm/cpu64.c | 1 +
12
target/arm/translate-a64.c | 71 ++++++++++++++++++++++++++--
13
target/arm/vfp_helper.c | 96 ++++++++++++++++++++++++++++++++++++++
14
5 files changed, 173 insertions(+), 5 deletions(-)
15
16
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
19
--- a/target/arm/cpu.h
19
+++ b/target/arm/cpu.h
20
+++ b/target/arm/cpu.h
20
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_predinv(const ARMISARegisters *id)
21
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
21
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SPECRES) != 0;
22
uint32_t id_afr0;
22
}
23
uint64_t id_aa64afr0;
23
24
uint64_t id_aa64afr1;
24
+static inline bool isar_feature_aa64_frint(const ARMISARegisters *id)
25
- uint32_t clidr;
25
+{
26
+ uint64_t clidr;
26
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FRINTTS) != 0;
27
uint64_t mp_affinity; /* MP ID without feature bits */
27
+}
28
/* The elements of this array are the CCSIDR values for each cache,
28
+
29
* in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
29
static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
30
{
31
/* We always set the AdvSIMD and FP fields identically wrt FP16. */
32
diff --git a/target/arm/helper.h b/target/arm/helper.h
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/helper.h
35
+++ b/target/arm/helper.h
36
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a32, TCG_CALL_NO_RWG,
37
DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a64, TCG_CALL_NO_RWG,
38
void, ptr, ptr, ptr, ptr, i32)
39
40
+DEF_HELPER_FLAGS_2(frint32_s, TCG_CALL_NO_RWG, f32, f32, ptr)
41
+DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f32, ptr)
42
+DEF_HELPER_FLAGS_2(frint32_d, TCG_CALL_NO_RWG, f64, f64, ptr)
43
+DEF_HELPER_FLAGS_2(frint64_d, TCG_CALL_NO_RWG, f64, f64, ptr)
44
+
45
#ifdef TARGET_AARCH64
46
#include "helper-a64.h"
47
#include "helper-sve.h"
48
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/target/arm/cpu64.c
51
+++ b/target/arm/cpu64.c
52
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
53
t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0);
54
t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
55
t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1);
56
+ t = FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1);
57
cpu->isar.id_aa64isar1 = t;
58
59
t = cpu->isar.id_aa64pfr0;
60
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
61
index XXXXXXX..XXXXXXX 100644
62
--- a/target/arm/translate-a64.c
63
+++ b/target/arm/translate-a64.c
64
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
65
case 0xf: /* FRINTI */
66
gen_fpst = gen_helper_rints;
67
break;
68
+ case 0x10: /* FRINT32Z */
69
+ rmode = float_round_to_zero;
70
+ gen_fpst = gen_helper_frint32_s;
71
+ break;
72
+ case 0x11: /* FRINT32X */
73
+ gen_fpst = gen_helper_frint32_s;
74
+ break;
75
+ case 0x12: /* FRINT64Z */
76
+ rmode = float_round_to_zero;
77
+ gen_fpst = gen_helper_frint64_s;
78
+ break;
79
+ case 0x13: /* FRINT64X */
80
+ gen_fpst = gen_helper_frint64_s;
81
+ break;
82
default:
83
g_assert_not_reached();
84
}
85
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
86
case 0xf: /* FRINTI */
87
gen_fpst = gen_helper_rintd;
88
break;
89
+ case 0x10: /* FRINT32Z */
90
+ rmode = float_round_to_zero;
91
+ gen_fpst = gen_helper_frint32_d;
92
+ break;
93
+ case 0x11: /* FRINT32X */
94
+ gen_fpst = gen_helper_frint32_d;
95
+ break;
96
+ case 0x12: /* FRINT64Z */
97
+ rmode = float_round_to_zero;
98
+ gen_fpst = gen_helper_frint64_d;
99
+ break;
100
+ case 0x13: /* FRINT64X */
101
+ gen_fpst = gen_helper_frint64_d;
102
+ break;
103
default:
104
g_assert_not_reached();
105
}
106
@@ -XXX,XX +XXX,XX @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
107
handle_fp_fcvt(s, opcode, rd, rn, dtype, type);
108
break;
109
}
110
+
111
+ case 0x10 ... 0x13: /* FRINT{32,64}{X,Z} */
112
+ if (type > 1 || !dc_isar_feature(aa64_frint, s)) {
113
+ unallocated_encoding(s);
114
+ return;
115
+ }
116
+ /* fall through */
117
case 0x0 ... 0x3:
118
case 0x8 ... 0xc:
119
case 0xe ... 0xf:
120
@@ -XXX,XX +XXX,XX @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
121
if (!fp_access_check(s)) {
122
return;
123
}
124
-
125
handle_fp_1src_single(s, opcode, rd, rn);
126
break;
127
case 1:
128
if (!fp_access_check(s)) {
129
return;
130
}
131
-
132
handle_fp_1src_double(s, opcode, rd, rn);
133
break;
134
case 3:
135
@@ -XXX,XX +XXX,XX @@ static void disas_fp_1src(DisasContext *s, uint32_t insn)
136
if (!fp_access_check(s)) {
137
return;
138
}
139
-
140
handle_fp_1src_half(s, opcode, rd, rn);
141
break;
142
default:
143
unallocated_encoding(s);
144
}
145
break;
146
+
147
default:
148
unallocated_encoding(s);
149
break;
150
@@ -XXX,XX +XXX,XX @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u,
151
case 0x59: /* FRINTX */
152
gen_helper_rintd_exact(tcg_rd, tcg_rn, tcg_fpstatus);
153
break;
154
+ case 0x1e: /* FRINT32Z */
155
+ case 0x5e: /* FRINT32X */
156
+ gen_helper_frint32_d(tcg_rd, tcg_rn, tcg_fpstatus);
157
+ break;
158
+ case 0x1f: /* FRINT64Z */
159
+ case 0x5f: /* FRINT64X */
160
+ gen_helper_frint64_d(tcg_rd, tcg_rn, tcg_fpstatus);
161
+ break;
162
default:
163
g_assert_not_reached();
164
}
165
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
166
}
167
break;
168
case 0xc ... 0xf:
169
- case 0x16 ... 0x1d:
170
- case 0x1f:
171
+ case 0x16 ... 0x1f:
172
{
173
/* Floating point: U, size[1] and opcode indicate operation;
174
* size[0] indicates single or double precision.
175
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
176
}
177
need_fpstatus = true;
178
break;
179
+ case 0x1e: /* FRINT32Z */
180
+ case 0x1f: /* FRINT64Z */
181
+ need_rmode = true;
182
+ rmode = FPROUNDING_ZERO;
183
+ /* fall through */
184
+ case 0x5e: /* FRINT32X */
185
+ case 0x5f: /* FRINT64X */
186
+ need_fpstatus = true;
187
+ if ((size == 3 && !is_q) || !dc_isar_feature(aa64_frint, s)) {
188
+ unallocated_encoding(s);
189
+ return;
190
+ }
191
+ break;
192
default:
193
unallocated_encoding(s);
194
return;
195
@@ -XXX,XX +XXX,XX @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
196
case 0x7c: /* URSQRTE */
197
gen_helper_rsqrte_u32(tcg_res, tcg_op, tcg_fpstatus);
198
break;
199
+ case 0x1e: /* FRINT32Z */
200
+ case 0x5e: /* FRINT32X */
201
+ gen_helper_frint32_s(tcg_res, tcg_op, tcg_fpstatus);
202
+ break;
203
+ case 0x1f: /* FRINT64Z */
204
+ case 0x5f: /* FRINT64X */
205
+ gen_helper_frint64_s(tcg_res, tcg_op, tcg_fpstatus);
206
+ break;
207
default:
208
g_assert_not_reached();
209
}
210
diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c
211
index XXXXXXX..XXXXXXX 100644
212
--- a/target/arm/vfp_helper.c
213
+++ b/target/arm/vfp_helper.c
214
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(vjcvt)(float64 value, CPUARMState *env)
215
216
return result;
217
}
218
+
219
+/* Round a float32 to an integer that fits in int32_t or int64_t. */
220
+static float32 frint_s(float32 f, float_status *fpst, int intsize)
221
+{
222
+ int old_flags = get_float_exception_flags(fpst);
223
+ uint32_t exp = extract32(f, 23, 8);
224
+
225
+ if (unlikely(exp == 0xff)) {
226
+ /* NaN or Inf. */
227
+ goto overflow;
228
+ }
229
+
230
+ /* Round and re-extract the exponent. */
231
+ f = float32_round_to_int(f, fpst);
232
+ exp = extract32(f, 23, 8);
233
+
234
+ /* Validate the range of the result. */
235
+ if (exp < 126 + intsize) {
236
+ /* abs(F) <= INT{N}_MAX */
237
+ return f;
238
+ }
239
+ if (exp == 126 + intsize) {
240
+ uint32_t sign = extract32(f, 31, 1);
241
+ uint32_t frac = extract32(f, 0, 23);
242
+ if (sign && frac == 0) {
243
+ /* F == INT{N}_MIN */
244
+ return f;
245
+ }
246
+ }
247
+
248
+ overflow:
249
+ /*
250
+ * Raise Invalid and return INT{N}_MIN as a float. Revert any
251
+ * inexact exception float32_round_to_int may have raised.
252
+ */
253
+ set_float_exception_flags(old_flags | float_flag_invalid, fpst);
254
+ return (0x100u + 126u + intsize) << 23;
255
+}
256
+
257
+float32 HELPER(frint32_s)(float32 f, void *fpst)
258
+{
259
+ return frint_s(f, fpst, 32);
260
+}
261
+
262
+float32 HELPER(frint64_s)(float32 f, void *fpst)
263
+{
264
+ return frint_s(f, fpst, 64);
265
+}
266
+
267
+/* Round a float64 to an integer that fits in int32_t or int64_t. */
268
+static float64 frint_d(float64 f, float_status *fpst, int intsize)
269
+{
270
+ int old_flags = get_float_exception_flags(fpst);
271
+ uint32_t exp = extract64(f, 52, 11);
272
+
273
+ if (unlikely(exp == 0x7ff)) {
274
+ /* NaN or Inf. */
275
+ goto overflow;
276
+ }
277
+
278
+ /* Round and re-extract the exponent. */
279
+ f = float64_round_to_int(f, fpst);
280
+ exp = extract64(f, 52, 11);
281
+
282
+ /* Validate the range of the result. */
283
+ if (exp < 1022 + intsize) {
284
+ /* abs(F) <= INT{N}_MAX */
285
+ return f;
286
+ }
287
+ if (exp == 1022 + intsize) {
288
+ uint64_t sign = extract64(f, 63, 1);
289
+ uint64_t frac = extract64(f, 0, 52);
290
+ if (sign && frac == 0) {
291
+ /* F == INT{N}_MIN */
292
+ return f;
293
+ }
294
+ }
295
+
296
+ overflow:
297
+ /*
298
+ * Raise Invalid and return INT{N}_MIN as a float. Revert any
299
+ * inexact exception float64_round_to_int may have raised.
300
+ */
301
+ set_float_exception_flags(old_flags | float_flag_invalid, fpst);
302
+ return (uint64_t)(0x800 + 1022 + intsize) << 52;
303
+}
304
+
305
+float64 HELPER(frint32_d)(float64 f, void *fpst)
306
+{
307
+ return frint_d(f, fpst, 32);
308
+}
309
+
310
+float64 HELPER(frint64_d)(float64 f, void *fpst)
311
+{
312
+ return frint_d(f, fpst, 64);
313
+}
314
--
30
--
315
2.20.1
31
2.20.1
316
32
317
33
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Leif Lindholm <leif@nuviainc.com>
2
2
3
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
3
When FEAT_MTE is implemented, the AArch64 view of CTR_EL0 adds the
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
TminLine field in bits [37:32].
5
Message-id: 20190301200501.16533-9-richard.henderson@linaro.org
5
Extend the ctr field to be able to hold this context.
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
7
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
8
Reviewed-by: Hao Wu <wuhaotsh@google.com>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
11
Message-id: 20210108185154.8108-4-leif@nuviainc.com
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
13
---
9
target/arm/cpu.h | 5 ++++
14
target/arm/cpu.h | 2 +-
10
target/arm/cpu64.c | 2 +-
15
1 file changed, 1 insertion(+), 1 deletion(-)
11
target/arm/translate-a64.c | 58 ++++++++++++++++++++++++++++++++++++++
12
3 files changed, 64 insertions(+), 1 deletion(-)
13
16
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.h
19
--- a/target/arm/cpu.h
17
+++ b/target/arm/cpu.h
20
+++ b/target/arm/cpu.h
18
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id)
21
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
19
return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
22
uint64_t midr;
20
}
23
uint32_t revidr;
21
24
uint32_t reset_fpsid;
22
+static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id)
25
- uint32_t ctr;
23
+{
26
+ uint64_t ctr;
24
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2;
27
uint32_t reset_sctlr;
25
+}
28
uint64_t pmceid0;
26
+
29
uint64_t pmceid1;
27
static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
28
{
29
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
30
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
31
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/cpu64.c
33
+++ b/target/arm/cpu64.c
34
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
35
t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
36
t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
37
t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
38
- t = FIELD_DP64(t, ID_AA64ISAR0, TS, 1);
39
+ t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
40
cpu->isar.id_aa64isar0 = t;
41
42
t = cpu->isar.id_aa64isar1;
43
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/target/arm/translate-a64.c
46
+++ b/target/arm/translate-a64.c
47
@@ -XXX,XX +XXX,XX @@ static void handle_sync(DisasContext *s, uint32_t insn,
48
}
49
}
50
51
+static void gen_xaflag(void)
52
+{
53
+ TCGv_i32 z = tcg_temp_new_i32();
54
+
55
+ tcg_gen_setcondi_i32(TCG_COND_EQ, z, cpu_ZF, 0);
56
+
57
+ /*
58
+ * (!C & !Z) << 31
59
+ * (!(C | Z)) << 31
60
+ * ~((C | Z) << 31)
61
+ * ~-(C | Z)
62
+ * (C | Z) - 1
63
+ */
64
+ tcg_gen_or_i32(cpu_NF, cpu_CF, z);
65
+ tcg_gen_subi_i32(cpu_NF, cpu_NF, 1);
66
+
67
+ /* !(Z & C) */
68
+ tcg_gen_and_i32(cpu_ZF, z, cpu_CF);
69
+ tcg_gen_xori_i32(cpu_ZF, cpu_ZF, 1);
70
+
71
+ /* (!C & Z) << 31 -> -(Z & ~C) */
72
+ tcg_gen_andc_i32(cpu_VF, z, cpu_CF);
73
+ tcg_gen_neg_i32(cpu_VF, cpu_VF);
74
+
75
+ /* C | Z */
76
+ tcg_gen_or_i32(cpu_CF, cpu_CF, z);
77
+
78
+ tcg_temp_free_i32(z);
79
+}
80
+
81
+static void gen_axflag(void)
82
+{
83
+ tcg_gen_sari_i32(cpu_VF, cpu_VF, 31); /* V ? -1 : 0 */
84
+ tcg_gen_andc_i32(cpu_CF, cpu_CF, cpu_VF); /* C & !V */
85
+
86
+ /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */
87
+ tcg_gen_andc_i32(cpu_ZF, cpu_ZF, cpu_VF);
88
+
89
+ tcg_gen_movi_i32(cpu_NF, 0);
90
+ tcg_gen_movi_i32(cpu_VF, 0);
91
+}
92
+
93
/* MSR (immediate) - move immediate to processor state field */
94
static void handle_msr_i(DisasContext *s, uint32_t insn,
95
unsigned int op1, unsigned int op2, unsigned int crm)
96
@@ -XXX,XX +XXX,XX @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
97
s->base.is_jmp = DISAS_NEXT;
98
break;
99
100
+ case 0x01: /* XAFlag */
101
+ if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) {
102
+ goto do_unallocated;
103
+ }
104
+ gen_xaflag();
105
+ s->base.is_jmp = DISAS_NEXT;
106
+ break;
107
+
108
+ case 0x02: /* AXFlag */
109
+ if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) {
110
+ goto do_unallocated;
111
+ }
112
+ gen_axflag();
113
+ s->base.is_jmp = DISAS_NEXT;
114
+ break;
115
+
116
case 0x05: /* SPSel */
117
if (s->current_el == 0) {
118
goto do_unallocated;
119
--
30
--
120
2.20.1
31
2.20.1
121
32
122
33
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Leif Lindholm <leif@nuviainc.com>
2
2
3
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
3
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
5
Message-id: 20190301200501.16533-8-richard.henderson@linaro.org
5
Message-id: 20210108185154.8108-5-leif@nuviainc.com
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
[PMM: fixed up block comment style]
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
7
---
10
target/arm/cpu.h | 5 ++
8
target/arm/cpu.h | 31 +++++++++++++++++++++++++++++++
11
linux-user/elfload.c | 1 +
9
1 file changed, 31 insertions(+)
12
target/arm/cpu64.c | 1 +
13
target/arm/translate-a64.c | 99 +++++++++++++++++++++++++++++++++++++-
14
4 files changed, 105 insertions(+), 1 deletion(-)
15
10
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
11
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
12
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
13
--- a/target/arm/cpu.h
19
+++ b/target/arm/cpu.h
14
+++ b/target/arm/cpu.h
20
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id)
15
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
21
return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
16
/*
22
}
17
* System register ID fields.
23
18
*/
24
+static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id)
19
+FIELD(CLIDR_EL1, CTYPE1, 0, 3)
25
+{
20
+FIELD(CLIDR_EL1, CTYPE2, 3, 3)
26
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
21
+FIELD(CLIDR_EL1, CTYPE3, 6, 3)
27
+}
22
+FIELD(CLIDR_EL1, CTYPE4, 9, 3)
23
+FIELD(CLIDR_EL1, CTYPE5, 12, 3)
24
+FIELD(CLIDR_EL1, CTYPE6, 15, 3)
25
+FIELD(CLIDR_EL1, CTYPE7, 18, 3)
26
+FIELD(CLIDR_EL1, LOUIS, 21, 3)
27
+FIELD(CLIDR_EL1, LOC, 24, 3)
28
+FIELD(CLIDR_EL1, LOUU, 27, 3)
29
+FIELD(CLIDR_EL1, ICB, 30, 3)
28
+
30
+
29
static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
31
+/* When FEAT_CCIDX is implemented */
30
{
32
+FIELD(CCSIDR_EL1, CCIDX_LINESIZE, 0, 3)
31
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
33
+FIELD(CCSIDR_EL1, CCIDX_ASSOCIATIVITY, 3, 21)
32
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
34
+FIELD(CCSIDR_EL1, CCIDX_NUMSETS, 32, 24)
33
index XXXXXXX..XXXXXXX 100644
34
--- a/linux-user/elfload.c
35
+++ b/linux-user/elfload.c
36
@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void)
37
GET_FEATURE_ID(aa64_fhm, ARM_HWCAP_A64_ASIMDFHM);
38
GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT);
39
GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB);
40
+ GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM);
41
42
#undef GET_FEATURE_ID
43
44
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/cpu64.c
47
+++ b/target/arm/cpu64.c
48
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
49
t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
50
t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
51
t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
52
+ t = FIELD_DP64(t, ID_AA64ISAR0, TS, 1);
53
cpu->isar.id_aa64isar0 = t;
54
55
t = cpu->isar.id_aa64isar1;
56
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
57
index XXXXXXX..XXXXXXX 100644
58
--- a/target/arm/translate-a64.c
59
+++ b/target/arm/translate-a64.c
60
@@ -XXX,XX +XXX,XX @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
61
s->base.is_jmp = DISAS_TOO_MANY;
62
63
switch (op) {
64
+ case 0x00: /* CFINV */
65
+ if (crm != 0 || !dc_isar_feature(aa64_condm_4, s)) {
66
+ goto do_unallocated;
67
+ }
68
+ tcg_gen_xori_i32(cpu_CF, cpu_CF, 1);
69
+ s->base.is_jmp = DISAS_NEXT;
70
+ break;
71
+
35
+
72
case 0x05: /* SPSel */
36
+/* When FEAT_CCIDX is not implemented */
73
if (s->current_el == 0) {
37
+FIELD(CCSIDR_EL1, LINESIZE, 0, 3)
74
goto do_unallocated;
38
+FIELD(CCSIDR_EL1, ASSOCIATIVITY, 3, 10)
75
@@ -XXX,XX +XXX,XX @@ static void gen_get_nzcv(TCGv_i64 tcg_rt)
39
+FIELD(CCSIDR_EL1, NUMSETS, 13, 15)
76
}
77
78
static void gen_set_nzcv(TCGv_i64 tcg_rt)
79
-
80
{
81
TCGv_i32 nzcv = tcg_temp_new_i32();
82
83
@@ -XXX,XX +XXX,XX @@ static void disas_adc_sbc(DisasContext *s, uint32_t insn)
84
}
85
}
86
87
+/*
88
+ * Rotate right into flags
89
+ * 31 30 29 21 15 10 5 4 0
90
+ * +--+--+--+-----------------+--------+-----------+------+--+------+
91
+ * |sf|op| S| 1 1 0 1 0 0 0 0 | imm6 | 0 0 0 0 1 | Rn |o2| mask |
92
+ * +--+--+--+-----------------+--------+-----------+------+--+------+
93
+ */
94
+static void disas_rotate_right_into_flags(DisasContext *s, uint32_t insn)
95
+{
96
+ int mask = extract32(insn, 0, 4);
97
+ int o2 = extract32(insn, 4, 1);
98
+ int rn = extract32(insn, 5, 5);
99
+ int imm6 = extract32(insn, 15, 6);
100
+ int sf_op_s = extract32(insn, 29, 3);
101
+ TCGv_i64 tcg_rn;
102
+ TCGv_i32 nzcv;
103
+
40
+
104
+ if (sf_op_s != 5 || o2 != 0 || !dc_isar_feature(aa64_condm_4, s)) {
41
+FIELD(CTR_EL0, IMINLINE, 0, 4)
105
+ unallocated_encoding(s);
42
+FIELD(CTR_EL0, L1IP, 14, 2)
106
+ return;
43
+FIELD(CTR_EL0, DMINLINE, 16, 4)
107
+ }
44
+FIELD(CTR_EL0, ERG, 20, 4)
45
+FIELD(CTR_EL0, CWG, 24, 4)
46
+FIELD(CTR_EL0, IDC, 28, 1)
47
+FIELD(CTR_EL0, DIC, 29, 1)
48
+FIELD(CTR_EL0, TMINLINE, 32, 6)
108
+
49
+
109
+ tcg_rn = read_cpu_reg(s, rn, 1);
50
FIELD(MIDR_EL1, REVISION, 0, 4)
110
+ tcg_gen_rotri_i64(tcg_rn, tcg_rn, imm6);
51
FIELD(MIDR_EL1, PARTNUM, 4, 12)
111
+
52
FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
112
+ nzcv = tcg_temp_new_i32();
113
+ tcg_gen_extrl_i64_i32(nzcv, tcg_rn);
114
+
115
+ if (mask & 8) { /* N */
116
+ tcg_gen_shli_i32(cpu_NF, nzcv, 31 - 3);
117
+ }
118
+ if (mask & 4) { /* Z */
119
+ tcg_gen_not_i32(cpu_ZF, nzcv);
120
+ tcg_gen_andi_i32(cpu_ZF, cpu_ZF, 4);
121
+ }
122
+ if (mask & 2) { /* C */
123
+ tcg_gen_extract_i32(cpu_CF, nzcv, 1, 1);
124
+ }
125
+ if (mask & 1) { /* V */
126
+ tcg_gen_shli_i32(cpu_VF, nzcv, 31 - 0);
127
+ }
128
+
129
+ tcg_temp_free_i32(nzcv);
130
+}
131
+
132
+/*
133
+ * Evaluate into flags
134
+ * 31 30 29 21 15 14 10 5 4 0
135
+ * +--+--+--+-----------------+---------+----+---------+------+--+------+
136
+ * |sf|op| S| 1 1 0 1 0 0 0 0 | opcode2 | sz | 0 0 1 0 | Rn |o3| mask |
137
+ * +--+--+--+-----------------+---------+----+---------+------+--+------+
138
+ */
139
+static void disas_evaluate_into_flags(DisasContext *s, uint32_t insn)
140
+{
141
+ int o3_mask = extract32(insn, 0, 5);
142
+ int rn = extract32(insn, 5, 5);
143
+ int o2 = extract32(insn, 15, 6);
144
+ int sz = extract32(insn, 14, 1);
145
+ int sf_op_s = extract32(insn, 29, 3);
146
+ TCGv_i32 tmp;
147
+ int shift;
148
+
149
+ if (sf_op_s != 1 || o2 != 0 || o3_mask != 0xd ||
150
+ !dc_isar_feature(aa64_condm_4, s)) {
151
+ unallocated_encoding(s);
152
+ return;
153
+ }
154
+ shift = sz ? 16 : 24; /* SETF16 or SETF8 */
155
+
156
+ tmp = tcg_temp_new_i32();
157
+ tcg_gen_extrl_i64_i32(tmp, cpu_reg(s, rn));
158
+ tcg_gen_shli_i32(cpu_NF, tmp, shift);
159
+ tcg_gen_shli_i32(cpu_VF, tmp, shift - 1);
160
+ tcg_gen_mov_i32(cpu_ZF, cpu_NF);
161
+ tcg_gen_xor_i32(cpu_VF, cpu_VF, cpu_NF);
162
+ tcg_temp_free_i32(tmp);
163
+}
164
+
165
/* Conditional compare (immediate / register)
166
* 31 30 29 28 27 26 25 24 23 22 21 20 16 15 12 11 10 9 5 4 3 0
167
* +--+--+--+------------------------+--------+------+----+--+------+--+-----+
168
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
169
disas_adc_sbc(s, insn);
170
break;
171
172
+ case 0x01: /* Rotate right into flags */
173
+ case 0x21:
174
+ disas_rotate_right_into_flags(s, insn);
175
+ break;
176
+
177
+ case 0x02: /* Evaluate into flags */
178
+ case 0x12:
179
+ case 0x22:
180
+ case 0x32:
181
+ disas_evaluate_into_flags(s, insn);
182
+ break;
183
+
184
default:
185
goto do_unallocated;
186
}
187
--
53
--
188
2.20.1
54
2.20.1
189
55
190
56
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Leif Lindholm <leif@nuviainc.com>
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
Add entries present in ARM DDI 0487F.c (August 2020).
4
Message-id: 20190301200501.16533-3-richard.henderson@linaro.org
4
5
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
8
Message-id: 20210108185154.8108-6-leif@nuviainc.com
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
10
---
8
target/arm/cpu.h | 10 ++++++++++
11
target/arm/cpu.h | 15 +++++++++++++++
9
linux-user/elfload.c | 1 +
12
1 file changed, 15 insertions(+)
10
target/arm/cpu.c | 1 +
11
target/arm/cpu64.c | 2 ++
12
target/arm/translate-a64.c | 14 ++++++++++++++
13
target/arm/translate.c | 22 ++++++++++++++++++++++
14
6 files changed, 50 insertions(+)
15
13
16
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.h
16
--- a/target/arm/cpu.h
19
+++ b/target/arm/cpu.h
17
+++ b/target/arm/cpu.h
20
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)
18
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64ISAR1, GPI, 28, 4)
21
return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
19
FIELD(ID_AA64ISAR1, FRINTTS, 32, 4)
22
}
20
FIELD(ID_AA64ISAR1, SB, 36, 4)
23
21
FIELD(ID_AA64ISAR1, SPECRES, 40, 4)
24
+static inline bool isar_feature_aa32_sb(const ARMISARegisters *id)
22
+FIELD(ID_AA64ISAR1, BF16, 44, 4)
25
+{
23
+FIELD(ID_AA64ISAR1, DGH, 48, 4)
26
+ return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0;
24
+FIELD(ID_AA64ISAR1, I8MM, 52, 4)
27
+}
25
28
+
26
FIELD(ID_AA64PFR0, EL0, 0, 4)
29
static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
27
FIELD(ID_AA64PFR0, EL1, 4, 4)
30
{
28
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, ADVSIMD, 20, 4)
31
/*
29
FIELD(ID_AA64PFR0, GIC, 24, 4)
32
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)
30
FIELD(ID_AA64PFR0, RAS, 28, 4)
33
FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0;
31
FIELD(ID_AA64PFR0, SVE, 32, 4)
34
}
32
+FIELD(ID_AA64PFR0, SEL2, 36, 4)
35
33
+FIELD(ID_AA64PFR0, MPAM, 40, 4)
36
+static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)
34
+FIELD(ID_AA64PFR0, AMU, 44, 4)
37
+{
35
+FIELD(ID_AA64PFR0, DIT, 48, 4)
38
+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;
36
+FIELD(ID_AA64PFR0, CSV2, 56, 4)
39
+}
37
+FIELD(ID_AA64PFR0, CSV3, 60, 4)
40
+
38
41
static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
39
FIELD(ID_AA64PFR1, BT, 0, 4)
42
{
40
FIELD(ID_AA64PFR1, SSBS, 4, 4)
43
/* We always set the AdvSIMD and FP fields identically wrt FP16. */
41
FIELD(ID_AA64PFR1, MTE, 8, 4)
44
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
42
FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4)
45
index XXXXXXX..XXXXXXX 100644
43
+FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4)
46
--- a/linux-user/elfload.c
44
47
+++ b/linux-user/elfload.c
45
FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
48
@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void)
46
FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
49
GET_FEATURE_ID(aa64_pauth, ARM_HWCAP_A64_PACA | ARM_HWCAP_A64_PACG);
47
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
50
GET_FEATURE_ID(aa64_fhm, ARM_HWCAP_A64_ASIMDFHM);
48
FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
51
GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT);
49
FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
52
+ GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB);
50
FIELD(ID_AA64MMFR0, EXS, 44, 4)
53
51
+FIELD(ID_AA64MMFR0, FGT, 56, 4)
54
#undef GET_FEATURE_ID
52
+FIELD(ID_AA64MMFR0, ECV, 60, 4)
55
53
56
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
54
FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
57
index XXXXXXX..XXXXXXX 100644
55
FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
58
--- a/target/arm/cpu.c
56
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR1, LO, 16, 4)
59
+++ b/target/arm/cpu.c
57
FIELD(ID_AA64MMFR1, PAN, 20, 4)
60
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
58
FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
61
t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
59
FIELD(ID_AA64MMFR1, XNX, 28, 4)
62
t = FIELD_DP32(t, ID_ISAR6, DP, 1);
60
+FIELD(ID_AA64MMFR1, TWED, 32, 4)
63
t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
61
+FIELD(ID_AA64MMFR1, ETS, 36, 4)
64
+ t = FIELD_DP32(t, ID_ISAR6, SB, 1);
62
65
cpu->isar.id_isar6 = t;
63
FIELD(ID_AA64MMFR2, CNP, 0, 4)
66
64
FIELD(ID_AA64MMFR2, UAO, 4, 4)
67
t = cpu->id_mmfr4;
65
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4)
68
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
66
FIELD(ID_AA64DFR0, PMSVER, 32, 4)
69
index XXXXXXX..XXXXXXX 100644
67
FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4)
70
--- a/target/arm/cpu64.c
68
FIELD(ID_AA64DFR0, TRACEFILT, 40, 4)
71
+++ b/target/arm/cpu64.c
69
+FIELD(ID_AA64DFR0, MTPMU, 48, 4)
72
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
70
73
t = FIELD_DP64(t, ID_AA64ISAR1, API, 0);
71
FIELD(ID_DFR0, COPDBG, 0, 4)
74
t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1);
72
FIELD(ID_DFR0, COPSDBG, 4, 4)
75
t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0);
76
+ t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);
77
cpu->isar.id_aa64isar1 = t;
78
79
t = cpu->isar.id_aa64pfr0;
80
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
81
u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
82
u = FIELD_DP32(u, ID_ISAR6, DP, 1);
83
u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
84
+ u = FIELD_DP32(u, ID_ISAR6, SB, 1);
85
cpu->isar.id_isar6 = u;
86
87
/*
88
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
89
index XXXXXXX..XXXXXXX 100644
90
--- a/target/arm/translate-a64.c
91
+++ b/target/arm/translate-a64.c
92
@@ -XXX,XX +XXX,XX @@ static void handle_sync(DisasContext *s, uint32_t insn,
93
reset_btype(s);
94
gen_goto_tb(s, 0, s->pc);
95
return;
96
+
97
+ case 7: /* SB */
98
+ if (crm != 0 || !dc_isar_feature(aa64_sb, s)) {
99
+ goto do_unallocated;
100
+ }
101
+ /*
102
+ * TODO: There is no speculation barrier opcode for TCG;
103
+ * MB and end the TB instead.
104
+ */
105
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
106
+ gen_goto_tb(s, 0, s->pc);
107
+ return;
108
+
109
default:
110
+ do_unallocated:
111
unallocated_encoding(s);
112
return;
113
}
114
diff --git a/target/arm/translate.c b/target/arm/translate.c
115
index XXXXXXX..XXXXXXX 100644
116
--- a/target/arm/translate.c
117
+++ b/target/arm/translate.c
118
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
119
*/
120
gen_goto_tb(s, 0, s->pc & ~1);
121
return;
122
+ case 7: /* sb */
123
+ if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) {
124
+ goto illegal_op;
125
+ }
126
+ /*
127
+ * TODO: There is no speculation barrier opcode
128
+ * for TCG; MB and end the TB instead.
129
+ */
130
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
131
+ gen_goto_tb(s, 0, s->pc & ~1);
132
+ return;
133
default:
134
goto illegal_op;
135
}
136
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
137
*/
138
gen_goto_tb(s, 0, s->pc & ~1);
139
break;
140
+ case 7: /* sb */
141
+ if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) {
142
+ goto illegal_op;
143
+ }
144
+ /*
145
+ * TODO: There is no speculation barrier opcode
146
+ * for TCG; MB and end the TB instead.
147
+ */
148
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
149
+ gen_goto_tb(s, 0, s->pc & ~1);
150
+ break;
151
default:
152
goto illegal_op;
153
}
154
--
73
--
155
2.20.1
74
2.20.1
156
75
157
76
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Leif Lindholm <leif@nuviainc.com>
2
2
3
Minimize the number of places that will need updating when
3
Add entries present in ARM DDI 0487F.c (August 2020).
4
the virtual host extensions are added.
5
4
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Signed-off-by: Leif Lindholm <leif@nuviainc.com>
7
Message-id: 20190301200501.16533-2-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
8
Message-id: 20210108185154.8108-7-leif@nuviainc.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
target/arm/cpu.h | 26 ++++++++++++++++----------
11
target/arm/cpu.h | 28 ++++++++++++++++++++++++++++
12
target/arm/helper.c | 8 ++------
12
1 file changed, 28 insertions(+)
13
2 files changed, 18 insertions(+), 16 deletions(-)
14
13
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu.h
16
--- a/target/arm/cpu.h
18
+++ b/target/arm/cpu.h
17
+++ b/target/arm/cpu.h
19
@@ -XXX,XX +XXX,XX @@ static inline bool arm_sctlr_b(CPUARMState *env)
18
@@ -XXX,XX +XXX,XX @@ FIELD(ID_ISAR6, DP, 4, 4)
20
(env->cp15.sctlr_el[1] & SCTLR_B) != 0;
19
FIELD(ID_ISAR6, FHM, 8, 4)
21
}
20
FIELD(ID_ISAR6, SB, 12, 4)
22
21
FIELD(ID_ISAR6, SPECRES, 16, 4)
23
+static inline uint64_t arm_sctlr(CPUARMState *env, int el)
22
+FIELD(ID_ISAR6, BF16, 20, 4)
24
+{
23
+FIELD(ID_ISAR6, I8MM, 24, 4)
25
+ if (el == 0) {
24
26
+ /* FIXME: ARMv8.1-VHE S2 translation regime. */
25
FIELD(ID_MMFR0, VMSA, 0, 4)
27
+ return env->cp15.sctlr_el[1];
26
FIELD(ID_MMFR0, PMSA, 4, 4)
28
+ } else {
27
@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR0, AUXREG, 20, 4)
29
+ return env->cp15.sctlr_el[el];
28
FIELD(ID_MMFR0, FCSE, 24, 4)
30
+ }
29
FIELD(ID_MMFR0, INNERSHR, 28, 4)
31
+}
30
31
+FIELD(ID_MMFR1, L1HVDVA, 0, 4)
32
+FIELD(ID_MMFR1, L1UNIVA, 4, 4)
33
+FIELD(ID_MMFR1, L1HVDSW, 8, 4)
34
+FIELD(ID_MMFR1, L1UNISW, 12, 4)
35
+FIELD(ID_MMFR1, L1HVD, 16, 4)
36
+FIELD(ID_MMFR1, L1UNI, 20, 4)
37
+FIELD(ID_MMFR1, L1TSTCLN, 24, 4)
38
+FIELD(ID_MMFR1, BPRED, 28, 4)
32
+
39
+
40
+FIELD(ID_MMFR2, L1HVDFG, 0, 4)
41
+FIELD(ID_MMFR2, L1HVDBG, 4, 4)
42
+FIELD(ID_MMFR2, L1HVDRNG, 8, 4)
43
+FIELD(ID_MMFR2, HVDTLB, 12, 4)
44
+FIELD(ID_MMFR2, UNITLB, 16, 4)
45
+FIELD(ID_MMFR2, MEMBARR, 20, 4)
46
+FIELD(ID_MMFR2, WFISTALL, 24, 4)
47
+FIELD(ID_MMFR2, HWACCFLG, 28, 4)
33
+
48
+
34
/* Return true if the processor is in big-endian mode. */
49
FIELD(ID_MMFR3, CMAINTVA, 0, 4)
35
static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
50
FIELD(ID_MMFR3, CMAINTSW, 4, 4)
36
{
51
FIELD(ID_MMFR3, BPMAINT, 8, 4)
37
- int cur_el;
52
@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR4, LSM, 20, 4)
38
-
53
FIELD(ID_MMFR4, CCIDX, 24, 4)
39
/* In 32bit endianness is determined by looking at CPSR's E bit */
54
FIELD(ID_MMFR4, EVT, 28, 4)
40
if (!is_a64(env)) {
55
41
return
56
+FIELD(ID_MMFR5, ETS, 0, 4)
42
@@ -XXX,XX +XXX,XX @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
43
arm_sctlr_b(env) ||
44
#endif
45
((env->uncached_cpsr & CPSR_E) ? 1 : 0);
46
+ } else {
47
+ int cur_el = arm_current_el(env);
48
+ uint64_t sctlr = arm_sctlr(env, cur_el);
49
+
57
+
50
+ return (sctlr & (cur_el ? SCTLR_EE : SCTLR_E0E)) != 0;
58
FIELD(ID_PFR0, STATE0, 0, 4)
51
}
59
FIELD(ID_PFR0, STATE1, 4, 4)
52
-
60
FIELD(ID_PFR0, STATE2, 8, 4)
53
- cur_el = arm_current_el(env);
61
@@ -XXX,XX +XXX,XX @@ FIELD(ID_PFR1, SEC_FRAC, 20, 4)
54
-
62
FIELD(ID_PFR1, VIRT_FRAC, 24, 4)
55
- if (cur_el == 0) {
63
FIELD(ID_PFR1, GIC, 28, 4)
56
- return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0;
64
57
- }
65
+FIELD(ID_PFR2, CSV3, 0, 4)
58
-
66
+FIELD(ID_PFR2, SSBS, 4, 4)
59
- return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0;
67
+FIELD(ID_PFR2, RAS_FRAC, 8, 4)
60
}
61
62
#include "exec/cpu-all.h"
63
diff --git a/target/arm/helper.c b/target/arm/helper.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/target/arm/helper.c
66
+++ b/target/arm/helper.c
67
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
68
flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len);
69
}
70
71
- if (current_el == 0) {
72
- /* FIXME: ARMv8.1-VHE S2 translation regime. */
73
- sctlr = env->cp15.sctlr_el[1];
74
- } else {
75
- sctlr = env->cp15.sctlr_el[current_el];
76
- }
77
+ sctlr = arm_sctlr(env, current_el);
78
+
68
+
79
if (cpu_isar_feature(aa64_pauth, cpu)) {
69
FIELD(ID_AA64ISAR0, AES, 4, 4)
80
/*
70
FIELD(ID_AA64ISAR0, SHA1, 8, 4)
81
* In order to save space in flags, we record only whether
71
FIELD(ID_AA64ISAR0, SHA2, 12, 4)
72
@@ -XXX,XX +XXX,XX @@ FIELD(ID_DFR0, MPROFDBG, 20, 4)
73
FIELD(ID_DFR0, PERFMON, 24, 4)
74
FIELD(ID_DFR0, TRACEFILT, 28, 4)
75
76
+FIELD(ID_DFR1, MTPMU, 0, 4)
77
+
78
FIELD(DBGDIDR, SE_IMP, 12, 1)
79
FIELD(DBGDIDR, NSUHD_IMP, 14, 1)
80
FIELD(DBGDIDR, VERSION, 16, 4)
82
--
81
--
83
2.20.1
82
2.20.1
84
83
85
84
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Roman Bolshakov <r.bolshakov@yadro.com>
2
2
3
This will allow sharing code that adjusts rmode beyond
3
QEMU documentation can't be opened if QEMU is run from build tree
4
the existing users.
4
because executables are placed in the top of build tree after conversion
5
to meson.
5
6
6
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
7
Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reported-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20190301200501.16533-10-richard.henderson@linaro.org
9
Message-id: 20210108213815.64678-1-r.bolshakov@yadro.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
---
12
target/arm/translate-a64.c | 90 +++++++++++++++++++++-----------------
13
ui/cocoa.m | 2 +-
13
1 file changed, 49 insertions(+), 41 deletions(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
14
15
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
16
diff --git a/ui/cocoa.m b/ui/cocoa.m
16
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
18
--- a/ui/cocoa.m
18
+++ b/target/arm/translate-a64.c
19
+++ b/ui/cocoa.m
19
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
20
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
20
/* Floating-point data-processing (1 source) - single precision */
21
- (void) openDocumentation: (NSString *) filename
21
static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
22
{
22
{
23
+ void (*gen_fpst)(TCGv_i32, TCGv_i32, TCGv_ptr);
23
/* Where to look for local files */
24
+ TCGv_i32 tcg_op, tcg_res;
24
- NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"../docs/"};
25
TCGv_ptr fpst;
25
+ NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"};
26
- TCGv_i32 tcg_op;
26
NSString *full_file_path;
27
- TCGv_i32 tcg_res;
27
28
+ int rmode = -1;
28
/* iterate thru the possible paths until the file is found */
29
30
- fpst = get_fpstatus_ptr(false);
31
tcg_op = read_fp_sreg(s, rn);
32
tcg_res = tcg_temp_new_i32();
33
34
switch (opcode) {
35
case 0x0: /* FMOV */
36
tcg_gen_mov_i32(tcg_res, tcg_op);
37
- break;
38
+ goto done;
39
case 0x1: /* FABS */
40
gen_helper_vfp_abss(tcg_res, tcg_op);
41
- break;
42
+ goto done;
43
case 0x2: /* FNEG */
44
gen_helper_vfp_negs(tcg_res, tcg_op);
45
- break;
46
+ goto done;
47
case 0x3: /* FSQRT */
48
gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env);
49
- break;
50
+ goto done;
51
case 0x8: /* FRINTN */
52
case 0x9: /* FRINTP */
53
case 0xa: /* FRINTM */
54
case 0xb: /* FRINTZ */
55
case 0xc: /* FRINTA */
56
- {
57
- TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
58
-
59
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
60
- gen_helper_rints(tcg_res, tcg_op, fpst);
61
-
62
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
63
- tcg_temp_free_i32(tcg_rmode);
64
+ rmode = arm_rmode_to_sf(opcode & 7);
65
+ gen_fpst = gen_helper_rints;
66
break;
67
- }
68
case 0xe: /* FRINTX */
69
- gen_helper_rints_exact(tcg_res, tcg_op, fpst);
70
+ gen_fpst = gen_helper_rints_exact;
71
break;
72
case 0xf: /* FRINTI */
73
- gen_helper_rints(tcg_res, tcg_op, fpst);
74
+ gen_fpst = gen_helper_rints;
75
break;
76
default:
77
- abort();
78
+ g_assert_not_reached();
79
}
80
81
- write_fp_sreg(s, rd, tcg_res);
82
-
83
+ fpst = get_fpstatus_ptr(false);
84
+ if (rmode >= 0) {
85
+ TCGv_i32 tcg_rmode = tcg_const_i32(rmode);
86
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
87
+ gen_fpst(tcg_res, tcg_op, fpst);
88
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
89
+ tcg_temp_free_i32(tcg_rmode);
90
+ } else {
91
+ gen_fpst(tcg_res, tcg_op, fpst);
92
+ }
93
tcg_temp_free_ptr(fpst);
94
+
95
+ done:
96
+ write_fp_sreg(s, rd, tcg_res);
97
tcg_temp_free_i32(tcg_op);
98
tcg_temp_free_i32(tcg_res);
99
}
100
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
101
/* Floating-point data-processing (1 source) - double precision */
102
static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
103
{
104
+ void (*gen_fpst)(TCGv_i64, TCGv_i64, TCGv_ptr);
105
+ TCGv_i64 tcg_op, tcg_res;
106
TCGv_ptr fpst;
107
- TCGv_i64 tcg_op;
108
- TCGv_i64 tcg_res;
109
+ int rmode = -1;
110
111
switch (opcode) {
112
case 0x0: /* FMOV */
113
@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
114
return;
115
}
116
117
- fpst = get_fpstatus_ptr(false);
118
tcg_op = read_fp_dreg(s, rn);
119
tcg_res = tcg_temp_new_i64();
120
121
switch (opcode) {
122
case 0x1: /* FABS */
123
gen_helper_vfp_absd(tcg_res, tcg_op);
124
- break;
125
+ goto done;
126
case 0x2: /* FNEG */
127
gen_helper_vfp_negd(tcg_res, tcg_op);
128
- break;
129
+ goto done;
130
case 0x3: /* FSQRT */
131
gen_helper_vfp_sqrtd(tcg_res, tcg_op, cpu_env);
132
- break;
133
+ goto done;
134
case 0x8: /* FRINTN */
135
case 0x9: /* FRINTP */
136
case 0xa: /* FRINTM */
137
case 0xb: /* FRINTZ */
138
case 0xc: /* FRINTA */
139
- {
140
- TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));
141
-
142
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
143
- gen_helper_rintd(tcg_res, tcg_op, fpst);
144
-
145
- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
146
- tcg_temp_free_i32(tcg_rmode);
147
+ rmode = arm_rmode_to_sf(opcode & 7);
148
+ gen_fpst = gen_helper_rintd;
149
break;
150
- }
151
case 0xe: /* FRINTX */
152
- gen_helper_rintd_exact(tcg_res, tcg_op, fpst);
153
+ gen_fpst = gen_helper_rintd_exact;
154
break;
155
case 0xf: /* FRINTI */
156
- gen_helper_rintd(tcg_res, tcg_op, fpst);
157
+ gen_fpst = gen_helper_rintd;
158
break;
159
default:
160
- abort();
161
+ g_assert_not_reached();
162
}
163
164
- write_fp_dreg(s, rd, tcg_res);
165
-
166
+ fpst = get_fpstatus_ptr(false);
167
+ if (rmode >= 0) {
168
+ TCGv_i32 tcg_rmode = tcg_const_i32(rmode);
169
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
170
+ gen_fpst(tcg_res, tcg_op, fpst);
171
+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);
172
+ tcg_temp_free_i32(tcg_rmode);
173
+ } else {
174
+ gen_fpst(tcg_res, tcg_op, fpst);
175
+ }
176
tcg_temp_free_ptr(fpst);
177
+
178
+ done:
179
+ write_fp_dreg(s, rd, tcg_res);
180
tcg_temp_free_i64(tcg_op);
181
tcg_temp_free_i64(tcg_res);
182
}
183
--
29
--
184
2.20.1
30
2.20.1
185
31
186
32
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
In commit 1982e1602d15 we added a new qemu-storage-daemon(1) manpage.
2
At the moment new manpages have to be listed both in the conf.py for
3
Sphinx and also in docs/meson.build for Meson. We forgot the second
4
of those -- correct the omission.
2
5
3
This patch implements the machine class kvm_type() callback.
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
It returns the number of bits requested to implement the whole GPA
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
5
range including the RAM and IO regions located beyond.
8
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
6
The returned value is passed though the KVM_CREATE_VM ioctl and
9
Message-id: 20210108161416.21129-2-peter.maydell@linaro.org
7
this allows KVM to set the stage2 tables dynamically.
10
---
11
docs/meson.build | 1 +
12
1 file changed, 1 insertion(+)
8
13
9
To compute the highest GPA used in the memory map, kvm_type()
14
diff --git a/docs/meson.build b/docs/meson.build
10
must freeze the memory map by calling virt_set_memmap().
11
12
Signed-off-by: Eric Auger <eric.auger@redhat.com>
13
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
14
Message-id: 20190304101339.25970-9-eric.auger@redhat.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/arm/virt.c | 39 ++++++++++++++++++++++++++++++++++++++-
18
1 file changed, 38 insertions(+), 1 deletion(-)
19
20
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
21
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/virt.c
16
--- a/docs/meson.build
23
+++ b/hw/arm/virt.c
17
+++ b/docs/meson.build
24
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
18
@@ -XXX,XX +XXX,XX @@ if build_docs
25
bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0);
19
'qemu-img.1': (have_tools ? 'man1' : ''),
26
bool aarch64 = true;
20
'qemu-nbd.8': (have_tools ? 'man8' : ''),
27
21
'qemu-pr-helper.8': (have_tools ? 'man8' : ''),
28
- virt_set_memmap(vms);
22
+ 'qemu-storage-daemon.1': (have_tools ? 'man1' : ''),
29
+ /*
23
'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''),
30
+ * In accelerated mode, the memory map is computed earlier in kvm_type()
24
'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''),
31
+ * to create a VM with the right number of IPA bits.
25
'virtiofsd.1': (have_virtiofsd ? 'man1' : ''),
32
+ */
33
+ if (!vms->memmap) {
34
+ virt_set_memmap(vms);
35
+ }
36
37
/* We can probe only here because during property set
38
* KVM is not available yet
39
@@ -XXX,XX +XXX,XX @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,
40
return NULL;
41
}
42
43
+/*
44
+ * for arm64 kvm_type [7-0] encodes the requested number of bits
45
+ * in the IPA address space
46
+ */
47
+static int virt_kvm_type(MachineState *ms, const char *type_str)
48
+{
49
+ VirtMachineState *vms = VIRT_MACHINE(ms);
50
+ int max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms);
51
+ int requested_pa_size;
52
+
53
+ /* we freeze the memory map to compute the highest gpa */
54
+ virt_set_memmap(vms);
55
+
56
+ requested_pa_size = 64 - clz64(vms->highest_gpa);
57
+
58
+ if (requested_pa_size > max_vm_pa_size) {
59
+ error_report("-m and ,maxmem option values "
60
+ "require an IPA range (%d bits) larger than "
61
+ "the one supported by the host (%d bits)",
62
+ requested_pa_size, max_vm_pa_size);
63
+ exit(1);
64
+ }
65
+ /*
66
+ * By default we return 0 which corresponds to an implicit legacy
67
+ * 40b IPA setting. Otherwise we return the actual requested PA
68
+ * logsize
69
+ */
70
+ return requested_pa_size > 40 ? requested_pa_size : 0;
71
+}
72
+
73
static void virt_machine_class_init(ObjectClass *oc, void *data)
74
{
75
MachineClass *mc = MACHINE_CLASS(oc);
76
@@ -XXX,XX +XXX,XX @@ static void virt_machine_class_init(ObjectClass *oc, void *data)
77
mc->cpu_index_to_instance_props = virt_cpu_index_to_props;
78
mc->default_cpu_type = ARM_CPU_TYPE_NAME("cortex-a15");
79
mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
80
+ mc->kvm_type = virt_kvm_type;
81
assert(!mc->get_hotplug_handler);
82
mc->get_hotplug_handler = virt_machine_get_hotplug_handler;
83
hc->plug = virt_machine_device_plug_cb;
84
--
26
--
85
2.20.1
27
2.20.1
86
28
87
29
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
When we first converted our documentation to Sphinx, we split it into
2
2
multiple manuals (system, interop, tools, etc), which are all built
3
The machine RAM attributes will need to be analyzed during the
3
separately. The primary driver for this was wanting to be able to
4
configure_accelerator() process. especially kvm_type() arm64
4
avoid shipping the 'devel' manual to end-users. However, this is
5
machine callback will use them to know how many IPA/GPA bits are
5
working against the grain of the way Sphinx wants to be used and
6
needed to model the whole RAM range. So let's assign those machine
6
causes some annoyances:
7
state fields before calling configure_accelerator.
7
* Cross-references between documents become much harder or
8
8
possibly impossible
9
Signed-off-by: Eric Auger <eric.auger@redhat.com>
9
* There is no single index to the whole documentation
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
* Within one manual there's no links or table-of-contents info
11
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
11
that lets you easily navigate to the others
12
Message-id: 20190304101339.25970-7-eric.auger@redhat.com
12
* The devel manual doesn't get published on the QEMU website
13
(it would be nice to able to refer to it there)
14
15
Merely hiding our developer documentation from end users seems like
16
it's not enough benefit for these costs. Combine all the
17
documentation into a single manual (the same way that the readthedocs
18
site builds it) and install the whole thing. The previous manual
19
divisions remain as the new top level sections in the manual.
20
21
* The per-manual conf.py files are no longer needed
22
* The man_pages[] specifications previously in each per-manual
23
conf.py move to the top level conf.py
24
* docs/meson.build logic is simplified as we now only need to run
25
Sphinx once for the HTML and then once for the manpages5B
26
* The old index.html.in that produced the top-level page with
27
links to each manual is no longer needed
28
29
Unfortunately this means that we now have to build the HTML
30
documentation into docs/manual in the build tree rather than directly
31
into docs/; otherwise it is too awkward to ensure we install only the
32
built manual and not also the dependency info, stamp file, etc. The
33
manual still ends up in the same place in the final installed
34
directory, but anybody who was consulting documentation from within
35
the build tree will have to adjust where they're looking.
36
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
37
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
38
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
39
Message-id: 20210108161416.21129-3-peter.maydell@linaro.org
14
---
40
---
15
vl.c | 6 +++---
41
docs/conf.py | 46 ++++++++++++++++++++++++++++++-
16
1 file changed, 3 insertions(+), 3 deletions(-)
42
docs/devel/conf.py | 15 -----------
17
43
docs/index.html.in | 17 ------------
18
diff --git a/vl.c b/vl.c
44
docs/interop/conf.py | 28 -------------------
45
docs/meson.build | 64 +++++++++++++++++---------------------------
46
docs/specs/conf.py | 16 -----------
47
docs/system/conf.py | 28 -------------------
48
docs/tools/conf.py | 37 -------------------------
49
docs/user/conf.py | 15 -----------
50
9 files changed, 70 insertions(+), 196 deletions(-)
51
delete mode 100644 docs/devel/conf.py
52
delete mode 100644 docs/index.html.in
53
delete mode 100644 docs/interop/conf.py
54
delete mode 100644 docs/specs/conf.py
55
delete mode 100644 docs/system/conf.py
56
delete mode 100644 docs/tools/conf.py
57
delete mode 100644 docs/user/conf.py
58
59
diff --git a/docs/conf.py b/docs/conf.py
19
index XXXXXXX..XXXXXXX 100644
60
index XXXXXXX..XXXXXXX 100644
20
--- a/vl.c
61
--- a/docs/conf.py
21
+++ b/vl.c
62
+++ b/docs/conf.py
22
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv, char **envp)
63
@@ -XXX,XX +XXX,XX @@ latex_documents = [
23
machine_opts = qemu_get_machine_opts();
64
24
qemu_opt_foreach(machine_opts, machine_set_property, current_machine,
65
# -- Options for manual page output ---------------------------------------
25
&error_fatal);
66
# Individual manual/conf.py can override this to create man pages
26
+ current_machine->ram_size = ram_size;
67
-man_pages = []
27
+ current_machine->maxram_size = maxram_size;
68
+man_pages = [
28
+ current_machine->ram_slots = ram_slots;
69
+ ('interop/qemu-ga', 'qemu-ga',
29
70
+ 'QEMU Guest Agent',
30
configure_accelerator(current_machine, argv[0]);
71
+ ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8),
31
72
+ ('interop/qemu-ga-ref', 'qemu-ga-ref',
32
@@ -XXX,XX +XXX,XX @@ int main(int argc, char **argv, char **envp)
73
+ 'QEMU Guest Agent Protocol Reference',
33
replay_checkpoint(CHECKPOINT_INIT);
74
+ [], 7),
34
qdev_machine_init();
75
+ ('interop/qemu-qmp-ref', 'qemu-qmp-ref',
35
76
+ 'QEMU QMP Reference Manual',
36
- current_machine->ram_size = ram_size;
77
+ [], 7),
37
- current_machine->maxram_size = maxram_size;
78
+ ('interop/qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref',
38
- current_machine->ram_slots = ram_slots;
79
+ 'QEMU Storage Daemon QMP Reference Manual',
39
current_machine->boot_order = boot_order;
80
+ [], 7),
40
81
+ ('system/qemu-manpage', 'qemu',
41
/* parse features once if machine provides default cpu_type */
82
+ 'QEMU User Documentation',
83
+ ['Fabrice Bellard'], 1),
84
+ ('system/qemu-block-drivers', 'qemu-block-drivers',
85
+ 'QEMU block drivers reference',
86
+ ['Fabrice Bellard and the QEMU Project developers'], 7),
87
+ ('system/qemu-cpu-models', 'qemu-cpu-models',
88
+ 'QEMU CPU Models',
89
+ ['The QEMU Project developers'], 7),
90
+ ('tools/qemu-img', 'qemu-img',
91
+ 'QEMU disk image utility',
92
+ ['Fabrice Bellard'], 1),
93
+ ('tools/qemu-nbd', 'qemu-nbd',
94
+ 'QEMU Disk Network Block Device Server',
95
+ ['Anthony Liguori <anthony@codemonkey.ws>'], 8),
96
+ ('tools/qemu-pr-helper', 'qemu-pr-helper',
97
+ 'QEMU persistent reservation helper',
98
+ [], 8),
99
+ ('tools/qemu-storage-daemon', 'qemu-storage-daemon',
100
+ 'QEMU storage daemon',
101
+ [], 1),
102
+ ('tools/qemu-trace-stap', 'qemu-trace-stap',
103
+ 'QEMU SystemTap trace tool',
104
+ [], 1),
105
+ ('tools/virtfs-proxy-helper', 'virtfs-proxy-helper',
106
+ 'QEMU 9p virtfs proxy filesystem helper',
107
+ ['M. Mohan Kumar'], 1),
108
+ ('tools/virtiofsd', 'virtiofsd',
109
+ 'QEMU virtio-fs shared file system daemon',
110
+ ['Stefan Hajnoczi <stefanha@redhat.com>',
111
+ 'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1),
112
+]
113
114
# -- Options for Texinfo output -------------------------------------------
115
116
diff --git a/docs/devel/conf.py b/docs/devel/conf.py
117
deleted file mode 100644
118
index XXXXXXX..XXXXXXX
119
--- a/docs/devel/conf.py
120
+++ /dev/null
121
@@ -XXX,XX +XXX,XX @@
122
-# -*- coding: utf-8 -*-
123
-#
124
-# QEMU documentation build configuration file for the 'devel' manual.
125
-#
126
-# This includes the top level conf file and then makes any necessary tweaks.
127
-import sys
128
-import os
129
-
130
-qemu_docdir = os.path.abspath("..")
131
-parent_config = os.path.join(qemu_docdir, "conf.py")
132
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
133
-
134
-# This slightly misuses the 'description', but is the best way to get
135
-# the manual title to appear in the sidebar.
136
-html_theme_options['description'] = u'Developer''s Guide'
137
diff --git a/docs/index.html.in b/docs/index.html.in
138
deleted file mode 100644
139
index XXXXXXX..XXXXXXX
140
--- a/docs/index.html.in
141
+++ /dev/null
142
@@ -XXX,XX +XXX,XX @@
143
-<!DOCTYPE html>
144
-<html lang="en">
145
- <head>
146
- <meta charset="UTF-8">
147
- <title>QEMU @VERSION@ Documentation</title>
148
- </head>
149
- <body>
150
- <h1>QEMU @VERSION@ Documentation</h1>
151
- <ul>
152
- <li><a href="system/index.html">System Emulation User's Guide</a></li>
153
- <li><a href="user/index.html">User Mode Emulation User's Guide</a></li>
154
- <li><a href="tools/index.html">Tools Guide</a></li>
155
- <li><a href="interop/index.html">System Emulation Management and Interoperability Guide</a></li>
156
- <li><a href="specs/index.html">System Emulation Guest Hardware Specifications</a></li>
157
- </ul>
158
- </body>
159
-</html>
160
diff --git a/docs/interop/conf.py b/docs/interop/conf.py
161
deleted file mode 100644
162
index XXXXXXX..XXXXXXX
163
--- a/docs/interop/conf.py
164
+++ /dev/null
165
@@ -XXX,XX +XXX,XX @@
166
-# -*- coding: utf-8 -*-
167
-#
168
-# QEMU documentation build configuration file for the 'interop' manual.
169
-#
170
-# This includes the top level conf file and then makes any necessary tweaks.
171
-import sys
172
-import os
173
-
174
-qemu_docdir = os.path.abspath("..")
175
-parent_config = os.path.join(qemu_docdir, "conf.py")
176
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
177
-
178
-# This slightly misuses the 'description', but is the best way to get
179
-# the manual title to appear in the sidebar.
180
-html_theme_options['description'] = u'System Emulation Management and Interoperability Guide'
181
-
182
-# One entry per manual page. List of tuples
183
-# (source start file, name, description, authors, manual section).
184
-man_pages = [
185
- ('qemu-ga', 'qemu-ga', u'QEMU Guest Agent',
186
- ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8),
187
- ('qemu-ga-ref', 'qemu-ga-ref', 'QEMU Guest Agent Protocol Reference',
188
- [], 7),
189
- ('qemu-qmp-ref', 'qemu-qmp-ref', 'QEMU QMP Reference Manual',
190
- [], 7),
191
- ('qemu-storage-daemon-qmp-ref', 'qemu-storage-daemon-qmp-ref',
192
- 'QEMU Storage Daemon QMP Reference Manual', [], 7),
193
-]
194
diff --git a/docs/meson.build b/docs/meson.build
195
index XXXXXXX..XXXXXXX 100644
196
--- a/docs/meson.build
197
+++ b/docs/meson.build
198
@@ -XXX,XX +XXX,XX @@ if build_docs
199
meson.source_root() / 'docs/sphinx/qmp_lexer.py',
200
qapi_gen_depends ]
201
202
- configure_file(output: 'index.html',
203
- input: files('index.html.in'),
204
- configuration: {'VERSION': meson.project_version()},
205
- install_dir: qemu_docdir)
206
- manuals = [ 'devel', 'interop', 'tools', 'specs', 'system', 'user' ]
207
man_pages = {
208
- 'interop' : {
209
'qemu-ga.8': (have_tools ? 'man8' : ''),
210
'qemu-ga-ref.7': 'man7',
211
'qemu-qmp-ref.7': 'man7',
212
'qemu-storage-daemon-qmp-ref.7': (have_tools ? 'man7' : ''),
213
- },
214
- 'tools': {
215
'qemu-img.1': (have_tools ? 'man1' : ''),
216
'qemu-nbd.8': (have_tools ? 'man8' : ''),
217
'qemu-pr-helper.8': (have_tools ? 'man8' : ''),
218
@@ -XXX,XX +XXX,XX @@ if build_docs
219
'qemu-trace-stap.1': (config_host.has_key('CONFIG_TRACE_SYSTEMTAP') ? 'man1' : ''),
220
'virtfs-proxy-helper.1': (have_virtfs_proxy_helper ? 'man1' : ''),
221
'virtiofsd.1': (have_virtiofsd ? 'man1' : ''),
222
- },
223
- 'system': {
224
'qemu.1': 'man1',
225
'qemu-block-drivers.7': 'man7',
226
'qemu-cpu-models.7': 'man7'
227
- },
228
}
229
230
sphinxdocs = []
231
sphinxmans = []
232
- foreach manual : manuals
233
- private_dir = meson.current_build_dir() / (manual + '.p')
234
- output_dir = meson.current_build_dir() / manual
235
- input_dir = meson.current_source_dir() / manual
236
237
- this_manual = custom_target(manual + ' manual',
238
+ private_dir = meson.current_build_dir() / 'manual.p'
239
+ output_dir = meson.current_build_dir() / 'manual'
240
+ input_dir = meson.current_source_dir()
241
+
242
+ this_manual = custom_target('QEMU manual',
243
build_by_default: build_docs,
244
- output: [manual + '.stamp'],
245
- input: [files('conf.py'), files(manual / 'conf.py')],
246
- depfile: manual + '.d',
247
+ output: 'docs.stamp',
248
+ input: files('conf.py'),
249
+ depfile: 'docs.d',
250
depend_files: sphinx_extn_depends,
251
command: [SPHINX_ARGS, '-Ddepfile=@DEPFILE@',
252
'-Ddepfile_stamp=@OUTPUT0@',
253
'-b', 'html', '-d', private_dir,
254
input_dir, output_dir])
255
- sphinxdocs += this_manual
256
- if build_docs and manual != 'devel'
257
- install_subdir(output_dir, install_dir: qemu_docdir)
258
- endif
259
+ sphinxdocs += this_manual
260
+ install_subdir(output_dir, install_dir: qemu_docdir, strip_directory: true)
261
262
- these_man_pages = []
263
- install_dirs = []
264
- foreach page, section : man_pages.get(manual, {})
265
- these_man_pages += page
266
- install_dirs += section == '' ? false : get_option('mandir') / section
267
- endforeach
268
- if these_man_pages.length() > 0
269
- sphinxmans += custom_target(manual + ' man pages',
270
- build_by_default: build_docs,
271
- output: these_man_pages,
272
- input: this_manual,
273
- install: build_docs,
274
- install_dir: install_dirs,
275
- command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir,
276
- input_dir, meson.current_build_dir()])
277
- endif
278
+ these_man_pages = []
279
+ install_dirs = []
280
+ foreach page, section : man_pages
281
+ these_man_pages += page
282
+ install_dirs += section == '' ? false : get_option('mandir') / section
283
endforeach
284
+
285
+ sphinxmans += custom_target('QEMU man pages',
286
+ build_by_default: build_docs,
287
+ output: these_man_pages,
288
+ input: this_manual,
289
+ install: build_docs,
290
+ install_dir: install_dirs,
291
+ command: [SPHINX_ARGS, '-b', 'man', '-d', private_dir,
292
+ input_dir, meson.current_build_dir()])
293
+
294
alias_target('sphinxdocs', sphinxdocs)
295
alias_target('html', sphinxdocs)
296
alias_target('man', sphinxmans)
297
diff --git a/docs/specs/conf.py b/docs/specs/conf.py
298
deleted file mode 100644
299
index XXXXXXX..XXXXXXX
300
--- a/docs/specs/conf.py
301
+++ /dev/null
302
@@ -XXX,XX +XXX,XX @@
303
-# -*- coding: utf-8 -*-
304
-#
305
-# QEMU documentation build configuration file for the 'specs' manual.
306
-#
307
-# This includes the top level conf file and then makes any necessary tweaks.
308
-import sys
309
-import os
310
-
311
-qemu_docdir = os.path.abspath("..")
312
-parent_config = os.path.join(qemu_docdir, "conf.py")
313
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
314
-
315
-# This slightly misuses the 'description', but is the best way to get
316
-# the manual title to appear in the sidebar.
317
-html_theme_options['description'] = \
318
- u'System Emulation Guest Hardware Specifications'
319
diff --git a/docs/system/conf.py b/docs/system/conf.py
320
deleted file mode 100644
321
index XXXXXXX..XXXXXXX
322
--- a/docs/system/conf.py
323
+++ /dev/null
324
@@ -XXX,XX +XXX,XX @@
325
-# -*- coding: utf-8 -*-
326
-#
327
-# QEMU documentation build configuration file for the 'system' manual.
328
-#
329
-# This includes the top level conf file and then makes any necessary tweaks.
330
-import sys
331
-import os
332
-
333
-qemu_docdir = os.path.abspath("..")
334
-parent_config = os.path.join(qemu_docdir, "conf.py")
335
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
336
-
337
-# This slightly misuses the 'description', but is the best way to get
338
-# the manual title to appear in the sidebar.
339
-html_theme_options['description'] = u'System Emulation User''s Guide'
340
-
341
-# One entry per manual page. List of tuples
342
-# (source start file, name, description, authors, manual section).
343
-man_pages = [
344
- ('qemu-manpage', 'qemu', u'QEMU User Documentation',
345
- ['Fabrice Bellard'], 1),
346
- ('qemu-block-drivers', 'qemu-block-drivers',
347
- u'QEMU block drivers reference',
348
- ['Fabrice Bellard and the QEMU Project developers'], 7),
349
- ('qemu-cpu-models', 'qemu-cpu-models',
350
- u'QEMU CPU Models',
351
- ['The QEMU Project developers'], 7)
352
-]
353
diff --git a/docs/tools/conf.py b/docs/tools/conf.py
354
deleted file mode 100644
355
index XXXXXXX..XXXXXXX
356
--- a/docs/tools/conf.py
357
+++ /dev/null
358
@@ -XXX,XX +XXX,XX @@
359
-# -*- coding: utf-8 -*-
360
-#
361
-# QEMU documentation build configuration file for the 'tools' manual.
362
-#
363
-# This includes the top level conf file and then makes any necessary tweaks.
364
-import sys
365
-import os
366
-
367
-qemu_docdir = os.path.abspath("..")
368
-parent_config = os.path.join(qemu_docdir, "conf.py")
369
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
370
-
371
-# This slightly misuses the 'description', but is the best way to get
372
-# the manual title to appear in the sidebar.
373
-html_theme_options['description'] = \
374
- u'Tools Guide'
375
-
376
-# One entry per manual page. List of tuples
377
-# (source start file, name, description, authors, manual section).
378
-man_pages = [
379
- ('qemu-img', 'qemu-img', u'QEMU disk image utility',
380
- ['Fabrice Bellard'], 1),
381
- ('qemu-storage-daemon', 'qemu-storage-daemon', u'QEMU storage daemon',
382
- [], 1),
383
- ('qemu-nbd', 'qemu-nbd', u'QEMU Disk Network Block Device Server',
384
- ['Anthony Liguori <anthony@codemonkey.ws>'], 8),
385
- ('qemu-pr-helper', 'qemu-pr-helper', 'QEMU persistent reservation helper',
386
- [], 8),
387
- ('qemu-trace-stap', 'qemu-trace-stap', u'QEMU SystemTap trace tool',
388
- [], 1),
389
- ('virtfs-proxy-helper', 'virtfs-proxy-helper',
390
- u'QEMU 9p virtfs proxy filesystem helper',
391
- ['M. Mohan Kumar'], 1),
392
- ('virtiofsd', 'virtiofsd', u'QEMU virtio-fs shared file system daemon',
393
- ['Stefan Hajnoczi <stefanha@redhat.com>',
394
- 'Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>'], 1),
395
-]
396
diff --git a/docs/user/conf.py b/docs/user/conf.py
397
deleted file mode 100644
398
index XXXXXXX..XXXXXXX
399
--- a/docs/user/conf.py
400
+++ /dev/null
401
@@ -XXX,XX +XXX,XX @@
402
-# -*- coding: utf-8 -*-
403
-#
404
-# QEMU documentation build configuration file for the 'user' manual.
405
-#
406
-# This includes the top level conf file and then makes any necessary tweaks.
407
-import sys
408
-import os
409
-
410
-qemu_docdir = os.path.abspath("..")
411
-parent_config = os.path.join(qemu_docdir, "conf.py")
412
-exec(compile(open(parent_config, "rb").read(), parent_config, 'exec'))
413
-
414
-# This slightly misuses the 'description', but is the best way to get
415
-# the manual title to appear in the sidebar.
416
-html_theme_options['description'] = u'User Mode Emulation User''s Guide'
42
--
417
--
43
2.20.1
418
2.20.1
44
419
45
420
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
In commit cd8be50e58f63413c0 we converted the A32 coprocessor
2
insns to decodetree. This accidentally broke XScale/iWMMXt insns,
3
because it moved the handling of "cp insns which are handled
4
by looking up the cp register in the hashtable" from after the
5
call to the legacy disas_xscale_insn() decode to before it,
6
with the result that all XScale/iWMMXt insns now UNDEF.
2
7
3
Found by inspection: Rn is the base register against which the
8
Update valid_cp() so that it knows that on XScale cp 0 and 1
4
load began; I is the register within the mask being processed.
9
are not standard coprocessor instructions; this will cause
5
The exception return should of course be processed from the loaded PC.
10
the decodetree trans_ functions to ignore them, so that
11
execution will correctly get through to the legacy decode again.
6
12
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Cc: qemu-stable@nongnu.org
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Reported-by: Guenter Roeck <linux@roeck-us.net>
9
Message-id: 20190301202921.21209-1-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Tested-by: Guenter Roeck <linux@roeck-us.net>
18
Message-id: 20210108195157.32067-1-peter.maydell@linaro.org
11
---
19
---
12
target/arm/translate.c | 2 +-
20
target/arm/translate.c | 7 +++++++
13
1 file changed, 1 insertion(+), 1 deletion(-)
21
1 file changed, 7 insertions(+)
14
22
15
diff --git a/target/arm/translate.c b/target/arm/translate.c
23
diff --git a/target/arm/translate.c b/target/arm/translate.c
16
index XXXXXXX..XXXXXXX 100644
24
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate.c
25
--- a/target/arm/translate.c
18
+++ b/target/arm/translate.c
26
+++ b/target/arm/translate.c
19
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
27
@@ -XXX,XX +XXX,XX @@ static bool valid_cp(DisasContext *s, int cp)
20
} else if (i == rn) {
28
* only cp14 and cp15 are valid, and other values aren't considered
21
loaded_var = tmp;
29
* to be in the coprocessor-instruction space at all. v8M still
22
loaded_base = 1;
30
* permits coprocessors 0..7.
23
- } else if (rn == 15 && exc_return) {
31
+ * For XScale, we must not decode the XScale cp0, cp1 space as
24
+ } else if (i == 15 && exc_return) {
32
+ * a standard coprocessor insn, because we want to fall through to
25
store_pc_exc_ret(s, tmp);
33
+ * the legacy disas_xscale_insn() decoder after decodetree is done.
26
} else {
34
*/
27
store_reg_from_load(s, i, tmp);
35
+ if (arm_dc_feature(s, ARM_FEATURE_XSCALE) && (cp == 0 || cp == 1)) {
36
+ return false;
37
+ }
38
+
39
if (arm_dc_feature(s, ARM_FEATURE_V8) &&
40
!arm_dc_feature(s, ARM_FEATURE_M)) {
41
return cp >= 14;
28
--
42
--
29
2.20.1
43
2.20.1
30
44
31
45
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
A copy-and-paste error meant that the return value for register offset 0x44
2
(the RX Status FIFO PEEK register) returned a byte from a bogus offset in
3
the rx status FIFO. Fix the typo.
2
4
3
Add the kvm_arm_get_max_vm_ipa_size() helper that returns the
5
Cc: qemu-stable@nongnu.org
4
number of bits in the IPA address space supported by KVM.
6
Fixes: https://bugs.launchpad.net/qemu/+bug/1904954
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
9
Message-id: 20210108180401.2263-2-peter.maydell@linaro.org
10
---
11
hw/net/lan9118.c | 2 +-
12
1 file changed, 1 insertion(+), 1 deletion(-)
5
13
6
This capability needs to be known to create the VM with a
14
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
7
specific IPA max size (kvm_type passed along KVM_CREATE_VM ioctl.
8
9
Signed-off-by: Eric Auger <eric.auger@redhat.com>
10
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
11
Message-id: 20190304101339.25970-6-eric.auger@redhat.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/kvm_arm.h | 13 +++++++++++++
15
target/arm/kvm.c | 10 ++++++++++
16
2 files changed, 23 insertions(+)
17
18
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
19
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/kvm_arm.h
16
--- a/hw/net/lan9118.c
21
+++ b/target/arm/kvm_arm.h
17
+++ b/hw/net/lan9118.c
22
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf);
18
@@ -XXX,XX +XXX,XX @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset,
23
*/
19
case 0x40:
24
void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu);
20
return rx_status_fifo_pop(s);
25
21
case 0x44:
26
+/**
22
- return s->rx_status_fifo[s->tx_status_fifo_head];
27
+ * kvm_arm_get_max_vm_ipa_size - Returns the number of bits in the
23
+ return s->rx_status_fifo[s->rx_status_fifo_head];
28
+ * IPA address space supported by KVM
24
case 0x48:
29
+ *
25
return tx_status_fifo_pop(s);
30
+ * @ms: Machine state handle
26
case 0x4c:
31
+ */
32
+int kvm_arm_get_max_vm_ipa_size(MachineState *ms);
33
+
34
/**
35
* kvm_arm_sync_mpstate_to_kvm
36
* @cpu: ARMCPU
37
@@ -XXX,XX +XXX,XX @@ static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
38
cpu->host_cpu_probe_failed = true;
39
}
40
41
+static inline int kvm_arm_get_max_vm_ipa_size(MachineState *ms)
42
+{
43
+ return -ENOENT;
44
+}
45
+
46
static inline int kvm_arm_vgic_probe(void)
47
{
48
return 0;
49
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
50
index XXXXXXX..XXXXXXX 100644
51
--- a/target/arm/kvm.c
52
+++ b/target/arm/kvm.c
53
@@ -XXX,XX +XXX,XX @@
54
#include "qemu/error-report.h"
55
#include "sysemu/sysemu.h"
56
#include "sysemu/kvm.h"
57
+#include "sysemu/kvm_int.h"
58
#include "kvm_arm.h"
59
#include "cpu.h"
60
#include "trace.h"
61
@@ -XXX,XX +XXX,XX @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
62
env->features = arm_host_cpu_features.features;
63
}
64
65
+int kvm_arm_get_max_vm_ipa_size(MachineState *ms)
66
+{
67
+ KVMState *s = KVM_STATE(ms->accelerator);
68
+ int ret;
69
+
70
+ ret = kvm_check_extension(s, KVM_CAP_ARM_VM_IPA_SIZE);
71
+ return ret > 0 ? ret : 40;
72
+}
73
+
74
int kvm_arch_init(MachineState *ms, KVMState *s)
75
{
76
/* For ARM interrupt delivery is always asynchronous,
77
--
27
--
78
2.20.1
28
2.20.1
79
29
80
30
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
The lan9118 code mostly uses symbolic constants for register offsets;
2
the exceptions are those which the datasheet doesn't give an official
3
symbolic name to.
2
4
3
On ARM, the kvm_type will be resolved by querying the KVMState.
5
Add some names for the registers which don't already have them, based
4
Let's add the MachineState handle to the callback so that we
6
on the longer names they are given in the memory map.
5
can retrieve the KVMState handle. in kvm_init, when the callback
6
is called, the kvm_state variable is not yet set.
7
7
8
Signed-off-by: Eric Auger <eric.auger@redhat.com>
9
Acked-by: David Gibson <david@gibson.dropbear.id.au>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
12
Message-id: 20190304101339.25970-5-eric.auger@redhat.com
13
[ppc parts]
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
10
Message-id: 20210108180401.2263-3-peter.maydell@linaro.org
17
---
11
---
18
include/hw/boards.h | 5 ++++-
12
hw/net/lan9118.c | 24 ++++++++++++++++++------
19
accel/kvm/kvm-all.c | 2 +-
13
1 file changed, 18 insertions(+), 6 deletions(-)
20
hw/ppc/mac_newworld.c | 3 +--
21
hw/ppc/mac_oldworld.c | 2 +-
22
hw/ppc/spapr.c | 2 +-
23
5 files changed, 8 insertions(+), 6 deletions(-)
24
14
25
diff --git a/include/hw/boards.h b/include/hw/boards.h
15
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
26
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
27
--- a/include/hw/boards.h
17
--- a/hw/net/lan9118.c
28
+++ b/include/hw/boards.h
18
+++ b/hw/net/lan9118.c
29
@@ -XXX,XX +XXX,XX @@ typedef struct {
19
@@ -XXX,XX +XXX,XX @@ do { hw_error("lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
30
* should instead use "unimplemented-device" for all memory ranges where
20
do { fprintf(stderr, "lan9118: error: " fmt , ## __VA_ARGS__);} while (0)
31
* the guest will attempt to probe for a device that QEMU doesn't
21
#endif
32
* implement and a stub device is required.
22
33
+ * @kvm_type:
23
+/* The tx and rx fifo ports are a range of aliased 32-bit registers */
34
+ * Return the type of KVM corresponding to the kvm-type string option or
24
+#define RX_DATA_FIFO_PORT_FIRST 0x00
35
+ * computed based on other criteria such as the host kernel capabilities.
25
+#define RX_DATA_FIFO_PORT_LAST 0x1f
36
*/
26
+#define TX_DATA_FIFO_PORT_FIRST 0x20
37
struct MachineClass {
27
+#define TX_DATA_FIFO_PORT_LAST 0x3f
38
/*< private >*/
28
+
39
@@ -XXX,XX +XXX,XX @@ struct MachineClass {
29
+#define RX_STATUS_FIFO_PORT 0x40
40
void (*init)(MachineState *state);
30
+#define RX_STATUS_FIFO_PEEK 0x44
41
void (*reset)(void);
31
+#define TX_STATUS_FIFO_PORT 0x48
42
void (*hot_add_cpu)(const int64_t id, Error **errp);
32
+#define TX_STATUS_FIFO_PEEK 0x4c
43
- int (*kvm_type)(const char *arg);
33
+
44
+ int (*kvm_type)(MachineState *machine, const char *arg);
34
#define CSR_ID_REV 0x50
45
35
#define CSR_IRQ_CFG 0x54
46
BlockInterfaceType block_default_type;
36
#define CSR_INT_STS 0x58
47
int units_per_default_bus;
37
@@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset,
48
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
38
offset &= 0xff;
49
index XXXXXXX..XXXXXXX 100644
39
50
--- a/accel/kvm/kvm-all.c
40
//DPRINTF("Write reg 0x%02x = 0x%08x\n", (int)offset, val);
51
+++ b/accel/kvm/kvm-all.c
41
- if (offset >= 0x20 && offset < 0x40) {
52
@@ -XXX,XX +XXX,XX @@ static int kvm_init(MachineState *ms)
42
+ if (offset >= TX_DATA_FIFO_PORT_FIRST &&
53
43
+ offset <= TX_DATA_FIFO_PORT_LAST) {
54
kvm_type = qemu_opt_get(qemu_get_machine_opts(), "kvm-type");
44
/* TX FIFO */
55
if (mc->kvm_type) {
45
tx_fifo_push(s, val);
56
- type = mc->kvm_type(kvm_type);
46
return;
57
+ type = mc->kvm_type(ms, kvm_type);
47
@@ -XXX,XX +XXX,XX @@ static uint64_t lan9118_readl(void *opaque, hwaddr offset,
58
} else if (kvm_type) {
48
lan9118_state *s = (lan9118_state *)opaque;
59
ret = -EINVAL;
49
60
fprintf(stderr, "Invalid argument kvm-type=%s\n", kvm_type);
50
//DPRINTF("Read reg 0x%02x\n", (int)offset);
61
diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c
51
- if (offset < 0x20) {
62
index XXXXXXX..XXXXXXX 100644
52
+ if (offset <= RX_DATA_FIFO_PORT_LAST) {
63
--- a/hw/ppc/mac_newworld.c
53
/* RX FIFO */
64
+++ b/hw/ppc/mac_newworld.c
54
return rx_fifo_pop(s);
65
@@ -XXX,XX +XXX,XX @@ static char *core99_fw_dev_path(FWPathProvider *p, BusState *bus,
66
67
return NULL;
68
}
69
-
70
-static int core99_kvm_type(const char *arg)
71
+static int core99_kvm_type(MachineState *machine, const char *arg)
72
{
73
/* Always force PR KVM */
74
return 2;
75
diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c
76
index XXXXXXX..XXXXXXX 100644
77
--- a/hw/ppc/mac_oldworld.c
78
+++ b/hw/ppc/mac_oldworld.c
79
@@ -XXX,XX +XXX,XX @@ static char *heathrow_fw_dev_path(FWPathProvider *p, BusState *bus,
80
return NULL;
81
}
82
83
-static int heathrow_kvm_type(const char *arg)
84
+static int heathrow_kvm_type(MachineState *machine, const char *arg)
85
{
86
/* Always force PR KVM */
87
return 2;
88
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
89
index XXXXXXX..XXXXXXX 100644
90
--- a/hw/ppc/spapr.c
91
+++ b/hw/ppc/spapr.c
92
@@ -XXX,XX +XXX,XX @@ static void spapr_machine_init(MachineState *machine)
93
}
55
}
94
}
56
switch (offset) {
95
57
- case 0x40:
96
-static int spapr_kvm_type(const char *vm_type)
58
+ case RX_STATUS_FIFO_PORT:
97
+static int spapr_kvm_type(MachineState *machine, const char *vm_type)
59
return rx_status_fifo_pop(s);
98
{
60
- case 0x44:
99
if (!vm_type) {
61
+ case RX_STATUS_FIFO_PEEK:
100
return 0;
62
return s->rx_status_fifo[s->rx_status_fifo_head];
63
- case 0x48:
64
+ case TX_STATUS_FIFO_PORT:
65
return tx_status_fifo_pop(s);
66
- case 0x4c:
67
+ case TX_STATUS_FIFO_PEEK:
68
return s->tx_status_fifo[s->tx_status_fifo_head];
69
case CSR_ID_REV:
70
return 0x01180001;
101
--
71
--
102
2.20.1
72
2.20.1
103
73
104
74
diff view generated by jsdifflib
1
From: Michel Heily <michelheily@gmail.com>
1
From: Hao Wu <wuhaotsh@google.com>
2
2
3
Implement the watchdog timer for the stellaris boards.
3
This patch allows NPCM7XX CLK module to compute clocks that are used by
4
This device is a close variant of the CMSDK APB watchdog
4
other NPCM7XX modules.
5
device, so we can model it by subclassing that device and
6
tweaking the behaviour of some of its registers.
7
5
8
Signed-off-by: Michel Heily <michelheily@gmail.com>
6
Add a new struct NPCM7xxClockConverterState which represents a
9
Reviewed-by: Peter Maydell <petser.maydell@linaro.org>
7
single converter. Each clock converter in CLK module represents one
10
[PMM: rewrote commit message, fixed a few checkpatch nits,
8
converter in NPCM7XX CLK Module(PLL, SEL or Divider). Each converter
11
added comment giving the URL of the spec for the Stellaris
9
takes one or more input clocks and converts them into one output clock.
12
variant of the watchdog device]
10
They form a clock hierarchy in the CLK module and are responsible for
11
outputing clocks for various other modules in an NPCM7XX SoC.
12
13
Each converter has a function pointer called "convert" which represents
14
the unique logic for that converter.
15
16
The clock contains two initialization information: ConverterInitInfo and
17
ConverterConnectionInfo. They represent the vertices and edges in the
18
clock diagram respectively.
19
20
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
21
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
22
Signed-off-by: Hao Wu <wuhaotsh@google.com>
23
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
24
Message-id: 20210108190945.949196-2-wuhaotsh@google.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
26
---
15
include/hw/watchdog/cmsdk-apb-watchdog.h | 8 +++
27
include/hw/misc/npcm7xx_clk.h | 140 +++++-
16
hw/arm/stellaris.c | 22 ++++++-
28
hw/misc/npcm7xx_clk.c | 805 +++++++++++++++++++++++++++++++++-
17
hw/watchdog/cmsdk-apb-watchdog.c | 74 +++++++++++++++++++++++-
29
2 files changed, 932 insertions(+), 13 deletions(-)
18
3 files changed, 100 insertions(+), 4 deletions(-)
19
30
20
diff --git a/include/hw/watchdog/cmsdk-apb-watchdog.h b/include/hw/watchdog/cmsdk-apb-watchdog.h
31
diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
21
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
22
--- a/include/hw/watchdog/cmsdk-apb-watchdog.h
33
--- a/include/hw/misc/npcm7xx_clk.h
23
+++ b/include/hw/watchdog/cmsdk-apb-watchdog.h
34
+++ b/include/hw/misc/npcm7xx_clk.h
24
@@ -XXX,XX +XXX,XX @@
35
@@ -XXX,XX +XXX,XX @@
25
#define CMSDK_APB_WATCHDOG(obj) OBJECT_CHECK(CMSDKAPBWatchdog, (obj), \
36
#define NPCM7XX_CLK_H
26
TYPE_CMSDK_APB_WATCHDOG)
37
38
#include "exec/memory.h"
39
+#include "hw/clock.h"
40
#include "hw/sysbus.h"
41
42
/*
43
@@ -XXX,XX +XXX,XX @@
44
45
#define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
46
47
-typedef struct NPCM7xxCLKState {
48
+/* Maximum amount of clock inputs in a SEL module. */
49
+#define NPCM7XX_CLK_SEL_MAX_INPUT 5
50
+
51
+/* PLLs in CLK module. */
52
+typedef enum NPCM7xxClockPLL {
53
+ NPCM7XX_CLOCK_PLL0,
54
+ NPCM7XX_CLOCK_PLL1,
55
+ NPCM7XX_CLOCK_PLL2,
56
+ NPCM7XX_CLOCK_PLLG,
57
+ NPCM7XX_CLOCK_NR_PLLS,
58
+} NPCM7xxClockPLL;
59
+
60
+/* SEL/MUX in CLK module. */
61
+typedef enum NPCM7xxClockSEL {
62
+ NPCM7XX_CLOCK_PIXCKSEL,
63
+ NPCM7XX_CLOCK_MCCKSEL,
64
+ NPCM7XX_CLOCK_CPUCKSEL,
65
+ NPCM7XX_CLOCK_CLKOUTSEL,
66
+ NPCM7XX_CLOCK_UARTCKSEL,
67
+ NPCM7XX_CLOCK_TIMCKSEL,
68
+ NPCM7XX_CLOCK_SDCKSEL,
69
+ NPCM7XX_CLOCK_GFXMSEL,
70
+ NPCM7XX_CLOCK_SUCKSEL,
71
+ NPCM7XX_CLOCK_NR_SELS,
72
+} NPCM7xxClockSEL;
73
+
74
+/* Dividers in CLK module. */
75
+typedef enum NPCM7xxClockDivider {
76
+ NPCM7XX_CLOCK_PLL1D2, /* PLL1/2 */
77
+ NPCM7XX_CLOCK_PLL2D2, /* PLL2/2 */
78
+ NPCM7XX_CLOCK_MC_DIVIDER,
79
+ NPCM7XX_CLOCK_AXI_DIVIDER,
80
+ NPCM7XX_CLOCK_AHB_DIVIDER,
81
+ NPCM7XX_CLOCK_AHB3_DIVIDER,
82
+ NPCM7XX_CLOCK_SPI0_DIVIDER,
83
+ NPCM7XX_CLOCK_SPIX_DIVIDER,
84
+ NPCM7XX_CLOCK_APB1_DIVIDER,
85
+ NPCM7XX_CLOCK_APB2_DIVIDER,
86
+ NPCM7XX_CLOCK_APB3_DIVIDER,
87
+ NPCM7XX_CLOCK_APB4_DIVIDER,
88
+ NPCM7XX_CLOCK_APB5_DIVIDER,
89
+ NPCM7XX_CLOCK_CLKOUT_DIVIDER,
90
+ NPCM7XX_CLOCK_UART_DIVIDER,
91
+ NPCM7XX_CLOCK_TIMER_DIVIDER,
92
+ NPCM7XX_CLOCK_ADC_DIVIDER,
93
+ NPCM7XX_CLOCK_MMC_DIVIDER,
94
+ NPCM7XX_CLOCK_SDHC_DIVIDER,
95
+ NPCM7XX_CLOCK_GFXM_DIVIDER, /* divide by 3 */
96
+ NPCM7XX_CLOCK_UTMI_DIVIDER,
97
+ NPCM7XX_CLOCK_NR_DIVIDERS,
98
+} NPCM7xxClockConverter;
99
+
100
+typedef struct NPCM7xxCLKState NPCM7xxCLKState;
101
+
102
+/**
103
+ * struct NPCM7xxClockPLLState - A PLL module in CLK module.
104
+ * @name: The name of the module.
105
+ * @clk: The CLK module that owns this module.
106
+ * @clock_in: The input clock of this module.
107
+ * @clock_out: The output clock of this module.
108
+ * @reg: The control registers for this PLL module.
109
+ */
110
+typedef struct NPCM7xxClockPLLState {
111
+ DeviceState parent;
112
+
113
+ const char *name;
114
+ NPCM7xxCLKState *clk;
115
+ Clock *clock_in;
116
+ Clock *clock_out;
117
+
118
+ int reg;
119
+} NPCM7xxClockPLLState;
120
+
121
+/**
122
+ * struct NPCM7xxClockSELState - A SEL module in CLK module.
123
+ * @name: The name of the module.
124
+ * @clk: The CLK module that owns this module.
125
+ * @input_size: The size of inputs of this module.
126
+ * @clock_in: The input clocks of this module.
127
+ * @clock_out: The output clocks of this module.
128
+ * @offset: The offset of this module in the control register.
129
+ * @len: The length of this module in the control register.
130
+ */
131
+typedef struct NPCM7xxClockSELState {
132
+ DeviceState parent;
133
+
134
+ const char *name;
135
+ NPCM7xxCLKState *clk;
136
+ uint8_t input_size;
137
+ Clock *clock_in[NPCM7XX_CLK_SEL_MAX_INPUT];
138
+ Clock *clock_out;
139
+
140
+ int offset;
141
+ int len;
142
+} NPCM7xxClockSELState;
143
+
144
+/**
145
+ * struct NPCM7xxClockDividerState - A Divider module in CLK module.
146
+ * @name: The name of the module.
147
+ * @clk: The CLK module that owns this module.
148
+ * @clock_in: The input clock of this module.
149
+ * @clock_out: The output clock of this module.
150
+ * @divide: The function the divider uses to divide the input.
151
+ * @reg: The index of the control register that contains the divisor.
152
+ * @offset: The offset of the divisor in the control register.
153
+ * @len: The length of the divisor in the control register.
154
+ * @divisor: The divisor for a constant divisor
155
+ */
156
+typedef struct NPCM7xxClockDividerState {
157
+ DeviceState parent;
158
+
159
+ const char *name;
160
+ NPCM7xxCLKState *clk;
161
+ Clock *clock_in;
162
+ Clock *clock_out;
163
+
164
+ uint32_t (*divide)(struct NPCM7xxClockDividerState *s);
165
+ union {
166
+ struct {
167
+ int reg;
168
+ int offset;
169
+ int len;
170
+ };
171
+ int divisor;
172
+ };
173
+} NPCM7xxClockDividerState;
174
+
175
+struct NPCM7xxCLKState {
176
SysBusDevice parent;
177
178
MemoryRegion iomem;
179
180
+ /* Clock converters */
181
+ NPCM7xxClockPLLState plls[NPCM7XX_CLOCK_NR_PLLS];
182
+ NPCM7xxClockSELState sels[NPCM7XX_CLOCK_NR_SELS];
183
+ NPCM7xxClockDividerState dividers[NPCM7XX_CLOCK_NR_DIVIDERS];
184
+
185
uint32_t regs[NPCM7XX_CLK_NR_REGS];
186
187
/* Time reference for SECCNT and CNTR25M, initialized by power on reset */
188
int64_t ref_ns;
189
-} NPCM7xxCLKState;
190
+
191
+ /* The incoming reference clock. */
192
+ Clock *clkref;
193
+};
194
195
#define TYPE_NPCM7XX_CLK "npcm7xx-clk"
196
#define NPCM7XX_CLK(obj) OBJECT_CHECK(NPCM7xxCLKState, (obj), TYPE_NPCM7XX_CLK)
197
diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
198
index XXXXXXX..XXXXXXX 100644
199
--- a/hw/misc/npcm7xx_clk.c
200
+++ b/hw/misc/npcm7xx_clk.c
201
@@ -XXX,XX +XXX,XX @@
202
203
#include "hw/misc/npcm7xx_clk.h"
204
#include "hw/timer/npcm7xx_timer.h"
205
+#include "hw/qdev-clock.h"
206
#include "migration/vmstate.h"
207
#include "qemu/error-report.h"
208
#include "qemu/log.h"
209
@@ -XXX,XX +XXX,XX @@
210
#include "trace.h"
211
#include "sysemu/watchdog.h"
27
212
28
+/*
213
+/*
29
+ * This shares the same struct (and cast macro) as the base
214
+ * The reference clock hz, and the SECCNT and CNTR25M registers in this module,
30
+ * cmsdk-apb-watchdog device.
215
+ * is always 25 MHz.
31
+ */
216
+ */
32
+#define TYPE_LUMINARY_WATCHDOG "luminary-watchdog"
217
+#define NPCM7XX_CLOCK_REF_HZ (25000000)
33
+
218
+
34
typedef struct CMSDKAPBWatchdog {
219
+/* Register Field Definitions */
35
/*< private >*/
220
+#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */
36
SysBusDevice parent_obj;
221
+
37
@@ -XXX,XX +XXX,XX @@ typedef struct CMSDKAPBWatchdog {
222
#define PLLCON_LOKI BIT(31)
38
MemoryRegion iomem;
223
#define PLLCON_LOKS BIT(30)
39
qemu_irq wdogint;
224
#define PLLCON_PWDEN BIT(12)
40
uint32_t wdogclk_frq;
225
+#define PLLCON_FBDV(con) extract32((con), 16, 12)
41
+ bool is_luminary;
226
+#define PLLCON_OTDV2(con) extract32((con), 13, 3)
42
struct ptimer_state *timer;
227
+#define PLLCON_OTDV1(con) extract32((con), 8, 3)
43
228
+#define PLLCON_INDV(con) extract32((con), 0, 6)
44
uint32_t control;
229
45
@@ -XXX,XX +XXX,XX @@ typedef struct CMSDKAPBWatchdog {
230
enum NPCM7xxCLKRegisters {
46
uint32_t itcr;
231
NPCM7XX_CLK_CLKEN1,
47
uint32_t itop;
232
@@ -XXX,XX +XXX,XX @@ static const uint32_t cold_reset_values[NPCM7XX_CLK_NR_REGS] = {
48
uint32_t resetstatus;
233
[NPCM7XX_CLK_AHBCKFI] = 0x000000c8,
49
+ const uint32_t *id;
50
} CMSDKAPBWatchdog;
51
52
#endif
53
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
54
index XXXXXXX..XXXXXXX 100644
55
--- a/hw/arm/stellaris.c
56
+++ b/hw/arm/stellaris.c
57
@@ -XXX,XX +XXX,XX @@
58
#include "sysemu/sysemu.h"
59
#include "hw/arm/armv7m.h"
60
#include "hw/char/pl011.h"
61
+#include "hw/watchdog/cmsdk-apb-watchdog.h"
62
#include "hw/misc/unimp.h"
63
#include "cpu.h"
64
65
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
66
* Stellaris LM3S6965 Microcontroller Data Sheet (rev I)
67
* http://www.ti.com/lit/ds/symlink/lm3s6965.pdf
68
*
69
- * 40000000 wdtimer (unimplemented)
70
+ * 40000000 wdtimer
71
* 40002000 i2c (unimplemented)
72
* 40004000 GPIO
73
* 40005000 GPIO
74
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
75
stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28),
76
board, nd_table[0].macaddr.a);
77
78
+
79
+ if (board->dc1 & (1 << 3)) { /* watchdog present */
80
+ dev = qdev_create(NULL, TYPE_LUMINARY_WATCHDOG);
81
+
82
+ /* system_clock_scale is valid now */
83
+ uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale;
84
+ qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk);
85
+
86
+ qdev_init_nofail(dev);
87
+ sysbus_mmio_map(SYS_BUS_DEVICE(dev),
88
+ 0,
89
+ 0x40000000u);
90
+ sysbus_connect_irq(SYS_BUS_DEVICE(dev),
91
+ 0,
92
+ qdev_get_gpio_in(nvic, 18));
93
+ }
94
+
95
+
96
for (i = 0; i < 7; i++) {
97
if (board->dc4 & (1 << i)) {
98
gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],
99
@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)
100
/* Add dummy regions for the devices we don't implement yet,
101
* so guest accesses don't cause unlogged crashes.
102
*/
103
- create_unimplemented_device("wdtimer", 0x40000000, 0x1000);
104
create_unimplemented_device("i2c-0", 0x40002000, 0x1000);
105
create_unimplemented_device("i2c-2", 0x40021000, 0x1000);
106
create_unimplemented_device("PWM", 0x40028000, 0x1000);
107
diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c
108
index XXXXXXX..XXXXXXX 100644
109
--- a/hw/watchdog/cmsdk-apb-watchdog.c
110
+++ b/hw/watchdog/cmsdk-apb-watchdog.c
111
@@ -XXX,XX +XXX,XX @@
112
* System Design Kit (CMSDK) and documented in the Cortex-M System
113
* Design Kit Technical Reference Manual (ARM DDI0479C):
114
* https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
115
+ *
116
+ * We also support the variant of this device found in the TI
117
+ * Stellaris/Luminary boards and documented in:
118
+ * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf
119
*/
120
121
#include "qemu/osdep.h"
122
@@ -XXX,XX +XXX,XX @@ REG32(WDOGINTCLR, 0xc)
123
REG32(WDOGRIS, 0x10)
124
FIELD(WDOGRIS, INT, 0, 1)
125
REG32(WDOGMIS, 0x14)
126
+REG32(WDOGTEST, 0x418) /* only in Stellaris/Luminary version of the device */
127
REG32(WDOGLOCK, 0xc00)
128
#define WDOG_UNLOCK_VALUE 0x1ACCE551
129
REG32(WDOGITCR, 0xf00)
130
@@ -XXX,XX +XXX,XX @@ REG32(CID2, 0xff8)
131
REG32(CID3, 0xffc)
132
133
/* PID/CID values */
134
-static const int watchdog_id[] = {
135
+static const uint32_t cmsdk_apb_watchdog_id[] = {
136
0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
137
0x24, 0xb8, 0x1b, 0x00, /* PID0..PID3 */
138
0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
139
};
234
};
140
235
141
+static const uint32_t luminary_watchdog_id[] = {
236
-/* Register Field Definitions */
142
+ 0x00, 0x00, 0x00, 0x00, /* PID4..PID7 */
237
-#define NPCM7XX_CLK_WDRCR_CA9C BIT(0) /* Cortex A9 Cores */
143
+ 0x05, 0x18, 0x18, 0x01, /* PID0..PID3 */
238
-
144
+ 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
239
/* The number of watchdogs that can trigger a reset. */
240
#define NPCM7XX_NR_WATCHDOGS (3)
241
242
+/* Clock converter functions */
243
+
244
+#define TYPE_NPCM7XX_CLOCK_PLL "npcm7xx-clock-pll"
245
+#define NPCM7XX_CLOCK_PLL(obj) OBJECT_CHECK(NPCM7xxClockPLLState, \
246
+ (obj), TYPE_NPCM7XX_CLOCK_PLL)
247
+#define TYPE_NPCM7XX_CLOCK_SEL "npcm7xx-clock-sel"
248
+#define NPCM7XX_CLOCK_SEL(obj) OBJECT_CHECK(NPCM7xxClockSELState, \
249
+ (obj), TYPE_NPCM7XX_CLOCK_SEL)
250
+#define TYPE_NPCM7XX_CLOCK_DIVIDER "npcm7xx-clock-divider"
251
+#define NPCM7XX_CLOCK_DIVIDER(obj) OBJECT_CHECK(NPCM7xxClockDividerState, \
252
+ (obj), TYPE_NPCM7XX_CLOCK_DIVIDER)
253
+
254
+static void npcm7xx_clk_update_pll(void *opaque)
255
+{
256
+ NPCM7xxClockPLLState *s = opaque;
257
+ uint32_t con = s->clk->regs[s->reg];
258
+ uint64_t freq;
259
+
260
+ /* The PLL is grounded if it is not locked yet. */
261
+ if (con & PLLCON_LOKI) {
262
+ freq = clock_get_hz(s->clock_in);
263
+ freq *= PLLCON_FBDV(con);
264
+ freq /= PLLCON_INDV(con) * PLLCON_OTDV1(con) * PLLCON_OTDV2(con);
265
+ } else {
266
+ freq = 0;
267
+ }
268
+
269
+ clock_update_hz(s->clock_out, freq);
270
+}
271
+
272
+static void npcm7xx_clk_update_sel(void *opaque)
273
+{
274
+ NPCM7xxClockSELState *s = opaque;
275
+ uint32_t index = extract32(s->clk->regs[NPCM7XX_CLK_CLKSEL], s->offset,
276
+ s->len);
277
+
278
+ if (index >= s->input_size) {
279
+ qemu_log_mask(LOG_GUEST_ERROR,
280
+ "%s: SEL index: %u out of range\n",
281
+ __func__, index);
282
+ index = 0;
283
+ }
284
+ clock_update_hz(s->clock_out, clock_get_hz(s->clock_in[index]));
285
+}
286
+
287
+static void npcm7xx_clk_update_divider(void *opaque)
288
+{
289
+ NPCM7xxClockDividerState *s = opaque;
290
+ uint32_t freq;
291
+
292
+ freq = s->divide(s);
293
+ clock_update_hz(s->clock_out, freq);
294
+}
295
+
296
+static uint32_t divide_by_constant(NPCM7xxClockDividerState *s)
297
+{
298
+ return clock_get_hz(s->clock_in) / s->divisor;
299
+}
300
+
301
+static uint32_t divide_by_reg_divisor(NPCM7xxClockDividerState *s)
302
+{
303
+ return clock_get_hz(s->clock_in) /
304
+ (extract32(s->clk->regs[s->reg], s->offset, s->len) + 1);
305
+}
306
+
307
+static uint32_t divide_by_reg_divisor_times_2(NPCM7xxClockDividerState *s)
308
+{
309
+ return divide_by_reg_divisor(s) / 2;
310
+}
311
+
312
+static uint32_t shift_by_reg_divisor(NPCM7xxClockDividerState *s)
313
+{
314
+ return clock_get_hz(s->clock_in) >>
315
+ extract32(s->clk->regs[s->reg], s->offset, s->len);
316
+}
317
+
318
+static NPCM7xxClockPLL find_pll_by_reg(enum NPCM7xxCLKRegisters reg)
319
+{
320
+ switch (reg) {
321
+ case NPCM7XX_CLK_PLLCON0:
322
+ return NPCM7XX_CLOCK_PLL0;
323
+ case NPCM7XX_CLK_PLLCON1:
324
+ return NPCM7XX_CLOCK_PLL1;
325
+ case NPCM7XX_CLK_PLLCON2:
326
+ return NPCM7XX_CLOCK_PLL2;
327
+ case NPCM7XX_CLK_PLLCONG:
328
+ return NPCM7XX_CLOCK_PLLG;
329
+ default:
330
+ g_assert_not_reached();
331
+ }
332
+}
333
+
334
+static void npcm7xx_clk_update_all_plls(NPCM7xxCLKState *clk)
335
+{
336
+ int i;
337
+
338
+ for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
339
+ npcm7xx_clk_update_pll(&clk->plls[i]);
340
+ }
341
+}
342
+
343
+static void npcm7xx_clk_update_all_sels(NPCM7xxCLKState *clk)
344
+{
345
+ int i;
346
+
347
+ for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
348
+ npcm7xx_clk_update_sel(&clk->sels[i]);
349
+ }
350
+}
351
+
352
+static void npcm7xx_clk_update_all_dividers(NPCM7xxCLKState *clk)
353
+{
354
+ int i;
355
+
356
+ for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
357
+ npcm7xx_clk_update_divider(&clk->dividers[i]);
358
+ }
359
+}
360
+
361
+static void npcm7xx_clk_update_all_clocks(NPCM7xxCLKState *clk)
362
+{
363
+ clock_update_hz(clk->clkref, NPCM7XX_CLOCK_REF_HZ);
364
+ npcm7xx_clk_update_all_plls(clk);
365
+ npcm7xx_clk_update_all_sels(clk);
366
+ npcm7xx_clk_update_all_dividers(clk);
367
+}
368
+
369
+/* Types of clock sources. */
370
+typedef enum ClockSrcType {
371
+ CLKSRC_REF,
372
+ CLKSRC_PLL,
373
+ CLKSRC_SEL,
374
+ CLKSRC_DIV,
375
+} ClockSrcType;
376
+
377
+typedef struct PLLInitInfo {
378
+ const char *name;
379
+ ClockSrcType src_type;
380
+ int src_index;
381
+ int reg;
382
+ const char *public_name;
383
+} PLLInitInfo;
384
+
385
+typedef struct SELInitInfo {
386
+ const char *name;
387
+ uint8_t input_size;
388
+ ClockSrcType src_type[NPCM7XX_CLK_SEL_MAX_INPUT];
389
+ int src_index[NPCM7XX_CLK_SEL_MAX_INPUT];
390
+ int offset;
391
+ int len;
392
+ const char *public_name;
393
+} SELInitInfo;
394
+
395
+typedef struct DividerInitInfo {
396
+ const char *name;
397
+ ClockSrcType src_type;
398
+ int src_index;
399
+ uint32_t (*divide)(NPCM7xxClockDividerState *s);
400
+ int reg; /* not used when type == CONSTANT */
401
+ int offset; /* not used when type == CONSTANT */
402
+ int len; /* not used when type == CONSTANT */
403
+ int divisor; /* used only when type == CONSTANT */
404
+ const char *public_name;
405
+} DividerInitInfo;
406
+
407
+static const PLLInitInfo pll_init_info_list[] = {
408
+ [NPCM7XX_CLOCK_PLL0] = {
409
+ .name = "pll0",
410
+ .src_type = CLKSRC_REF,
411
+ .reg = NPCM7XX_CLK_PLLCON0,
412
+ },
413
+ [NPCM7XX_CLOCK_PLL1] = {
414
+ .name = "pll1",
415
+ .src_type = CLKSRC_REF,
416
+ .reg = NPCM7XX_CLK_PLLCON1,
417
+ },
418
+ [NPCM7XX_CLOCK_PLL2] = {
419
+ .name = "pll2",
420
+ .src_type = CLKSRC_REF,
421
+ .reg = NPCM7XX_CLK_PLLCON2,
422
+ },
423
+ [NPCM7XX_CLOCK_PLLG] = {
424
+ .name = "pllg",
425
+ .src_type = CLKSRC_REF,
426
+ .reg = NPCM7XX_CLK_PLLCONG,
427
+ },
145
+};
428
+};
146
+
429
+
147
static bool cmsdk_apb_watchdog_intstatus(CMSDKAPBWatchdog *s)
430
+static const SELInitInfo sel_init_info_list[] = {
431
+ [NPCM7XX_CLOCK_PIXCKSEL] = {
432
+ .name = "pixcksel",
433
+ .input_size = 2,
434
+ .src_type = {CLKSRC_PLL, CLKSRC_REF},
435
+ .src_index = {NPCM7XX_CLOCK_PLLG, 0},
436
+ .offset = 5,
437
+ .len = 1,
438
+ .public_name = "pixel-clock",
439
+ },
440
+ [NPCM7XX_CLOCK_MCCKSEL] = {
441
+ .name = "mccksel",
442
+ .input_size = 4,
443
+ .src_type = {CLKSRC_DIV, CLKSRC_REF, CLKSRC_REF,
444
+ /*MCBPCK, shouldn't be used in normal operation*/
445
+ CLKSRC_REF},
446
+ .src_index = {NPCM7XX_CLOCK_PLL1D2, 0, 0, 0},
447
+ .offset = 12,
448
+ .len = 2,
449
+ .public_name = "mc-phy-clock",
450
+ },
451
+ [NPCM7XX_CLOCK_CPUCKSEL] = {
452
+ .name = "cpucksel",
453
+ .input_size = 4,
454
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF,
455
+ /*SYSBPCK, shouldn't be used in normal operation*/
456
+ CLKSRC_REF},
457
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0, 0},
458
+ .offset = 0,
459
+ .len = 2,
460
+ .public_name = "system-clock",
461
+ },
462
+ [NPCM7XX_CLOCK_CLKOUTSEL] = {
463
+ .name = "clkoutsel",
464
+ .input_size = 5,
465
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF,
466
+ CLKSRC_PLL, CLKSRC_DIV},
467
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
468
+ NPCM7XX_CLOCK_PLLG, NPCM7XX_CLOCK_PLL2D2},
469
+ .offset = 18,
470
+ .len = 3,
471
+ .public_name = "tock",
472
+ },
473
+ [NPCM7XX_CLOCK_UARTCKSEL] = {
474
+ .name = "uartcksel",
475
+ .input_size = 4,
476
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
477
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
478
+ NPCM7XX_CLOCK_PLL2D2},
479
+ .offset = 8,
480
+ .len = 2,
481
+ },
482
+ [NPCM7XX_CLOCK_TIMCKSEL] = {
483
+ .name = "timcksel",
484
+ .input_size = 4,
485
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
486
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
487
+ NPCM7XX_CLOCK_PLL2D2},
488
+ .offset = 14,
489
+ .len = 2,
490
+ },
491
+ [NPCM7XX_CLOCK_SDCKSEL] = {
492
+ .name = "sdcksel",
493
+ .input_size = 4,
494
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
495
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
496
+ NPCM7XX_CLOCK_PLL2D2},
497
+ .offset = 6,
498
+ .len = 2,
499
+ },
500
+ [NPCM7XX_CLOCK_GFXMSEL] = {
501
+ .name = "gfxmksel",
502
+ .input_size = 2,
503
+ .src_type = {CLKSRC_REF, CLKSRC_PLL},
504
+ .src_index = {0, NPCM7XX_CLOCK_PLL2},
505
+ .offset = 21,
506
+ .len = 1,
507
+ },
508
+ [NPCM7XX_CLOCK_SUCKSEL] = {
509
+ .name = "sucksel",
510
+ .input_size = 4,
511
+ .src_type = {CLKSRC_PLL, CLKSRC_DIV, CLKSRC_REF, CLKSRC_DIV},
512
+ .src_index = {NPCM7XX_CLOCK_PLL0, NPCM7XX_CLOCK_PLL1D2, 0,
513
+ NPCM7XX_CLOCK_PLL2D2},
514
+ .offset = 10,
515
+ .len = 2,
516
+ },
517
+};
518
+
519
+static const DividerInitInfo divider_init_info_list[] = {
520
+ [NPCM7XX_CLOCK_PLL1D2] = {
521
+ .name = "pll1d2",
522
+ .src_type = CLKSRC_PLL,
523
+ .src_index = NPCM7XX_CLOCK_PLL1,
524
+ .divide = divide_by_constant,
525
+ .divisor = 2,
526
+ },
527
+ [NPCM7XX_CLOCK_PLL2D2] = {
528
+ .name = "pll2d2",
529
+ .src_type = CLKSRC_PLL,
530
+ .src_index = NPCM7XX_CLOCK_PLL2,
531
+ .divide = divide_by_constant,
532
+ .divisor = 2,
533
+ },
534
+ [NPCM7XX_CLOCK_MC_DIVIDER] = {
535
+ .name = "mc-divider",
536
+ .src_type = CLKSRC_SEL,
537
+ .src_index = NPCM7XX_CLOCK_MCCKSEL,
538
+ .divide = divide_by_constant,
539
+ .divisor = 2,
540
+ .public_name = "mc-clock"
541
+ },
542
+ [NPCM7XX_CLOCK_AXI_DIVIDER] = {
543
+ .name = "axi-divider",
544
+ .src_type = CLKSRC_SEL,
545
+ .src_index = NPCM7XX_CLOCK_CPUCKSEL,
546
+ .divide = shift_by_reg_divisor,
547
+ .reg = NPCM7XX_CLK_CLKDIV1,
548
+ .offset = 0,
549
+ .len = 1,
550
+ .public_name = "clk2"
551
+ },
552
+ [NPCM7XX_CLOCK_AHB_DIVIDER] = {
553
+ .name = "ahb-divider",
554
+ .src_type = CLKSRC_DIV,
555
+ .src_index = NPCM7XX_CLOCK_AXI_DIVIDER,
556
+ .divide = divide_by_reg_divisor,
557
+ .reg = NPCM7XX_CLK_CLKDIV1,
558
+ .offset = 26,
559
+ .len = 2,
560
+ .public_name = "clk4"
561
+ },
562
+ [NPCM7XX_CLOCK_AHB3_DIVIDER] = {
563
+ .name = "ahb3-divider",
564
+ .src_type = CLKSRC_DIV,
565
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
566
+ .divide = divide_by_reg_divisor,
567
+ .reg = NPCM7XX_CLK_CLKDIV1,
568
+ .offset = 6,
569
+ .len = 5,
570
+ .public_name = "ahb3-spi3-clock"
571
+ },
572
+ [NPCM7XX_CLOCK_SPI0_DIVIDER] = {
573
+ .name = "spi0-divider",
574
+ .src_type = CLKSRC_DIV,
575
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
576
+ .divide = divide_by_reg_divisor,
577
+ .reg = NPCM7XX_CLK_CLKDIV3,
578
+ .offset = 6,
579
+ .len = 5,
580
+ .public_name = "spi0-clock",
581
+ },
582
+ [NPCM7XX_CLOCK_SPIX_DIVIDER] = {
583
+ .name = "spix-divider",
584
+ .src_type = CLKSRC_DIV,
585
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
586
+ .divide = divide_by_reg_divisor,
587
+ .reg = NPCM7XX_CLK_CLKDIV3,
588
+ .offset = 1,
589
+ .len = 5,
590
+ .public_name = "spix-clock",
591
+ },
592
+ [NPCM7XX_CLOCK_APB1_DIVIDER] = {
593
+ .name = "apb1-divider",
594
+ .src_type = CLKSRC_DIV,
595
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
596
+ .divide = shift_by_reg_divisor,
597
+ .reg = NPCM7XX_CLK_CLKDIV2,
598
+ .offset = 24,
599
+ .len = 2,
600
+ .public_name = "apb1-clock",
601
+ },
602
+ [NPCM7XX_CLOCK_APB2_DIVIDER] = {
603
+ .name = "apb2-divider",
604
+ .src_type = CLKSRC_DIV,
605
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
606
+ .divide = shift_by_reg_divisor,
607
+ .reg = NPCM7XX_CLK_CLKDIV2,
608
+ .offset = 26,
609
+ .len = 2,
610
+ .public_name = "apb2-clock",
611
+ },
612
+ [NPCM7XX_CLOCK_APB3_DIVIDER] = {
613
+ .name = "apb3-divider",
614
+ .src_type = CLKSRC_DIV,
615
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
616
+ .divide = shift_by_reg_divisor,
617
+ .reg = NPCM7XX_CLK_CLKDIV2,
618
+ .offset = 28,
619
+ .len = 2,
620
+ .public_name = "apb3-clock",
621
+ },
622
+ [NPCM7XX_CLOCK_APB4_DIVIDER] = {
623
+ .name = "apb4-divider",
624
+ .src_type = CLKSRC_DIV,
625
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
626
+ .divide = shift_by_reg_divisor,
627
+ .reg = NPCM7XX_CLK_CLKDIV2,
628
+ .offset = 30,
629
+ .len = 2,
630
+ .public_name = "apb4-clock",
631
+ },
632
+ [NPCM7XX_CLOCK_APB5_DIVIDER] = {
633
+ .name = "apb5-divider",
634
+ .src_type = CLKSRC_DIV,
635
+ .src_index = NPCM7XX_CLOCK_AHB_DIVIDER,
636
+ .divide = shift_by_reg_divisor,
637
+ .reg = NPCM7XX_CLK_CLKDIV2,
638
+ .offset = 22,
639
+ .len = 2,
640
+ .public_name = "apb5-clock",
641
+ },
642
+ [NPCM7XX_CLOCK_CLKOUT_DIVIDER] = {
643
+ .name = "clkout-divider",
644
+ .src_type = CLKSRC_SEL,
645
+ .src_index = NPCM7XX_CLOCK_CLKOUTSEL,
646
+ .divide = divide_by_reg_divisor,
647
+ .reg = NPCM7XX_CLK_CLKDIV2,
648
+ .offset = 16,
649
+ .len = 5,
650
+ .public_name = "clkout",
651
+ },
652
+ [NPCM7XX_CLOCK_UART_DIVIDER] = {
653
+ .name = "uart-divider",
654
+ .src_type = CLKSRC_SEL,
655
+ .src_index = NPCM7XX_CLOCK_UARTCKSEL,
656
+ .divide = divide_by_reg_divisor,
657
+ .reg = NPCM7XX_CLK_CLKDIV1,
658
+ .offset = 16,
659
+ .len = 5,
660
+ .public_name = "uart-clock",
661
+ },
662
+ [NPCM7XX_CLOCK_TIMER_DIVIDER] = {
663
+ .name = "timer-divider",
664
+ .src_type = CLKSRC_SEL,
665
+ .src_index = NPCM7XX_CLOCK_TIMCKSEL,
666
+ .divide = divide_by_reg_divisor,
667
+ .reg = NPCM7XX_CLK_CLKDIV1,
668
+ .offset = 21,
669
+ .len = 5,
670
+ .public_name = "timer-clock",
671
+ },
672
+ [NPCM7XX_CLOCK_ADC_DIVIDER] = {
673
+ .name = "adc-divider",
674
+ .src_type = CLKSRC_DIV,
675
+ .src_index = NPCM7XX_CLOCK_TIMER_DIVIDER,
676
+ .divide = shift_by_reg_divisor,
677
+ .reg = NPCM7XX_CLK_CLKDIV1,
678
+ .offset = 28,
679
+ .len = 3,
680
+ .public_name = "adc-clock",
681
+ },
682
+ [NPCM7XX_CLOCK_MMC_DIVIDER] = {
683
+ .name = "mmc-divider",
684
+ .src_type = CLKSRC_SEL,
685
+ .src_index = NPCM7XX_CLOCK_SDCKSEL,
686
+ .divide = divide_by_reg_divisor,
687
+ .reg = NPCM7XX_CLK_CLKDIV1,
688
+ .offset = 11,
689
+ .len = 5,
690
+ .public_name = "mmc-clock",
691
+ },
692
+ [NPCM7XX_CLOCK_SDHC_DIVIDER] = {
693
+ .name = "sdhc-divider",
694
+ .src_type = CLKSRC_SEL,
695
+ .src_index = NPCM7XX_CLOCK_SDCKSEL,
696
+ .divide = divide_by_reg_divisor_times_2,
697
+ .reg = NPCM7XX_CLK_CLKDIV2,
698
+ .offset = 0,
699
+ .len = 4,
700
+ .public_name = "sdhc-clock",
701
+ },
702
+ [NPCM7XX_CLOCK_GFXM_DIVIDER] = {
703
+ .name = "gfxm-divider",
704
+ .src_type = CLKSRC_SEL,
705
+ .src_index = NPCM7XX_CLOCK_GFXMSEL,
706
+ .divide = divide_by_constant,
707
+ .divisor = 3,
708
+ .public_name = "gfxm-clock",
709
+ },
710
+ [NPCM7XX_CLOCK_UTMI_DIVIDER] = {
711
+ .name = "utmi-divider",
712
+ .src_type = CLKSRC_SEL,
713
+ .src_index = NPCM7XX_CLOCK_SUCKSEL,
714
+ .divide = divide_by_reg_divisor,
715
+ .reg = NPCM7XX_CLK_CLKDIV2,
716
+ .offset = 8,
717
+ .len = 5,
718
+ .public_name = "utmi-clock",
719
+ },
720
+};
721
+
722
+static void npcm7xx_clk_pll_init(Object *obj)
723
+{
724
+ NPCM7xxClockPLLState *pll = NPCM7XX_CLOCK_PLL(obj);
725
+
726
+ pll->clock_in = qdev_init_clock_in(DEVICE(pll), "clock-in",
727
+ npcm7xx_clk_update_pll, pll);
728
+ pll->clock_out = qdev_init_clock_out(DEVICE(pll), "clock-out");
729
+}
730
+
731
+static void npcm7xx_clk_sel_init(Object *obj)
732
+{
733
+ int i;
734
+ NPCM7xxClockSELState *sel = NPCM7XX_CLOCK_SEL(obj);
735
+
736
+ for (i = 0; i < NPCM7XX_CLK_SEL_MAX_INPUT; ++i) {
737
+ sel->clock_in[i] = qdev_init_clock_in(DEVICE(sel),
738
+ g_strdup_printf("clock-in[%d]", i),
739
+ npcm7xx_clk_update_sel, sel);
740
+ }
741
+ sel->clock_out = qdev_init_clock_out(DEVICE(sel), "clock-out");
742
+}
743
+static void npcm7xx_clk_divider_init(Object *obj)
744
+{
745
+ NPCM7xxClockDividerState *div = NPCM7XX_CLOCK_DIVIDER(obj);
746
+
747
+ div->clock_in = qdev_init_clock_in(DEVICE(div), "clock-in",
748
+ npcm7xx_clk_update_divider, div);
749
+ div->clock_out = qdev_init_clock_out(DEVICE(div), "clock-out");
750
+}
751
+
752
+static void npcm7xx_init_clock_pll(NPCM7xxClockPLLState *pll,
753
+ NPCM7xxCLKState *clk, const PLLInitInfo *init_info)
754
+{
755
+ pll->name = init_info->name;
756
+ pll->clk = clk;
757
+ pll->reg = init_info->reg;
758
+ if (init_info->public_name != NULL) {
759
+ qdev_alias_clock(DEVICE(pll), "clock-out", DEVICE(clk),
760
+ init_info->public_name);
761
+ }
762
+}
763
+
764
+static void npcm7xx_init_clock_sel(NPCM7xxClockSELState *sel,
765
+ NPCM7xxCLKState *clk, const SELInitInfo *init_info)
766
+{
767
+ int input_size = init_info->input_size;
768
+
769
+ sel->name = init_info->name;
770
+ sel->clk = clk;
771
+ sel->input_size = init_info->input_size;
772
+ g_assert(input_size <= NPCM7XX_CLK_SEL_MAX_INPUT);
773
+ sel->offset = init_info->offset;
774
+ sel->len = init_info->len;
775
+ if (init_info->public_name != NULL) {
776
+ qdev_alias_clock(DEVICE(sel), "clock-out", DEVICE(clk),
777
+ init_info->public_name);
778
+ }
779
+}
780
+
781
+static void npcm7xx_init_clock_divider(NPCM7xxClockDividerState *div,
782
+ NPCM7xxCLKState *clk, const DividerInitInfo *init_info)
783
+{
784
+ div->name = init_info->name;
785
+ div->clk = clk;
786
+
787
+ div->divide = init_info->divide;
788
+ if (div->divide == divide_by_constant) {
789
+ div->divisor = init_info->divisor;
790
+ } else {
791
+ div->reg = init_info->reg;
792
+ div->offset = init_info->offset;
793
+ div->len = init_info->len;
794
+ }
795
+ if (init_info->public_name != NULL) {
796
+ qdev_alias_clock(DEVICE(div), "clock-out", DEVICE(clk),
797
+ init_info->public_name);
798
+ }
799
+}
800
+
801
+static Clock *npcm7xx_get_clock(NPCM7xxCLKState *clk, ClockSrcType type,
802
+ int index)
803
+{
804
+ switch (type) {
805
+ case CLKSRC_REF:
806
+ return clk->clkref;
807
+ case CLKSRC_PLL:
808
+ return clk->plls[index].clock_out;
809
+ case CLKSRC_SEL:
810
+ return clk->sels[index].clock_out;
811
+ case CLKSRC_DIV:
812
+ return clk->dividers[index].clock_out;
813
+ default:
814
+ g_assert_not_reached();
815
+ }
816
+}
817
+
818
+static void npcm7xx_connect_clocks(NPCM7xxCLKState *clk)
819
+{
820
+ int i, j;
821
+ Clock *src;
822
+
823
+ for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
824
+ src = npcm7xx_get_clock(clk, pll_init_info_list[i].src_type,
825
+ pll_init_info_list[i].src_index);
826
+ clock_set_source(clk->plls[i].clock_in, src);
827
+ }
828
+ for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
829
+ for (j = 0; j < sel_init_info_list[i].input_size; ++j) {
830
+ src = npcm7xx_get_clock(clk, sel_init_info_list[i].src_type[j],
831
+ sel_init_info_list[i].src_index[j]);
832
+ clock_set_source(clk->sels[i].clock_in[j], src);
833
+ }
834
+ }
835
+ for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
836
+ src = npcm7xx_get_clock(clk, divider_init_info_list[i].src_type,
837
+ divider_init_info_list[i].src_index);
838
+ clock_set_source(clk->dividers[i].clock_in, src);
839
+ }
840
+}
841
+
842
static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
148
{
843
{
149
/* Return masked interrupt status */
844
uint32_t reg = offset / sizeof(uint32_t);
150
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_update(CMSDKAPBWatchdog *s)
845
@@ -XXX,XX +XXX,XX @@ static uint64_t npcm7xx_clk_read(void *opaque, hwaddr offset, unsigned size)
151
bool wdogres;
846
*
152
847
* The 4 LSBs are always zero: (1e9 / 640) << 4 = 25000000.
153
if (s->itcr) {
848
*/
154
+ /*
849
- value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_TIMER_REF_HZ;
155
+ * Not checking that !s->is_luminary since s->itcr can't be written
850
+ value = (((now_ns - s->ref_ns) / 640) << 4) % NPCM7XX_CLOCK_REF_HZ;
156
+ * when s->is_luminary in the first place.
157
+ */
158
wdogint = s->itop & R_WDOGITOP_WDOGINT_MASK;
159
wdogres = s->itop & R_WDOGITOP_WDOGRES_MASK;
160
} else {
161
@@ -XXX,XX +XXX,XX @@ static uint64_t cmsdk_apb_watchdog_read(void *opaque, hwaddr offset,
162
r = s->lock;
163
break;
851
break;
164
case A_WDOGITCR:
852
165
+ if (s->is_luminary) {
853
default:
166
+ goto bad_offset;
854
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_write(void *opaque, hwaddr offset,
855
value |= (value & PLLCON_LOKS);
856
}
857
}
858
+ /* Only update PLL when it is locked. */
859
+ if (value & PLLCON_LOKI) {
860
+ npcm7xx_clk_update_pll(&s->plls[find_pll_by_reg(reg)]);
167
+ }
861
+ }
168
r = s->itcr;
862
+ break;
863
+
864
+ case NPCM7XX_CLK_CLKSEL:
865
+ npcm7xx_clk_update_all_sels(s);
866
+ break;
867
+
868
+ case NPCM7XX_CLK_CLKDIV1:
869
+ case NPCM7XX_CLK_CLKDIV2:
870
+ case NPCM7XX_CLK_CLKDIV3:
871
+ npcm7xx_clk_update_all_dividers(s);
169
break;
872
break;
170
case A_PID4 ... A_CID3:
873
171
- r = watchdog_id[(offset - A_PID4) / 4];
874
case NPCM7XX_CLK_CNTR25M:
172
+ r = s->id[(offset - A_PID4) / 4];
875
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
173
break;
876
case RESET_TYPE_COLD:
174
case A_WDOGINTCLR:
877
memcpy(s->regs, cold_reset_values, sizeof(cold_reset_values));
175
case A_WDOGITOP:
878
s->ref_ns = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
176
+ if (s->is_luminary) {
879
+ npcm7xx_clk_update_all_clocks(s);
177
+ goto bad_offset;
880
return;
881
}
882
883
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_enter_reset(Object *obj, ResetType type)
884
__func__, type);
885
}
886
887
+static void npcm7xx_clk_init_clock_hierarchy(NPCM7xxCLKState *s)
888
+{
889
+ int i;
890
+
891
+ s->clkref = qdev_init_clock_in(DEVICE(s), "clkref", NULL, NULL);
892
+
893
+ /* First pass: init all converter modules */
894
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(pll_init_info_list) != NPCM7XX_CLOCK_NR_PLLS);
895
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(sel_init_info_list) != NPCM7XX_CLOCK_NR_SELS);
896
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(divider_init_info_list)
897
+ != NPCM7XX_CLOCK_NR_DIVIDERS);
898
+ for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
899
+ object_initialize_child(OBJECT(s), pll_init_info_list[i].name,
900
+ &s->plls[i], TYPE_NPCM7XX_CLOCK_PLL);
901
+ npcm7xx_init_clock_pll(&s->plls[i], s,
902
+ &pll_init_info_list[i]);
903
+ }
904
+ for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
905
+ object_initialize_child(OBJECT(s), sel_init_info_list[i].name,
906
+ &s->sels[i], TYPE_NPCM7XX_CLOCK_SEL);
907
+ npcm7xx_init_clock_sel(&s->sels[i], s,
908
+ &sel_init_info_list[i]);
909
+ }
910
+ for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
911
+ object_initialize_child(OBJECT(s), divider_init_info_list[i].name,
912
+ &s->dividers[i], TYPE_NPCM7XX_CLOCK_DIVIDER);
913
+ npcm7xx_init_clock_divider(&s->dividers[i], s,
914
+ &divider_init_info_list[i]);
915
+ }
916
+
917
+ /* Second pass: connect converter modules */
918
+ npcm7xx_connect_clocks(s);
919
+
920
+ clock_update_hz(s->clkref, NPCM7XX_CLOCK_REF_HZ);
921
+}
922
+
923
static void npcm7xx_clk_init(Object *obj)
924
{
925
NPCM7xxCLKState *s = NPCM7XX_CLK(obj);
926
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj)
927
memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
928
TYPE_NPCM7XX_CLK, 4 * KiB);
929
sysbus_init_mmio(&s->parent, &s->iomem);
930
- qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
931
- NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
932
}
933
934
-static const VMStateDescription vmstate_npcm7xx_clk = {
935
- .name = "npcm7xx-clk",
936
+static int npcm7xx_clk_post_load(void *opaque, int version_id)
937
+{
938
+ if (version_id >= 1) {
939
+ NPCM7xxCLKState *clk = opaque;
940
+
941
+ npcm7xx_clk_update_all_clocks(clk);
942
+ }
943
+
944
+ return 0;
945
+}
946
+
947
+static void npcm7xx_clk_realize(DeviceState *dev, Error **errp)
948
+{
949
+ int i;
950
+ NPCM7xxCLKState *s = NPCM7XX_CLK(dev);
951
+
952
+ qdev_init_gpio_in_named(DEVICE(s), npcm7xx_clk_perform_watchdog_reset,
953
+ NPCM7XX_WATCHDOG_RESET_GPIO_IN, NPCM7XX_NR_WATCHDOGS);
954
+ npcm7xx_clk_init_clock_hierarchy(s);
955
+
956
+ /* Realize child devices */
957
+ for (i = 0; i < NPCM7XX_CLOCK_NR_PLLS; ++i) {
958
+ if (!qdev_realize(DEVICE(&s->plls[i]), NULL, errp)) {
959
+ return;
178
+ }
960
+ }
179
qemu_log_mask(LOG_GUEST_ERROR,
961
+ }
180
"CMSDK APB watchdog read: read of WO offset %x\n",
962
+ for (i = 0; i < NPCM7XX_CLOCK_NR_SELS; ++i) {
181
(int)offset);
963
+ if (!qdev_realize(DEVICE(&s->sels[i]), NULL, errp)) {
182
r = 0;
964
+ return;
183
break;
184
+ case A_WDOGTEST:
185
+ if (!s->is_luminary) {
186
+ goto bad_offset;
187
+ }
965
+ }
188
+ qemu_log_mask(LOG_UNIMP,
966
+ }
189
+ "Luminary watchdog read: stall not implemented\n");
967
+ for (i = 0; i < NPCM7XX_CLOCK_NR_DIVIDERS; ++i) {
190
+ r = 0;
968
+ if (!qdev_realize(DEVICE(&s->dividers[i]), NULL, errp)) {
191
+ break;
969
+ return;
192
default:
193
+bad_offset:
194
qemu_log_mask(LOG_GUEST_ERROR,
195
"CMSDK APB watchdog read: bad offset %x\n", (int)offset);
196
r = 0;
197
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_write(void *opaque, hwaddr offset,
198
ptimer_run(s->timer, 0);
199
break;
200
case A_WDOGCONTROL:
201
+ if (s->is_luminary && 0 != (R_WDOGCONTROL_INTEN_MASK & s->control)) {
202
+ /*
203
+ * The Luminary version of this device ignores writes to
204
+ * this register after the guest has enabled interrupts
205
+ * (so they can only be disabled again via reset).
206
+ */
207
+ break;
208
+ }
970
+ }
209
s->control = value & R_WDOGCONTROL_VALID_MASK;
971
+ }
210
cmsdk_apb_watchdog_update(s);
972
+}
211
break;
973
+
212
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_write(void *opaque, hwaddr offset,
974
+static const VMStateDescription vmstate_npcm7xx_clk_pll = {
213
s->lock = (value != WDOG_UNLOCK_VALUE);
975
+ .name = "npcm7xx-clock-pll",
214
break;
976
.version_id = 0,
215
case A_WDOGITCR:
977
.minimum_version_id = 0,
216
+ if (s->is_luminary) {
978
- .fields = (VMStateField[]) {
217
+ goto bad_offset;
979
- VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
218
+ }
980
- VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
219
s->itcr = value & R_WDOGITCR_VALID_MASK;
981
+ .fields = (VMStateField[]) {
220
cmsdk_apb_watchdog_update(s);
982
+ VMSTATE_CLOCK(clock_in, NPCM7xxClockPLLState),
221
break;
983
VMSTATE_END_OF_LIST(),
222
case A_WDOGITOP:
984
},
223
+ if (s->is_luminary) {
985
};
224
+ goto bad_offset;
986
225
+ }
987
+static const VMStateDescription vmstate_npcm7xx_clk_sel = {
226
s->itop = value & R_WDOGITOP_VALID_MASK;
988
+ .name = "npcm7xx-clock-sel",
227
cmsdk_apb_watchdog_update(s);
989
+ .version_id = 0,
228
break;
990
+ .minimum_version_id = 0,
229
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_write(void *opaque, hwaddr offset,
991
+ .fields = (VMStateField[]) {
230
"CMSDK APB watchdog write: write to RO offset 0x%x\n",
992
+ VMSTATE_ARRAY_OF_POINTER_TO_STRUCT(clock_in, NPCM7xxClockSELState,
231
(int)offset);
993
+ NPCM7XX_CLK_SEL_MAX_INPUT, 0, vmstate_clock, Clock),
232
break;
994
+ VMSTATE_END_OF_LIST(),
233
+ case A_WDOGTEST:
995
+ },
234
+ if (!s->is_luminary) {
996
+};
235
+ goto bad_offset;
997
+
236
+ }
998
+static const VMStateDescription vmstate_npcm7xx_clk_divider = {
237
+ qemu_log_mask(LOG_UNIMP,
999
+ .name = "npcm7xx-clock-divider",
238
+ "Luminary watchdog write: stall not implemented\n");
1000
+ .version_id = 0,
239
+ break;
1001
+ .minimum_version_id = 0,
240
default:
1002
+ .fields = (VMStateField[]) {
241
+bad_offset:
1003
+ VMSTATE_CLOCK(clock_in, NPCM7xxClockDividerState),
242
qemu_log_mask(LOG_GUEST_ERROR,
1004
+ VMSTATE_END_OF_LIST(),
243
"CMSDK APB watchdog write: bad offset 0x%x\n",
1005
+ },
244
(int)offset);
1006
+};
245
@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_init(Object *obj)
1007
+
246
s, "cmsdk-apb-watchdog", 0x1000);
1008
+static const VMStateDescription vmstate_npcm7xx_clk = {
247
sysbus_init_mmio(sbd, &s->iomem);
1009
+ .name = "npcm7xx-clk",
248
sysbus_init_irq(sbd, &s->wdogint);
1010
+ .version_id = 1,
249
+
1011
+ .minimum_version_id = 1,
250
+ s->is_luminary = false;
1012
+ .post_load = npcm7xx_clk_post_load,
251
+ s->id = cmsdk_apb_watchdog_id;
1013
+ .fields = (VMStateField[]) {
1014
+ VMSTATE_UINT32_ARRAY(regs, NPCM7xxCLKState, NPCM7XX_CLK_NR_REGS),
1015
+ VMSTATE_INT64(ref_ns, NPCM7xxCLKState),
1016
+ VMSTATE_CLOCK(clkref, NPCM7xxCLKState),
1017
+ VMSTATE_END_OF_LIST(),
1018
+ },
1019
+};
1020
+
1021
+static void npcm7xx_clk_pll_class_init(ObjectClass *klass, void *data)
1022
+{
1023
+ DeviceClass *dc = DEVICE_CLASS(klass);
1024
+
1025
+ dc->desc = "NPCM7xx Clock PLL Module";
1026
+ dc->vmsd = &vmstate_npcm7xx_clk_pll;
1027
+}
1028
+
1029
+static void npcm7xx_clk_sel_class_init(ObjectClass *klass, void *data)
1030
+{
1031
+ DeviceClass *dc = DEVICE_CLASS(klass);
1032
+
1033
+ dc->desc = "NPCM7xx Clock SEL Module";
1034
+ dc->vmsd = &vmstate_npcm7xx_clk_sel;
1035
+}
1036
+
1037
+static void npcm7xx_clk_divider_class_init(ObjectClass *klass, void *data)
1038
+{
1039
+ DeviceClass *dc = DEVICE_CLASS(klass);
1040
+
1041
+ dc->desc = "NPCM7xx Clock Divider Module";
1042
+ dc->vmsd = &vmstate_npcm7xx_clk_divider;
1043
+}
1044
+
1045
static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
1046
{
1047
ResettableClass *rc = RESETTABLE_CLASS(klass);
1048
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_class_init(ObjectClass *klass, void *data)
1049
1050
dc->desc = "NPCM7xx Clock Control Registers";
1051
dc->vmsd = &vmstate_npcm7xx_clk;
1052
+ dc->realize = npcm7xx_clk_realize;
1053
rc->phases.enter = npcm7xx_clk_enter_reset;
252
}
1054
}
253
1055
254
static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp)
1056
+static const TypeInfo npcm7xx_clk_pll_info = {
255
@@ -XXX,XX +XXX,XX @@ static const TypeInfo cmsdk_apb_watchdog_info = {
1057
+ .name = TYPE_NPCM7XX_CLOCK_PLL,
256
.class_init = cmsdk_apb_watchdog_class_init,
1058
+ .parent = TYPE_DEVICE,
257
};
1059
+ .instance_size = sizeof(NPCM7xxClockPLLState),
258
1060
+ .instance_init = npcm7xx_clk_pll_init,
259
+static void luminary_watchdog_init(Object *obj)
1061
+ .class_init = npcm7xx_clk_pll_class_init,
260
+{
261
+ CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(obj);
262
+
263
+ s->is_luminary = true;
264
+ s->id = luminary_watchdog_id;
265
+}
266
+
267
+static const TypeInfo luminary_watchdog_info = {
268
+ .name = TYPE_LUMINARY_WATCHDOG,
269
+ .parent = TYPE_CMSDK_APB_WATCHDOG,
270
+ .instance_init = luminary_watchdog_init
271
+};
1062
+};
272
+
1063
+
273
static void cmsdk_apb_watchdog_register_types(void)
1064
+static const TypeInfo npcm7xx_clk_sel_info = {
1065
+ .name = TYPE_NPCM7XX_CLOCK_SEL,
1066
+ .parent = TYPE_DEVICE,
1067
+ .instance_size = sizeof(NPCM7xxClockSELState),
1068
+ .instance_init = npcm7xx_clk_sel_init,
1069
+ .class_init = npcm7xx_clk_sel_class_init,
1070
+};
1071
+
1072
+static const TypeInfo npcm7xx_clk_divider_info = {
1073
+ .name = TYPE_NPCM7XX_CLOCK_DIVIDER,
1074
+ .parent = TYPE_DEVICE,
1075
+ .instance_size = sizeof(NPCM7xxClockDividerState),
1076
+ .instance_init = npcm7xx_clk_divider_init,
1077
+ .class_init = npcm7xx_clk_divider_class_init,
1078
+};
1079
+
1080
static const TypeInfo npcm7xx_clk_info = {
1081
.name = TYPE_NPCM7XX_CLK,
1082
.parent = TYPE_SYS_BUS_DEVICE,
1083
@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_clk_info = {
1084
1085
static void npcm7xx_clk_register_type(void)
274
{
1086
{
275
type_register_static(&cmsdk_apb_watchdog_info);
1087
+ type_register_static(&npcm7xx_clk_pll_info);
276
+ type_register_static(&luminary_watchdog_info);
1088
+ type_register_static(&npcm7xx_clk_sel_info);
1089
+ type_register_static(&npcm7xx_clk_divider_info);
1090
type_register_static(&npcm7xx_clk_info);
277
}
1091
}
278
1092
type_init(npcm7xx_clk_register_type);
279
type_init(cmsdk_apb_watchdog_register_types);
280
--
1093
--
281
2.20.1
1094
2.20.1
282
1095
283
1096
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Hao Wu <wuhaotsh@google.com>
2
2
3
We do not need an out-of-line helper for manipulating bits in pstate.
3
This patch makes NPCM7XX Timer to use a the timer clock generated by the
4
While changing things, share the implementation of gen_ss_advance.
4
CLK module instead of the magic number TIMER_REF_HZ.
5
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
7
Message-id: 20190301200501.16533-6-richard.henderson@linaro.org
7
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
8
Signed-off-by: Hao Wu <wuhaotsh@google.com>
9
Message-id: 20210108190945.949196-3-wuhaotsh@google.com
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
12
---
11
target/arm/helper.h | 2 --
13
include/hw/misc/npcm7xx_clk.h | 6 -----
12
target/arm/translate.h | 34 ++++++++++++++++++++++++++++++++++
14
include/hw/timer/npcm7xx_timer.h | 1 +
13
target/arm/op_helper.c | 5 -----
15
hw/arm/npcm7xx.c | 5 ++++
14
target/arm/translate-a64.c | 11 -----------
16
hw/timer/npcm7xx_timer.c | 39 +++++++++++++++-----------------
15
target/arm/translate.c | 11 -----------
17
4 files changed, 24 insertions(+), 27 deletions(-)
16
5 files changed, 34 insertions(+), 29 deletions(-)
17
18
18
diff --git a/target/arm/helper.h b/target/arm/helper.h
19
diff --git a/include/hw/misc/npcm7xx_clk.h b/include/hw/misc/npcm7xx_clk.h
19
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/helper.h
21
--- a/include/hw/misc/npcm7xx_clk.h
21
+++ b/target/arm/helper.h
22
+++ b/include/hw/misc/npcm7xx_clk.h
22
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(get_cp_reg, i32, env, ptr)
23
@@ -XXX,XX +XXX,XX @@
23
DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64)
24
#include "hw/clock.h"
24
DEF_HELPER_2(get_cp_reg64, i64, env, ptr)
25
#include "hw/sysbus.h"
25
26
26
-DEF_HELPER_1(clear_pstate_ss, void, env)
27
-/*
28
- * The reference clock frequency for the timer modules, and the SECCNT and
29
- * CNTR25M registers in this module, is always 25 MHz.
30
- */
31
-#define NPCM7XX_TIMER_REF_HZ (25000000)
27
-
32
-
28
DEF_HELPER_2(get_r13_banked, i32, env, i32)
33
/*
29
DEF_HELPER_3(set_r13_banked, void, env, i32, i32)
34
* Number of registers in our device state structure. Don't change this without
30
35
* incrementing the version_id in the vmstate.
31
diff --git a/target/arm/translate.h b/target/arm/translate.h
36
diff --git a/include/hw/timer/npcm7xx_timer.h b/include/hw/timer/npcm7xx_timer.h
32
index XXXXXXX..XXXXXXX 100644
37
index XXXXXXX..XXXXXXX 100644
33
--- a/target/arm/translate.h
38
--- a/include/hw/timer/npcm7xx_timer.h
34
+++ b/target/arm/translate.h
39
+++ b/include/hw/timer/npcm7xx_timer.h
35
@@ -XXX,XX +XXX,XX @@ static inline TCGv_i32 get_ahp_flag(void)
40
@@ -XXX,XX +XXX,XX @@ struct NPCM7xxTimerCtrlState {
36
return ret;
41
42
uint32_t tisr;
43
44
+ Clock *clock;
45
NPCM7xxTimer timer[NPCM7XX_TIMERS_PER_CTRL];
46
NPCM7xxWatchdogTimer watchdog_timer;
47
};
48
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/hw/arm/npcm7xx.c
51
+++ b/hw/arm/npcm7xx.c
52
@@ -XXX,XX +XXX,XX @@
53
#include "hw/char/serial.h"
54
#include "hw/loader.h"
55
#include "hw/misc/unimp.h"
56
+#include "hw/qdev-clock.h"
57
#include "hw/qdev-properties.h"
58
#include "qapi/error.h"
59
#include "qemu/units.h"
60
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
61
int first_irq;
62
int j;
63
64
+ /* Connect the timer clock. */
65
+ qdev_connect_clock_in(DEVICE(&s->tim[i]), "clock", qdev_get_clock_out(
66
+ DEVICE(&s->clk), "timer-clock"));
67
+
68
sysbus_realize(sbd, &error_abort);
69
sysbus_mmio_map(sbd, 0, npcm7xx_tim_addr[i]);
70
71
diff --git a/hw/timer/npcm7xx_timer.c b/hw/timer/npcm7xx_timer.c
72
index XXXXXXX..XXXXXXX 100644
73
--- a/hw/timer/npcm7xx_timer.c
74
+++ b/hw/timer/npcm7xx_timer.c
75
@@ -XXX,XX +XXX,XX @@
76
#include "qemu/osdep.h"
77
78
#include "hw/irq.h"
79
+#include "hw/qdev-clock.h"
80
#include "hw/qdev-properties.h"
81
-#include "hw/misc/npcm7xx_clk.h"
82
#include "hw/timer/npcm7xx_timer.h"
83
#include "migration/vmstate.h"
84
#include "qemu/bitops.h"
85
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr)
86
/* Convert a timer cycle count to a time interval in nanoseconds. */
87
static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count)
88
{
89
- int64_t ns = count;
90
+ int64_t ticks = count;
91
92
- ns *= NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ;
93
- ns *= npcm7xx_tcsr_prescaler(t->tcsr);
94
+ ticks *= npcm7xx_tcsr_prescaler(t->tcsr);
95
96
- return ns;
97
+ return clock_ticks_to_ns(t->ctrl->clock, ticks);
37
}
98
}
38
99
39
+/* Set bits within PSTATE. */
100
/* Convert a time interval in nanoseconds to a timer cycle count. */
40
+static inline void set_pstate_bits(uint32_t bits)
101
static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns)
41
+{
102
{
42
+ TCGv_i32 p = tcg_temp_new_i32();
103
- int64_t count;
43
+
104
-
44
+ tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
105
- count = ns / (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ);
45
+
106
- count /= npcm7xx_tcsr_prescaler(t->tcsr);
46
+ tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
107
-
47
+ tcg_gen_ori_i32(p, p, bits);
108
- return count;
48
+ tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
109
+ return ns / clock_ticks_to_ns(t->ctrl->clock,
49
+ tcg_temp_free_i32(p);
110
+ npcm7xx_tcsr_prescaler(t->tcsr));
50
+}
51
+
52
+/* Clear bits within PSTATE. */
53
+static inline void clear_pstate_bits(uint32_t bits)
54
+{
55
+ TCGv_i32 p = tcg_temp_new_i32();
56
+
57
+ tcg_debug_assert(!(bits & CACHED_PSTATE_BITS));
58
+
59
+ tcg_gen_ld_i32(p, cpu_env, offsetof(CPUARMState, pstate));
60
+ tcg_gen_andi_i32(p, p, ~bits);
61
+ tcg_gen_st_i32(p, cpu_env, offsetof(CPUARMState, pstate));
62
+ tcg_temp_free_i32(p);
63
+}
64
+
65
+/* If the singlestep state is Active-not-pending, advance to Active-pending. */
66
+static inline void gen_ss_advance(DisasContext *s)
67
+{
68
+ if (s->ss_active) {
69
+ s->pstate_ss = 0;
70
+ clear_pstate_bits(PSTATE_SS);
71
+ }
72
+}
73
74
/* Vector operations shared between ARM and AArch64. */
75
extern const GVecGen3 bsl_op;
76
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
77
index XXXXXXX..XXXXXXX 100644
78
--- a/target/arm/op_helper.c
79
+++ b/target/arm/op_helper.c
80
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
81
return res;
82
}
111
}
83
112
84
-void HELPER(clear_pstate_ss)(CPUARMState *env)
113
static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
85
-{
114
@@ -XXX,XX +XXX,XX @@ static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t)
86
- env->pstate &= ~PSTATE_SS;
115
static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
87
-}
116
int64_t cycles)
88
-
89
void HELPER(pre_hvc)(CPUARMState *env)
90
{
117
{
91
ARMCPU *cpu = arm_env_get_cpu(env);
118
- uint32_t prescaler = npcm7xx_watchdog_timer_prescaler(t);
92
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
119
- int64_t ns = (NANOSECONDS_PER_SECOND / NPCM7XX_TIMER_REF_HZ) * cycles;
93
index XXXXXXX..XXXXXXX 100644
120
+ int64_t ticks = cycles * npcm7xx_watchdog_timer_prescaler(t);
94
--- a/target/arm/translate-a64.c
121
+ int64_t ns = clock_ticks_to_ns(t->ctrl->clock, ticks);
95
+++ b/target/arm/translate-a64.c
122
96
@@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, int offset,
123
/*
97
s->base.is_jmp = DISAS_NORETURN;
124
* The reset function always clears the current timer. The caller of the
125
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t,
126
*/
127
npcm7xx_timer_clear(&t->base_timer);
128
129
- ns *= prescaler;
130
t->base_timer.remaining_ns = ns;
98
}
131
}
99
132
100
-static void gen_ss_advance(DisasContext *s)
133
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_hold_reset(Object *obj)
101
-{
134
qemu_irq_lower(s->watchdog_timer.irq);
102
- /* If the singlestep state is Active-not-pending, advance to
135
}
103
- * Active-pending.
136
104
- */
137
-static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
105
- if (s->ss_active) {
138
+static void npcm7xx_timer_init(Object *obj)
106
- s->pstate_ss = 0;
107
- gen_helper_clear_pstate_ss(cpu_env);
108
- }
109
-}
110
-
111
static void gen_step_complete_exception(DisasContext *s)
112
{
139
{
113
/* We just completed step of an insn. Move from Active-not-pending
140
- NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(dev);
114
diff --git a/target/arm/translate.c b/target/arm/translate.c
141
- SysBusDevice *sbd = &s->parent;
115
index XXXXXXX..XXXXXXX 100644
142
+ NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj);
116
--- a/target/arm/translate.c
143
+ DeviceState *dev = DEVICE(obj);
117
+++ b/target/arm/translate.c
144
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
118
@@ -XXX,XX +XXX,XX @@ static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el)
145
int i;
119
tcg_temp_free_i32(tcg_excp);
146
NPCM7xxWatchdogTimer *w;
147
148
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_realize(DeviceState *dev, Error **errp)
149
npcm7xx_watchdog_timer_expired, w);
150
sysbus_init_irq(sbd, &w->irq);
151
152
- memory_region_init_io(&s->iomem, OBJECT(s), &npcm7xx_timer_ops, s,
153
+ memory_region_init_io(&s->iomem, obj, &npcm7xx_timer_ops, s,
154
TYPE_NPCM7XX_TIMER, 4 * KiB);
155
sysbus_init_mmio(sbd, &s->iomem);
156
qdev_init_gpio_out_named(dev, &w->reset_signal,
157
NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1);
158
+ s->clock = qdev_init_clock_in(dev, "clock", NULL, NULL);
120
}
159
}
121
160
122
-static void gen_ss_advance(DisasContext *s)
161
static const VMStateDescription vmstate_npcm7xx_base_timer = {
123
-{
162
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_npcm7xx_watchdog_timer = {
124
- /* If the singlestep state is Active-not-pending, advance to
163
125
- * Active-pending.
164
static const VMStateDescription vmstate_npcm7xx_timer_ctrl = {
126
- */
165
.name = "npcm7xx-timer-ctrl",
127
- if (s->ss_active) {
166
- .version_id = 1,
128
- s->pstate_ss = 0;
167
- .minimum_version_id = 1,
129
- gen_helper_clear_pstate_ss(cpu_env);
168
+ .version_id = 2,
130
- }
169
+ .minimum_version_id = 2,
131
-}
170
.fields = (VMStateField[]) {
132
-
171
VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState),
133
static void gen_step_complete_exception(DisasContext *s)
172
+ VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState),
134
{
173
VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState,
135
/* We just completed step of an insn. Move from Active-not-pending
174
NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer,
175
NPCM7xxTimer),
176
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_timer_class_init(ObjectClass *klass, void *data)
177
QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS);
178
179
dc->desc = "NPCM7xx Timer Controller";
180
- dc->realize = npcm7xx_timer_realize;
181
dc->vmsd = &vmstate_npcm7xx_timer_ctrl;
182
rc->phases.enter = npcm7xx_timer_enter_reset;
183
rc->phases.hold = npcm7xx_timer_hold_reset;
184
@@ -XXX,XX +XXX,XX @@ static const TypeInfo npcm7xx_timer_info = {
185
.parent = TYPE_SYS_BUS_DEVICE,
186
.instance_size = sizeof(NPCM7xxTimerCtrlState),
187
.class_init = npcm7xx_timer_class_init,
188
+ .instance_init = npcm7xx_timer_init,
189
};
190
191
static void npcm7xx_timer_register_type(void)
136
--
192
--
137
2.20.1
193
2.20.1
138
194
139
195
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Hao Wu <wuhaotsh@google.com>
2
2
3
The EL0+UMA check is unique to DAIF. While SPSel had avoided the
3
The ADC is part of NPCM7XX Module. Its behavior is controled by the
4
check by nature of already checking EL >= 1, the other post v8.0
4
ADC_CON register. It converts one of the eight analog inputs into a
5
extensions to MSR (imm) allow EL0 and do not require UMA. Avoid
5
digital input and stores it in the ADC_DATA register when enabled.
6
the unconditional write to pc and use raise_exception_ra to unwind.
7
6
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Users can alter input value by using qom-set QMP command.
9
Message-id: 20190301200501.16533-5-richard.henderson@linaro.org
8
9
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
10
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
11
Signed-off-by: Hao Wu <wuhaotsh@google.com>
12
Message-id: 20210108190945.949196-4-wuhaotsh@google.com
13
[PMM: Added missing hw/adc/trace.h file]
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
16
---
13
target/arm/helper-a64.h | 3 +++
17
docs/system/arm/nuvoton.rst | 2 +-
14
target/arm/helper.h | 1 -
18
meson.build | 1 +
15
target/arm/internals.h | 15 ++++++++++++++
19
hw/adc/trace.h | 1 +
16
target/arm/helper-a64.c | 30 +++++++++++++++++++++++++++
20
include/hw/adc/npcm7xx_adc.h | 69 ++++++
17
target/arm/op_helper.c | 42 --------------------------------------
21
include/hw/arm/npcm7xx.h | 2 +
18
target/arm/translate-a64.c | 41 ++++++++++++++++++++++---------------
22
hw/adc/npcm7xx_adc.c | 301 ++++++++++++++++++++++++++
19
6 files changed, 73 insertions(+), 59 deletions(-)
23
hw/arm/npcm7xx.c | 24 ++-
24
tests/qtest/npcm7xx_adc-test.c | 377 +++++++++++++++++++++++++++++++++
25
hw/adc/meson.build | 1 +
26
hw/adc/trace-events | 5 +
27
tests/qtest/meson.build | 3 +-
28
11 files changed, 783 insertions(+), 3 deletions(-)
29
create mode 100644 hw/adc/trace.h
30
create mode 100644 include/hw/adc/npcm7xx_adc.h
31
create mode 100644 hw/adc/npcm7xx_adc.c
32
create mode 100644 tests/qtest/npcm7xx_adc-test.c
33
create mode 100644 hw/adc/trace-events
20
34
21
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
35
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
22
index XXXXXXX..XXXXXXX 100644
36
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/helper-a64.h
37
--- a/docs/system/arm/nuvoton.rst
24
+++ b/target/arm/helper-a64.h
38
+++ b/docs/system/arm/nuvoton.rst
39
@@ -XXX,XX +XXX,XX @@ Supported devices
40
* Random Number Generator (RNG)
41
* USB host (USBH)
42
* GPIO controller
43
+ * Analog to Digital Converter (ADC)
44
45
Missing devices
46
---------------
47
@@ -XXX,XX +XXX,XX @@ Missing devices
48
* USB device (USBD)
49
* SMBus controller (SMBF)
50
* Peripheral SPI controller (PSPI)
51
- * Analog to Digital Converter (ADC)
52
* SD/MMC host
53
* PECI interface
54
* Pulse Width Modulation (PWM)
55
diff --git a/meson.build b/meson.build
56
index XXXXXXX..XXXXXXX 100644
57
--- a/meson.build
58
+++ b/meson.build
59
@@ -XXX,XX +XXX,XX @@ if have_system
60
'chardev',
61
'hw/9pfs',
62
'hw/acpi',
63
+ 'hw/adc',
64
'hw/alpha',
65
'hw/arm',
66
'hw/audio',
67
diff --git a/hw/adc/trace.h b/hw/adc/trace.h
68
new file mode 100644
69
index XXXXXXX..XXXXXXX
70
--- /dev/null
71
+++ b/hw/adc/trace.h
72
@@ -0,0 +1 @@
73
+#include "trace/trace-hw_adc.h"
74
diff --git a/include/hw/adc/npcm7xx_adc.h b/include/hw/adc/npcm7xx_adc.h
75
new file mode 100644
76
index XXXXXXX..XXXXXXX
77
--- /dev/null
78
+++ b/include/hw/adc/npcm7xx_adc.h
25
@@ -XXX,XX +XXX,XX @@
79
@@ -XXX,XX +XXX,XX @@
26
DEF_HELPER_FLAGS_2(udiv64, TCG_CALL_NO_RWG_SE, i64, i64, i64)
80
+/*
27
DEF_HELPER_FLAGS_2(sdiv64, TCG_CALL_NO_RWG_SE, s64, s64, s64)
81
+ * Nuvoton NPCM7xx ADC Module
28
DEF_HELPER_FLAGS_1(rbit64, TCG_CALL_NO_RWG_SE, i64, i64)
82
+ *
29
+DEF_HELPER_2(msr_i_spsel, void, env, i32)
83
+ * Copyright 2020 Google LLC
30
+DEF_HELPER_2(msr_i_daifset, void, env, i32)
84
+ *
31
+DEF_HELPER_2(msr_i_daifclear, void, env, i32)
85
+ * This program is free software; you can redistribute it and/or modify it
32
DEF_HELPER_3(vfp_cmph_a64, i64, f16, f16, ptr)
86
+ * under the terms of the GNU General Public License as published by the
33
DEF_HELPER_3(vfp_cmpeh_a64, i64, f16, f16, ptr)
87
+ * Free Software Foundation; either version 2 of the License, or
34
DEF_HELPER_3(vfp_cmps_a64, i64, f32, f32, ptr)
88
+ * (at your option) any later version.
35
diff --git a/target/arm/helper.h b/target/arm/helper.h
89
+ *
90
+ * This program is distributed in the hope that it will be useful, but WITHOUT
91
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
92
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
93
+ * for more details.
94
+ */
95
+#ifndef NPCM7XX_ADC_H
96
+#define NPCM7XX_ADC_H
97
+
98
+#include "hw/clock.h"
99
+#include "hw/irq.h"
100
+#include "hw/sysbus.h"
101
+#include "qemu/timer.h"
102
+
103
+#define NPCM7XX_ADC_NUM_INPUTS 8
104
+/**
105
+ * This value should not be changed unless write_adc_calibration function in
106
+ * hw/arm/npcm7xx.c is also changed.
107
+ */
108
+#define NPCM7XX_ADC_NUM_CALIB 2
109
+
110
+/**
111
+ * struct NPCM7xxADCState - Analog to Digital Converter Module device state.
112
+ * @parent: System bus device.
113
+ * @iomem: Memory region through which registers are accessed.
114
+ * @conv_timer: The timer counts down remaining cycles for the conversion.
115
+ * @irq: GIC interrupt line to fire on expiration (if enabled).
116
+ * @con: The Control Register.
117
+ * @data: The Data Buffer.
118
+ * @clock: The ADC Clock.
119
+ * @adci: The input voltage in units of uV. 1uv = 1e-6V.
120
+ * @vref: The external reference voltage.
121
+ * @iref: The internal reference voltage, initialized at launch time.
122
+ * @rv: The calibrated output values of 0.5V and 1.5V for the ADC.
123
+ */
124
+typedef struct {
125
+ SysBusDevice parent;
126
+
127
+ MemoryRegion iomem;
128
+
129
+ QEMUTimer conv_timer;
130
+
131
+ qemu_irq irq;
132
+ uint32_t con;
133
+ uint32_t data;
134
+ Clock *clock;
135
+
136
+ /* Voltages are in unit of uV. 1V = 1000000uV. */
137
+ uint32_t adci[NPCM7XX_ADC_NUM_INPUTS];
138
+ uint32_t vref;
139
+ uint32_t iref;
140
+
141
+ uint16_t calibration_r_values[NPCM7XX_ADC_NUM_CALIB];
142
+} NPCM7xxADCState;
143
+
144
+#define TYPE_NPCM7XX_ADC "npcm7xx-adc"
145
+#define NPCM7XX_ADC(obj) \
146
+ OBJECT_CHECK(NPCM7xxADCState, (obj), TYPE_NPCM7XX_ADC)
147
+
148
+#endif /* NPCM7XX_ADC_H */
149
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
36
index XXXXXXX..XXXXXXX 100644
150
index XXXXXXX..XXXXXXX 100644
37
--- a/target/arm/helper.h
151
--- a/include/hw/arm/npcm7xx.h
38
+++ b/target/arm/helper.h
152
+++ b/include/hw/arm/npcm7xx.h
39
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(get_cp_reg, i32, env, ptr)
153
@@ -XXX,XX +XXX,XX @@
40
DEF_HELPER_3(set_cp_reg64, void, env, ptr, i64)
154
#define NPCM7XX_H
41
DEF_HELPER_2(get_cp_reg64, i64, env, ptr)
155
42
156
#include "hw/boards.h"
43
-DEF_HELPER_3(msr_i_pstate, void, env, i32, i32)
157
+#include "hw/adc/npcm7xx_adc.h"
44
DEF_HELPER_1(clear_pstate_ss, void, env)
158
#include "hw/cpu/a9mpcore.h"
45
159
#include "hw/gpio/npcm7xx_gpio.h"
46
DEF_HELPER_2(get_r13_banked, i32, env, i32)
160
#include "hw/mem/npcm7xx_mc.h"
47
diff --git a/target/arm/internals.h b/target/arm/internals.h
161
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
162
NPCM7xxGCRState gcr;
163
NPCM7xxCLKState clk;
164
NPCM7xxTimerCtrlState tim[3];
165
+ NPCM7xxADCState adc;
166
NPCM7xxOTPState key_storage;
167
NPCM7xxOTPState fuse_array;
168
NPCM7xxMCState mc;
169
diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c
170
new file mode 100644
171
index XXXXXXX..XXXXXXX
172
--- /dev/null
173
+++ b/hw/adc/npcm7xx_adc.c
174
@@ -XXX,XX +XXX,XX @@
175
+/*
176
+ * Nuvoton NPCM7xx ADC Module
177
+ *
178
+ * Copyright 2020 Google LLC
179
+ *
180
+ * This program is free software; you can redistribute it and/or modify it
181
+ * under the terms of the GNU General Public License as published by the
182
+ * Free Software Foundation; either version 2 of the License, or
183
+ * (at your option) any later version.
184
+ *
185
+ * This program is distributed in the hope that it will be useful, but WITHOUT
186
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
187
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
188
+ * for more details.
189
+ */
190
+
191
+#include "qemu/osdep.h"
192
+#include "hw/adc/npcm7xx_adc.h"
193
+#include "hw/qdev-clock.h"
194
+#include "hw/qdev-properties.h"
195
+#include "hw/registerfields.h"
196
+#include "migration/vmstate.h"
197
+#include "qemu/log.h"
198
+#include "qemu/module.h"
199
+#include "qemu/timer.h"
200
+#include "qemu/units.h"
201
+#include "trace.h"
202
+
203
+REG32(NPCM7XX_ADC_CON, 0x0)
204
+REG32(NPCM7XX_ADC_DATA, 0x4)
205
+
206
+/* Register field definitions. */
207
+#define NPCM7XX_ADC_CON_MUX(rv) extract32(rv, 24, 4)
208
+#define NPCM7XX_ADC_CON_INT_EN BIT(21)
209
+#define NPCM7XX_ADC_CON_REFSEL BIT(19)
210
+#define NPCM7XX_ADC_CON_INT BIT(18)
211
+#define NPCM7XX_ADC_CON_EN BIT(17)
212
+#define NPCM7XX_ADC_CON_RST BIT(16)
213
+#define NPCM7XX_ADC_CON_CONV BIT(14)
214
+#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8)
215
+
216
+#define NPCM7XX_ADC_MAX_RESULT 1023
217
+#define NPCM7XX_ADC_DEFAULT_IREF 2000000
218
+#define NPCM7XX_ADC_CONV_CYCLES 20
219
+#define NPCM7XX_ADC_RESET_CYCLES 10
220
+#define NPCM7XX_ADC_R0_INPUT 500000
221
+#define NPCM7XX_ADC_R1_INPUT 1500000
222
+
223
+static void npcm7xx_adc_reset(NPCM7xxADCState *s)
224
+{
225
+ timer_del(&s->conv_timer);
226
+ s->con = 0x000c0001;
227
+ s->data = 0x00000000;
228
+}
229
+
230
+static uint32_t npcm7xx_adc_convert(uint32_t input, uint32_t ref)
231
+{
232
+ uint32_t result;
233
+
234
+ result = input * (NPCM7XX_ADC_MAX_RESULT + 1) / ref;
235
+ if (result > NPCM7XX_ADC_MAX_RESULT) {
236
+ result = NPCM7XX_ADC_MAX_RESULT;
237
+ }
238
+
239
+ return result;
240
+}
241
+
242
+static uint32_t npcm7xx_adc_prescaler(NPCM7xxADCState *s)
243
+{
244
+ return 2 * (NPCM7XX_ADC_CON_DIV(s->con) + 1);
245
+}
246
+
247
+static void npcm7xx_adc_start_timer(Clock *clk, QEMUTimer *timer,
248
+ uint32_t cycles, uint32_t prescaler)
249
+{
250
+ int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
251
+ int64_t ticks = cycles;
252
+ int64_t ns;
253
+
254
+ ticks *= prescaler;
255
+ ns = clock_ticks_to_ns(clk, ticks);
256
+ ns += now;
257
+ timer_mod(timer, ns);
258
+}
259
+
260
+static void npcm7xx_adc_start_convert(NPCM7xxADCState *s)
261
+{
262
+ uint32_t prescaler = npcm7xx_adc_prescaler(s);
263
+
264
+ npcm7xx_adc_start_timer(s->clock, &s->conv_timer, NPCM7XX_ADC_CONV_CYCLES,
265
+ prescaler);
266
+}
267
+
268
+static void npcm7xx_adc_convert_done(void *opaque)
269
+{
270
+ NPCM7xxADCState *s = opaque;
271
+ uint32_t input = NPCM7XX_ADC_CON_MUX(s->con);
272
+ uint32_t ref = (s->con & NPCM7XX_ADC_CON_REFSEL)
273
+ ? s->iref : s->vref;
274
+
275
+ if (input >= NPCM7XX_ADC_NUM_INPUTS) {
276
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid input: %u\n",
277
+ __func__, input);
278
+ return;
279
+ }
280
+ s->data = npcm7xx_adc_convert(s->adci[input], ref);
281
+ if (s->con & NPCM7XX_ADC_CON_INT_EN) {
282
+ s->con |= NPCM7XX_ADC_CON_INT;
283
+ qemu_irq_raise(s->irq);
284
+ }
285
+ s->con &= ~NPCM7XX_ADC_CON_CONV;
286
+}
287
+
288
+static void npcm7xx_adc_calibrate(NPCM7xxADCState *adc)
289
+{
290
+ adc->calibration_r_values[0] = npcm7xx_adc_convert(NPCM7XX_ADC_R0_INPUT,
291
+ adc->iref);
292
+ adc->calibration_r_values[1] = npcm7xx_adc_convert(NPCM7XX_ADC_R1_INPUT,
293
+ adc->iref);
294
+}
295
+
296
+static void npcm7xx_adc_write_con(NPCM7xxADCState *s, uint32_t new_con)
297
+{
298
+ uint32_t old_con = s->con;
299
+
300
+ /* Write ADC_INT to 1 to clear it */
301
+ if (new_con & NPCM7XX_ADC_CON_INT) {
302
+ new_con &= ~NPCM7XX_ADC_CON_INT;
303
+ qemu_irq_lower(s->irq);
304
+ } else if (old_con & NPCM7XX_ADC_CON_INT) {
305
+ new_con |= NPCM7XX_ADC_CON_INT;
306
+ }
307
+
308
+ s->con = new_con;
309
+
310
+ if (s->con & NPCM7XX_ADC_CON_RST) {
311
+ npcm7xx_adc_reset(s);
312
+ return;
313
+ }
314
+
315
+ if ((s->con & NPCM7XX_ADC_CON_EN)) {
316
+ if (s->con & NPCM7XX_ADC_CON_CONV) {
317
+ if (!(old_con & NPCM7XX_ADC_CON_CONV)) {
318
+ npcm7xx_adc_start_convert(s);
319
+ }
320
+ } else {
321
+ timer_del(&s->conv_timer);
322
+ }
323
+ }
324
+}
325
+
326
+static uint64_t npcm7xx_adc_read(void *opaque, hwaddr offset, unsigned size)
327
+{
328
+ uint64_t value = 0;
329
+ NPCM7xxADCState *s = opaque;
330
+
331
+ switch (offset) {
332
+ case A_NPCM7XX_ADC_CON:
333
+ value = s->con;
334
+ break;
335
+
336
+ case A_NPCM7XX_ADC_DATA:
337
+ value = s->data;
338
+ break;
339
+
340
+ default:
341
+ qemu_log_mask(LOG_GUEST_ERROR,
342
+ "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
343
+ __func__, offset);
344
+ break;
345
+ }
346
+
347
+ trace_npcm7xx_adc_read(DEVICE(s)->canonical_path, offset, value);
348
+ return value;
349
+}
350
+
351
+static void npcm7xx_adc_write(void *opaque, hwaddr offset, uint64_t v,
352
+ unsigned size)
353
+{
354
+ NPCM7xxADCState *s = opaque;
355
+
356
+ trace_npcm7xx_adc_write(DEVICE(s)->canonical_path, offset, v);
357
+ switch (offset) {
358
+ case A_NPCM7XX_ADC_CON:
359
+ npcm7xx_adc_write_con(s, v);
360
+ break;
361
+
362
+ case A_NPCM7XX_ADC_DATA:
363
+ qemu_log_mask(LOG_GUEST_ERROR,
364
+ "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
365
+ __func__, offset);
366
+ break;
367
+
368
+ default:
369
+ qemu_log_mask(LOG_GUEST_ERROR,
370
+ "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
371
+ __func__, offset);
372
+ break;
373
+ }
374
+
375
+}
376
+
377
+static const struct MemoryRegionOps npcm7xx_adc_ops = {
378
+ .read = npcm7xx_adc_read,
379
+ .write = npcm7xx_adc_write,
380
+ .endianness = DEVICE_LITTLE_ENDIAN,
381
+ .valid = {
382
+ .min_access_size = 4,
383
+ .max_access_size = 4,
384
+ .unaligned = false,
385
+ },
386
+};
387
+
388
+static void npcm7xx_adc_enter_reset(Object *obj, ResetType type)
389
+{
390
+ NPCM7xxADCState *s = NPCM7XX_ADC(obj);
391
+
392
+ npcm7xx_adc_reset(s);
393
+}
394
+
395
+static void npcm7xx_adc_hold_reset(Object *obj)
396
+{
397
+ NPCM7xxADCState *s = NPCM7XX_ADC(obj);
398
+
399
+ qemu_irq_lower(s->irq);
400
+}
401
+
402
+static void npcm7xx_adc_init(Object *obj)
403
+{
404
+ NPCM7xxADCState *s = NPCM7XX_ADC(obj);
405
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
406
+ int i;
407
+
408
+ sysbus_init_irq(sbd, &s->irq);
409
+
410
+ timer_init_ns(&s->conv_timer, QEMU_CLOCK_VIRTUAL,
411
+ npcm7xx_adc_convert_done, s);
412
+ memory_region_init_io(&s->iomem, obj, &npcm7xx_adc_ops, s,
413
+ TYPE_NPCM7XX_ADC, 4 * KiB);
414
+ sysbus_init_mmio(sbd, &s->iomem);
415
+ s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL);
416
+
417
+ for (i = 0; i < NPCM7XX_ADC_NUM_INPUTS; ++i) {
418
+ object_property_add_uint32_ptr(obj, "adci[*]",
419
+ &s->adci[i], OBJ_PROP_FLAG_WRITE);
420
+ }
421
+ object_property_add_uint32_ptr(obj, "vref",
422
+ &s->vref, OBJ_PROP_FLAG_WRITE);
423
+ npcm7xx_adc_calibrate(s);
424
+}
425
+
426
+static const VMStateDescription vmstate_npcm7xx_adc = {
427
+ .name = "npcm7xx-adc",
428
+ .version_id = 0,
429
+ .minimum_version_id = 0,
430
+ .fields = (VMStateField[]) {
431
+ VMSTATE_TIMER(conv_timer, NPCM7xxADCState),
432
+ VMSTATE_UINT32(con, NPCM7xxADCState),
433
+ VMSTATE_UINT32(data, NPCM7xxADCState),
434
+ VMSTATE_CLOCK(clock, NPCM7xxADCState),
435
+ VMSTATE_UINT32_ARRAY(adci, NPCM7xxADCState, NPCM7XX_ADC_NUM_INPUTS),
436
+ VMSTATE_UINT32(vref, NPCM7xxADCState),
437
+ VMSTATE_UINT32(iref, NPCM7xxADCState),
438
+ VMSTATE_UINT16_ARRAY(calibration_r_values, NPCM7xxADCState,
439
+ NPCM7XX_ADC_NUM_CALIB),
440
+ VMSTATE_END_OF_LIST(),
441
+ },
442
+};
443
+
444
+static Property npcm7xx_timer_properties[] = {
445
+ DEFINE_PROP_UINT32("iref", NPCM7xxADCState, iref, NPCM7XX_ADC_DEFAULT_IREF),
446
+ DEFINE_PROP_END_OF_LIST(),
447
+};
448
+
449
+static void npcm7xx_adc_class_init(ObjectClass *klass, void *data)
450
+{
451
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
452
+ DeviceClass *dc = DEVICE_CLASS(klass);
453
+
454
+ dc->desc = "NPCM7xx ADC Module";
455
+ dc->vmsd = &vmstate_npcm7xx_adc;
456
+ rc->phases.enter = npcm7xx_adc_enter_reset;
457
+ rc->phases.hold = npcm7xx_adc_hold_reset;
458
+
459
+ device_class_set_props(dc, npcm7xx_timer_properties);
460
+}
461
+
462
+static const TypeInfo npcm7xx_adc_info = {
463
+ .name = TYPE_NPCM7XX_ADC,
464
+ .parent = TYPE_SYS_BUS_DEVICE,
465
+ .instance_size = sizeof(NPCM7xxADCState),
466
+ .class_init = npcm7xx_adc_class_init,
467
+ .instance_init = npcm7xx_adc_init,
468
+};
469
+
470
+static void npcm7xx_adc_register_types(void)
471
+{
472
+ type_register_static(&npcm7xx_adc_info);
473
+}
474
+
475
+type_init(npcm7xx_adc_register_types);
476
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
48
index XXXXXXX..XXXXXXX 100644
477
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/internals.h
478
--- a/hw/arm/npcm7xx.c
50
+++ b/target/arm/internals.h
479
+++ b/hw/arm/npcm7xx.c
51
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va,
480
@@ -XXX,XX +XXX,XX @@
52
ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
481
#define NPCM7XX_EHCI_BA (0xf0806000)
53
ARMMMUIdx mmu_idx, bool data);
482
#define NPCM7XX_OHCI_BA (0xf0807000)
54
483
55
+static inline int exception_target_el(CPUARMState *env)
484
+/* ADC Module */
56
+{
485
+#define NPCM7XX_ADC_BA (0xf000c000)
57
+ int target_el = MAX(1, arm_current_el(env));
486
+
487
/* Internal AHB SRAM */
488
#define NPCM7XX_RAM3_BA (0xc0008000)
489
#define NPCM7XX_RAM3_SZ (4 * KiB)
490
@@ -XXX,XX +XXX,XX @@
491
#define NPCM7XX_ROM_BA (0xffff0000)
492
#define NPCM7XX_ROM_SZ (64 * KiB)
493
494
+
495
/* Clock configuration values to be fixed up when bypassing bootloader */
496
497
/* Run PLL1 at 1600 MHz */
498
@@ -XXX,XX +XXX,XX @@
499
* interrupts.
500
*/
501
enum NPCM7xxInterrupt {
502
+ NPCM7XX_ADC_IRQ = 0,
503
NPCM7XX_UART0_IRQ = 2,
504
NPCM7XX_UART1_IRQ,
505
NPCM7XX_UART2_IRQ,
506
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init_fuses(NPCM7xxState *s)
507
sizeof(value));
508
}
509
510
+static void npcm7xx_write_adc_calibration(NPCM7xxState *s)
511
+{
512
+ /* Both ADC and the fuse array must have realized. */
513
+ QEMU_BUILD_BUG_ON(sizeof(s->adc.calibration_r_values) != 4);
514
+ npcm7xx_otp_array_write(&s->fuse_array, s->adc.calibration_r_values,
515
+ NPCM7XX_FUSE_ADC_CALIB, sizeof(s->adc.calibration_r_values));
516
+}
517
+
518
static qemu_irq npcm7xx_irq(NPCM7xxState *s, int n)
519
{
520
return qdev_get_gpio_in(DEVICE(&s->a9mpcore), n);
521
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
522
TYPE_NPCM7XX_FUSE_ARRAY);
523
object_initialize_child(obj, "mc", &s->mc, TYPE_NPCM7XX_MC);
524
object_initialize_child(obj, "rng", &s->rng, TYPE_NPCM7XX_RNG);
525
+ object_initialize_child(obj, "adc", &s->adc, TYPE_NPCM7XX_ADC);
526
527
for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
528
object_initialize_child(obj, "tim[*]", &s->tim[i], TYPE_NPCM7XX_TIMER);
529
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
530
sysbus_realize(SYS_BUS_DEVICE(&s->mc), &error_abort);
531
sysbus_mmio_map(SYS_BUS_DEVICE(&s->mc), 0, NPCM7XX_MC_BA);
532
533
+ /* ADC Modules. Cannot fail. */
534
+ qdev_connect_clock_in(DEVICE(&s->adc), "clock", qdev_get_clock_out(
535
+ DEVICE(&s->clk), "adc-clock"));
536
+ sysbus_realize(SYS_BUS_DEVICE(&s->adc), &error_abort);
537
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->adc), 0, NPCM7XX_ADC_BA);
538
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
539
+ npcm7xx_irq(s, NPCM7XX_ADC_IRQ));
540
+ npcm7xx_write_adc_calibration(s);
541
+
542
/* Timer Modules (TIM). Cannot fail. */
543
QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_tim_addr) != ARRAY_SIZE(s->tim));
544
for (i = 0; i < ARRAY_SIZE(s->tim); i++) {
545
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
546
create_unimplemented_device("npcm7xx.vdmx", 0xe0800000, 4 * KiB);
547
create_unimplemented_device("npcm7xx.pcierc", 0xe1000000, 64 * KiB);
548
create_unimplemented_device("npcm7xx.kcs", 0xf0007000, 4 * KiB);
549
- create_unimplemented_device("npcm7xx.adc", 0xf000c000, 4 * KiB);
550
create_unimplemented_device("npcm7xx.gfxi", 0xf000e000, 4 * KiB);
551
create_unimplemented_device("npcm7xx.gpio[0]", 0xf0010000, 4 * KiB);
552
create_unimplemented_device("npcm7xx.gpio[1]", 0xf0011000, 4 * KiB);
553
diff --git a/tests/qtest/npcm7xx_adc-test.c b/tests/qtest/npcm7xx_adc-test.c
554
new file mode 100644
555
index XXXXXXX..XXXXXXX
556
--- /dev/null
557
+++ b/tests/qtest/npcm7xx_adc-test.c
558
@@ -XXX,XX +XXX,XX @@
559
+/*
560
+ * QTests for Nuvoton NPCM7xx ADCModules.
561
+ *
562
+ * Copyright 2020 Google LLC
563
+ *
564
+ * This program is free software; you can redistribute it and/or modify it
565
+ * under the terms of the GNU General Public License as published by the
566
+ * Free Software Foundation; either version 2 of the License, or
567
+ * (at your option) any later version.
568
+ *
569
+ * This program is distributed in the hope that it will be useful, but WITHOUT
570
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
571
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
572
+ * for more details.
573
+ */
574
+
575
+#include "qemu/osdep.h"
576
+#include "qemu/bitops.h"
577
+#include "qemu/timer.h"
578
+#include "libqos/libqtest.h"
579
+#include "qapi/qmp/qdict.h"
580
+
581
+#define REF_HZ (25000000)
582
+
583
+#define CON_OFFSET 0x0
584
+#define DATA_OFFSET 0x4
585
+
586
+#define NUM_INPUTS 8
587
+#define DEFAULT_IREF 2000000
588
+#define CONV_CYCLES 20
589
+#define RESET_CYCLES 10
590
+#define R0_INPUT 500000
591
+#define R1_INPUT 1500000
592
+#define MAX_RESULT 1023
593
+
594
+#define DEFAULT_CLKDIV 5
595
+
596
+#define FUSE_ARRAY_BA 0xf018a000
597
+#define FCTL_OFFSET 0x14
598
+#define FST_OFFSET 0x0
599
+#define FADDR_OFFSET 0x4
600
+#define FDATA_OFFSET 0x8
601
+#define ADC_CALIB_ADDR 24
602
+#define FUSE_READ 0x2
603
+
604
+/* Register field definitions. */
605
+#define CON_MUX(rv) ((rv) << 24)
606
+#define CON_INT_EN BIT(21)
607
+#define CON_REFSEL BIT(19)
608
+#define CON_INT BIT(18)
609
+#define CON_EN BIT(17)
610
+#define CON_RST BIT(16)
611
+#define CON_CONV BIT(14)
612
+#define CON_DIV(rv) extract32(rv, 1, 8)
613
+
614
+#define FST_RDST BIT(1)
615
+#define FDATA_MASK 0xff
616
+
617
+#define MAX_ERROR 10000
618
+#define MIN_CALIB_INPUT 100000
619
+#define MAX_CALIB_INPUT 1800000
620
+
621
+static const uint32_t input_list[] = {
622
+ 100000,
623
+ 500000,
624
+ 1000000,
625
+ 1500000,
626
+ 1800000,
627
+ 2000000,
628
+};
629
+
630
+static const uint32_t vref_list[] = {
631
+ 2000000,
632
+ 2200000,
633
+ 2500000,
634
+};
635
+
636
+static const uint32_t iref_list[] = {
637
+ 1800000,
638
+ 1900000,
639
+ 2000000,
640
+ 2100000,
641
+ 2200000,
642
+};
643
+
644
+static const uint32_t div_list[] = {0, 1, 3, 7, 15};
645
+
646
+typedef struct ADC {
647
+ int irq;
648
+ uint64_t base_addr;
649
+} ADC;
650
+
651
+ADC adc = {
652
+ .irq = 0,
653
+ .base_addr = 0xf000c000
654
+};
655
+
656
+static uint32_t adc_read_con(QTestState *qts, const ADC *adc)
657
+{
658
+ return qtest_readl(qts, adc->base_addr + CON_OFFSET);
659
+}
660
+
661
+static void adc_write_con(QTestState *qts, const ADC *adc, uint32_t value)
662
+{
663
+ qtest_writel(qts, adc->base_addr + CON_OFFSET, value);
664
+}
665
+
666
+static uint32_t adc_read_data(QTestState *qts, const ADC *adc)
667
+{
668
+ return qtest_readl(qts, adc->base_addr + DATA_OFFSET);
669
+}
670
+
671
+static uint32_t adc_calibrate(uint32_t measured, uint32_t *rv)
672
+{
673
+ return R0_INPUT + (R1_INPUT - R0_INPUT) * (int32_t)(measured - rv[0])
674
+ / (int32_t)(rv[1] - rv[0]);
675
+}
676
+
677
+static void adc_qom_set(QTestState *qts, const ADC *adc,
678
+ const char *name, uint32_t value)
679
+{
680
+ QDict *response;
681
+ const char *path = "/machine/soc/adc";
682
+
683
+ g_test_message("Setting properties %s of %s with value %u",
684
+ name, path, value);
685
+ response = qtest_qmp(qts, "{ 'execute': 'qom-set',"
686
+ " 'arguments': { 'path': %s, 'property': %s, 'value': %u}}",
687
+ path, name, value);
688
+ /* The qom set message returns successfully. */
689
+ g_assert_true(qdict_haskey(response, "return"));
690
+}
691
+
692
+static void adc_write_input(QTestState *qts, const ADC *adc,
693
+ uint32_t index, uint32_t value)
694
+{
695
+ char name[100];
696
+
697
+ sprintf(name, "adci[%u]", index);
698
+ adc_qom_set(qts, adc, name, value);
699
+}
700
+
701
+static void adc_write_vref(QTestState *qts, const ADC *adc, uint32_t value)
702
+{
703
+ adc_qom_set(qts, adc, "vref", value);
704
+}
705
+
706
+static uint32_t adc_calculate_output(uint32_t input, uint32_t ref)
707
+{
708
+ uint32_t output;
709
+
710
+ g_assert_cmpuint(input, <=, ref);
711
+ output = (input * (MAX_RESULT + 1)) / ref;
712
+ if (output > MAX_RESULT) {
713
+ output = MAX_RESULT;
714
+ }
715
+
716
+ return output;
717
+}
718
+
719
+static uint32_t adc_prescaler(QTestState *qts, const ADC *adc)
720
+{
721
+ uint32_t div = extract32(adc_read_con(qts, adc), 1, 8);
722
+
723
+ return 2 * (div + 1);
724
+}
725
+
726
+static int64_t adc_calculate_steps(uint32_t cycles, uint32_t prescale,
727
+ uint32_t clkdiv)
728
+{
729
+ return (NANOSECONDS_PER_SECOND / (REF_HZ >> clkdiv)) * cycles * prescale;
730
+}
731
+
732
+static void adc_wait_conv_finished(QTestState *qts, const ADC *adc,
733
+ uint32_t clkdiv)
734
+{
735
+ uint32_t prescaler = adc_prescaler(qts, adc);
58
+
736
+
59
+ /*
737
+ /*
60
+ * No such thing as secure EL1 if EL3 is aarch32,
738
+ * ADC should takes roughly 20 cycles to convert one sample. So we assert it
61
+ * so update the target EL to EL3 in this case.
739
+ * should take 10~30 cycles here.
62
+ */
740
+ */
63
+ if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) {
741
+ qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES / 2, prescaler,
64
+ target_el = 3;
742
+ clkdiv));
65
+ }
743
+ /* ADC is still converting. */
66
+
744
+ g_assert_true(adc_read_con(qts, adc) & CON_CONV);
67
+ return target_el;
745
+ qtest_clock_step(qts, adc_calculate_steps(CONV_CYCLES, prescaler, clkdiv));
68
+}
746
+ /* ADC has finished conversion. */
69
+
747
+ g_assert_false(adc_read_con(qts, adc) & CON_CONV);
70
#endif
748
+}
71
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
749
+
750
+/* Check ADC can be reset to default value. */
751
+static void test_init(gconstpointer adc_p)
752
+{
753
+ const ADC *adc = adc_p;
754
+
755
+ QTestState *qts = qtest_init("-machine quanta-gsj");
756
+ adc_write_con(qts, adc, CON_REFSEL | CON_INT);
757
+ g_assert_cmphex(adc_read_con(qts, adc), ==, CON_REFSEL);
758
+ qtest_quit(qts);
759
+}
760
+
761
+/* Check ADC can convert from an internal reference. */
762
+static void test_convert_internal(gconstpointer adc_p)
763
+{
764
+ const ADC *adc = adc_p;
765
+ uint32_t index, input, output, expected_output;
766
+ QTestState *qts = qtest_init("-machine quanta-gsj");
767
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
768
+
769
+ for (index = 0; index < NUM_INPUTS; ++index) {
770
+ for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) {
771
+ input = input_list[i];
772
+ expected_output = adc_calculate_output(input, DEFAULT_IREF);
773
+
774
+ adc_write_input(qts, adc, index, input);
775
+ adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT |
776
+ CON_EN | CON_CONV);
777
+ adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
778
+ g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) |
779
+ CON_REFSEL | CON_EN);
780
+ g_assert_false(qtest_get_irq(qts, adc->irq));
781
+ output = adc_read_data(qts, adc);
782
+ g_assert_cmpuint(output, ==, expected_output);
783
+ }
784
+ }
785
+
786
+ qtest_quit(qts);
787
+}
788
+
789
+/* Check ADC can convert from an external reference. */
790
+static void test_convert_external(gconstpointer adc_p)
791
+{
792
+ const ADC *adc = adc_p;
793
+ uint32_t index, input, vref, output, expected_output;
794
+ QTestState *qts = qtest_init("-machine quanta-gsj");
795
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
796
+
797
+ for (index = 0; index < NUM_INPUTS; ++index) {
798
+ for (size_t i = 0; i < ARRAY_SIZE(input_list); ++i) {
799
+ for (size_t j = 0; j < ARRAY_SIZE(vref_list); ++j) {
800
+ input = input_list[i];
801
+ vref = vref_list[j];
802
+ expected_output = adc_calculate_output(input, vref);
803
+
804
+ adc_write_input(qts, adc, index, input);
805
+ adc_write_vref(qts, adc, vref);
806
+ adc_write_con(qts, adc, CON_MUX(index) | CON_INT | CON_EN |
807
+ CON_CONV);
808
+ adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
809
+ g_assert_cmphex(adc_read_con(qts, adc), ==,
810
+ CON_MUX(index) | CON_EN);
811
+ g_assert_false(qtest_get_irq(qts, adc->irq));
812
+ output = adc_read_data(qts, adc);
813
+ g_assert_cmpuint(output, ==, expected_output);
814
+ }
815
+ }
816
+ }
817
+
818
+ qtest_quit(qts);
819
+}
820
+
821
+/* Check ADC interrupt files if and only if CON_INT_EN is set. */
822
+static void test_interrupt(gconstpointer adc_p)
823
+{
824
+ const ADC *adc = adc_p;
825
+ uint32_t index, input, output, expected_output;
826
+ QTestState *qts = qtest_init("-machine quanta-gsj");
827
+
828
+ index = 1;
829
+ input = input_list[1];
830
+ expected_output = adc_calculate_output(input, DEFAULT_IREF);
831
+
832
+ qtest_irq_intercept_in(qts, "/machine/soc/a9mpcore/gic");
833
+ adc_write_input(qts, adc, index, input);
834
+ g_assert_false(qtest_get_irq(qts, adc->irq));
835
+ adc_write_con(qts, adc, CON_MUX(index) | CON_INT_EN | CON_REFSEL | CON_INT
836
+ | CON_EN | CON_CONV);
837
+ adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
838
+ g_assert_cmphex(adc_read_con(qts, adc), ==, CON_MUX(index) | CON_INT_EN
839
+ | CON_REFSEL | CON_INT | CON_EN);
840
+ g_assert_true(qtest_get_irq(qts, adc->irq));
841
+ output = adc_read_data(qts, adc);
842
+ g_assert_cmpuint(output, ==, expected_output);
843
+
844
+ qtest_quit(qts);
845
+}
846
+
847
+/* Check ADC is reset after setting ADC_RST for 10 ADC cycles. */
848
+static void test_reset(gconstpointer adc_p)
849
+{
850
+ const ADC *adc = adc_p;
851
+ QTestState *qts = qtest_init("-machine quanta-gsj");
852
+
853
+ for (size_t i = 0; i < ARRAY_SIZE(div_list); ++i) {
854
+ uint32_t div = div_list[i];
855
+
856
+ adc_write_con(qts, adc, CON_INT | CON_EN | CON_RST | CON_DIV(div));
857
+ qtest_clock_step(qts, adc_calculate_steps(RESET_CYCLES,
858
+ adc_prescaler(qts, adc), DEFAULT_CLKDIV));
859
+ g_assert_false(adc_read_con(qts, adc) & CON_EN);
860
+ }
861
+ qtest_quit(qts);
862
+}
863
+
864
+/* Check ADC Calibration works as desired. */
865
+static void test_calibrate(gconstpointer adc_p)
866
+{
867
+ int i, j;
868
+ const ADC *adc = adc_p;
869
+
870
+ for (j = 0; j < ARRAY_SIZE(iref_list); ++j) {
871
+ uint32_t iref = iref_list[j];
872
+ uint32_t expected_rv[] = {
873
+ adc_calculate_output(R0_INPUT, iref),
874
+ adc_calculate_output(R1_INPUT, iref),
875
+ };
876
+ char buf[100];
877
+ QTestState *qts;
878
+
879
+ sprintf(buf, "-machine quanta-gsj -global npcm7xx-adc.iref=%u", iref);
880
+ qts = qtest_init(buf);
881
+
882
+ /* Check the converted value is correct using the calibration value. */
883
+ for (i = 0; i < ARRAY_SIZE(input_list); ++i) {
884
+ uint32_t input;
885
+ uint32_t output;
886
+ uint32_t expected_output;
887
+ uint32_t calibrated_voltage;
888
+ uint32_t index = 0;
889
+
890
+ input = input_list[i];
891
+ /* Calibration only works for input range 0.1V ~ 1.8V. */
892
+ if (input < MIN_CALIB_INPUT || input > MAX_CALIB_INPUT) {
893
+ continue;
894
+ }
895
+ expected_output = adc_calculate_output(input, iref);
896
+
897
+ adc_write_input(qts, adc, index, input);
898
+ adc_write_con(qts, adc, CON_MUX(index) | CON_REFSEL | CON_INT |
899
+ CON_EN | CON_CONV);
900
+ adc_wait_conv_finished(qts, adc, DEFAULT_CLKDIV);
901
+ g_assert_cmphex(adc_read_con(qts, adc), ==,
902
+ CON_REFSEL | CON_MUX(index) | CON_EN);
903
+ output = adc_read_data(qts, adc);
904
+ g_assert_cmpuint(output, ==, expected_output);
905
+
906
+ calibrated_voltage = adc_calibrate(output, expected_rv);
907
+ g_assert_cmpuint(calibrated_voltage, >, input - MAX_ERROR);
908
+ g_assert_cmpuint(calibrated_voltage, <, input + MAX_ERROR);
909
+ }
910
+
911
+ qtest_quit(qts);
912
+ }
913
+}
914
+
915
+static void adc_add_test(const char *name, const ADC* wd,
916
+ GTestDataFunc fn)
917
+{
918
+ g_autofree char *full_name = g_strdup_printf("npcm7xx_adc/%s", name);
919
+ qtest_add_data_func(full_name, wd, fn);
920
+}
921
+#define add_test(name, td) adc_add_test(#name, td, test_##name)
922
+
923
+int main(int argc, char **argv)
924
+{
925
+ g_test_init(&argc, &argv, NULL);
926
+
927
+ add_test(init, &adc);
928
+ add_test(convert_internal, &adc);
929
+ add_test(convert_external, &adc);
930
+ add_test(interrupt, &adc);
931
+ add_test(reset, &adc);
932
+ add_test(calibrate, &adc);
933
+
934
+ return g_test_run();
935
+}
936
diff --git a/hw/adc/meson.build b/hw/adc/meson.build
72
index XXXXXXX..XXXXXXX 100644
937
index XXXXXXX..XXXXXXX 100644
73
--- a/target/arm/helper-a64.c
938
--- a/hw/adc/meson.build
74
+++ b/target/arm/helper-a64.c
939
+++ b/hw/adc/meson.build
75
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(rbit64)(uint64_t x)
940
@@ -1 +1,2 @@
76
return revbit64(x);
941
softmmu_ss.add(when: 'CONFIG_STM32F2XX_ADC', if_true: files('stm32f2xx_adc.c'))
77
}
942
+softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files('npcm7xx_adc.c'))
78
943
diff --git a/hw/adc/trace-events b/hw/adc/trace-events
79
+void HELPER(msr_i_spsel)(CPUARMState *env, uint32_t imm)
944
new file mode 100644
80
+{
945
index XXXXXXX..XXXXXXX
81
+ update_spsel(env, imm);
946
--- /dev/null
82
+}
947
+++ b/hw/adc/trace-events
83
+
948
@@ -XXX,XX +XXX,XX @@
84
+static void daif_check(CPUARMState *env, uint32_t op,
949
+# See docs/devel/tracing.txt for syntax documentation.
85
+ uint32_t imm, uintptr_t ra)
950
+
86
+{
951
+# npcm7xx_adc.c
87
+ /* DAIF update to PSTATE. This is OK from EL0 only if UMA is set. */
952
+npcm7xx_adc_read(const char *id, uint64_t offset, uint32_t value) " %s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
88
+ if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
953
+npcm7xx_adc_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value 0x%04" PRIx32
89
+ raise_exception_ra(env, EXCP_UDEF,
954
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
90
+ syn_aa64_sysregtrap(0, extract32(op, 0, 3),
91
+ extract32(op, 3, 3), 4,
92
+ imm, 0x1f, 0),
93
+ exception_target_el(env), ra);
94
+ }
95
+}
96
+
97
+void HELPER(msr_i_daifset)(CPUARMState *env, uint32_t imm)
98
+{
99
+ daif_check(env, 0x1e, imm, GETPC());
100
+ env->daif |= (imm << 6) & PSTATE_DAIF;
101
+}
102
+
103
+void HELPER(msr_i_daifclear)(CPUARMState *env, uint32_t imm)
104
+{
105
+ daif_check(env, 0x1f, imm, GETPC());
106
+ env->daif &= ~((imm << 6) & PSTATE_DAIF);
107
+}
108
+
109
/* Convert a softfloat float_relation_ (as returned by
110
* the float*_compare functions) to the correct ARM
111
* NZCV flag state.
112
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
113
index XXXXXXX..XXXXXXX 100644
955
index XXXXXXX..XXXXXXX 100644
114
--- a/target/arm/op_helper.c
956
--- a/tests/qtest/meson.build
115
+++ b/target/arm/op_helper.c
957
+++ b/tests/qtest/meson.build
116
@@ -XXX,XX +XXX,XX @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome,
958
@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
117
cpu_loop_exit_restore(cs, ra);
959
['prom-env-test', 'boot-serial-test']
118
}
960
119
961
qtests_npcm7xx = \
120
-static int exception_target_el(CPUARMState *env)
962
- ['npcm7xx_gpio-test',
121
-{
963
+ ['npcm7xx_adc-test',
122
- int target_el = MAX(1, arm_current_el(env));
964
+ 'npcm7xx_gpio-test',
123
-
965
'npcm7xx_rng-test',
124
- /* No such thing as secure EL1 if EL3 is aarch32, so update the target EL
966
'npcm7xx_timer-test',
125
- * to EL3 in this case.
967
'npcm7xx_watchdog_timer-test']
126
- */
127
- if (arm_is_secure(env) && !arm_el_is_aa64(env, 3) && target_el == 1) {
128
- target_el = 3;
129
- }
130
-
131
- return target_el;
132
-}
133
-
134
uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn,
135
uint32_t maxindex)
136
{
137
@@ -XXX,XX +XXX,XX @@ uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
138
return res;
139
}
140
141
-void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm)
142
-{
143
- /* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set.
144
- * Note that SPSel is never OK from EL0; we rely on handle_msr_i()
145
- * to catch that case at translate time.
146
- */
147
- if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UMA)) {
148
- uint32_t syndrome = syn_aa64_sysregtrap(0, extract32(op, 0, 3),
149
- extract32(op, 3, 3), 4,
150
- imm, 0x1f, 0);
151
- raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env));
152
- }
153
-
154
- switch (op) {
155
- case 0x05: /* SPSel */
156
- update_spsel(env, imm);
157
- break;
158
- case 0x1e: /* DAIFSet */
159
- env->daif |= (imm << 6) & PSTATE_DAIF;
160
- break;
161
- case 0x1f: /* DAIFClear */
162
- env->daif &= ~((imm << 6) & PSTATE_DAIF);
163
- break;
164
- default:
165
- g_assert_not_reached();
166
- }
167
-}
168
-
169
void HELPER(clear_pstate_ss)(CPUARMState *env)
170
{
171
env->pstate &= ~PSTATE_SS;
172
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
173
index XXXXXXX..XXXXXXX 100644
174
--- a/target/arm/translate-a64.c
175
+++ b/target/arm/translate-a64.c
176
@@ -XXX,XX +XXX,XX @@ static void handle_sync(DisasContext *s, uint32_t insn,
177
static void handle_msr_i(DisasContext *s, uint32_t insn,
178
unsigned int op1, unsigned int op2, unsigned int crm)
179
{
180
+ TCGv_i32 t1;
181
int op = op1 << 3 | op2;
182
+
183
+ /* End the TB by default, chaining is ok. */
184
+ s->base.is_jmp = DISAS_TOO_MANY;
185
+
186
switch (op) {
187
case 0x05: /* SPSel */
188
if (s->current_el == 0) {
189
- unallocated_encoding(s);
190
- return;
191
+ goto do_unallocated;
192
}
193
- /* fall through */
194
- case 0x1e: /* DAIFSet */
195
- case 0x1f: /* DAIFClear */
196
- {
197
- TCGv_i32 tcg_imm = tcg_const_i32(crm);
198
- TCGv_i32 tcg_op = tcg_const_i32(op);
199
- gen_a64_set_pc_im(s->pc - 4);
200
- gen_helper_msr_i_pstate(cpu_env, tcg_op, tcg_imm);
201
- tcg_temp_free_i32(tcg_imm);
202
- tcg_temp_free_i32(tcg_op);
203
- /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
204
- gen_a64_set_pc_im(s->pc);
205
- s->base.is_jmp = (op == 0x1f ? DISAS_EXIT : DISAS_JUMP);
206
+ t1 = tcg_const_i32(crm & PSTATE_SP);
207
+ gen_helper_msr_i_spsel(cpu_env, t1);
208
+ tcg_temp_free_i32(t1);
209
break;
210
- }
211
+
212
+ case 0x1e: /* DAIFSet */
213
+ t1 = tcg_const_i32(crm);
214
+ gen_helper_msr_i_daifset(cpu_env, t1);
215
+ tcg_temp_free_i32(t1);
216
+ break;
217
+
218
+ case 0x1f: /* DAIFClear */
219
+ t1 = tcg_const_i32(crm);
220
+ gen_helper_msr_i_daifclear(cpu_env, t1);
221
+ tcg_temp_free_i32(t1);
222
+ /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. */
223
+ s->base.is_jmp = DISAS_UPDATE;
224
+ break;
225
+
226
default:
227
+ do_unallocated:
228
unallocated_encoding(s);
229
return;
230
}
231
--
968
--
232
2.20.1
969
2.20.1
233
970
234
971
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Hao Wu <wuhaotsh@google.com>
2
2
3
Up to now the memory map has been static and the high IO region
3
The PWM module is part of NPCM7XX module. Each NPCM7XX module has two
4
base has always been 256GiB.
4
identical PWM modules. Each module contains 4 PWM entries. Each PWM has
5
two outputs: frequency and duty_cycle. Both are computed using inputs
6
from software side.
5
7
6
This patch modifies the virt_set_memmap() function, which freezes
8
This module does not model detail pulse signals since it is expensive.
7
the memory map, so that the high IO range base becomes floating,
9
It also does not model interrupts and watchdogs that are dependant on
8
located after the initial RAM and the device memory.
10
the detail models. The interfaces for these are left in the module so
11
that anyone in need for these functionalities can implement on their
12
own.
9
13
10
The function computes
14
The user can read the duty cycle and frequency using qom-get command.
11
- the base of the device memory,
12
- the size of the device memory,
13
- the high IO region base
14
- the highest GPA used in the memory map.
15
15
16
Entries of the high IO region are assigned a base address. The
16
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
17
device memory is initialized.
17
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
18
18
Signed-off-by: Hao Wu <wuhaotsh@google.com>
19
The highest GPA used in the memory map will be used at VM creation
19
Message-id: 20210108190945.949196-5-wuhaotsh@google.com
20
to choose the requested IPA size.
20
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
21
22
Setting all the existing highmem IO regions beyond the RAM
23
allows to have a single contiguous RAM region (initial RAM and
24
possible hotpluggable device memory). That way we do not need
25
to do invasive changes in the EDK2 FW to support a dynamic
26
RAM base.
27
28
Still the user cannot request an initial RAM size greater than 255GB.
29
30
Signed-off-by: Eric Auger <eric.auger@redhat.com>
31
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
32
Message-id: 20190304101339.25970-8-eric.auger@redhat.com
33
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
34
---
22
---
35
include/hw/arm/virt.h | 1 +
23
docs/system/arm/nuvoton.rst | 2 +-
36
hw/arm/virt.c | 52 ++++++++++++++++++++++++++++++++++++++-----
24
include/hw/arm/npcm7xx.h | 2 +
37
2 files changed, 47 insertions(+), 6 deletions(-)
25
include/hw/misc/npcm7xx_pwm.h | 105 +++++++
26
hw/arm/npcm7xx.c | 26 +-
27
hw/misc/npcm7xx_pwm.c | 550 ++++++++++++++++++++++++++++++++++
28
hw/misc/meson.build | 1 +
29
hw/misc/trace-events | 6 +
30
7 files changed, 689 insertions(+), 3 deletions(-)
31
create mode 100644 include/hw/misc/npcm7xx_pwm.h
32
create mode 100644 hw/misc/npcm7xx_pwm.c
38
33
39
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
34
diff --git a/docs/system/arm/nuvoton.rst b/docs/system/arm/nuvoton.rst
40
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
41
--- a/include/hw/arm/virt.h
36
--- a/docs/system/arm/nuvoton.rst
42
+++ b/include/hw/arm/virt.h
37
+++ b/docs/system/arm/nuvoton.rst
43
@@ -XXX,XX +XXX,XX @@ typedef struct {
38
@@ -XXX,XX +XXX,XX @@ Supported devices
44
uint32_t msi_phandle;
39
* USB host (USBH)
45
uint32_t iommu_phandle;
40
* GPIO controller
46
int psci_conduit;
41
* Analog to Digital Converter (ADC)
47
+ hwaddr highest_gpa;
42
+ * Pulse Width Modulation (PWM)
48
} VirtMachineState;
43
49
44
Missing devices
50
#define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)
45
---------------
51
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
46
@@ -XXX,XX +XXX,XX @@ Missing devices
47
* Peripheral SPI controller (PSPI)
48
* SD/MMC host
49
* PECI interface
50
- * Pulse Width Modulation (PWM)
51
* Tachometer
52
* PCI and PCIe root complex and bridges
53
* VDM and MCTP support
54
diff --git a/include/hw/arm/npcm7xx.h b/include/hw/arm/npcm7xx.h
52
index XXXXXXX..XXXXXXX 100644
55
index XXXXXXX..XXXXXXX 100644
53
--- a/hw/arm/virt.c
56
--- a/include/hw/arm/npcm7xx.h
54
+++ b/hw/arm/virt.c
57
+++ b/include/hw/arm/npcm7xx.h
55
@@ -XXX,XX +XXX,XX @@
58
@@ -XXX,XX +XXX,XX @@
56
#include "qapi/visitor.h"
59
#include "hw/mem/npcm7xx_mc.h"
57
#include "standard-headers/linux/input.h"
60
#include "hw/misc/npcm7xx_clk.h"
58
#include "hw/arm/smmuv3.h"
61
#include "hw/misc/npcm7xx_gcr.h"
59
+#include "hw/acpi/acpi.h"
62
+#include "hw/misc/npcm7xx_pwm.h"
60
63
#include "hw/misc/npcm7xx_rng.h"
61
#define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
64
#include "hw/nvram/npcm7xx_otp.h"
62
static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
65
#include "hw/timer/npcm7xx_timer.h"
66
@@ -XXX,XX +XXX,XX @@ typedef struct NPCM7xxState {
67
NPCM7xxCLKState clk;
68
NPCM7xxTimerCtrlState tim[3];
69
NPCM7xxADCState adc;
70
+ NPCM7xxPWMState pwm[2];
71
NPCM7xxOTPState key_storage;
72
NPCM7xxOTPState fuse_array;
73
NPCM7xxMCState mc;
74
diff --git a/include/hw/misc/npcm7xx_pwm.h b/include/hw/misc/npcm7xx_pwm.h
75
new file mode 100644
76
index XXXXXXX..XXXXXXX
77
--- /dev/null
78
+++ b/include/hw/misc/npcm7xx_pwm.h
63
@@ -XXX,XX +XXX,XX @@
79
@@ -XXX,XX +XXX,XX @@
64
* of a terabyte of RAM will be doing it on a host with more than a
80
+/*
65
* terabyte of physical address space.)
81
+ * Nuvoton NPCM7xx PWM Module
66
*/
82
+ *
67
-#define RAMLIMIT_GB 255
83
+ * Copyright 2020 Google LLC
68
-#define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024)
84
+ *
69
+#define LEGACY_RAMLIMIT_GB 255
85
+ * This program is free software; you can redistribute it and/or modify it
70
+#define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)
86
+ * under the terms of the GNU General Public License as published by the
71
87
+ * Free Software Foundation; either version 2 of the License, or
72
/* Addresses and sizes of our components.
88
+ * (at your option) any later version.
73
* 0..128MB is space for a flash device so we can run bootrom code such as UEFI.
89
+ *
74
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry base_memmap[] = {
90
+ * This program is distributed in the hope that it will be useful, but WITHOUT
75
[VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },
91
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
76
[VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
92
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
77
[VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
93
+ * for more details.
78
- [VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES },
94
+ */
79
+ /* Actual RAM size depends on initial RAM and device memory settings */
95
+#ifndef NPCM7XX_PWM_H
80
+ [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES },
96
+#define NPCM7XX_PWM_H
97
+
98
+#include "hw/clock.h"
99
+#include "hw/sysbus.h"
100
+#include "hw/irq.h"
101
+
102
+/* Each PWM module holds 4 PWM channels. */
103
+#define NPCM7XX_PWM_PER_MODULE 4
104
+
105
+/*
106
+ * Number of registers in one pwm module. Don't change this without increasing
107
+ * the version_id in vmstate.
108
+ */
109
+#define NPCM7XX_PWM_NR_REGS (0x54 / sizeof(uint32_t))
110
+
111
+/*
112
+ * The maximum duty values. Each duty unit represents 1/NPCM7XX_PWM_MAX_DUTY
113
+ * cycles. For example, if NPCM7XX_PWM_MAX_DUTY=1,000,000 and a PWM has a duty
114
+ * value of 100,000 the duty cycle for that PWM is 10%.
115
+ */
116
+#define NPCM7XX_PWM_MAX_DUTY 1000000
117
+
118
+typedef struct NPCM7xxPWMState NPCM7xxPWMState;
119
+
120
+/**
121
+ * struct NPCM7xxPWM - The state of a single PWM channel.
122
+ * @module: The PWM module that contains this channel.
123
+ * @irq: GIC interrupt line to fire on expiration if enabled.
124
+ * @running: Whether this PWM channel is generating output.
125
+ * @inverted: Whether this PWM channel is inverted.
126
+ * @index: The index of this PWM channel.
127
+ * @cnr: The counter register.
128
+ * @cmr: The comparator register.
129
+ * @pdr: The data register.
130
+ * @pwdr: The watchdog register.
131
+ * @freq: The frequency of this PWM channel.
132
+ * @duty: The duty cycle of this PWM channel. One unit represents
133
+ * 1/NPCM7XX_MAX_DUTY cycles.
134
+ */
135
+typedef struct NPCM7xxPWM {
136
+ NPCM7xxPWMState *module;
137
+
138
+ qemu_irq irq;
139
+
140
+ bool running;
141
+ bool inverted;
142
+
143
+ uint8_t index;
144
+ uint32_t cnr;
145
+ uint32_t cmr;
146
+ uint32_t pdr;
147
+ uint32_t pwdr;
148
+
149
+ uint32_t freq;
150
+ uint32_t duty;
151
+} NPCM7xxPWM;
152
+
153
+/**
154
+ * struct NPCM7xxPWMState - Pulse Width Modulation device state.
155
+ * @parent: System bus device.
156
+ * @iomem: Memory region through which registers are accessed.
157
+ * @clock: The PWM clock.
158
+ * @pwm: The PWM channels owned by this module.
159
+ * @ppr: The prescaler register.
160
+ * @csr: The clock selector register.
161
+ * @pcr: The control register.
162
+ * @pier: The interrupt enable register.
163
+ * @piir: The interrupt indication register.
164
+ */
165
+struct NPCM7xxPWMState {
166
+ SysBusDevice parent;
167
+
168
+ MemoryRegion iomem;
169
+
170
+ Clock *clock;
171
+ NPCM7xxPWM pwm[NPCM7XX_PWM_PER_MODULE];
172
+
173
+ uint32_t ppr;
174
+ uint32_t csr;
175
+ uint32_t pcr;
176
+ uint32_t pier;
177
+ uint32_t piir;
178
+};
179
+
180
+#define TYPE_NPCM7XX_PWM "npcm7xx-pwm"
181
+#define NPCM7XX_PWM(obj) \
182
+ OBJECT_CHECK(NPCM7xxPWMState, (obj), TYPE_NPCM7XX_PWM)
183
+
184
+#endif /* NPCM7XX_PWM_H */
185
diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c
186
index XXXXXXX..XXXXXXX 100644
187
--- a/hw/arm/npcm7xx.c
188
+++ b/hw/arm/npcm7xx.c
189
@@ -XXX,XX +XXX,XX @@ enum NPCM7xxInterrupt {
190
NPCM7XX_WDG2_IRQ, /* Timer Module 2 Watchdog */
191
NPCM7XX_EHCI_IRQ = 61,
192
NPCM7XX_OHCI_IRQ = 62,
193
+ NPCM7XX_PWM0_IRQ = 93, /* PWM module 0 */
194
+ NPCM7XX_PWM1_IRQ, /* PWM module 1 */
195
NPCM7XX_GPIO0_IRQ = 116,
196
NPCM7XX_GPIO1_IRQ,
197
NPCM7XX_GPIO2_IRQ,
198
@@ -XXX,XX +XXX,XX @@ static const hwaddr npcm7xx_fiu3_flash_addr[] = {
199
0xb8000000, /* CS3 */
81
};
200
};
82
201
83
/*
202
+/* Register base address for each PWM Module */
84
@@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)
203
+static const hwaddr npcm7xx_pwm_addr[] = {
85
204
+ 0xf0103000,
86
static void virt_set_memmap(VirtMachineState *vms)
205
+ 0xf0104000,
87
{
206
+};
88
- hwaddr base;
207
+
89
+ MachineState *ms = MACHINE(vms);
208
static const struct {
90
+ hwaddr base, device_memory_base, device_memory_size;
209
hwaddr regs_addr;
91
int i;
210
uint32_t unconnected_pins;
92
211
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_init(Object *obj)
93
vms->memmap = extended_memmap;
212
object_initialize_child(obj, npcm7xx_fiu[i].name, &s->fiu[i],
94
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms)
213
TYPE_NPCM7XX_FIU);
95
vms->memmap[i] = base_memmap[i];
96
}
214
}
97
215
+
98
- base = 256 * GiB; /* Top of the legacy initial RAM region */
216
+ for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
99
+ if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) {
217
+ object_initialize_child(obj, "pwm[*]", &s->pwm[i], TYPE_NPCM7XX_PWM);
100
+ error_report("unsupported number of memory slots: %"PRIu64,
101
+ ms->ram_slots);
102
+ exit(EXIT_FAILURE);
103
+ }
104
+
105
+ /*
106
+ * We compute the base of the high IO region depending on the
107
+ * amount of initial and device memory. The device memory start/size
108
+ * is aligned on 1GiB. We never put the high IO region below 256GiB
109
+ * so that if maxram_size is < 255GiB we keep the legacy memory map.
110
+ * The device region size assumes 1GiB page max alignment per slot.
111
+ */
112
+ device_memory_base =
113
+ ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);
114
+ device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;
115
+
116
+ /* Base address of the high IO region */
117
+ base = device_memory_base + ROUND_UP(device_memory_size, GiB);
118
+ if (base < device_memory_base) {
119
+ error_report("maxmem/slots too huge");
120
+ exit(EXIT_FAILURE);
121
+ }
122
+ if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {
123
+ base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;
124
+ }
125
126
for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {
127
hwaddr size = extended_memmap[i].size;
128
@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms)
129
vms->memmap[i].size = size;
130
base += size;
131
}
132
+ vms->highest_gpa = base - 1;
133
+ if (device_memory_size > 0) {
134
+ ms->device_memory = g_malloc0(sizeof(*ms->device_memory));
135
+ ms->device_memory->base = device_memory_base;
136
+ memory_region_init(&ms->device_memory->mr, OBJECT(vms),
137
+ "device-memory", device_memory_size);
138
+ }
218
+ }
139
}
219
}
140
220
141
static void machvirt_init(MachineState *machine)
221
static void npcm7xx_realize(DeviceState *dev, Error **errp)
142
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
222
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
143
vms->smp_cpus = smp_cpus;
223
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci), 0,
144
224
npcm7xx_irq(s, NPCM7XX_OHCI_IRQ));
145
if (machine->ram_size > vms->memmap[VIRT_MEM].size) {
225
146
- error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB);
226
+ /* PWM Modules. Cannot fail. */
147
+ error_report("mach-virt: cannot model more than %dGB RAM",
227
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_pwm_addr) != ARRAY_SIZE(s->pwm));
148
+ LEGACY_RAMLIMIT_GB);
228
+ for (i = 0; i < ARRAY_SIZE(s->pwm); i++) {
149
exit(1);
229
+ SysBusDevice *sbd = SYS_BUS_DEVICE(&s->pwm[i]);
150
}
230
+
151
231
+ qdev_connect_clock_in(DEVICE(&s->pwm[i]), "clock", qdev_get_clock_out(
152
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
232
+ DEVICE(&s->clk), "apb3-clock"));
153
memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram",
233
+ sysbus_realize(sbd, &error_abort);
154
machine->ram_size);
234
+ sysbus_mmio_map(sbd, 0, npcm7xx_pwm_addr[i]);
155
memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram);
235
+ sysbus_connect_irq(sbd, i, npcm7xx_irq(s, NPCM7XX_PWM0_IRQ + i));
156
+ if (machine->device_memory) {
236
+ }
157
+ memory_region_add_subregion(sysmem, machine->device_memory->base,
237
+
158
+ &machine->device_memory->mr);
238
/*
159
+ }
239
* Flash Interface Unit (FIU). Can fail if incorrect number of chip selects
160
240
* specified, but this is a programming error.
161
create_flash(vms, sysmem, secure_sysmem ? secure_sysmem : sysmem);
241
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_realize(DeviceState *dev, Error **errp)
162
242
create_unimplemented_device("npcm7xx.peci", 0xf0100000, 4 * KiB);
243
create_unimplemented_device("npcm7xx.siox[1]", 0xf0101000, 4 * KiB);
244
create_unimplemented_device("npcm7xx.siox[2]", 0xf0102000, 4 * KiB);
245
- create_unimplemented_device("npcm7xx.pwm[0]", 0xf0103000, 4 * KiB);
246
- create_unimplemented_device("npcm7xx.pwm[1]", 0xf0104000, 4 * KiB);
247
create_unimplemented_device("npcm7xx.mft[0]", 0xf0180000, 4 * KiB);
248
create_unimplemented_device("npcm7xx.mft[1]", 0xf0181000, 4 * KiB);
249
create_unimplemented_device("npcm7xx.mft[2]", 0xf0182000, 4 * KiB);
250
diff --git a/hw/misc/npcm7xx_pwm.c b/hw/misc/npcm7xx_pwm.c
251
new file mode 100644
252
index XXXXXXX..XXXXXXX
253
--- /dev/null
254
+++ b/hw/misc/npcm7xx_pwm.c
255
@@ -XXX,XX +XXX,XX @@
256
+/*
257
+ * Nuvoton NPCM7xx PWM Module
258
+ *
259
+ * Copyright 2020 Google LLC
260
+ *
261
+ * This program is free software; you can redistribute it and/or modify it
262
+ * under the terms of the GNU General Public License as published by the
263
+ * Free Software Foundation; either version 2 of the License, or
264
+ * (at your option) any later version.
265
+ *
266
+ * This program is distributed in the hope that it will be useful, but WITHOUT
267
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
268
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
269
+ * for more details.
270
+ */
271
+
272
+#include "qemu/osdep.h"
273
+#include "hw/irq.h"
274
+#include "hw/qdev-clock.h"
275
+#include "hw/qdev-properties.h"
276
+#include "hw/misc/npcm7xx_pwm.h"
277
+#include "hw/registerfields.h"
278
+#include "migration/vmstate.h"
279
+#include "qemu/bitops.h"
280
+#include "qemu/error-report.h"
281
+#include "qemu/log.h"
282
+#include "qemu/module.h"
283
+#include "qemu/units.h"
284
+#include "trace.h"
285
+
286
+REG32(NPCM7XX_PWM_PPR, 0x00);
287
+REG32(NPCM7XX_PWM_CSR, 0x04);
288
+REG32(NPCM7XX_PWM_PCR, 0x08);
289
+REG32(NPCM7XX_PWM_CNR0, 0x0c);
290
+REG32(NPCM7XX_PWM_CMR0, 0x10);
291
+REG32(NPCM7XX_PWM_PDR0, 0x14);
292
+REG32(NPCM7XX_PWM_CNR1, 0x18);
293
+REG32(NPCM7XX_PWM_CMR1, 0x1c);
294
+REG32(NPCM7XX_PWM_PDR1, 0x20);
295
+REG32(NPCM7XX_PWM_CNR2, 0x24);
296
+REG32(NPCM7XX_PWM_CMR2, 0x28);
297
+REG32(NPCM7XX_PWM_PDR2, 0x2c);
298
+REG32(NPCM7XX_PWM_CNR3, 0x30);
299
+REG32(NPCM7XX_PWM_CMR3, 0x34);
300
+REG32(NPCM7XX_PWM_PDR3, 0x38);
301
+REG32(NPCM7XX_PWM_PIER, 0x3c);
302
+REG32(NPCM7XX_PWM_PIIR, 0x40);
303
+REG32(NPCM7XX_PWM_PWDR0, 0x44);
304
+REG32(NPCM7XX_PWM_PWDR1, 0x48);
305
+REG32(NPCM7XX_PWM_PWDR2, 0x4c);
306
+REG32(NPCM7XX_PWM_PWDR3, 0x50);
307
+
308
+/* Register field definitions. */
309
+#define NPCM7XX_PPR(rv, index) extract32((rv), npcm7xx_ppr_base[index], 8)
310
+#define NPCM7XX_CSR(rv, index) extract32((rv), npcm7xx_csr_base[index], 3)
311
+#define NPCM7XX_CH(rv, index) extract32((rv), npcm7xx_ch_base[index], 4)
312
+#define NPCM7XX_CH_EN BIT(0)
313
+#define NPCM7XX_CH_INV BIT(2)
314
+#define NPCM7XX_CH_MOD BIT(3)
315
+
316
+/* Offset of each PWM channel's prescaler in the PPR register. */
317
+static const int npcm7xx_ppr_base[] = { 0, 0, 8, 8 };
318
+/* Offset of each PWM channel's clock selector in the CSR register. */
319
+static const int npcm7xx_csr_base[] = { 0, 4, 8, 12 };
320
+/* Offset of each PWM channel's control variable in the PCR register. */
321
+static const int npcm7xx_ch_base[] = { 0, 8, 12, 16 };
322
+
323
+static uint32_t npcm7xx_pwm_calculate_freq(NPCM7xxPWM *p)
324
+{
325
+ uint32_t ppr;
326
+ uint32_t csr;
327
+ uint32_t freq;
328
+
329
+ if (!p->running) {
330
+ return 0;
331
+ }
332
+
333
+ csr = NPCM7XX_CSR(p->module->csr, p->index);
334
+ ppr = NPCM7XX_PPR(p->module->ppr, p->index);
335
+ freq = clock_get_hz(p->module->clock);
336
+ freq /= ppr + 1;
337
+ /* csr can only be 0~4 */
338
+ if (csr > 4) {
339
+ qemu_log_mask(LOG_GUEST_ERROR,
340
+ "%s: invalid csr value %u\n",
341
+ __func__, csr);
342
+ csr = 4;
343
+ }
344
+ /* freq won't be changed if csr == 4. */
345
+ if (csr < 4) {
346
+ freq >>= csr + 1;
347
+ }
348
+
349
+ return freq / (p->cnr + 1);
350
+}
351
+
352
+static uint32_t npcm7xx_pwm_calculate_duty(NPCM7xxPWM *p)
353
+{
354
+ uint64_t duty;
355
+
356
+ if (p->running) {
357
+ if (p->cnr == 0) {
358
+ duty = 0;
359
+ } else if (p->cmr >= p->cnr) {
360
+ duty = NPCM7XX_PWM_MAX_DUTY;
361
+ } else {
362
+ duty = NPCM7XX_PWM_MAX_DUTY * (p->cmr + 1) / (p->cnr + 1);
363
+ }
364
+ } else {
365
+ duty = 0;
366
+ }
367
+
368
+ if (p->inverted) {
369
+ duty = NPCM7XX_PWM_MAX_DUTY - duty;
370
+ }
371
+
372
+ return duty;
373
+}
374
+
375
+static void npcm7xx_pwm_update_freq(NPCM7xxPWM *p)
376
+{
377
+ uint32_t freq = npcm7xx_pwm_calculate_freq(p);
378
+
379
+ if (freq != p->freq) {
380
+ trace_npcm7xx_pwm_update_freq(DEVICE(p->module)->canonical_path,
381
+ p->index, p->freq, freq);
382
+ p->freq = freq;
383
+ }
384
+}
385
+
386
+static void npcm7xx_pwm_update_duty(NPCM7xxPWM *p)
387
+{
388
+ uint32_t duty = npcm7xx_pwm_calculate_duty(p);
389
+
390
+ if (duty != p->duty) {
391
+ trace_npcm7xx_pwm_update_duty(DEVICE(p->module)->canonical_path,
392
+ p->index, p->duty, duty);
393
+ p->duty = duty;
394
+ }
395
+}
396
+
397
+static void npcm7xx_pwm_update_output(NPCM7xxPWM *p)
398
+{
399
+ npcm7xx_pwm_update_freq(p);
400
+ npcm7xx_pwm_update_duty(p);
401
+}
402
+
403
+static void npcm7xx_pwm_write_ppr(NPCM7xxPWMState *s, uint32_t new_ppr)
404
+{
405
+ int i;
406
+ uint32_t old_ppr = s->ppr;
407
+
408
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ppr_base) != NPCM7XX_PWM_PER_MODULE);
409
+ s->ppr = new_ppr;
410
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
411
+ if (NPCM7XX_PPR(old_ppr, i) != NPCM7XX_PPR(new_ppr, i)) {
412
+ npcm7xx_pwm_update_freq(&s->pwm[i]);
413
+ }
414
+ }
415
+}
416
+
417
+static void npcm7xx_pwm_write_csr(NPCM7xxPWMState *s, uint32_t new_csr)
418
+{
419
+ int i;
420
+ uint32_t old_csr = s->csr;
421
+
422
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_csr_base) != NPCM7XX_PWM_PER_MODULE);
423
+ s->csr = new_csr;
424
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
425
+ if (NPCM7XX_CSR(old_csr, i) != NPCM7XX_CSR(new_csr, i)) {
426
+ npcm7xx_pwm_update_freq(&s->pwm[i]);
427
+ }
428
+ }
429
+}
430
+
431
+static void npcm7xx_pwm_write_pcr(NPCM7xxPWMState *s, uint32_t new_pcr)
432
+{
433
+ int i;
434
+ bool inverted;
435
+ uint32_t pcr;
436
+ NPCM7xxPWM *p;
437
+
438
+ s->pcr = new_pcr;
439
+ QEMU_BUILD_BUG_ON(ARRAY_SIZE(npcm7xx_ch_base) != NPCM7XX_PWM_PER_MODULE);
440
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
441
+ p = &s->pwm[i];
442
+ pcr = NPCM7XX_CH(new_pcr, i);
443
+ inverted = pcr & NPCM7XX_CH_INV;
444
+
445
+ /*
446
+ * We only run a PWM channel with toggle mode. Single-shot mode does not
447
+ * generate frequency and duty-cycle values.
448
+ */
449
+ if ((pcr & NPCM7XX_CH_EN) && (pcr & NPCM7XX_CH_MOD)) {
450
+ if (p->running) {
451
+ /* Re-run this PWM channel if inverted changed. */
452
+ if (p->inverted ^ inverted) {
453
+ p->inverted = inverted;
454
+ npcm7xx_pwm_update_duty(p);
455
+ }
456
+ } else {
457
+ /* Run this PWM channel. */
458
+ p->running = true;
459
+ p->inverted = inverted;
460
+ npcm7xx_pwm_update_output(p);
461
+ }
462
+ } else {
463
+ /* Clear this PWM channel. */
464
+ p->running = false;
465
+ p->inverted = inverted;
466
+ npcm7xx_pwm_update_output(p);
467
+ }
468
+ }
469
+
470
+}
471
+
472
+static hwaddr npcm7xx_cnr_index(hwaddr offset)
473
+{
474
+ switch (offset) {
475
+ case A_NPCM7XX_PWM_CNR0:
476
+ return 0;
477
+ case A_NPCM7XX_PWM_CNR1:
478
+ return 1;
479
+ case A_NPCM7XX_PWM_CNR2:
480
+ return 2;
481
+ case A_NPCM7XX_PWM_CNR3:
482
+ return 3;
483
+ default:
484
+ g_assert_not_reached();
485
+ }
486
+}
487
+
488
+static hwaddr npcm7xx_cmr_index(hwaddr offset)
489
+{
490
+ switch (offset) {
491
+ case A_NPCM7XX_PWM_CMR0:
492
+ return 0;
493
+ case A_NPCM7XX_PWM_CMR1:
494
+ return 1;
495
+ case A_NPCM7XX_PWM_CMR2:
496
+ return 2;
497
+ case A_NPCM7XX_PWM_CMR3:
498
+ return 3;
499
+ default:
500
+ g_assert_not_reached();
501
+ }
502
+}
503
+
504
+static hwaddr npcm7xx_pdr_index(hwaddr offset)
505
+{
506
+ switch (offset) {
507
+ case A_NPCM7XX_PWM_PDR0:
508
+ return 0;
509
+ case A_NPCM7XX_PWM_PDR1:
510
+ return 1;
511
+ case A_NPCM7XX_PWM_PDR2:
512
+ return 2;
513
+ case A_NPCM7XX_PWM_PDR3:
514
+ return 3;
515
+ default:
516
+ g_assert_not_reached();
517
+ }
518
+}
519
+
520
+static hwaddr npcm7xx_pwdr_index(hwaddr offset)
521
+{
522
+ switch (offset) {
523
+ case A_NPCM7XX_PWM_PWDR0:
524
+ return 0;
525
+ case A_NPCM7XX_PWM_PWDR1:
526
+ return 1;
527
+ case A_NPCM7XX_PWM_PWDR2:
528
+ return 2;
529
+ case A_NPCM7XX_PWM_PWDR3:
530
+ return 3;
531
+ default:
532
+ g_assert_not_reached();
533
+ }
534
+}
535
+
536
+static uint64_t npcm7xx_pwm_read(void *opaque, hwaddr offset, unsigned size)
537
+{
538
+ NPCM7xxPWMState *s = opaque;
539
+ uint64_t value = 0;
540
+
541
+ switch (offset) {
542
+ case A_NPCM7XX_PWM_CNR0:
543
+ case A_NPCM7XX_PWM_CNR1:
544
+ case A_NPCM7XX_PWM_CNR2:
545
+ case A_NPCM7XX_PWM_CNR3:
546
+ value = s->pwm[npcm7xx_cnr_index(offset)].cnr;
547
+ break;
548
+
549
+ case A_NPCM7XX_PWM_CMR0:
550
+ case A_NPCM7XX_PWM_CMR1:
551
+ case A_NPCM7XX_PWM_CMR2:
552
+ case A_NPCM7XX_PWM_CMR3:
553
+ value = s->pwm[npcm7xx_cmr_index(offset)].cmr;
554
+ break;
555
+
556
+ case A_NPCM7XX_PWM_PDR0:
557
+ case A_NPCM7XX_PWM_PDR1:
558
+ case A_NPCM7XX_PWM_PDR2:
559
+ case A_NPCM7XX_PWM_PDR3:
560
+ value = s->pwm[npcm7xx_pdr_index(offset)].pdr;
561
+ break;
562
+
563
+ case A_NPCM7XX_PWM_PWDR0:
564
+ case A_NPCM7XX_PWM_PWDR1:
565
+ case A_NPCM7XX_PWM_PWDR2:
566
+ case A_NPCM7XX_PWM_PWDR3:
567
+ value = s->pwm[npcm7xx_pwdr_index(offset)].pwdr;
568
+ break;
569
+
570
+ case A_NPCM7XX_PWM_PPR:
571
+ value = s->ppr;
572
+ break;
573
+
574
+ case A_NPCM7XX_PWM_CSR:
575
+ value = s->csr;
576
+ break;
577
+
578
+ case A_NPCM7XX_PWM_PCR:
579
+ value = s->pcr;
580
+ break;
581
+
582
+ case A_NPCM7XX_PWM_PIER:
583
+ value = s->pier;
584
+ break;
585
+
586
+ case A_NPCM7XX_PWM_PIIR:
587
+ value = s->piir;
588
+ break;
589
+
590
+ default:
591
+ qemu_log_mask(LOG_GUEST_ERROR,
592
+ "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
593
+ __func__, offset);
594
+ break;
595
+ }
596
+
597
+ trace_npcm7xx_pwm_read(DEVICE(s)->canonical_path, offset, value);
598
+ return value;
599
+}
600
+
601
+static void npcm7xx_pwm_write(void *opaque, hwaddr offset,
602
+ uint64_t v, unsigned size)
603
+{
604
+ NPCM7xxPWMState *s = opaque;
605
+ NPCM7xxPWM *p;
606
+ uint32_t value = v;
607
+
608
+ trace_npcm7xx_pwm_write(DEVICE(s)->canonical_path, offset, value);
609
+ switch (offset) {
610
+ case A_NPCM7XX_PWM_CNR0:
611
+ case A_NPCM7XX_PWM_CNR1:
612
+ case A_NPCM7XX_PWM_CNR2:
613
+ case A_NPCM7XX_PWM_CNR3:
614
+ p = &s->pwm[npcm7xx_cnr_index(offset)];
615
+ p->cnr = value;
616
+ npcm7xx_pwm_update_output(p);
617
+ break;
618
+
619
+ case A_NPCM7XX_PWM_CMR0:
620
+ case A_NPCM7XX_PWM_CMR1:
621
+ case A_NPCM7XX_PWM_CMR2:
622
+ case A_NPCM7XX_PWM_CMR3:
623
+ p = &s->pwm[npcm7xx_cmr_index(offset)];
624
+ p->cmr = value;
625
+ npcm7xx_pwm_update_output(p);
626
+ break;
627
+
628
+ case A_NPCM7XX_PWM_PDR0:
629
+ case A_NPCM7XX_PWM_PDR1:
630
+ case A_NPCM7XX_PWM_PDR2:
631
+ case A_NPCM7XX_PWM_PDR3:
632
+ qemu_log_mask(LOG_GUEST_ERROR,
633
+ "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n",
634
+ __func__, offset);
635
+ break;
636
+
637
+ case A_NPCM7XX_PWM_PWDR0:
638
+ case A_NPCM7XX_PWM_PWDR1:
639
+ case A_NPCM7XX_PWM_PWDR2:
640
+ case A_NPCM7XX_PWM_PWDR3:
641
+ qemu_log_mask(LOG_UNIMP,
642
+ "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
643
+ __func__, offset);
644
+ break;
645
+
646
+ case A_NPCM7XX_PWM_PPR:
647
+ npcm7xx_pwm_write_ppr(s, value);
648
+ break;
649
+
650
+ case A_NPCM7XX_PWM_CSR:
651
+ npcm7xx_pwm_write_csr(s, value);
652
+ break;
653
+
654
+ case A_NPCM7XX_PWM_PCR:
655
+ npcm7xx_pwm_write_pcr(s, value);
656
+ break;
657
+
658
+ case A_NPCM7XX_PWM_PIER:
659
+ qemu_log_mask(LOG_UNIMP,
660
+ "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
661
+ __func__, offset);
662
+ break;
663
+
664
+ case A_NPCM7XX_PWM_PIIR:
665
+ qemu_log_mask(LOG_UNIMP,
666
+ "%s: register @ 0x%04" HWADDR_PRIx " is not implemented\n",
667
+ __func__, offset);
668
+ break;
669
+
670
+ default:
671
+ qemu_log_mask(LOG_GUEST_ERROR,
672
+ "%s: invalid offset 0x%04" HWADDR_PRIx "\n",
673
+ __func__, offset);
674
+ break;
675
+ }
676
+}
677
+
678
+static const struct MemoryRegionOps npcm7xx_pwm_ops = {
679
+ .read = npcm7xx_pwm_read,
680
+ .write = npcm7xx_pwm_write,
681
+ .endianness = DEVICE_LITTLE_ENDIAN,
682
+ .valid = {
683
+ .min_access_size = 4,
684
+ .max_access_size = 4,
685
+ .unaligned = false,
686
+ },
687
+};
688
+
689
+static void npcm7xx_pwm_enter_reset(Object *obj, ResetType type)
690
+{
691
+ NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
692
+ int i;
693
+
694
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
695
+ NPCM7xxPWM *p = &s->pwm[i];
696
+
697
+ p->cnr = 0x00000000;
698
+ p->cmr = 0x00000000;
699
+ p->pdr = 0x00000000;
700
+ p->pwdr = 0x00000000;
701
+ }
702
+
703
+ s->ppr = 0x00000000;
704
+ s->csr = 0x00000000;
705
+ s->pcr = 0x00000000;
706
+ s->pier = 0x00000000;
707
+ s->piir = 0x00000000;
708
+}
709
+
710
+static void npcm7xx_pwm_hold_reset(Object *obj)
711
+{
712
+ NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
713
+ int i;
714
+
715
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
716
+ qemu_irq_lower(s->pwm[i].irq);
717
+ }
718
+}
719
+
720
+static void npcm7xx_pwm_init(Object *obj)
721
+{
722
+ NPCM7xxPWMState *s = NPCM7XX_PWM(obj);
723
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
724
+ int i;
725
+
726
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; i++) {
727
+ NPCM7xxPWM *p = &s->pwm[i];
728
+ p->module = s;
729
+ p->index = i;
730
+ sysbus_init_irq(sbd, &p->irq);
731
+ }
732
+
733
+ memory_region_init_io(&s->iomem, obj, &npcm7xx_pwm_ops, s,
734
+ TYPE_NPCM7XX_PWM, 4 * KiB);
735
+ sysbus_init_mmio(sbd, &s->iomem);
736
+ s->clock = qdev_init_clock_in(DEVICE(s), "clock", NULL, NULL);
737
+
738
+ for (i = 0; i < NPCM7XX_PWM_PER_MODULE; ++i) {
739
+ object_property_add_uint32_ptr(obj, "freq[*]",
740
+ &s->pwm[i].freq, OBJ_PROP_FLAG_READ);
741
+ object_property_add_uint32_ptr(obj, "duty[*]",
742
+ &s->pwm[i].duty, OBJ_PROP_FLAG_READ);
743
+ }
744
+}
745
+
746
+static const VMStateDescription vmstate_npcm7xx_pwm = {
747
+ .name = "npcm7xx-pwm",
748
+ .version_id = 0,
749
+ .minimum_version_id = 0,
750
+ .fields = (VMStateField[]) {
751
+ VMSTATE_BOOL(running, NPCM7xxPWM),
752
+ VMSTATE_BOOL(inverted, NPCM7xxPWM),
753
+ VMSTATE_UINT8(index, NPCM7xxPWM),
754
+ VMSTATE_UINT32(cnr, NPCM7xxPWM),
755
+ VMSTATE_UINT32(cmr, NPCM7xxPWM),
756
+ VMSTATE_UINT32(pdr, NPCM7xxPWM),
757
+ VMSTATE_UINT32(pwdr, NPCM7xxPWM),
758
+ VMSTATE_UINT32(freq, NPCM7xxPWM),
759
+ VMSTATE_UINT32(duty, NPCM7xxPWM),
760
+ VMSTATE_END_OF_LIST(),
761
+ },
762
+};
763
+
764
+static const VMStateDescription vmstate_npcm7xx_pwm_module = {
765
+ .name = "npcm7xx-pwm-module",
766
+ .version_id = 0,
767
+ .minimum_version_id = 0,
768
+ .fields = (VMStateField[]) {
769
+ VMSTATE_CLOCK(clock, NPCM7xxPWMState),
770
+ VMSTATE_STRUCT_ARRAY(pwm, NPCM7xxPWMState,
771
+ NPCM7XX_PWM_PER_MODULE, 0, vmstate_npcm7xx_pwm,
772
+ NPCM7xxPWM),
773
+ VMSTATE_UINT32(ppr, NPCM7xxPWMState),
774
+ VMSTATE_UINT32(csr, NPCM7xxPWMState),
775
+ VMSTATE_UINT32(pcr, NPCM7xxPWMState),
776
+ VMSTATE_UINT32(pier, NPCM7xxPWMState),
777
+ VMSTATE_UINT32(piir, NPCM7xxPWMState),
778
+ VMSTATE_END_OF_LIST(),
779
+ },
780
+};
781
+
782
+static void npcm7xx_pwm_class_init(ObjectClass *klass, void *data)
783
+{
784
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
785
+ DeviceClass *dc = DEVICE_CLASS(klass);
786
+
787
+ dc->desc = "NPCM7xx PWM Controller";
788
+ dc->vmsd = &vmstate_npcm7xx_pwm_module;
789
+ rc->phases.enter = npcm7xx_pwm_enter_reset;
790
+ rc->phases.hold = npcm7xx_pwm_hold_reset;
791
+}
792
+
793
+static const TypeInfo npcm7xx_pwm_info = {
794
+ .name = TYPE_NPCM7XX_PWM,
795
+ .parent = TYPE_SYS_BUS_DEVICE,
796
+ .instance_size = sizeof(NPCM7xxPWMState),
797
+ .class_init = npcm7xx_pwm_class_init,
798
+ .instance_init = npcm7xx_pwm_init,
799
+};
800
+
801
+static void npcm7xx_pwm_register_type(void)
802
+{
803
+ type_register_static(&npcm7xx_pwm_info);
804
+}
805
+type_init(npcm7xx_pwm_register_type);
806
diff --git a/hw/misc/meson.build b/hw/misc/meson.build
807
index XXXXXXX..XXXXXXX 100644
808
--- a/hw/misc/meson.build
809
+++ b/hw/misc/meson.build
810
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_MAINSTONE', if_true: files('mst_fpga.c'))
811
softmmu_ss.add(when: 'CONFIG_NPCM7XX', if_true: files(
812
'npcm7xx_clk.c',
813
'npcm7xx_gcr.c',
814
+ 'npcm7xx_pwm.c',
815
'npcm7xx_rng.c',
816
))
817
softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files(
818
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
819
index XXXXXXX..XXXXXXX 100644
820
--- a/hw/misc/trace-events
821
+++ b/hw/misc/trace-events
822
@@ -XXX,XX +XXX,XX @@ npcm7xx_gcr_write(uint64_t offset, uint32_t value) "offset: 0x%04" PRIx64 " valu
823
npcm7xx_rng_read(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
824
npcm7xx_rng_write(uint64_t offset, uint64_t value, unsigned size) "offset: 0x%04" PRIx64 " value: 0x%02" PRIx64 " size: %u"
825
826
+# npcm7xx_pwm.c
827
+npcm7xx_pwm_read(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
828
+npcm7xx_pwm_write(const char *id, uint64_t offset, uint32_t value) "%s offset: 0x%04" PRIx64 " value: 0x%08" PRIx32
829
+npcm7xx_pwm_update_freq(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Freq: old_freq: %u, new_freq: %u"
830
+npcm7xx_pwm_update_duty(const char *id, uint8_t index, uint32_t old_value, uint32_t new_value) "%s pwm[%u] Update Duty: old_duty: %u, new_duty: %u"
831
+
832
# stm32f4xx_syscfg.c
833
stm32f4xx_syscfg_set_irq(int gpio, int line, int level) "Interupt: GPIO: %d, Line: %d; Level: %d"
834
stm32f4xx_pulse_exti(int irq) "Pulse EXTI: %d"
163
--
835
--
164
2.20.1
836
2.20.1
165
837
166
838
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Hao Wu <wuhaotsh@google.com>
2
2
3
We are about to allow the memory map to grow beyond 1TB and
3
We add a qtest for the PWM in the previous patch. It proves it works as
4
potentially overshoot the VCPU AA64MMFR0.PARANGE.
4
expected.
5
5
6
In aarch64 mode and when highmem is set, let's check the VCPU
6
Reviewed-by: Havard Skinnemoen <hskinnemoen@google.com>
7
PA range is sufficient to address the highest GPA of the memory
7
Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
8
map.
8
Signed-off-by: Hao Wu <wuhaotsh@google.com>
9
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Eric Auger <eric.auger@redhat.com>
10
Message-id: 20210108190945.949196-6-wuhaotsh@google.com
11
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
12
Message-id: 20190304101339.25970-10-eric.auger@redhat.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
12
---
15
hw/arm/virt.c | 17 +++++++++++++++++
13
tests/qtest/npcm7xx_pwm-test.c | 490 +++++++++++++++++++++++++++++++++
16
1 file changed, 17 insertions(+)
14
tests/qtest/meson.build | 1 +
15
2 files changed, 491 insertions(+)
16
create mode 100644 tests/qtest/npcm7xx_pwm-test.c
17
17
18
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
18
diff --git a/tests/qtest/npcm7xx_pwm-test.c b/tests/qtest/npcm7xx_pwm-test.c
19
index XXXXXXX..XXXXXXX 100644
19
new file mode 100644
20
--- a/hw/arm/virt.c
20
index XXXXXXX..XXXXXXX
21
+++ b/hw/arm/virt.c
21
--- /dev/null
22
+++ b/tests/qtest/npcm7xx_pwm-test.c
22
@@ -XXX,XX +XXX,XX @@
23
@@ -XXX,XX +XXX,XX @@
23
#include "standard-headers/linux/input.h"
24
+/*
24
#include "hw/arm/smmuv3.h"
25
+ * QTests for Nuvoton NPCM7xx PWM Modules.
25
#include "hw/acpi/acpi.h"
26
+ *
26
+#include "target/arm/internals.h"
27
+ * Copyright 2020 Google LLC
27
28
+ *
28
#define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \
29
+ * This program is free software; you can redistribute it and/or modify it
29
static void virt_##major##_##minor##_class_init(ObjectClass *oc, \
30
+ * under the terms of the GNU General Public License as published by the
30
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
31
+ * Free Software Foundation; either version 2 of the License, or
31
fdt_add_timer_nodes(vms);
32
+ * (at your option) any later version.
32
fdt_add_cpu_nodes(vms);
33
+ *
33
34
+ * This program is distributed in the hope that it will be useful, but WITHOUT
34
+ if (!kvm_enabled()) {
35
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
35
+ ARMCPU *cpu = ARM_CPU(first_cpu);
36
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
36
+ bool aarch64 = object_property_get_bool(OBJECT(cpu), "aarch64", NULL);
37
+ * for more details.
37
+
38
+ */
38
+ if (aarch64 && vms->highmem) {
39
+
39
+ int requested_pa_size, pamax = arm_pamax(cpu);
40
+#include "qemu/osdep.h"
40
+
41
+#include "qemu/bitops.h"
41
+ requested_pa_size = 64 - clz64(vms->highest_gpa);
42
+#include "libqos/libqtest.h"
42
+ if (pamax < requested_pa_size) {
43
+#include "qapi/qmp/qdict.h"
43
+ error_report("VCPU supports less PA bits (%d) than requested "
44
+#include "qapi/qmp/qnum.h"
44
+ "by the memory map (%d)", pamax, requested_pa_size);
45
+
45
+ exit(1);
46
+#define REF_HZ 25000000
47
+
48
+/* Register field definitions. */
49
+#define CH_EN BIT(0)
50
+#define CH_INV BIT(2)
51
+#define CH_MOD BIT(3)
52
+
53
+/* Registers shared between all PWMs in a module */
54
+#define PPR 0x00
55
+#define CSR 0x04
56
+#define PCR 0x08
57
+#define PIER 0x3c
58
+#define PIIR 0x40
59
+
60
+/* CLK module related */
61
+#define CLK_BA 0xf0801000
62
+#define CLKSEL 0x04
63
+#define CLKDIV1 0x08
64
+#define CLKDIV2 0x2c
65
+#define PLLCON0 0x0c
66
+#define PLLCON1 0x10
67
+#define PLL_INDV(rv) extract32((rv), 0, 6)
68
+#define PLL_FBDV(rv) extract32((rv), 16, 12)
69
+#define PLL_OTDV1(rv) extract32((rv), 8, 3)
70
+#define PLL_OTDV2(rv) extract32((rv), 13, 3)
71
+#define APB3CKDIV(rv) extract32((rv), 28, 2)
72
+#define CLK2CKDIV(rv) extract32((rv), 0, 1)
73
+#define CLK4CKDIV(rv) extract32((rv), 26, 2)
74
+#define CPUCKSEL(rv) extract32((rv), 0, 2)
75
+
76
+#define MAX_DUTY 1000000
77
+
78
+typedef struct PWMModule {
79
+ int irq;
80
+ uint64_t base_addr;
81
+} PWMModule;
82
+
83
+typedef struct PWM {
84
+ uint32_t cnr_offset;
85
+ uint32_t cmr_offset;
86
+ uint32_t pdr_offset;
87
+ uint32_t pwdr_offset;
88
+} PWM;
89
+
90
+typedef struct TestData {
91
+ const PWMModule *module;
92
+ const PWM *pwm;
93
+} TestData;
94
+
95
+static const PWMModule pwm_module_list[] = {
96
+ {
97
+ .irq = 93,
98
+ .base_addr = 0xf0103000
99
+ },
100
+ {
101
+ .irq = 94,
102
+ .base_addr = 0xf0104000
103
+ }
104
+};
105
+
106
+static const PWM pwm_list[] = {
107
+ {
108
+ .cnr_offset = 0x0c,
109
+ .cmr_offset = 0x10,
110
+ .pdr_offset = 0x14,
111
+ .pwdr_offset = 0x44,
112
+ },
113
+ {
114
+ .cnr_offset = 0x18,
115
+ .cmr_offset = 0x1c,
116
+ .pdr_offset = 0x20,
117
+ .pwdr_offset = 0x48,
118
+ },
119
+ {
120
+ .cnr_offset = 0x24,
121
+ .cmr_offset = 0x28,
122
+ .pdr_offset = 0x2c,
123
+ .pwdr_offset = 0x4c,
124
+ },
125
+ {
126
+ .cnr_offset = 0x30,
127
+ .cmr_offset = 0x34,
128
+ .pdr_offset = 0x38,
129
+ .pwdr_offset = 0x50,
130
+ },
131
+};
132
+
133
+static const int ppr_base[] = { 0, 0, 8, 8 };
134
+static const int csr_base[] = { 0, 4, 8, 12 };
135
+static const int pcr_base[] = { 0, 8, 12, 16 };
136
+
137
+static const uint32_t ppr_list[] = {
138
+ 0,
139
+ 1,
140
+ 10,
141
+ 100,
142
+ 255, /* Max possible value. */
143
+};
144
+
145
+static const uint32_t csr_list[] = {
146
+ 0,
147
+ 1,
148
+ 2,
149
+ 3,
150
+ 4, /* Max possible value. */
151
+};
152
+
153
+static const uint32_t cnr_list[] = {
154
+ 0,
155
+ 1,
156
+ 50,
157
+ 100,
158
+ 150,
159
+ 200,
160
+ 1000,
161
+ 10000,
162
+ 65535, /* Max possible value. */
163
+};
164
+
165
+static const uint32_t cmr_list[] = {
166
+ 0,
167
+ 1,
168
+ 10,
169
+ 50,
170
+ 100,
171
+ 150,
172
+ 200,
173
+ 1000,
174
+ 10000,
175
+ 65535, /* Max possible value. */
176
+};
177
+
178
+/* Returns the index of the PWM module. */
179
+static int pwm_module_index(const PWMModule *module)
180
+{
181
+ ptrdiff_t diff = module - pwm_module_list;
182
+
183
+ g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_module_list));
184
+
185
+ return diff;
186
+}
187
+
188
+/* Returns the index of the PWM entry. */
189
+static int pwm_index(const PWM *pwm)
190
+{
191
+ ptrdiff_t diff = pwm - pwm_list;
192
+
193
+ g_assert_true(diff >= 0 && diff < ARRAY_SIZE(pwm_list));
194
+
195
+ return diff;
196
+}
197
+
198
+static uint64_t pwm_qom_get(QTestState *qts, const char *path, const char *name)
199
+{
200
+ QDict *response;
201
+
202
+ g_test_message("Getting properties %s from %s", name, path);
203
+ response = qtest_qmp(qts, "{ 'execute': 'qom-get',"
204
+ " 'arguments': { 'path': %s, 'property': %s}}",
205
+ path, name);
206
+ /* The qom set message returns successfully. */
207
+ g_assert_true(qdict_haskey(response, "return"));
208
+ return qnum_get_uint(qobject_to(QNum, qdict_get(response, "return")));
209
+}
210
+
211
+static uint64_t pwm_get_freq(QTestState *qts, int module_index, int pwm_index)
212
+{
213
+ char path[100];
214
+ char name[100];
215
+
216
+ sprintf(path, "/machine/soc/pwm[%d]", module_index);
217
+ sprintf(name, "freq[%d]", pwm_index);
218
+
219
+ return pwm_qom_get(qts, path, name);
220
+}
221
+
222
+static uint64_t pwm_get_duty(QTestState *qts, int module_index, int pwm_index)
223
+{
224
+ char path[100];
225
+ char name[100];
226
+
227
+ sprintf(path, "/machine/soc/pwm[%d]", module_index);
228
+ sprintf(name, "duty[%d]", pwm_index);
229
+
230
+ return pwm_qom_get(qts, path, name);
231
+}
232
+
233
+static uint32_t get_pll(uint32_t con)
234
+{
235
+ return REF_HZ * PLL_FBDV(con) / (PLL_INDV(con) * PLL_OTDV1(con)
236
+ * PLL_OTDV2(con));
237
+}
238
+
239
+static uint64_t read_pclk(QTestState *qts)
240
+{
241
+ uint64_t freq = REF_HZ;
242
+ uint32_t clksel = qtest_readl(qts, CLK_BA + CLKSEL);
243
+ uint32_t pllcon;
244
+ uint32_t clkdiv1 = qtest_readl(qts, CLK_BA + CLKDIV1);
245
+ uint32_t clkdiv2 = qtest_readl(qts, CLK_BA + CLKDIV2);
246
+
247
+ switch (CPUCKSEL(clksel)) {
248
+ case 0:
249
+ pllcon = qtest_readl(qts, CLK_BA + PLLCON0);
250
+ freq = get_pll(pllcon);
251
+ break;
252
+ case 1:
253
+ pllcon = qtest_readl(qts, CLK_BA + PLLCON1);
254
+ freq = get_pll(pllcon);
255
+ break;
256
+ case 2:
257
+ break;
258
+ case 3:
259
+ break;
260
+ default:
261
+ g_assert_not_reached();
262
+ }
263
+
264
+ freq >>= (CLK2CKDIV(clkdiv1) + CLK4CKDIV(clkdiv1) + APB3CKDIV(clkdiv2));
265
+
266
+ return freq;
267
+}
268
+
269
+static uint32_t pwm_selector(uint32_t csr)
270
+{
271
+ switch (csr) {
272
+ case 0:
273
+ return 2;
274
+ case 1:
275
+ return 4;
276
+ case 2:
277
+ return 8;
278
+ case 3:
279
+ return 16;
280
+ case 4:
281
+ return 1;
282
+ default:
283
+ g_assert_not_reached();
284
+ }
285
+}
286
+
287
+static uint64_t pwm_compute_freq(QTestState *qts, uint32_t ppr, uint32_t csr,
288
+ uint32_t cnr)
289
+{
290
+ return read_pclk(qts) / ((ppr + 1) * pwm_selector(csr) * (cnr + 1));
291
+}
292
+
293
+static uint64_t pwm_compute_duty(uint32_t cnr, uint32_t cmr, bool inverted)
294
+{
295
+ uint64_t duty;
296
+
297
+ if (cnr == 0) {
298
+ /* PWM is stopped. */
299
+ duty = 0;
300
+ } else if (cmr >= cnr) {
301
+ duty = MAX_DUTY;
302
+ } else {
303
+ duty = MAX_DUTY * (cmr + 1) / (cnr + 1);
304
+ }
305
+
306
+ if (inverted) {
307
+ duty = MAX_DUTY - duty;
308
+ }
309
+
310
+ return duty;
311
+}
312
+
313
+static uint32_t pwm_read(QTestState *qts, const TestData *td, unsigned offset)
314
+{
315
+ return qtest_readl(qts, td->module->base_addr + offset);
316
+}
317
+
318
+static void pwm_write(QTestState *qts, const TestData *td, unsigned offset,
319
+ uint32_t value)
320
+{
321
+ qtest_writel(qts, td->module->base_addr + offset, value);
322
+}
323
+
324
+static uint32_t pwm_read_ppr(QTestState *qts, const TestData *td)
325
+{
326
+ return extract32(pwm_read(qts, td, PPR), ppr_base[pwm_index(td->pwm)], 8);
327
+}
328
+
329
+static void pwm_write_ppr(QTestState *qts, const TestData *td, uint32_t value)
330
+{
331
+ pwm_write(qts, td, PPR, value << ppr_base[pwm_index(td->pwm)]);
332
+}
333
+
334
+static uint32_t pwm_read_csr(QTestState *qts, const TestData *td)
335
+{
336
+ return extract32(pwm_read(qts, td, CSR), csr_base[pwm_index(td->pwm)], 3);
337
+}
338
+
339
+static void pwm_write_csr(QTestState *qts, const TestData *td, uint32_t value)
340
+{
341
+ pwm_write(qts, td, CSR, value << csr_base[pwm_index(td->pwm)]);
342
+}
343
+
344
+static uint32_t pwm_read_pcr(QTestState *qts, const TestData *td)
345
+{
346
+ return extract32(pwm_read(qts, td, PCR), pcr_base[pwm_index(td->pwm)], 4);
347
+}
348
+
349
+static void pwm_write_pcr(QTestState *qts, const TestData *td, uint32_t value)
350
+{
351
+ pwm_write(qts, td, PCR, value << pcr_base[pwm_index(td->pwm)]);
352
+}
353
+
354
+static uint32_t pwm_read_cnr(QTestState *qts, const TestData *td)
355
+{
356
+ return pwm_read(qts, td, td->pwm->cnr_offset);
357
+}
358
+
359
+static void pwm_write_cnr(QTestState *qts, const TestData *td, uint32_t value)
360
+{
361
+ pwm_write(qts, td, td->pwm->cnr_offset, value);
362
+}
363
+
364
+static uint32_t pwm_read_cmr(QTestState *qts, const TestData *td)
365
+{
366
+ return pwm_read(qts, td, td->pwm->cmr_offset);
367
+}
368
+
369
+static void pwm_write_cmr(QTestState *qts, const TestData *td, uint32_t value)
370
+{
371
+ pwm_write(qts, td, td->pwm->cmr_offset, value);
372
+}
373
+
374
+/* Check pwm registers can be reset to default value */
375
+static void test_init(gconstpointer test_data)
376
+{
377
+ const TestData *td = test_data;
378
+ QTestState *qts = qtest_init("-machine quanta-gsj");
379
+ int module = pwm_module_index(td->module);
380
+ int pwm = pwm_index(td->pwm);
381
+
382
+ g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0);
383
+ g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0);
384
+
385
+ qtest_quit(qts);
386
+}
387
+
388
+/* One-shot mode should not change frequency and duty cycle. */
389
+static void test_oneshot(gconstpointer test_data)
390
+{
391
+ const TestData *td = test_data;
392
+ QTestState *qts = qtest_init("-machine quanta-gsj");
393
+ int module = pwm_module_index(td->module);
394
+ int pwm = pwm_index(td->pwm);
395
+ uint32_t ppr, csr, pcr;
396
+ int i, j;
397
+
398
+ pcr = CH_EN;
399
+ for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
400
+ ppr = ppr_list[i];
401
+ pwm_write_ppr(qts, td, ppr);
402
+
403
+ for (j = 0; j < ARRAY_SIZE(csr_list); ++j) {
404
+ csr = csr_list[j];
405
+ pwm_write_csr(qts, td, csr);
406
+ pwm_write_pcr(qts, td, pcr);
407
+
408
+ g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr);
409
+ g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr);
410
+ g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr);
411
+ g_assert_cmpuint(pwm_get_freq(qts, module, pwm), ==, 0);
412
+ g_assert_cmpuint(pwm_get_duty(qts, module, pwm), ==, 0);
413
+ }
414
+ }
415
+
416
+ qtest_quit(qts);
417
+}
418
+
419
+/* In toggle mode, the PWM generates correct outputs. */
420
+static void test_toggle(gconstpointer test_data)
421
+{
422
+ const TestData *td = test_data;
423
+ QTestState *qts = qtest_init("-machine quanta-gsj");
424
+ int module = pwm_module_index(td->module);
425
+ int pwm = pwm_index(td->pwm);
426
+ uint32_t ppr, csr, pcr, cnr, cmr;
427
+ int i, j, k, l;
428
+ uint64_t expected_freq, expected_duty;
429
+
430
+ pcr = CH_EN | CH_MOD;
431
+ for (i = 0; i < ARRAY_SIZE(ppr_list); ++i) {
432
+ ppr = ppr_list[i];
433
+ pwm_write_ppr(qts, td, ppr);
434
+
435
+ for (j = 0; j < ARRAY_SIZE(csr_list); ++j) {
436
+ csr = csr_list[j];
437
+ pwm_write_csr(qts, td, csr);
438
+
439
+ for (k = 0; k < ARRAY_SIZE(cnr_list); ++k) {
440
+ cnr = cnr_list[k];
441
+ pwm_write_cnr(qts, td, cnr);
442
+
443
+ for (l = 0; l < ARRAY_SIZE(cmr_list); ++l) {
444
+ cmr = cmr_list[l];
445
+ pwm_write_cmr(qts, td, cmr);
446
+ expected_freq = pwm_compute_freq(qts, ppr, csr, cnr);
447
+ expected_duty = pwm_compute_duty(cnr, cmr, false);
448
+
449
+ pwm_write_pcr(qts, td, pcr);
450
+ g_assert_cmpuint(pwm_read_ppr(qts, td), ==, ppr);
451
+ g_assert_cmpuint(pwm_read_csr(qts, td), ==, csr);
452
+ g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr);
453
+ g_assert_cmpuint(pwm_read_cnr(qts, td), ==, cnr);
454
+ g_assert_cmpuint(pwm_read_cmr(qts, td), ==, cmr);
455
+ g_assert_cmpuint(pwm_get_duty(qts, module, pwm),
456
+ ==, expected_duty);
457
+ if (expected_duty != 0 && expected_duty != 100) {
458
+ /* Duty cycle with 0 or 100 doesn't need frequency. */
459
+ g_assert_cmpuint(pwm_get_freq(qts, module, pwm),
460
+ ==, expected_freq);
461
+ }
462
+
463
+ /* Test inverted mode */
464
+ expected_duty = pwm_compute_duty(cnr, cmr, true);
465
+ pwm_write_pcr(qts, td, pcr | CH_INV);
466
+ g_assert_cmpuint(pwm_read_pcr(qts, td), ==, pcr | CH_INV);
467
+ g_assert_cmpuint(pwm_get_duty(qts, module, pwm),
468
+ ==, expected_duty);
469
+ if (expected_duty != 0 && expected_duty != 100) {
470
+ /* Duty cycle with 0 or 100 doesn't need frequency. */
471
+ g_assert_cmpuint(pwm_get_freq(qts, module, pwm),
472
+ ==, expected_freq);
473
+ }
474
+
475
+ }
46
+ }
476
+ }
47
+ }
477
+ }
48
+ }
478
+ }
49
+
479
+
50
memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram",
480
+ qtest_quit(qts);
51
machine->ram_size);
481
+}
52
memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram);
482
+
483
+static void pwm_add_test(const char *name, const TestData* td,
484
+ GTestDataFunc fn)
485
+{
486
+ g_autofree char *full_name = g_strdup_printf(
487
+ "npcm7xx_pwm/module[%d]/pwm[%d]/%s", pwm_module_index(td->module),
488
+ pwm_index(td->pwm), name);
489
+ qtest_add_data_func(full_name, td, fn);
490
+}
491
+#define add_test(name, td) pwm_add_test(#name, td, test_##name)
492
+
493
+int main(int argc, char **argv)
494
+{
495
+ TestData test_data_list[ARRAY_SIZE(pwm_module_list) * ARRAY_SIZE(pwm_list)];
496
+
497
+ g_test_init(&argc, &argv, NULL);
498
+
499
+ for (int i = 0; i < ARRAY_SIZE(pwm_module_list); ++i) {
500
+ for (int j = 0; j < ARRAY_SIZE(pwm_list); ++j) {
501
+ TestData *td = &test_data_list[i * ARRAY_SIZE(pwm_list) + j];
502
+
503
+ td->module = &pwm_module_list[i];
504
+ td->pwm = &pwm_list[j];
505
+
506
+ add_test(init, td);
507
+ add_test(oneshot, td);
508
+ add_test(toggle, td);
509
+ }
510
+ }
511
+
512
+ return g_test_run();
513
+}
514
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
515
index XXXXXXX..XXXXXXX 100644
516
--- a/tests/qtest/meson.build
517
+++ b/tests/qtest/meson.build
518
@@ -XXX,XX +XXX,XX @@ qtests_sparc64 = \
519
qtests_npcm7xx = \
520
['npcm7xx_adc-test',
521
'npcm7xx_gpio-test',
522
+ 'npcm7xx_pwm-test',
523
'npcm7xx_rng-test',
524
'npcm7xx_timer-test',
525
'npcm7xx_watchdog_timer-test']
53
--
526
--
54
2.20.1
527
2.20.1
55
528
56
529
diff view generated by jsdifflib
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Hao Wu <wuhaotsh@google.com>
2
2
3
This decoding more closely matches the ARMv8.4 Table C4-6,
3
A device shouldn't access its parent object which is QOM internal.
4
Encoding table for Data Processing - Register Group.
4
Instead it should use type cast for this purporse. This patch fixes this
5
issue for all NPCM7XX Devices.
5
6
6
In particular, op2 == 0 is now more than just Add/sub (with carry).
7
Signed-off-by: Hao Wu <wuhaotsh@google.com>
7
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20190301200501.16533-7-richard.henderson@linaro.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20210108190945.949196-7-wuhaotsh@google.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
11
---
13
target/arm/translate-a64.c | 98 ++++++++++++++++++++++----------------
12
hw/arm/npcm7xx_boards.c | 2 +-
14
1 file changed, 57 insertions(+), 41 deletions(-)
13
hw/mem/npcm7xx_mc.c | 2 +-
14
hw/misc/npcm7xx_clk.c | 2 +-
15
hw/misc/npcm7xx_gcr.c | 2 +-
16
hw/misc/npcm7xx_rng.c | 2 +-
17
hw/nvram/npcm7xx_otp.c | 2 +-
18
hw/ssi/npcm7xx_fiu.c | 2 +-
19
7 files changed, 7 insertions(+), 7 deletions(-)
15
20
16
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
21
diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c
17
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/translate-a64.c
23
--- a/hw/arm/npcm7xx_boards.c
19
+++ b/target/arm/translate-a64.c
24
+++ b/hw/arm/npcm7xx_boards.c
20
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_3src(DisasContext *s, uint32_t insn)
25
@@ -XXX,XX +XXX,XX @@ static NPCM7xxState *npcm7xx_create_soc(MachineState *machine,
26
uint32_t hw_straps)
27
{
28
NPCM7xxMachineClass *nmc = NPCM7XX_MACHINE_GET_CLASS(machine);
29
- MachineClass *mc = &nmc->parent;
30
+ MachineClass *mc = MACHINE_CLASS(nmc);
31
Object *obj;
32
33
if (strcmp(machine->cpu_type, mc->default_cpu_type) != 0) {
34
diff --git a/hw/mem/npcm7xx_mc.c b/hw/mem/npcm7xx_mc.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/hw/mem/npcm7xx_mc.c
37
+++ b/hw/mem/npcm7xx_mc.c
38
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_mc_realize(DeviceState *dev, Error **errp)
39
40
memory_region_init_io(&s->mmio, OBJECT(s), &npcm7xx_mc_ops, s, "regs",
41
NPCM7XX_MC_REGS_SIZE);
42
- sysbus_init_mmio(&s->parent, &s->mmio);
43
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->mmio);
21
}
44
}
22
45
23
/* Add/subtract (with carry)
46
static void npcm7xx_mc_class_init(ObjectClass *klass, void *data)
24
- * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
47
diff --git a/hw/misc/npcm7xx_clk.c b/hw/misc/npcm7xx_clk.c
25
- * +--+--+--+------------------------+------+---------+------+-----+
48
index XXXXXXX..XXXXXXX 100644
26
- * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | opcode2 | Rn | Rd |
49
--- a/hw/misc/npcm7xx_clk.c
27
- * +--+--+--+------------------------+------+---------+------+-----+
50
+++ b/hw/misc/npcm7xx_clk.c
28
- * [000000]
51
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_clk_init(Object *obj)
29
+ * 31 30 29 28 27 26 25 24 23 22 21 20 16 15 10 9 5 4 0
52
30
+ * +--+--+--+------------------------+------+-------------+------+-----+
53
memory_region_init_io(&s->iomem, obj, &npcm7xx_clk_ops, s,
31
+ * |sf|op| S| 1 1 0 1 0 0 0 0 | rm | 0 0 0 0 0 0 | Rn | Rd |
54
TYPE_NPCM7XX_CLK, 4 * KiB);
32
+ * +--+--+--+------------------------+------+-------------+------+-----+
55
- sysbus_init_mmio(&s->parent, &s->iomem);
33
*/
56
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
34
35
static void disas_adc_sbc(DisasContext *s, uint32_t insn)
36
@@ -XXX,XX +XXX,XX @@ static void disas_adc_sbc(DisasContext *s, uint32_t insn)
37
unsigned int sf, op, setflags, rm, rn, rd;
38
TCGv_i64 tcg_y, tcg_rn, tcg_rd;
39
40
- if (extract32(insn, 10, 6) != 0) {
41
- unallocated_encoding(s);
42
- return;
43
- }
44
-
45
sf = extract32(insn, 31, 1);
46
op = extract32(insn, 30, 1);
47
setflags = extract32(insn, 29, 1);
48
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
49
}
50
}
57
}
51
58
52
-/* Data processing - register */
59
static int npcm7xx_clk_post_load(void *opaque, int version_id)
53
+/*
60
diff --git a/hw/misc/npcm7xx_gcr.c b/hw/misc/npcm7xx_gcr.c
54
+ * Data processing - register
61
index XXXXXXX..XXXXXXX 100644
55
+ * 31 30 29 28 25 21 20 16 10 0
62
--- a/hw/misc/npcm7xx_gcr.c
56
+ * +--+---+--+---+-------+-----+-------+-------+---------+
63
+++ b/hw/misc/npcm7xx_gcr.c
57
+ * | |op0| |op1| 1 0 1 | op2 | | op3 | |
64
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_gcr_init(Object *obj)
58
+ * +--+---+--+---+-------+-----+-------+-------+---------+
65
59
+ */
66
memory_region_init_io(&s->iomem, obj, &npcm7xx_gcr_ops, s,
60
static void disas_data_proc_reg(DisasContext *s, uint32_t insn)
67
TYPE_NPCM7XX_GCR, 4 * KiB);
68
- sysbus_init_mmio(&s->parent, &s->iomem);
69
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
70
}
71
72
static const VMStateDescription vmstate_npcm7xx_gcr = {
73
diff --git a/hw/misc/npcm7xx_rng.c b/hw/misc/npcm7xx_rng.c
74
index XXXXXXX..XXXXXXX 100644
75
--- a/hw/misc/npcm7xx_rng.c
76
+++ b/hw/misc/npcm7xx_rng.c
77
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_rng_init(Object *obj)
78
79
memory_region_init_io(&s->iomem, obj, &npcm7xx_rng_ops, s, "regs",
80
NPCM7XX_RNG_REGS_SIZE);
81
- sysbus_init_mmio(&s->parent, &s->iomem);
82
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
83
}
84
85
static const VMStateDescription vmstate_npcm7xx_rng = {
86
diff --git a/hw/nvram/npcm7xx_otp.c b/hw/nvram/npcm7xx_otp.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/hw/nvram/npcm7xx_otp.c
89
+++ b/hw/nvram/npcm7xx_otp.c
90
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_otp_realize(DeviceState *dev, Error **errp)
61
{
91
{
62
- switch (extract32(insn, 24, 5)) {
92
NPCM7xxOTPClass *oc = NPCM7XX_OTP_GET_CLASS(dev);
63
- case 0x0a: /* Logical (shifted register) */
93
NPCM7xxOTPState *s = NPCM7XX_OTP(dev);
64
- disas_logic_reg(s, insn);
94
- SysBusDevice *sbd = &s->parent;
65
- break;
95
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
66
- case 0x0b: /* Add/subtract */
96
67
- if (insn & (1 << 21)) { /* (extended register) */
97
memset(s->array, 0, sizeof(s->array));
68
- disas_add_sub_ext_reg(s, insn);
98
69
+ int op0 = extract32(insn, 30, 1);
99
diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c
70
+ int op1 = extract32(insn, 28, 1);
100
index XXXXXXX..XXXXXXX 100644
71
+ int op2 = extract32(insn, 21, 4);
101
--- a/hw/ssi/npcm7xx_fiu.c
72
+ int op3 = extract32(insn, 10, 6);
102
+++ b/hw/ssi/npcm7xx_fiu.c
73
+
103
@@ -XXX,XX +XXX,XX @@ static void npcm7xx_fiu_hold_reset(Object *obj)
74
+ if (!op1) {
104
static void npcm7xx_fiu_realize(DeviceState *dev, Error **errp)
75
+ if (op2 & 8) {
105
{
76
+ if (op2 & 1) {
106
NPCM7xxFIUState *s = NPCM7XX_FIU(dev);
77
+ /* Add/sub (extended register) */
107
- SysBusDevice *sbd = &s->parent;
78
+ disas_add_sub_ext_reg(s, insn);
108
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
79
+ } else {
109
int i;
80
+ /* Add/sub (shifted register) */
110
81
+ disas_add_sub_reg(s, insn);
111
if (s->cs_count <= 0) {
82
+ }
83
} else {
84
- disas_add_sub_reg(s, insn);
85
+ /* Logical (shifted register) */
86
+ disas_logic_reg(s, insn);
87
}
88
- break;
89
- case 0x1b: /* Data-processing (3 source) */
90
- disas_data_proc_3src(s, insn);
91
- break;
92
- case 0x1a:
93
- switch (extract32(insn, 21, 3)) {
94
- case 0x0: /* Add/subtract (with carry) */
95
+ return;
96
+ }
97
+
98
+ switch (op2) {
99
+ case 0x0:
100
+ switch (op3) {
101
+ case 0x00: /* Add/subtract (with carry) */
102
disas_adc_sbc(s, insn);
103
break;
104
- case 0x2: /* Conditional compare */
105
- disas_cc(s, insn); /* both imm and reg forms */
106
- break;
107
- case 0x4: /* Conditional select */
108
- disas_cond_select(s, insn);
109
- break;
110
- case 0x6: /* Data-processing */
111
- if (insn & (1 << 30)) { /* (1 source) */
112
- disas_data_proc_1src(s, insn);
113
- } else { /* (2 source) */
114
- disas_data_proc_2src(s, insn);
115
- }
116
- break;
117
+
118
default:
119
- unallocated_encoding(s);
120
- break;
121
+ goto do_unallocated;
122
}
123
break;
124
+
125
+ case 0x2: /* Conditional compare */
126
+ disas_cc(s, insn); /* both imm and reg forms */
127
+ break;
128
+
129
+ case 0x4: /* Conditional select */
130
+ disas_cond_select(s, insn);
131
+ break;
132
+
133
+ case 0x6: /* Data-processing */
134
+ if (op0) { /* (1 source) */
135
+ disas_data_proc_1src(s, insn);
136
+ } else { /* (2 source) */
137
+ disas_data_proc_2src(s, insn);
138
+ }
139
+ break;
140
+ case 0x8 ... 0xf: /* (3 source) */
141
+ disas_data_proc_3src(s, insn);
142
+ break;
143
+
144
default:
145
+ do_unallocated:
146
unallocated_encoding(s);
147
break;
148
}
149
--
112
--
150
2.20.1
113
2.20.1
151
114
152
115
diff view generated by jsdifflib
Deleted patch
1
From: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
2
1
3
We introduce an helper to create a memory node.
4
5
Signed-off-by: Eric Auger <eric.auger@redhat.com>
6
Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
7
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20190304101339.25970-2-eric.auger@redhat.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/arm/boot.c | 54 ++++++++++++++++++++++++++++++++-------------------
13
1 file changed, 34 insertions(+), 20 deletions(-)
14
15
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/boot.c
18
+++ b/hw/arm/boot.c
19
@@ -XXX,XX +XXX,XX @@ static void set_kernel_args_old(const struct arm_boot_info *info,
20
}
21
}
22
23
+static int fdt_add_memory_node(void *fdt, uint32_t acells, hwaddr mem_base,
24
+ uint32_t scells, hwaddr mem_len,
25
+ int numa_node_id)
26
+{
27
+ char *nodename;
28
+ int ret;
29
+
30
+ nodename = g_strdup_printf("/memory@%" PRIx64, mem_base);
31
+ qemu_fdt_add_subnode(fdt, nodename);
32
+ qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
33
+ ret = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg", acells, mem_base,
34
+ scells, mem_len);
35
+ if (ret < 0) {
36
+ goto out;
37
+ }
38
+
39
+ /* only set the NUMA ID if it is specified */
40
+ if (numa_node_id >= 0) {
41
+ ret = qemu_fdt_setprop_cell(fdt, nodename,
42
+ "numa-node-id", numa_node_id);
43
+ }
44
+out:
45
+ g_free(nodename);
46
+ return ret;
47
+}
48
+
49
static void fdt_add_psci_node(void *fdt)
50
{
51
uint32_t cpu_suspend_fn;
52
@@ -XXX,XX +XXX,XX @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
53
void *fdt = NULL;
54
int size, rc, n = 0;
55
uint32_t acells, scells;
56
- char *nodename;
57
unsigned int i;
58
hwaddr mem_base, mem_len;
59
char **node_path;
60
@@ -XXX,XX +XXX,XX @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo,
61
mem_base = binfo->loader_start;
62
for (i = 0; i < nb_numa_nodes; i++) {
63
mem_len = numa_info[i].node_mem;
64
- nodename = g_strdup_printf("/memory@%" PRIx64, mem_base);
65
- qemu_fdt_add_subnode(fdt, nodename);
66
- qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
67
- rc = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg",
68
- acells, mem_base,
69
- scells, mem_len);
70
+ rc = fdt_add_memory_node(fdt, acells, mem_base,
71
+ scells, mem_len, i);
72
if (rc < 0) {
73
- fprintf(stderr, "couldn't set %s/reg for node %d\n", nodename,
74
- i);
75
+ fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n",
76
+ mem_base);
77
goto fail;
78
}
79
80
- qemu_fdt_setprop_cell(fdt, nodename, "numa-node-id", i);
81
mem_base += mem_len;
82
- g_free(nodename);
83
}
84
} else {
85
- nodename = g_strdup_printf("/memory@%" PRIx64, binfo->loader_start);
86
- qemu_fdt_add_subnode(fdt, nodename);
87
- qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
88
-
89
- rc = qemu_fdt_setprop_sized_cells(fdt, nodename, "reg",
90
- acells, binfo->loader_start,
91
- scells, binfo->ram_size);
92
+ rc = fdt_add_memory_node(fdt, acells, binfo->loader_start,
93
+ scells, binfo->ram_size, -1);
94
if (rc < 0) {
95
- fprintf(stderr, "couldn't set %s reg\n", nodename);
96
+ fprintf(stderr, "couldn't add /memory@%"PRIx64" node\n",
97
+ binfo->loader_start);
98
goto fail;
99
}
100
- g_free(nodename);
101
}
102
103
rc = fdt_path_offset(fdt, "/chosen");
104
--
105
2.20.1
106
107
diff view generated by jsdifflib
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Roman Bolshakov <r.bolshakov@yadro.com>
2
2
3
In preparation for a split of the memory map into a static
3
ui/cocoa.m:1188:44: warning: 'openFile:' is deprecated: first deprecated in macOS 11.0 - Use -[NSWorkspace openURL:] instead.
4
part and a dynamic part floating after the RAM, let's rename the
4
[-Wdeprecated-declarations]
5
regions located after the RAM
5
if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
6
^
7
/Library/Developer/CommandLineTools/SDKs/MacOSX.sdk/System/Library/Frameworks/AppKit.framework/Headers/NSWorkspace.h:350:1: note:
8
'openFile:' has been explicitly marked deprecated here
9
- (BOOL)openFile:(NSString *)fullPath API_DEPRECATED("Use -[NSWorkspace openURL:] instead.", macos(10.0, 11.0));
10
^
6
11
7
Signed-off-by: Eric Auger <eric.auger@redhat.com>
12
Signed-off-by: Roman Bolshakov <r.bolshakov@yadro.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
14
Message-id: 20210102150718.47618-1-r.bolshakov@yadro.com
10
Message-id: 20190304101339.25970-3-eric.auger@redhat.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
16
---
13
include/hw/arm/virt.h | 8 ++++----
17
ui/cocoa.m | 5 ++++-
14
hw/arm/virt-acpi-build.c | 10 ++++++----
18
1 file changed, 4 insertions(+), 1 deletion(-)
15
hw/arm/virt.c | 33 ++++++++++++++++++---------------
16
3 files changed, 28 insertions(+), 23 deletions(-)
17
19
18
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
20
diff --git a/ui/cocoa.m b/ui/cocoa.m
19
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
20
--- a/include/hw/arm/virt.h
22
--- a/ui/cocoa.m
21
+++ b/include/hw/arm/virt.h
23
+++ b/ui/cocoa.m
22
@@ -XXX,XX +XXX,XX @@ enum {
24
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
23
VIRT_GIC_VCPU,
25
/* Where to look for local files */
24
VIRT_GIC_ITS,
26
NSString *path_array[] = {@"../share/doc/qemu/", @"../doc/qemu/", @"docs/"};
25
VIRT_GIC_REDIST,
27
NSString *full_file_path;
26
- VIRT_GIC_REDIST2,
28
+ NSURL *full_file_url;
27
+ VIRT_HIGH_GIC_REDIST2,
29
28
VIRT_SMMU,
30
/* iterate thru the possible paths until the file is found */
29
VIRT_UART,
31
int index;
30
VIRT_MMIO,
32
@@ -XXX,XX +XXX,XX @@ QemuCocoaView *cocoaView;
31
@@ -XXX,XX +XXX,XX @@ enum {
33
full_file_path = [full_file_path stringByDeletingLastPathComponent];
32
VIRT_PCIE_MMIO,
34
full_file_path = [NSString stringWithFormat: @"%@/%@%@", full_file_path,
33
VIRT_PCIE_PIO,
35
path_array[index], filename];
34
VIRT_PCIE_ECAM,
36
- if ([[NSWorkspace sharedWorkspace] openFile: full_file_path] == YES) {
35
- VIRT_PCIE_ECAM_HIGH,
37
+ full_file_url = [NSURL fileURLWithPath: full_file_path
36
+ VIRT_HIGH_PCIE_ECAM,
38
+ isDirectory: false];
37
VIRT_PLATFORM_BUS,
39
+ if ([[NSWorkspace sharedWorkspace] openURL: full_file_url] == YES) {
38
- VIRT_PCIE_MMIO_HIGH,
40
return;
39
+ VIRT_HIGH_PCIE_MMIO,
40
VIRT_GPIO,
41
VIRT_SECURE_UART,
42
VIRT_SECURE_MEM,
43
@@ -XXX,XX +XXX,XX @@ typedef struct {
44
int psci_conduit;
45
} VirtMachineState;
46
47
-#define VIRT_ECAM_ID(high) (high ? VIRT_PCIE_ECAM_HIGH : VIRT_PCIE_ECAM)
48
+#define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)
49
50
#define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
51
#define VIRT_MACHINE(obj) \
52
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/hw/arm/virt-acpi-build.c
55
+++ b/hw/arm/virt-acpi-build.c
56
@@ -XXX,XX +XXX,XX @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap,
57
size_pio));
58
59
if (use_highmem) {
60
- hwaddr base_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].base;
61
- hwaddr size_mmio_high = memmap[VIRT_PCIE_MMIO_HIGH].size;
62
+ hwaddr base_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].base;
63
+ hwaddr size_mmio_high = memmap[VIRT_HIGH_PCIE_MMIO].size;
64
65
aml_append(rbuf,
66
aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED,
67
@@ -XXX,XX +XXX,XX @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
68
gicr = acpi_data_push(table_data, sizeof(*gicr));
69
gicr->type = ACPI_APIC_GENERIC_REDISTRIBUTOR;
70
gicr->length = sizeof(*gicr);
71
- gicr->base_address = cpu_to_le64(memmap[VIRT_GIC_REDIST2].base);
72
- gicr->range_length = cpu_to_le32(memmap[VIRT_GIC_REDIST2].size);
73
+ gicr->base_address =
74
+ cpu_to_le64(memmap[VIRT_HIGH_GIC_REDIST2].base);
75
+ gicr->range_length =
76
+ cpu_to_le32(memmap[VIRT_HIGH_GIC_REDIST2].size);
77
}
41
}
78
79
if (its_class_name() && !vmc->no_its) {
80
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
81
index XXXXXXX..XXXXXXX 100644
82
--- a/hw/arm/virt.c
83
+++ b/hw/arm/virt.c
84
@@ -XXX,XX +XXX,XX @@ static const MemMapEntry a15memmap[] = {
85
[VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },
86
[VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES },
87
/* Additional 64 MB redist region (can contain up to 512 redistributors) */
88
- [VIRT_GIC_REDIST2] = { 0x4000000000ULL, 0x4000000 },
89
- [VIRT_PCIE_ECAM_HIGH] = { 0x4010000000ULL, 0x10000000 },
90
+ [VIRT_HIGH_GIC_REDIST2] = { 0x4000000000ULL, 0x4000000 },
91
+ [VIRT_HIGH_PCIE_ECAM] = { 0x4010000000ULL, 0x10000000 },
92
/* Second PCIe window, 512GB wide at the 512GB boundary */
93
- [VIRT_PCIE_MMIO_HIGH] = { 0x8000000000ULL, 0x8000000000ULL },
94
+ [VIRT_HIGH_PCIE_MMIO] = { 0x8000000000ULL, 0x8000000000ULL },
95
};
96
97
static const int a15irqmap[] = {
98
@@ -XXX,XX +XXX,XX @@ static void fdt_add_gic_node(VirtMachineState *vms)
99
2, vms->memmap[VIRT_GIC_REDIST].size);
100
} else {
101
qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
102
- 2, vms->memmap[VIRT_GIC_DIST].base,
103
- 2, vms->memmap[VIRT_GIC_DIST].size,
104
- 2, vms->memmap[VIRT_GIC_REDIST].base,
105
- 2, vms->memmap[VIRT_GIC_REDIST].size,
106
- 2, vms->memmap[VIRT_GIC_REDIST2].base,
107
- 2, vms->memmap[VIRT_GIC_REDIST2].size);
108
+ 2, vms->memmap[VIRT_GIC_DIST].base,
109
+ 2, vms->memmap[VIRT_GIC_DIST].size,
110
+ 2, vms->memmap[VIRT_GIC_REDIST].base,
111
+ 2, vms->memmap[VIRT_GIC_REDIST].size,
112
+ 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].base,
113
+ 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].size);
114
}
115
116
if (vms->virt) {
117
@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, qemu_irq *pic)
118
119
if (nb_redist_regions == 2) {
120
uint32_t redist1_capacity =
121
- vms->memmap[VIRT_GIC_REDIST2].size / GICV3_REDIST_SIZE;
122
+ vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
123
124
qdev_prop_set_uint32(gicdev, "redist-region-count[1]",
125
MIN(smp_cpus - redist0_count, redist1_capacity));
126
@@ -XXX,XX +XXX,XX @@ static void create_gic(VirtMachineState *vms, qemu_irq *pic)
127
if (type == 3) {
128
sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base);
129
if (nb_redist_regions == 2) {
130
- sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_REDIST2].base);
131
+ sysbus_mmio_map(gicbusdev, 2,
132
+ vms->memmap[VIRT_HIGH_GIC_REDIST2].base);
133
}
134
} else {
135
sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
136
@@ -XXX,XX +XXX,XX @@ static void create_pcie(VirtMachineState *vms, qemu_irq *pic)
137
{
138
hwaddr base_mmio = vms->memmap[VIRT_PCIE_MMIO].base;
139
hwaddr size_mmio = vms->memmap[VIRT_PCIE_MMIO].size;
140
- hwaddr base_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].base;
141
- hwaddr size_mmio_high = vms->memmap[VIRT_PCIE_MMIO_HIGH].size;
142
+ hwaddr base_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].base;
143
+ hwaddr size_mmio_high = vms->memmap[VIRT_HIGH_PCIE_MMIO].size;
144
hwaddr base_pio = vms->memmap[VIRT_PCIE_PIO].base;
145
hwaddr size_pio = vms->memmap[VIRT_PCIE_PIO].size;
146
hwaddr base_ecam, size_ecam;
147
@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)
148
* many redistributors we can fit into the memory map.
149
*/
150
if (vms->gic_version == 3) {
151
- virt_max_cpus = vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
152
- virt_max_cpus += vms->memmap[VIRT_GIC_REDIST2].size / GICV3_REDIST_SIZE;
153
+ virt_max_cpus =
154
+ vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
155
+ virt_max_cpus +=
156
+ vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE;
157
} else {
158
virt_max_cpus = GIC_NCPU;
159
}
42
}
160
--
43
--
161
2.20.1
44
2.20.1
162
45
163
46
diff view generated by jsdifflib