target-arm queue for softfreeze:

This has all the big stuff I want to get in for softfreeze;

there may be one or two smaller patches I pick up later in

the week.

The following changes since commit 0984a157c1c053394adbf64ed7de97f1aebe6a2d:

Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging (2019-03-05 09:33:20 +0000)

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190305

for you to fetch changes up to 566528f823d1a2e9eb2d7b2ed839547cb31bfc34:

hw/arm/stellaris: Implement watchdog timer (2019-03-05 15:55:09 +0000)

* Fix PC test for LDM (exception return)

* Implement ARMv8.0-SB

* Implement ARMv8.0-PredInv

* Implement ARMv8.4-CondM

* Implement ARMv8.5-CondM

* Implement ARMv8.5-FRINT

* hw/arm/stellaris: Implement watchdog timer

* virt: support more than 255GB of RAM

Eric Auger (9):

hw/arm/virt: Rename highmem IO regions

hw/arm/virt: Split the memory map description

hw/boards: Add a MachineState parameter to kvm_type callback

kvm: add kvm_arm_get_max_vm_ipa_size

vl: Set machine ram_size, maxram_size and ram_slots earlier

hw/arm/virt: Dynamic memory map depending on RAM requirements

hw/arm/virt: Implement kvm_type function for 4.0 machine

hw/arm/virt: Check the VCPU PA range in TCG mode

hw/arm/virt: Bump the 255GB initial RAM limit

Michel Heily (1):

hw/arm/stellaris: Implement watchdog timer

Richard Henderson (11):

target/arm: Fix PC test for LDM (exception return)

target/arm: Split out arm_sctlr

target/arm: Implement ARMv8.0-SB

target/arm: Implement ARMv8.0-PredInv

target/arm: Split helper_msr_i_pstate into 3

target/arm: Add set/clear_pstate_bits, share gen_ss_advance

target/arm: Rearrange disas_data_proc_reg

target/arm: Implement ARMv8.4-CondM

target/arm: Implement ARMv8.5-CondM

target/arm: Restructure handle_fp_1src_{single, double}

target/arm: Implement ARMv8.5-FRINT

Shameer Kolothum (1):

hw/arm/boot: introduce fdt_add_memory_node helper

include/hw/arm/virt.h | 16 +-

include/hw/boards.h | 5 +-

include/hw/watchdog/cmsdk-apb-watchdog.h | 8 +

target/arm/cpu.h | 64 ++++-

target/arm/helper-a64.h | 3 +

target/arm/helper.h | 8 +-

target/arm/internals.h | 15 +

target/arm/kvm_arm.h | 13 +

target/arm/translate.h | 34 +++

accel/kvm/kvm-all.c | 2 +-

hw/arm/boot.c | 54 ++--

hw/arm/stellaris.c | 22 +-

hw/arm/virt-acpi-build.c | 10 +-

hw/arm/virt.c | 196 ++++++++++---

hw/ppc/mac_newworld.c | 3 +-

hw/ppc/mac_oldworld.c | 2 +-

hw/ppc/spapr.c | 2 +-

hw/watchdog/cmsdk-apb-watchdog.c | 74 ++++-

linux-user/elfload.c | 2 +

target/arm/cpu.c | 2 +

target/arm/cpu64.c | 6 +

target/arm/helper-a64.c | 30 ++

target/arm/helper.c | 63 +++-

target/arm/kvm.c | 10 +

target/arm/op_helper.c | 47 ---

target/arm/translate-a64.c | 478 +++++++++++++++++++++++--------

target/arm/translate.c | 35 ++-

target/arm/vfp_helper.c | 96 +++++++

vl.c | 6 +-

29 files changed, 1032 insertions(+), 274 deletions(-)

From: Michel Heily <michelheily@gmail.com>

Implement the watchdog timer for the stellaris boards.

This device is a close variant of the CMSDK APB watchdog

device, so we can model it by subclassing that device and

tweaking the behaviour of some of its registers.

Signed-off-by: Michel Heily <michelheily@gmail.com>

Reviewed-by: Peter Maydell <petser.maydell@linaro.org>

[PMM: rewrote commit message, fixed a few checkpatch nits,

added comment giving the URL of the spec for the Stellaris

variant of the watchdog device]

include/hw/watchdog/cmsdk-apb-watchdog.h | 8 +++

hw/arm/stellaris.c | 22 ++++++-

hw/watchdog/cmsdk-apb-watchdog.c | 74 +++++++++++++++++++++++-

3 files changed, 100 insertions(+), 4 deletions(-)

diff --git a/include/hw/watchdog/cmsdk-apb-watchdog.h b/include/hw/watchdog/cmsdk-apb-watchdog.h

--- a/include/hw/watchdog/cmsdk-apb-watchdog.h

+++ b/include/hw/watchdog/cmsdk-apb-watchdog.h

@@ -XXX,XX +XXX,XX @@

#define CMSDK_APB_WATCHDOG(obj) OBJECT_CHECK(CMSDKAPBWatchdog, (obj), \

TYPE_CMSDK_APB_WATCHDOG)

+/*

+ * This shares the same struct (and cast macro) as the base

+ * cmsdk-apb-watchdog device.

+ */

+#define TYPE_LUMINARY_WATCHDOG "luminary-watchdog"

+

typedef struct CMSDKAPBWatchdog {

/*< private >*/

SysBusDevice parent_obj;

@@ -XXX,XX +XXX,XX @@ typedef struct CMSDKAPBWatchdog {

MemoryRegion iomem;

qemu_irq wdogint;

uint32_t wdogclk_frq;

+ bool is_luminary;

struct ptimer_state *timer;

uint32_t control;

@@ -XXX,XX +XXX,XX @@ typedef struct CMSDKAPBWatchdog {

uint32_t itcr;

uint32_t itop;

uint32_t resetstatus;

+ const uint32_t *id;

} CMSDKAPBWatchdog;

#endif

diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/stellaris.c

+++ b/hw/arm/stellaris.c

@@ -XXX,XX +XXX,XX @@

#include "sysemu/sysemu.h"

#include "hw/arm/armv7m.h"

#include "hw/char/pl011.h"

+#include "hw/watchdog/cmsdk-apb-watchdog.h"

#include "hw/misc/unimp.h"

#include "cpu.h"

@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)

* Stellaris LM3S6965 Microcontroller Data Sheet (rev I)

* http://www.ti.com/lit/ds/symlink/lm3s6965.pdf

*

- * 40000000 wdtimer (unimplemented)

+ * 40000000 wdtimer

* 40002000 i2c (unimplemented)

* 40004000 GPIO

* 40005000 GPIO

@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)

stellaris_sys_init(0x400fe000, qdev_get_gpio_in(nvic, 28),

board, nd_table[0].macaddr.a);

+

+ if (board->dc1 & (1 << 3)) { /* watchdog present */

+ dev = qdev_create(NULL, TYPE_LUMINARY_WATCHDOG);

+

+ /* system_clock_scale is valid now */

+ uint32_t mainclk = NANOSECONDS_PER_SECOND / system_clock_scale;

+ qdev_prop_set_uint32(dev, "wdogclk-frq", mainclk);

+

+ qdev_init_nofail(dev);

+ sysbus_mmio_map(SYS_BUS_DEVICE(dev),

+ 0,

+ 0x40000000u);

+ sysbus_connect_irq(SYS_BUS_DEVICE(dev),

+ 0,

+ qdev_get_gpio_in(nvic, 18));

+ }

+

+

for (i = 0; i < 7; i++) {

if (board->dc4 & (1 << i)) {

gpio_dev[i] = sysbus_create_simple("pl061_luminary", gpio_addr[i],

@@ -XXX,XX +XXX,XX @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board)

/* Add dummy regions for the devices we don't implement yet,

* so guest accesses don't cause unlogged crashes.

*/

- create_unimplemented_device("wdtimer", 0x40000000, 0x1000);

create_unimplemented_device("i2c-0", 0x40002000, 0x1000);

create_unimplemented_device("i2c-2", 0x40021000, 0x1000);

create_unimplemented_device("PWM", 0x40028000, 0x1000);

diff --git a/hw/watchdog/cmsdk-apb-watchdog.c b/hw/watchdog/cmsdk-apb-watchdog.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/watchdog/cmsdk-apb-watchdog.c

+++ b/hw/watchdog/cmsdk-apb-watchdog.c

@@ -XXX,XX +XXX,XX @@

* System Design Kit (CMSDK) and documented in the Cortex-M System

* Design Kit Technical Reference Manual (ARM DDI0479C):

* https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit

+ *

+ * We also support the variant of this device found in the TI

+ * Stellaris/Luminary boards and documented in:

+ * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf

*/

#include "qemu/osdep.h"

@@ -XXX,XX +XXX,XX @@ REG32(WDOGINTCLR, 0xc)

REG32(WDOGRIS, 0x10)

FIELD(WDOGRIS, INT, 0, 1)

REG32(WDOGMIS, 0x14)

+REG32(WDOGTEST, 0x418) /* only in Stellaris/Luminary version of the device */

REG32(WDOGLOCK, 0xc00)

#define WDOG_UNLOCK_VALUE 0x1ACCE551

REG32(WDOGITCR, 0xf00)

@@ -XXX,XX +XXX,XX @@ REG32(CID2, 0xff8)

REG32(CID3, 0xffc)

/* PID/CID values */

-static const int watchdog_id[] = {

+static const uint32_t cmsdk_apb_watchdog_id[] = {

0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */

0x24, 0xb8, 0x1b, 0x00, /* PID0..PID3 */

0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */

};

+static const uint32_t luminary_watchdog_id[] = {

+ 0x00, 0x00, 0x00, 0x00, /* PID4..PID7 */

+ 0x05, 0x18, 0x18, 0x01, /* PID0..PID3 */

+ 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */

+};

+

static bool cmsdk_apb_watchdog_intstatus(CMSDKAPBWatchdog *s)

{

/* Return masked interrupt status */

@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_update(CMSDKAPBWatchdog *s)

bool wdogres;

if (s->itcr) {

+ /*

+ * Not checking that !s->is_luminary since s->itcr can't be written

+ * when s->is_luminary in the first place.

+ */

wdogint = s->itop & R_WDOGITOP_WDOGINT_MASK;

wdogres = s->itop & R_WDOGITOP_WDOGRES_MASK;

} else {

@@ -XXX,XX +XXX,XX @@ static uint64_t cmsdk_apb_watchdog_read(void *opaque, hwaddr offset,

r = s->lock;

break;

case A_WDOGITCR:

+ if (s->is_luminary) {

+ goto bad_offset;

+ }

r = s->itcr;

break;

case A_PID4 ... A_CID3:

- r = watchdog_id[(offset - A_PID4) / 4];

+ r = s->id[(offset - A_PID4) / 4];

break;

case A_WDOGINTCLR:

case A_WDOGITOP:

+ if (s->is_luminary) {

+ goto bad_offset;

+ }

qemu_log_mask(LOG_GUEST_ERROR,

"CMSDK APB watchdog read: read of WO offset %x\n",

(int)offset);

r = 0;

break;

+ case A_WDOGTEST:

+ if (!s->is_luminary) {

+ goto bad_offset;

+ }

+ qemu_log_mask(LOG_UNIMP,

+ "Luminary watchdog read: stall not implemented\n");

+ r = 0;

+ break;

default:

+bad_offset:

qemu_log_mask(LOG_GUEST_ERROR,

"CMSDK APB watchdog read: bad offset %x\n", (int)offset);

r = 0;

@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_write(void *opaque, hwaddr offset,

ptimer_run(s->timer, 0);

break;

case A_WDOGCONTROL:

+ if (s->is_luminary && 0 != (R_WDOGCONTROL_INTEN_MASK & s->control)) {

+ /*

+ * The Luminary version of this device ignores writes to

+ * this register after the guest has enabled interrupts

+ * (so they can only be disabled again via reset).

+ */

+ break;

+ }

s->control = value & R_WDOGCONTROL_VALID_MASK;

cmsdk_apb_watchdog_update(s);

break;

@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_write(void *opaque, hwaddr offset,

s->lock = (value != WDOG_UNLOCK_VALUE);

break;

case A_WDOGITCR:

+ if (s->is_luminary) {

+ goto bad_offset;

+ }

s->itcr = value & R_WDOGITCR_VALID_MASK;

cmsdk_apb_watchdog_update(s);

break;

case A_WDOGITOP:

+ if (s->is_luminary) {

+ goto bad_offset;

+ }

s->itop = value & R_WDOGITOP_VALID_MASK;

cmsdk_apb_watchdog_update(s);

break;

@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_write(void *opaque, hwaddr offset,

"CMSDK APB watchdog write: write to RO offset 0x%x\n",

(int)offset);

break;

+ case A_WDOGTEST:

+ if (!s->is_luminary) {

+ goto bad_offset;

+ }

+ qemu_log_mask(LOG_UNIMP,

+ "Luminary watchdog write: stall not implemented\n");

+ break;

default:

+bad_offset:

qemu_log_mask(LOG_GUEST_ERROR,

"CMSDK APB watchdog write: bad offset 0x%x\n",

(int)offset);

@@ -XXX,XX +XXX,XX @@ static void cmsdk_apb_watchdog_init(Object *obj)

s, "cmsdk-apb-watchdog", 0x1000);

sysbus_init_mmio(sbd, &s->iomem);

sysbus_init_irq(sbd, &s->wdogint);

+

+ s->is_luminary = false;

+ s->id = cmsdk_apb_watchdog_id;

}

static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp)

@@ -XXX,XX +XXX,XX @@ static const TypeInfo cmsdk_apb_watchdog_info = {

.class_init = cmsdk_apb_watchdog_class_init,

};

+static void luminary_watchdog_init(Object *obj)

+{

+ CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(obj);

+

+ s->is_luminary = true;

+ s->id = luminary_watchdog_id;

+}

+

+static const TypeInfo luminary_watchdog_info = {

+ .name = TYPE_LUMINARY_WATCHDOG,

+ .parent = TYPE_CMSDK_APB_WATCHDOG,

+ .instance_init = luminary_watchdog_init

+};

+

static void cmsdk_apb_watchdog_register_types(void)

{

type_register_static(&cmsdk_apb_watchdog_info);

+ type_register_static(&luminary_watchdog_info);

}

type_init(cmsdk_apb_watchdog_register_types);

From: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20190301200501.16533-3-richard.henderson@linaro.org

target/arm/cpu.h | 10 ++++++++++

linux-user/elfload.c | 1 +

target/arm/cpu.c | 1 +

target/arm/cpu64.c | 2 ++

target/arm/translate-a64.c | 14 ++++++++++++++

target/arm/translate.c | 22 ++++++++++++++++++++++

6 files changed, 50 insertions(+)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h

--- a/target/arm/cpu.h

+++ b/target/arm/cpu.h

@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)

return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;

+static inline bool isar_feature_aa32_sb(const ARMISARegisters *id)

+{

+ return FIELD_EX32(id->id_isar6, ID_ISAR6, SB) != 0;

+}

+

static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)

{

/*

@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)

FIELD_DP64(0, ID_AA64ISAR1, GPI, 0xf))) != 0;

+static inline bool isar_feature_aa64_sb(const ARMISARegisters *id)

+{

+ return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, SB) != 0;

+}

+

static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)

{

/* We always set the AdvSIMD and FP fields identically wrt FP16. */

diff --git a/linux-user/elfload.c b/linux-user/elfload.c

index XXXXXXX..XXXXXXX 100644

--- a/linux-user/elfload.c

+++ b/linux-user/elfload.c

@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void)

GET_FEATURE_ID(aa64_pauth, ARM_HWCAP_A64_PACA | ARM_HWCAP_A64_PACG);

GET_FEATURE_ID(aa64_fhm, ARM_HWCAP_A64_ASIMDFHM);

GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT);

+ GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB);

#undef GET_FEATURE_ID

diff --git a/target/arm/cpu.c b/target/arm/cpu.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu.c

+++ b/target/arm/cpu.c

@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)

t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);

t = FIELD_DP32(t, ID_ISAR6, DP, 1);

t = FIELD_DP32(t, ID_ISAR6, FHM, 1);

+ t = FIELD_DP32(t, ID_ISAR6, SB, 1);

cpu->isar.id_isar6 = t;

t = cpu->id_mmfr4;

diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/cpu64.c

+++ b/target/arm/cpu64.c

@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)

t = FIELD_DP64(t, ID_AA64ISAR1, API, 0);

t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1);

t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0);

+ t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1);

cpu->isar.id_aa64isar1 = t;

t = cpu->isar.id_aa64pfr0;

@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)

u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);

u = FIELD_DP32(u, ID_ISAR6, DP, 1);

u = FIELD_DP32(u, ID_ISAR6, FHM, 1);

+ u = FIELD_DP32(u, ID_ISAR6, SB, 1);

cpu->isar.id_isar6 = u;

/*

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void handle_sync(DisasContext *s, uint32_t insn,

reset_btype(s);

gen_goto_tb(s, 0, s->pc);

return;

+

+ case 7: /* SB */

+ if (crm != 0 || !dc_isar_feature(aa64_sb, s)) {

+ goto do_unallocated;

+ }

+ /*

+ * TODO: There is no speculation barrier opcode for TCG;

+ * MB and end the TB instead.

+ */

+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);

+ gen_goto_tb(s, 0, s->pc);

+ return;

+

default:

+ do_unallocated:

unallocated_encoding(s);

return;

diff --git a/target/arm/translate.c b/target/arm/translate.c

index XXXXXXX..XXXXXXX 100644

--- a/target/arm/translate.c

+++ b/target/arm/translate.c

@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)

*/

gen_goto_tb(s, 0, s->pc & ~1);

return;

+ case 7: /* sb */

+ if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) {

+ goto illegal_op;

+ }

+ /*

+ * TODO: There is no speculation barrier opcode

+ * for TCG; MB and end the TB instead.

+ */

+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);

+ gen_goto_tb(s, 0, s->pc & ~1);

+ return;

default:

goto illegal_op;

}

@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)

*/

gen_goto_tb(s, 0, s->pc & ~1);

break;

+ case 7: /* sb */

+ if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) {

+ goto illegal_op;

+ }

+ /*

+ * TODO: There is no speculation barrier opcode

+ * for TCG; MB and end the TB instead.

+ */

+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);

+ gen_goto_tb(s, 0, s->pc & ~1);

+ break;

default:

goto illegal_op;

}

From: Eric Auger <eric.auger@redhat.com>

Now we have the extended memory map (high IO regions beyond the

scalable RAM) and dynamic IPA range support at KVM/ARM level

we can bump the legacy 255GB initial RAM limit. The actual maximum

RAM size now depends on the physical CPU and host kernel, in

accelerated mode. In TCG mode, it depends on the VCPU

AA64MMFR0.PARANGE.

Signed-off-by: Eric Auger <eric.auger@redhat.com>

Reviewed-by: Igor Mammedov <imammedo@redhat.com>

Message-id: 20190304101339.25970-11-eric.auger@redhat.com

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/arm/virt.c | 21 +--------------------

1 file changed, 1 insertion(+), 20 deletions(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c

--- a/hw/arm/virt.c

+++ b/hw/arm/virt.c

#define PLATFORM_BUS_NUM_IRQS 64

-/* RAM limit in GB. Since VIRT_MEM starts at the 1GB mark, this means

- * RAM can go up to the 256GB mark, leaving 256GB of the physical

- * address space unallocated and free for future use between 256G and 512G.

- * If we need to provide more RAM to VMs in the future then we need to:

- * * allocate a second bank of RAM starting at 2TB and working up

- * * fix the DT and ACPI table generation code in QEMU to correctly

- * report two split lumps of RAM to the guest

- * * fix KVM in the host kernel to allow guests with >40 bit address spaces

- * (We don't want to fill all the way up to 512GB with RAM because

- * we might want it for non-RAM purposes later. Conversely it seems

- * reasonable to assume that anybody configuring a VM with a quarter

- * of a terabyte of RAM will be doing it on a host with more than a

- * terabyte of physical address space.)

- */

+/* Legacy RAM limit in GB (< version 4.0) */

#define LEGACY_RAMLIMIT_GB 255

#define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)

@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)

vms->smp_cpus = smp_cpus;

- if (machine->ram_size > vms->memmap[VIRT_MEM].size) {

- error_report("mach-virt: cannot model more than %dGB RAM",

- LEGACY_RAMLIMIT_GB);

- exit(1);

- }

if (vms->virt && kvm_enabled()) {

error_report("mach-virt: KVM does not support providing "

"Virtualization extensions to the guest CPU");

From: Eric Auger <eric.auger@redhat.com>

We are about to allow the memory map to grow beyond 1TB and

potentially overshoot the VCPU AA64MMFR0.PARANGE.

In aarch64 mode and when highmem is set, let's check the VCPU

PA range is sufficient to address the highest GPA of the memory

map.

Signed-off-by: Eric Auger <eric.auger@redhat.com>

Reviewed-by: Igor Mammedov <imammedo@redhat.com>

Message-id: 20190304101339.25970-10-eric.auger@redhat.com

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

---

hw/arm/virt.c | 17 +++++++++++++++++

1 file changed, 17 insertions(+)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c

--- a/hw/arm/virt.c

+++ b/hw/arm/virt.c

@@ -XXX,XX +XXX,XX @@

#include "standard-headers/linux/input.h"

#include "hw/arm/smmuv3.h"

#include "hw/acpi/acpi.h"

+#include "target/arm/internals.h"

#define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \

static void virt_##major##_##minor##_class_init(ObjectClass *oc, \

@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)

fdt_add_timer_nodes(vms);

fdt_add_cpu_nodes(vms);

+ if (!kvm_enabled()) {

+ ARMCPU *cpu = ARM_CPU(first_cpu);

+ bool aarch64 = object_property_get_bool(OBJECT(cpu), "aarch64", NULL);

+

+ if (aarch64 && vms->highmem) {

+ int requested_pa_size, pamax = arm_pamax(cpu);

+

+ requested_pa_size = 64 - clz64(vms->highest_gpa);

+ if (pamax < requested_pa_size) {

+ error_report("VCPU supports less PA bits (%d) than requested "

+ "by the memory map (%d)", pamax, requested_pa_size);

+ exit(1);

+ }

+ }

+ }

+

memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram",

machine->ram_size);

memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram);

From: Eric Auger <eric.auger@redhat.com>

Up to now the memory map has been static and the high IO region

base has always been 256GiB.

This patch modifies the virt_set_memmap() function, which freezes

the memory map, so that the high IO range base becomes floating,

located after the initial RAM and the device memory.

The function computes

- the base of the device memory,

- the size of the device memory,

- the high IO region base

- the highest GPA used in the memory map.

Entries of the high IO region are assigned a base address. The

device memory is initialized.

The highest GPA used in the memory map will be used at VM creation

to choose the requested IPA size.

Setting all the existing highmem IO regions beyond the RAM

allows to have a single contiguous RAM region (initial RAM and

possible hotpluggable device memory). That way we do not need

to do invasive changes in the EDK2 FW to support a dynamic

RAM base.

Still the user cannot request an initial RAM size greater than 255GB.

Signed-off-by: Eric Auger <eric.auger@redhat.com>

Reviewed-by: Igor Mammedov <imammedo@redhat.com>

Message-id: 20190304101339.25970-8-eric.auger@redhat.com

include/hw/arm/virt.h | 1 +

hw/arm/virt.c | 52 ++++++++++++++++++++++++++++++++++++++-----

2 files changed, 47 insertions(+), 6 deletions(-)

diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h

--- a/include/hw/arm/virt.h

+++ b/include/hw/arm/virt.h

@@ -XXX,XX +XXX,XX @@ typedef struct {

uint32_t msi_phandle;

uint32_t iommu_phandle;

int psci_conduit;

+ hwaddr highest_gpa;

} VirtMachineState;

#define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/virt.c

+++ b/hw/arm/virt.c

@@ -XXX,XX +XXX,XX @@

#include "qapi/visitor.h"

#include "standard-headers/linux/input.h"

#include "hw/arm/smmuv3.h"

+#include "hw/acpi/acpi.h"

#define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \

static void virt_##major##_##minor##_class_init(ObjectClass *oc, \

@@ -XXX,XX +XXX,XX @@

* of a terabyte of RAM will be doing it on a host with more than a

* terabyte of physical address space.)

*/

-#define RAMLIMIT_GB 255

-#define RAMLIMIT_BYTES (RAMLIMIT_GB * 1024ULL * 1024 * 1024)

+#define LEGACY_RAMLIMIT_GB 255

+#define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB)

/* Addresses and sizes of our components.

* 0..128MB is space for a flash device so we can run bootrom code such as UEFI.

@@ -XXX,XX +XXX,XX @@ static const MemMapEntry base_memmap[] = {

[VIRT_PCIE_MMIO] = { 0x10000000, 0x2eff0000 },

[VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },

[VIRT_PCIE_ECAM] = { 0x3f000000, 0x01000000 },

- [VIRT_MEM] = { 0x40000000, RAMLIMIT_BYTES },

+ /* Actual RAM size depends on initial RAM and device memory settings */

+ [VIRT_MEM] = { GiB, LEGACY_RAMLIMIT_BYTES },

};

/*

@@ -XXX,XX +XXX,XX @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx)

static void virt_set_memmap(VirtMachineState *vms)

{

- hwaddr base;

+ MachineState *ms = MACHINE(vms);

+ hwaddr base, device_memory_base, device_memory_size;

int i;

vms->memmap = extended_memmap;

@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms)

vms->memmap[i] = base_memmap[i];

}

- base = 256 * GiB; /* Top of the legacy initial RAM region */

+ if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) {

+ error_report("unsupported number of memory slots: %"PRIu64,

+ ms->ram_slots);

+ exit(EXIT_FAILURE);

+ }

+

+ /*

+ * We compute the base of the high IO region depending on the

+ * amount of initial and device memory. The device memory start/size

+ * is aligned on 1GiB. We never put the high IO region below 256GiB

+ * so that if maxram_size is < 255GiB we keep the legacy memory map.

+ * The device region size assumes 1GiB page max alignment per slot.

+ */

+ device_memory_base =

+ ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB);

+ device_memory_size = ms->maxram_size - ms->ram_size + ms->ram_slots * GiB;

+

+ /* Base address of the high IO region */

+ base = device_memory_base + ROUND_UP(device_memory_size, GiB);

+ if (base < device_memory_base) {

+ error_report("maxmem/slots too huge");

+ exit(EXIT_FAILURE);

+ }

+ if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) {

+ base = vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES;

+ }

for (i = VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) {

hwaddr size = extended_memmap[i].size;

@@ -XXX,XX +XXX,XX @@ static void virt_set_memmap(VirtMachineState *vms)

vms->memmap[i].size = size;

base += size;

}

+ vms->highest_gpa = base - 1;

+ if (device_memory_size > 0) {

+ ms->device_memory = g_malloc0(sizeof(*ms->device_memory));

+ ms->device_memory->base = device_memory_base;

+ memory_region_init(&ms->device_memory->mr, OBJECT(vms),

+ "device-memory", device_memory_size);

+ }

}

static void machvirt_init(MachineState *machine)

@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)

vms->smp_cpus = smp_cpus;

if (machine->ram_size > vms->memmap[VIRT_MEM].size) {

- error_report("mach-virt: cannot model more than %dGB RAM", RAMLIMIT_GB);

+ error_report("mach-virt: cannot model more than %dGB RAM",

+ LEGACY_RAMLIMIT_GB);

exit(1);

}

@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)

memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram",

machine->ram_size);

memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram);

+ if (machine->device_memory) {

+ memory_region_add_subregion(sysmem, machine->device_memory->base,

+ &machine->device_memory->mr);

+ }

create_flash(vms, sysmem, secure_sysmem ? secure_sysmem : sysmem);

From: Richard Henderson <richard.henderson@linaro.org>

This will allow sharing code that adjusts rmode beyond

the existing users.

Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Message-id: 20190301200501.16533-10-richard.henderson@linaro.org

target/arm/translate-a64.c | 90 +++++++++++++++++++++-----------------

1 file changed, 49 insertions(+), 41 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c

--- a/target/arm/translate-a64.c

+++ b/target/arm/translate-a64.c

@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)

/* Floating-point data-processing (1 source) - single precision */

static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)

{

+ void (*gen_fpst)(TCGv_i32, TCGv_i32, TCGv_ptr);

+ TCGv_i32 tcg_op, tcg_res;

TCGv_ptr fpst;

- TCGv_i32 tcg_op;

- TCGv_i32 tcg_res;

+ int rmode = -1;

- fpst = get_fpstatus_ptr(false);

tcg_op = read_fp_sreg(s, rn);

tcg_res = tcg_temp_new_i32();

switch (opcode) {

case 0x0: /* FMOV */

tcg_gen_mov_i32(tcg_res, tcg_op);

- break;

+ goto done;

case 0x1: /* FABS */

gen_helper_vfp_abss(tcg_res, tcg_op);

- break;

+ goto done;

case 0x2: /* FNEG */

gen_helper_vfp_negs(tcg_res, tcg_op);

- break;

+ goto done;

case 0x3: /* FSQRT */

gen_helper_vfp_sqrts(tcg_res, tcg_op, cpu_env);

- break;

+ goto done;

case 0x8: /* FRINTN */

case 0x9: /* FRINTP */

case 0xa: /* FRINTM */

case 0xb: /* FRINTZ */

case 0xc: /* FRINTA */

- {

- TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));

-

- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);

- gen_helper_rints(tcg_res, tcg_op, fpst);

-

- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);

- tcg_temp_free_i32(tcg_rmode);

+ rmode = arm_rmode_to_sf(opcode & 7);

+ gen_fpst = gen_helper_rints;

break;

- }

case 0xe: /* FRINTX */

- gen_helper_rints_exact(tcg_res, tcg_op, fpst);

+ gen_fpst = gen_helper_rints_exact;

break;

case 0xf: /* FRINTI */

- gen_helper_rints(tcg_res, tcg_op, fpst);

+ gen_fpst = gen_helper_rints;

break;

default:

- abort();

+ g_assert_not_reached();

- write_fp_sreg(s, rd, tcg_res);

-

+ fpst = get_fpstatus_ptr(false);

+ if (rmode >= 0) {

+ TCGv_i32 tcg_rmode = tcg_const_i32(rmode);

+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);

+ gen_fpst(tcg_res, tcg_op, fpst);

+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);

+ tcg_temp_free_i32(tcg_rmode);

+ } else {

+ gen_fpst(tcg_res, tcg_op, fpst);

+ }

tcg_temp_free_ptr(fpst);

+

+ done:

+ write_fp_sreg(s, rd, tcg_res);

tcg_temp_free_i32(tcg_op);

tcg_temp_free_i32(tcg_res);

}

@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)

/* Floating-point data-processing (1 source) - double precision */

static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)

{

+ void (*gen_fpst)(TCGv_i64, TCGv_i64, TCGv_ptr);

+ TCGv_i64 tcg_op, tcg_res;

TCGv_ptr fpst;

- TCGv_i64 tcg_op;

- TCGv_i64 tcg_res;

+ int rmode = -1;

switch (opcode) {

case 0x0: /* FMOV */

@@ -XXX,XX +XXX,XX @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)

return;

}

- fpst = get_fpstatus_ptr(false);

tcg_op = read_fp_dreg(s, rn);

tcg_res = tcg_temp_new_i64();

switch (opcode) {

case 0x1: /* FABS */

gen_helper_vfp_absd(tcg_res, tcg_op);

- break;

+ goto done;

case 0x2: /* FNEG */

gen_helper_vfp_negd(tcg_res, tcg_op);

- break;

+ goto done;

case 0x3: /* FSQRT */

gen_helper_vfp_sqrtd(tcg_res, tcg_op, cpu_env);

- break;

+ goto done;

case 0x8: /* FRINTN */

case 0x9: /* FRINTP */

case 0xa: /* FRINTM */

case 0xb: /* FRINTZ */

case 0xc: /* FRINTA */

- {

- TCGv_i32 tcg_rmode = tcg_const_i32(arm_rmode_to_sf(opcode & 7));

-

- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);

- gen_helper_rintd(tcg_res, tcg_op, fpst);

-

- gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);

- tcg_temp_free_i32(tcg_rmode);

+ rmode = arm_rmode_to_sf(opcode & 7);

+ gen_fpst = gen_helper_rintd;

break;

- }

case 0xe: /* FRINTX */

- gen_helper_rintd_exact(tcg_res, tcg_op, fpst);

+ gen_fpst = gen_helper_rintd_exact;

break;

case 0xf: /* FRINTI */

- gen_helper_rintd(tcg_res, tcg_op, fpst);

+ gen_fpst = gen_helper_rintd;

break;

default:

- abort();

+ g_assert_not_reached();

}

- write_fp_dreg(s, rd, tcg_res);

-

+ fpst = get_fpstatus_ptr(false);

+ if (rmode >= 0) {

+ TCGv_i32 tcg_rmode = tcg_const_i32(rmode);

+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);

+ gen_fpst(tcg_res, tcg_op, fpst);

+ gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst);

+ tcg_temp_free_i32(tcg_rmode);

+ } else {

+ gen_fpst(tcg_res, tcg_op, fpst);

+ }

tcg_temp_free_ptr(fpst);

+

+ done:

+ write_fp_dreg(s, rd, tcg_res);

tcg_temp_free_i64(tcg_op);

tcg_temp_free_i64(tcg_res);

From: Eric Auger <eric.auger@redhat.com>

This patch implements the machine class kvm_type() callback.

It returns the number of bits requested to implement the whole GPA

range including the RAM and IO regions located beyond.

The returned value is passed though the KVM_CREATE_VM ioctl and

this allows KVM to set the stage2 tables dynamically.

To compute the highest GPA used in the memory map, kvm_type()

must freeze the memory map by calling virt_set_memmap().

hw/arm/virt.c | 39 ++++++++++++++++++++++++++++++++++++++-

1 file changed, 38 insertions(+), 1 deletion(-)

diff --git a/hw/arm/virt.c b/hw/arm/virt.c

index XXXXXXX..XXXXXXX 100644

--- a/hw/arm/virt.c

+++ b/hw/arm/virt.c

@@ -XXX,XX +XXX,XX @@ static void machvirt_init(MachineState *machine)

bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0);

bool aarch64 = true;

- virt_set_memmap(vms);

+ /*

+ * In accelerated mode, the memory map is computed earlier in kvm_type()

+ * to create a VM with the right number of IPA bits.

+ */

+ if (!vms->memmap) {

+ virt_set_memmap(vms);

+ }

/* We can probe only here because during property set

* KVM is not available yet

@@ -XXX,XX +XXX,XX @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine,

return NULL;

}

+/*

+ * for arm64 kvm_type [7-0] encodes the requested number of bits

+ * in the IPA address space

+ */

+static int virt_kvm_type(MachineState *ms, const char *type_str)

+ VirtMachineState *vms = VIRT_MACHINE(ms);

+ int max_vm_pa_size = kvm_arm_get_max_vm_ipa_size(ms);

+ int requested_pa_size;

+

+ /* we freeze the memory map to compute the highest gpa */

+ virt_set_memmap(vms);