Series comparison

-[Qemu-devel] [PULL 00/16] target-arm queue
+[PULL 0/7] target-arm queue
-The following changes since commit adf2e451f357e993f173ba9b4176dbf3e65fee7e:
+A last small test of bug fixes before rc1.
-  Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2019-02-26 19:04:47 +0000)
+thanks
 -- PMM
 The following changes since commit ed8ad9728a9c0eec34db9dff61dfa2f1dd625637:
   Merge tag 'pull-tpm-2023-07-14-1' of https://github.com/stefanberger/qemu-tpm into staging (2023-07-15 14:54:04 +0100)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190228-1
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230717
-for you to fetch changes up to 1c9af3a9e05c1607a36df4943f8f5393d7621a91:
+for you to fetch changes up to c2c1c4a35c7c2b1a4140b0942b9797c857e476a4:
-  linux-user: Enable HWCAP_ASIMDFHM, HWCAP_JSCVT (2019-02-28 11:03:05 +0000)
+  hw/nvram: Avoid unnecessary Xilinx eFuse backstore write (2023-07-17 11:05:52 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * add MHU and dual-core support to Musca boards
+ * hw/arm/sbsa-ref: set 'slots' property of xhci
- * refactor some VFP insns to be gated by ID registers
+ * linux-user: Remove pointless NULL check in clock_adjtime handling
- * Revert "arm: Allow system registers for KVM guests to be changed by QEMU code"
+ * ptw: Fix S1_ptw_translate() debug path
- * Implement ARMv8.2-FHM extension
+ * ptw: Account for FEAT_RME when applying {N}SW, SA bits
- * Advertise JSCVT via HWCAP for linux-user
+ * accel/tcg: Zero-pad PC in TCG CPU exec trace lines
  * hw/nvram: Avoid unnecessary Xilinx eFuse backstore write
 ----------------------------------------------------------------
-Peter Maydell (11):
+Peter Maydell (5):
-      hw/misc/armsse-mhu.c: Model the SSE-200 Message Handling Unit
+      linux-user: Remove pointless NULL check in clock_adjtime handling
-      hw/arm/armsse: Wire up the MHUs
+      target/arm/ptw.c: Add comments to S1Translate struct fields
-      target/arm/cpu: Allow init-svtor property to be set after realize
+      target/arm: Fix S1_ptw_translate() debug path
-      target/arm/arm-powerctl: Add new arm_set_cpu_on_and_reset()
+      target/arm/ptw.c: Account for FEAT_RME when applying {N}SW, SA bits
-      hw/misc/iotkit-sysctl: Correct typo in INITSVTOR0 register name
+      accel/tcg: Zero-pad PC in TCG CPU exec trace lines
       hw/arm/iotkit-sysctl: Add SSE-200 registers
       hw/arm/iotkit-sysctl: Implement CPUWAIT and INITSVTOR*
       hw/arm/armsse: Unify init-svtor and cpuwait handling
       target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions
       target/arm: Gate "miscellaneous FP" insns by ID register field
       Revert "arm: Allow system registers for KVM guests to be changed by QEMU code"
-Richard Henderson (5):
+Tong Ho (1):
-      target/arm: Add helpers for FMLAL
+      hw/nvram: Avoid unnecessary Xilinx eFuse backstore write
       target/arm: Implement FMLAL and FMLSL for aarch64
       target/arm: Implement VFMAL and VFMSL for aarch32
       target/arm: Enable ARMv8.2-FHM for -cpu max
       linux-user: Enable HWCAP_ASIMDFHM, HWCAP_JSCVT
- hw/misc/Makefile.objs           |   1 +
+Yuquan Wang (1):
- include/hw/arm/armsse.h         |   3 +-
+      hw/arm/sbsa-ref: set 'slots' property of xhci
  include/hw/misc/armsse-mhu.h    |  44 ++++++
  include/hw/misc/iotkit-sysctl.h |  25 +++-
  target/arm/arm-powerctl.h       |  16 +++
  target/arm/cpu.h                |  76 +++++++++--
  target/arm/helper.h             |   9 ++
  hw/arm/armsse.c                 |  91 +++++++++----
  hw/misc/armsse-mhu.c            | 198 +++++++++++++++++++++++++++
  hw/misc/iotkit-sysctl.c         | 294 ++++++++++++++++++++++++++++++++++++++--
  linux-user/elfload.c            |   2 +
  target/arm/arm-powerctl.c       |  56 ++++++++
  target/arm/cpu.c                |  32 ++++-
  target/arm/cpu64.c              |   2 +
  target/arm/helper.c             |  27 +---
  target/arm/kvm32.c              |  23 +++-
  target/arm/kvm64.c              |   2 -
  target/arm/machine.c            |   2 +-
  target/arm/translate-a64.c      |  49 ++++++-
  target/arm/translate.c          | 180 ++++++++++++++++--------
  target/arm/vec_helper.c         | 148 ++++++++++++++++++++
  MAINTAINERS                     |   2 +
  default-configs/arm-softmmu.mak |   1 +
  hw/misc/trace-events            |   4 +
 files changed, 1139 insertions(+), 148 deletions(-)
  create mode 100644 include/hw/misc/armsse-mhu.h
  create mode 100644 hw/misc/armsse-mhu.c
+ accel/tcg/cpu-exec.c      |  4 +--
+ accel/tcg/translate-all.c |  2 +-
+ hw/arm/sbsa-ref.c         |  1 +
+ hw/nvram/xlnx-efuse.c     | 11 ++++--
+ linux-user/syscall.c      | 12 +++----
+ target/arm/ptw.c          | 90 +++++++++++++++++++++++++++++++++++++++++------
+files changed, 98 insertions(+), 22 deletions(-)

-[Qemu-devel] [PULL 16/16] linux-user: Enable HWCAP_ASIMDFHM, HWCAP_JSCVT
+[PULL 1/7] hw/arm/sbsa-ref: set 'slots' property of xhci
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Yuquan Wang <wangyuquan1236@phytium.com.cn>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+This extends the slots of xhci to 64, since the default xhci_sysbus
-Message-id: 20190219222952.22183-6-richard.henderson@linaro.org
+just supports one slot.
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Wang Yuquan <wangyuquan1236@phytium.com.cn>
 Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Reviewed-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
 Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
 Message-id: 20230710063750.473510-2-wangyuquan1236@phytium.com.cn
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- linux-user/elfload.c | 2 ++
+ hw/arm/sbsa-ref.c | 1 +
-file changed, 2 insertions(+)
+file changed, 1 insertion(+)
-diff --git a/linux-user/elfload.c b/linux-user/elfload.c
+diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
 index XXXXXXX..XXXXXXX 100644
---- a/linux-user/elfload.c
+--- a/hw/arm/sbsa-ref.c
-+++ b/linux-user/elfload.c
++++ b/hw/arm/sbsa-ref.c
-@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void)
+@@ -XXX,XX +XXX,XX @@ static void create_xhci(const SBSAMachineState *sms)
-     GET_FEATURE_ID(aa64_fcma, ARM_HWCAP_A64_FCMA);
+     hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base;
-     GET_FEATURE_ID(aa64_sve, ARM_HWCAP_A64_SVE);
+     int irq = sbsa_ref_irqmap[SBSA_XHCI];
-     GET_FEATURE_ID(aa64_pauth, ARM_HWCAP_A64_PACA | ARM_HWCAP_A64_PACG);
+     DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS);
-+    GET_FEATURE_ID(aa64_fhm, ARM_HWCAP_A64_ASIMDFHM);
++    qdev_prop_set_uint32(dev, "slots", XHCI_MAXSLOTS);
-+    GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT);
+     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
- #undef GET_FEATURE_ID
+     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
 --
-.20.1
+.34.1

-[Qemu-devel] [PULL 10/16] target/arm: Gate "miscellaneous FP" insns by ID register field
+[PULL 2/7] linux-user: Remove pointless NULL check in clock_adjtime handling
-There is a set of VFP instructions which we implement in
+In the code for TARGET_NR_clock_adjtime, we set the pointer phtx to
-disas_vfp_v8_insn() and gate on the ARM_FEATURE_V8 bit.
+the address of the local variable htx.  This means it can never be
-These were all first introduced in v8 for A-profile, but in
+NULL, but later in the code we check it for NULL anyway.  Coverity
-M-profile they appeared in v7M. Gate them on the MVFR2
+complains about this (CID 1507683) because the NULL check comes after
-FPMisc field instead, and rename the function appropriately.
+a call to clock_adjtime() that assumes it is non-NULL.
 Since phtx is always &htx, and is used only in three places, it's not
 really necessary.  Remove it, bringing the code structure in to line
 with that for TARGET_NR_clock_adjtime64, which already uses a simple
 '&htx' when it wants a pointer to 'htx'.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20190222170936.13268-3-peter.maydell@linaro.org
+Message-id: 20230623144410.1837261-1-peter.maydell@linaro.org
 ---
- target/arm/cpu.h       | 20 ++++++++++++++++++++
+ linux-user/syscall.c | 12 +++++-------
- target/arm/translate.c | 25 +++++++++++++------------
+file changed, 5 insertions(+), 7 deletions(-)
 files changed, 33 insertions(+), 12 deletions(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+diff --git a/linux-user/syscall.c b/linux-user/syscall.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/linux-user/syscall.c
-+++ b/target/arm/cpu.h
++++ b/linux-user/syscall.c
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
+@@ -XXX,XX +XXX,XX @@ static abi_long do_syscall1(CPUArchState *cpu_env, int num, abi_long arg1,
-     return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1;
+ #if defined(TARGET_NR_clock_adjtime) && defined(CONFIG_CLOCK_ADJTIME)
- }
+     case TARGET_NR_clock_adjtime:
+         {
-+static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
+-            struct timex htx, *phtx = &htx;
-+{
++            struct timex htx;
-+    return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 1;
-+}
+-            if (target_to_host_timex(phtx, arg2) != 0) {
-+
++            if (target_to_host_timex(&htx, arg2) != 0) {
-+static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id)
+                 return -TARGET_EFAULT;
-+{
+             }
-+    return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 2;
+-            ret = get_errno(clock_adjtime(arg1, phtx));
-+}
+-            if (!is_error(ret) && phtx) {
-+
+-                if (host_to_target_timex(arg2, phtx) != 0) {
-+static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id)
+-                    return -TARGET_EFAULT;
-+{
+-                }
-+    return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 3;
++            ret = get_errno(clock_adjtime(arg1, &htx));
-+}
++            if (!is_error(ret) && host_to_target_timex(arg2, &htx)) {
-+
++                return -TARGET_EFAULT;
-+static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
+             }
-+{
+         }
-+    return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4;
+         return ret;
 +}
 +
  /*
   * 64-bit feature tests via id registers.
   */
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static const uint8_t fp_decode_rm[] = {
      FPROUNDING_NEGINF,
  };
 -static int disas_vfp_v8_insn(DisasContext *s, uint32_t insn)
 +static int disas_vfp_misc_insn(DisasContext *s, uint32_t insn)
  {
      uint32_t rd, rn, rm, dp = extract32(insn, 8, 1);
 -    if (!arm_dc_feature(s, ARM_FEATURE_V8)) {
 -        return 1;
 -    }
 -
      if (dp) {
          VFP_DREG_D(rd, insn);
          VFP_DREG_N(rn, insn);
@@ -XXX,XX +XXX,XX @@ static int disas_vfp_v8_insn(DisasContext *s, uint32_t insn)
          rm = VFP_SREG_M(insn);
      }
 -    if ((insn & 0x0f800e50) == 0x0e000a00) {
 +    if ((insn & 0x0f800e50) == 0x0e000a00 && dc_isar_feature(aa32_vsel, s)) {
          return handle_vsel(insn, rd, rn, rm, dp);
 -    } else if ((insn & 0x0fb00e10) == 0x0e800a00) {
 +    } else if ((insn & 0x0fb00e10) == 0x0e800a00 &&
 +               dc_isar_feature(aa32_vminmaxnm, s)) {
          return handle_vminmaxnm(insn, rd, rn, rm, dp);
 -    } else if ((insn & 0x0fbc0ed0) == 0x0eb80a40) {
 +    } else if ((insn & 0x0fbc0ed0) == 0x0eb80a40 &&
 +               dc_isar_feature(aa32_vrint, s)) {
          /* VRINTA, VRINTN, VRINTP, VRINTM */
          int rounding = fp_decode_rm[extract32(insn, 16, 2)];
          return handle_vrint(insn, rd, rm, dp, rounding);
 -    } else if ((insn & 0x0fbc0e50) == 0x0ebc0a40) {
 +    } else if ((insn & 0x0fbc0e50) == 0x0ebc0a40 &&
 +               dc_isar_feature(aa32_vcvt_dr, s)) {
          /* VCVTA, VCVTN, VCVTP, VCVTM */
          int rounding = fp_decode_rm[extract32(insn, 16, 2)];
          return handle_vcvt(insn, rd, rm, dp, rounding);
@@ -XXX,XX +XXX,XX @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
      }
      if (extract32(insn, 28, 4) == 0xf) {
 -        /* Encodings with T=1 (Thumb) or unconditional (ARM):
 -         * only used in v8 and above.
 +        /*
 +         * Encodings with T=1 (Thumb) or unconditional (ARM):
 +         * only used for the "miscellaneous VFP features" added in v8A
 +         * and v7M (and gated on the MVFR2.FPMisc field).
           */
 -        return disas_vfp_v8_insn(s, insn);
 +        return disas_vfp_misc_insn(s, insn);
      }
      dp = ((insn & 0xf00) == 0xb00);
 --
-.20.1
+.34.1

-[Qemu-devel] [PULL 03/16] target/arm/cpu: Allow init-svtor property to be set after realize
+[PULL 3/7] target/arm/ptw.c: Add comments to S1Translate struct fields
-Make the M-profile "init-svtor" property be settable after realize.
+Add comments to the in_* fields in the S1Translate struct
-This matches the hardware, where this is a config signal which
+that explain what they're doing.
 is sampled on CPU reset and can thus be changed between one
 reset and another. To do this we have to change the API we
 use to add the property.
 (We will need this capability for the SSE-200.)
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20190219125808.25174-4-peter.maydell@linaro.org
+Message-id: 20230710152130.3928330-2-peter.maydell@linaro.org
 ---
- target/arm/cpu.c | 29 ++++++++++++++++++++++++-----
+ target/arm/ptw.c | 40 ++++++++++++++++++++++++++++++++++++++++
-file changed, 24 insertions(+), 5 deletions(-)
+file changed, 40 insertions(+)
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+diff --git a/target/arm/ptw.c b/target/arm/ptw.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
+--- a/target/arm/ptw.c
-+++ b/target/arm/cpu.c
++++ b/target/arm/ptw.c
 @@ -XXX,XX +XXX,XX @@
- #include "target/arm/idau.h"
+ #endif
- #include "qemu/error-report.h"
- #include "qapi/error.h"
+ typedef struct S1Translate {
-+#include "qapi/visitor.h"
++    /*
- #include "cpu.h"
++     * in_mmu_idx : specifies which TTBR, TCR, etc to use for the walk.
- #include "internals.h"
++     * Together with in_space, specifies the architectural translation regime.
- #include "qemu-common.h"
++     */
-@@ -XXX,XX +XXX,XX @@ static Property arm_cpu_pmsav7_dregion_property =
+     ARMMMUIdx in_mmu_idx;
-                                            pmsav7_dregion,
++    /*
-                                            qdev_prop_uint32, uint32_t);
++     * in_ptw_idx: specifies which mmuidx to use for the actual
++     * page table descriptor load operations. This will be one of the
--/* M profile: initial value of the Secure VTOR */
++     * ARMMMUIdx_Stage2* or one of the ARMMMUIdx_Phys_* indexes.
--static Property arm_cpu_initsvtor_property =
++     * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit,
--            DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0);
++     * this field is updated accordingly.
-+static void arm_get_init_svtor(Object *obj, Visitor *v, const char *name,
++     */
-+                               void *opaque, Error **errp)
+     ARMMMUIdx in_ptw_idx;
-+{
++    /*
-+    ARMCPU *cpu = ARM_CPU(obj);
++     * in_space: the security space for this walk. This plus
-+
++     * the in_mmu_idx specify the architectural translation regime.
-+    visit_type_uint32(v, name, &cpu->init_svtor, errp);
++     * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit,
-+}
++     * this field is updated accordingly.
-+
++     *
-+static void arm_set_init_svtor(Object *obj, Visitor *v, const char *name,
++     * Note that the security space for the in_ptw_idx may be different
-+                               void *opaque, Error **errp)
++     * from that for the in_mmu_idx. We do not need to explicitly track
-+{
++     * the in_ptw_idx security space because:
-+    ARMCPU *cpu = ARM_CPU(obj);
++     *  - if the in_ptw_idx is an ARMMMUIdx_Phys_* then the mmuidx
-+
++     *    itself specifies the security space
-+    visit_type_uint32(v, name, &cpu->init_svtor, errp);
++     *  - if the in_ptw_idx is an ARMMMUIdx_Stage2* then the security
-+}
++     *    space used for ptw reads is the same as that of the security
++     *    space of the stage 1 translation for all cases except where
- void arm_cpu_post_init(Object *obj)
++     *    stage 1 is Secure; in that case the only possibilities for
- {
++     *    the ptw read are Secure and NonSecure, and the in_ptw_idx
-@@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj)
++     *    value being Stage2 vs Stage2_S distinguishes those.
-                                  qdev_prop_allow_set_link_before_realize,
++     */
-                                  OBJ_PROP_LINK_STRONG,
+     ARMSecuritySpace in_space;
-                                  &error_abort);
++    /*
--        qdev_property_add_static(DEVICE(obj), &arm_cpu_initsvtor_property,
++     * in_secure: whether the translation regime is a Secure one.
--                                 &error_abort);
++     * This is always equal to arm_space_is_secure(in_space).
-+        /*
++     * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit,
-+         * M profile: initial value of the Secure VTOR. We can't just use
++     * this field is updated accordingly.
-+         * a simple DEFINE_PROP_UINT32 for this because we want to permit
++     */
-+         * the property to be set after realize.
+     bool in_secure;
-+         */
++    /*
-+        object_property_add(obj, "init-svtor", "uint32",
++     * in_debug: is this a QEMU debug access (gdbstub, etc)? Debug
-+                            arm_get_init_svtor, arm_set_init_svtor,
++     * accesses will not update the guest page table access flags
-+                            NULL, NULL, &error_abort);
++     * and will not change the state of the softmmu TLBs.
-     }
++     */
+     bool in_debug;
-     qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
+     /*
       * If this is stage 2 of a stage 1+2 page table walk, then this must
 --
-.20.1
+.34.1

-[Qemu-devel] [PULL 14/16] target/arm: Implement VFMAL and VFMSL for aarch32
+[PULL 4/7] target/arm: Fix S1_ptw_translate() debug path
-From: Richard Henderson <richard.henderson@linaro.org>
+In commit fe4a5472ccd6 we rearranged the logic in S1_ptw_translate()
 so that the debug-access "call get_phys_addr_*" codepath is used both
 when S1 is doing ptw reads from stage 2 and when it is doing ptw
 reads from physical memory.  However, we didn't update the
 calculation of s2ptw->in_space and s2ptw->in_secure to account for
 the "ptw reads from physical memory" case.  This meant that debug
 accesses when in Secure state broke.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Create a new function S2_security_space() which returns the
-Message-id: 20190219222952.22183-4-richard.henderson@linaro.org
+correct security space to use for the ptw load, and use it to
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+determine the correct .in_secure and .in_space fields for the
 stage 2 lookup for the ptw load.
 Reported-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
 Message-id: 20230710152130.3928330-3-peter.maydell@linaro.org
 Fixes: fe4a5472ccd6 ("target/arm: Use get_phys_addr_with_struct in S1_ptw_translate")
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.h       |   5 ++
+ target/arm/ptw.c | 37 ++++++++++++++++++++++++++++++++-----
- target/arm/translate.c | 129 ++++++++++++++++++++++++++++++-----------
+file changed, 32 insertions(+), 5 deletions(-)
 files changed, 101 insertions(+), 33 deletions(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+diff --git a/target/arm/ptw.c b/target/arm/ptw.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/target/arm/ptw.c
-+++ b/target/arm/cpu.h
++++ b/target/arm/ptw.c
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
+@@ -XXX,XX +XXX,XX @@ static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs)
-     return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
+     }
  }
-+static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)
++static ARMSecuritySpace S2_security_space(ARMSecuritySpace s1_space,
 +                                          ARMMMUIdx s2_mmu_idx)
 +{
-+    return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
++    /*
 +     * Return the security space to use for stage 2 when doing
 +     * the S1 page table descriptor load.
 +     */
 +    if (regime_is_stage2(s2_mmu_idx)) {
 +        /*
 +         * The security space for ptw reads is almost always the same
 +         * as that of the security space of the stage 1 translation.
 +         * The only exception is when stage 1 is Secure; in that case
 +         * the ptw read might be to the Secure or the NonSecure space
 +         * (but never Realm or Root), and the s2_mmu_idx tells us which.
 +         * Root translations are always single-stage.
 +         */
 +        if (s1_space == ARMSS_Secure) {
 +            return arm_secure_to_space(s2_mmu_idx == ARMMMUIdx_Stage2_S);
 +        } else {
 +            assert(s2_mmu_idx != ARMMMUIdx_Stage2_S);
 +            assert(s1_space != ARMSS_Root);
 +            return s1_space;
 +        }
 +    } else {
 +        /* ptw loads are from phys: the mmu idx itself says which space */
 +        return arm_phys_to_space(s2_mmu_idx);
 +    }
 +}
 +
- static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
+ /* Translate a S1 pagetable walk through S2 if needed.  */
  static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
                               hwaddr addr, ARMMMUFaultInfo *fi)
  {
-     /*
+-    ARMSecuritySpace space = ptw->in_space;
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+     bool is_secure = ptw->in_secure;
-index XXXXXXX..XXXXXXX 100644
+     ARMMMUIdx mmu_idx = ptw->in_mmu_idx;
---- a/target/arm/translate.c
+     ARMMMUIdx s2_mmu_idx = ptw->in_ptw_idx;
-+++ b/target/arm/translate.c
+@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
+          * From gdbstub, do not use softmmu so that we don't modify the
-     gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL;
+          * state of the cpu at all, including softmmu tlb contents.
-     int rd, rn, rm, opr_sz;
+          */
-     int data = 0;
++        ARMSecuritySpace s2_space = S2_security_space(ptw->in_space, s2_mmu_idx);
--    bool q;
+         S1Translate s2ptw = {
--
+             .in_mmu_idx = s2_mmu_idx,
--    q = extract32(insn, 6, 1);
+             .in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx),
--    VFP_DREG_D(rd, insn);
+-            .in_secure = s2_mmu_idx == ARMMMUIdx_Stage2_S,
--    VFP_DREG_N(rn, insn);
+-            .in_space = (s2_mmu_idx == ARMMMUIdx_Stage2_S ? ARMSS_Secure
--    VFP_DREG_M(rm, insn);
+-                         : space == ARMSS_Realm ? ARMSS_Realm
--    if ((rd | rn | rm) & q) {
+-                         : ARMSS_NonSecure),
--        return 1;
++            .in_secure = arm_space_is_secure(s2_space),
--    }
++            .in_space = s2_space,
-+    int off_rn, off_rm;
+             .in_debug = true,
-+    bool is_long = false, q = extract32(insn, 6, 1);
+         };
-+    bool ptr_is_env = false;
+         GetPhysAddrResult s2 = { };
      if ((insn & 0xfe200f10) == 0xfc200800) {
          /* VCMLA -- 1111 110R R.1S .... .... 1000 ...0 .... */
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
              return 1;
          }
          fn_gvec = u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b;
 +    } else if ((insn & 0xff300f10) == 0xfc200810) {
 +        /* VFM[AS]L -- 1111 1100 S.10 .... .... 1000 .Q.1 .... */
 +        int is_s = extract32(insn, 23, 1);
 +        if (!dc_isar_feature(aa32_fhm, s)) {
 +            return 1;
 +        }
 +        is_long = true;
 +        data = is_s; /* is_2 == 0 */
 +        fn_gvec_ptr = gen_helper_gvec_fmlal_a32;
 +        ptr_is_env = true;
      } else {
          return 1;
      }
 +    VFP_DREG_D(rd, insn);
 +    if (rd & q) {
 +        return 1;
 +    }
 +    if (q || !is_long) {
 +        VFP_DREG_N(rn, insn);
 +        VFP_DREG_M(rm, insn);
 +        if ((rn | rm) & q & !is_long) {
 +            return 1;
 +        }
 +        off_rn = vfp_reg_offset(1, rn);
 +        off_rm = vfp_reg_offset(1, rm);
 +    } else {
 +        rn = VFP_SREG_N(insn);
 +        rm = VFP_SREG_M(insn);
 +        off_rn = vfp_reg_offset(0, rn);
 +        off_rm = vfp_reg_offset(0, rm);
 +    }
 +
      if (s->fp_excp_el) {
          gen_exception_insn(s, 4, EXCP_UDEF,
                             syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
      opr_sz = (1 + q) * 8;
      if (fn_gvec_ptr) {
 -        TCGv_ptr fpst = get_fpstatus_ptr(1);
 -        tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd),
 -                           vfp_reg_offset(1, rn),
 -                           vfp_reg_offset(1, rm), fpst,
 +        TCGv_ptr ptr;
 +        if (ptr_is_env) {
 +            ptr = cpu_env;
 +        } else {
 +            ptr = get_fpstatus_ptr(1);
 +        }
 +        tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr,
                             opr_sz, opr_sz, data, fn_gvec_ptr);
 -        tcg_temp_free_ptr(fpst);
 +        if (!ptr_is_env) {
 +            tcg_temp_free_ptr(ptr);
 +        }
      } else {
 -        tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd),
 -                           vfp_reg_offset(1, rn),
 -                           vfp_reg_offset(1, rm),
 +        tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm,
                             opr_sz, opr_sz, data, fn_gvec);
      }
      return 0;
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
      gen_helper_gvec_3 *fn_gvec = NULL;
      gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL;
      int rd, rn, rm, opr_sz, data;
 -    bool q;
 -
 -    q = extract32(insn, 6, 1);
 -    VFP_DREG_D(rd, insn);
 -    VFP_DREG_N(rn, insn);
 -    if ((rd | rn) & q) {
 -        return 1;
 -    }
 +    int off_rn, off_rm;
 +    bool is_long = false, q = extract32(insn, 6, 1);
 +    bool ptr_is_env = false;
      if ((insn & 0xff000f10) == 0xfe000800) {
          /* VCMLA (indexed) -- 1111 1110 S.RR .... .... 1000 ...0 .... */
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
      } else if ((insn & 0xffb00f00) == 0xfe200d00) {
          /* V[US]DOT -- 1111 1110 0.10 .... .... 1101 .Q.U .... */
          int u = extract32(insn, 4, 1);
 +
          if (!dc_isar_feature(aa32_dp, s)) {
              return 1;
          }
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
          /* rm is just Vm, and index is M.  */
          data = extract32(insn, 5, 1); /* index */
          rm = extract32(insn, 0, 4);
 +    } else if ((insn & 0xffa00f10) == 0xfe000810) {
 +        /* VFM[AS]L -- 1111 1110 0.0S .... .... 1000 .Q.1 .... */
 +        int is_s = extract32(insn, 20, 1);
 +        int vm20 = extract32(insn, 0, 3);
 +        int vm3 = extract32(insn, 3, 1);
 +        int m = extract32(insn, 5, 1);
 +        int index;
 +
 +        if (!dc_isar_feature(aa32_fhm, s)) {
 +            return 1;
 +        }
 +        if (q) {
 +            rm = vm20;
 +            index = m * 2 + vm3;
 +        } else {
 +            rm = vm20 * 2 + m;
 +            index = vm3;
 +        }
 +        is_long = true;
 +        data = (index << 2) | is_s; /* is_2 == 0 */
 +        fn_gvec_ptr = gen_helper_gvec_fmlal_idx_a32;
 +        ptr_is_env = true;
      } else {
          return 1;
      }
 +    VFP_DREG_D(rd, insn);
 +    if (rd & q) {
 +        return 1;
 +    }
 +    if (q || !is_long) {
 +        VFP_DREG_N(rn, insn);
 +        if (rn & q & !is_long) {
 +            return 1;
 +        }
 +        off_rn = vfp_reg_offset(1, rn);
 +        off_rm = vfp_reg_offset(1, rm);
 +    } else {
 +        rn = VFP_SREG_N(insn);
 +        off_rn = vfp_reg_offset(0, rn);
 +        off_rm = vfp_reg_offset(0, rm);
 +    }
      if (s->fp_excp_el) {
          gen_exception_insn(s, 4, EXCP_UDEF,
                             syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
      opr_sz = (1 + q) * 8;
      if (fn_gvec_ptr) {
 -        TCGv_ptr fpst = get_fpstatus_ptr(1);
 -        tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd),
 -                           vfp_reg_offset(1, rn),
 -                           vfp_reg_offset(1, rm), fpst,
 +        TCGv_ptr ptr;
 +        if (ptr_is_env) {
 +            ptr = cpu_env;
 +        } else {
 +            ptr = get_fpstatus_ptr(1);
 +        }
 +        tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr,
                             opr_sz, opr_sz, data, fn_gvec_ptr);
 -        tcg_temp_free_ptr(fpst);
 +        if (!ptr_is_env) {
 +            tcg_temp_free_ptr(ptr);
 +        }
      } else {
 -        tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd),
 -                           vfp_reg_offset(1, rn),
 -                           vfp_reg_offset(1, rm),
 +        tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm,
                             opr_sz, opr_sz, data, fn_gvec);
      }
      return 0;
 --
-.20.1
+.34.1

-[Qemu-devel] [PULL 01/16] hw/misc/armsse-mhu.c: Model the SSE-200 Message Handling Unit
+[PULL 5/7] target/arm/ptw.c: Account for FEAT_RME when applying {N}SW, SA bits
-Implement a model of the Message Handling Unit (MHU) found in
+In get_phys_addr_twostage() the code that applies the effects of
-the Arm SSE-200. This is a simple device which just contains
+VSTCR.{SA,SW} and VTCR.{NSA,NSW} only updates result->f.attrs.secure.
-some registers which allow the two cores of the SSE-200
+Now we also have f.attrs.space for FEAT_RME, we need to keep the two
-to raise interrupts on each other.
+in sync.
 These bits only have an effect for Secure space translations, not
 for Root, so use the input in_space field to determine whether to
 apply them rather than the input is_secure. This doesn't actually
 make a difference because Root translations are never two-stage,
 but it's a little clearer.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20190219125808.25174-2-peter.maydell@linaro.org
+Message-id: 20230710152130.3928330-4-peter.maydell@linaro.org
 ---
- hw/misc/Makefile.objs           |   1 +
+ target/arm/ptw.c | 13 ++++++++-----
- include/hw/misc/armsse-mhu.h    |  44 +++++++
+file changed, 8 insertions(+), 5 deletions(-)
  hw/misc/armsse-mhu.c            | 198 ++++++++++++++++++++++++++++++++
  MAINTAINERS                     |   2 +
  default-configs/arm-softmmu.mak |   1 +
  hw/misc/trace-events            |   4 +
 files changed, 250 insertions(+)
  create mode 100644 include/hw/misc/armsse-mhu.h
  create mode 100644 hw/misc/armsse-mhu.c
-diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
+diff --git a/target/arm/ptw.c b/target/arm/ptw.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/Makefile.objs
+--- a/target/arm/ptw.c
-+++ b/hw/misc/Makefile.objs
++++ b/target/arm/ptw.c
-@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_IOTKIT_SECCTL) += iotkit-secctl.o
+@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
- obj-$(CONFIG_IOTKIT_SYSCTL) += iotkit-sysctl.o
+     hwaddr ipa;
- obj-$(CONFIG_IOTKIT_SYSINFO) += iotkit-sysinfo.o
+     int s1_prot, s1_lgpgsz;
- obj-$(CONFIG_ARMSSE_CPUID) += armsse-cpuid.o
+     bool is_secure = ptw->in_secure;
-+obj-$(CONFIG_ARMSSE_MHU) += armsse-mhu.o
++    ARMSecuritySpace in_space = ptw->in_space;
+     bool ret, ipa_secure;
- obj-$(CONFIG_PVPANIC) += pvpanic.o
+     ARMCacheAttrs cacheattrs1;
- obj-$(CONFIG_AUX) += auxbus.o
+     ARMSecuritySpace ipa_space;
-diff --git a/include/hw/misc/armsse-mhu.h b/include/hw/misc/armsse-mhu.h
+@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
-new file mode 100644
+      * Check if IPA translates to secure or non-secure PA space.
-index XXXXXXX..XXXXXXX
+      * Note that VSTCR overrides VTCR and {N}SW overrides {N}SA.
---- /dev/null
+      */
-+++ b/include/hw/misc/armsse-mhu.h
+-    result->f.attrs.secure =
-@@ -XXX,XX +XXX,XX @@
+-        (is_secure
-+/*
+-         && !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))
-+ * ARM SSE-200 Message Handling Unit (MHU)
+-         && (ipa_secure
-+ *
+-             || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW))));
-+ * Copyright (c) 2019 Linaro Limited
++    if (in_space == ARMSS_Secure) {
-+ * Written by Peter Maydell
++        result->f.attrs.secure =
-+ *
++            !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))
-+ *  This program is free software; you can redistribute it and/or modify
++            && (ipa_secure
-+ *  it under the terms of the GNU General Public License version 2 or
++                || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW)));
-+ *  (at your option) any later version.
++        result->f.attrs.space = arm_secure_to_space(result->f.attrs.secure);
 + */
 +
 +/*
 + * This is a model of the Message Handling Unit (MHU) which is part of the
 + * Arm SSE-200 and documented in
 + * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
 + *
 + * QEMU interface:
 + *  + sysbus MMIO region 0: the system information register bank
 + *  + sysbus IRQ 0: interrupt for CPU 0
 + *  + sysbus IRQ 1: interrupt for CPU 1
 + */
 +
 +#ifndef HW_MISC_SSE_MHU_H
 +#define HW_MISC_SSE_MHU_H
 +
 +#include "hw/sysbus.h"
 +
 +#define TYPE_ARMSSE_MHU "armsse-mhu"
 +#define ARMSSE_MHU(obj) OBJECT_CHECK(ARMSSEMHU, (obj), TYPE_ARMSSE_MHU)
 +
 +typedef struct ARMSSEMHU {
 +    /*< private >*/
 +    SysBusDevice parent_obj;
 +
 +    /*< public >*/
 +    MemoryRegion iomem;
 +    qemu_irq cpu0irq;
 +    qemu_irq cpu1irq;
 +
 +    uint32_t cpu0intr;
 +    uint32_t cpu1intr;
 +} ARMSSEMHU;
 +
 +#endif
 diff --git a/hw/misc/armsse-mhu.c b/hw/misc/armsse-mhu.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/misc/armsse-mhu.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * ARM SSE-200 Message Handling Unit (MHU)
 + *
 + * Copyright (c) 2019 Linaro Limited
 + * Written by Peter Maydell
 + *
 + *  This program is free software; you can redistribute it and/or modify
 + *  it under the terms of the GNU General Public License version 2 or
 + *  (at your option) any later version.
 + */
 +
 +/*
 + * This is a model of the Message Handling Unit (MHU) which is part of the
 + * Arm SSE-200 and documented in
 + * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/log.h"
 +#include "trace.h"
 +#include "qapi/error.h"
 +#include "sysemu/sysemu.h"
 +#include "hw/sysbus.h"
 +#include "hw/registerfields.h"
 +#include "hw/misc/armsse-mhu.h"
 +
 +REG32(CPU0INTR_STAT, 0x0)
 +REG32(CPU0INTR_SET, 0x4)
 +REG32(CPU0INTR_CLR, 0x8)
 +REG32(CPU1INTR_STAT, 0x10)
 +REG32(CPU1INTR_SET, 0x14)
 +REG32(CPU1INTR_CLR, 0x18)
 +REG32(PID4, 0xfd0)
 +REG32(PID5, 0xfd4)
 +REG32(PID6, 0xfd8)
 +REG32(PID7, 0xfdc)
 +REG32(PID0, 0xfe0)
 +REG32(PID1, 0xfe4)
 +REG32(PID2, 0xfe8)
 +REG32(PID3, 0xfec)
 +REG32(CID0, 0xff0)
 +REG32(CID1, 0xff4)
 +REG32(CID2, 0xff8)
 +REG32(CID3, 0xffc)
 +
 +/* Valid bits in the interrupt registers. If any are set the IRQ is raised */
 +#define INTR_MASK 0xf
 +
 +/* PID/CID values */
 +static const int armsse_mhu_id[] = {
 +    0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
 +    0x56, 0xb8, 0x0b, 0x00, /* PID0..PID3 */
 +    0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
 +};
 +
 +static void armsse_mhu_update(ARMSSEMHU *s)
 +{
 +    qemu_set_irq(s->cpu0irq, s->cpu0intr != 0);
 +    qemu_set_irq(s->cpu1irq, s->cpu1intr != 0);
 +}
 +
 +static uint64_t armsse_mhu_read(void *opaque, hwaddr offset, unsigned size)
 +{
 +    ARMSSEMHU *s = ARMSSE_MHU(opaque);
 +    uint64_t r;
 +
 +    switch (offset) {
 +    case A_CPU0INTR_STAT:
 +        r = s->cpu0intr;
 +        break;
 +
 +    case A_CPU1INTR_STAT:
 +        r = s->cpu1intr;
 +        break;
 +
 +    case A_PID4 ... A_CID3:
 +        r = armsse_mhu_id[(offset - A_PID4) / 4];
 +        break;
 +
 +    case A_CPU0INTR_SET:
 +    case A_CPU0INTR_CLR:
 +    case A_CPU1INTR_SET:
 +    case A_CPU1INTR_CLR:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "SSE MHU: read of write-only register at offset 0x%x\n",
 +                      (int)offset);
 +        r = 0;
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "SSE MHU read: bad offset 0x%x\n", (int)offset);
 +        r = 0;
 +        break;
 +    }
-+    trace_armsse_mhu_read(offset, r, size);
-+    return r;
+     return false;
-+}
+ }
 +
 +static void armsse_mhu_write(void *opaque, hwaddr offset,
 +                             uint64_t value, unsigned size)
 +{
 +    ARMSSEMHU *s = ARMSSE_MHU(opaque);
 +
 +    trace_armsse_mhu_write(offset, value, size);
 +
 +    switch (offset) {
 +    case A_CPU0INTR_SET:
 +        s->cpu0intr |= (value & INTR_MASK);
 +        break;
 +    case A_CPU0INTR_CLR:
 +        s->cpu0intr &= ~(value & INTR_MASK);
 +        break;
 +    case A_CPU1INTR_SET:
 +        s->cpu1intr |= (value & INTR_MASK);
 +        break;
 +    case A_CPU1INTR_CLR:
 +        s->cpu1intr &= ~(value & INTR_MASK);
 +        break;
 +
 +    case A_CPU0INTR_STAT:
 +    case A_CPU1INTR_STAT:
 +    case A_PID4 ... A_CID3:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "SSE MHU: write to read-only register at offset 0x%x\n",
 +                      (int)offset);
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "SSE MHU write: bad offset 0x%x\n", (int)offset);
 +        break;
 +    }
 +
 +    armsse_mhu_update(s);
 +}
 +
 +static const MemoryRegionOps armsse_mhu_ops = {
 +    .read = armsse_mhu_read,
 +    .write = armsse_mhu_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +    .valid.min_access_size = 4,
 +    .valid.max_access_size = 4,
 +};
 +
 +static void armsse_mhu_reset(DeviceState *dev)
 +{
 +    ARMSSEMHU *s = ARMSSE_MHU(dev);
 +
 +    s->cpu0intr = 0;
 +    s->cpu1intr = 0;
 +}
 +
 +static const VMStateDescription armsse_mhu_vmstate = {
 +    .name = "armsse-mhu",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32(cpu0intr, ARMSSEMHU),
 +        VMSTATE_UINT32(cpu1intr, ARMSSEMHU),
 +        VMSTATE_END_OF_LIST()
 +    },
 +};
 +
 +static void armsse_mhu_init(Object *obj)
 +{
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 +    ARMSSEMHU *s = ARMSSE_MHU(obj);
 +
 +    memory_region_init_io(&s->iomem, obj, &armsse_mhu_ops,
 +                          s, "armsse-mhu", 0x1000);
 +    sysbus_init_mmio(sbd, &s->iomem);
 +    sysbus_init_irq(sbd, &s->cpu0irq);
 +    sysbus_init_irq(sbd, &s->cpu1irq);
 +}
 +
 +static void armsse_mhu_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
 +    dc->reset = armsse_mhu_reset;
 +    dc->vmsd = &armsse_mhu_vmstate;
 +}
 +
 +static const TypeInfo armsse_mhu_info = {
 +    .name = TYPE_ARMSSE_MHU,
 +    .parent = TYPE_SYS_BUS_DEVICE,
 +    .instance_size = sizeof(ARMSSEMHU),
 +    .instance_init = armsse_mhu_init,
 +    .class_init = armsse_mhu_class_init,
 +};
 +
 +static void armsse_mhu_register_types(void)
 +{
 +    type_register_static(&armsse_mhu_info);
 +}
 +
 +type_init(armsse_mhu_register_types);
 diff --git a/MAINTAINERS b/MAINTAINERS
 index XXXXXXX..XXXXXXX 100644
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: hw/misc/iotkit-sysinfo.c
  F: include/hw/misc/iotkit-sysinfo.h
  F: hw/misc/armsse-cpuid.c
  F: include/hw/misc/armsse-cpuid.h
 +F: hw/misc/armsse-mhu.c
 +F: include/hw/misc/armsse-mhu.h
  Musca
  M: Peter Maydell <peter.maydell@linaro.org>
 diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
 index XXXXXXX..XXXXXXX 100644
 --- a/default-configs/arm-softmmu.mak
 +++ b/default-configs/arm-softmmu.mak
@@ -XXX,XX +XXX,XX @@ CONFIG_IOTKIT_SECCTL=y
  CONFIG_IOTKIT_SYSCTL=y
  CONFIG_IOTKIT_SYSINFO=y
  CONFIG_ARMSSE_CPUID=y
 +CONFIG_ARMSSE_MHU=y
  CONFIG_VERSATILE=y
  CONFIG_VERSATILE_PCI=y
 diff --git a/hw/misc/trace-events b/hw/misc/trace-events
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/trace-events
 +++ b/hw/misc/trace-events
@@ -XXX,XX +XXX,XX @@ iotkit_sysctl_reset(void) "IoTKit SysCtl: reset"
  # hw/misc/armsse-cpuid.c
  armsse_cpuid_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
  armsse_cpuid_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
 +
 +# hw/misc/armsse-mhu.c
 +armsse_mhu_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
 +armsse_mhu_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
 --
-.20.1
+.34.1

-[Qemu-devel] [PULL 02/16] hw/arm/armsse: Wire up the MHUs
+[PULL 6/7] accel/tcg: Zero-pad PC in TCG CPU exec trace lines
-Create and connect the MHUs in the SSE-200.
+In commit f0a08b0913befbd we changed the type of the PC from
 target_ulong to vaddr.  In doing so we inadvertently dropped the
 zero-padding on the PC in trace lines (the second item inside the []
 in these lines).  They used to look like this on AArch64, for
 instance:
+Trace 0: 0x7f2260000100 [00000000/0000000040000000/00000061/ff200000]
+and now they look like this:
+Trace 0: 0x7f4f50000100 [00000000/40000000/00000061/ff200000]
+and if the PC happens to be somewhere low like 0x5000
+then the field is shown as /5000/.
+This is because TARGET_FMT_lx is a "%08x" or "%016x" specifier,
+depending on TARGET_LONG_SIZE, whereas VADDR_PRIx is just PRIx64
+with no width specifier.
+Restore the zero-padding by adding an 016 width specifier to
+this tracing and a couple of others that were similarly recently
+changed to use VADDR_PRIx without a width specifier.
+We can't unfortunately restore the "32-bit guests are padded to
+hex digits and 64-bit guests to 16 hex digits" behaviour so
+easily.
+Fixes: f0a08b0913befbd ("accel/tcg/cpu-exec.c: Widen pc to vaddr")
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
-Message-id: 20190219125808.25174-3-peter.maydell@linaro.org
+Reviewed-by: Anton Johansson <anjo@rev.ng>
 Message-id: 20230711165434.4123674-1-peter.maydell@linaro.org
 ---
- include/hw/arm/armsse.h |  3 ++-
+ accel/tcg/cpu-exec.c      | 4 ++--
- hw/arm/armsse.c         | 40 ++++++++++++++++++++++++++++++----------
+ accel/tcg/translate-all.c | 2 +-
-files changed, 32 insertions(+), 11 deletions(-)
+files changed, 3 insertions(+), 3 deletions(-)
-diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
+diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/armsse.h
+--- a/accel/tcg/cpu-exec.c
-+++ b/include/hw/arm/armsse.h
++++ b/accel/tcg/cpu-exec.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void log_cpu_exec(vaddr pc, CPUState *cpu,
- #include "hw/misc/iotkit-sysctl.h"
+     if (qemu_log_in_addr_range(pc)) {
- #include "hw/misc/iotkit-sysinfo.h"
+         qemu_log_mask(CPU_LOG_EXEC,
- #include "hw/misc/armsse-cpuid.h"
+                       "Trace %d: %p [%08" PRIx64
-+#include "hw/misc/armsse-mhu.h"
+-                      "/%" VADDR_PRIx "/%08x/%08x] %s\n",
- #include "hw/misc/unimp.h"
++                      "/%016" VADDR_PRIx "/%08x/%08x] %s\n",
- #include "hw/or-irq.h"
+                       cpu->cpu_index, tb->tc.ptr, tb->cs_base, pc,
- #include "hw/core/split-irq.h"
+                       tb->flags, tb->cflags, lookup_symbol(pc));
-@@ -XXX,XX +XXX,XX @@ typedef struct ARMSSE {
-     IoTKitSysCtl sysctl;
+@@ -XXX,XX +XXX,XX @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
-     IoTKitSysCtl sysinfo;
+         if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
+             vaddr pc = log_pc(cpu, last_tb);
--    UnimplementedDeviceState mhu[2];
+             if (qemu_log_in_addr_range(pc)) {
-+    ARMSSEMHU mhu[2];
+-                qemu_log("Stopped execution of TB chain before %p [%"
-     UnimplementedDeviceState ppu[NUM_PPUS];
++                qemu_log("Stopped execution of TB chain before %p [%016"
-     UnimplementedDeviceState cachectrl[SSE_MAX_CPUS];
+                          VADDR_PRIx "] %s\n",
-     UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS];
+                          last_tb->tc.ptr, pc, lookup_symbol(pc));
-diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
+             }
 diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/armsse.c
+--- a/accel/tcg/translate-all.c
-+++ b/hw/arm/armsse.c
++++ b/accel/tcg/translate-all.c
-@@ -XXX,XX +XXX,XX @@ static void armsse_init(Object *obj)
+@@ -XXX,XX +XXX,XX @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
-                           sizeof(s->sysinfo), TYPE_IOTKIT_SYSINFO);
+     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
-     if (info->has_mhus) {
+         vaddr pc = log_pc(cpu, tb);
-         sysbus_init_child_obj(obj, "mhu0", &s->mhu[0], sizeof(s->mhu[0]),
+         if (qemu_log_in_addr_range(pc)) {
--                              TYPE_UNIMPLEMENTED_DEVICE);
+-            qemu_log("cpu_io_recompile: rewound execution of TB to %"
-+                              TYPE_ARMSSE_MHU);
++            qemu_log("cpu_io_recompile: rewound execution of TB to %016"
-         sysbus_init_child_obj(obj, "mhu1", &s->mhu[1], sizeof(s->mhu[1]),
+                      VADDR_PRIx "\n", pc);
 -                              TYPE_UNIMPLEMENTED_DEVICE);
 +                              TYPE_ARMSSE_MHU);
      }
      if (info->has_ppus) {
          for (i = 0; i < info->num_cpus; i++) {
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
      }
      if (info->has_mhus) {
 -        for (i = 0; i < ARRAY_SIZE(s->mhu); i++) {
 -            char *name;
 -            char *port;
 +        /*
 +         * An SSE-200 with only one CPU should have only one MHU created,
 +         * with the region where the second MHU usually is being RAZ/WI.
 +         * We don't implement that SSE-200 config; if we want to support
 +         * it then this code needs to be enhanced to handle creating the
 +         * RAZ/WI region instead of the second MHU.
 +         */
 +        assert(info->num_cpus == ARRAY_SIZE(s->mhu));
 +
 +        for (i = 0; i < ARRAY_SIZE(s->mhu); i++) {
 +            char *port;
 +            int cpunum;
 +            SysBusDevice *mhu_sbd = SYS_BUS_DEVICE(&s->mhu[i]);
 -            name = g_strdup_printf("MHU%d", i);
 -            qdev_prop_set_string(DEVICE(&s->mhu[i]), "name", name);
 -            qdev_prop_set_uint64(DEVICE(&s->mhu[i]), "size", 0x1000);
              object_property_set_bool(OBJECT(&s->mhu[i]), true,
                                       "realized", &err);
 -            g_free(name);
              if (err) {
                  error_propagate(errp, err);
                  return;
              }
              port = g_strdup_printf("port[%d]", i + 3);
 -            mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mhu[i]), 0);
 +            mr = sysbus_mmio_get_region(mhu_sbd, 0);
              object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr),
                                       port, &err);
              g_free(port);
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
                  error_propagate(errp, err);
                  return;
              }
 +
 +            /*
 +             * Each MHU has an irq line for each CPU:
 +             *  MHU 0 irq line 0 -> CPU 0 IRQ 6
 +             *  MHU 0 irq line 1 -> CPU 1 IRQ 6
 +             *  MHU 1 irq line 0 -> CPU 0 IRQ 7
 +             *  MHU 1 irq line 1 -> CPU 1 IRQ 7
 +             */
 +            for (cpunum = 0; cpunum < info->num_cpus; cpunum++) {
 +                DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]);
 +
 +                sysbus_connect_irq(mhu_sbd, cpunum,
 +                                   qdev_get_gpio_in(cpudev, 6 + i));
 +            }
          }
      }
 --
-.20.1
+.34.1

-[Qemu-devel] [PULL 04/16] target/arm/arm-powerctl: Add new arm_set_cpu_on_and_reset()
+Deleted patch
-Currently the Arm arm-powerctl.h APIs allow:
- * arm_set_cpu_on(), which powers on a CPU and sets its
-   initial PC and other startup state
- * arm_reset_cpu(), which resets a CPU which is already on
-   (and fails if the CPU is powered off)
-but there is no way to say "power on a CPU as if it had
-just come out of reset and don't do anything else to it".
-Add a new function arm_set_cpu_on_and_reset(), which does this.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20190219125808.25174-5-peter.maydell@linaro.org
----
- target/arm/arm-powerctl.h | 16 +++++++++++
- target/arm/arm-powerctl.c | 56 +++++++++++++++++++++++++++++++++++++++
-files changed, 72 insertions(+)
-diff --git a/target/arm/arm-powerctl.h b/target/arm/arm-powerctl.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/arm-powerctl.h
-+++ b/target/arm/arm-powerctl.h
-@@ -XXX,XX +XXX,XX @@ int arm_set_cpu_off(uint64_t cpuid);
-  */
- int arm_reset_cpu(uint64_t cpuid);
-+/*
-+ * arm_set_cpu_on_and_reset:
-+ * @cpuid: the id of the CPU we want to star
-+ *
-+ * Start the cpu designated by @cpuid and put it through its normal
-+ * CPU reset process. The CPU will start in the way it is architected
-+ * to start after a power-on reset.
-+ *
-+ * Returns: QEMU_ARM_POWERCTL_RET_SUCCESS on success.
-+ * QEMU_ARM_POWERCTL_INVALID_PARAM if there is no CPU with that ID.
-+ * QEMU_ARM_POWERCTL_ALREADY_ON if the CPU is already on.
-+ * QEMU_ARM_POWERCTL_ON_PENDING if the CPU is already partway through
-+ * powering on.
-+ */
-+int arm_set_cpu_on_and_reset(uint64_t cpuid);
-+
- #endif
-diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/arm-powerctl.c
-+++ b/target/arm/arm-powerctl.c
-@@ -XXX,XX +XXX,XX @@ int arm_set_cpu_on(uint64_t cpuid, uint64_t entry, uint64_t context_id,
-     return QEMU_ARM_POWERCTL_RET_SUCCESS;
- }
-+static void arm_set_cpu_on_and_reset_async_work(CPUState *target_cpu_state,
-+                                                run_on_cpu_data data)
-+{
-+    ARMCPU *target_cpu = ARM_CPU(target_cpu_state);
-+
-+    /* Initialize the cpu we are turning on */
-+    cpu_reset(target_cpu_state);
-+    target_cpu_state->halted = 0;
-+
-+    /* Finally set the power status */
-+    assert(qemu_mutex_iothread_locked());
-+    target_cpu->power_state = PSCI_ON;
-+}
-+
-+int arm_set_cpu_on_and_reset(uint64_t cpuid)
-+{
-+    CPUState *target_cpu_state;
-+    ARMCPU *target_cpu;
-+
-+    assert(qemu_mutex_iothread_locked());
-+
-+    /* Retrieve the cpu we are powering up */
-+    target_cpu_state = arm_get_cpu_by_id(cpuid);
-+    if (!target_cpu_state) {
-+        /* The cpu was not found */
-+        return QEMU_ARM_POWERCTL_INVALID_PARAM;
-+    }
-+
-+    target_cpu = ARM_CPU(target_cpu_state);
-+    if (target_cpu->power_state == PSCI_ON) {
-+        qemu_log_mask(LOG_GUEST_ERROR,
-+                      "[ARM]%s: CPU %" PRId64 " is already on\n",
-+                      __func__, cpuid);
-+        return QEMU_ARM_POWERCTL_ALREADY_ON;
-+    }
-+
-+    /*
-+     * If another CPU has powered the target on we are in the state
-+     * ON_PENDING and additional attempts to power on the CPU should
-+     * fail (see 6.6 Implementation CPU_ON/CPU_OFF races in the PSCI
-+     * spec)
-+     */
-+    if (target_cpu->power_state == PSCI_ON_PENDING) {
-+        qemu_log_mask(LOG_GUEST_ERROR,
-+                      "[ARM]%s: CPU %" PRId64 " is already powering on\n",
-+                      __func__, cpuid);
-+        return QEMU_ARM_POWERCTL_ON_PENDING;
-+    }
-+
-+    async_run_on_cpu(target_cpu_state, arm_set_cpu_on_and_reset_async_work,
-+                     RUN_ON_CPU_NULL);
-+
-+    /* We are good to go */
-+    return QEMU_ARM_POWERCTL_RET_SUCCESS;
-+}
-+
- static void arm_set_cpu_off_async_work(CPUState *target_cpu_state,
-                                        run_on_cpu_data data)
- {
---
-.20.1

-[Qemu-devel] [PULL 05/16] hw/misc/iotkit-sysctl: Correct typo in INITSVTOR0 register name
+Deleted patch
-The iotkit-sysctl device has a register it names INITSVRTOR0.
-This is actually a typo present in the IoTKit documentation
-and also in part of the SSE-200 documentation:  it should be
-INITSVTOR0 because it is specifying the initial value of the
-Secure VTOR register in the CPU. Correct the typo.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20190219125808.25174-6-peter.maydell@linaro.org
----
- include/hw/misc/iotkit-sysctl.h |  2 +-
- hw/misc/iotkit-sysctl.c         | 16 ++++++++--------
-files changed, 9 insertions(+), 9 deletions(-)
-diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/misc/iotkit-sysctl.h
-+++ b/include/hw/misc/iotkit-sysctl.h
-@@ -XXX,XX +XXX,XX @@ typedef struct IoTKitSysCtl {
-     uint32_t reset_syndrome;
-     uint32_t reset_mask;
-     uint32_t gretreg;
--    uint32_t initsvrtor0;
-+    uint32_t initsvtor0;
-     uint32_t cpuwait;
-     uint32_t wicctrl;
- } IoTKitSysCtl;
-diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/iotkit-sysctl.c
-+++ b/hw/misc/iotkit-sysctl.c
-@@ -XXX,XX +XXX,XX @@ REG32(RESET_MASK, 0x104)
- REG32(SWRESET, 0x108)
-     FIELD(SWRESET, SWRESETREQ, 9, 1)
- REG32(GRETREG, 0x10c)
--REG32(INITSVRTOR0, 0x110)
-+REG32(INITSVTOR0, 0x110)
- REG32(CPUWAIT, 0x118)
- REG32(BUSWAIT, 0x11c)
- REG32(WICCTRL, 0x120)
-@@ -XXX,XX +XXX,XX @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
-     case A_GRETREG:
-         r = s->gretreg;
-         break;
--    case A_INITSVRTOR0:
--        r = s->initsvrtor0;
-+    case A_INITSVTOR0:
-+        r = s->initsvtor0;
-         break;
-     case A_CPUWAIT:
-         r = s->cpuwait;
-@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
-          */
-         s->gretreg = value;
-         break;
--    case A_INITSVRTOR0:
--        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVRTOR0 unimplemented\n");
--        s->initsvrtor0 = value;
-+    case A_INITSVTOR0:
-+        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR0 unimplemented\n");
-+        s->initsvtor0 = value;
-         break;
-     case A_CPUWAIT:
-         qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CPUWAIT unimplemented\n");
-@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_reset(DeviceState *dev)
-     s->reset_syndrome = 1;
-     s->reset_mask = 0;
-     s->gretreg = 0;
--    s->initsvrtor0 = 0x10000000;
-+    s->initsvtor0 = 0x10000000;
-     s->cpuwait = 0;
-     s->wicctrl = 0;
- }
-@@ -XXX,XX +XXX,XX @@ static const VMStateDescription iotkit_sysctl_vmstate = {
-         VMSTATE_UINT32(reset_syndrome, IoTKitSysCtl),
-         VMSTATE_UINT32(reset_mask, IoTKitSysCtl),
-         VMSTATE_UINT32(gretreg, IoTKitSysCtl),
--        VMSTATE_UINT32(initsvrtor0, IoTKitSysCtl),
-+        VMSTATE_UINT32(initsvtor0, IoTKitSysCtl),
-         VMSTATE_UINT32(cpuwait, IoTKitSysCtl),
-         VMSTATE_UINT32(wicctrl, IoTKitSysCtl),
-         VMSTATE_END_OF_LIST()
---
-.20.1

-[Qemu-devel] [PULL 06/16] hw/arm/iotkit-sysctl: Add SSE-200 registers
+Deleted patch
-The SYSCTL block in the SSE-200 has some extra registers that
-are not present in the IoTKit version. Add these registers
-(as reads-as-written stubs), enabled by a new QOM property.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20190219125808.25174-7-peter.maydell@linaro.org
----
- include/hw/misc/iotkit-sysctl.h |  20 +++
- hw/arm/armsse.c                 |   2 +
- hw/misc/iotkit-sysctl.c         | 245 +++++++++++++++++++++++++++++++-
-files changed, 262 insertions(+), 5 deletions(-)
-diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/misc/iotkit-sysctl.h
-+++ b/include/hw/misc/iotkit-sysctl.h
-@@ -XXX,XX +XXX,XX @@
-  * "system control register" blocks.
-  *
-  * QEMU interface:
-+ *  + QOM property "SYS_VERSION": value of the SYS_VERSION register of the
-+ *    system information block of the SSE
-+ *    (used to identify whether to provide SSE-200-only registers)
-  *  + sysbus MMIO region 0: the system information register bank
-  *  + sysbus MMIO region 1: the system control register bank
-  */
-@@ -XXX,XX +XXX,XX @@ typedef struct IoTKitSysCtl {
-     uint32_t initsvtor0;
-     uint32_t cpuwait;
-     uint32_t wicctrl;
-+    uint32_t scsecctrl;
-+    uint32_t fclk_div;
-+    uint32_t sysclk_div;
-+    uint32_t clock_force;
-+    uint32_t initsvtor1;
-+    uint32_t nmi_enable;
-+    uint32_t ewctrl;
-+    uint32_t pdcm_pd_sys_sense;
-+    uint32_t pdcm_pd_sram0_sense;
-+    uint32_t pdcm_pd_sram1_sense;
-+    uint32_t pdcm_pd_sram2_sense;
-+    uint32_t pdcm_pd_sram3_sense;
-+
-+    /* Properties */
-+    uint32_t sys_version;
-+
-+    bool is_sse200;
- } IoTKitSysCtl;
- #endif
-diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/armsse.c
-+++ b/hw/arm/armsse.c
-@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
-     /* System information registers */
-     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysinfo), 0, 0x40020000);
-     /* System control registers */
-+    object_property_set_int(OBJECT(&s->sysctl), info->sys_version,
-+                            "SYS_VERSION", &err);
-     object_property_set_bool(OBJECT(&s->sysctl), true, "realized", &err);
-     if (err) {
-         error_propagate(errp, err);
-diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/iotkit-sysctl.c
-+++ b/hw/misc/iotkit-sysctl.c
-@@ -XXX,XX +XXX,XX @@
-  */
- #include "qemu/osdep.h"
-+#include "qemu/bitops.h"
- #include "qemu/log.h"
- #include "trace.h"
- #include "qapi/error.h"
-@@ -XXX,XX +XXX,XX @@
- REG32(SECDBGSTAT, 0x0)
- REG32(SECDBGSET, 0x4)
- REG32(SECDBGCLR, 0x8)
-+REG32(SCSECCTRL, 0xc)
-+REG32(FCLK_DIV, 0x10)
-+REG32(SYSCLK_DIV, 0x14)
-+REG32(CLOCK_FORCE, 0x18)
- REG32(RESET_SYNDROME, 0x100)
- REG32(RESET_MASK, 0x104)
- REG32(SWRESET, 0x108)
-     FIELD(SWRESET, SWRESETREQ, 9, 1)
- REG32(GRETREG, 0x10c)
- REG32(INITSVTOR0, 0x110)
-+REG32(INITSVTOR1, 0x114)
- REG32(CPUWAIT, 0x118)
--REG32(BUSWAIT, 0x11c)
-+REG32(NMI_ENABLE, 0x11c) /* BUSWAIT in IoTKit */
- REG32(WICCTRL, 0x120)
-+REG32(EWCTRL, 0x124)
-+REG32(PDCM_PD_SYS_SENSE, 0x200)
-+REG32(PDCM_PD_SRAM0_SENSE, 0x20c)
-+REG32(PDCM_PD_SRAM1_SENSE, 0x210)
-+REG32(PDCM_PD_SRAM2_SENSE, 0x214)
-+REG32(PDCM_PD_SRAM3_SENSE, 0x218)
- REG32(PID4, 0xfd0)
- REG32(PID5, 0xfd4)
- REG32(PID6, 0xfd8)
-@@ -XXX,XX +XXX,XX @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
-     case A_SECDBGSTAT:
-         r = s->secure_debug;
-         break;
-+    case A_SCSECCTRL:
-+        if (!s->is_sse200) {
-+            goto bad_offset;
-+        }
-+        r = s->scsecctrl;
-+        break;
-+    case A_FCLK_DIV:
-+        if (!s->is_sse200) {
-+            goto bad_offset;
-+        }
-+        r = s->fclk_div;
-+        break;
-+    case A_SYSCLK_DIV:
-+        if (!s->is_sse200) {
-+            goto bad_offset;
-+        }
-+        r = s->sysclk_div;
-+        break;
-+    case A_CLOCK_FORCE:
-+        if (!s->is_sse200) {
-+            goto bad_offset;
-+        }
-+        r = s->clock_force;
-+        break;
-     case A_RESET_SYNDROME:
-         r = s->reset_syndrome;
-         break;
-@@ -XXX,XX +XXX,XX @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
-     case A_INITSVTOR0:
-         r = s->initsvtor0;
-         break;
-+    case A_INITSVTOR1:
-+        if (!s->is_sse200) {
-+            goto bad_offset;
-+        }
-+        r = s->initsvtor1;
-+        break;
-     case A_CPUWAIT:
-         r = s->cpuwait;
-         break;
--    case A_BUSWAIT:
--        /* In IoTKit BUSWAIT is reserved, R/O, zero */
--        r = 0;
-+    case A_NMI_ENABLE:
-+        /* In IoTKit this is named BUSWAIT but is marked reserved, R/O, zero */
-+        if (!s->is_sse200) {
-+            r = 0;
-+            break;
-+        }
-+        r = s->nmi_enable;
-         break;
-     case A_WICCTRL:
-         r = s->wicctrl;
-         break;
-+    case A_EWCTRL:
-+        if (!s->is_sse200) {
-+            goto bad_offset;
-+        }
-+        r = s->ewctrl;
-+        break;
-+    case A_PDCM_PD_SYS_SENSE:
-+        if (!s->is_sse200) {
-+            goto bad_offset;
-+        }
-+        r = s->pdcm_pd_sys_sense;
-+        break;
-+    case A_PDCM_PD_SRAM0_SENSE:
-+        if (!s->is_sse200) {
-+            goto bad_offset;
-+        }
-+        r = s->pdcm_pd_sram0_sense;
-+        break;
-+    case A_PDCM_PD_SRAM1_SENSE:
-+        if (!s->is_sse200) {
-+            goto bad_offset;
-+        }
-+        r = s->pdcm_pd_sram1_sense;
-+        break;
-+    case A_PDCM_PD_SRAM2_SENSE:
-+        if (!s->is_sse200) {
-+            goto bad_offset;
-+        }
-+        r = s->pdcm_pd_sram2_sense;
-+        break;
-+    case A_PDCM_PD_SRAM3_SENSE:
-+        if (!s->is_sse200) {
-+            goto bad_offset;
-+        }
-+        r = s->pdcm_pd_sram3_sense;
-+        break;
-     case A_PID4 ... A_CID3:
-         r = sysctl_id[(offset - A_PID4) / 4];
-         break;
-@@ -XXX,XX +XXX,XX @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
-         r = 0;
-         break;
-     default:
-+    bad_offset:
-         qemu_log_mask(LOG_GUEST_ERROR,
-                       "IoTKit SysCtl read: bad offset %x\n", (int)offset);
-         r = 0;
-@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
-             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
-         }
-         break;
--    case A_BUSWAIT:        /* In IoTKit BUSWAIT is reserved, R/O, zero */
-+    case A_SCSECCTRL:
-+        if (!s->is_sse200) {
-+            goto bad_offset;
-+        }
-+        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SCSECCTRL unimplemented\n");
-+        s->scsecctrl = value;
-+        break;
-+    case A_FCLK_DIV:
-+        if (!s->is_sse200) {
-+            goto bad_offset;
-+        }
-+        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl FCLK_DIV unimplemented\n");
-+        s->fclk_div = value;
-+        break;
-+    case A_SYSCLK_DIV:
-+        if (!s->is_sse200) {
-+            goto bad_offset;
-+        }
-+        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SYSCLK_DIV unimplemented\n");
-+        s->sysclk_div = value;
-+        break;
-+    case A_CLOCK_FORCE:
-+        if (!s->is_sse200) {
-+            goto bad_offset;
-+        }
-+        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CLOCK_FORCE unimplemented\n");
-+        s->clock_force = value;
-+        break;
-+    case A_INITSVTOR1:
-+        if (!s->is_sse200) {
-+            goto bad_offset;
-+        }
-+        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR1 unimplemented\n");
-+        s->initsvtor1 = value;
-+        break;
-+    case A_EWCTRL:
-+        if (!s->is_sse200) {
-+            goto bad_offset;
-+        }
-+        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl EWCTRL unimplemented\n");
-+        s->ewctrl = value;
-+        break;
-+    case A_PDCM_PD_SYS_SENSE:
-+        if (!s->is_sse200) {
-+            goto bad_offset;
-+        }
-+        qemu_log_mask(LOG_UNIMP,
-+                      "IoTKit SysCtl PDCM_PD_SYS_SENSE unimplemented\n");
-+        s->pdcm_pd_sys_sense = value;
-+        break;
-+    case A_PDCM_PD_SRAM0_SENSE:
-+        if (!s->is_sse200) {
-+            goto bad_offset;
-+        }
-+        qemu_log_mask(LOG_UNIMP,
-+                      "IoTKit SysCtl PDCM_PD_SRAM0_SENSE unimplemented\n");
-+        s->pdcm_pd_sram0_sense = value;
-+        break;
-+    case A_PDCM_PD_SRAM1_SENSE:
-+        if (!s->is_sse200) {
-+            goto bad_offset;
-+        }
-+        qemu_log_mask(LOG_UNIMP,
-+                      "IoTKit SysCtl PDCM_PD_SRAM1_SENSE unimplemented\n");
-+        s->pdcm_pd_sram1_sense = value;
-+        break;
-+    case A_PDCM_PD_SRAM2_SENSE:
-+        if (!s->is_sse200) {
-+            goto bad_offset;
-+        }
-+        qemu_log_mask(LOG_UNIMP,
-+                      "IoTKit SysCtl PDCM_PD_SRAM2_SENSE unimplemented\n");
-+        s->pdcm_pd_sram2_sense = value;
-+        break;
-+    case A_PDCM_PD_SRAM3_SENSE:
-+        if (!s->is_sse200) {
-+            goto bad_offset;
-+        }
-+        qemu_log_mask(LOG_UNIMP,
-+                      "IoTKit SysCtl PDCM_PD_SRAM3_SENSE unimplemented\n");
-+        s->pdcm_pd_sram3_sense = value;
-+        break;
-+    case A_NMI_ENABLE:
-+        /* In IoTKit this is BUSWAIT: reserved, R/O, zero */
-+        if (!s->is_sse200) {
-+            goto ro_offset;
-+        }
-+        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE unimplemented\n");
-+        s->nmi_enable = value;
-+        break;
-     case A_SECDBGSTAT:
-     case A_PID4 ... A_CID3:
-+    ro_offset:
-         qemu_log_mask(LOG_GUEST_ERROR,
-                       "IoTKit SysCtl write: write of RO offset %x\n",
-                       (int)offset);
-         break;
-     default:
-+    bad_offset:
-         qemu_log_mask(LOG_GUEST_ERROR,
-                       "IoTKit SysCtl write: bad offset %x\n", (int)offset);
-         break;
-@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_reset(DeviceState *dev)
-     s->reset_mask = 0;
-     s->gretreg = 0;
-     s->initsvtor0 = 0x10000000;
-+    s->initsvtor1 = 0x10000000;
-     s->cpuwait = 0;
-     s->wicctrl = 0;
-+    s->scsecctrl = 0;
-+    s->fclk_div = 0;
-+    s->sysclk_div = 0;
-+    s->clock_force = 0;
-+    s->nmi_enable = 0;
-+    s->ewctrl = 0;
-+    s->pdcm_pd_sys_sense = 0x7f;
-+    s->pdcm_pd_sram0_sense = 0;
-+    s->pdcm_pd_sram1_sense = 0;
-+    s->pdcm_pd_sram2_sense = 0;
-+    s->pdcm_pd_sram3_sense = 0;
- }
- static void iotkit_sysctl_init(Object *obj)
-@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_init(Object *obj)
-     sysbus_init_mmio(sbd, &s->iomem);
- }
-+static void iotkit_sysctl_realize(DeviceState *dev, Error **errp)
-+{
-+    IoTKitSysCtl *s = IOTKIT_SYSCTL(dev);
-+
-+    /* The top 4 bits of the SYS_VERSION register tell us if we're an SSE-200 */
-+    if (extract32(s->sys_version, 28, 4) == 2) {
-+        s->is_sse200 = true;
-+    }
-+}
-+
-+static bool sse200_needed(void *opaque)
-+{
-+    IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque);
-+
-+    return s->is_sse200;
-+}
-+
-+static const VMStateDescription iotkit_sysctl_sse200_vmstate = {
-+    .name = "iotkit-sysctl/sse-200",
-+    .version_id = 1,
-+    .minimum_version_id = 1,
-+    .needed = sse200_needed,
-+    .fields = (VMStateField[]) {
-+        VMSTATE_UINT32(scsecctrl, IoTKitSysCtl),
-+        VMSTATE_UINT32(fclk_div, IoTKitSysCtl),
-+        VMSTATE_UINT32(sysclk_div, IoTKitSysCtl),
-+        VMSTATE_UINT32(clock_force, IoTKitSysCtl),
-+        VMSTATE_UINT32(initsvtor1, IoTKitSysCtl),
-+        VMSTATE_UINT32(nmi_enable, IoTKitSysCtl),
-+        VMSTATE_UINT32(pdcm_pd_sys_sense, IoTKitSysCtl),
-+        VMSTATE_UINT32(pdcm_pd_sram0_sense, IoTKitSysCtl),
-+        VMSTATE_UINT32(pdcm_pd_sram1_sense, IoTKitSysCtl),
-+        VMSTATE_UINT32(pdcm_pd_sram2_sense, IoTKitSysCtl),
-+        VMSTATE_UINT32(pdcm_pd_sram3_sense, IoTKitSysCtl),
-+        VMSTATE_END_OF_LIST()
-+    }
-+};
-+
- static const VMStateDescription iotkit_sysctl_vmstate = {
-     .name = "iotkit-sysctl",
-     .version_id = 1,
-@@ -XXX,XX +XXX,XX @@ static const VMStateDescription iotkit_sysctl_vmstate = {
-         VMSTATE_UINT32(cpuwait, IoTKitSysCtl),
-         VMSTATE_UINT32(wicctrl, IoTKitSysCtl),
-         VMSTATE_END_OF_LIST()
-+    },
-+    .subsections = (const VMStateDescription*[]) {
-+        &iotkit_sysctl_sse200_vmstate,
-+        NULL
-     }
- };
-+static Property iotkit_sysctl_props[] = {
-+    DEFINE_PROP_UINT32("SYS_VERSION", IoTKitSysCtl, sys_version, 0),
-+    DEFINE_PROP_END_OF_LIST()
-+};
-+
- static void iotkit_sysctl_class_init(ObjectClass *klass, void *data)
- {
-     DeviceClass *dc = DEVICE_CLASS(klass);
-     dc->vmsd = &iotkit_sysctl_vmstate;
-     dc->reset = iotkit_sysctl_reset;
-+    dc->props = iotkit_sysctl_props;
-+    dc->realize = iotkit_sysctl_realize;
- }
- static const TypeInfo iotkit_sysctl_info = {
---
-.20.1

-[Qemu-devel] [PULL 07/16] hw/arm/iotkit-sysctl: Implement CPUWAIT and INITSVTOR*
+Deleted patch
-The CPUWAIT register acts as a sort of power-control: if a bit
-in it is 1 then the CPU will have been forced into waiting
-when the system was reset (which in QEMU we model as the
-CPU starting powered off). Writing a 0 to the register will
-allow the CPU to boot (for QEMU, we model this as powering
-it on). Note that writing 0 to the register does not power
-off a CPU.
-For this to work correctly we need to also honour the
-INITSVTOR* registers, which let the guest control where the
-CPU will load its SP and PC from when it comes out of reset.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20190219125808.25174-8-peter.maydell@linaro.org
----
- hw/misc/iotkit-sysctl.c | 41 +++++++++++++++++++++++++++++++++++++----
-file changed, 37 insertions(+), 4 deletions(-)
-diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/iotkit-sysctl.c
-+++ b/hw/misc/iotkit-sysctl.c
-@@ -XXX,XX +XXX,XX @@
- #include "hw/sysbus.h"
- #include "hw/registerfields.h"
- #include "hw/misc/iotkit-sysctl.h"
-+#include "target/arm/arm-powerctl.h"
-+#include "target/arm/cpu.h"
- REG32(SECDBGSTAT, 0x0)
- REG32(SECDBGSET, 0x4)
-@@ -XXX,XX +XXX,XX @@ static const int sysctl_id[] = {
-x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
- };
-+/*
-+ * Set the initial secure vector table offset address for the core.
-+ * This will take effect when the CPU next resets.
-+ */
-+static void set_init_vtor(uint64_t cpuid, uint32_t vtor)
-+{
-+    Object *cpuobj = OBJECT(arm_get_cpu_by_id(cpuid));
-+
-+    if (cpuobj) {
-+        if (object_property_find(cpuobj, "init-svtor", NULL)) {
-+            object_property_set_uint(cpuobj, vtor, "init-svtor", &error_abort);
-+        }
-+    }
-+}
-+
- static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
-                                     unsigned size)
- {
-@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
-         s->gretreg = value;
-         break;
-     case A_INITSVTOR0:
--        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR0 unimplemented\n");
-         s->initsvtor0 = value;
-+        set_init_vtor(0, s->initsvtor0);
-         break;
-     case A_CPUWAIT:
--        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CPUWAIT unimplemented\n");
-+        if ((s->cpuwait & 1) && !(value & 1)) {
-+            /* Powering up CPU 0 */
-+            arm_set_cpu_on_and_reset(0);
-+        }
-+        if ((s->cpuwait & 2) && !(value & 2)) {
-+            /* Powering up CPU 1 */
-+            arm_set_cpu_on_and_reset(1);
-+        }
-         s->cpuwait = value;
-         break;
-     case A_WICCTRL:
-@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
-         if (!s->is_sse200) {
-             goto bad_offset;
-         }
--        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR1 unimplemented\n");
-         s->initsvtor1 = value;
-+        set_init_vtor(1, s->initsvtor1);
-         break;
-     case A_EWCTRL:
-         if (!s->is_sse200) {
-@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_reset(DeviceState *dev)
-     s->gretreg = 0;
-     s->initsvtor0 = 0x10000000;
-     s->initsvtor1 = 0x10000000;
--    s->cpuwait = 0;
-+    if (s->is_sse200) {
-+        /*
-+         * CPU 0 starts on, CPU 1 starts off. In real hardware this is
-+         * configurable by the SoC integrator as a verilog parameter.
-+         */
-+        s->cpuwait = 2;
-+    } else {
-+        /* CPU 0 starts on */
-+        s->cpuwait = 0;
-+    }
-     s->wicctrl = 0;
-     s->scsecctrl = 0;
-     s->fclk_div = 0;
---
-.20.1

-[Qemu-devel] [PULL 08/16] hw/arm/armsse: Unify init-svtor and cpuwait handling
+Deleted patch
-At the moment the handling of init-svtor and cpuwait initial
-values is split between armsse.c and iotkit-sysctl.c:
-the code in armsse.c sets the initial state of the CPU
-object by setting the init-svtor and start-powered-off
-properties, but the iotkit-sysctl.c code has its own
-code setting the reset values of its registers (which are
-then used when updating the CPU when the guest makes
-runtime changes).
-Clean this up by making the armsse.c code set properties on the
-iotkit-sysctl object to define the initial values of the
-registers, so they always match the initial CPU state,
-and update the comments in armsse.c accordingly.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20190219125808.25174-9-peter.maydell@linaro.org
----
- include/hw/misc/iotkit-sysctl.h |  3 ++
- hw/arm/armsse.c                 | 49 +++++++++++++++++++++------------
- hw/misc/iotkit-sysctl.c         | 20 ++++++--------
-files changed, 42 insertions(+), 30 deletions(-)
-diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/misc/iotkit-sysctl.h
-+++ b/include/hw/misc/iotkit-sysctl.h
-@@ -XXX,XX +XXX,XX @@ typedef struct IoTKitSysCtl {
-     /* Properties */
-     uint32_t sys_version;
-+    uint32_t cpuwait_rst;
-+    uint32_t initsvtor0_rst;
-+    uint32_t initsvtor1_rst;
-     bool is_sse200;
- } IoTKitSysCtl;
-diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/arm/armsse.c
-+++ b/hw/arm/armsse.c
-@@ -XXX,XX +XXX,XX @@
- #include "qemu/osdep.h"
- #include "qemu/log.h"
-+#include "qemu/bitops.h"
- #include "qapi/error.h"
- #include "trace.h"
- #include "hw/sysbus.h"
-@@ -XXX,XX +XXX,XX @@ struct ARMSSEInfo {
-     int sram_banks;
-     int num_cpus;
-     uint32_t sys_version;
-+    uint32_t cpuwait_rst;
-     SysConfigFormat sys_config_format;
-     bool has_mhus;
-     bool has_ppus;
-@@ -XXX,XX +XXX,XX @@ static const ARMSSEInfo armsse_variants[] = {
-         .sram_banks = 1,
-         .num_cpus = 1,
-         .sys_version = 0x41743,
-+        .cpuwait_rst = 0,
-         .sys_config_format = IoTKitFormat,
-         .has_mhus = false,
-         .has_ppus = false,
-@@ -XXX,XX +XXX,XX @@ static const ARMSSEInfo armsse_variants[] = {
-         .sram_banks = 4,
-         .num_cpus = 2,
-         .sys_version = 0x22041743,
-+        .cpuwait_rst = 2,
-         .sys_config_format = SSE200Format,
-         .has_mhus = true,
-         .has_ppus = true,
-@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
-         qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + 32);
-         /*
--         * In real hardware the initial Secure VTOR is set from the INITSVTOR0
--         * register in the IoT Kit System Control Register block, and the
--         * initial value of that is in turn specifiable by the FPGA that
--         * instantiates the IoT Kit. In QEMU we don't implement this wrinkle,
--         * and simply set the CPU's init-svtor to the IoT Kit default value.
--         * In SSE-200 the situation is similar, except that the default value
--         * is a reset-time signal input. Typically a board using the SSE-200
--         * will have a system control processor whose boot firmware initializes
--         * the INITSVTOR* registers before powering up the CPUs in any case,
--         * so the hardware's default value doesn't matter. QEMU doesn't emulate
-+         * In real hardware the initial Secure VTOR is set from the INITSVTOR*
-+         * registers in the IoT Kit System Control Register block. In QEMU
-+         * we set the initial value here, and also the reset value of the
-+         * sysctl register, from this object's QOM init-svtor property.
-+         * If the guest changes the INITSVTOR* registers at runtime then the
-+         * code in iotkit-sysctl.c will update the CPU init-svtor property
-+         * (which will then take effect on the next CPU warm-reset).
-+         *
-+         * Note that typically a board using the SSE-200 will have a system
-+         * control processor whose boot firmware initializes the INITSVTOR*
-+         * registers before powering up the CPUs. QEMU doesn't emulate
-          * the control processor, so instead we behave in the way that the
--         * firmware does. The initial value is configurable by the board code
--         * to match whatever its firmware does.
-+         * firmware does: the initial value should be set by the board code
-+         * (using the init-svtor property on the ARMSSE object) to match
-+         * whatever its firmware does.
-          */
-         qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor);
-         /*
--         * Start all CPUs except CPU0 powered down. In real hardware it is
--         * a configurable property of the SSE-200 which CPUs start powered up
--         * (via the CPUWAIT0_RST and CPUWAIT1_RST parameters), but since all
--         * the boards we care about start CPU0 and leave CPU1 powered off,
--         * we hard-code that for now. We can add QOM properties for this
-+         * CPUs start powered down if the corresponding bit in the CPUWAIT
-+         * register is 1. In real hardware the CPUWAIT register reset value is
-+         * a configurable property of the SSE-200 (via the CPUWAIT0_RST and
-+         * CPUWAIT1_RST parameters), but since all the boards we care about
-+         * start CPU0 and leave CPU1 powered off, we hard-code that in
-+         * info->cpuwait_rst for now. We can add QOM properties for this
-          * later if necessary.
-          */
--        if (i > 0) {
-+        if (extract32(info->cpuwait_rst, i, 1)) {
-             object_property_set_bool(cpuobj, true, "start-powered-off", &err);
-             if (err) {
-                 error_propagate(errp, err);
-@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
-     /* System control registers */
-     object_property_set_int(OBJECT(&s->sysctl), info->sys_version,
-                             "SYS_VERSION", &err);
-+    object_property_set_int(OBJECT(&s->sysctl), info->cpuwait_rst,
-+                            "CPUWAIT_RST", &err);
-+    object_property_set_int(OBJECT(&s->sysctl), s->init_svtor,
-+                            "INITSVTOR0_RST", &err);
-+    object_property_set_int(OBJECT(&s->sysctl), s->init_svtor,
-+                            "INITSVTOR1_RST", &err);
-     object_property_set_bool(OBJECT(&s->sysctl), true, "realized", &err);
-     if (err) {
-         error_propagate(errp, err);
-diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/iotkit-sysctl.c
-+++ b/hw/misc/iotkit-sysctl.c
-@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_reset(DeviceState *dev)
-     s->reset_syndrome = 1;
-     s->reset_mask = 0;
-     s->gretreg = 0;
--    s->initsvtor0 = 0x10000000;
--    s->initsvtor1 = 0x10000000;
--    if (s->is_sse200) {
--        /*
--         * CPU 0 starts on, CPU 1 starts off. In real hardware this is
--         * configurable by the SoC integrator as a verilog parameter.
--         */
--        s->cpuwait = 2;
--    } else {
--        /* CPU 0 starts on */
--        s->cpuwait = 0;
--    }
-+    s->initsvtor0 = s->initsvtor0_rst;
-+    s->initsvtor1 = s->initsvtor1_rst;
-+    s->cpuwait = s->cpuwait_rst;
-     s->wicctrl = 0;
-     s->scsecctrl = 0;
-     s->fclk_div = 0;
-@@ -XXX,XX +XXX,XX @@ static const VMStateDescription iotkit_sysctl_vmstate = {
- static Property iotkit_sysctl_props[] = {
-     DEFINE_PROP_UINT32("SYS_VERSION", IoTKitSysCtl, sys_version, 0),
-+    DEFINE_PROP_UINT32("CPUWAIT_RST", IoTKitSysCtl, cpuwait_rst, 0),
-+    DEFINE_PROP_UINT32("INITSVTOR0_RST", IoTKitSysCtl, initsvtor0_rst,
-+                       0x10000000),
-+    DEFINE_PROP_UINT32("INITSVTOR1_RST", IoTKitSysCtl, initsvtor1_rst,
-+                       0x10000000),
-     DEFINE_PROP_END_OF_LIST()
- };
---
-.20.1

-[Qemu-devel] [PULL 09/16] target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions
+Deleted patch
-Instead of gating the A32/T32 FP16 conversion instructions on
-the ARM_FEATURE_VFP_FP16 flag, switch to our new approach of
-looking at ID register bits. In this case MVFR1 fields FPHP
-and SIMDHP indicate the presence of these insns.
-This change doesn't alter behaviour for any of our CPUs.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20190222170936.13268-2-peter.maydell@linaro.org
----
- target/arm/cpu.h       | 37 ++++++++++++++++++++++++++++++++++++-
- target/arm/cpu.c       |  2 --
- target/arm/kvm32.c     |  3 ---
- target/arm/translate.c | 26 ++++++++++++++++++--------
-files changed, 54 insertions(+), 14 deletions(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
-+++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ FIELD(ID_DFR0, MPROFDBG, 20, 4)
- FIELD(ID_DFR0, PERFMON, 24, 4)
- FIELD(ID_DFR0, TRACEFILT, 28, 4)
-+FIELD(MVFR0, SIMDREG, 0, 4)
-+FIELD(MVFR0, FPSP, 4, 4)
-+FIELD(MVFR0, FPDP, 8, 4)
-+FIELD(MVFR0, FPTRAP, 12, 4)
-+FIELD(MVFR0, FPDIVIDE, 16, 4)
-+FIELD(MVFR0, FPSQRT, 20, 4)
-+FIELD(MVFR0, FPSHVEC, 24, 4)
-+FIELD(MVFR0, FPROUND, 28, 4)
-+
-+FIELD(MVFR1, FPFTZ, 0, 4)
-+FIELD(MVFR1, FPDNAN, 4, 4)
-+FIELD(MVFR1, SIMDLS, 8, 4)
-+FIELD(MVFR1, SIMDINT, 12, 4)
-+FIELD(MVFR1, SIMDSP, 16, 4)
-+FIELD(MVFR1, SIMDHP, 20, 4)
-+FIELD(MVFR1, FPHP, 24, 4)
-+FIELD(MVFR1, SIMDFMAC, 28, 4)
-+
-+FIELD(MVFR2, SIMDMISC, 0, 4)
-+FIELD(MVFR2, FPMISC, 4, 4)
-+
- QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
- /* If adding a feature bit which corresponds to a Linux ELF
-@@ -XXX,XX +XXX,XX @@ enum arm_features {
-     ARM_FEATURE_THUMB2,
-     ARM_FEATURE_PMSA,   /* no MMU; may have Memory Protection Unit */
-     ARM_FEATURE_VFP3,
--    ARM_FEATURE_VFP_FP16,
-     ARM_FEATURE_NEON,
-     ARM_FEATURE_M, /* Microcontroller profile.  */
-     ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
-     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
- }
-+/*
-+ * We always set the FP and SIMD FP16 fields to indicate identical
-+ * levels of support (assuming SIMD is implemented at all), so
-+ * we only need one set of accessors.
-+ */
-+static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id)
-+{
-+    return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 0;
-+}
-+
-+static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
-+{
-+    return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1;
-+}
-+
- /*
-  * 64-bit feature tests via id registers.
-  */
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
-+++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
-     }
-     if (arm_feature(env, ARM_FEATURE_VFP4)) {
-         set_feature(env, ARM_FEATURE_VFP3);
--        set_feature(env, ARM_FEATURE_VFP_FP16);
-     }
-     if (arm_feature(env, ARM_FEATURE_VFP3)) {
-         set_feature(env, ARM_FEATURE_VFP);
-@@ -XXX,XX +XXX,XX @@ static void cortex_a9_initfn(Object *obj)
-     cpu->dtb_compatible = "arm,cortex-a9";
-     set_feature(&cpu->env, ARM_FEATURE_V7);
-     set_feature(&cpu->env, ARM_FEATURE_VFP3);
--    set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
-     set_feature(&cpu->env, ARM_FEATURE_NEON);
-     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
-     set_feature(&cpu->env, ARM_FEATURE_EL3);
-diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/kvm32.c
-+++ b/target/arm/kvm32.c
-@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
-     if (extract32(id_pfr0, 12, 4) == 1) {
-         set_feature(&features, ARM_FEATURE_THUMB2EE);
-     }
--    if (extract32(ahcf->isar.mvfr1, 20, 4) == 1) {
--        set_feature(&features, ARM_FEATURE_VFP_FP16);
--    }
-     if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
-         set_feature(&features, ARM_FEATURE_NEON);
-     }
-diff --git a/target/arm/translate.c b/target/arm/translate.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
-                      * UNPREDICTABLE if bit 8 is set prior to ARMv8
-                      * (we choose to UNDEF)
-                      */
--                    if ((dp && !arm_dc_feature(s, ARM_FEATURE_V8)) ||
--                        !arm_dc_feature(s, ARM_FEATURE_VFP_FP16)) {
--                        return 1;
-+                    if (dp) {
-+                        if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
-+                            return 1;
-+                        }
-+                    } else {
-+                        if (!dc_isar_feature(aa32_fp16_spconv, s)) {
-+                            return 1;
-+                        }
-                     }
-                     rm_is_dp = false;
-                     break;
-                 case 0x06: /* vcvtb.f16.f32, vcvtb.f16.f64 */
-                 case 0x07: /* vcvtt.f16.f32, vcvtt.f16.f64 */
--                    if ((dp && !arm_dc_feature(s, ARM_FEATURE_V8)) ||
--                        !arm_dc_feature(s, ARM_FEATURE_VFP_FP16)) {
--                        return 1;
-+                    if (dp) {
-+                        if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
-+                            return 1;
-+                        }
-+                    } else {
-+                        if (!dc_isar_feature(aa32_fp16_spconv, s)) {
-+                            return 1;
-+                        }
-                     }
-                     rd_is_dp = false;
-                     break;
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                     TCGv_ptr fpst;
-                     TCGv_i32 ahp;
--                    if (!arm_dc_feature(s, ARM_FEATURE_VFP_FP16) ||
-+                    if (!dc_isar_feature(aa32_fp16_spconv, s) ||
-                         q || (rm & 1)) {
-                         return 1;
-                     }
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-                 {
-                     TCGv_ptr fpst;
-                     TCGv_i32 ahp;
--                    if (!arm_dc_feature(s, ARM_FEATURE_VFP_FP16) ||
-+                    if (!dc_isar_feature(aa32_fp16_spconv, s) ||
-                         q || (rd & 1)) {
-                         return 1;
-                     }
---
-.20.1

-[Qemu-devel] [PULL 11/16] Revert "arm: Allow system registers for KVM guests to be changed by QEMU code"
+[PULL 7/7] hw/nvram: Avoid unnecessary Xilinx eFuse backstore write
-This reverts commit 823e1b3818f9b10b824ddcd756983b6e2fa68730,
+From: Tong Ho <tong.ho@amd.com>
 which introduces a regression running EDK2 guest firmware
 under KVM:
-error: kvm run failed Function not implemented
+Add a check in the bit-set operation to write the backstore
- PC=000000013f5a6208 X00=00000000404003c4 X01=000000000000003a
+only if the affected bit is 0 before.
 X02=0000000000000000 X03=00000000404003c4 X04=0000000000000000
 X05=0000000096000046 X06=000000013d2ef270 X07=000000013e3d1710
 X08=09010755ffaf8ba8 X09=ffaf8b9cfeeb5468 X10=feeb546409010756
 X11=09010757ffaf8b90 X12=feeb50680903068b X13=090306a1ffaf8bc0
 X14=0000000000000000 X15=0000000000000000 X16=000000013f872da0
 X17=00000000ffffa6ab X18=0000000000000000 X19=000000013f5a92d0
 X20=000000013f5a7a78 X21=000000000000003a X22=000000013f5a7ab2
 X23=000000013f5a92e8 X24=000000013f631090 X25=0000000000000010
 X26=0000000000000100 X27=000000013f89501b X28=000000013e3d14e0
 X29=000000013e3d12a0 X30=000000013f5a2518  SP=000000013b7be0b0
 PSTATE=404003c4 -Z-- EL1t
-with
+With this in place, there will be no need for callers to
-[ 3507.926571] kvm [35042]: load/store instruction decoding not implemented
+do the checking in order to avoid unnecessary writes.
 in the host dmesg.
-Revert the change for the moment until we can investigate the
+Signed-off-by: Tong Ho <tong.ho@amd.com>
-cause of the regression.
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
-Reported-by: Eric Auger <eric.auger@redhat.com>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.h     |  9 +--------
+ hw/nvram/xlnx-efuse.c | 11 +++++++++--
- target/arm/helper.c  | 27 ++-------------------------
+file changed, 9 insertions(+), 2 deletions(-)
  target/arm/kvm32.c   | 20 ++++++++++++++++++--
  target/arm/kvm64.c   |  2 --
  target/arm/machine.c |  2 +-
 files changed, 22 insertions(+), 38 deletions(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/hw/nvram/xlnx-efuse.c
-+++ b/target/arm/cpu.h
++++ b/hw/nvram/xlnx-efuse.c
-@@ -XXX,XX +XXX,XX @@ bool write_list_to_cpustate(ARMCPU *cpu);
+@@ -XXX,XX +XXX,XX @@ static bool efuse_ro_bits_find(XlnxEFuse *s, uint32_t k)
- /**
-  * write_cpustate_to_list:
+ bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit)
-  * @cpu: ARMCPU
+ {
-- * @kvm_sync: true if this is for syncing back to KVM
++    uint32_t set, *row;
-  *
++
-  * For each register listed in the ARMCPU cpreg_indexes list, write
+     if (efuse_ro_bits_find(s, bit)) {
-  * its value from the ARMCPUState structure into the cpreg_values list.
+         g_autofree char *path = object_get_canonical_path(OBJECT(s));
-  * This is used to copy info from TCG's working data structures into
-  * KVM or for outbound migration.
+@@ -XXX,XX +XXX,XX @@ bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit)
-  *
+         return false;
-- * @kvm_sync is true if we are doing this in order to sync the
+     }
-- * register state back to KVM. In this case we will only update
-- * values in the list if the previous list->cpustate sync actually
+-    s->fuse32[bit / 32] |= 1 << (bit % 32);
-- * successfully wrote the CPU state. Otherwise we will keep the value
+-    efuse_bdrv_sync(s, bit);
-- * that is in the list.
++    /* Avoid back-end write unless there is a real update */
-- *
++    row = &s->fuse32[bit / 32];
-  * Returns: true if all register values were read correctly,
++    set = 1 << (bit % 32);
-  * false if some register was unknown or could not be read.
++    if (!(set & *row)) {
-  * Note that we do not stop early on failure -- we will attempt
++        *row |= set;
-  * reading all registers in the list.
++        efuse_bdrv_sync(s, bit);
-  */
++    }
 -bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
 +bool write_cpustate_to_list(ARMCPU *cpu);
  #define ARM_CPUID_TI915T      0x54029152
  #define ARM_CPUID_TI925T      0x54029252
 diff --git a/target/arm/helper.c b/target/arm/helper.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/helper.c
 +++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
      return true;
  }
--bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync)
-+bool write_cpustate_to_list(ARMCPU *cpu)
- {
-     /* Write the coprocessor state from cpu->env to the (index,value) list. */
-     int i;
-@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync)
-     for (i = 0; i < cpu->cpreg_array_len; i++) {
-         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
-         const ARMCPRegInfo *ri;
--        uint64_t newval;
-         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
-         if (!ri) {
-@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync)
-         if (ri->type & ARM_CP_NO_RAW) {
-             continue;
-         }
--
--        newval = read_raw_cp_reg(&cpu->env, ri);
--        if (kvm_sync) {
--            /*
--             * Only sync if the previous list->cpustate sync succeeded.
--             * Rather than tracking the success/failure state for every
--             * item in the list, we just recheck "does the raw write we must
--             * have made in write_list_to_cpustate() read back OK" here.
--             */
--            uint64_t oldval = cpu->cpreg_values[i];
--
--            if (oldval == newval) {
--                continue;
--            }
--
--            write_raw_cp_reg(&cpu->env, ri, oldval);
--            if (read_raw_cp_reg(&cpu->env, ri) != oldval) {
--                continue;
--            }
--
--            write_raw_cp_reg(&cpu->env, ri, newval);
--        }
--        cpu->cpreg_values[i] = newval;
-+        cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
-     }
-     return ok;
- }
-diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/kvm32.c
-+++ b/target/arm/kvm32.c
-@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
-         return ret;
-     }
--    write_cpustate_to_list(cpu, true);
--
-+    /* Note that we do not call write_cpustate_to_list()
-+     * here, so we are only writing the tuple list back to
-+     * KVM. This is safe because nothing can change the
-+     * CPUARMState cp15 fields (in particular gdb accesses cannot)
-+     * and so there are no changes to sync. In fact syncing would
-+     * be wrong at this point: for a constant register where TCG and
-+     * KVM disagree about its value, the preceding write_list_to_cpustate()
-+     * would not have had any effect on the CPUARMState value (since the
-+     * register is read-only), and a write_cpustate_to_list() here would
-+     * then try to write the TCG value back into KVM -- this would either
-+     * fail or incorrectly change the value the guest sees.
-+     *
-+     * If we ever want to allow the user to modify cp15 registers via
-+     * the gdb stub, we would need to be more clever here (for instance
-+     * tracking the set of registers kvm_arch_get_registers() successfully
-+     * managed to update the CPUARMState with, and only allowing those
-+     * to be written back up into the kernel).
-+     */
-     if (!write_list_to_kvmstate(cpu, level)) {
-         return EINVAL;
-     }
-diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/kvm64.c
-+++ b/target/arm/kvm64.c
-@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
-         return ret;
-     }
--    write_cpustate_to_list(cpu, true);
--
-     if (!write_list_to_kvmstate(cpu, level)) {
-         return EINVAL;
-     }
-diff --git a/target/arm/machine.c b/target/arm/machine.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/machine.c
-+++ b/target/arm/machine.c
-@@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque)
-             abort();
-         }
-     } else {
--        if (!write_cpustate_to_list(cpu, false)) {
-+        if (!write_cpustate_to_list(cpu)) {
-             /* This should never fail. */
-             abort();
-         }
 --
-.20.1
+.34.1

-[Qemu-devel] [PULL 12/16] target/arm: Add helpers for FMLAL
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Note that float16_to_float32 rightly squashes SNaN to QNaN.
-But of course pickNaNMulAdd, for ARM, selects SNaNs first.
-So we have to preserve SNaN long enough for the correct NaN
-to be selected.  Thus float16_to_float32_by_bits.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20190219222952.22183-2-richard.henderson@linaro.org
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/helper.h     |   9 +++
- target/arm/vec_helper.c | 148 ++++++++++++++++++++++++++++++++++++++++
-files changed, 157 insertions(+)
-diff --git a/target/arm/helper.h b/target/arm/helper.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.h
-+++ b/target/arm/helper.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_sqsub_s, TCG_CALL_NO_RWG,
- DEF_HELPER_FLAGS_5(gvec_sqsub_d, TCG_CALL_NO_RWG,
-                    void, ptr, ptr, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_5(gvec_fmlal_a32, TCG_CALL_NO_RWG,
-+                   void, ptr, ptr, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_5(gvec_fmlal_a64, TCG_CALL_NO_RWG,
-+                   void, ptr, ptr, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a32, TCG_CALL_NO_RWG,
-+                   void, ptr, ptr, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a64, TCG_CALL_NO_RWG,
-+                   void, ptr, ptr, ptr, ptr, i32)
-+
- #ifdef TARGET_AARCH64
- #include "helper-a64.h"
- #include "helper-sve.h"
-diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/vec_helper.c
-+++ b/target/arm/vec_helper.c
-@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sqsub_d)(void *vd, void *vq, void *vn,
-     }
-     clear_tail(d, oprsz, simd_maxsz(desc));
- }
-+
-+/*
-+ * Convert float16 to float32, raising no exceptions and
-+ * preserving exceptional values, including SNaN.
-+ * This is effectively an unpack+repack operation.
-+ */
-+static float32 float16_to_float32_by_bits(uint32_t f16, bool fz16)
-+{
-+    const int f16_bias = 15;
-+    const int f32_bias = 127;
-+    uint32_t sign = extract32(f16, 15, 1);
-+    uint32_t exp = extract32(f16, 10, 5);
-+    uint32_t frac = extract32(f16, 0, 10);
-+
-+    if (exp == 0x1f) {
-+        /* Inf or NaN */
-+        exp = 0xff;
-+    } else if (exp == 0) {
-+        /* Zero or denormal.  */
-+        if (frac != 0) {
-+            if (fz16) {
-+                frac = 0;
-+            } else {
-+                /*
-+                 * Denormal; these are all normal float32.
-+                 * Shift the fraction so that the msb is at bit 11,
-+                 * then remove bit 11 as the implicit bit of the
-+                 * normalized float32.  Note that we still go through
-+                 * the shift for normal numbers below, to put the
-+                 * float32 fraction at the right place.
-+                 */
-+                int shift = clz32(frac) - 21;
-+                frac = (frac << shift) & 0x3ff;
-+                exp = f32_bias - f16_bias - shift + 1;
-+            }
-+        }
-+    } else {
-+        /* Normal number; adjust the bias.  */
-+        exp += f32_bias - f16_bias;
-+    }
-+    sign <<= 31;
-+    exp <<= 23;
-+    frac <<= 23 - 10;
-+
-+    return sign | exp | frac;
-+}
-+
-+static uint64_t load4_f16(uint64_t *ptr, int is_q, int is_2)
-+{
-+    /*
-+     * Branchless load of u32[0], u64[0], u32[1], or u64[1].
-+     * Load the 2nd qword iff is_q & is_2.
-+     * Shift to the 2nd dword iff !is_q & is_2.
-+     * For !is_q & !is_2, the upper bits of the result are garbage.
-+     */
-+    return ptr[is_q & is_2] >> ((is_2 & ~is_q) << 5);
-+}
-+
-+/*
-+ * Note that FMLAL requires oprsz == 8 or oprsz == 16,
-+ * as there is not yet SVE versions that might use blocking.
-+ */
-+
-+static void do_fmlal(float32 *d, void *vn, void *vm, float_status *fpst,
-+                     uint32_t desc, bool fz16)
-+{
-+    intptr_t i, oprsz = simd_oprsz(desc);
-+    int is_s = extract32(desc, SIMD_DATA_SHIFT, 1);
-+    int is_2 = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
-+    int is_q = oprsz == 16;
-+    uint64_t n_4, m_4;
-+
-+    /* Pre-load all of the f16 data, avoiding overlap issues.  */
-+    n_4 = load4_f16(vn, is_q, is_2);
-+    m_4 = load4_f16(vm, is_q, is_2);
-+
-+    /* Negate all inputs for FMLSL at once.  */
-+    if (is_s) {
-+        n_4 ^= 0x8000800080008000ull;
-+    }
-+
-+    for (i = 0; i < oprsz / 4; i++) {
-+        float32 n_1 = float16_to_float32_by_bits(n_4 >> (i * 16), fz16);
-+        float32 m_1 = float16_to_float32_by_bits(m_4 >> (i * 16), fz16);
-+        d[H4(i)] = float32_muladd(n_1, m_1, d[H4(i)], 0, fpst);
-+    }
-+    clear_tail(d, oprsz, simd_maxsz(desc));
-+}
-+
-+void HELPER(gvec_fmlal_a32)(void *vd, void *vn, void *vm,
-+                            void *venv, uint32_t desc)
-+{
-+    CPUARMState *env = venv;
-+    do_fmlal(vd, vn, vm, &env->vfp.standard_fp_status, desc,
-+             get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
-+}
-+
-+void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void *vm,
-+                            void *venv, uint32_t desc)
-+{
-+    CPUARMState *env = venv;
-+    do_fmlal(vd, vn, vm, &env->vfp.fp_status, desc,
-+             get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
-+}
-+
-+static void do_fmlal_idx(float32 *d, void *vn, void *vm, float_status *fpst,
-+                         uint32_t desc, bool fz16)
-+{
-+    intptr_t i, oprsz = simd_oprsz(desc);
-+    int is_s = extract32(desc, SIMD_DATA_SHIFT, 1);
-+    int is_2 = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
-+    int index = extract32(desc, SIMD_DATA_SHIFT + 2, 3);
-+    int is_q = oprsz == 16;
-+    uint64_t n_4;
-+    float32 m_1;
-+
-+    /* Pre-load all of the f16 data, avoiding overlap issues.  */
-+    n_4 = load4_f16(vn, is_q, is_2);
-+
-+    /* Negate all inputs for FMLSL at once.  */
-+    if (is_s) {
-+        n_4 ^= 0x8000800080008000ull;
-+    }
-+
-+    m_1 = float16_to_float32_by_bits(((float16 *)vm)[H2(index)], fz16);
-+
-+    for (i = 0; i < oprsz / 4; i++) {
-+        float32 n_1 = float16_to_float32_by_bits(n_4 >> (i * 16), fz16);
-+        d[H4(i)] = float32_muladd(n_1, m_1, d[H4(i)], 0, fpst);
-+    }
-+    clear_tail(d, oprsz, simd_maxsz(desc));
-+}
-+
-+void HELPER(gvec_fmlal_idx_a32)(void *vd, void *vn, void *vm,
-+                                void *venv, uint32_t desc)
-+{
-+    CPUARMState *env = venv;
-+    do_fmlal_idx(vd, vn, vm, &env->vfp.standard_fp_status, desc,
-+                 get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
-+}
-+
-+void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm,
-+                                void *venv, uint32_t desc)
-+{
-+    CPUARMState *env = venv;
-+    do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status, desc,
-+                 get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
-+}
---
-.20.1

-[Qemu-devel] [PULL 13/16] target/arm: Implement FMLAL and FMLSL for aarch64
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20190219222952.22183-3-richard.henderson@linaro.org
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/cpu.h           |  5 ++++
- target/arm/translate-a64.c | 49 +++++++++++++++++++++++++++++++++++++-
-files changed, 53 insertions(+), 1 deletion(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
-+++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
-     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
- }
-+static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id)
-+{
-+    return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
-+}
-+
- static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
- {
-     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
-diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate-a64.c
-+++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_float(DisasContext *s, uint32_t insn)
-         if (!fp_access_check(s)) {
-             return;
-         }
--
-         handle_3same_float(s, size, elements, fpopcode, rd, rn, rm);
-         return;
-+
-+    case 0x1d: /* FMLAL  */
-+    case 0x3d: /* FMLSL  */
-+    case 0x59: /* FMLAL2 */
-+    case 0x79: /* FMLSL2 */
-+        if (size & 1 || !dc_isar_feature(aa64_fhm, s)) {
-+            unallocated_encoding(s);
-+            return;
-+        }
-+        if (fp_access_check(s)) {
-+            int is_s = extract32(insn, 23, 1);
-+            int is_2 = extract32(insn, 29, 1);
-+            int data = (is_2 << 1) | is_s;
-+            tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
-+                               vec_full_reg_offset(s, rn),
-+                               vec_full_reg_offset(s, rm), cpu_env,
-+                               is_q ? 16 : 8, vec_full_reg_size(s),
-+                               data, gen_helper_gvec_fmlal_a64);
-+        }
-+        return;
-+
-     default:
-         unallocated_encoding(s);
-         return;
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
-         }
-         is_fp = 2;
-         break;
-+    case 0x00: /* FMLAL */
-+    case 0x04: /* FMLSL */
-+    case 0x18: /* FMLAL2 */
-+    case 0x1c: /* FMLSL2 */
-+        if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_fhm, s)) {
-+            unallocated_encoding(s);
-+            return;
-+        }
-+        size = MO_16;
-+        /* is_fp, but we pass cpu_env not fp_status.  */
-+        break;
-     default:
-         unallocated_encoding(s);
-         return;
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
-             tcg_temp_free_ptr(fpst);
-         }
-         return;
-+
-+    case 0x00: /* FMLAL */
-+    case 0x04: /* FMLSL */
-+    case 0x18: /* FMLAL2 */
-+    case 0x1c: /* FMLSL2 */
-+        {
-+            int is_s = extract32(opcode, 2, 1);
-+            int is_2 = u;
-+            int data = (index << 2) | (is_2 << 1) | is_s;
-+            tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
-+                               vec_full_reg_offset(s, rn),
-+                               vec_full_reg_offset(s, rm), cpu_env,
-+                               is_q ? 16 : 8, vec_full_reg_size(s),
-+                               data, gen_helper_gvec_fmlal_idx_a64);
-+        }
-+        return;
-     }
-     if (size == 3) {
---
-.20.1

-[Qemu-devel] [PULL 15/16] target/arm: Enable ARMv8.2-FHM for -cpu max
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20190219222952.22183-5-richard.henderson@linaro.org
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/cpu.c   | 1 +
- target/arm/cpu64.c | 2 ++
-files changed, 3 insertions(+)
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
-+++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
-             t = cpu->isar.id_isar6;
-             t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
-             t = FIELD_DP32(t, ID_ISAR6, DP, 1);
-+            t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
-             cpu->isar.id_isar6 = t;
-             t = cpu->id_mmfr4;
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu64.c
-+++ b/target/arm/cpu64.c
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
-         t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
-         t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
-         t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
-+        t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
-         cpu->isar.id_aa64isar0 = t;
-         t = cpu->isar.id_aa64isar1;
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
-         u = cpu->isar.id_isar6;
-         u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
-         u = FIELD_DP32(u, ID_ISAR6, DP, 1);
-+        u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
-         cpu->isar.id_isar6 = u;
-         /*
---
-.20.1

The following changes since commit adf2e451f357e993f173ba9b4176dbf3e65fee7e:

Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2019-02-26 19:04:47 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190228-1

for you to fetch changes up to 1c9af3a9e05c1607a36df4943f8f5393d7621a91:

linux-user: Enable HWCAP_ASIMDFHM, HWCAP_JSCVT (2019-02-28 11:03:05 +0000)

----------------------------------------------------------------
target-arm queue:
 * add MHU and dual-core support to Musca boards
 * refactor some VFP insns to be gated by ID registers
 * Revert "arm: Allow system registers for KVM guests to be changed by QEMU code"
 * Implement ARMv8.2-FHM extension
 * Advertise JSCVT via HWCAP for linux-user

----------------------------------------------------------------
Peter Maydell (11):
      hw/misc/armsse-mhu.c: Model the SSE-200 Message Handling Unit
      hw/arm/armsse: Wire up the MHUs
      target/arm/cpu: Allow init-svtor property to be set after realize
      target/arm/arm-powerctl: Add new arm_set_cpu_on_and_reset()
      hw/misc/iotkit-sysctl: Correct typo in INITSVTOR0 register name
      hw/arm/iotkit-sysctl: Add SSE-200 registers
      hw/arm/iotkit-sysctl: Implement CPUWAIT and INITSVTOR*
      hw/arm/armsse: Unify init-svtor and cpuwait handling
      target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions
      target/arm: Gate "miscellaneous FP" insns by ID register field
      Revert "arm: Allow system registers for KVM guests to be changed by QEMU code"

Richard Henderson (5):
      target/arm: Add helpers for FMLAL
      target/arm: Implement FMLAL and FMLSL for aarch64
      target/arm: Implement VFMAL and VFMSL for aarch32
      target/arm: Enable ARMv8.2-FHM for -cpu max
      linux-user: Enable HWCAP_ASIMDFHM, HWCAP_JSCVT

Implement a model of the Message Handling Unit (MHU) found in
the Arm SSE-200. This is a simple device which just contains
some registers which allow the two cores of the SSE-200
to raise interrupts on each other.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190219125808.25174-2-peter.maydell@linaro.org
---
 hw/misc/Makefile.objs           |   1 +
 include/hw/misc/armsse-mhu.h    |  44 +++++++
 hw/misc/armsse-mhu.c            | 198 ++++++++++++++++++++++++++++++++
 MAINTAINERS                     |   2 +
 default-configs/arm-softmmu.mak |   1 +
 hw/misc/trace-events            |   4 +
 6 files changed, 250 insertions(+)
 create mode 100644 include/hw/misc/armsse-mhu.h
 create mode 100644 hw/misc/armsse-mhu.c

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_IOTKIT_SECCTL) += iotkit-secctl.o
 obj-$(CONFIG_IOTKIT_SYSCTL) += iotkit-sysctl.o
 obj-$(CONFIG_IOTKIT_SYSINFO) += iotkit-sysinfo.o
 obj-$(CONFIG_ARMSSE_CPUID) += armsse-cpuid.o
+obj-$(CONFIG_ARMSSE_MHU) += armsse-mhu.o
 
 obj-$(CONFIG_PVPANIC) += pvpanic.o
 obj-$(CONFIG_AUX) += auxbus.o
diff --git a/include/hw/misc/armsse-mhu.h b/include/hw/misc/armsse-mhu.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/armsse-mhu.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * ARM SSE-200 Message Handling Unit (MHU)
+ *
+ * Copyright (c) 2019 Linaro Limited
+ * Written by Peter Maydell
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 or
+ *  (at your option) any later version.
+ */
+
+/*
+ * This is a model of the Message Handling Unit (MHU) which is part of the
+ * Arm SSE-200 and documented in
+ * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
+ *
+ * QEMU interface:
+ *  + sysbus MMIO region 0: the system information register bank
+ *  + sysbus IRQ 0: interrupt for CPU 0
+ *  + sysbus IRQ 1: interrupt for CPU 1
+ */
+
+#ifndef HW_MISC_SSE_MHU_H
+#define HW_MISC_SSE_MHU_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_ARMSSE_MHU "armsse-mhu"
+#define ARMSSE_MHU(obj) OBJECT_CHECK(ARMSSEMHU, (obj), TYPE_ARMSSE_MHU)
+
+typedef struct ARMSSEMHU {
+    /*< private >*/
+    SysBusDevice parent_obj;
+
+    /*< public >*/
+    MemoryRegion iomem;
+    qemu_irq cpu0irq;
+    qemu_irq cpu1irq;
+
+    uint32_t cpu0intr;
+    uint32_t cpu1intr;
+} ARMSSEMHU;
+
+#endif
diff --git a/hw/misc/armsse-mhu.c b/hw/misc/armsse-mhu.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/armsse-mhu.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * ARM SSE-200 Message Handling Unit (MHU)
+ *
+ * Copyright (c) 2019 Linaro Limited
+ * Written by Peter Maydell
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 or
+ *  (at your option) any later version.
+ */
+
+/*
+ * This is a model of the Message Handling Unit (MHU) which is part of the
+ * Arm SSE-200 and documented in
+ * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "trace.h"
+#include "qapi/error.h"
+#include "sysemu/sysemu.h"
+#include "hw/sysbus.h"
+#include "hw/registerfields.h"
+#include "hw/misc/armsse-mhu.h"
+
+REG32(CPU0INTR_STAT, 0x0)
+REG32(CPU0INTR_SET, 0x4)
+REG32(CPU0INTR_CLR, 0x8)
+REG32(CPU1INTR_STAT, 0x10)
+REG32(CPU1INTR_SET, 0x14)
+REG32(CPU1INTR_CLR, 0x18)
+REG32(PID4, 0xfd0)
+REG32(PID5, 0xfd4)
+REG32(PID6, 0xfd8)
+REG32(PID7, 0xfdc)
+REG32(PID0, 0xfe0)
+REG32(PID1, 0xfe4)
+REG32(PID2, 0xfe8)
+REG32(PID3, 0xfec)
+REG32(CID0, 0xff0)
+REG32(CID1, 0xff4)
+REG32(CID2, 0xff8)
+REG32(CID3, 0xffc)
+
+/* Valid bits in the interrupt registers. If any are set the IRQ is raised */
+#define INTR_MASK 0xf
+
+/* PID/CID values */
+static const int armsse_mhu_id[] = {
+    0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
+    0x56, 0xb8, 0x0b, 0x00, /* PID0..PID3 */
+    0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
+};
+
+static void armsse_mhu_update(ARMSSEMHU *s)
+{
+    qemu_set_irq(s->cpu0irq, s->cpu0intr != 0);
+    qemu_set_irq(s->cpu1irq, s->cpu1intr != 0);
+}
+
+static uint64_t armsse_mhu_read(void *opaque, hwaddr offset, unsigned size)
+{
+    ARMSSEMHU *s = ARMSSE_MHU(opaque);
+    uint64_t r;
+
+    switch (offset) {
+    case A_CPU0INTR_STAT:
+        r = s->cpu0intr;
+        break;
+
+    case A_CPU1INTR_STAT:
+        r = s->cpu1intr;
+        break;
+
+    case A_PID4 ... A_CID3:
+        r = armsse_mhu_id[(offset - A_PID4) / 4];
+        break;
+
+    case A_CPU0INTR_SET:
+    case A_CPU0INTR_CLR:
+    case A_CPU1INTR_SET:
+    case A_CPU1INTR_CLR:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "SSE MHU: read of write-only register at offset 0x%x\n",
+                      (int)offset);
+        r = 0;
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "SSE MHU read: bad offset 0x%x\n", (int)offset);
+        r = 0;
+        break;
+    }
+    trace_armsse_mhu_read(offset, r, size);
+    return r;
+}
+
+static void armsse_mhu_write(void *opaque, hwaddr offset,
+                             uint64_t value, unsigned size)
+{
+    ARMSSEMHU *s = ARMSSE_MHU(opaque);
+
+    trace_armsse_mhu_write(offset, value, size);
+
+    switch (offset) {
+    case A_CPU0INTR_SET:
+        s->cpu0intr |= (value & INTR_MASK);
+        break;
+    case A_CPU0INTR_CLR:
+        s->cpu0intr &= ~(value & INTR_MASK);
+        break;
+    case A_CPU1INTR_SET:
+        s->cpu1intr |= (value & INTR_MASK);
+        break;
+    case A_CPU1INTR_CLR:
+        s->cpu1intr &= ~(value & INTR_MASK);
+        break;
+
+    case A_CPU0INTR_STAT:
+    case A_CPU1INTR_STAT:
+    case A_PID4 ... A_CID3:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "SSE MHU: write to read-only register at offset 0x%x\n",
+                      (int)offset);
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "SSE MHU write: bad offset 0x%x\n", (int)offset);
+        break;
+    }
+
+    armsse_mhu_update(s);
+}
+
+static const MemoryRegionOps armsse_mhu_ops = {
+    .read = armsse_mhu_read,
+    .write = armsse_mhu_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid.min_access_size = 4,
+    .valid.max_access_size = 4,
+};
+
+static void armsse_mhu_reset(DeviceState *dev)
+{
+    ARMSSEMHU *s = ARMSSE_MHU(dev);
+
+    s->cpu0intr = 0;
+    s->cpu1intr = 0;
+}
+
+static const VMStateDescription armsse_mhu_vmstate = {
+    .name = "armsse-mhu",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(cpu0intr, ARMSSEMHU),
+        VMSTATE_UINT32(cpu1intr, ARMSSEMHU),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
+static void armsse_mhu_init(Object *obj)
+{
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    ARMSSEMHU *s = ARMSSE_MHU(obj);
+
+    memory_region_init_io(&s->iomem, obj, &armsse_mhu_ops,
+                          s, "armsse-mhu", 0x1000);
+    sysbus_init_mmio(sbd, &s->iomem);
+    sysbus_init_irq(sbd, &s->cpu0irq);
+    sysbus_init_irq(sbd, &s->cpu1irq);
+}
+
+static void armsse_mhu_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset = armsse_mhu_reset;
+    dc->vmsd = &armsse_mhu_vmstate;
+}
+
+static const TypeInfo armsse_mhu_info = {
+    .name = TYPE_ARMSSE_MHU,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(ARMSSEMHU),
+    .instance_init = armsse_mhu_init,
+    .class_init = armsse_mhu_class_init,
+};
+
+static void armsse_mhu_register_types(void)
+{
+    type_register_static(&armsse_mhu_info);
+}
+
+type_init(armsse_mhu_register_types);
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: hw/misc/iotkit-sysinfo.c
 F: include/hw/misc/iotkit-sysinfo.h
 F: hw/misc/armsse-cpuid.c
 F: include/hw/misc/armsse-cpuid.h
+F: hw/misc/armsse-mhu.c
+F: include/hw/misc/armsse-mhu.h
 
 Musca
 M: Peter Maydell <peter.maydell@linaro.org>
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index XXXXXXX..XXXXXXX 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -XXX,XX +XXX,XX @@ CONFIG_IOTKIT_SECCTL=y
 CONFIG_IOTKIT_SYSCTL=y
 CONFIG_IOTKIT_SYSINFO=y
 CONFIG_ARMSSE_CPUID=y
+CONFIG_ARMSSE_MHU=y
 
 CONFIG_VERSATILE=y
 CONFIG_VERSATILE_PCI=y
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -XXX,XX +XXX,XX @@ iotkit_sysctl_reset(void) "IoTKit SysCtl: reset"
 # hw/misc/armsse-cpuid.c
 armsse_cpuid_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
 armsse_cpuid_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
+
+# hw/misc/armsse-mhu.c
+armsse_mhu_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
+armsse_mhu_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
-- 
2.20.1

Create and connect the MHUs in the SSE-200.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190219125808.25174-3-peter.maydell@linaro.org
---
 include/hw/arm/armsse.h |  3 ++-
 hw/arm/armsse.c         | 40 ++++++++++++++++++++++++++++++----------
 2 files changed, 32 insertions(+), 11 deletions(-)

diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/armsse.h
+++ b/include/hw/arm/armsse.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/iotkit-sysctl.h"
 #include "hw/misc/iotkit-sysinfo.h"
 #include "hw/misc/armsse-cpuid.h"
+#include "hw/misc/armsse-mhu.h"
 #include "hw/misc/unimp.h"
 #include "hw/or-irq.h"
 #include "hw/core/split-irq.h"
@@ -XXX,XX +XXX,XX @@ typedef struct ARMSSE {
     IoTKitSysCtl sysctl;
     IoTKitSysCtl sysinfo;
 
-    UnimplementedDeviceState mhu[2];
+    ARMSSEMHU mhu[2];
     UnimplementedDeviceState ppu[NUM_PPUS];
     UnimplementedDeviceState cachectrl[SSE_MAX_CPUS];
     UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS];
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -XXX,XX +XXX,XX @@ static void armsse_init(Object *obj)
                           sizeof(s->sysinfo), TYPE_IOTKIT_SYSINFO);
     if (info->has_mhus) {
         sysbus_init_child_obj(obj, "mhu0", &s->mhu[0], sizeof(s->mhu[0]),
-                              TYPE_UNIMPLEMENTED_DEVICE);
+                              TYPE_ARMSSE_MHU);
         sysbus_init_child_obj(obj, "mhu1", &s->mhu[1], sizeof(s->mhu[1]),
-                              TYPE_UNIMPLEMENTED_DEVICE);
+                              TYPE_ARMSSE_MHU);
     }
     if (info->has_ppus) {
         for (i = 0; i < info->num_cpus; i++) {
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
     }
 
     if (info->has_mhus) {
-        for (i = 0; i < ARRAY_SIZE(s->mhu); i++) {
-            char *name;
-            char *port;
+        /*
+         * An SSE-200 with only one CPU should have only one MHU created,
+         * with the region where the second MHU usually is being RAZ/WI.
+         * We don't implement that SSE-200 config; if we want to support
+         * it then this code needs to be enhanced to handle creating the
+         * RAZ/WI region instead of the second MHU.
+         */
+        assert(info->num_cpus == ARRAY_SIZE(s->mhu));
+
+        for (i = 0; i < ARRAY_SIZE(s->mhu); i++) {
+            char *port;
+            int cpunum;
+            SysBusDevice *mhu_sbd = SYS_BUS_DEVICE(&s->mhu[i]);
 
-            name = g_strdup_printf("MHU%d", i);
-            qdev_prop_set_string(DEVICE(&s->mhu[i]), "name", name);
-            qdev_prop_set_uint64(DEVICE(&s->mhu[i]), "size", 0x1000);
             object_property_set_bool(OBJECT(&s->mhu[i]), true,
                                      "realized", &err);
-            g_free(name);
             if (err) {
                 error_propagate(errp, err);
                 return;
             }
             port = g_strdup_printf("port[%d]", i + 3);
-            mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mhu[i]), 0);
+            mr = sysbus_mmio_get_region(mhu_sbd, 0);
             object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr),
                                      port, &err);
             g_free(port);
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
                 error_propagate(errp, err);
                 return;
             }
+
+            /*
+             * Each MHU has an irq line for each CPU:
+             *  MHU 0 irq line 0 -> CPU 0 IRQ 6
+             *  MHU 0 irq line 1 -> CPU 1 IRQ 6
+             *  MHU 1 irq line 0 -> CPU 0 IRQ 7
+             *  MHU 1 irq line 1 -> CPU 1 IRQ 7
+             */
+            for (cpunum = 0; cpunum < info->num_cpus; cpunum++) {
+                DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]);
+
+                sysbus_connect_irq(mhu_sbd, cpunum,
+                                   qdev_get_gpio_in(cpudev, 6 + i));
+            }
         }
     }
 
-- 
2.20.1

Make the M-profile "init-svtor" property be settable after realize.
This matches the hardware, where this is a config signal which
is sampled on CPU reset and can thus be changed between one
reset and another. To do this we have to change the API we
use to add the property.

(We will need this capability for the SSE-200.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190219125808.25174-4-peter.maydell@linaro.org
---
 target/arm/cpu.c | 29 ++++++++++++++++++++++++-----
 1 file changed, 24 insertions(+), 5 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
 #include "target/arm/idau.h"
 #include "qemu/error-report.h"
 #include "qapi/error.h"
+#include "qapi/visitor.h"
 #include "cpu.h"
 #include "internals.h"
 #include "qemu-common.h"
@@ -XXX,XX +XXX,XX @@ static Property arm_cpu_pmsav7_dregion_property =
                                            pmsav7_dregion,
                                            qdev_prop_uint32, uint32_t);
 
-/* M profile: initial value of the Secure VTOR */
-static Property arm_cpu_initsvtor_property =
-            DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0);
+static void arm_get_init_svtor(Object *obj, Visitor *v, const char *name,
+                               void *opaque, Error **errp)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    visit_type_uint32(v, name, &cpu->init_svtor, errp);
+}
+
+static void arm_set_init_svtor(Object *obj, Visitor *v, const char *name,
+                               void *opaque, Error **errp)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    visit_type_uint32(v, name, &cpu->init_svtor, errp);
+}
 
 void arm_cpu_post_init(Object *obj)
 {
@@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj)
                                  qdev_prop_allow_set_link_before_realize,
                                  OBJ_PROP_LINK_STRONG,
                                  &error_abort);
-        qdev_property_add_static(DEVICE(obj), &arm_cpu_initsvtor_property,
-                                 &error_abort);
+        /*
+         * M profile: initial value of the Secure VTOR. We can't just use
+         * a simple DEFINE_PROP_UINT32 for this because we want to permit
+         * the property to be set after realize.
+         */
+        object_property_add(obj, "init-svtor", "uint32",
+                            arm_get_init_svtor, arm_set_init_svtor,
+                            NULL, NULL, &error_abort);
     }
 
     qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
-- 
2.20.1

Currently the Arm arm-powerctl.h APIs allow:
 * arm_set_cpu_on(), which powers on a CPU and sets its
   initial PC and other startup state
 * arm_reset_cpu(), which resets a CPU which is already on
   (and fails if the CPU is powered off)

but there is no way to say "power on a CPU as if it had
just come out of reset and don't do anything else to it".

Add a new function arm_set_cpu_on_and_reset(), which does this.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190219125808.25174-5-peter.maydell@linaro.org
---
 target/arm/arm-powerctl.h | 16 +++++++++++
 target/arm/arm-powerctl.c | 56 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 72 insertions(+)

diff --git a/target/arm/arm-powerctl.h b/target/arm/arm-powerctl.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/arm-powerctl.h
+++ b/target/arm/arm-powerctl.h
@@ -XXX,XX +XXX,XX @@ int arm_set_cpu_off(uint64_t cpuid);
  */
 int arm_reset_cpu(uint64_t cpuid);
 
+/*
+ * arm_set_cpu_on_and_reset:
+ * @cpuid: the id of the CPU we want to star
+ *
+ * Start the cpu designated by @cpuid and put it through its normal
+ * CPU reset process. The CPU will start in the way it is architected
+ * to start after a power-on reset.
+ *
+ * Returns: QEMU_ARM_POWERCTL_RET_SUCCESS on success.
+ * QEMU_ARM_POWERCTL_INVALID_PARAM if there is no CPU with that ID.
+ * QEMU_ARM_POWERCTL_ALREADY_ON if the CPU is already on.
+ * QEMU_ARM_POWERCTL_ON_PENDING if the CPU is already partway through
+ * powering on.
+ */
+int arm_set_cpu_on_and_reset(uint64_t cpuid);
+
 #endif
diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/arm-powerctl.c
+++ b/target/arm/arm-powerctl.c
@@ -XXX,XX +XXX,XX @@ int arm_set_cpu_on(uint64_t cpuid, uint64_t entry, uint64_t context_id,
     return QEMU_ARM_POWERCTL_RET_SUCCESS;
 }
 
+static void arm_set_cpu_on_and_reset_async_work(CPUState *target_cpu_state,
+                                                run_on_cpu_data data)
+{
+    ARMCPU *target_cpu = ARM_CPU(target_cpu_state);
+
+    /* Initialize the cpu we are turning on */
+    cpu_reset(target_cpu_state);
+    target_cpu_state->halted = 0;
+
+    /* Finally set the power status */
+    assert(qemu_mutex_iothread_locked());
+    target_cpu->power_state = PSCI_ON;
+}
+
+int arm_set_cpu_on_and_reset(uint64_t cpuid)
+{
+    CPUState *target_cpu_state;
+    ARMCPU *target_cpu;
+
+    assert(qemu_mutex_iothread_locked());
+
+    /* Retrieve the cpu we are powering up */
+    target_cpu_state = arm_get_cpu_by_id(cpuid);
+    if (!target_cpu_state) {
+        /* The cpu was not found */
+        return QEMU_ARM_POWERCTL_INVALID_PARAM;
+    }
+
+    target_cpu = ARM_CPU(target_cpu_state);
+    if (target_cpu->power_state == PSCI_ON) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "[ARM]%s: CPU %" PRId64 " is already on\n",
+                      __func__, cpuid);
+        return QEMU_ARM_POWERCTL_ALREADY_ON;
+    }
+
+    /*
+     * If another CPU has powered the target on we are in the state
+     * ON_PENDING and additional attempts to power on the CPU should
+     * fail (see 6.6 Implementation CPU_ON/CPU_OFF races in the PSCI
+     * spec)
+     */
+    if (target_cpu->power_state == PSCI_ON_PENDING) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "[ARM]%s: CPU %" PRId64 " is already powering on\n",
+                      __func__, cpuid);
+        return QEMU_ARM_POWERCTL_ON_PENDING;
+    }
+
+    async_run_on_cpu(target_cpu_state, arm_set_cpu_on_and_reset_async_work,
+                     RUN_ON_CPU_NULL);
+
+    /* We are good to go */
+    return QEMU_ARM_POWERCTL_RET_SUCCESS;
+}
+
 static void arm_set_cpu_off_async_work(CPUState *target_cpu_state,
                                        run_on_cpu_data data)
 {
-- 
2.20.1

The iotkit-sysctl device has a register it names INITSVRTOR0.
This is actually a typo present in the IoTKit documentation
and also in part of the SSE-200 documentation:  it should be
INITSVTOR0 because it is specifying the initial value of the
Secure VTOR register in the CPU. Correct the typo.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190219125808.25174-6-peter.maydell@linaro.org
---
 include/hw/misc/iotkit-sysctl.h |  2 +-
 hw/misc/iotkit-sysctl.c         | 16 ++++++++--------
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/misc/iotkit-sysctl.h
+++ b/include/hw/misc/iotkit-sysctl.h
@@ -XXX,XX +XXX,XX @@ typedef struct IoTKitSysCtl {
     uint32_t reset_syndrome;
     uint32_t reset_mask;
     uint32_t gretreg;
-    uint32_t initsvrtor0;
+    uint32_t initsvtor0;
     uint32_t cpuwait;
     uint32_t wicctrl;
 } IoTKitSysCtl;
diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/iotkit-sysctl.c
+++ b/hw/misc/iotkit-sysctl.c
@@ -XXX,XX +XXX,XX @@ REG32(RESET_MASK, 0x104)
 REG32(SWRESET, 0x108)
     FIELD(SWRESET, SWRESETREQ, 9, 1)
 REG32(GRETREG, 0x10c)
-REG32(INITSVRTOR0, 0x110)
+REG32(INITSVTOR0, 0x110)
 REG32(CPUWAIT, 0x118)
 REG32(BUSWAIT, 0x11c)
 REG32(WICCTRL, 0x120)
@@ -XXX,XX +XXX,XX @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
     case A_GRETREG:
         r = s->gretreg;
         break;
-    case A_INITSVRTOR0:
-        r = s->initsvrtor0;
+    case A_INITSVTOR0:
+        r = s->initsvtor0;
         break;
     case A_CPUWAIT:
         r = s->cpuwait;
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
          */
         s->gretreg = value;
         break;
-    case A_INITSVRTOR0:
-        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVRTOR0 unimplemented\n");
-        s->initsvrtor0 = value;
+    case A_INITSVTOR0:
+        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR0 unimplemented\n");
+        s->initsvtor0 = value;
         break;
     case A_CPUWAIT:
         qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CPUWAIT unimplemented\n");
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_reset(DeviceState *dev)
     s->reset_syndrome = 1;
     s->reset_mask = 0;
     s->gretreg = 0;
-    s->initsvrtor0 = 0x10000000;
+    s->initsvtor0 = 0x10000000;
     s->cpuwait = 0;
     s->wicctrl = 0;
 }
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription iotkit_sysctl_vmstate = {
         VMSTATE_UINT32(reset_syndrome, IoTKitSysCtl),
         VMSTATE_UINT32(reset_mask, IoTKitSysCtl),
         VMSTATE_UINT32(gretreg, IoTKitSysCtl),
-        VMSTATE_UINT32(initsvrtor0, IoTKitSysCtl),
+        VMSTATE_UINT32(initsvtor0, IoTKitSysCtl),
         VMSTATE_UINT32(cpuwait, IoTKitSysCtl),
         VMSTATE_UINT32(wicctrl, IoTKitSysCtl),
         VMSTATE_END_OF_LIST()
-- 
2.20.1

The SYSCTL block in the SSE-200 has some extra registers that
are not present in the IoTKit version. Add these registers
(as reads-as-written stubs), enabled by a new QOM property.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190219125808.25174-7-peter.maydell@linaro.org
---
 include/hw/misc/iotkit-sysctl.h |  20 +++
 hw/arm/armsse.c                 |   2 +
 hw/misc/iotkit-sysctl.c         | 245 +++++++++++++++++++++++++++++++-
 3 files changed, 262 insertions(+), 5 deletions(-)

diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/misc/iotkit-sysctl.h
+++ b/include/hw/misc/iotkit-sysctl.h
@@ -XXX,XX +XXX,XX @@
  * "system control register" blocks.
  *
  * QEMU interface:
+ *  + QOM property "SYS_VERSION": value of the SYS_VERSION register of the
+ *    system information block of the SSE
+ *    (used to identify whether to provide SSE-200-only registers)
  *  + sysbus MMIO region 0: the system information register bank
  *  + sysbus MMIO region 1: the system control register bank
  */
@@ -XXX,XX +XXX,XX @@ typedef struct IoTKitSysCtl {
     uint32_t initsvtor0;
     uint32_t cpuwait;
     uint32_t wicctrl;
+    uint32_t scsecctrl;
+    uint32_t fclk_div;
+    uint32_t sysclk_div;
+    uint32_t clock_force;
+    uint32_t initsvtor1;
+    uint32_t nmi_enable;
+    uint32_t ewctrl;
+    uint32_t pdcm_pd_sys_sense;
+    uint32_t pdcm_pd_sram0_sense;
+    uint32_t pdcm_pd_sram1_sense;
+    uint32_t pdcm_pd_sram2_sense;
+    uint32_t pdcm_pd_sram3_sense;
+
+    /* Properties */
+    uint32_t sys_version;
+
+    bool is_sse200;
 } IoTKitSysCtl;
 
 #endif
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
     /* System information registers */
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysinfo), 0, 0x40020000);
     /* System control registers */
+    object_property_set_int(OBJECT(&s->sysctl), info->sys_version,
+                            "SYS_VERSION", &err);
     object_property_set_bool(OBJECT(&s->sysctl), true, "realized", &err);
     if (err) {
         error_propagate(errp, err);
diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/iotkit-sysctl.c
+++ b/hw/misc/iotkit-sysctl.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/bitops.h"
 #include "qemu/log.h"
 #include "trace.h"
 #include "qapi/error.h"
@@ -XXX,XX +XXX,XX @@
 REG32(SECDBGSTAT, 0x0)
 REG32(SECDBGSET, 0x4)
 REG32(SECDBGCLR, 0x8)
+REG32(SCSECCTRL, 0xc)
+REG32(FCLK_DIV, 0x10)
+REG32(SYSCLK_DIV, 0x14)
+REG32(CLOCK_FORCE, 0x18)
 REG32(RESET_SYNDROME, 0x100)
 REG32(RESET_MASK, 0x104)
 REG32(SWRESET, 0x108)
     FIELD(SWRESET, SWRESETREQ, 9, 1)
 REG32(GRETREG, 0x10c)
 REG32(INITSVTOR0, 0x110)
+REG32(INITSVTOR1, 0x114)
 REG32(CPUWAIT, 0x118)
-REG32(BUSWAIT, 0x11c)
+REG32(NMI_ENABLE, 0x11c) /* BUSWAIT in IoTKit */
 REG32(WICCTRL, 0x120)
+REG32(EWCTRL, 0x124)
+REG32(PDCM_PD_SYS_SENSE, 0x200)
+REG32(PDCM_PD_SRAM0_SENSE, 0x20c)
+REG32(PDCM_PD_SRAM1_SENSE, 0x210)
+REG32(PDCM_PD_SRAM2_SENSE, 0x214)
+REG32(PDCM_PD_SRAM3_SENSE, 0x218)
 REG32(PID4, 0xfd0)
 REG32(PID5, 0xfd4)
 REG32(PID6, 0xfd8)
@@ -XXX,XX +XXX,XX @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
     case A_SECDBGSTAT:
         r = s->secure_debug;
         break;
+    case A_SCSECCTRL:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        r = s->scsecctrl;
+        break;
+    case A_FCLK_DIV:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        r = s->fclk_div;
+        break;
+    case A_SYSCLK_DIV:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        r = s->sysclk_div;
+        break;
+    case A_CLOCK_FORCE:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        r = s->clock_force;
+        break;
     case A_RESET_SYNDROME:
         r = s->reset_syndrome;
         break;
@@ -XXX,XX +XXX,XX @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
     case A_INITSVTOR0:
         r = s->initsvtor0;
         break;
+    case A_INITSVTOR1:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        r = s->initsvtor1;
+        break;
     case A_CPUWAIT:
         r = s->cpuwait;
         break;
-    case A_BUSWAIT:
-        /* In IoTKit BUSWAIT is reserved, R/O, zero */
-        r = 0;
+    case A_NMI_ENABLE:
+        /* In IoTKit this is named BUSWAIT but is marked reserved, R/O, zero */
+        if (!s->is_sse200) {
+            r = 0;
+            break;
+        }
+        r = s->nmi_enable;
         break;
     case A_WICCTRL:
         r = s->wicctrl;
         break;
+    case A_EWCTRL:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        r = s->ewctrl;
+        break;
+    case A_PDCM_PD_SYS_SENSE:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        r = s->pdcm_pd_sys_sense;
+        break;
+    case A_PDCM_PD_SRAM0_SENSE:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        r = s->pdcm_pd_sram0_sense;
+        break;
+    case A_PDCM_PD_SRAM1_SENSE:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        r = s->pdcm_pd_sram1_sense;
+        break;
+    case A_PDCM_PD_SRAM2_SENSE:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        r = s->pdcm_pd_sram2_sense;
+        break;
+    case A_PDCM_PD_SRAM3_SENSE:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        r = s->pdcm_pd_sram3_sense;
+        break;
     case A_PID4 ... A_CID3:
         r = sysctl_id[(offset - A_PID4) / 4];
         break;
@@ -XXX,XX +XXX,XX @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
         r = 0;
         break;
     default:
+    bad_offset:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "IoTKit SysCtl read: bad offset %x\n", (int)offset);
         r = 0;
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
         }
         break;
-    case A_BUSWAIT:        /* In IoTKit BUSWAIT is reserved, R/O, zero */
+    case A_SCSECCTRL:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SCSECCTRL unimplemented\n");
+        s->scsecctrl = value;
+        break;
+    case A_FCLK_DIV:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl FCLK_DIV unimplemented\n");
+        s->fclk_div = value;
+        break;
+    case A_SYSCLK_DIV:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SYSCLK_DIV unimplemented\n");
+        s->sysclk_div = value;
+        break;
+    case A_CLOCK_FORCE:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CLOCK_FORCE unimplemented\n");
+        s->clock_force = value;
+        break;
+    case A_INITSVTOR1:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR1 unimplemented\n");
+        s->initsvtor1 = value;
+        break;
+    case A_EWCTRL:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl EWCTRL unimplemented\n");
+        s->ewctrl = value;
+        break;
+    case A_PDCM_PD_SYS_SENSE:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        qemu_log_mask(LOG_UNIMP,
+                      "IoTKit SysCtl PDCM_PD_SYS_SENSE unimplemented\n");
+        s->pdcm_pd_sys_sense = value;
+        break;
+    case A_PDCM_PD_SRAM0_SENSE:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        qemu_log_mask(LOG_UNIMP,
+                      "IoTKit SysCtl PDCM_PD_SRAM0_SENSE unimplemented\n");
+        s->pdcm_pd_sram0_sense = value;
+        break;
+    case A_PDCM_PD_SRAM1_SENSE:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        qemu_log_mask(LOG_UNIMP,
+                      "IoTKit SysCtl PDCM_PD_SRAM1_SENSE unimplemented\n");
+        s->pdcm_pd_sram1_sense = value;
+        break;
+    case A_PDCM_PD_SRAM2_SENSE:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        qemu_log_mask(LOG_UNIMP,
+                      "IoTKit SysCtl PDCM_PD_SRAM2_SENSE unimplemented\n");
+        s->pdcm_pd_sram2_sense = value;
+        break;
+    case A_PDCM_PD_SRAM3_SENSE:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        qemu_log_mask(LOG_UNIMP,
+                      "IoTKit SysCtl PDCM_PD_SRAM3_SENSE unimplemented\n");
+        s->pdcm_pd_sram3_sense = value;
+        break;
+    case A_NMI_ENABLE:
+        /* In IoTKit this is BUSWAIT: reserved, R/O, zero */
+        if (!s->is_sse200) {
+            goto ro_offset;
+        }
+        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE unimplemented\n");
+        s->nmi_enable = value;
+        break;
     case A_SECDBGSTAT:
     case A_PID4 ... A_CID3:
+    ro_offset:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "IoTKit SysCtl write: write of RO offset %x\n",
                       (int)offset);
         break;
     default:
+    bad_offset:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "IoTKit SysCtl write: bad offset %x\n", (int)offset);
         break;
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_reset(DeviceState *dev)
     s->reset_mask = 0;
     s->gretreg = 0;
     s->initsvtor0 = 0x10000000;
+    s->initsvtor1 = 0x10000000;
     s->cpuwait = 0;
     s->wicctrl = 0;
+    s->scsecctrl = 0;
+    s->fclk_div = 0;
+    s->sysclk_div = 0;
+    s->clock_force = 0;
+    s->nmi_enable = 0;
+    s->ewctrl = 0;
+    s->pdcm_pd_sys_sense = 0x7f;
+    s->pdcm_pd_sram0_sense = 0;
+    s->pdcm_pd_sram1_sense = 0;
+    s->pdcm_pd_sram2_sense = 0;
+    s->pdcm_pd_sram3_sense = 0;
 }
 
 static void iotkit_sysctl_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_init(Object *obj)
     sysbus_init_mmio(sbd, &s->iomem);
 }
 
+static void iotkit_sysctl_realize(DeviceState *dev, Error **errp)
+{
+    IoTKitSysCtl *s = IOTKIT_SYSCTL(dev);
+
+    /* The top 4 bits of the SYS_VERSION register tell us if we're an SSE-200 */
+    if (extract32(s->sys_version, 28, 4) == 2) {
+        s->is_sse200 = true;
+    }
+}
+
+static bool sse200_needed(void *opaque)
+{
+    IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque);
+
+    return s->is_sse200;
+}
+
+static const VMStateDescription iotkit_sysctl_sse200_vmstate = {
+    .name = "iotkit-sysctl/sse-200",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = sse200_needed,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(scsecctrl, IoTKitSysCtl),
+        VMSTATE_UINT32(fclk_div, IoTKitSysCtl),
+        VMSTATE_UINT32(sysclk_div, IoTKitSysCtl),
+        VMSTATE_UINT32(clock_force, IoTKitSysCtl),
+        VMSTATE_UINT32(initsvtor1, IoTKitSysCtl),
+        VMSTATE_UINT32(nmi_enable, IoTKitSysCtl),
+        VMSTATE_UINT32(pdcm_pd_sys_sense, IoTKitSysCtl),
+        VMSTATE_UINT32(pdcm_pd_sram0_sense, IoTKitSysCtl),
+        VMSTATE_UINT32(pdcm_pd_sram1_sense, IoTKitSysCtl),
+        VMSTATE_UINT32(pdcm_pd_sram2_sense, IoTKitSysCtl),
+        VMSTATE_UINT32(pdcm_pd_sram3_sense, IoTKitSysCtl),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static const VMStateDescription iotkit_sysctl_vmstate = {
     .name = "iotkit-sysctl",
     .version_id = 1,
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription iotkit_sysctl_vmstate = {
         VMSTATE_UINT32(cpuwait, IoTKitSysCtl),
         VMSTATE_UINT32(wicctrl, IoTKitSysCtl),
         VMSTATE_END_OF_LIST()
+    },
+    .subsections = (const VMStateDescription*[]) {
+        &iotkit_sysctl_sse200_vmstate,
+        NULL
     }
 };
 
+static Property iotkit_sysctl_props[] = {
+    DEFINE_PROP_UINT32("SYS_VERSION", IoTKitSysCtl, sys_version, 0),
+    DEFINE_PROP_END_OF_LIST()
+};
+
 static void iotkit_sysctl_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
 
     dc->vmsd = &iotkit_sysctl_vmstate;
     dc->reset = iotkit_sysctl_reset;
+    dc->props = iotkit_sysctl_props;
+    dc->realize = iotkit_sysctl_realize;
 }
 
 static const TypeInfo iotkit_sysctl_info = {
-- 
2.20.1

The CPUWAIT register acts as a sort of power-control: if a bit
in it is 1 then the CPU will have been forced into waiting
when the system was reset (which in QEMU we model as the
CPU starting powered off). Writing a 0 to the register will
allow the CPU to boot (for QEMU, we model this as powering
it on). Note that writing 0 to the register does not power
off a CPU.

For this to work correctly we need to also honour the
INITSVTOR* registers, which let the guest control where the
CPU will load its SP and PC from when it comes out of reset.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190219125808.25174-8-peter.maydell@linaro.org
---
 hw/misc/iotkit-sysctl.c | 41 +++++++++++++++++++++++++++++++++++++----
 1 file changed, 37 insertions(+), 4 deletions(-)

diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/iotkit-sysctl.c
+++ b/hw/misc/iotkit-sysctl.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "hw/registerfields.h"
 #include "hw/misc/iotkit-sysctl.h"
+#include "target/arm/arm-powerctl.h"
+#include "target/arm/cpu.h"
 
 REG32(SECDBGSTAT, 0x0)
 REG32(SECDBGSET, 0x4)
@@ -XXX,XX +XXX,XX @@ static const int sysctl_id[] = {
     0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
 };
 
+/*
+ * Set the initial secure vector table offset address for the core.
+ * This will take effect when the CPU next resets.
+ */
+static void set_init_vtor(uint64_t cpuid, uint32_t vtor)
+{
+    Object *cpuobj = OBJECT(arm_get_cpu_by_id(cpuid));
+
+    if (cpuobj) {
+        if (object_property_find(cpuobj, "init-svtor", NULL)) {
+            object_property_set_uint(cpuobj, vtor, "init-svtor", &error_abort);
+        }
+    }
+}
+
 static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
                                     unsigned size)
 {
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
         s->gretreg = value;
         break;
     case A_INITSVTOR0:
-        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR0 unimplemented\n");
         s->initsvtor0 = value;
+        set_init_vtor(0, s->initsvtor0);
         break;
     case A_CPUWAIT:
-        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CPUWAIT unimplemented\n");
+        if ((s->cpuwait & 1) && !(value & 1)) {
+            /* Powering up CPU 0 */
+            arm_set_cpu_on_and_reset(0);
+        }
+        if ((s->cpuwait & 2) && !(value & 2)) {
+            /* Powering up CPU 1 */
+            arm_set_cpu_on_and_reset(1);
+        }
         s->cpuwait = value;
         break;
     case A_WICCTRL:
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
         if (!s->is_sse200) {
             goto bad_offset;
         }
-        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR1 unimplemented\n");
         s->initsvtor1 = value;
+        set_init_vtor(1, s->initsvtor1);
         break;
     case A_EWCTRL:
         if (!s->is_sse200) {
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_reset(DeviceState *dev)
     s->gretreg = 0;
     s->initsvtor0 = 0x10000000;
     s->initsvtor1 = 0x10000000;
-    s->cpuwait = 0;
+    if (s->is_sse200) {
+        /*
+         * CPU 0 starts on, CPU 1 starts off. In real hardware this is
+         * configurable by the SoC integrator as a verilog parameter.
+         */
+        s->cpuwait = 2;
+    } else {
+        /* CPU 0 starts on */
+        s->cpuwait = 0;
+    }
     s->wicctrl = 0;
     s->scsecctrl = 0;
     s->fclk_div = 0;
-- 
2.20.1

At the moment the handling of init-svtor and cpuwait initial
values is split between armsse.c and iotkit-sysctl.c:
the code in armsse.c sets the initial state of the CPU
object by setting the init-svtor and start-powered-off
properties, but the iotkit-sysctl.c code has its own
code setting the reset values of its registers (which are
then used when updating the CPU when the guest makes
runtime changes).

Clean this up by making the armsse.c code set properties on the
iotkit-sysctl object to define the initial values of the
registers, so they always match the initial CPU state,
and update the comments in armsse.c accordingly.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190219125808.25174-9-peter.maydell@linaro.org
---
 include/hw/misc/iotkit-sysctl.h |  3 ++
 hw/arm/armsse.c                 | 49 +++++++++++++++++++++------------
 hw/misc/iotkit-sysctl.c         | 20 ++++++--------
 3 files changed, 42 insertions(+), 30 deletions(-)

diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/misc/iotkit-sysctl.h
+++ b/include/hw/misc/iotkit-sysctl.h
@@ -XXX,XX +XXX,XX @@ typedef struct IoTKitSysCtl {
 
     /* Properties */
     uint32_t sys_version;
+    uint32_t cpuwait_rst;
+    uint32_t initsvtor0_rst;
+    uint32_t initsvtor1_rst;
 
     bool is_sse200;
 } IoTKitSysCtl;
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -XXX,XX +XXX,XX @@
 
 #include "qemu/osdep.h"
 #include "qemu/log.h"
+#include "qemu/bitops.h"
 #include "qapi/error.h"
 #include "trace.h"
 #include "hw/sysbus.h"
@@ -XXX,XX +XXX,XX @@ struct ARMSSEInfo {
     int sram_banks;
     int num_cpus;
     uint32_t sys_version;
+    uint32_t cpuwait_rst;
     SysConfigFormat sys_config_format;
     bool has_mhus;
     bool has_ppus;
@@ -XXX,XX +XXX,XX @@ static const ARMSSEInfo armsse_variants[] = {
         .sram_banks = 1,
         .num_cpus = 1,
         .sys_version = 0x41743,
+        .cpuwait_rst = 0,
         .sys_config_format = IoTKitFormat,
         .has_mhus = false,
         .has_ppus = false,
@@ -XXX,XX +XXX,XX @@ static const ARMSSEInfo armsse_variants[] = {
         .sram_banks = 4,
         .num_cpus = 2,
         .sys_version = 0x22041743,
+        .cpuwait_rst = 2,
         .sys_config_format = SSE200Format,
         .has_mhus = true,
         .has_ppus = true,
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
 
         qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + 32);
         /*
-         * In real hardware the initial Secure VTOR is set from the INITSVTOR0
-         * register in the IoT Kit System Control Register block, and the
-         * initial value of that is in turn specifiable by the FPGA that
-         * instantiates the IoT Kit. In QEMU we don't implement this wrinkle,
-         * and simply set the CPU's init-svtor to the IoT Kit default value.
-         * In SSE-200 the situation is similar, except that the default value
-         * is a reset-time signal input. Typically a board using the SSE-200
-         * will have a system control processor whose boot firmware initializes
-         * the INITSVTOR* registers before powering up the CPUs in any case,
-         * so the hardware's default value doesn't matter. QEMU doesn't emulate
+         * In real hardware the initial Secure VTOR is set from the INITSVTOR*
+         * registers in the IoT Kit System Control Register block. In QEMU
+         * we set the initial value here, and also the reset value of the
+         * sysctl register, from this object's QOM init-svtor property.
+         * If the guest changes the INITSVTOR* registers at runtime then the
+         * code in iotkit-sysctl.c will update the CPU init-svtor property
+         * (which will then take effect on the next CPU warm-reset).
+         *
+         * Note that typically a board using the SSE-200 will have a system
+         * control processor whose boot firmware initializes the INITSVTOR*
+         * registers before powering up the CPUs. QEMU doesn't emulate
          * the control processor, so instead we behave in the way that the
-         * firmware does. The initial value is configurable by the board code
-         * to match whatever its firmware does.
+         * firmware does: the initial value should be set by the board code
+         * (using the init-svtor property on the ARMSSE object) to match
+         * whatever its firmware does.
          */
         qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor);
         /*
-         * Start all CPUs except CPU0 powered down. In real hardware it is
-         * a configurable property of the SSE-200 which CPUs start powered up
-         * (via the CPUWAIT0_RST and CPUWAIT1_RST parameters), but since all
-         * the boards we care about start CPU0 and leave CPU1 powered off,
-         * we hard-code that for now. We can add QOM properties for this
+         * CPUs start powered down if the corresponding bit in the CPUWAIT
+         * register is 1. In real hardware the CPUWAIT register reset value is
+         * a configurable property of the SSE-200 (via the CPUWAIT0_RST and
+         * CPUWAIT1_RST parameters), but since all the boards we care about
+         * start CPU0 and leave CPU1 powered off, we hard-code that in
+         * info->cpuwait_rst for now. We can add QOM properties for this
          * later if necessary.
          */
-        if (i > 0) {
+        if (extract32(info->cpuwait_rst, i, 1)) {
             object_property_set_bool(cpuobj, true, "start-powered-off", &err);
             if (err) {
                 error_propagate(errp, err);
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
     /* System control registers */
     object_property_set_int(OBJECT(&s->sysctl), info->sys_version,
                             "SYS_VERSION", &err);
+    object_property_set_int(OBJECT(&s->sysctl), info->cpuwait_rst,
+                            "CPUWAIT_RST", &err);
+    object_property_set_int(OBJECT(&s->sysctl), s->init_svtor,
+                            "INITSVTOR0_RST", &err);
+    object_property_set_int(OBJECT(&s->sysctl), s->init_svtor,
+                            "INITSVTOR1_RST", &err);
     object_property_set_bool(OBJECT(&s->sysctl), true, "realized", &err);
     if (err) {
         error_propagate(errp, err);
diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/iotkit-sysctl.c
+++ b/hw/misc/iotkit-sysctl.c
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_reset(DeviceState *dev)
     s->reset_syndrome = 1;
     s->reset_mask = 0;
     s->gretreg = 0;
-    s->initsvtor0 = 0x10000000;
-    s->initsvtor1 = 0x10000000;
-    if (s->is_sse200) {
-        /*
-         * CPU 0 starts on, CPU 1 starts off. In real hardware this is
-         * configurable by the SoC integrator as a verilog parameter.
-         */
-        s->cpuwait = 2;
-    } else {
-        /* CPU 0 starts on */
-        s->cpuwait = 0;
-    }
+    s->initsvtor0 = s->initsvtor0_rst;
+    s->initsvtor1 = s->initsvtor1_rst;
+    s->cpuwait = s->cpuwait_rst;
     s->wicctrl = 0;
     s->scsecctrl = 0;
     s->fclk_div = 0;
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription iotkit_sysctl_vmstate = {
 
 static Property iotkit_sysctl_props[] = {
     DEFINE_PROP_UINT32("SYS_VERSION", IoTKitSysCtl, sys_version, 0),
+    DEFINE_PROP_UINT32("CPUWAIT_RST", IoTKitSysCtl, cpuwait_rst, 0),
+    DEFINE_PROP_UINT32("INITSVTOR0_RST", IoTKitSysCtl, initsvtor0_rst,
+                       0x10000000),
+    DEFINE_PROP_UINT32("INITSVTOR1_RST", IoTKitSysCtl, initsvtor1_rst,
+                       0x10000000),
     DEFINE_PROP_END_OF_LIST()
 };
 
-- 
2.20.1

Instead of gating the A32/T32 FP16 conversion instructions on
the ARM_FEATURE_VFP_FP16 flag, switch to our new approach of
looking at ID register bits. In this case MVFR1 fields FPHP
and SIMDHP indicate the presence of these insns.

This change doesn't alter behaviour for any of our CPUs.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190222170936.13268-2-peter.maydell@linaro.org
---
 target/arm/cpu.h       | 37 ++++++++++++++++++++++++++++++++++++-
 target/arm/cpu.c       |  2 --
 target/arm/kvm32.c     |  3 ---
 target/arm/translate.c | 26 ++++++++++++++++++--------
 4 files changed, 54 insertions(+), 14 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(ID_DFR0, MPROFDBG, 20, 4)
 FIELD(ID_DFR0, PERFMON, 24, 4)
 FIELD(ID_DFR0, TRACEFILT, 28, 4)
 
+FIELD(MVFR0, SIMDREG, 0, 4)
+FIELD(MVFR0, FPSP, 4, 4)
+FIELD(MVFR0, FPDP, 8, 4)
+FIELD(MVFR0, FPTRAP, 12, 4)
+FIELD(MVFR0, FPDIVIDE, 16, 4)
+FIELD(MVFR0, FPSQRT, 20, 4)
+FIELD(MVFR0, FPSHVEC, 24, 4)
+FIELD(MVFR0, FPROUND, 28, 4)
+
+FIELD(MVFR1, FPFTZ, 0, 4)
+FIELD(MVFR1, FPDNAN, 4, 4)
+FIELD(MVFR1, SIMDLS, 8, 4)
+FIELD(MVFR1, SIMDINT, 12, 4)
+FIELD(MVFR1, SIMDSP, 16, 4)
+FIELD(MVFR1, SIMDHP, 20, 4)
+FIELD(MVFR1, FPHP, 24, 4)
+FIELD(MVFR1, SIMDFMAC, 28, 4)
+
+FIELD(MVFR2, SIMDMISC, 0, 4)
+FIELD(MVFR2, FPMISC, 4, 4)
+
 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
 
 /* If adding a feature bit which corresponds to a Linux ELF
@@ -XXX,XX +XXX,XX @@ enum arm_features {
     ARM_FEATURE_THUMB2,
     ARM_FEATURE_PMSA,   /* no MMU; may have Memory Protection Unit */
     ARM_FEATURE_VFP3,
-    ARM_FEATURE_VFP_FP16,
     ARM_FEATURE_NEON,
     ARM_FEATURE_M, /* Microcontroller profile.  */
     ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
 }
 
+/*
+ * We always set the FP and SIMD FP16 fields to indicate identical
+ * levels of support (assuming SIMD is implemented at all), so
+ * we only need one set of accessors.
+ */
+static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 0;
+}
+
+static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1;
+}
+
 /*
  * 64-bit feature tests via id registers.
  */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
     }
     if (arm_feature(env, ARM_FEATURE_VFP4)) {
         set_feature(env, ARM_FEATURE_VFP3);
-        set_feature(env, ARM_FEATURE_VFP_FP16);
     }
     if (arm_feature(env, ARM_FEATURE_VFP3)) {
         set_feature(env, ARM_FEATURE_VFP);
@@ -XXX,XX +XXX,XX @@ static void cortex_a9_initfn(Object *obj)
     cpu->dtb_compatible = "arm,cortex-a9";
     set_feature(&cpu->env, ARM_FEATURE_V7);
     set_feature(&cpu->env, ARM_FEATURE_VFP3);
-    set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
     set_feature(&cpu->env, ARM_FEATURE_EL3);
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
     if (extract32(id_pfr0, 12, 4) == 1) {
         set_feature(&features, ARM_FEATURE_THUMB2EE);
     }
-    if (extract32(ahcf->isar.mvfr1, 20, 4) == 1) {
-        set_feature(&features, ARM_FEATURE_VFP_FP16);
-    }
     if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
         set_feature(&features, ARM_FEATURE_NEON);
     }
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
                      * UNPREDICTABLE if bit 8 is set prior to ARMv8
                      * (we choose to UNDEF)
                      */
-                    if ((dp && !arm_dc_feature(s, ARM_FEATURE_V8)) ||
-                        !arm_dc_feature(s, ARM_FEATURE_VFP_FP16)) {
-                        return 1;
+                    if (dp) {
+                        if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
+                            return 1;
+                        }
+                    } else {
+                        if (!dc_isar_feature(aa32_fp16_spconv, s)) {
+                            return 1;
+                        }
                     }
                     rm_is_dp = false;
                     break;
                 case 0x06: /* vcvtb.f16.f32, vcvtb.f16.f64 */
                 case 0x07: /* vcvtt.f16.f32, vcvtt.f16.f64 */
-                    if ((dp && !arm_dc_feature(s, ARM_FEATURE_V8)) ||
-                        !arm_dc_feature(s, ARM_FEATURE_VFP_FP16)) {
-                        return 1;
+                    if (dp) {
+                        if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
+                            return 1;
+                        }
+                    } else {
+                        if (!dc_isar_feature(aa32_fp16_spconv, s)) {
+                            return 1;
+                        }
                     }
                     rd_is_dp = false;
                     break;
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                     TCGv_ptr fpst;
                     TCGv_i32 ahp;
 
-                    if (!arm_dc_feature(s, ARM_FEATURE_VFP_FP16) ||
+                    if (!dc_isar_feature(aa32_fp16_spconv, s) ||
                         q || (rm & 1)) {
                         return 1;
                     }
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                 {
                     TCGv_ptr fpst;
                     TCGv_i32 ahp;
-                    if (!arm_dc_feature(s, ARM_FEATURE_VFP_FP16) ||
+                    if (!dc_isar_feature(aa32_fp16_spconv, s) ||
                         q || (rd & 1)) {
                         return 1;
                     }
-- 
2.20.1

There is a set of VFP instructions which we implement in
disas_vfp_v8_insn() and gate on the ARM_FEATURE_V8 bit.
These were all first introduced in v8 for A-profile, but in
M-profile they appeared in v7M. Gate them on the MVFR2
FPMisc field instead, and rename the function appropriately.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190222170936.13268-3-peter.maydell@linaro.org
---
 target/arm/cpu.h       | 20 ++++++++++++++++++++
 target/arm/translate.c | 25 +++++++++++++------------
 2 files changed, 33 insertions(+), 12 deletions(-)

This reverts commit 823e1b3818f9b10b824ddcd756983b6e2fa68730,
which introduces a regression running EDK2 guest firmware
under KVM:

error: kvm run failed Function not implemented
 PC=000000013f5a6208 X00=00000000404003c4 X01=000000000000003a
X02=0000000000000000 X03=00000000404003c4 X04=0000000000000000
X05=0000000096000046 X06=000000013d2ef270 X07=000000013e3d1710
X08=09010755ffaf8ba8 X09=ffaf8b9cfeeb5468 X10=feeb546409010756
X11=09010757ffaf8b90 X12=feeb50680903068b X13=090306a1ffaf8bc0
X14=0000000000000000 X15=0000000000000000 X16=000000013f872da0
X17=00000000ffffa6ab X18=0000000000000000 X19=000000013f5a92d0
X20=000000013f5a7a78 X21=000000000000003a X22=000000013f5a7ab2
X23=000000013f5a92e8 X24=000000013f631090 X25=0000000000000010
X26=0000000000000100 X27=000000013f89501b X28=000000013e3d14e0
X29=000000013e3d12a0 X30=000000013f5a2518  SP=000000013b7be0b0
PSTATE=404003c4 -Z-- EL1t

with
[ 3507.926571] kvm [35042]: load/store instruction decoding not implemented
in the host dmesg.

Revert the change for the moment until we can investigate the
cause of the regression.

Reported-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h     |  9 +--------
 target/arm/helper.c  | 27 ++-------------------------
 target/arm/kvm32.c   | 20 ++++++++++++++++++--
 target/arm/kvm64.c   |  2 --
 target/arm/machine.c |  2 +-
 5 files changed, 22 insertions(+), 38 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ bool write_list_to_cpustate(ARMCPU *cpu);
 /**
  * write_cpustate_to_list:
  * @cpu: ARMCPU
- * @kvm_sync: true if this is for syncing back to KVM
  *
  * For each register listed in the ARMCPU cpreg_indexes list, write
  * its value from the ARMCPUState structure into the cpreg_values list.
  * This is used to copy info from TCG's working data structures into
  * KVM or for outbound migration.
  *
- * @kvm_sync is true if we are doing this in order to sync the
- * register state back to KVM. In this case we will only update
- * values in the list if the previous list->cpustate sync actually
- * successfully wrote the CPU state. Otherwise we will keep the value
- * that is in the list.
- *
  * Returns: true if all register values were read correctly,
  * false if some register was unknown or could not be read.
  * Note that we do not stop early on failure -- we will attempt
  * reading all registers in the list.
  */
-bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
+bool write_cpustate_to_list(ARMCPU *cpu);
 
 #define ARM_CPUID_TI915T      0x54029152
 #define ARM_CPUID_TI925T      0x54029252
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
     return true;
 }
 
-bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync)
+bool write_cpustate_to_list(ARMCPU *cpu)
 {
     /* Write the coprocessor state from cpu->env to the (index,value) list. */
     int i;
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync)
     for (i = 0; i < cpu->cpreg_array_len; i++) {
         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
         const ARMCPRegInfo *ri;
-        uint64_t newval;
 
         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
         if (!ri) {
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync)
         if (ri->type & ARM_CP_NO_RAW) {
             continue;
         }
-
-        newval = read_raw_cp_reg(&cpu->env, ri);
-        if (kvm_sync) {
-            /*
-             * Only sync if the previous list->cpustate sync succeeded.
-             * Rather than tracking the success/failure state for every
-             * item in the list, we just recheck "does the raw write we must
-             * have made in write_list_to_cpustate() read back OK" here.
-             */
-            uint64_t oldval = cpu->cpreg_values[i];
-
-            if (oldval == newval) {
-                continue;
-            }
-
-            write_raw_cp_reg(&cpu->env, ri, oldval);
-            if (read_raw_cp_reg(&cpu->env, ri) != oldval) {
-                continue;
-            }
-
-            write_raw_cp_reg(&cpu->env, ri, newval);
-        }
-        cpu->cpreg_values[i] = newval;
+        cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
     }
     return ok;
 }
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
         return ret;
     }
 
-    write_cpustate_to_list(cpu, true);
-
+    /* Note that we do not call write_cpustate_to_list()
+     * here, so we are only writing the tuple list back to
+     * KVM. This is safe because nothing can change the
+     * CPUARMState cp15 fields (in particular gdb accesses cannot)
+     * and so there are no changes to sync. In fact syncing would
+     * be wrong at this point: for a constant register where TCG and
+     * KVM disagree about its value, the preceding write_list_to_cpustate()
+     * would not have had any effect on the CPUARMState value (since the
+     * register is read-only), and a write_cpustate_to_list() here would
+     * then try to write the TCG value back into KVM -- this would either
+     * fail or incorrectly change the value the guest sees.
+     *
+     * If we ever want to allow the user to modify cp15 registers via
+     * the gdb stub, we would need to be more clever here (for instance
+     * tracking the set of registers kvm_arch_get_registers() successfully
+     * managed to update the CPUARMState with, and only allowing those
+     * to be written back up into the kernel).
+     */
     if (!write_list_to_kvmstate(cpu, level)) {
         return EINVAL;
     }
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
         return ret;
     }
 
-    write_cpustate_to_list(cpu, true);
-
     if (!write_list_to_kvmstate(cpu, level)) {
         return EINVAL;
     }
diff --git a/target/arm/machine.c b/target/arm/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque)
             abort();
         }
     } else {
-        if (!write_cpustate_to_list(cpu, false)) {
+        if (!write_cpustate_to_list(cpu)) {
             /* This should never fail. */
             abort();
         }
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

Note that float16_to_float32 rightly squashes SNaN to QNaN.
But of course pickNaNMulAdd, for ARM, selects SNaNs first.
So we have to preserve SNaN long enough for the correct NaN
to be selected.  Thus float16_to_float32_by_bits.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190219222952.22183-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h     |   9 +++
 target/arm/vec_helper.c | 148 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 157 insertions(+)

diff --git a/target/arm/helper.h b/target/arm/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_sqsub_s, TCG_CALL_NO_RWG,
 DEF_HELPER_FLAGS_5(gvec_sqsub_d, TCG_CALL_NO_RWG,
                    void, ptr, ptr, ptr, ptr, i32)
 
+DEF_HELPER_FLAGS_5(gvec_fmlal_a32, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_fmlal_a64, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a32, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a64, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, i32)
+
 #ifdef TARGET_AARCH64
 #include "helper-a64.h"
 #include "helper-sve.h"
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/vec_helper.c
+++ b/target/arm/vec_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sqsub_d)(void *vd, void *vq, void *vn,
     }
     clear_tail(d, oprsz, simd_maxsz(desc));
 }
+
+/*
+ * Convert float16 to float32, raising no exceptions and
+ * preserving exceptional values, including SNaN.
+ * This is effectively an unpack+repack operation.
+ */
+static float32 float16_to_float32_by_bits(uint32_t f16, bool fz16)
+{
+    const int f16_bias = 15;
+    const int f32_bias = 127;
+    uint32_t sign = extract32(f16, 15, 1);
+    uint32_t exp = extract32(f16, 10, 5);
+    uint32_t frac = extract32(f16, 0, 10);
+
+    if (exp == 0x1f) {
+        /* Inf or NaN */
+        exp = 0xff;
+    } else if (exp == 0) {
+        /* Zero or denormal.  */
+        if (frac != 0) {
+            if (fz16) {
+                frac = 0;
+            } else {
+                /*
+                 * Denormal; these are all normal float32.
+                 * Shift the fraction so that the msb is at bit 11,
+                 * then remove bit 11 as the implicit bit of the
+                 * normalized float32.  Note that we still go through
+                 * the shift for normal numbers below, to put the
+                 * float32 fraction at the right place.
+                 */
+                int shift = clz32(frac) - 21;
+                frac = (frac << shift) & 0x3ff;
+                exp = f32_bias - f16_bias - shift + 1;
+            }
+        }
+    } else {
+        /* Normal number; adjust the bias.  */
+        exp += f32_bias - f16_bias;
+    }
+    sign <<= 31;
+    exp <<= 23;
+    frac <<= 23 - 10;
+
+    return sign | exp | frac;
+}
+
+static uint64_t load4_f16(uint64_t *ptr, int is_q, int is_2)
+{
+    /*
+     * Branchless load of u32[0], u64[0], u32[1], or u64[1].
+     * Load the 2nd qword iff is_q & is_2.
+     * Shift to the 2nd dword iff !is_q & is_2.
+     * For !is_q & !is_2, the upper bits of the result are garbage.
+     */
+    return ptr[is_q & is_2] >> ((is_2 & ~is_q) << 5);
+}
+
+/*
+ * Note that FMLAL requires oprsz == 8 or oprsz == 16,
+ * as there is not yet SVE versions that might use blocking.
+ */
+
+static void do_fmlal(float32 *d, void *vn, void *vm, float_status *fpst,
+                     uint32_t desc, bool fz16)
+{
+    intptr_t i, oprsz = simd_oprsz(desc);
+    int is_s = extract32(desc, SIMD_DATA_SHIFT, 1);
+    int is_2 = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
+    int is_q = oprsz == 16;
+    uint64_t n_4, m_4;
+
+    /* Pre-load all of the f16 data, avoiding overlap issues.  */
+    n_4 = load4_f16(vn, is_q, is_2);
+    m_4 = load4_f16(vm, is_q, is_2);
+
+    /* Negate all inputs for FMLSL at once.  */
+    if (is_s) {
+        n_4 ^= 0x8000800080008000ull;
+    }
+
+    for (i = 0; i < oprsz / 4; i++) {
+        float32 n_1 = float16_to_float32_by_bits(n_4 >> (i * 16), fz16);
+        float32 m_1 = float16_to_float32_by_bits(m_4 >> (i * 16), fz16);
+        d[H4(i)] = float32_muladd(n_1, m_1, d[H4(i)], 0, fpst);
+    }
+    clear_tail(d, oprsz, simd_maxsz(desc));
+}
+
+void HELPER(gvec_fmlal_a32)(void *vd, void *vn, void *vm,
+                            void *venv, uint32_t desc)
+{
+    CPUARMState *env = venv;
+    do_fmlal(vd, vn, vm, &env->vfp.standard_fp_status, desc,
+             get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
+}
+
+void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void *vm,
+                            void *venv, uint32_t desc)
+{
+    CPUARMState *env = venv;
+    do_fmlal(vd, vn, vm, &env->vfp.fp_status, desc,
+             get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
+}
+
+static void do_fmlal_idx(float32 *d, void *vn, void *vm, float_status *fpst,
+                         uint32_t desc, bool fz16)
+{
+    intptr_t i, oprsz = simd_oprsz(desc);
+    int is_s = extract32(desc, SIMD_DATA_SHIFT, 1);
+    int is_2 = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
+    int index = extract32(desc, SIMD_DATA_SHIFT + 2, 3);
+    int is_q = oprsz == 16;
+    uint64_t n_4;
+    float32 m_1;
+
+    /* Pre-load all of the f16 data, avoiding overlap issues.  */
+    n_4 = load4_f16(vn, is_q, is_2);
+
+    /* Negate all inputs for FMLSL at once.  */
+    if (is_s) {
+        n_4 ^= 0x8000800080008000ull;
+    }
+
+    m_1 = float16_to_float32_by_bits(((float16 *)vm)[H2(index)], fz16);
+
+    for (i = 0; i < oprsz / 4; i++) {
+        float32 n_1 = float16_to_float32_by_bits(n_4 >> (i * 16), fz16);
+        d[H4(i)] = float32_muladd(n_1, m_1, d[H4(i)], 0, fpst);
+    }
+    clear_tail(d, oprsz, simd_maxsz(desc));
+}
+
+void HELPER(gvec_fmlal_idx_a32)(void *vd, void *vn, void *vm,
+                                void *venv, uint32_t desc)
+{
+    CPUARMState *env = venv;
+    do_fmlal_idx(vd, vn, vm, &env->vfp.standard_fp_status, desc,
+                 get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
+}
+
+void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm,
+                                void *venv, uint32_t desc)
+{
+    CPUARMState *env = venv;
+    do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status, desc,
+                 get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
+}
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190219222952.22183-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h           |  5 ++++
 target/arm/translate-a64.c | 49 +++++++++++++++++++++++++++++++++++++-
 2 files changed, 53 insertions(+), 1 deletion(-)

From: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190219222952.22183-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h       |   5 ++
 target/arm/translate.c | 129 ++++++++++++++++++++++++++++++-----------
 2 files changed, 101 insertions(+), 33 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
     return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
 }
 
+static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)
+{
+    return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
+}
+
 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
 {
     /*
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
     gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL;
     int rd, rn, rm, opr_sz;
     int data = 0;
-    bool q;
-
-    q = extract32(insn, 6, 1);
-    VFP_DREG_D(rd, insn);
-    VFP_DREG_N(rn, insn);
-    VFP_DREG_M(rm, insn);
-    if ((rd | rn | rm) & q) {
-        return 1;
-    }
+    int off_rn, off_rm;
+    bool is_long = false, q = extract32(insn, 6, 1);
+    bool ptr_is_env = false;
 
     if ((insn & 0xfe200f10) == 0xfc200800) {
         /* VCMLA -- 1111 110R R.1S .... .... 1000 ...0 .... */
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
             return 1;
         }
         fn_gvec = u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b;
+    } else if ((insn & 0xff300f10) == 0xfc200810) {
+        /* VFM[AS]L -- 1111 1100 S.10 .... .... 1000 .Q.1 .... */
+        int is_s = extract32(insn, 23, 1);
+        if (!dc_isar_feature(aa32_fhm, s)) {
+            return 1;
+        }
+        is_long = true;
+        data = is_s; /* is_2 == 0 */
+        fn_gvec_ptr = gen_helper_gvec_fmlal_a32;
+        ptr_is_env = true;
     } else {
         return 1;
     }
 
+    VFP_DREG_D(rd, insn);
+    if (rd & q) {
+        return 1;
+    }
+    if (q || !is_long) {
+        VFP_DREG_N(rn, insn);
+        VFP_DREG_M(rm, insn);
+        if ((rn | rm) & q & !is_long) {
+            return 1;
+        }
+        off_rn = vfp_reg_offset(1, rn);
+        off_rm = vfp_reg_offset(1, rm);
+    } else {
+        rn = VFP_SREG_N(insn);
+        rm = VFP_SREG_M(insn);
+        off_rn = vfp_reg_offset(0, rn);
+        off_rm = vfp_reg_offset(0, rm);
+    }
+
     if (s->fp_excp_el) {
         gen_exception_insn(s, 4, EXCP_UDEF,
                            syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
 
     opr_sz = (1 + q) * 8;
     if (fn_gvec_ptr) {
-        TCGv_ptr fpst = get_fpstatus_ptr(1);
-        tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd),
-                           vfp_reg_offset(1, rn),
-                           vfp_reg_offset(1, rm), fpst,
+        TCGv_ptr ptr;
+        if (ptr_is_env) {
+            ptr = cpu_env;
+        } else {
+            ptr = get_fpstatus_ptr(1);
+        }
+        tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr,
                            opr_sz, opr_sz, data, fn_gvec_ptr);
-        tcg_temp_free_ptr(fpst);
+        if (!ptr_is_env) {
+            tcg_temp_free_ptr(ptr);
+        }
     } else {
-        tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd),
-                           vfp_reg_offset(1, rn),
-                           vfp_reg_offset(1, rm),
+        tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm,
                            opr_sz, opr_sz, data, fn_gvec);
     }
     return 0;
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
     gen_helper_gvec_3 *fn_gvec = NULL;
     gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL;
     int rd, rn, rm, opr_sz, data;
-    bool q;
-
-    q = extract32(insn, 6, 1);
-    VFP_DREG_D(rd, insn);
-    VFP_DREG_N(rn, insn);
-    if ((rd | rn) & q) {
-        return 1;
-    }
+    int off_rn, off_rm;
+    bool is_long = false, q = extract32(insn, 6, 1);
+    bool ptr_is_env = false;
 
     if ((insn & 0xff000f10) == 0xfe000800) {
         /* VCMLA (indexed) -- 1111 1110 S.RR .... .... 1000 ...0 .... */
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
     } else if ((insn & 0xffb00f00) == 0xfe200d00) {
         /* V[US]DOT -- 1111 1110 0.10 .... .... 1101 .Q.U .... */
         int u = extract32(insn, 4, 1);
+
         if (!dc_isar_feature(aa32_dp, s)) {
             return 1;
         }
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
         /* rm is just Vm, and index is M.  */
         data = extract32(insn, 5, 1); /* index */
         rm = extract32(insn, 0, 4);
+    } else if ((insn & 0xffa00f10) == 0xfe000810) {
+        /* VFM[AS]L -- 1111 1110 0.0S .... .... 1000 .Q.1 .... */
+        int is_s = extract32(insn, 20, 1);
+        int vm20 = extract32(insn, 0, 3);
+        int vm3 = extract32(insn, 3, 1);
+        int m = extract32(insn, 5, 1);
+        int index;
+
+        if (!dc_isar_feature(aa32_fhm, s)) {
+            return 1;
+        }
+        if (q) {
+            rm = vm20;
+            index = m * 2 + vm3;
+        } else {
+            rm = vm20 * 2 + m;
+            index = vm3;
+        }
+        is_long = true;
+        data = (index << 2) | is_s; /* is_2 == 0 */
+        fn_gvec_ptr = gen_helper_gvec_fmlal_idx_a32;
+        ptr_is_env = true;
     } else {
         return 1;
     }
 
+    VFP_DREG_D(rd, insn);
+    if (rd & q) {
+        return 1;
+    }
+    if (q || !is_long) {
+        VFP_DREG_N(rn, insn);
+        if (rn & q & !is_long) {
+            return 1;
+        }
+        off_rn = vfp_reg_offset(1, rn);
+        off_rm = vfp_reg_offset(1, rm);
+    } else {
+        rn = VFP_SREG_N(insn);
+        off_rn = vfp_reg_offset(0, rn);
+        off_rm = vfp_reg_offset(0, rm);
+    }
     if (s->fp_excp_el) {
         gen_exception_insn(s, 4, EXCP_UDEF,
                            syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
 
     opr_sz = (1 + q) * 8;
     if (fn_gvec_ptr) {
-        TCGv_ptr fpst = get_fpstatus_ptr(1);
-        tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd),
-                           vfp_reg_offset(1, rn),
-                           vfp_reg_offset(1, rm), fpst,
+        TCGv_ptr ptr;
+        if (ptr_is_env) {
+            ptr = cpu_env;
+        } else {
+            ptr = get_fpstatus_ptr(1);
+        }
+        tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr,
                            opr_sz, opr_sz, data, fn_gvec_ptr);
-        tcg_temp_free_ptr(fpst);
+        if (!ptr_is_env) {
+            tcg_temp_free_ptr(ptr);
+        }
     } else {
-        tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd),
-                           vfp_reg_offset(1, rn),
-                           vfp_reg_offset(1, rm),
+        tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm,
                            opr_sz, opr_sz, data, fn_gvec);
     }
     return 0;
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190219222952.22183-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c   | 1 +
 target/arm/cpu64.c | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
             t = cpu->isar.id_isar6;
             t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
             t = FIELD_DP32(t, ID_ISAR6, DP, 1);
+            t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
             cpu->isar.id_isar6 = t;
 
             t = cpu->id_mmfr4;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
         t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
         t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
         t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
+        t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
         cpu->isar.id_aa64isar0 = t;
 
         t = cpu->isar.id_aa64isar1;
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
         u = cpu->isar.id_isar6;
         u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
         u = FIELD_DP32(u, ID_ISAR6, DP, 1);
+        u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
         cpu->isar.id_isar6 = u;
 
         /*
-- 
2.20.1

A last small test of bug fixes before rc1.

thanks
-- PMM

The following changes since commit ed8ad9728a9c0eec34db9dff61dfa2f1dd625637:

Merge tag 'pull-tpm-2023-07-14-1' of https://github.com/stefanberger/qemu-tpm into staging (2023-07-15 14:54:04 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20230717

for you to fetch changes up to c2c1c4a35c7c2b1a4140b0942b9797c857e476a4:

hw/nvram: Avoid unnecessary Xilinx eFuse backstore write (2023-07-17 11:05:52 +0100)

----------------------------------------------------------------
target-arm queue:
 * hw/arm/sbsa-ref: set 'slots' property of xhci
 * linux-user: Remove pointless NULL check in clock_adjtime handling
 * ptw: Fix S1_ptw_translate() debug path
 * ptw: Account for FEAT_RME when applying {N}SW, SA bits
 * accel/tcg: Zero-pad PC in TCG CPU exec trace lines
 * hw/nvram: Avoid unnecessary Xilinx eFuse backstore write

----------------------------------------------------------------
Peter Maydell (5):
      linux-user: Remove pointless NULL check in clock_adjtime handling
      target/arm/ptw.c: Add comments to S1Translate struct fields
      target/arm: Fix S1_ptw_translate() debug path
      target/arm/ptw.c: Account for FEAT_RME when applying {N}SW, SA bits
      accel/tcg: Zero-pad PC in TCG CPU exec trace lines

Tong Ho (1):
      hw/nvram: Avoid unnecessary Xilinx eFuse backstore write

Yuquan Wang (1):
      hw/arm/sbsa-ref: set 'slots' property of xhci

From: Yuquan Wang <wangyuquan1236@phytium.com.cn>

This extends the slots of xhci to 64, since the default xhci_sysbus
just supports one slot.

Signed-off-by: Wang Yuquan <wangyuquan1236@phytium.com.cn>
Signed-off-by: Chen Baozi <chenbaozi@phytium.com.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Tested-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
Message-id: 20230710063750.473510-2-wangyuquan1236@phytium.com.cn
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/sbsa-ref.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -XXX,XX +XXX,XX @@ static void create_xhci(const SBSAMachineState *sms)
     hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base;
     int irq = sbsa_ref_irqmap[SBSA_XHCI];
     DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS);
+    qdev_prop_set_uint32(dev, "slots", XHCI_MAXSLOTS);
 
     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base);
-- 
2.34.1

In the code for TARGET_NR_clock_adjtime, we set the pointer phtx to
the address of the local variable htx.  This means it can never be
NULL, but later in the code we check it for NULL anyway.  Coverity
complains about this (CID 1507683) because the NULL check comes after
a call to clock_adjtime() that assumes it is non-NULL.

Since phtx is always &htx, and is used only in three places, it's not
really necessary.  Remove it, bringing the code structure in to line
with that for TARGET_NR_clock_adjtime64, which already uses a simple
'&htx' when it wants a pointer to 'htx'.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230623144410.1837261-1-peter.maydell@linaro.org
---
 linux-user/syscall.c | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index XXXXXXX..XXXXXXX 100644
--- a/linux-user/syscall.c
+++ b/linux-user/syscall.c
@@ -XXX,XX +XXX,XX @@ static abi_long do_syscall1(CPUArchState *cpu_env, int num, abi_long arg1,
 #if defined(TARGET_NR_clock_adjtime) && defined(CONFIG_CLOCK_ADJTIME)
     case TARGET_NR_clock_adjtime:
         {
-            struct timex htx, *phtx = &htx;
+            struct timex htx;
 
-            if (target_to_host_timex(phtx, arg2) != 0) {
+            if (target_to_host_timex(&htx, arg2) != 0) {
                 return -TARGET_EFAULT;
             }
-            ret = get_errno(clock_adjtime(arg1, phtx));
-            if (!is_error(ret) && phtx) {
-                if (host_to_target_timex(arg2, phtx) != 0) {
-                    return -TARGET_EFAULT;
-                }
+            ret = get_errno(clock_adjtime(arg1, &htx));
+            if (!is_error(ret) && host_to_target_timex(arg2, &htx)) {
+                return -TARGET_EFAULT;
             }
         }
         return ret;
-- 
2.34.1

Add comments to the in_* fields in the S1Translate struct
that explain what they're doing.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230710152130.3928330-2-peter.maydell@linaro.org
---
 target/arm/ptw.c | 40 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@
 #endif
 
 typedef struct S1Translate {
+    /*
+     * in_mmu_idx : specifies which TTBR, TCR, etc to use for the walk.
+     * Together with in_space, specifies the architectural translation regime.
+     */
     ARMMMUIdx in_mmu_idx;
+    /*
+     * in_ptw_idx: specifies which mmuidx to use for the actual
+     * page table descriptor load operations. This will be one of the
+     * ARMMMUIdx_Stage2* or one of the ARMMMUIdx_Phys_* indexes.
+     * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit,
+     * this field is updated accordingly.
+     */
     ARMMMUIdx in_ptw_idx;
+    /*
+     * in_space: the security space for this walk. This plus
+     * the in_mmu_idx specify the architectural translation regime.
+     * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit,
+     * this field is updated accordingly.
+     *
+     * Note that the security space for the in_ptw_idx may be different
+     * from that for the in_mmu_idx. We do not need to explicitly track
+     * the in_ptw_idx security space because:
+     *  - if the in_ptw_idx is an ARMMMUIdx_Phys_* then the mmuidx
+     *    itself specifies the security space
+     *  - if the in_ptw_idx is an ARMMMUIdx_Stage2* then the security
+     *    space used for ptw reads is the same as that of the security
+     *    space of the stage 1 translation for all cases except where
+     *    stage 1 is Secure; in that case the only possibilities for
+     *    the ptw read are Secure and NonSecure, and the in_ptw_idx
+     *    value being Stage2 vs Stage2_S distinguishes those.
+     */
     ARMSecuritySpace in_space;
+    /*
+     * in_secure: whether the translation regime is a Secure one.
+     * This is always equal to arm_space_is_secure(in_space).
+     * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit,
+     * this field is updated accordingly.
+     */
     bool in_secure;
+    /*
+     * in_debug: is this a QEMU debug access (gdbstub, etc)? Debug
+     * accesses will not update the guest page table access flags
+     * and will not change the state of the softmmu TLBs.
+     */
     bool in_debug;
     /*
      * If this is stage 2 of a stage 1+2 page table walk, then this must
-- 
2.34.1

In commit fe4a5472ccd6 we rearranged the logic in S1_ptw_translate()
so that the debug-access "call get_phys_addr_*" codepath is used both
when S1 is doing ptw reads from stage 2 and when it is doing ptw
reads from physical memory.  However, we didn't update the
calculation of s2ptw->in_space and s2ptw->in_secure to account for
the "ptw reads from physical memory" case.  This meant that debug
accesses when in Secure state broke.

Create a new function S2_security_space() which returns the
correct security space to use for the ptw load, and use it to
determine the correct .in_secure and .in_space fields for the
stage 2 lookup for the ptw load.

Reported-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Jean-Philippe Brucker <jean-philippe@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230710152130.3928330-3-peter.maydell@linaro.org
Fixes: fe4a5472ccd6 ("target/arm: Use get_phys_addr_with_struct in S1_ptw_translate")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/ptw.c | 37 ++++++++++++++++++++++++++++++++-----
 1 file changed, 32 insertions(+), 5 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs)
     }
 }
 
+static ARMSecuritySpace S2_security_space(ARMSecuritySpace s1_space,
+                                          ARMMMUIdx s2_mmu_idx)
+{
+    /*
+     * Return the security space to use for stage 2 when doing
+     * the S1 page table descriptor load.
+     */
+    if (regime_is_stage2(s2_mmu_idx)) {
+        /*
+         * The security space for ptw reads is almost always the same
+         * as that of the security space of the stage 1 translation.
+         * The only exception is when stage 1 is Secure; in that case
+         * the ptw read might be to the Secure or the NonSecure space
+         * (but never Realm or Root), and the s2_mmu_idx tells us which.
+         * Root translations are always single-stage.
+         */
+        if (s1_space == ARMSS_Secure) {
+            return arm_secure_to_space(s2_mmu_idx == ARMMMUIdx_Stage2_S);
+        } else {
+            assert(s2_mmu_idx != ARMMMUIdx_Stage2_S);
+            assert(s1_space != ARMSS_Root);
+            return s1_space;
+        }
+    } else {
+        /* ptw loads are from phys: the mmu idx itself says which space */
+        return arm_phys_to_space(s2_mmu_idx);
+    }
+}
+
 /* Translate a S1 pagetable walk through S2 if needed.  */
 static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
                              hwaddr addr, ARMMMUFaultInfo *fi)
 {
-    ARMSecuritySpace space = ptw->in_space;
     bool is_secure = ptw->in_secure;
     ARMMMUIdx mmu_idx = ptw->in_mmu_idx;
     ARMMMUIdx s2_mmu_idx = ptw->in_ptw_idx;
@@ -XXX,XX +XXX,XX @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw,
          * From gdbstub, do not use softmmu so that we don't modify the
          * state of the cpu at all, including softmmu tlb contents.
          */
+        ARMSecuritySpace s2_space = S2_security_space(ptw->in_space, s2_mmu_idx);
         S1Translate s2ptw = {
             .in_mmu_idx = s2_mmu_idx,
             .in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx),
-            .in_secure = s2_mmu_idx == ARMMMUIdx_Stage2_S,
-            .in_space = (s2_mmu_idx == ARMMMUIdx_Stage2_S ? ARMSS_Secure
-                         : space == ARMSS_Realm ? ARMSS_Realm
-                         : ARMSS_NonSecure),
+            .in_secure = arm_space_is_secure(s2_space),
+            .in_space = s2_space,
             .in_debug = true,
         };
         GetPhysAddrResult s2 = { };
-- 
2.34.1

In get_phys_addr_twostage() the code that applies the effects of
VSTCR.{SA,SW} and VTCR.{NSA,NSW} only updates result->f.attrs.secure.
Now we also have f.attrs.space for FEAT_RME, we need to keep the two
in sync.

These bits only have an effect for Secure space translations, not
for Root, so use the input in_space field to determine whether to
apply them rather than the input is_secure. This doesn't actually
make a difference because Root translations are never two-stage,
but it's a little clearer.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230710152130.3928330-4-peter.maydell@linaro.org
---
 target/arm/ptw.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
     hwaddr ipa;
     int s1_prot, s1_lgpgsz;
     bool is_secure = ptw->in_secure;
+    ARMSecuritySpace in_space = ptw->in_space;
     bool ret, ipa_secure;
     ARMCacheAttrs cacheattrs1;
     ARMSecuritySpace ipa_space;
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw,
      * Check if IPA translates to secure or non-secure PA space.
      * Note that VSTCR overrides VTCR and {N}SW overrides {N}SA.
      */
-    result->f.attrs.secure =
-        (is_secure
-         && !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))
-         && (ipa_secure
-             || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW))));
+    if (in_space == ARMSS_Secure) {
+        result->f.attrs.secure =
+            !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW))
+            && (ipa_secure
+                || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW)));
+        result->f.attrs.space = arm_secure_to_space(result->f.attrs.secure);
+    }
 
     return false;
 }
-- 
2.34.1

In commit f0a08b0913befbd we changed the type of the PC from
target_ulong to vaddr.  In doing so we inadvertently dropped the
zero-padding on the PC in trace lines (the second item inside the []
in these lines).  They used to look like this on AArch64, for
instance:

Trace 0: 0x7f2260000100 [00000000/0000000040000000/00000061/ff200000]

and now they look like this:
Trace 0: 0x7f4f50000100 [00000000/40000000/00000061/ff200000]

and if the PC happens to be somewhere low like 0x5000
then the field is shown as /5000/.

This is because TARGET_FMT_lx is a "%08x" or "%016x" specifier,
depending on TARGET_LONG_SIZE, whereas VADDR_PRIx is just PRIx64
with no width specifier.

Restore the zero-padding by adding an 016 width specifier to
this tracing and a couple of others that were similarly recently
changed to use VADDR_PRIx without a width specifier.

We can't unfortunately restore the "32-bit guests are padded to
8 hex digits and 64-bit guests to 16 hex digits" behaviour so
easily.

Fixes: f0a08b0913befbd ("accel/tcg/cpu-exec.c: Widen pc to vaddr")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-id: 20230711165434.4123674-1-peter.maydell@linaro.org
---
 accel/tcg/cpu-exec.c      | 4 ++--
 accel/tcg/translate-all.c | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/cpu-exec.c
+++ b/accel/tcg/cpu-exec.c
@@ -XXX,XX +XXX,XX @@ static void log_cpu_exec(vaddr pc, CPUState *cpu,
     if (qemu_log_in_addr_range(pc)) {
         qemu_log_mask(CPU_LOG_EXEC,
                       "Trace %d: %p [%08" PRIx64
-                      "/%" VADDR_PRIx "/%08x/%08x] %s\n",
+                      "/%016" VADDR_PRIx "/%08x/%08x] %s\n",
                       cpu->cpu_index, tb->tc.ptr, tb->cs_base, pc,
                       tb->flags, tb->cflags, lookup_symbol(pc));
 
@@ -XXX,XX +XXX,XX @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit)
         if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
             vaddr pc = log_pc(cpu, last_tb);
             if (qemu_log_in_addr_range(pc)) {
-                qemu_log("Stopped execution of TB chain before %p [%"
+                qemu_log("Stopped execution of TB chain before %p [%016"
                          VADDR_PRIx "] %s\n",
                          last_tb->tc.ptr, pc, lookup_symbol(pc));
             }
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index XXXXXXX..XXXXXXX 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -XXX,XX +XXX,XX @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
         vaddr pc = log_pc(cpu, tb);
         if (qemu_log_in_addr_range(pc)) {
-            qemu_log("cpu_io_recompile: rewound execution of TB to %"
+            qemu_log("cpu_io_recompile: rewound execution of TB to %016"
                      VADDR_PRIx "\n", pc);
         }
     }
-- 
2.34.1

From: Tong Ho <tong.ho@amd.com>

Add a check in the bit-set operation to write the backstore
only if the affected bit is 0 before.

With this in place, there will be no need for callers to
do the checking in order to avoid unnecessary writes.

Signed-off-by: Tong Ho <tong.ho@amd.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/nvram/xlnx-efuse.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/nvram/xlnx-efuse.c
+++ b/hw/nvram/xlnx-efuse.c
@@ -XXX,XX +XXX,XX @@ static bool efuse_ro_bits_find(XlnxEFuse *s, uint32_t k)
 
 bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit)
 {
+    uint32_t set, *row;
+
     if (efuse_ro_bits_find(s, bit)) {
         g_autofree char *path = object_get_canonical_path(OBJECT(s));
 
@@ -XXX,XX +XXX,XX @@ bool xlnx_efuse_set_bit(XlnxEFuse *s, unsigned int bit)
         return false;
     }
 
-    s->fuse32[bit / 32] |= 1 << (bit % 32);
-    efuse_bdrv_sync(s, bit);
+    /* Avoid back-end write unless there is a real update */
+    row = &s->fuse32[bit / 32];
+    set = 1 << (bit % 32);
+    if (!(set & *row)) {
+        *row |= set;
+        efuse_bdrv_sync(s, bit);
+    }
     return true;
 }
 
-- 
2.34.1