[Qemu-devel] [PULL 00/16] target-arm queue
[PULL 00/36] target-arm queue
1
The following changes since commit adf2e451f357e993f173ba9b4176dbf3e65fee7e:
1
First pullreq for 6.0: mostly my v8.1M work, plus some other
2
bits and pieces. (I still have a lot of stuff in my to-review
3
folder, which I may or may not get to before the Christmas break...)
2
4
3
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2019-02-26 19:04:47 +0000)
5
thanks
6
-- PMM
7
8
The following changes since commit 5e7b204dbfae9a562fc73684986f936b97f63877:
9
10
Merge remote-tracking branch 'remotes/mst/tags/for_upstream' into staging (2020-12-09 20:08:54 +0000)
4
11
5
are available in the Git repository at:
12
are available in the Git repository at:
6
13
7
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190228-1
14
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20201210
8
15
9
for you to fetch changes up to 1c9af3a9e05c1607a36df4943f8f5393d7621a91:
16
for you to fetch changes up to 71f916be1c7e9ede0e37d9cabc781b5a9e8638ff:
10
17
11
linux-user: Enable HWCAP_ASIMDFHM, HWCAP_JSCVT (2019-02-28 11:03:05 +0000)
18
hw/arm/armv7m: Correct typo in QOM object name (2020-12-10 11:44:56 +0000)
12
19
13
----------------------------------------------------------------
20
----------------------------------------------------------------
14
target-arm queue:
21
target-arm queue:
15
* add MHU and dual-core support to Musca boards
22
* hw/arm/smmuv3: Fix up L1STD_SPAN decoding
16
* refactor some VFP insns to be gated by ID registers
23
* xlnx-zynqmp: Support Xilinx ZynqMP CAN controllers
17
* Revert "arm: Allow system registers for KVM guests to be changed by QEMU code"
24
* sbsa-ref: allow to use Cortex-A53/57/72 cpus
18
* Implement ARMv8.2-FHM extension
25
* Various minor code cleanups
19
* Advertise JSCVT via HWCAP for linux-user
26
* hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault
27
* Implement more pieces of ARMv8.1M support
20
28
21
----------------------------------------------------------------
29
----------------------------------------------------------------
22
Peter Maydell (11):
30
Alex Chen (4):
23
hw/misc/armsse-mhu.c: Model the SSE-200 Message Handling Unit
31
i.MX25: Fix bad printf format specifiers
24
hw/arm/armsse: Wire up the MHUs
32
i.MX31: Fix bad printf format specifiers
25
target/arm/cpu: Allow init-svtor property to be set after realize
33
i.MX6: Fix bad printf format specifiers
26
target/arm/arm-powerctl: Add new arm_set_cpu_on_and_reset()
34
i.MX6ul: Fix bad printf format specifiers
27
hw/misc/iotkit-sysctl: Correct typo in INITSVTOR0 register name
28
hw/arm/iotkit-sysctl: Add SSE-200 registers
29
hw/arm/iotkit-sysctl: Implement CPUWAIT and INITSVTOR*
30
hw/arm/armsse: Unify init-svtor and cpuwait handling
31
target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions
32
target/arm: Gate "miscellaneous FP" insns by ID register field
33
Revert "arm: Allow system registers for KVM guests to be changed by QEMU code"
34
35
35
Richard Henderson (5):
36
Havard Skinnemoen (1):
36
target/arm: Add helpers for FMLAL
37
tests/qtest/npcm7xx_rng-test: dump random data on failure
37
target/arm: Implement FMLAL and FMLSL for aarch64
38
target/arm: Implement VFMAL and VFMSL for aarch32
39
target/arm: Enable ARMv8.2-FHM for -cpu max
40
linux-user: Enable HWCAP_ASIMDFHM, HWCAP_JSCVT
41
38
42
hw/misc/Makefile.objs | 1 +
39
Kunkun Jiang (1):
43
include/hw/arm/armsse.h | 3 +-
40
hw/arm/smmuv3: Fix up L1STD_SPAN decoding
44
include/hw/misc/armsse-mhu.h | 44 ++++++
45
include/hw/misc/iotkit-sysctl.h | 25 +++-
46
target/arm/arm-powerctl.h | 16 +++
47
target/arm/cpu.h | 76 +++++++++--
48
target/arm/helper.h | 9 ++
49
hw/arm/armsse.c | 91 +++++++++----
50
hw/misc/armsse-mhu.c | 198 +++++++++++++++++++++++++++
51
hw/misc/iotkit-sysctl.c | 294 ++++++++++++++++++++++++++++++++++++++--
52
linux-user/elfload.c | 2 +
53
target/arm/arm-powerctl.c | 56 ++++++++
54
target/arm/cpu.c | 32 ++++-
55
target/arm/cpu64.c | 2 +
56
target/arm/helper.c | 27 +---
57
target/arm/kvm32.c | 23 +++-
58
target/arm/kvm64.c | 2 -
59
target/arm/machine.c | 2 +-
60
target/arm/translate-a64.c | 49 ++++++-
61
target/arm/translate.c | 180 ++++++++++++++++--------
62
target/arm/vec_helper.c | 148 ++++++++++++++++++++
63
MAINTAINERS | 2 +
64
default-configs/arm-softmmu.mak | 1 +
65
hw/misc/trace-events | 4 +
66
24 files changed, 1139 insertions(+), 148 deletions(-)
67
create mode 100644 include/hw/misc/armsse-mhu.h
68
create mode 100644 hw/misc/armsse-mhu.c
69
41
42
Marcin Juszkiewicz (1):
43
sbsa-ref: allow to use Cortex-A53/57/72 cpus
44
45
Peter Maydell (25):
46
hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault
47
target/arm: Implement v8.1M PXN extension
48
target/arm: Don't clobber ID_PFR1.Security on M-profile cores
49
target/arm: Implement VSCCLRM insn
50
target/arm: Implement CLRM instruction
51
target/arm: Enforce M-profile VMRS/VMSR register restrictions
52
target/arm: Refactor M-profile VMSR/VMRS handling
53
target/arm: Move general-use constant expanders up in translate.c
54
target/arm: Implement VLDR/VSTR system register
55
target/arm: Implement M-profile FPSCR_nzcvqc
56
target/arm: Use new FPCR_NZCV_MASK constant
57
target/arm: Factor out preserve-fp-state from full_vfp_access_check()
58
target/arm: Implement FPCXT_S fp system register
59
hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M
60
target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry
61
target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failures
62
target/arm: Implement v8.1M REVIDR register
63
target/arm: Implement new v8.1M NOCP check for exception return
64
target/arm: Implement new v8.1M VLLDM and VLSTM encodings
65
hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit
66
target/arm: Implement CCR_S.TRD behaviour for SG insns
67
hw/intc/armv7m_nvic: Fix "return from inactive handler" check
68
target/arm: Implement M-profile "minimal RAS implementation"
69
hw/intc/armv7m_nvic: Implement read/write for RAS register block
70
hw/arm/armv7m: Correct typo in QOM object name
71
72
Vikram Garhwal (4):
73
hw/net/can: Introduce Xilinx ZynqMP CAN controller
74
xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllers
75
tests/qtest: Introduce tests for Xilinx ZynqMP CAN controller
76
MAINTAINERS: Add maintainer entry for Xilinx ZynqMP CAN controller
77
78
meson.build | 1 +
79
hw/arm/smmuv3-internal.h | 2 +-
80
hw/net/can/trace.h | 1 +
81
include/hw/arm/xlnx-zynqmp.h | 8 +
82
include/hw/intc/armv7m_nvic.h | 2 +
83
include/hw/net/xlnx-zynqmp-can.h | 78 +++
84
target/arm/cpu.h | 46 ++
85
target/arm/m-nocp.decode | 10 +-
86
target/arm/t32.decode | 10 +-
87
target/arm/vfp.decode | 14 +
88
hw/arm/armv7m.c | 4 +-
89
hw/arm/sbsa-ref.c | 23 +-
90
hw/arm/xlnx-zcu102.c | 20 +
91
hw/arm/xlnx-zynqmp.c | 34 ++
92
hw/intc/armv7m_nvic.c | 246 ++++++--
93
hw/misc/imx25_ccm.c | 12 +-
94
hw/misc/imx31_ccm.c | 14 +-
95
hw/misc/imx6_ccm.c | 20 +-
96
hw/misc/imx6_src.c | 2 +-
97
hw/misc/imx6ul_ccm.c | 4 +-
98
hw/misc/imx_ccm.c | 4 +-
99
hw/net/can/xlnx-zynqmp-can.c | 1161 ++++++++++++++++++++++++++++++++++++++
100
target/arm/cpu.c | 5 +-
101
target/arm/helper.c | 7 +-
102
target/arm/m_helper.c | 130 ++++-
103
target/arm/translate.c | 105 +++-
104
tests/qtest/npcm7xx_rng-test.c | 12 +
105
tests/qtest/xlnx-can-test.c | 360 ++++++++++++
106
MAINTAINERS | 8 +
107
hw/Kconfig | 1 +
108
hw/net/can/meson.build | 1 +
109
hw/net/can/trace-events | 9 +
110
target/arm/translate-vfp.c.inc | 511 ++++++++++++++++-
111
tests/qtest/meson.build | 1 +
112
34 files changed, 2713 insertions(+), 153 deletions(-)
113
create mode 100644 hw/net/can/trace.h
114
create mode 100644 include/hw/net/xlnx-zynqmp-can.h
115
create mode 100644 hw/net/can/xlnx-zynqmp-can.c
116
create mode 100644 tests/qtest/xlnx-can-test.c
117
create mode 100644 hw/net/can/trace-events
118
diff view generated by jsdifflib
New patch
[PULL 01/36] hw/arm/smmuv3: Fix up L1STD_SPAN decoding
1
From: Kunkun Jiang <jiangkunkun@huawei.com>
1
2
3
Accroding to the SMMUv3 spec, the SPAN field of Level1 Stream Table
4
Descriptor is 5 bits([4:0]).
5
6
Fixes: 9bde7f0674f(hw/arm/smmuv3: Implement translate callback)
7
Signed-off-by: Kunkun Jiang <jiangkunkun@huawei.com>
8
Message-id: 20201124023711.1184-1-jiangkunkun@huawei.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Acked-by: Eric Auger <eric.auger@redhat.com>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
hw/arm/smmuv3-internal.h | 2 +-
14
1 file changed, 1 insertion(+), 1 deletion(-)
15
16
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/smmuv3-internal.h
19
+++ b/hw/arm/smmuv3-internal.h
20
@@ -XXX,XX +XXX,XX @@ static inline uint64_t l1std_l2ptr(STEDesc *desc)
21
return hi << 32 | lo;
22
}
23
24
-#define L1STD_SPAN(stm) (extract32((stm)->word[0], 0, 4))
25
+#define L1STD_SPAN(stm) (extract32((stm)->word[0], 0, 5))
26
27
#endif
28
--
29
2.20.1
30
31
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/16] hw/misc/armsse-mhu.c: Model the SSE-200 Message Handling Unit
[PULL 02/36] hw/net/can: Introduce Xilinx ZynqMP CAN controller
1
Implement a model of the Message Handling Unit (MHU) found in
1
From: Vikram Garhwal <fnu.vikram@xilinx.com>
2
the Arm SSE-200. This is a simple device which just contains
3
some registers which allow the two cores of the SSE-200
4
to raise interrupts on each other.
5
2
3
The Xilinx ZynqMP CAN controller is developed based on SocketCAN, QEMU CAN bus
4
implementation. Bus connection and socketCAN connection for each CAN module
5
can be set through command lines.
6
7
Example for using single CAN:
8
-object can-bus,id=canbus0 \
9
-machine xlnx-zcu102.canbus0=canbus0 \
10
-object can-host-socketcan,id=socketcan0,if=vcan0,canbus=canbus0
11
12
Example for connecting both CAN to same virtual CAN on host machine:
13
-object can-bus,id=canbus0 -object can-bus,id=canbus1 \
14
-machine xlnx-zcu102.canbus0=canbus0 \
15
-machine xlnx-zcu102.canbus1=canbus1 \
16
-object can-host-socketcan,id=socketcan0,if=vcan0,canbus=canbus0 \
17
-object can-host-socketcan,id=socketcan1,if=vcan0,canbus=canbus1
18
19
To create virtual CAN on the host machine, please check the QEMU CAN docs:
20
https://github.com/qemu/qemu/blob/master/docs/can.txt
21
22
Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
23
Message-id: 1605728926-352690-2-git-send-email-fnu.vikram@xilinx.com
24
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20190219125808.25174-2-peter.maydell@linaro.org
9
---
26
---
10
hw/misc/Makefile.objs | 1 +
27
meson.build | 1 +
11
include/hw/misc/armsse-mhu.h | 44 +++++++
28
hw/net/can/trace.h | 1 +
12
hw/misc/armsse-mhu.c | 198 ++++++++++++++++++++++++++++++++
29
include/hw/net/xlnx-zynqmp-can.h | 78 ++
13
MAINTAINERS | 2 +
30
hw/net/can/xlnx-zynqmp-can.c | 1161 ++++++++++++++++++++++++++++++
14
default-configs/arm-softmmu.mak | 1 +
31
hw/Kconfig | 1 +
15
hw/misc/trace-events | 4 +
32
hw/net/can/meson.build | 1 +
16
6 files changed, 250 insertions(+)
33
hw/net/can/trace-events | 9 +
17
create mode 100644 include/hw/misc/armsse-mhu.h
34
7 files changed, 1252 insertions(+)
18
create mode 100644 hw/misc/armsse-mhu.c
35
create mode 100644 hw/net/can/trace.h
36
create mode 100644 include/hw/net/xlnx-zynqmp-can.h
37
create mode 100644 hw/net/can/xlnx-zynqmp-can.c
38
create mode 100644 hw/net/can/trace-events
19
39
20
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
40
diff --git a/meson.build b/meson.build
21
index XXXXXXX..XXXXXXX 100644
41
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/misc/Makefile.objs
42
--- a/meson.build
23
+++ b/hw/misc/Makefile.objs
43
+++ b/meson.build
24
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_IOTKIT_SECCTL) += iotkit-secctl.o
44
@@ -XXX,XX +XXX,XX @@ if have_system
25
obj-$(CONFIG_IOTKIT_SYSCTL) += iotkit-sysctl.o
45
'hw/misc',
26
obj-$(CONFIG_IOTKIT_SYSINFO) += iotkit-sysinfo.o
46
'hw/misc/macio',
27
obj-$(CONFIG_ARMSSE_CPUID) += armsse-cpuid.o
47
'hw/net',
28
+obj-$(CONFIG_ARMSSE_MHU) += armsse-mhu.o
48
+ 'hw/net/can',
29
49
'hw/nvram',
30
obj-$(CONFIG_PVPANIC) += pvpanic.o
50
'hw/pci',
31
obj-$(CONFIG_AUX) += auxbus.o
51
'hw/pci-host',
32
diff --git a/include/hw/misc/armsse-mhu.h b/include/hw/misc/armsse-mhu.h
52
diff --git a/hw/net/can/trace.h b/hw/net/can/trace.h
33
new file mode 100644
53
new file mode 100644
34
index XXXXXXX..XXXXXXX
54
index XXXXXXX..XXXXXXX
35
--- /dev/null
55
--- /dev/null
36
+++ b/include/hw/misc/armsse-mhu.h
56
+++ b/hw/net/can/trace.h
37
@@ -XXX,XX +XXX,XX @@
57
@@ -0,0 +1 @@
38
+/*
58
+#include "trace/trace-hw_net_can.h"
39
+ * ARM SSE-200 Message Handling Unit (MHU)
59
diff --git a/include/hw/net/xlnx-zynqmp-can.h b/include/hw/net/xlnx-zynqmp-can.h
40
+ *
41
+ * Copyright (c) 2019 Linaro Limited
42
+ * Written by Peter Maydell
43
+ *
44
+ * This program is free software; you can redistribute it and/or modify
45
+ * it under the terms of the GNU General Public License version 2 or
46
+ * (at your option) any later version.
47
+ */
48
+
49
+/*
50
+ * This is a model of the Message Handling Unit (MHU) which is part of the
51
+ * Arm SSE-200 and documented in
52
+ * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
53
+ *
54
+ * QEMU interface:
55
+ * + sysbus MMIO region 0: the system information register bank
56
+ * + sysbus IRQ 0: interrupt for CPU 0
57
+ * + sysbus IRQ 1: interrupt for CPU 1
58
+ */
59
+
60
+#ifndef HW_MISC_SSE_MHU_H
61
+#define HW_MISC_SSE_MHU_H
62
+
63
+#include "hw/sysbus.h"
64
+
65
+#define TYPE_ARMSSE_MHU "armsse-mhu"
66
+#define ARMSSE_MHU(obj) OBJECT_CHECK(ARMSSEMHU, (obj), TYPE_ARMSSE_MHU)
67
+
68
+typedef struct ARMSSEMHU {
69
+ /*< private >*/
70
+ SysBusDevice parent_obj;
71
+
72
+ /*< public >*/
73
+ MemoryRegion iomem;
74
+ qemu_irq cpu0irq;
75
+ qemu_irq cpu1irq;
76
+
77
+ uint32_t cpu0intr;
78
+ uint32_t cpu1intr;
79
+} ARMSSEMHU;
80
+
81
+#endif
82
diff --git a/hw/misc/armsse-mhu.c b/hw/misc/armsse-mhu.c
83
new file mode 100644
60
new file mode 100644
84
index XXXXXXX..XXXXXXX
61
index XXXXXXX..XXXXXXX
85
--- /dev/null
62
--- /dev/null
86
+++ b/hw/misc/armsse-mhu.c
63
+++ b/include/hw/net/xlnx-zynqmp-can.h
87
@@ -XXX,XX +XXX,XX @@
64
@@ -XXX,XX +XXX,XX @@
88
+/*
65
+/*
89
+ * ARM SSE-200 Message Handling Unit (MHU)
66
+ * QEMU model of the Xilinx ZynqMP CAN controller.
90
+ *
67
+ *
91
+ * Copyright (c) 2019 Linaro Limited
68
+ * Copyright (c) 2020 Xilinx Inc.
92
+ * Written by Peter Maydell
93
+ *
69
+ *
94
+ * This program is free software; you can redistribute it and/or modify
70
+ * Written-by: Vikram Garhwal<fnu.vikram@xilinx.com>
95
+ * it under the terms of the GNU General Public License version 2 or
71
+ *
96
+ * (at your option) any later version.
72
+ * Based on QEMU CAN Device emulation implemented by Jin Yang, Deniz Eren and
73
+ * Pavel Pisa.
74
+ *
75
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
76
+ * of this software and associated documentation files (the "Software"), to deal
77
+ * in the Software without restriction, including without limitation the rights
78
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
79
+ * copies of the Software, and to permit persons to whom the Software is
80
+ * furnished to do so, subject to the following conditions:
81
+ *
82
+ * The above copyright notice and this permission notice shall be included in
83
+ * all copies or substantial portions of the Software.
84
+ *
85
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
86
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
87
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
88
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
89
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
90
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
91
+ * THE SOFTWARE.
97
+ */
92
+ */
98
+
93
+
94
+#ifndef XLNX_ZYNQMP_CAN_H
95
+#define XLNX_ZYNQMP_CAN_H
96
+
97
+#include "hw/register.h"
98
+#include "net/can_emu.h"
99
+#include "net/can_host.h"
100
+#include "qemu/fifo32.h"
101
+#include "hw/ptimer.h"
102
+#include "hw/qdev-clock.h"
103
+
104
+#define TYPE_XLNX_ZYNQMP_CAN "xlnx.zynqmp-can"
105
+
106
+#define XLNX_ZYNQMP_CAN(obj) \
107
+ OBJECT_CHECK(XlnxZynqMPCANState, (obj), TYPE_XLNX_ZYNQMP_CAN)
108
+
109
+#define MAX_CAN_CTRLS 2
110
+#define XLNX_ZYNQMP_CAN_R_MAX (0x84 / 4)
111
+#define MAILBOX_CAPACITY 64
112
+#define CAN_TIMER_MAX 0XFFFFUL
113
+#define CAN_DEFAULT_CLOCK (24 * 1000 * 1000)
114
+
115
+/* Each CAN_FRAME will have 4 * 32bit size. */
116
+#define CAN_FRAME_SIZE 4
117
+#define RXFIFO_SIZE (MAILBOX_CAPACITY * CAN_FRAME_SIZE)
118
+
119
+typedef struct XlnxZynqMPCANState {
120
+ SysBusDevice parent_obj;
121
+ MemoryRegion iomem;
122
+
123
+ qemu_irq irq;
124
+
125
+ CanBusClientState bus_client;
126
+ CanBusState *canbus;
127
+
128
+ struct {
129
+ uint32_t ext_clk_freq;
130
+ } cfg;
131
+
132
+ RegisterInfo reg_info[XLNX_ZYNQMP_CAN_R_MAX];
133
+ uint32_t regs[XLNX_ZYNQMP_CAN_R_MAX];
134
+
135
+ Fifo32 rx_fifo;
136
+ Fifo32 tx_fifo;
137
+ Fifo32 txhpb_fifo;
138
+
139
+ ptimer_state *can_timer;
140
+} XlnxZynqMPCANState;
141
+
142
+#endif
143
diff --git a/hw/net/can/xlnx-zynqmp-can.c b/hw/net/can/xlnx-zynqmp-can.c
144
new file mode 100644
145
index XXXXXXX..XXXXXXX
146
--- /dev/null
147
+++ b/hw/net/can/xlnx-zynqmp-can.c
148
@@ -XXX,XX +XXX,XX @@
99
+/*
149
+/*
100
+ * This is a model of the Message Handling Unit (MHU) which is part of the
150
+ * QEMU model of the Xilinx ZynqMP CAN controller.
101
+ * Arm SSE-200 and documented in
151
+ * This implementation is based on the following datasheet:
102
+ * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
152
+ * https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ultrascale-trm.pdf
153
+ *
154
+ * Copyright (c) 2020 Xilinx Inc.
155
+ *
156
+ * Written-by: Vikram Garhwal<fnu.vikram@xilinx.com>
157
+ *
158
+ * Based on QEMU CAN Device emulation implemented by Jin Yang, Deniz Eren and
159
+ * Pavel Pisa
160
+ *
161
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
162
+ * of this software and associated documentation files (the "Software"), to deal
163
+ * in the Software without restriction, including without limitation the rights
164
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
165
+ * copies of the Software, and to permit persons to whom the Software is
166
+ * furnished to do so, subject to the following conditions:
167
+ *
168
+ * The above copyright notice and this permission notice shall be included in
169
+ * all copies or substantial portions of the Software.
170
+ *
171
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
172
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
173
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
174
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
175
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
176
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
177
+ * THE SOFTWARE.
103
+ */
178
+ */
104
+
179
+
105
+#include "qemu/osdep.h"
180
+#include "qemu/osdep.h"
181
+#include "hw/sysbus.h"
182
+#include "hw/register.h"
183
+#include "hw/irq.h"
184
+#include "qapi/error.h"
185
+#include "qemu/bitops.h"
106
+#include "qemu/log.h"
186
+#include "qemu/log.h"
187
+#include "qemu/cutils.h"
188
+#include "sysemu/sysemu.h"
189
+#include "migration/vmstate.h"
190
+#include "hw/qdev-properties.h"
191
+#include "net/can_emu.h"
192
+#include "net/can_host.h"
193
+#include "qemu/event_notifier.h"
194
+#include "qom/object_interfaces.h"
195
+#include "hw/net/xlnx-zynqmp-can.h"
107
+#include "trace.h"
196
+#include "trace.h"
108
+#include "qapi/error.h"
197
+
109
+#include "sysemu/sysemu.h"
198
+#ifndef XLNX_ZYNQMP_CAN_ERR_DEBUG
110
+#include "hw/sysbus.h"
199
+#define XLNX_ZYNQMP_CAN_ERR_DEBUG 0
111
+#include "hw/registerfields.h"
200
+#endif
112
+#include "hw/misc/armsse-mhu.h"
201
+
113
+
202
+#define MAX_DLC 8
114
+REG32(CPU0INTR_STAT, 0x0)
203
+#undef ERROR
115
+REG32(CPU0INTR_SET, 0x4)
204
+
116
+REG32(CPU0INTR_CLR, 0x8)
205
+REG32(SOFTWARE_RESET_REGISTER, 0x0)
117
+REG32(CPU1INTR_STAT, 0x10)
206
+ FIELD(SOFTWARE_RESET_REGISTER, CEN, 1, 1)
118
+REG32(CPU1INTR_SET, 0x14)
207
+ FIELD(SOFTWARE_RESET_REGISTER, SRST, 0, 1)
119
+REG32(CPU1INTR_CLR, 0x18)
208
+REG32(MODE_SELECT_REGISTER, 0x4)
120
+REG32(PID4, 0xfd0)
209
+ FIELD(MODE_SELECT_REGISTER, SNOOP, 2, 1)
121
+REG32(PID5, 0xfd4)
210
+ FIELD(MODE_SELECT_REGISTER, LBACK, 1, 1)
122
+REG32(PID6, 0xfd8)
211
+ FIELD(MODE_SELECT_REGISTER, SLEEP, 0, 1)
123
+REG32(PID7, 0xfdc)
212
+REG32(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, 0x8)
124
+REG32(PID0, 0xfe0)
213
+ FIELD(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, BRP, 0, 8)
125
+REG32(PID1, 0xfe4)
214
+REG32(ARBITRATION_PHASE_BIT_TIMING_REGISTER, 0xc)
126
+REG32(PID2, 0xfe8)
215
+ FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, SJW, 7, 2)
127
+REG32(PID3, 0xfec)
216
+ FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, TS2, 4, 3)
128
+REG32(CID0, 0xff0)
217
+ FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, TS1, 0, 4)
129
+REG32(CID1, 0xff4)
218
+REG32(ERROR_COUNTER_REGISTER, 0x10)
130
+REG32(CID2, 0xff8)
219
+ FIELD(ERROR_COUNTER_REGISTER, REC, 8, 8)
131
+REG32(CID3, 0xffc)
220
+ FIELD(ERROR_COUNTER_REGISTER, TEC, 0, 8)
132
+
221
+REG32(ERROR_STATUS_REGISTER, 0x14)
133
+/* Valid bits in the interrupt registers. If any are set the IRQ is raised */
222
+ FIELD(ERROR_STATUS_REGISTER, ACKER, 4, 1)
134
+#define INTR_MASK 0xf
223
+ FIELD(ERROR_STATUS_REGISTER, BERR, 3, 1)
135
+
224
+ FIELD(ERROR_STATUS_REGISTER, STER, 2, 1)
136
+/* PID/CID values */
225
+ FIELD(ERROR_STATUS_REGISTER, FMER, 1, 1)
137
+static const int armsse_mhu_id[] = {
226
+ FIELD(ERROR_STATUS_REGISTER, CRCER, 0, 1)
138
+ 0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
227
+REG32(STATUS_REGISTER, 0x18)
139
+ 0x56, 0xb8, 0x0b, 0x00, /* PID0..PID3 */
228
+ FIELD(STATUS_REGISTER, SNOOP, 12, 1)
140
+ 0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
229
+ FIELD(STATUS_REGISTER, ACFBSY, 11, 1)
230
+ FIELD(STATUS_REGISTER, TXFLL, 10, 1)
231
+ FIELD(STATUS_REGISTER, TXBFLL, 9, 1)
232
+ FIELD(STATUS_REGISTER, ESTAT, 7, 2)
233
+ FIELD(STATUS_REGISTER, ERRWRN, 6, 1)
234
+ FIELD(STATUS_REGISTER, BBSY, 5, 1)
235
+ FIELD(STATUS_REGISTER, BIDLE, 4, 1)
236
+ FIELD(STATUS_REGISTER, NORMAL, 3, 1)
237
+ FIELD(STATUS_REGISTER, SLEEP, 2, 1)
238
+ FIELD(STATUS_REGISTER, LBACK, 1, 1)
239
+ FIELD(STATUS_REGISTER, CONFIG, 0, 1)
240
+REG32(INTERRUPT_STATUS_REGISTER, 0x1c)
241
+ FIELD(INTERRUPT_STATUS_REGISTER, TXFEMP, 14, 1)
242
+ FIELD(INTERRUPT_STATUS_REGISTER, TXFWMEMP, 13, 1)
243
+ FIELD(INTERRUPT_STATUS_REGISTER, RXFWMFLL, 12, 1)
244
+ FIELD(INTERRUPT_STATUS_REGISTER, WKUP, 11, 1)
245
+ FIELD(INTERRUPT_STATUS_REGISTER, SLP, 10, 1)
246
+ FIELD(INTERRUPT_STATUS_REGISTER, BSOFF, 9, 1)
247
+ FIELD(INTERRUPT_STATUS_REGISTER, ERROR, 8, 1)
248
+ FIELD(INTERRUPT_STATUS_REGISTER, RXNEMP, 7, 1)
249
+ FIELD(INTERRUPT_STATUS_REGISTER, RXOFLW, 6, 1)
250
+ FIELD(INTERRUPT_STATUS_REGISTER, RXUFLW, 5, 1)
251
+ FIELD(INTERRUPT_STATUS_REGISTER, RXOK, 4, 1)
252
+ FIELD(INTERRUPT_STATUS_REGISTER, TXBFLL, 3, 1)
253
+ FIELD(INTERRUPT_STATUS_REGISTER, TXFLL, 2, 1)
254
+ FIELD(INTERRUPT_STATUS_REGISTER, TXOK, 1, 1)
255
+ FIELD(INTERRUPT_STATUS_REGISTER, ARBLST, 0, 1)
256
+REG32(INTERRUPT_ENABLE_REGISTER, 0x20)
257
+ FIELD(INTERRUPT_ENABLE_REGISTER, ETXFEMP, 14, 1)
258
+ FIELD(INTERRUPT_ENABLE_REGISTER, ETXFWMEMP, 13, 1)
259
+ FIELD(INTERRUPT_ENABLE_REGISTER, ERXFWMFLL, 12, 1)
260
+ FIELD(INTERRUPT_ENABLE_REGISTER, EWKUP, 11, 1)
261
+ FIELD(INTERRUPT_ENABLE_REGISTER, ESLP, 10, 1)
262
+ FIELD(INTERRUPT_ENABLE_REGISTER, EBSOFF, 9, 1)
263
+ FIELD(INTERRUPT_ENABLE_REGISTER, EERROR, 8, 1)
264
+ FIELD(INTERRUPT_ENABLE_REGISTER, ERXNEMP, 7, 1)
265
+ FIELD(INTERRUPT_ENABLE_REGISTER, ERXOFLW, 6, 1)
266
+ FIELD(INTERRUPT_ENABLE_REGISTER, ERXUFLW, 5, 1)
267
+ FIELD(INTERRUPT_ENABLE_REGISTER, ERXOK, 4, 1)
268
+ FIELD(INTERRUPT_ENABLE_REGISTER, ETXBFLL, 3, 1)
269
+ FIELD(INTERRUPT_ENABLE_REGISTER, ETXFLL, 2, 1)
270
+ FIELD(INTERRUPT_ENABLE_REGISTER, ETXOK, 1, 1)
271
+ FIELD(INTERRUPT_ENABLE_REGISTER, EARBLST, 0, 1)
272
+REG32(INTERRUPT_CLEAR_REGISTER, 0x24)
273
+ FIELD(INTERRUPT_CLEAR_REGISTER, CTXFEMP, 14, 1)
274
+ FIELD(INTERRUPT_CLEAR_REGISTER, CTXFWMEMP, 13, 1)
275
+ FIELD(INTERRUPT_CLEAR_REGISTER, CRXFWMFLL, 12, 1)
276
+ FIELD(INTERRUPT_CLEAR_REGISTER, CWKUP, 11, 1)
277
+ FIELD(INTERRUPT_CLEAR_REGISTER, CSLP, 10, 1)
278
+ FIELD(INTERRUPT_CLEAR_REGISTER, CBSOFF, 9, 1)
279
+ FIELD(INTERRUPT_CLEAR_REGISTER, CERROR, 8, 1)
280
+ FIELD(INTERRUPT_CLEAR_REGISTER, CRXNEMP, 7, 1)
281
+ FIELD(INTERRUPT_CLEAR_REGISTER, CRXOFLW, 6, 1)
282
+ FIELD(INTERRUPT_CLEAR_REGISTER, CRXUFLW, 5, 1)
283
+ FIELD(INTERRUPT_CLEAR_REGISTER, CRXOK, 4, 1)
284
+ FIELD(INTERRUPT_CLEAR_REGISTER, CTXBFLL, 3, 1)
285
+ FIELD(INTERRUPT_CLEAR_REGISTER, CTXFLL, 2, 1)
286
+ FIELD(INTERRUPT_CLEAR_REGISTER, CTXOK, 1, 1)
287
+ FIELD(INTERRUPT_CLEAR_REGISTER, CARBLST, 0, 1)
288
+REG32(TIMESTAMP_REGISTER, 0x28)
289
+ FIELD(TIMESTAMP_REGISTER, CTS, 0, 1)
290
+REG32(WIR, 0x2c)
291
+ FIELD(WIR, EW, 8, 8)
292
+ FIELD(WIR, FW, 0, 8)
293
+REG32(TXFIFO_ID, 0x30)
294
+ FIELD(TXFIFO_ID, IDH, 21, 11)
295
+ FIELD(TXFIFO_ID, SRRRTR, 20, 1)
296
+ FIELD(TXFIFO_ID, IDE, 19, 1)
297
+ FIELD(TXFIFO_ID, IDL, 1, 18)
298
+ FIELD(TXFIFO_ID, RTR, 0, 1)
299
+REG32(TXFIFO_DLC, 0x34)
300
+ FIELD(TXFIFO_DLC, DLC, 28, 4)
301
+REG32(TXFIFO_DATA1, 0x38)
302
+ FIELD(TXFIFO_DATA1, DB0, 24, 8)
303
+ FIELD(TXFIFO_DATA1, DB1, 16, 8)
304
+ FIELD(TXFIFO_DATA1, DB2, 8, 8)
305
+ FIELD(TXFIFO_DATA1, DB3, 0, 8)
306
+REG32(TXFIFO_DATA2, 0x3c)
307
+ FIELD(TXFIFO_DATA2, DB4, 24, 8)
308
+ FIELD(TXFIFO_DATA2, DB5, 16, 8)
309
+ FIELD(TXFIFO_DATA2, DB6, 8, 8)
310
+ FIELD(TXFIFO_DATA2, DB7, 0, 8)
311
+REG32(TXHPB_ID, 0x40)
312
+ FIELD(TXHPB_ID, IDH, 21, 11)
313
+ FIELD(TXHPB_ID, SRRRTR, 20, 1)
314
+ FIELD(TXHPB_ID, IDE, 19, 1)
315
+ FIELD(TXHPB_ID, IDL, 1, 18)
316
+ FIELD(TXHPB_ID, RTR, 0, 1)
317
+REG32(TXHPB_DLC, 0x44)
318
+ FIELD(TXHPB_DLC, DLC, 28, 4)
319
+REG32(TXHPB_DATA1, 0x48)
320
+ FIELD(TXHPB_DATA1, DB0, 24, 8)
321
+ FIELD(TXHPB_DATA1, DB1, 16, 8)
322
+ FIELD(TXHPB_DATA1, DB2, 8, 8)
323
+ FIELD(TXHPB_DATA1, DB3, 0, 8)
324
+REG32(TXHPB_DATA2, 0x4c)
325
+ FIELD(TXHPB_DATA2, DB4, 24, 8)
326
+ FIELD(TXHPB_DATA2, DB5, 16, 8)
327
+ FIELD(TXHPB_DATA2, DB6, 8, 8)
328
+ FIELD(TXHPB_DATA2, DB7, 0, 8)
329
+REG32(RXFIFO_ID, 0x50)
330
+ FIELD(RXFIFO_ID, IDH, 21, 11)
331
+ FIELD(RXFIFO_ID, SRRRTR, 20, 1)
332
+ FIELD(RXFIFO_ID, IDE, 19, 1)
333
+ FIELD(RXFIFO_ID, IDL, 1, 18)
334
+ FIELD(RXFIFO_ID, RTR, 0, 1)
335
+REG32(RXFIFO_DLC, 0x54)
336
+ FIELD(RXFIFO_DLC, DLC, 28, 4)
337
+ FIELD(RXFIFO_DLC, RXT, 0, 16)
338
+REG32(RXFIFO_DATA1, 0x58)
339
+ FIELD(RXFIFO_DATA1, DB0, 24, 8)
340
+ FIELD(RXFIFO_DATA1, DB1, 16, 8)
341
+ FIELD(RXFIFO_DATA1, DB2, 8, 8)
342
+ FIELD(RXFIFO_DATA1, DB3, 0, 8)
343
+REG32(RXFIFO_DATA2, 0x5c)
344
+ FIELD(RXFIFO_DATA2, DB4, 24, 8)
345
+ FIELD(RXFIFO_DATA2, DB5, 16, 8)
346
+ FIELD(RXFIFO_DATA2, DB6, 8, 8)
347
+ FIELD(RXFIFO_DATA2, DB7, 0, 8)
348
+REG32(AFR, 0x60)
349
+ FIELD(AFR, UAF4, 3, 1)
350
+ FIELD(AFR, UAF3, 2, 1)
351
+ FIELD(AFR, UAF2, 1, 1)
352
+ FIELD(AFR, UAF1, 0, 1)
353
+REG32(AFMR1, 0x64)
354
+ FIELD(AFMR1, AMIDH, 21, 11)
355
+ FIELD(AFMR1, AMSRR, 20, 1)
356
+ FIELD(AFMR1, AMIDE, 19, 1)
357
+ FIELD(AFMR1, AMIDL, 1, 18)
358
+ FIELD(AFMR1, AMRTR, 0, 1)
359
+REG32(AFIR1, 0x68)
360
+ FIELD(AFIR1, AIIDH, 21, 11)
361
+ FIELD(AFIR1, AISRR, 20, 1)
362
+ FIELD(AFIR1, AIIDE, 19, 1)
363
+ FIELD(AFIR1, AIIDL, 1, 18)
364
+ FIELD(AFIR1, AIRTR, 0, 1)
365
+REG32(AFMR2, 0x6c)
366
+ FIELD(AFMR2, AMIDH, 21, 11)
367
+ FIELD(AFMR2, AMSRR, 20, 1)
368
+ FIELD(AFMR2, AMIDE, 19, 1)
369
+ FIELD(AFMR2, AMIDL, 1, 18)
370
+ FIELD(AFMR2, AMRTR, 0, 1)
371
+REG32(AFIR2, 0x70)
372
+ FIELD(AFIR2, AIIDH, 21, 11)
373
+ FIELD(AFIR2, AISRR, 20, 1)
374
+ FIELD(AFIR2, AIIDE, 19, 1)
375
+ FIELD(AFIR2, AIIDL, 1, 18)
376
+ FIELD(AFIR2, AIRTR, 0, 1)
377
+REG32(AFMR3, 0x74)
378
+ FIELD(AFMR3, AMIDH, 21, 11)
379
+ FIELD(AFMR3, AMSRR, 20, 1)
380
+ FIELD(AFMR3, AMIDE, 19, 1)
381
+ FIELD(AFMR3, AMIDL, 1, 18)
382
+ FIELD(AFMR3, AMRTR, 0, 1)
383
+REG32(AFIR3, 0x78)
384
+ FIELD(AFIR3, AIIDH, 21, 11)
385
+ FIELD(AFIR3, AISRR, 20, 1)
386
+ FIELD(AFIR3, AIIDE, 19, 1)
387
+ FIELD(AFIR3, AIIDL, 1, 18)
388
+ FIELD(AFIR3, AIRTR, 0, 1)
389
+REG32(AFMR4, 0x7c)
390
+ FIELD(AFMR4, AMIDH, 21, 11)
391
+ FIELD(AFMR4, AMSRR, 20, 1)
392
+ FIELD(AFMR4, AMIDE, 19, 1)
393
+ FIELD(AFMR4, AMIDL, 1, 18)
394
+ FIELD(AFMR4, AMRTR, 0, 1)
395
+REG32(AFIR4, 0x80)
396
+ FIELD(AFIR4, AIIDH, 21, 11)
397
+ FIELD(AFIR4, AISRR, 20, 1)
398
+ FIELD(AFIR4, AIIDE, 19, 1)
399
+ FIELD(AFIR4, AIIDL, 1, 18)
400
+ FIELD(AFIR4, AIRTR, 0, 1)
401
+
402
+static void can_update_irq(XlnxZynqMPCANState *s)
403
+{
404
+ uint32_t irq;
405
+
406
+ /* Watermark register interrupts. */
407
+ if ((fifo32_num_free(&s->tx_fifo) / CAN_FRAME_SIZE) >
408
+ ARRAY_FIELD_EX32(s->regs, WIR, EW)) {
409
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXFWMEMP, 1);
410
+ }
411
+
412
+ if ((fifo32_num_used(&s->rx_fifo) / CAN_FRAME_SIZE) >
413
+ ARRAY_FIELD_EX32(s->regs, WIR, FW)) {
414
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFWMFLL, 1);
415
+ }
416
+
417
+ /* RX Interrupts. */
418
+ if (fifo32_num_used(&s->rx_fifo) >= CAN_FRAME_SIZE) {
419
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXNEMP, 1);
420
+ }
421
+
422
+ /* TX interrupts. */
423
+ if (fifo32_is_empty(&s->tx_fifo)) {
424
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXFEMP, 1);
425
+ }
426
+
427
+ if (fifo32_is_full(&s->tx_fifo)) {
428
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXFLL, 1);
429
+ }
430
+
431
+ if (fifo32_is_full(&s->txhpb_fifo)) {
432
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXBFLL, 1);
433
+ }
434
+
435
+ irq = s->regs[R_INTERRUPT_STATUS_REGISTER];
436
+ irq &= s->regs[R_INTERRUPT_ENABLE_REGISTER];
437
+
438
+ trace_xlnx_can_update_irq(s->regs[R_INTERRUPT_STATUS_REGISTER],
439
+ s->regs[R_INTERRUPT_ENABLE_REGISTER], irq);
440
+ qemu_set_irq(s->irq, irq);
441
+}
442
+
443
+static void can_ier_post_write(RegisterInfo *reg, uint64_t val)
444
+{
445
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
446
+
447
+ can_update_irq(s);
448
+}
449
+
450
+static uint64_t can_icr_pre_write(RegisterInfo *reg, uint64_t val)
451
+{
452
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
453
+
454
+ s->regs[R_INTERRUPT_STATUS_REGISTER] &= ~val;
455
+ can_update_irq(s);
456
+
457
+ return 0;
458
+}
459
+
460
+static void can_config_reset(XlnxZynqMPCANState *s)
461
+{
462
+ /* Reset all the configuration registers. */
463
+ register_reset(&s->reg_info[R_SOFTWARE_RESET_REGISTER]);
464
+ register_reset(&s->reg_info[R_MODE_SELECT_REGISTER]);
465
+ register_reset(
466
+ &s->reg_info[R_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER]);
467
+ register_reset(&s->reg_info[R_ARBITRATION_PHASE_BIT_TIMING_REGISTER]);
468
+ register_reset(&s->reg_info[R_STATUS_REGISTER]);
469
+ register_reset(&s->reg_info[R_INTERRUPT_STATUS_REGISTER]);
470
+ register_reset(&s->reg_info[R_INTERRUPT_ENABLE_REGISTER]);
471
+ register_reset(&s->reg_info[R_INTERRUPT_CLEAR_REGISTER]);
472
+ register_reset(&s->reg_info[R_WIR]);
473
+}
474
+
475
+static void can_config_mode(XlnxZynqMPCANState *s)
476
+{
477
+ register_reset(&s->reg_info[R_ERROR_COUNTER_REGISTER]);
478
+ register_reset(&s->reg_info[R_ERROR_STATUS_REGISTER]);
479
+
480
+ /* Put XlnxZynqMPCAN in configuration mode. */
481
+ ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 1);
482
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP, 0);
483
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP, 0);
484
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, BSOFF, 0);
485
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ERROR, 0);
486
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOFLW, 0);
487
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 0);
488
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 0);
489
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ARBLST, 0);
490
+
491
+ can_update_irq(s);
492
+}
493
+
494
+static void update_status_register_mode_bits(XlnxZynqMPCANState *s)
495
+{
496
+ bool sleep_status = ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP);
497
+ bool sleep_mode = ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SLEEP);
498
+ /* Wake up interrupt bit. */
499
+ bool wakeup_irq_val = sleep_status && (sleep_mode == 0);
500
+ /* Sleep interrupt bit. */
501
+ bool sleep_irq_val = sleep_mode && (sleep_status == 0);
502
+
503
+ /* Clear previous core mode status bits. */
504
+ ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 0);
505
+ ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 0);
506
+ ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 0);
507
+ ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 0);
508
+
509
+ /* set current mode bit and generate irqs accordingly. */
510
+ if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, LBACK)) {
511
+ ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 1);
512
+ } else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SLEEP)) {
513
+ ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 1);
514
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP,
515
+ sleep_irq_val);
516
+ } else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SNOOP)) {
517
+ ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 1);
518
+ } else {
519
+ /*
520
+ * If all bits are zero then XlnxZynqMPCAN is set in normal mode.
521
+ */
522
+ ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 1);
523
+ /* Set wakeup interrupt bit. */
524
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP,
525
+ wakeup_irq_val);
526
+ }
527
+
528
+ can_update_irq(s);
529
+}
530
+
531
+static void can_exit_sleep_mode(XlnxZynqMPCANState *s)
532
+{
533
+ ARRAY_FIELD_DP32(s->regs, MODE_SELECT_REGISTER, SLEEP, 0);
534
+ update_status_register_mode_bits(s);
535
+}
536
+
537
+static void generate_frame(qemu_can_frame *frame, uint32_t *data)
538
+{
539
+ frame->can_id = data[0];
540
+ frame->can_dlc = FIELD_EX32(data[1], TXFIFO_DLC, DLC);
541
+
542
+ frame->data[0] = FIELD_EX32(data[2], TXFIFO_DATA1, DB3);
543
+ frame->data[1] = FIELD_EX32(data[2], TXFIFO_DATA1, DB2);
544
+ frame->data[2] = FIELD_EX32(data[2], TXFIFO_DATA1, DB1);
545
+ frame->data[3] = FIELD_EX32(data[2], TXFIFO_DATA1, DB0);
546
+
547
+ frame->data[4] = FIELD_EX32(data[3], TXFIFO_DATA2, DB7);
548
+ frame->data[5] = FIELD_EX32(data[3], TXFIFO_DATA2, DB6);
549
+ frame->data[6] = FIELD_EX32(data[3], TXFIFO_DATA2, DB5);
550
+ frame->data[7] = FIELD_EX32(data[3], TXFIFO_DATA2, DB4);
551
+}
552
+
553
+static bool tx_ready_check(XlnxZynqMPCANState *s)
554
+{
555
+ if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, SRST)) {
556
+ g_autofree char *path = object_get_canonical_path(OBJECT(s));
557
+
558
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer data while"
559
+ " data while controller is in reset mode.\n",
560
+ path);
561
+ return false;
562
+ }
563
+
564
+ if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) {
565
+ g_autofree char *path = object_get_canonical_path(OBJECT(s));
566
+
567
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer"
568
+ " data while controller is in configuration mode. Reset"
569
+ " the core so operations can start fresh.\n",
570
+ path);
571
+ return false;
572
+ }
573
+
574
+ if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SNOOP)) {
575
+ g_autofree char *path = object_get_canonical_path(OBJECT(s));
576
+
577
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer"
578
+ " data while controller is in SNOOP MODE.\n",
579
+ path);
580
+ return false;
581
+ }
582
+
583
+ return true;
584
+}
585
+
586
+static void transfer_fifo(XlnxZynqMPCANState *s, Fifo32 *fifo)
587
+{
588
+ qemu_can_frame frame;
589
+ uint32_t data[CAN_FRAME_SIZE];
590
+ int i;
591
+ bool can_tx = tx_ready_check(s);
592
+
593
+ if (!can_tx) {
594
+ g_autofree char *path = object_get_canonical_path(OBJECT(s));
595
+
596
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Controller is not enabled for data"
597
+ " transfer.\n", path);
598
+ can_update_irq(s);
599
+ return;
600
+ }
601
+
602
+ while (!fifo32_is_empty(fifo)) {
603
+ for (i = 0; i < CAN_FRAME_SIZE; i++) {
604
+ data[i] = fifo32_pop(fifo);
605
+ }
606
+
607
+ if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, LBACK)) {
608
+ /*
609
+ * Controller is in loopback. In Loopback mode, the CAN core
610
+ * transmits a recessive bitstream on to the XlnxZynqMPCAN Bus.
611
+ * Any message transmitted is looped back to the RX line and
612
+ * acknowledged. The XlnxZynqMPCAN core receives any message
613
+ * that it transmits.
614
+ */
615
+ if (fifo32_is_full(&s->rx_fifo)) {
616
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOFLW, 1);
617
+ } else {
618
+ for (i = 0; i < CAN_FRAME_SIZE; i++) {
619
+ fifo32_push(&s->rx_fifo, data[i]);
620
+ }
621
+
622
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1);
623
+ }
624
+ } else {
625
+ /* Normal mode Tx. */
626
+ generate_frame(&frame, data);
627
+
628
+ trace_xlnx_can_tx_data(frame.can_id, frame.can_dlc,
629
+ frame.data[0], frame.data[1],
630
+ frame.data[2], frame.data[3],
631
+ frame.data[4], frame.data[5],
632
+ frame.data[6], frame.data[7]);
633
+ can_bus_client_send(&s->bus_client, &frame, 1);
634
+ }
635
+ }
636
+
637
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 1);
638
+ ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, TXBFLL, 0);
639
+
640
+ if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP)) {
641
+ can_exit_sleep_mode(s);
642
+ }
643
+
644
+ can_update_irq(s);
645
+}
646
+
647
+static uint64_t can_srr_pre_write(RegisterInfo *reg, uint64_t val)
648
+{
649
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
650
+
651
+ ARRAY_FIELD_DP32(s->regs, SOFTWARE_RESET_REGISTER, CEN,
652
+ FIELD_EX32(val, SOFTWARE_RESET_REGISTER, CEN));
653
+
654
+ if (FIELD_EX32(val, SOFTWARE_RESET_REGISTER, SRST)) {
655
+ trace_xlnx_can_reset(val);
656
+
657
+ /* First, core will do software reset then will enter in config mode. */
658
+ can_config_reset(s);
659
+ }
660
+
661
+ if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) {
662
+ can_config_mode(s);
663
+ } else {
664
+ /*
665
+ * Leave config mode. Now XlnxZynqMPCAN core will enter normal,
666
+ * sleep, snoop or loopback mode depending upon LBACK, SLEEP, SNOOP
667
+ * register states.
668
+ */
669
+ ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 0);
670
+
671
+ ptimer_transaction_begin(s->can_timer);
672
+ ptimer_set_count(s->can_timer, 0);
673
+ ptimer_transaction_commit(s->can_timer);
674
+
675
+ /* XlnxZynqMPCAN is out of config mode. It will send pending data. */
676
+ transfer_fifo(s, &s->txhpb_fifo);
677
+ transfer_fifo(s, &s->tx_fifo);
678
+ }
679
+
680
+ update_status_register_mode_bits(s);
681
+
682
+ return s->regs[R_SOFTWARE_RESET_REGISTER];
683
+}
684
+
685
+static uint64_t can_msr_pre_write(RegisterInfo *reg, uint64_t val)
686
+{
687
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
688
+ uint8_t multi_mode;
689
+
690
+ /*
691
+ * Multiple mode set check. This is done to make sure user doesn't set
692
+ * multiple modes.
693
+ */
694
+ multi_mode = FIELD_EX32(val, MODE_SELECT_REGISTER, LBACK) +
695
+ FIELD_EX32(val, MODE_SELECT_REGISTER, SLEEP) +
696
+ FIELD_EX32(val, MODE_SELECT_REGISTER, SNOOP);
697
+
698
+ if (multi_mode > 1) {
699
+ g_autofree char *path = object_get_canonical_path(OBJECT(s));
700
+
701
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to config"
702
+ " several modes simultaneously. One mode will be selected"
703
+ " according to their priority: LBACK > SLEEP > SNOOP.\n",
704
+ path);
705
+ }
706
+
707
+ if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) == 0) {
708
+ /* We are in configuration mode, any mode can be selected. */
709
+ s->regs[R_MODE_SELECT_REGISTER] = val;
710
+ } else {
711
+ bool sleep_mode_bit = FIELD_EX32(val, MODE_SELECT_REGISTER, SLEEP);
712
+
713
+ ARRAY_FIELD_DP32(s->regs, MODE_SELECT_REGISTER, SLEEP, sleep_mode_bit);
714
+
715
+ if (FIELD_EX32(val, MODE_SELECT_REGISTER, LBACK)) {
716
+ g_autofree char *path = object_get_canonical_path(OBJECT(s));
717
+
718
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to set"
719
+ " LBACK mode without setting CEN bit as 0.\n",
720
+ path);
721
+ } else if (FIELD_EX32(val, MODE_SELECT_REGISTER, SNOOP)) {
722
+ g_autofree char *path = object_get_canonical_path(OBJECT(s));
723
+
724
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to set"
725
+ " SNOOP mode without setting CEN bit as 0.\n",
726
+ path);
727
+ }
728
+
729
+ update_status_register_mode_bits(s);
730
+ }
731
+
732
+ return s->regs[R_MODE_SELECT_REGISTER];
733
+}
734
+
735
+static uint64_t can_brpr_pre_write(RegisterInfo *reg, uint64_t val)
736
+{
737
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
738
+
739
+ /* Only allow writes when in config mode. */
740
+ if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) {
741
+ return s->regs[R_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER];
742
+ }
743
+
744
+ return val;
745
+}
746
+
747
+static uint64_t can_btr_pre_write(RegisterInfo *reg, uint64_t val)
748
+{
749
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
750
+
751
+ /* Only allow writes when in config mode. */
752
+ if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) {
753
+ return s->regs[R_ARBITRATION_PHASE_BIT_TIMING_REGISTER];
754
+ }
755
+
756
+ return val;
757
+}
758
+
759
+static uint64_t can_tcr_pre_write(RegisterInfo *reg, uint64_t val)
760
+{
761
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
762
+
763
+ if (FIELD_EX32(val, TIMESTAMP_REGISTER, CTS)) {
764
+ ptimer_transaction_begin(s->can_timer);
765
+ ptimer_set_count(s->can_timer, 0);
766
+ ptimer_transaction_commit(s->can_timer);
767
+ }
768
+
769
+ return 0;
770
+}
771
+
772
+static void update_rx_fifo(XlnxZynqMPCANState *s, const qemu_can_frame *frame)
773
+{
774
+ bool filter_pass = false;
775
+ uint16_t timestamp = 0;
776
+
777
+ /* If no filter is enabled. Message will be stored in FIFO. */
778
+ if (!((ARRAY_FIELD_EX32(s->regs, AFR, UAF1)) |
779
+ (ARRAY_FIELD_EX32(s->regs, AFR, UAF2)) |
780
+ (ARRAY_FIELD_EX32(s->regs, AFR, UAF3)) |
781
+ (ARRAY_FIELD_EX32(s->regs, AFR, UAF4)))) {
782
+ filter_pass = true;
783
+ }
784
+
785
+ /*
786
+ * Messages that pass any of the acceptance filters will be stored in
787
+ * the RX FIFO.
788
+ */
789
+ if (ARRAY_FIELD_EX32(s->regs, AFR, UAF1)) {
790
+ uint32_t id_masked = s->regs[R_AFMR1] & frame->can_id;
791
+ uint32_t filter_id_masked = s->regs[R_AFMR1] & s->regs[R_AFIR1];
792
+
793
+ if (filter_id_masked == id_masked) {
794
+ filter_pass = true;
795
+ }
796
+ }
797
+
798
+ if (ARRAY_FIELD_EX32(s->regs, AFR, UAF2)) {
799
+ uint32_t id_masked = s->regs[R_AFMR2] & frame->can_id;
800
+ uint32_t filter_id_masked = s->regs[R_AFMR2] & s->regs[R_AFIR2];
801
+
802
+ if (filter_id_masked == id_masked) {
803
+ filter_pass = true;
804
+ }
805
+ }
806
+
807
+ if (ARRAY_FIELD_EX32(s->regs, AFR, UAF3)) {
808
+ uint32_t id_masked = s->regs[R_AFMR3] & frame->can_id;
809
+ uint32_t filter_id_masked = s->regs[R_AFMR3] & s->regs[R_AFIR3];
810
+
811
+ if (filter_id_masked == id_masked) {
812
+ filter_pass = true;
813
+ }
814
+ }
815
+
816
+ if (ARRAY_FIELD_EX32(s->regs, AFR, UAF4)) {
817
+ uint32_t id_masked = s->regs[R_AFMR4] & frame->can_id;
818
+ uint32_t filter_id_masked = s->regs[R_AFMR4] & s->regs[R_AFIR4];
819
+
820
+ if (filter_id_masked == id_masked) {
821
+ filter_pass = true;
822
+ }
823
+ }
824
+
825
+ if (!filter_pass) {
826
+ trace_xlnx_can_rx_fifo_filter_reject(frame->can_id, frame->can_dlc);
827
+ return;
828
+ }
829
+
830
+ /* Store the message in fifo if it passed through any of the filters. */
831
+ if (filter_pass && frame->can_dlc <= MAX_DLC) {
832
+
833
+ if (fifo32_is_full(&s->rx_fifo)) {
834
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOFLW, 1);
835
+ } else {
836
+ timestamp = CAN_TIMER_MAX - ptimer_get_count(s->can_timer);
837
+
838
+ fifo32_push(&s->rx_fifo, frame->can_id);
839
+
840
+ fifo32_push(&s->rx_fifo, deposit32(0, R_RXFIFO_DLC_DLC_SHIFT,
841
+ R_RXFIFO_DLC_DLC_LENGTH,
842
+ frame->can_dlc) |
843
+ deposit32(0, R_RXFIFO_DLC_RXT_SHIFT,
844
+ R_RXFIFO_DLC_RXT_LENGTH,
845
+ timestamp));
846
+
847
+ /* First 32 bit of the data. */
848
+ fifo32_push(&s->rx_fifo, deposit32(0, R_TXFIFO_DATA1_DB3_SHIFT,
849
+ R_TXFIFO_DATA1_DB3_LENGTH,
850
+ frame->data[0]) |
851
+ deposit32(0, R_TXFIFO_DATA1_DB2_SHIFT,
852
+ R_TXFIFO_DATA1_DB2_LENGTH,
853
+ frame->data[1]) |
854
+ deposit32(0, R_TXFIFO_DATA1_DB1_SHIFT,
855
+ R_TXFIFO_DATA1_DB1_LENGTH,
856
+ frame->data[2]) |
857
+ deposit32(0, R_TXFIFO_DATA1_DB0_SHIFT,
858
+ R_TXFIFO_DATA1_DB0_LENGTH,
859
+ frame->data[3]));
860
+ /* Last 32 bit of the data. */
861
+ fifo32_push(&s->rx_fifo, deposit32(0, R_TXFIFO_DATA2_DB7_SHIFT,
862
+ R_TXFIFO_DATA2_DB7_LENGTH,
863
+ frame->data[4]) |
864
+ deposit32(0, R_TXFIFO_DATA2_DB6_SHIFT,
865
+ R_TXFIFO_DATA2_DB6_LENGTH,
866
+ frame->data[5]) |
867
+ deposit32(0, R_TXFIFO_DATA2_DB5_SHIFT,
868
+ R_TXFIFO_DATA2_DB5_LENGTH,
869
+ frame->data[6]) |
870
+ deposit32(0, R_TXFIFO_DATA2_DB4_SHIFT,
871
+ R_TXFIFO_DATA2_DB4_LENGTH,
872
+ frame->data[7]));
873
+
874
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1);
875
+ trace_xlnx_can_rx_data(frame->can_id, frame->can_dlc,
876
+ frame->data[0], frame->data[1],
877
+ frame->data[2], frame->data[3],
878
+ frame->data[4], frame->data[5],
879
+ frame->data[6], frame->data[7]);
880
+ }
881
+
882
+ can_update_irq(s);
883
+ }
884
+}
885
+
886
+static uint64_t can_rxfifo_pre_read(RegisterInfo *reg, uint64_t val)
887
+{
888
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
889
+
890
+ if (!fifo32_is_empty(&s->rx_fifo)) {
891
+ val = fifo32_pop(&s->rx_fifo);
892
+ } else {
893
+ ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXUFLW, 1);
894
+ }
895
+
896
+ can_update_irq(s);
897
+ return val;
898
+}
899
+
900
+static void can_filter_enable_post_write(RegisterInfo *reg, uint64_t val)
901
+{
902
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
903
+
904
+ if (ARRAY_FIELD_EX32(s->regs, AFR, UAF1) &&
905
+ ARRAY_FIELD_EX32(s->regs, AFR, UAF2) &&
906
+ ARRAY_FIELD_EX32(s->regs, AFR, UAF3) &&
907
+ ARRAY_FIELD_EX32(s->regs, AFR, UAF4)) {
908
+ ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, ACFBSY, 1);
909
+ } else {
910
+ ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, ACFBSY, 0);
911
+ }
912
+}
913
+
914
+static uint64_t can_filter_mask_pre_write(RegisterInfo *reg, uint64_t val)
915
+{
916
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
917
+ uint32_t reg_idx = (reg->access->addr) / 4;
918
+ uint32_t filter_number = (reg_idx - R_AFMR1) / 2;
919
+
920
+ /* modify an acceptance filter, the corresponding UAF bit should be '0'. */
921
+ if (!(s->regs[R_AFR] & (1 << filter_number))) {
922
+ s->regs[reg_idx] = val;
923
+
924
+ trace_xlnx_can_filter_mask_pre_write(filter_number, s->regs[reg_idx]);
925
+ } else {
926
+ g_autofree char *path = object_get_canonical_path(OBJECT(s));
927
+
928
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Acceptance filter %d"
929
+ " mask is not set as corresponding UAF bit is not 0.\n",
930
+ path, filter_number + 1);
931
+ }
932
+
933
+ return s->regs[reg_idx];
934
+}
935
+
936
+static uint64_t can_filter_id_pre_write(RegisterInfo *reg, uint64_t val)
937
+{
938
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
939
+ uint32_t reg_idx = (reg->access->addr) / 4;
940
+ uint32_t filter_number = (reg_idx - R_AFIR1) / 2;
941
+
942
+ if (!(s->regs[R_AFR] & (1 << filter_number))) {
943
+ s->regs[reg_idx] = val;
944
+
945
+ trace_xlnx_can_filter_id_pre_write(filter_number, s->regs[reg_idx]);
946
+ } else {
947
+ g_autofree char *path = object_get_canonical_path(OBJECT(s));
948
+
949
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Acceptance filter %d"
950
+ " id is not set as corresponding UAF bit is not 0.\n",
951
+ path, filter_number + 1);
952
+ }
953
+
954
+ return s->regs[reg_idx];
955
+}
956
+
957
+static void can_tx_post_write(RegisterInfo *reg, uint64_t val)
958
+{
959
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(reg->opaque);
960
+
961
+ bool is_txhpb = reg->access->addr > A_TXFIFO_DATA2;
962
+
963
+ bool initiate_transfer = (reg->access->addr == A_TXFIFO_DATA2) ||
964
+ (reg->access->addr == A_TXHPB_DATA2);
965
+
966
+ Fifo32 *f = is_txhpb ? &s->txhpb_fifo : &s->tx_fifo;
967
+
968
+ if (!fifo32_is_full(f)) {
969
+ fifo32_push(f, val);
970
+ } else {
971
+ g_autofree char *path = object_get_canonical_path(OBJECT(s));
972
+
973
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: TX FIFO is full.\n", path);
974
+ }
975
+
976
+ /* Initiate the message send if TX register is written. */
977
+ if (initiate_transfer &&
978
+ ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) {
979
+ transfer_fifo(s, f);
980
+ }
981
+
982
+ can_update_irq(s);
983
+}
984
+
985
+static const RegisterAccessInfo can_regs_info[] = {
986
+ { .name = "SOFTWARE_RESET_REGISTER",
987
+ .addr = A_SOFTWARE_RESET_REGISTER,
988
+ .rsvd = 0xfffffffc,
989
+ .pre_write = can_srr_pre_write,
990
+ },{ .name = "MODE_SELECT_REGISTER",
991
+ .addr = A_MODE_SELECT_REGISTER,
992
+ .rsvd = 0xfffffff8,
993
+ .pre_write = can_msr_pre_write,
994
+ },{ .name = "ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER",
995
+ .addr = A_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER,
996
+ .rsvd = 0xffffff00,
997
+ .pre_write = can_brpr_pre_write,
998
+ },{ .name = "ARBITRATION_PHASE_BIT_TIMING_REGISTER",
999
+ .addr = A_ARBITRATION_PHASE_BIT_TIMING_REGISTER,
1000
+ .rsvd = 0xfffffe00,
1001
+ .pre_write = can_btr_pre_write,
1002
+ },{ .name = "ERROR_COUNTER_REGISTER",
1003
+ .addr = A_ERROR_COUNTER_REGISTER,
1004
+ .rsvd = 0xffff0000,
1005
+ .ro = 0xffffffff,
1006
+ },{ .name = "ERROR_STATUS_REGISTER",
1007
+ .addr = A_ERROR_STATUS_REGISTER,
1008
+ .rsvd = 0xffffffe0,
1009
+ .w1c = 0x1f,
1010
+ },{ .name = "STATUS_REGISTER", .addr = A_STATUS_REGISTER,
1011
+ .reset = 0x1,
1012
+ .rsvd = 0xffffe000,
1013
+ .ro = 0x1fff,
1014
+ },{ .name = "INTERRUPT_STATUS_REGISTER",
1015
+ .addr = A_INTERRUPT_STATUS_REGISTER,
1016
+ .reset = 0x6000,
1017
+ .rsvd = 0xffff8000,
1018
+ .ro = 0x7fff,
1019
+ },{ .name = "INTERRUPT_ENABLE_REGISTER",
1020
+ .addr = A_INTERRUPT_ENABLE_REGISTER,
1021
+ .rsvd = 0xffff8000,
1022
+ .post_write = can_ier_post_write,
1023
+ },{ .name = "INTERRUPT_CLEAR_REGISTER",
1024
+ .addr = A_INTERRUPT_CLEAR_REGISTER,
1025
+ .rsvd = 0xffff8000,
1026
+ .pre_write = can_icr_pre_write,
1027
+ },{ .name = "TIMESTAMP_REGISTER",
1028
+ .addr = A_TIMESTAMP_REGISTER,
1029
+ .rsvd = 0xfffffffe,
1030
+ .pre_write = can_tcr_pre_write,
1031
+ },{ .name = "WIR", .addr = A_WIR,
1032
+ .reset = 0x3f3f,
1033
+ .rsvd = 0xffff0000,
1034
+ },{ .name = "TXFIFO_ID", .addr = A_TXFIFO_ID,
1035
+ .post_write = can_tx_post_write,
1036
+ },{ .name = "TXFIFO_DLC", .addr = A_TXFIFO_DLC,
1037
+ .rsvd = 0xfffffff,
1038
+ .post_write = can_tx_post_write,
1039
+ },{ .name = "TXFIFO_DATA1", .addr = A_TXFIFO_DATA1,
1040
+ .post_write = can_tx_post_write,
1041
+ },{ .name = "TXFIFO_DATA2", .addr = A_TXFIFO_DATA2,
1042
+ .post_write = can_tx_post_write,
1043
+ },{ .name = "TXHPB_ID", .addr = A_TXHPB_ID,
1044
+ .post_write = can_tx_post_write,
1045
+ },{ .name = "TXHPB_DLC", .addr = A_TXHPB_DLC,
1046
+ .rsvd = 0xfffffff,
1047
+ .post_write = can_tx_post_write,
1048
+ },{ .name = "TXHPB_DATA1", .addr = A_TXHPB_DATA1,
1049
+ .post_write = can_tx_post_write,
1050
+ },{ .name = "TXHPB_DATA2", .addr = A_TXHPB_DATA2,
1051
+ .post_write = can_tx_post_write,
1052
+ },{ .name = "RXFIFO_ID", .addr = A_RXFIFO_ID,
1053
+ .ro = 0xffffffff,
1054
+ .post_read = can_rxfifo_pre_read,
1055
+ },{ .name = "RXFIFO_DLC", .addr = A_RXFIFO_DLC,
1056
+ .rsvd = 0xfff0000,
1057
+ .post_read = can_rxfifo_pre_read,
1058
+ },{ .name = "RXFIFO_DATA1", .addr = A_RXFIFO_DATA1,
1059
+ .post_read = can_rxfifo_pre_read,
1060
+ },{ .name = "RXFIFO_DATA2", .addr = A_RXFIFO_DATA2,
1061
+ .post_read = can_rxfifo_pre_read,
1062
+ },{ .name = "AFR", .addr = A_AFR,
1063
+ .rsvd = 0xfffffff0,
1064
+ .post_write = can_filter_enable_post_write,
1065
+ },{ .name = "AFMR1", .addr = A_AFMR1,
1066
+ .pre_write = can_filter_mask_pre_write,
1067
+ },{ .name = "AFIR1", .addr = A_AFIR1,
1068
+ .pre_write = can_filter_id_pre_write,
1069
+ },{ .name = "AFMR2", .addr = A_AFMR2,
1070
+ .pre_write = can_filter_mask_pre_write,
1071
+ },{ .name = "AFIR2", .addr = A_AFIR2,
1072
+ .pre_write = can_filter_id_pre_write,
1073
+ },{ .name = "AFMR3", .addr = A_AFMR3,
1074
+ .pre_write = can_filter_mask_pre_write,
1075
+ },{ .name = "AFIR3", .addr = A_AFIR3,
1076
+ .pre_write = can_filter_id_pre_write,
1077
+ },{ .name = "AFMR4", .addr = A_AFMR4,
1078
+ .pre_write = can_filter_mask_pre_write,
1079
+ },{ .name = "AFIR4", .addr = A_AFIR4,
1080
+ .pre_write = can_filter_id_pre_write,
1081
+ }
141
+};
1082
+};
142
+
1083
+
143
+static void armsse_mhu_update(ARMSSEMHU *s)
1084
+static void xlnx_zynqmp_can_ptimer_cb(void *opaque)
144
+{
1085
+{
145
+ qemu_set_irq(s->cpu0irq, s->cpu0intr != 0);
1086
+ /* No action required on the timer rollover. */
146
+ qemu_set_irq(s->cpu1irq, s->cpu1intr != 0);
1087
+}
147
+}
1088
+
148
+
1089
+static const MemoryRegionOps can_ops = {
149
+static uint64_t armsse_mhu_read(void *opaque, hwaddr offset, unsigned size)
1090
+ .read = register_read_memory,
150
+{
1091
+ .write = register_write_memory,
151
+ ARMSSEMHU *s = ARMSSE_MHU(opaque);
152
+ uint64_t r;
153
+
154
+ switch (offset) {
155
+ case A_CPU0INTR_STAT:
156
+ r = s->cpu0intr;
157
+ break;
158
+
159
+ case A_CPU1INTR_STAT:
160
+ r = s->cpu1intr;
161
+ break;
162
+
163
+ case A_PID4 ... A_CID3:
164
+ r = armsse_mhu_id[(offset - A_PID4) / 4];
165
+ break;
166
+
167
+ case A_CPU0INTR_SET:
168
+ case A_CPU0INTR_CLR:
169
+ case A_CPU1INTR_SET:
170
+ case A_CPU1INTR_CLR:
171
+ qemu_log_mask(LOG_GUEST_ERROR,
172
+ "SSE MHU: read of write-only register at offset 0x%x\n",
173
+ (int)offset);
174
+ r = 0;
175
+ break;
176
+
177
+ default:
178
+ qemu_log_mask(LOG_GUEST_ERROR,
179
+ "SSE MHU read: bad offset 0x%x\n", (int)offset);
180
+ r = 0;
181
+ break;
182
+ }
183
+ trace_armsse_mhu_read(offset, r, size);
184
+ return r;
185
+}
186
+
187
+static void armsse_mhu_write(void *opaque, hwaddr offset,
188
+ uint64_t value, unsigned size)
189
+{
190
+ ARMSSEMHU *s = ARMSSE_MHU(opaque);
191
+
192
+ trace_armsse_mhu_write(offset, value, size);
193
+
194
+ switch (offset) {
195
+ case A_CPU0INTR_SET:
196
+ s->cpu0intr |= (value & INTR_MASK);
197
+ break;
198
+ case A_CPU0INTR_CLR:
199
+ s->cpu0intr &= ~(value & INTR_MASK);
200
+ break;
201
+ case A_CPU1INTR_SET:
202
+ s->cpu1intr |= (value & INTR_MASK);
203
+ break;
204
+ case A_CPU1INTR_CLR:
205
+ s->cpu1intr &= ~(value & INTR_MASK);
206
+ break;
207
+
208
+ case A_CPU0INTR_STAT:
209
+ case A_CPU1INTR_STAT:
210
+ case A_PID4 ... A_CID3:
211
+ qemu_log_mask(LOG_GUEST_ERROR,
212
+ "SSE MHU: write to read-only register at offset 0x%x\n",
213
+ (int)offset);
214
+ break;
215
+
216
+ default:
217
+ qemu_log_mask(LOG_GUEST_ERROR,
218
+ "SSE MHU write: bad offset 0x%x\n", (int)offset);
219
+ break;
220
+ }
221
+
222
+ armsse_mhu_update(s);
223
+}
224
+
225
+static const MemoryRegionOps armsse_mhu_ops = {
226
+ .read = armsse_mhu_read,
227
+ .write = armsse_mhu_write,
228
+ .endianness = DEVICE_LITTLE_ENDIAN,
1092
+ .endianness = DEVICE_LITTLE_ENDIAN,
229
+ .valid.min_access_size = 4,
1093
+ .valid = {
230
+ .valid.max_access_size = 4,
1094
+ .min_access_size = 4,
1095
+ .max_access_size = 4,
1096
+ },
231
+};
1097
+};
232
+
1098
+
233
+static void armsse_mhu_reset(DeviceState *dev)
1099
+static void xlnx_zynqmp_can_reset_init(Object *obj, ResetType type)
234
+{
1100
+{
235
+ ARMSSEMHU *s = ARMSSE_MHU(dev);
1101
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(obj);
236
+
1102
+ unsigned int i;
237
+ s->cpu0intr = 0;
1103
+
238
+ s->cpu1intr = 0;
1104
+ for (i = R_RXFIFO_ID; i < ARRAY_SIZE(s->reg_info); ++i) {
239
+}
1105
+ register_reset(&s->reg_info[i]);
240
+
1106
+ }
241
+static const VMStateDescription armsse_mhu_vmstate = {
1107
+
242
+ .name = "armsse-mhu",
1108
+ ptimer_transaction_begin(s->can_timer);
1109
+ ptimer_set_count(s->can_timer, 0);
1110
+ ptimer_transaction_commit(s->can_timer);
1111
+}
1112
+
1113
+static void xlnx_zynqmp_can_reset_hold(Object *obj)
1114
+{
1115
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(obj);
1116
+ unsigned int i;
1117
+
1118
+ for (i = 0; i < R_RXFIFO_ID; ++i) {
1119
+ register_reset(&s->reg_info[i]);
1120
+ }
1121
+
1122
+ /*
1123
+ * Reset FIFOs when CAN model is reset. This will clear the fifo writes
1124
+ * done by post_write which gets called from register_reset function,
1125
+ * post_write handle will not be able to trigger tx because CAN will be
1126
+ * disabled when software_reset_register is cleared first.
1127
+ */
1128
+ fifo32_reset(&s->rx_fifo);
1129
+ fifo32_reset(&s->tx_fifo);
1130
+ fifo32_reset(&s->txhpb_fifo);
1131
+}
1132
+
1133
+static bool xlnx_zynqmp_can_can_receive(CanBusClientState *client)
1134
+{
1135
+ XlnxZynqMPCANState *s = container_of(client, XlnxZynqMPCANState,
1136
+ bus_client);
1137
+
1138
+ if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, SRST)) {
1139
+ g_autofree char *path = object_get_canonical_path(OBJECT(s));
1140
+
1141
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Controller is in reset state.\n",
1142
+ path);
1143
+ return false;
1144
+ }
1145
+
1146
+ if ((ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) == 0) {
1147
+ g_autofree char *path = object_get_canonical_path(OBJECT(s));
1148
+
1149
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Controller is disabled. Incoming"
1150
+ " messages will be discarded.\n", path);
1151
+ return false;
1152
+ }
1153
+
1154
+ return true;
1155
+}
1156
+
1157
+static ssize_t xlnx_zynqmp_can_receive(CanBusClientState *client,
1158
+ const qemu_can_frame *buf, size_t buf_size) {
1159
+ XlnxZynqMPCANState *s = container_of(client, XlnxZynqMPCANState,
1160
+ bus_client);
1161
+ const qemu_can_frame *frame = buf;
1162
+
1163
+ if (buf_size <= 0) {
1164
+ g_autofree char *path = object_get_canonical_path(OBJECT(s));
1165
+
1166
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Error in the data received.\n",
1167
+ path);
1168
+ return 0;
1169
+ }
1170
+
1171
+ if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SNOOP)) {
1172
+ /* Snoop Mode: Just keep the data. no response back. */
1173
+ update_rx_fifo(s, frame);
1174
+ } else if ((ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP))) {
1175
+ /*
1176
+ * XlnxZynqMPCAN is in sleep mode. Any data on bus will bring it to wake
1177
+ * up state.
1178
+ */
1179
+ can_exit_sleep_mode(s);
1180
+ update_rx_fifo(s, frame);
1181
+ } else if ((ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP)) == 0) {
1182
+ update_rx_fifo(s, frame);
1183
+ } else {
1184
+ /*
1185
+ * XlnxZynqMPCAN will not participate in normal bus communication
1186
+ * and will not receive any messages transmitted by other CAN nodes.
1187
+ */
1188
+ trace_xlnx_can_rx_discard(s->regs[R_STATUS_REGISTER]);
1189
+ }
1190
+
1191
+ return 1;
1192
+}
1193
+
1194
+static CanBusClientInfo can_xilinx_bus_client_info = {
1195
+ .can_receive = xlnx_zynqmp_can_can_receive,
1196
+ .receive = xlnx_zynqmp_can_receive,
1197
+};
1198
+
1199
+static int xlnx_zynqmp_can_connect_to_bus(XlnxZynqMPCANState *s,
1200
+ CanBusState *bus)
1201
+{
1202
+ s->bus_client.info = &can_xilinx_bus_client_info;
1203
+
1204
+ if (can_bus_insert_client(bus, &s->bus_client) < 0) {
1205
+ return -1;
1206
+ }
1207
+ return 0;
1208
+}
1209
+
1210
+static void xlnx_zynqmp_can_realize(DeviceState *dev, Error **errp)
1211
+{
1212
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(dev);
1213
+
1214
+ if (s->canbus) {
1215
+ if (xlnx_zynqmp_can_connect_to_bus(s, s->canbus) < 0) {
1216
+ g_autofree char *path = object_get_canonical_path(OBJECT(s));
1217
+
1218
+ error_setg(errp, "%s: xlnx_zynqmp_can_connect_to_bus"
1219
+ " failed.", path);
1220
+ return;
1221
+ }
1222
+ }
1223
+
1224
+ /* Create RX FIFO, TXFIFO, TXHPB storage. */
1225
+ fifo32_create(&s->rx_fifo, RXFIFO_SIZE);
1226
+ fifo32_create(&s->tx_fifo, RXFIFO_SIZE);
1227
+ fifo32_create(&s->txhpb_fifo, CAN_FRAME_SIZE);
1228
+
1229
+ /* Allocate a new timer. */
1230
+ s->can_timer = ptimer_init(xlnx_zynqmp_can_ptimer_cb, s,
1231
+ PTIMER_POLICY_DEFAULT);
1232
+
1233
+ ptimer_transaction_begin(s->can_timer);
1234
+
1235
+ ptimer_set_freq(s->can_timer, s->cfg.ext_clk_freq);
1236
+ ptimer_set_limit(s->can_timer, CAN_TIMER_MAX, 1);
1237
+ ptimer_run(s->can_timer, 0);
1238
+ ptimer_transaction_commit(s->can_timer);
1239
+}
1240
+
1241
+static void xlnx_zynqmp_can_init(Object *obj)
1242
+{
1243
+ XlnxZynqMPCANState *s = XLNX_ZYNQMP_CAN(obj);
1244
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1245
+
1246
+ RegisterInfoArray *reg_array;
1247
+
1248
+ memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_CAN,
1249
+ XLNX_ZYNQMP_CAN_R_MAX * 4);
1250
+ reg_array = register_init_block32(DEVICE(obj), can_regs_info,
1251
+ ARRAY_SIZE(can_regs_info),
1252
+ s->reg_info, s->regs,
1253
+ &can_ops,
1254
+ XLNX_ZYNQMP_CAN_ERR_DEBUG,
1255
+ XLNX_ZYNQMP_CAN_R_MAX * 4);
1256
+
1257
+ memory_region_add_subregion(&s->iomem, 0x00, &reg_array->mem);
1258
+ sysbus_init_mmio(sbd, &s->iomem);
1259
+ sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq);
1260
+}
1261
+
1262
+static const VMStateDescription vmstate_can = {
1263
+ .name = TYPE_XLNX_ZYNQMP_CAN,
243
+ .version_id = 1,
1264
+ .version_id = 1,
244
+ .minimum_version_id = 1,
1265
+ .minimum_version_id = 1,
245
+ .fields = (VMStateField[]) {
1266
+ .fields = (VMStateField[]) {
246
+ VMSTATE_UINT32(cpu0intr, ARMSSEMHU),
1267
+ VMSTATE_FIFO32(rx_fifo, XlnxZynqMPCANState),
247
+ VMSTATE_UINT32(cpu1intr, ARMSSEMHU),
1268
+ VMSTATE_FIFO32(tx_fifo, XlnxZynqMPCANState),
248
+ VMSTATE_END_OF_LIST()
1269
+ VMSTATE_FIFO32(txhpb_fifo, XlnxZynqMPCANState),
249
+ },
1270
+ VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPCANState, XLNX_ZYNQMP_CAN_R_MAX),
1271
+ VMSTATE_PTIMER(can_timer, XlnxZynqMPCANState),
1272
+ VMSTATE_END_OF_LIST(),
1273
+ }
250
+};
1274
+};
251
+
1275
+
252
+static void armsse_mhu_init(Object *obj)
1276
+static Property xlnx_zynqmp_can_properties[] = {
253
+{
1277
+ DEFINE_PROP_UINT32("ext_clk_freq", XlnxZynqMPCANState, cfg.ext_clk_freq,
254
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1278
+ CAN_DEFAULT_CLOCK),
255
+ ARMSSEMHU *s = ARMSSE_MHU(obj);
1279
+ DEFINE_PROP_LINK("canbus", XlnxZynqMPCANState, canbus, TYPE_CAN_BUS,
256
+
1280
+ CanBusState *),
257
+ memory_region_init_io(&s->iomem, obj, &armsse_mhu_ops,
1281
+ DEFINE_PROP_END_OF_LIST(),
258
+ s, "armsse-mhu", 0x1000);
1282
+};
259
+ sysbus_init_mmio(sbd, &s->iomem);
1283
+
260
+ sysbus_init_irq(sbd, &s->cpu0irq);
1284
+static void xlnx_zynqmp_can_class_init(ObjectClass *klass, void *data)
261
+ sysbus_init_irq(sbd, &s->cpu1irq);
262
+}
263
+
264
+static void armsse_mhu_class_init(ObjectClass *klass, void *data)
265
+{
1285
+{
266
+ DeviceClass *dc = DEVICE_CLASS(klass);
1286
+ DeviceClass *dc = DEVICE_CLASS(klass);
267
+
1287
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
268
+ dc->reset = armsse_mhu_reset;
1288
+
269
+ dc->vmsd = &armsse_mhu_vmstate;
1289
+ rc->phases.enter = xlnx_zynqmp_can_reset_init;
270
+}
1290
+ rc->phases.hold = xlnx_zynqmp_can_reset_hold;
271
+
1291
+ dc->realize = xlnx_zynqmp_can_realize;
272
+static const TypeInfo armsse_mhu_info = {
1292
+ device_class_set_props(dc, xlnx_zynqmp_can_properties);
273
+ .name = TYPE_ARMSSE_MHU,
1293
+ dc->vmsd = &vmstate_can;
274
+ .parent = TYPE_SYS_BUS_DEVICE,
1294
+}
275
+ .instance_size = sizeof(ARMSSEMHU),
1295
+
276
+ .instance_init = armsse_mhu_init,
1296
+static const TypeInfo can_info = {
277
+ .class_init = armsse_mhu_class_init,
1297
+ .name = TYPE_XLNX_ZYNQMP_CAN,
1298
+ .parent = TYPE_SYS_BUS_DEVICE,
1299
+ .instance_size = sizeof(XlnxZynqMPCANState),
1300
+ .class_init = xlnx_zynqmp_can_class_init,
1301
+ .instance_init = xlnx_zynqmp_can_init,
278
+};
1302
+};
279
+
1303
+
280
+static void armsse_mhu_register_types(void)
1304
+static void can_register_types(void)
281
+{
1305
+{
282
+ type_register_static(&armsse_mhu_info);
1306
+ type_register_static(&can_info);
283
+}
1307
+}
284
+
1308
+
285
+type_init(armsse_mhu_register_types);
1309
+type_init(can_register_types)
286
diff --git a/MAINTAINERS b/MAINTAINERS
1310
diff --git a/hw/Kconfig b/hw/Kconfig
287
index XXXXXXX..XXXXXXX 100644
1311
index XXXXXXX..XXXXXXX 100644
288
--- a/MAINTAINERS
1312
--- a/hw/Kconfig
289
+++ b/MAINTAINERS
1313
+++ b/hw/Kconfig
290
@@ -XXX,XX +XXX,XX @@ F: hw/misc/iotkit-sysinfo.c
1314
@@ -XXX,XX +XXX,XX @@ config XILINX_AXI
291
F: include/hw/misc/iotkit-sysinfo.h
1315
config XLNX_ZYNQMP
292
F: hw/misc/armsse-cpuid.c
1316
bool
293
F: include/hw/misc/armsse-cpuid.h
1317
select REGISTER
294
+F: hw/misc/armsse-mhu.c
1318
+ select CAN_BUS
295
+F: include/hw/misc/armsse-mhu.h
1319
diff --git a/hw/net/can/meson.build b/hw/net/can/meson.build
296
297
Musca
298
M: Peter Maydell <peter.maydell@linaro.org>
299
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
300
index XXXXXXX..XXXXXXX 100644
1320
index XXXXXXX..XXXXXXX 100644
301
--- a/default-configs/arm-softmmu.mak
1321
--- a/hw/net/can/meson.build
302
+++ b/default-configs/arm-softmmu.mak
1322
+++ b/hw/net/can/meson.build
303
@@ -XXX,XX +XXX,XX @@ CONFIG_IOTKIT_SECCTL=y
1323
@@ -XXX,XX +XXX,XX @@ softmmu_ss.add(when: 'CONFIG_CAN_PCI', if_true: files('can_pcm3680_pci.c'))
304
CONFIG_IOTKIT_SYSCTL=y
1324
softmmu_ss.add(when: 'CONFIG_CAN_PCI', if_true: files('can_mioe3680_pci.c'))
305
CONFIG_IOTKIT_SYSINFO=y
1325
softmmu_ss.add(when: 'CONFIG_CAN_CTUCANFD', if_true: files('ctucan_core.c'))
306
CONFIG_ARMSSE_CPUID=y
1326
softmmu_ss.add(when: 'CONFIG_CAN_CTUCANFD_PCI', if_true: files('ctucan_pci.c'))
307
+CONFIG_ARMSSE_MHU=y
1327
+softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP', if_true: files('xlnx-zynqmp-can.c'))
308
1328
diff --git a/hw/net/can/trace-events b/hw/net/can/trace-events
309
CONFIG_VERSATILE=y
1329
new file mode 100644
310
CONFIG_VERSATILE_PCI=y
1330
index XXXXXXX..XXXXXXX
311
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
1331
--- /dev/null
312
index XXXXXXX..XXXXXXX 100644
1332
+++ b/hw/net/can/trace-events
313
--- a/hw/misc/trace-events
1333
@@ -XXX,XX +XXX,XX @@
314
+++ b/hw/misc/trace-events
1334
+# xlnx-zynqmp-can.c
315
@@ -XXX,XX +XXX,XX @@ iotkit_sysctl_reset(void) "IoTKit SysCtl: reset"
1335
+xlnx_can_update_irq(uint32_t isr, uint32_t ier, uint32_t irq) "ISR: 0x%08x IER: 0x%08x IRQ: 0x%08x"
316
# hw/misc/armsse-cpuid.c
1336
+xlnx_can_reset(uint32_t val) "Resetting controller with value = 0x%08x"
317
armsse_cpuid_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
1337
+xlnx_can_rx_fifo_filter_reject(uint32_t id, uint8_t dlc) "Frame: ID: 0x%08x DLC: 0x%02x"
318
armsse_cpuid_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
1338
+xlnx_can_filter_id_pre_write(uint8_t filter_num, uint32_t value) "Filter%d ID: 0x%08x"
319
+
1339
+xlnx_can_filter_mask_pre_write(uint8_t filter_num, uint32_t value) "Filter%d MASK: 0x%08x"
320
+# hw/misc/armsse-mhu.c
1340
+xlnx_can_tx_data(uint32_t id, uint8_t dlc, uint8_t db0, uint8_t db1, uint8_t db2, uint8_t db3, uint8_t db4, uint8_t db5, uint8_t db6, uint8_t db7) "Frame: ID: 0x%08x DLC: 0x%02x DATA: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x"
321
+armsse_mhu_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
1341
+xlnx_can_rx_data(uint32_t id, uint32_t dlc, uint8_t db0, uint8_t db1, uint8_t db2, uint8_t db3, uint8_t db4, uint8_t db5, uint8_t db6, uint8_t db7) "Frame: ID: 0x%08x DLC: 0x%02x DATA: 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x"
322
+armsse_mhu_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
1342
+xlnx_can_rx_discard(uint32_t status) "Controller is not enabled for bus communication. Status Register: 0x%08x"
323
--
1343
--
324
2.20.1
1344
2.20.1
325
1345
326
1346
diff view generated by jsdifflib
New patch
[PULL 03/36] xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllers
1
From: Vikram Garhwal <fnu.vikram@xilinx.com>
1
2
3
Connect CAN0 and CAN1 on the ZynqMP.
4
5
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
6
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
7
Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
8
Message-id: 1605728926-352690-3-git-send-email-fnu.vikram@xilinx.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
include/hw/arm/xlnx-zynqmp.h | 8 ++++++++
12
hw/arm/xlnx-zcu102.c | 20 ++++++++++++++++++++
13
hw/arm/xlnx-zynqmp.c | 34 ++++++++++++++++++++++++++++++++++
14
3 files changed, 62 insertions(+)
15
16
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
17
index XXXXXXX..XXXXXXX 100644
18
--- a/include/hw/arm/xlnx-zynqmp.h
19
+++ b/include/hw/arm/xlnx-zynqmp.h
20
@@ -XXX,XX +XXX,XX @@
21
#include "hw/intc/arm_gic.h"
22
#include "hw/net/cadence_gem.h"
23
#include "hw/char/cadence_uart.h"
24
+#include "hw/net/xlnx-zynqmp-can.h"
25
#include "hw/ide/ahci.h"
26
#include "hw/sd/sdhci.h"
27
#include "hw/ssi/xilinx_spips.h"
28
@@ -XXX,XX +XXX,XX @@
29
#include "hw/cpu/cluster.h"
30
#include "target/arm/cpu.h"
31
#include "qom/object.h"
32
+#include "net/can_emu.h"
33
34
#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
35
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
36
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
37
#define XLNX_ZYNQMP_NUM_RPU_CPUS 2
38
#define XLNX_ZYNQMP_NUM_GEMS 4
39
#define XLNX_ZYNQMP_NUM_UARTS 2
40
+#define XLNX_ZYNQMP_NUM_CAN 2
41
+#define XLNX_ZYNQMP_CAN_REF_CLK (24 * 1000 * 1000)
42
#define XLNX_ZYNQMP_NUM_SDHCI 2
43
#define XLNX_ZYNQMP_NUM_SPIS 2
44
#define XLNX_ZYNQMP_NUM_GDMA_CH 8
45
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
46
47
CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
48
CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
49
+ XlnxZynqMPCANState can[XLNX_ZYNQMP_NUM_CAN];
50
SysbusAHCIState sata;
51
SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI];
52
XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
53
@@ -XXX,XX +XXX,XX @@ struct XlnxZynqMPState {
54
bool virt;
55
/* Has the RPU subsystem? */
56
bool has_rpu;
57
+
58
+ /* CAN bus. */
59
+ CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN];
60
};
61
62
#endif
63
diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/hw/arm/xlnx-zcu102.c
66
+++ b/hw/arm/xlnx-zcu102.c
67
@@ -XXX,XX +XXX,XX @@
68
#include "sysemu/qtest.h"
69
#include "sysemu/device_tree.h"
70
#include "qom/object.h"
71
+#include "net/can_emu.h"
72
73
struct XlnxZCU102 {
74
MachineState parent_obj;
75
@@ -XXX,XX +XXX,XX @@ struct XlnxZCU102 {
76
bool secure;
77
bool virt;
78
79
+ CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN];
80
+
81
struct arm_boot_info binfo;
82
};
83
84
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_init(MachineState *machine)
85
object_property_set_bool(OBJECT(&s->soc), "virtualization", s->virt,
86
&error_fatal);
87
88
+ for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
89
+ gchar *bus_name = g_strdup_printf("canbus%d", i);
90
+
91
+ object_property_set_link(OBJECT(&s->soc), bus_name,
92
+ OBJECT(s->canbus[i]), &error_fatal);
93
+ g_free(bus_name);
94
+ }
95
+
96
qdev_realize(DEVICE(&s->soc), NULL, &error_fatal);
97
98
/* Create and plug in the SD cards */
99
@@ -XXX,XX +XXX,XX @@ static void xlnx_zcu102_machine_instance_init(Object *obj)
100
s->secure = false;
101
/* Default to virt (EL2) being disabled */
102
s->virt = false;
103
+ object_property_add_link(obj, "xlnx-zcu102.canbus0", TYPE_CAN_BUS,
104
+ (Object **)&s->canbus[0],
105
+ object_property_allow_set_link,
106
+ 0);
107
+
108
+ object_property_add_link(obj, "xlnx-zcu102.canbus1", TYPE_CAN_BUS,
109
+ (Object **)&s->canbus[1],
110
+ object_property_allow_set_link,
111
+ 0);
112
}
113
114
static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data)
115
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
116
index XXXXXXX..XXXXXXX 100644
117
--- a/hw/arm/xlnx-zynqmp.c
118
+++ b/hw/arm/xlnx-zynqmp.c
119
@@ -XXX,XX +XXX,XX @@ static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = {
120
21, 22,
121
};
122
123
+static const uint64_t can_addr[XLNX_ZYNQMP_NUM_CAN] = {
124
+ 0xFF060000, 0xFF070000,
125
+};
126
+
127
+static const int can_intr[XLNX_ZYNQMP_NUM_CAN] = {
128
+ 23, 24,
129
+};
130
+
131
static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = {
132
0xFF160000, 0xFF170000,
133
};
134
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_init(Object *obj)
135
TYPE_CADENCE_UART);
136
}
137
138
+ for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
139
+ object_initialize_child(obj, "can[*]", &s->can[i],
140
+ TYPE_XLNX_ZYNQMP_CAN);
141
+ }
142
+
143
object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI);
144
145
for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) {
146
@@ -XXX,XX +XXX,XX @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
147
gic_spi[uart_intr[i]]);
148
}
149
150
+ for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) {
151
+ object_property_set_int(OBJECT(&s->can[i]), "ext_clk_freq",
152
+ XLNX_ZYNQMP_CAN_REF_CLK, &error_abort);
153
+
154
+ object_property_set_link(OBJECT(&s->can[i]), "canbus",
155
+ OBJECT(s->canbus[i]), &error_fatal);
156
+
157
+ sysbus_realize(SYS_BUS_DEVICE(&s->can[i]), &err);
158
+ if (err) {
159
+ error_propagate(errp, err);
160
+ return;
161
+ }
162
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->can[i]), 0, can_addr[i]);
163
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->can[i]), 0,
164
+ gic_spi[can_intr[i]]);
165
+ }
166
+
167
object_property_set_int(OBJECT(&s->sata), "num-ports", SATA_NUM_PORTS,
168
&error_abort);
169
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) {
170
@@ -XXX,XX +XXX,XX @@ static Property xlnx_zynqmp_props[] = {
171
DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false),
172
DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGION,
173
MemoryRegion *),
174
+ DEFINE_PROP_LINK("canbus0", XlnxZynqMPState, canbus[0], TYPE_CAN_BUS,
175
+ CanBusState *),
176
+ DEFINE_PROP_LINK("canbus1", XlnxZynqMPState, canbus[1], TYPE_CAN_BUS,
177
+ CanBusState *),
178
DEFINE_PROP_END_OF_LIST()
179
};
180
181
--
182
2.20.1
183
184
diff view generated by jsdifflib
New patch
[PULL 04/36] tests/qtest: Introduce tests for Xilinx ZynqMP CAN controller
1
1
From: Vikram Garhwal <fnu.vikram@xilinx.com>
2
3
The QTests perform five tests on the Xilinx ZynqMP CAN controller:
4
Tests the CAN controller in loopback, sleep and snoop mode.
5
Tests filtering of incoming CAN messages.
6
7
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
8
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
9
Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
10
Message-id: 1605728926-352690-4-git-send-email-fnu.vikram@xilinx.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
tests/qtest/xlnx-can-test.c | 360 ++++++++++++++++++++++++++++++++++++
14
tests/qtest/meson.build | 1 +
15
2 files changed, 361 insertions(+)
16
create mode 100644 tests/qtest/xlnx-can-test.c
17
18
diff --git a/tests/qtest/xlnx-can-test.c b/tests/qtest/xlnx-can-test.c
19
new file mode 100644
20
index XXXXXXX..XXXXXXX
21
--- /dev/null
22
+++ b/tests/qtest/xlnx-can-test.c
23
@@ -XXX,XX +XXX,XX @@
24
+/*
25
+ * QTests for the Xilinx ZynqMP CAN controller.
26
+ *
27
+ * Copyright (c) 2020 Xilinx Inc.
28
+ *
29
+ * Written-by: Vikram Garhwal<fnu.vikram@xilinx.com>
30
+ *
31
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
32
+ * of this software and associated documentation files (the "Software"), to deal
33
+ * in the Software without restriction, including without limitation the rights
34
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
35
+ * copies of the Software, and to permit persons to whom the Software is
36
+ * furnished to do so, subject to the following conditions:
37
+ *
38
+ * The above copyright notice and this permission notice shall be included in
39
+ * all copies or substantial portions of the Software.
40
+ *
41
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
42
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
43
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
44
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
45
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
46
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
47
+ * THE SOFTWARE.
48
+ */
49
+
50
+#include "qemu/osdep.h"
51
+#include "libqos/libqtest.h"
52
+
53
+/* Base address. */
54
+#define CAN0_BASE_ADDR 0xFF060000
55
+#define CAN1_BASE_ADDR 0xFF070000
56
+
57
+/* Register addresses. */
58
+#define R_SRR_OFFSET 0x00
59
+#define R_MSR_OFFSET 0x04
60
+#define R_SR_OFFSET 0x18
61
+#define R_ISR_OFFSET 0x1C
62
+#define R_ICR_OFFSET 0x24
63
+#define R_TXID_OFFSET 0x30
64
+#define R_TXDLC_OFFSET 0x34
65
+#define R_TXDATA1_OFFSET 0x38
66
+#define R_TXDATA2_OFFSET 0x3C
67
+#define R_RXID_OFFSET 0x50
68
+#define R_RXDLC_OFFSET 0x54
69
+#define R_RXDATA1_OFFSET 0x58
70
+#define R_RXDATA2_OFFSET 0x5C
71
+#define R_AFR 0x60
72
+#define R_AFMR1 0x64
73
+#define R_AFIR1 0x68
74
+#define R_AFMR2 0x6C
75
+#define R_AFIR2 0x70
76
+#define R_AFMR3 0x74
77
+#define R_AFIR3 0x78
78
+#define R_AFMR4 0x7C
79
+#define R_AFIR4 0x80
80
+
81
+/* CAN modes. */
82
+#define CONFIG_MODE 0x00
83
+#define NORMAL_MODE 0x00
84
+#define LOOPBACK_MODE 0x02
85
+#define SNOOP_MODE 0x04
86
+#define SLEEP_MODE 0x01
87
+#define ENABLE_CAN (1 << 1)
88
+#define STATUS_NORMAL_MODE (1 << 3)
89
+#define STATUS_LOOPBACK_MODE (1 << 1)
90
+#define STATUS_SNOOP_MODE (1 << 12)
91
+#define STATUS_SLEEP_MODE (1 << 2)
92
+#define ISR_TXOK (1 << 1)
93
+#define ISR_RXOK (1 << 4)
94
+
95
+static void match_rx_tx_data(const uint32_t *buf_tx, const uint32_t *buf_rx,
96
+ uint8_t can_timestamp)
97
+{
98
+ uint16_t size = 0;
99
+ uint8_t len = 4;
100
+
101
+ while (size < len) {
102
+ if (R_RXID_OFFSET + 4 * size == R_RXDLC_OFFSET) {
103
+ g_assert_cmpint(buf_rx[size], ==, buf_tx[size] + can_timestamp);
104
+ } else {
105
+ g_assert_cmpint(buf_rx[size], ==, buf_tx[size]);
106
+ }
107
+
108
+ size++;
109
+ }
110
+}
111
+
112
+static void read_data(QTestState *qts, uint64_t can_base_addr, uint32_t *buf_rx)
113
+{
114
+ uint32_t int_status;
115
+
116
+ /* Read the interrupt on CAN rx. */
117
+ int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_RXOK;
118
+
119
+ g_assert_cmpint(int_status, ==, ISR_RXOK);
120
+
121
+ /* Read the RX register data for CAN. */
122
+ buf_rx[0] = qtest_readl(qts, can_base_addr + R_RXID_OFFSET);
123
+ buf_rx[1] = qtest_readl(qts, can_base_addr + R_RXDLC_OFFSET);
124
+ buf_rx[2] = qtest_readl(qts, can_base_addr + R_RXDATA1_OFFSET);
125
+ buf_rx[3] = qtest_readl(qts, can_base_addr + R_RXDATA2_OFFSET);
126
+
127
+ /* Clear the RX interrupt. */
128
+ qtest_writel(qts, CAN1_BASE_ADDR + R_ICR_OFFSET, ISR_RXOK);
129
+}
130
+
131
+static void send_data(QTestState *qts, uint64_t can_base_addr,
132
+ const uint32_t *buf_tx)
133
+{
134
+ uint32_t int_status;
135
+
136
+ /* Write the TX register data for CAN. */
137
+ qtest_writel(qts, can_base_addr + R_TXID_OFFSET, buf_tx[0]);
138
+ qtest_writel(qts, can_base_addr + R_TXDLC_OFFSET, buf_tx[1]);
139
+ qtest_writel(qts, can_base_addr + R_TXDATA1_OFFSET, buf_tx[2]);
140
+ qtest_writel(qts, can_base_addr + R_TXDATA2_OFFSET, buf_tx[3]);
141
+
142
+ /* Read the interrupt on CAN for tx. */
143
+ int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_TXOK;
144
+
145
+ g_assert_cmpint(int_status, ==, ISR_TXOK);
146
+
147
+ /* Clear the interrupt for tx. */
148
+ qtest_writel(qts, CAN0_BASE_ADDR + R_ICR_OFFSET, ISR_TXOK);
149
+}
150
+
151
+/*
152
+ * This test will be transferring data from CAN0 and CAN1 through canbus. CAN0
153
+ * initiate the data transfer to can-bus, CAN1 receives the data. Test compares
154
+ * the data sent from CAN0 with received on CAN1.
155
+ */
156
+static void test_can_bus(void)
157
+{
158
+ const uint32_t buf_tx[4] = { 0xFF, 0x80000000, 0x12345678, 0x87654321 };
159
+ uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
160
+ uint32_t status = 0;
161
+ uint8_t can_timestamp = 1;
162
+
163
+ QTestState *qts = qtest_init("-machine xlnx-zcu102"
164
+ " -object can-bus,id=canbus0"
165
+ " -machine xlnx-zcu102.canbus0=canbus0"
166
+ " -machine xlnx-zcu102.canbus1=canbus0"
167
+ );
168
+
169
+ /* Configure the CAN0 and CAN1. */
170
+ qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
171
+ qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
172
+ qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
173
+ qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
174
+
175
+ /* Check here if CAN0 and CAN1 are in normal mode. */
176
+ status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
177
+ g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
178
+
179
+ status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
180
+ g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
181
+
182
+ send_data(qts, CAN0_BASE_ADDR, buf_tx);
183
+
184
+ read_data(qts, CAN1_BASE_ADDR, buf_rx);
185
+ match_rx_tx_data(buf_tx, buf_rx, can_timestamp);
186
+
187
+ qtest_quit(qts);
188
+}
189
+
190
+/*
191
+ * This test is performing loopback mode on CAN0 and CAN1. Data sent from TX of
192
+ * each CAN0 and CAN1 are compared with RX register data for respective CAN.
193
+ */
194
+static void test_can_loopback(void)
195
+{
196
+ uint32_t buf_tx[4] = { 0xFF, 0x80000000, 0x12345678, 0x87654321 };
197
+ uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
198
+ uint32_t status = 0;
199
+
200
+ QTestState *qts = qtest_init("-machine xlnx-zcu102"
201
+ " -object can-bus,id=canbus0"
202
+ " -machine xlnx-zcu102.canbus0=canbus0"
203
+ " -machine xlnx-zcu102.canbus1=canbus0"
204
+ );
205
+
206
+ /* Configure the CAN0 in loopback mode. */
207
+ qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE);
208
+ qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, LOOPBACK_MODE);
209
+ qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
210
+
211
+ /* Check here if CAN0 is set in loopback mode. */
212
+ status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
213
+
214
+ g_assert_cmpint(status, ==, STATUS_LOOPBACK_MODE);
215
+
216
+ send_data(qts, CAN0_BASE_ADDR, buf_tx);
217
+ read_data(qts, CAN0_BASE_ADDR, buf_rx);
218
+ match_rx_tx_data(buf_tx, buf_rx, 0);
219
+
220
+ /* Configure the CAN1 in loopback mode. */
221
+ qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE);
222
+ qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, LOOPBACK_MODE);
223
+ qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
224
+
225
+ /* Check here if CAN1 is set in loopback mode. */
226
+ status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
227
+
228
+ g_assert_cmpint(status, ==, STATUS_LOOPBACK_MODE);
229
+
230
+ send_data(qts, CAN1_BASE_ADDR, buf_tx);
231
+ read_data(qts, CAN1_BASE_ADDR, buf_rx);
232
+ match_rx_tx_data(buf_tx, buf_rx, 0);
233
+
234
+ qtest_quit(qts);
235
+}
236
+
237
+/*
238
+ * Enable filters for CAN1. This will filter incoming messages with ID. In this
239
+ * test message will pass through filter 2.
240
+ */
241
+static void test_can_filter(void)
242
+{
243
+ uint32_t buf_tx[4] = { 0x14, 0x80000000, 0x12345678, 0x87654321 };
244
+ uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
245
+ uint32_t status = 0;
246
+ uint8_t can_timestamp = 1;
247
+
248
+ QTestState *qts = qtest_init("-machine xlnx-zcu102"
249
+ " -object can-bus,id=canbus0"
250
+ " -machine xlnx-zcu102.canbus0=canbus0"
251
+ " -machine xlnx-zcu102.canbus1=canbus0"
252
+ );
253
+
254
+ /* Configure the CAN0 and CAN1. */
255
+ qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
256
+ qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
257
+ qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
258
+ qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
259
+
260
+ /* Check here if CAN0 and CAN1 are in normal mode. */
261
+ status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
262
+ g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
263
+
264
+ status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
265
+ g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
266
+
267
+ /* Set filter for CAN1 for incoming messages. */
268
+ qtest_writel(qts, CAN1_BASE_ADDR + R_AFR, 0x0);
269
+ qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR1, 0xF7);
270
+ qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR1, 0x121F);
271
+ qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR2, 0x5431);
272
+ qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR2, 0x14);
273
+ qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR3, 0x1234);
274
+ qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR3, 0x5431);
275
+ qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR4, 0xFFF);
276
+ qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR4, 0x1234);
277
+
278
+ qtest_writel(qts, CAN1_BASE_ADDR + R_AFR, 0xF);
279
+
280
+ send_data(qts, CAN0_BASE_ADDR, buf_tx);
281
+
282
+ read_data(qts, CAN1_BASE_ADDR, buf_rx);
283
+ match_rx_tx_data(buf_tx, buf_rx, can_timestamp);
284
+
285
+ qtest_quit(qts);
286
+}
287
+
288
+/* Testing sleep mode on CAN0 while CAN1 is in normal mode. */
289
+static void test_can_sleepmode(void)
290
+{
291
+ uint32_t buf_tx[4] = { 0x14, 0x80000000, 0x12345678, 0x87654321 };
292
+ uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
293
+ uint32_t status = 0;
294
+ uint8_t can_timestamp = 1;
295
+
296
+ QTestState *qts = qtest_init("-machine xlnx-zcu102"
297
+ " -object can-bus,id=canbus0"
298
+ " -machine xlnx-zcu102.canbus0=canbus0"
299
+ " -machine xlnx-zcu102.canbus1=canbus0"
300
+ );
301
+
302
+ /* Configure the CAN0. */
303
+ qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE);
304
+ qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, SLEEP_MODE);
305
+ qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
306
+
307
+ qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
308
+ qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
309
+
310
+ /* Check here if CAN0 is in SLEEP mode and CAN1 in normal mode. */
311
+ status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
312
+ g_assert_cmpint(status, ==, STATUS_SLEEP_MODE);
313
+
314
+ status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
315
+ g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
316
+
317
+ send_data(qts, CAN1_BASE_ADDR, buf_tx);
318
+
319
+ /*
320
+ * Once CAN1 sends data on can-bus. CAN0 should exit sleep mode.
321
+ * Check the CAN0 status now. It should exit the sleep mode and receive the
322
+ * incoming data.
323
+ */
324
+ status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
325
+ g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
326
+
327
+ read_data(qts, CAN0_BASE_ADDR, buf_rx);
328
+
329
+ match_rx_tx_data(buf_tx, buf_rx, can_timestamp);
330
+
331
+ qtest_quit(qts);
332
+}
333
+
334
+/* Testing Snoop mode on CAN0 while CAN1 is in normal mode. */
335
+static void test_can_snoopmode(void)
336
+{
337
+ uint32_t buf_tx[4] = { 0x14, 0x80000000, 0x12345678, 0x87654321 };
338
+ uint32_t buf_rx[4] = { 0x00, 0x00, 0x00, 0x00 };
339
+ uint32_t status = 0;
340
+ uint8_t can_timestamp = 1;
341
+
342
+ QTestState *qts = qtest_init("-machine xlnx-zcu102"
343
+ " -object can-bus,id=canbus0"
344
+ " -machine xlnx-zcu102.canbus0=canbus0"
345
+ " -machine xlnx-zcu102.canbus1=canbus0"
346
+ );
347
+
348
+ /* Configure the CAN0. */
349
+ qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE);
350
+ qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, SNOOP_MODE);
351
+ qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
352
+
353
+ qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN);
354
+ qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE);
355
+
356
+ /* Check here if CAN0 is in SNOOP mode and CAN1 in normal mode. */
357
+ status = qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET);
358
+ g_assert_cmpint(status, ==, STATUS_SNOOP_MODE);
359
+
360
+ status = qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET);
361
+ g_assert_cmpint(status, ==, STATUS_NORMAL_MODE);
362
+
363
+ send_data(qts, CAN1_BASE_ADDR, buf_tx);
364
+
365
+ read_data(qts, CAN0_BASE_ADDR, buf_rx);
366
+
367
+ match_rx_tx_data(buf_tx, buf_rx, can_timestamp);
368
+
369
+ qtest_quit(qts);
370
+}
371
+
372
+int main(int argc, char **argv)
373
+{
374
+ g_test_init(&argc, &argv, NULL);
375
+
376
+ qtest_add_func("/net/can/can_bus", test_can_bus);
377
+ qtest_add_func("/net/can/can_loopback", test_can_loopback);
378
+ qtest_add_func("/net/can/can_filter", test_can_filter);
379
+ qtest_add_func("/net/can/can_test_snoopmode", test_can_snoopmode);
380
+ qtest_add_func("/net/can/can_test_sleepmode", test_can_sleepmode);
381
+
382
+ return g_test_run();
383
+}
384
diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
385
index XXXXXXX..XXXXXXX 100644
386
--- a/tests/qtest/meson.build
387
+++ b/tests/qtest/meson.build
388
@@ -XXX,XX +XXX,XX @@ qtests_aarch64 = \
389
['arm-cpu-features',
390
'numa-test',
391
'boot-serial-test',
392
+ 'xlnx-can-test',
393
'migration-test']
394
395
qtests_s390x = \
396
--
397
2.20.1
398
399
diff view generated by jsdifflib
New patch
[PULL 05/36] MAINTAINERS: Add maintainer entry for Xilinx ZynqMP CAN controller
1
From: Vikram Garhwal <fnu.vikram@xilinx.com>
1
2
3
Reviewed-by: Francisco Iglesias <francisco.iglesias@xilinx.com>
4
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
5
Signed-off-by: Vikram Garhwal <fnu.vikram@xilinx.com>
6
Message-id: 1605728926-352690-5-git-send-email-fnu.vikram@xilinx.com
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
9
MAINTAINERS | 8 ++++++++
10
1 file changed, 8 insertions(+)
11
12
diff --git a/MAINTAINERS b/MAINTAINERS
13
index XXXXXXX..XXXXXXX 100644
14
--- a/MAINTAINERS
15
+++ b/MAINTAINERS
16
@@ -XXX,XX +XXX,XX @@ F: hw/net/opencores_eth.c
17
18
Devices
19
-------
20
+Xilinx CAN
21
+M: Vikram Garhwal <fnu.vikram@xilinx.com>
22
+M: Francisco Iglesias <francisco.iglesias@xilinx.com>
23
+S: Maintained
24
+F: hw/net/can/xlnx-*
25
+F: include/hw/net/xlnx-*
26
+F: tests/qtest/xlnx-can-test*
27
+
28
EDU
29
M: Jiri Slaby <jslaby@suse.cz>
30
S: Maintained
31
--
32
2.20.1
33
34
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/16] linux-user: Enable HWCAP_ASIMDFHM, HWCAP_JSCVT
[PULL 06/36] sbsa-ref: allow to use Cortex-A53/57/72 cpus
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
2
2
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
Trusted Firmware now supports A72 on sbsa-ref by default [1] so enable
4
Message-id: 20190219222952.22183-6-richard.henderson@linaro.org
4
it for QEMU as well. A53 was already enabled there.
5
6
1. https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/7117
7
8
Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20201120141705.246690-1-marcin.juszkiewicz@linaro.org
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
13
---
8
linux-user/elfload.c | 2 ++
14
hw/arm/sbsa-ref.c | 23 ++++++++++++++++++++---
9
1 file changed, 2 insertions(+)
15
1 file changed, 20 insertions(+), 3 deletions(-)
10
16
11
diff --git a/linux-user/elfload.c b/linux-user/elfload.c
17
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
12
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
13
--- a/linux-user/elfload.c
19
--- a/hw/arm/sbsa-ref.c
14
+++ b/linux-user/elfload.c
20
+++ b/hw/arm/sbsa-ref.c
15
@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void)
21
@@ -XXX,XX +XXX,XX @@ static const int sbsa_ref_irqmap[] = {
16
GET_FEATURE_ID(aa64_fcma, ARM_HWCAP_A64_FCMA);
22
[SBSA_GWDT] = 16,
17
GET_FEATURE_ID(aa64_sve, ARM_HWCAP_A64_SVE);
23
};
18
GET_FEATURE_ID(aa64_pauth, ARM_HWCAP_A64_PACA | ARM_HWCAP_A64_PACG);
24
19
+ GET_FEATURE_ID(aa64_fhm, ARM_HWCAP_A64_ASIMDFHM);
25
+static const char * const valid_cpus[] = {
20
+ GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT);
26
+ ARM_CPU_TYPE_NAME("cortex-a53"),
21
27
+ ARM_CPU_TYPE_NAME("cortex-a57"),
22
#undef GET_FEATURE_ID
28
+ ARM_CPU_TYPE_NAME("cortex-a72"),
29
+};
30
+
31
+static bool cpu_type_valid(const char *cpu)
32
+{
33
+ int i;
34
+
35
+ for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
36
+ if (strcmp(cpu, valid_cpus[i]) == 0) {
37
+ return true;
38
+ }
39
+ }
40
+ return false;
41
+}
42
+
43
static uint64_t sbsa_ref_cpu_mp_affinity(SBSAMachineState *sms, int idx)
44
{
45
uint8_t clustersz = ARM_DEFAULT_CPUS_PER_CLUSTER;
46
@@ -XXX,XX +XXX,XX @@ static void sbsa_ref_init(MachineState *machine)
47
const CPUArchIdList *possible_cpus;
48
int n, sbsa_max_cpus;
49
50
- if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a57"))) {
51
- error_report("sbsa-ref: CPU type other than the built-in "
52
- "cortex-a57 not supported");
53
+ if (!cpu_type_valid(machine->cpu_type)) {
54
+ error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
55
exit(1);
56
}
23
57
24
--
58
--
25
2.20.1
59
2.20.1
26
60
27
61
diff view generated by jsdifflib
New patch
[PULL 07/36] tests/qtest/npcm7xx_rng-test: dump random data on failure
1
From: Havard Skinnemoen <hskinnemoen@google.com>
1
2
3
Dump the collected random data after a randomness test failure.
4
5
Note that this relies on the test having called
6
g_test_set_nonfatal_assertions() so we don't abort immediately on the
7
assertion failure.
8
9
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
[PMM: minor commit message tweak]
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
tests/qtest/npcm7xx_rng-test.c | 12 ++++++++++++
15
1 file changed, 12 insertions(+)
16
17
diff --git a/tests/qtest/npcm7xx_rng-test.c b/tests/qtest/npcm7xx_rng-test.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/tests/qtest/npcm7xx_rng-test.c
20
+++ b/tests/qtest/npcm7xx_rng-test.c
21
@@ -XXX,XX +XXX,XX @@
22
23
#include "libqtest-single.h"
24
#include "qemu/bitops.h"
25
+#include "qemu-common.h"
26
27
#define RNG_BASE_ADDR 0xf000b000
28
29
@@ -XXX,XX +XXX,XX @@
30
/* Number of bits to collect for randomness tests. */
31
#define TEST_INPUT_BITS (128)
32
33
+static void dump_buf_if_failed(const uint8_t *buf, size_t size)
34
+{
35
+ if (g_test_failed()) {
36
+ qemu_hexdump(stderr, "", buf, size);
37
+ }
38
+}
39
+
40
static void rng_writeb(unsigned int offset, uint8_t value)
41
{
42
writeb(RNG_BASE_ADDR + offset, value);
43
@@ -XXX,XX +XXX,XX @@ static void test_continuous_monobit(void)
44
}
45
46
g_assert_cmpfloat(calc_monobit_p(buf, sizeof(buf)), >, 0.01);
47
+ dump_buf_if_failed(buf, sizeof(buf));
48
}
49
50
/*
51
@@ -XXX,XX +XXX,XX @@ static void test_continuous_runs(void)
52
}
53
54
g_assert_cmpfloat(calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE), >, 0.01);
55
+ dump_buf_if_failed(buf.c, sizeof(buf));
56
}
57
58
/*
59
@@ -XXX,XX +XXX,XX @@ static void test_first_byte_monobit(void)
60
}
61
62
g_assert_cmpfloat(calc_monobit_p(buf, sizeof(buf)), >, 0.01);
63
+ dump_buf_if_failed(buf, sizeof(buf));
64
}
65
66
/*
67
@@ -XXX,XX +XXX,XX @@ static void test_first_byte_runs(void)
68
}
69
70
g_assert_cmpfloat(calc_runs_p(buf.l, sizeof(buf) * BITS_PER_BYTE), >, 0.01);
71
+ dump_buf_if_failed(buf.c, sizeof(buf));
72
}
73
74
int main(int argc, char **argv)
75
--
76
2.20.1
77
78
diff view generated by jsdifflib
New patch
[PULL 08/36] i.MX25: Fix bad printf format specifiers
1
From: Alex Chen <alex.chen@huawei.com>
1
2
3
We should use printf format specifier "%u" instead of "%d" for
4
argument of type "unsigned int".
5
6
Reported-by: Euler Robot <euler.robot@huawei.com>
7
Signed-off-by: Alex Chen <alex.chen@huawei.com>
8
Message-id: 20201126111109.112238-2-alex.chen@huawei.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/misc/imx25_ccm.c | 12 ++++++------
13
1 file changed, 6 insertions(+), 6 deletions(-)
14
15
diff --git a/hw/misc/imx25_ccm.c b/hw/misc/imx25_ccm.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/misc/imx25_ccm.c
18
+++ b/hw/misc/imx25_ccm.c
19
@@ -XXX,XX +XXX,XX @@ static const char *imx25_ccm_reg_name(uint32_t reg)
20
case IMX25_CCM_LPIMR1_REG:
21
return "lpimr1";
22
default:
23
- sprintf(unknown, "[%d ?]", reg);
24
+ sprintf(unknown, "[%u ?]", reg);
25
return unknown;
26
}
27
}
28
@@ -XXX,XX +XXX,XX @@ static uint32_t imx25_ccm_get_mpll_clk(IMXCCMState *dev)
29
freq = imx_ccm_calc_pll(s->reg[IMX25_CCM_MPCTL_REG], CKIH_FREQ);
30
}
31
32
- DPRINTF("freq = %d\n", freq);
33
+ DPRINTF("freq = %u\n", freq);
34
35
return freq;
36
}
37
@@ -XXX,XX +XXX,XX @@ static uint32_t imx25_ccm_get_mcu_clk(IMXCCMState *dev)
38
39
freq = freq / (1 + EXTRACT(s->reg[IMX25_CCM_CCTL_REG], ARM_CLK_DIV));
40
41
- DPRINTF("freq = %d\n", freq);
42
+ DPRINTF("freq = %u\n", freq);
43
44
return freq;
45
}
46
@@ -XXX,XX +XXX,XX @@ static uint32_t imx25_ccm_get_ahb_clk(IMXCCMState *dev)
47
freq = imx25_ccm_get_mcu_clk(dev)
48
/ (1 + EXTRACT(s->reg[IMX25_CCM_CCTL_REG], AHB_CLK_DIV));
49
50
- DPRINTF("freq = %d\n", freq);
51
+ DPRINTF("freq = %u\n", freq);
52
53
return freq;
54
}
55
@@ -XXX,XX +XXX,XX @@ static uint32_t imx25_ccm_get_ipg_clk(IMXCCMState *dev)
56
57
freq = imx25_ccm_get_ahb_clk(dev) / 2;
58
59
- DPRINTF("freq = %d\n", freq);
60
+ DPRINTF("freq = %u\n", freq);
61
62
return freq;
63
}
64
@@ -XXX,XX +XXX,XX @@ static uint32_t imx25_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
65
break;
66
}
67
68
- DPRINTF("Clock = %d) = %d\n", clock, freq);
69
+ DPRINTF("Clock = %d) = %u\n", clock, freq);
70
71
return freq;
72
}
73
--
74
2.20.1
75
76
diff view generated by jsdifflib
New patch
[PULL 09/36] i.MX31: Fix bad printf format specifiers
1
From: Alex Chen <alex.chen@huawei.com>
1
2
3
We should use printf format specifier "%u" instead of "%d" for
4
argument of type "unsigned int".
5
6
Reported-by: Euler Robot <euler.robot@huawei.com>
7
Signed-off-by: Alex Chen <alex.chen@huawei.com>
8
Message-id: 20201126111109.112238-3-alex.chen@huawei.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/misc/imx31_ccm.c | 14 +++++++-------
13
hw/misc/imx_ccm.c | 4 ++--
14
2 files changed, 9 insertions(+), 9 deletions(-)
15
16
diff --git a/hw/misc/imx31_ccm.c b/hw/misc/imx31_ccm.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/misc/imx31_ccm.c
19
+++ b/hw/misc/imx31_ccm.c
20
@@ -XXX,XX +XXX,XX @@ static const char *imx31_ccm_reg_name(uint32_t reg)
21
case IMX31_CCM_PDR2_REG:
22
return "PDR2";
23
default:
24
- sprintf(unknown, "[%d ?]", reg);
25
+ sprintf(unknown, "[%u ?]", reg);
26
return unknown;
27
}
28
}
29
@@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_pll_ref_clk(IMXCCMState *dev)
30
freq = CKIH_FREQ;
31
}
32
33
- DPRINTF("freq = %d\n", freq);
34
+ DPRINTF("freq = %u\n", freq);
35
36
return freq;
37
}
38
@@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_mpll_clk(IMXCCMState *dev)
39
freq = imx_ccm_calc_pll(s->reg[IMX31_CCM_MPCTL_REG],
40
imx31_ccm_get_pll_ref_clk(dev));
41
42
- DPRINTF("freq = %d\n", freq);
43
+ DPRINTF("freq = %u\n", freq);
44
45
return freq;
46
}
47
@@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_mcu_main_clk(IMXCCMState *dev)
48
freq = imx31_ccm_get_mpll_clk(dev);
49
}
50
51
- DPRINTF("freq = %d\n", freq);
52
+ DPRINTF("freq = %u\n", freq);
53
54
return freq;
55
}
56
@@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_hclk_clk(IMXCCMState *dev)
57
freq = imx31_ccm_get_mcu_main_clk(dev)
58
/ (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], MAX));
59
60
- DPRINTF("freq = %d\n", freq);
61
+ DPRINTF("freq = %u\n", freq);
62
63
return freq;
64
}
65
@@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_ipg_clk(IMXCCMState *dev)
66
freq = imx31_ccm_get_hclk_clk(dev)
67
/ (1 + EXTRACT(s->reg[IMX31_CCM_PDR0_REG], IPG));
68
69
- DPRINTF("freq = %d\n", freq);
70
+ DPRINTF("freq = %u\n", freq);
71
72
return freq;
73
}
74
@@ -XXX,XX +XXX,XX @@ static uint32_t imx31_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
75
break;
76
}
77
78
- DPRINTF("Clock = %d) = %d\n", clock, freq);
79
+ DPRINTF("Clock = %d) = %u\n", clock, freq);
80
81
return freq;
82
}
83
diff --git a/hw/misc/imx_ccm.c b/hw/misc/imx_ccm.c
84
index XXXXXXX..XXXXXXX 100644
85
--- a/hw/misc/imx_ccm.c
86
+++ b/hw/misc/imx_ccm.c
87
@@ -XXX,XX +XXX,XX @@ uint32_t imx_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
88
freq = klass->get_clock_frequency(dev, clock);
89
}
90
91
- DPRINTF("(clock = %d) = %d\n", clock, freq);
92
+ DPRINTF("(clock = %d) = %u\n", clock, freq);
93
94
return freq;
95
}
96
@@ -XXX,XX +XXX,XX @@ uint32_t imx_ccm_calc_pll(uint32_t pllreg, uint32_t base_freq)
97
freq = ((2 * (base_freq >> 10) * (mfi * mfd + mfn)) /
98
(mfd * pd)) << 10;
99
100
- DPRINTF("(pllreg = 0x%08x, base_freq = %d) = %d\n", pllreg, base_freq,
101
+ DPRINTF("(pllreg = 0x%08x, base_freq = %u) = %d\n", pllreg, base_freq,
102
freq);
103
104
return freq;
105
--
106
2.20.1
107
108
diff view generated by jsdifflib
New patch
[PULL 10/36] i.MX6: Fix bad printf format specifiers
1
From: Alex Chen <alex.chen@huawei.com>
1
2
3
We should use printf format specifier "%u" instead of "%d" for
4
argument of type "unsigned int".
5
6
Reported-by: Euler Robot <euler.robot@huawei.com>
7
Signed-off-by: Alex Chen <alex.chen@huawei.com>
8
Message-id: 20201126111109.112238-4-alex.chen@huawei.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/misc/imx6_ccm.c | 20 ++++++++++----------
13
hw/misc/imx6_src.c | 2 +-
14
2 files changed, 11 insertions(+), 11 deletions(-)
15
16
diff --git a/hw/misc/imx6_ccm.c b/hw/misc/imx6_ccm.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/misc/imx6_ccm.c
19
+++ b/hw/misc/imx6_ccm.c
20
@@ -XXX,XX +XXX,XX @@ static const char *imx6_ccm_reg_name(uint32_t reg)
21
case CCM_CMEOR:
22
return "CMEOR";
23
default:
24
- sprintf(unknown, "%d ?", reg);
25
+ sprintf(unknown, "%u ?", reg);
26
return unknown;
27
}
28
}
29
@@ -XXX,XX +XXX,XX @@ static const char *imx6_analog_reg_name(uint32_t reg)
30
case USB_ANALOG_DIGPROG:
31
return "USB_ANALOG_DIGPROG";
32
default:
33
- sprintf(unknown, "%d ?", reg);
34
+ sprintf(unknown, "%u ?", reg);
35
return unknown;
36
}
37
}
38
@@ -XXX,XX +XXX,XX @@ static uint64_t imx6_analog_get_pll2_clk(IMX6CCMState *dev)
39
freq *= 20;
40
}
41
42
- DPRINTF("freq = %d\n", (uint32_t)freq);
43
+ DPRINTF("freq = %u\n", (uint32_t)freq);
44
45
return freq;
46
}
47
@@ -XXX,XX +XXX,XX @@ static uint64_t imx6_analog_get_pll2_pfd0_clk(IMX6CCMState *dev)
48
freq = imx6_analog_get_pll2_clk(dev) * 18
49
/ EXTRACT(dev->analog[CCM_ANALOG_PFD_528], PFD0_FRAC);
50
51
- DPRINTF("freq = %d\n", (uint32_t)freq);
52
+ DPRINTF("freq = %u\n", (uint32_t)freq);
53
54
return freq;
55
}
56
@@ -XXX,XX +XXX,XX @@ static uint64_t imx6_analog_get_pll2_pfd2_clk(IMX6CCMState *dev)
57
freq = imx6_analog_get_pll2_clk(dev) * 18
58
/ EXTRACT(dev->analog[CCM_ANALOG_PFD_528], PFD2_FRAC);
59
60
- DPRINTF("freq = %d\n", (uint32_t)freq);
61
+ DPRINTF("freq = %u\n", (uint32_t)freq);
62
63
return freq;
64
}
65
@@ -XXX,XX +XXX,XX @@ static uint64_t imx6_analog_get_periph_clk(IMX6CCMState *dev)
66
break;
67
}
68
69
- DPRINTF("freq = %d\n", (uint32_t)freq);
70
+ DPRINTF("freq = %u\n", (uint32_t)freq);
71
72
return freq;
73
}
74
@@ -XXX,XX +XXX,XX @@ static uint64_t imx6_ccm_get_ahb_clk(IMX6CCMState *dev)
75
freq = imx6_analog_get_periph_clk(dev)
76
/ (1 + EXTRACT(dev->ccm[CCM_CBCDR], AHB_PODF));
77
78
- DPRINTF("freq = %d\n", (uint32_t)freq);
79
+ DPRINTF("freq = %u\n", (uint32_t)freq);
80
81
return freq;
82
}
83
@@ -XXX,XX +XXX,XX @@ static uint64_t imx6_ccm_get_ipg_clk(IMX6CCMState *dev)
84
freq = imx6_ccm_get_ahb_clk(dev)
85
/ (1 + EXTRACT(dev->ccm[CCM_CBCDR], IPG_PODF));
86
87
- DPRINTF("freq = %d\n", (uint32_t)freq);
88
+ DPRINTF("freq = %u\n", (uint32_t)freq);
89
90
return freq;
91
}
92
@@ -XXX,XX +XXX,XX @@ static uint64_t imx6_ccm_get_per_clk(IMX6CCMState *dev)
93
freq = imx6_ccm_get_ipg_clk(dev)
94
/ (1 + EXTRACT(dev->ccm[CCM_CSCMR1], PERCLK_PODF));
95
96
- DPRINTF("freq = %d\n", (uint32_t)freq);
97
+ DPRINTF("freq = %u\n", (uint32_t)freq);
98
99
return freq;
100
}
101
@@ -XXX,XX +XXX,XX @@ static uint32_t imx6_ccm_get_clock_frequency(IMXCCMState *dev, IMXClk clock)
102
break;
103
}
104
105
- DPRINTF("Clock = %d) = %d\n", clock, freq);
106
+ DPRINTF("Clock = %d) = %u\n", clock, freq);
107
108
return freq;
109
}
110
diff --git a/hw/misc/imx6_src.c b/hw/misc/imx6_src.c
111
index XXXXXXX..XXXXXXX 100644
112
--- a/hw/misc/imx6_src.c
113
+++ b/hw/misc/imx6_src.c
114
@@ -XXX,XX +XXX,XX @@ static const char *imx6_src_reg_name(uint32_t reg)
115
case SRC_GPR10:
116
return "SRC_GPR10";
117
default:
118
- sprintf(unknown, "%d ?", reg);
119
+ sprintf(unknown, "%u ?", reg);
120
return unknown;
121
}
122
}
123
--
124
2.20.1
125
126
diff view generated by jsdifflib
New patch
[PULL 11/36] i.MX6ul: Fix bad printf format specifiers
1
From: Alex Chen <alex.chen@huawei.com>
1
2
3
We should use printf format specifier "%u" instead of "%d" for
4
argument of type "unsigned int".
5
6
Reported-by: Euler Robot <euler.robot@huawei.com>
7
Signed-off-by: Alex Chen <alex.chen@huawei.com>
8
Message-id: 20201126111109.112238-5-alex.chen@huawei.com
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
hw/misc/imx6ul_ccm.c | 4 ++--
13
1 file changed, 2 insertions(+), 2 deletions(-)
14
15
diff --git a/hw/misc/imx6ul_ccm.c b/hw/misc/imx6ul_ccm.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/misc/imx6ul_ccm.c
18
+++ b/hw/misc/imx6ul_ccm.c
19
@@ -XXX,XX +XXX,XX @@ static const char *imx6ul_ccm_reg_name(uint32_t reg)
20
case CCM_CMEOR:
21
return "CMEOR";
22
default:
23
- sprintf(unknown, "%d ?", reg);
24
+ sprintf(unknown, "%u ?", reg);
25
return unknown;
26
}
27
}
28
@@ -XXX,XX +XXX,XX @@ static const char *imx6ul_analog_reg_name(uint32_t reg)
29
case USB_ANALOG_DIGPROG:
30
return "USB_ANALOG_DIGPROG";
31
default:
32
- sprintf(unknown, "%d ?", reg);
33
+ sprintf(unknown, "%u ?", reg);
34
return unknown;
35
}
36
}
37
--
38
2.20.1
39
40
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/16] hw/arm/armsse: Unify init-svtor and cpuwait handling
[PULL 12/36] hw/intc/armv7m_nvic: Make all of system PPB range be RAZWI/BusFault
1
At the moment the handling of init-svtor and cpuwait initial
1
For M-profile CPUs, the range from 0xe0000000 to 0xe00fffff is the
2
values is split between armsse.c and iotkit-sysctl.c:
2
Private Peripheral Bus range, which includes all of the memory mapped
3
the code in armsse.c sets the initial state of the CPU
3
devices and registers that are part of the CPU itself, including the
4
object by setting the init-svtor and start-powered-off
4
NVIC, systick timer, and debug and trace components like the Data
5
properties, but the iotkit-sysctl.c code has its own
5
Watchpoint and Trace unit (DWT). Within this large region, the range
6
code setting the reset values of its registers (which are
6
0xe000e000 to 0xe000efff is the System Control Space (NVIC, system
7
then used when updating the CPU when the guest makes
7
registers, systick) and 0xe002e000 to 0exe002efff is its Non-secure
8
runtime changes).
8
alias.
9
9
10
Clean this up by making the armsse.c code set properties on the
10
The architecture is clear that within the SCS unimplemented registers
11
iotkit-sysctl object to define the initial values of the
11
should be RES0 for privileged accesses and generate BusFault for
12
registers, so they always match the initial CPU state,
12
unprivileged accesses, and we currently implement this.
13
and update the comments in armsse.c accordingly.
13
14
It is less clear about how to handle accesses to unimplemented
15
regions of the wider PPB. Unprivileged accesses should definitely
16
cause BusFaults (R_DQQS), but the behaviour of privileged accesses is
17
not given as a general rule. However, the register definitions of
18
individual registers for components like the DWT all state that they
19
are RES0 if the relevant component is not implemented, so the
20
simplest way to provide that is to provide RAZ/WI for the whole range
21
for privileged accesses. (The v7M Arm ARM does say that reserved
22
registers should be UNK/SBZP.)
23
24
Expand the container MemoryRegion that the NVIC exposes so that
25
it covers the whole PPB space. This means:
26
* moving the address that the ARMV7M device maps it to down by
27
0xe000 bytes
28
* moving the off and the offsets within the container of all the
29
subregions forward by 0xe000 bytes
30
* adding a new default MemoryRegion that covers the whole container
31
at a lower priority than anything else and which provides the
32
RAZWI/BusFault behaviour
14
33
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
35
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Message-id: 20190219125808.25174-9-peter.maydell@linaro.org
36
Message-id: 20201119215617.29887-2-peter.maydell@linaro.org
18
---
37
---
19
include/hw/misc/iotkit-sysctl.h | 3 ++
38
include/hw/intc/armv7m_nvic.h | 1 +
20
hw/arm/armsse.c | 49 +++++++++++++++++++++------------
39
hw/arm/armv7m.c | 2 +-
21
hw/misc/iotkit-sysctl.c | 20 ++++++--------
40
hw/intc/armv7m_nvic.c | 78 ++++++++++++++++++++++++++++++-----
22
3 files changed, 42 insertions(+), 30 deletions(-)
41
3 files changed, 69 insertions(+), 12 deletions(-)
23
42
24
diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h
43
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
25
index XXXXXXX..XXXXXXX 100644
44
index XXXXXXX..XXXXXXX 100644
26
--- a/include/hw/misc/iotkit-sysctl.h
45
--- a/include/hw/intc/armv7m_nvic.h
27
+++ b/include/hw/misc/iotkit-sysctl.h
46
+++ b/include/hw/intc/armv7m_nvic.h
28
@@ -XXX,XX +XXX,XX @@ typedef struct IoTKitSysCtl {
47
@@ -XXX,XX +XXX,XX @@ struct NVICState {
29
48
MemoryRegion systickmem;
30
/* Properties */
49
MemoryRegion systick_ns_mem;
31
uint32_t sys_version;
50
MemoryRegion container;
32
+ uint32_t cpuwait_rst;
51
+ MemoryRegion defaultmem;
33
+ uint32_t initsvtor0_rst;
52
34
+ uint32_t initsvtor1_rst;
53
uint32_t num_irq;
35
54
qemu_irq excpout;
36
bool is_sse200;
55
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
37
} IoTKitSysCtl;
38
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
39
index XXXXXXX..XXXXXXX 100644
56
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/arm/armsse.c
57
--- a/hw/arm/armv7m.c
41
+++ b/hw/arm/armsse.c
58
+++ b/hw/arm/armv7m.c
42
@@ -XXX,XX +XXX,XX @@
59
@@ -XXX,XX +XXX,XX @@ static void armv7m_realize(DeviceState *dev, Error **errp)
43
60
sysbus_connect_irq(sbd, 0,
44
#include "qemu/osdep.h"
61
qdev_get_gpio_in(DEVICE(s->cpu), ARM_CPU_IRQ));
45
#include "qemu/log.h"
62
46
+#include "qemu/bitops.h"
63
- memory_region_add_subregion(&s->container, 0xe000e000,
47
#include "qapi/error.h"
64
+ memory_region_add_subregion(&s->container, 0xe0000000,
48
#include "trace.h"
65
sysbus_mmio_get_region(sbd, 0));
49
#include "hw/sysbus.h"
66
50
@@ -XXX,XX +XXX,XX @@ struct ARMSSEInfo {
67
for (i = 0; i < ARRAY_SIZE(s->bitband); i++) {
51
int sram_banks;
68
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
52
int num_cpus;
53
uint32_t sys_version;
54
+ uint32_t cpuwait_rst;
55
SysConfigFormat sys_config_format;
56
bool has_mhus;
57
bool has_ppus;
58
@@ -XXX,XX +XXX,XX @@ static const ARMSSEInfo armsse_variants[] = {
59
.sram_banks = 1,
60
.num_cpus = 1,
61
.sys_version = 0x41743,
62
+ .cpuwait_rst = 0,
63
.sys_config_format = IoTKitFormat,
64
.has_mhus = false,
65
.has_ppus = false,
66
@@ -XXX,XX +XXX,XX @@ static const ARMSSEInfo armsse_variants[] = {
67
.sram_banks = 4,
68
.num_cpus = 2,
69
.sys_version = 0x22041743,
70
+ .cpuwait_rst = 2,
71
.sys_config_format = SSE200Format,
72
.has_mhus = true,
73
.has_ppus = true,
74
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
75
76
qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + 32);
77
/*
78
- * In real hardware the initial Secure VTOR is set from the INITSVTOR0
79
- * register in the IoT Kit System Control Register block, and the
80
- * initial value of that is in turn specifiable by the FPGA that
81
- * instantiates the IoT Kit. In QEMU we don't implement this wrinkle,
82
- * and simply set the CPU's init-svtor to the IoT Kit default value.
83
- * In SSE-200 the situation is similar, except that the default value
84
- * is a reset-time signal input. Typically a board using the SSE-200
85
- * will have a system control processor whose boot firmware initializes
86
- * the INITSVTOR* registers before powering up the CPUs in any case,
87
- * so the hardware's default value doesn't matter. QEMU doesn't emulate
88
+ * In real hardware the initial Secure VTOR is set from the INITSVTOR*
89
+ * registers in the IoT Kit System Control Register block. In QEMU
90
+ * we set the initial value here, and also the reset value of the
91
+ * sysctl register, from this object's QOM init-svtor property.
92
+ * If the guest changes the INITSVTOR* registers at runtime then the
93
+ * code in iotkit-sysctl.c will update the CPU init-svtor property
94
+ * (which will then take effect on the next CPU warm-reset).
95
+ *
96
+ * Note that typically a board using the SSE-200 will have a system
97
+ * control processor whose boot firmware initializes the INITSVTOR*
98
+ * registers before powering up the CPUs. QEMU doesn't emulate
99
* the control processor, so instead we behave in the way that the
100
- * firmware does. The initial value is configurable by the board code
101
- * to match whatever its firmware does.
102
+ * firmware does: the initial value should be set by the board code
103
+ * (using the init-svtor property on the ARMSSE object) to match
104
+ * whatever its firmware does.
105
*/
106
qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor);
107
/*
108
- * Start all CPUs except CPU0 powered down. In real hardware it is
109
- * a configurable property of the SSE-200 which CPUs start powered up
110
- * (via the CPUWAIT0_RST and CPUWAIT1_RST parameters), but since all
111
- * the boards we care about start CPU0 and leave CPU1 powered off,
112
- * we hard-code that for now. We can add QOM properties for this
113
+ * CPUs start powered down if the corresponding bit in the CPUWAIT
114
+ * register is 1. In real hardware the CPUWAIT register reset value is
115
+ * a configurable property of the SSE-200 (via the CPUWAIT0_RST and
116
+ * CPUWAIT1_RST parameters), but since all the boards we care about
117
+ * start CPU0 and leave CPU1 powered off, we hard-code that in
118
+ * info->cpuwait_rst for now. We can add QOM properties for this
119
* later if necessary.
120
*/
121
- if (i > 0) {
122
+ if (extract32(info->cpuwait_rst, i, 1)) {
123
object_property_set_bool(cpuobj, true, "start-powered-off", &err);
124
if (err) {
125
error_propagate(errp, err);
126
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
127
/* System control registers */
128
object_property_set_int(OBJECT(&s->sysctl), info->sys_version,
129
"SYS_VERSION", &err);
130
+ object_property_set_int(OBJECT(&s->sysctl), info->cpuwait_rst,
131
+ "CPUWAIT_RST", &err);
132
+ object_property_set_int(OBJECT(&s->sysctl), s->init_svtor,
133
+ "INITSVTOR0_RST", &err);
134
+ object_property_set_int(OBJECT(&s->sysctl), s->init_svtor,
135
+ "INITSVTOR1_RST", &err);
136
object_property_set_bool(OBJECT(&s->sysctl), true, "realized", &err);
137
if (err) {
138
error_propagate(errp, err);
139
diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
140
index XXXXXXX..XXXXXXX 100644
69
index XXXXXXX..XXXXXXX 100644
141
--- a/hw/misc/iotkit-sysctl.c
70
--- a/hw/intc/armv7m_nvic.c
142
+++ b/hw/misc/iotkit-sysctl.c
71
+++ b/hw/intc/armv7m_nvic.c
143
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_reset(DeviceState *dev)
72
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps nvic_systick_ops = {
144
s->reset_syndrome = 1;
73
.endianness = DEVICE_NATIVE_ENDIAN,
145
s->reset_mask = 0;
146
s->gretreg = 0;
147
- s->initsvtor0 = 0x10000000;
148
- s->initsvtor1 = 0x10000000;
149
- if (s->is_sse200) {
150
- /*
151
- * CPU 0 starts on, CPU 1 starts off. In real hardware this is
152
- * configurable by the SoC integrator as a verilog parameter.
153
- */
154
- s->cpuwait = 2;
155
- } else {
156
- /* CPU 0 starts on */
157
- s->cpuwait = 0;
158
- }
159
+ s->initsvtor0 = s->initsvtor0_rst;
160
+ s->initsvtor1 = s->initsvtor1_rst;
161
+ s->cpuwait = s->cpuwait_rst;
162
s->wicctrl = 0;
163
s->scsecctrl = 0;
164
s->fclk_div = 0;
165
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription iotkit_sysctl_vmstate = {
166
167
static Property iotkit_sysctl_props[] = {
168
DEFINE_PROP_UINT32("SYS_VERSION", IoTKitSysCtl, sys_version, 0),
169
+ DEFINE_PROP_UINT32("CPUWAIT_RST", IoTKitSysCtl, cpuwait_rst, 0),
170
+ DEFINE_PROP_UINT32("INITSVTOR0_RST", IoTKitSysCtl, initsvtor0_rst,
171
+ 0x10000000),
172
+ DEFINE_PROP_UINT32("INITSVTOR1_RST", IoTKitSysCtl, initsvtor1_rst,
173
+ 0x10000000),
174
DEFINE_PROP_END_OF_LIST()
175
};
74
};
75
76
+/*
77
+ * Unassigned portions of the PPB space are RAZ/WI for privileged
78
+ * accesses, and fault for non-privileged accesses.
79
+ */
80
+static MemTxResult ppb_default_read(void *opaque, hwaddr addr,
81
+ uint64_t *data, unsigned size,
82
+ MemTxAttrs attrs)
83
+{
84
+ qemu_log_mask(LOG_UNIMP, "Read of unassigned area of PPB: offset 0x%x\n",
85
+ (uint32_t)addr);
86
+ if (attrs.user) {
87
+ return MEMTX_ERROR;
88
+ }
89
+ *data = 0;
90
+ return MEMTX_OK;
91
+}
92
+
93
+static MemTxResult ppb_default_write(void *opaque, hwaddr addr,
94
+ uint64_t value, unsigned size,
95
+ MemTxAttrs attrs)
96
+{
97
+ qemu_log_mask(LOG_UNIMP, "Write of unassigned area of PPB: offset 0x%x\n",
98
+ (uint32_t)addr);
99
+ if (attrs.user) {
100
+ return MEMTX_ERROR;
101
+ }
102
+ return MEMTX_OK;
103
+}
104
+
105
+static const MemoryRegionOps ppb_default_ops = {
106
+ .read_with_attrs = ppb_default_read,
107
+ .write_with_attrs = ppb_default_write,
108
+ .endianness = DEVICE_NATIVE_ENDIAN,
109
+ .valid.min_access_size = 1,
110
+ .valid.max_access_size = 8,
111
+};
112
+
113
static int nvic_post_load(void *opaque, int version_id)
114
{
115
NVICState *s = opaque;
116
@@ -XXX,XX +XXX,XX @@ static void nvic_systick_trigger(void *opaque, int n, int level)
117
static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
118
{
119
NVICState *s = NVIC(dev);
120
- int regionlen;
121
122
/* The armv7m container object will have set our CPU pointer */
123
if (!s->cpu || !arm_feature(&s->cpu->env, ARM_FEATURE_M)) {
124
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
125
M_REG_S));
126
}
127
128
- /* The NVIC and System Control Space (SCS) starts at 0xe000e000
129
+ /*
130
+ * This device provides a single sysbus memory region which
131
+ * represents the whole of the "System PPB" space. This is the
132
+ * range from 0xe0000000 to 0xe00fffff and includes the NVIC,
133
+ * the System Control Space (system registers), the systick timer,
134
+ * and for CPUs with the Security extension an NS banked version
135
+ * of all of these.
136
+ *
137
+ * The default behaviour for unimplemented registers/ranges
138
+ * (for instance the Data Watchpoint and Trace unit at 0xe0001000)
139
+ * is to RAZ/WI for privileged access and BusFault for non-privileged
140
+ * access.
141
+ *
142
+ * The NVIC and System Control Space (SCS) starts at 0xe000e000
143
* and looks like this:
144
* 0x004 - ICTR
145
* 0x010 - 0xff - systick
146
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
147
* generally code determining which banked register to use should
148
* use attrs.secure; code determining actual behaviour of the system
149
* should use env->v7m.secure.
150
+ *
151
+ * The container covers the whole PPB space. Within it the priority
152
+ * of overlapping regions is:
153
+ * - default region (for RAZ/WI and BusFault) : -1
154
+ * - system register regions : 0
155
+ * - systick : 1
156
+ * This is because the systick device is a small block of registers
157
+ * in the middle of the other system control registers.
158
*/
159
- regionlen = arm_feature(&s->cpu->env, ARM_FEATURE_V8) ? 0x21000 : 0x1000;
160
- memory_region_init(&s->container, OBJECT(s), "nvic", regionlen);
161
- /* The system register region goes at the bottom of the priority
162
- * stack as it covers the whole page.
163
- */
164
+ memory_region_init(&s->container, OBJECT(s), "nvic", 0x100000);
165
+ memory_region_init_io(&s->defaultmem, OBJECT(s), &ppb_default_ops, s,
166
+ "nvic-default", 0x100000);
167
+ memory_region_add_subregion_overlap(&s->container, 0, &s->defaultmem, -1);
168
memory_region_init_io(&s->sysregmem, OBJECT(s), &nvic_sysreg_ops, s,
169
"nvic_sysregs", 0x1000);
170
- memory_region_add_subregion(&s->container, 0, &s->sysregmem);
171
+ memory_region_add_subregion(&s->container, 0xe000, &s->sysregmem);
172
173
memory_region_init_io(&s->systickmem, OBJECT(s),
174
&nvic_systick_ops, s,
175
"nvic_systick", 0xe0);
176
177
- memory_region_add_subregion_overlap(&s->container, 0x10,
178
+ memory_region_add_subregion_overlap(&s->container, 0xe010,
179
&s->systickmem, 1);
180
181
if (arm_feature(&s->cpu->env, ARM_FEATURE_V8)) {
182
memory_region_init_io(&s->sysreg_ns_mem, OBJECT(s),
183
&nvic_sysreg_ns_ops, &s->sysregmem,
184
"nvic_sysregs_ns", 0x1000);
185
- memory_region_add_subregion(&s->container, 0x20000, &s->sysreg_ns_mem);
186
+ memory_region_add_subregion(&s->container, 0x2e000, &s->sysreg_ns_mem);
187
memory_region_init_io(&s->systick_ns_mem, OBJECT(s),
188
&nvic_sysreg_ns_ops, &s->systickmem,
189
"nvic_systick_ns", 0xe0);
190
- memory_region_add_subregion_overlap(&s->container, 0x20010,
191
+ memory_region_add_subregion_overlap(&s->container, 0x2e010,
192
&s->systick_ns_mem, 1);
193
}
176
194
177
--
195
--
178
2.20.1
196
2.20.1
179
197
180
198
diff view generated by jsdifflib
New patch
[PULL 13/36] target/arm: Implement v8.1M PXN extension
1
In v8.1M the PXN architecture extension adds a new PXN bit to the
2
MPU_RLAR registers, which forbids execution of code in the region
3
from a privileged mode.
1
4
5
This is another feature which is just in the generic "in v8.1M" set
6
and has no ID register field indicating its presence.
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20201119215617.29887-3-peter.maydell@linaro.org
11
---
12
target/arm/helper.c | 7 ++++++-
13
1 file changed, 6 insertions(+), 1 deletion(-)
14
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper.c
18
+++ b/target/arm/helper.c
19
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
20
} else {
21
uint32_t ap = extract32(env->pmsav8.rbar[secure][matchregion], 1, 2);
22
uint32_t xn = extract32(env->pmsav8.rbar[secure][matchregion], 0, 1);
23
+ bool pxn = false;
24
+
25
+ if (arm_feature(env, ARM_FEATURE_V8_1M)) {
26
+ pxn = extract32(env->pmsav8.rlar[secure][matchregion], 4, 1);
27
+ }
28
29
if (m_is_system_region(env, address)) {
30
/* System space is always execute never */
31
@@ -XXX,XX +XXX,XX @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address,
32
}
33
34
*prot = simple_ap_to_rw_prot(env, mmu_idx, ap);
35
- if (*prot && !xn) {
36
+ if (*prot && !xn && !(pxn && !is_user)) {
37
*prot |= PAGE_EXEC;
38
}
39
/* We don't need to look the attribute up in the MAIR0/MAIR1
40
--
41
2.20.1
42
43
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/16] target/arm/cpu: Allow init-svtor property to be set after realize
[PULL 14/36] target/arm: Don't clobber ID_PFR1.Security on M-profile cores
1
Make the M-profile "init-svtor" property be settable after realize.
1
In arm_cpu_realizefn() we check whether the board code disabled EL3
2
This matches the hardware, where this is a config signal which
2
via the has_el3 CPU object property, which we create if the CPU
3
is sampled on CPU reset and can thus be changed between one
3
starts with the ARM_FEATURE_EL3 feature bit. If it is disabled, then
4
reset and another. To do this we have to change the API we
4
we turn off ARM_FEATURE_EL3 and also zero out the relevant fields in
5
use to add the property.
5
the ID_PFR1 and ID_AA64PFR0 registers.
6
6
7
(We will need this capability for the SSE-200.)
7
This codepath was incorrectly being taken for M-profile CPUs, which
8
do not have an EL3 and don't set ARM_FEATURE_EL3, but which may have
9
the M-profile Security extension and so should have non-zero values
10
in the ID_PFR1.Security field.
11
12
Restrict the handling of the feature flag to A/R-profile cores.
8
13
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20190219125808.25174-4-peter.maydell@linaro.org
16
Message-id: 20201119215617.29887-4-peter.maydell@linaro.org
12
---
17
---
13
target/arm/cpu.c | 29 ++++++++++++++++++++++++-----
18
target/arm/cpu.c | 2 +-
14
1 file changed, 24 insertions(+), 5 deletions(-)
19
1 file changed, 1 insertion(+), 1 deletion(-)
15
20
16
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
21
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
17
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.c
23
--- a/target/arm/cpu.c
19
+++ b/target/arm/cpu.c
24
+++ b/target/arm/cpu.c
20
@@ -XXX,XX +XXX,XX @@
25
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
21
#include "target/arm/idau.h"
26
}
22
#include "qemu/error-report.h"
23
#include "qapi/error.h"
24
+#include "qapi/visitor.h"
25
#include "cpu.h"
26
#include "internals.h"
27
#include "qemu-common.h"
28
@@ -XXX,XX +XXX,XX @@ static Property arm_cpu_pmsav7_dregion_property =
29
pmsav7_dregion,
30
qdev_prop_uint32, uint32_t);
31
32
-/* M profile: initial value of the Secure VTOR */
33
-static Property arm_cpu_initsvtor_property =
34
- DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0);
35
+static void arm_get_init_svtor(Object *obj, Visitor *v, const char *name,
36
+ void *opaque, Error **errp)
37
+{
38
+ ARMCPU *cpu = ARM_CPU(obj);
39
+
40
+ visit_type_uint32(v, name, &cpu->init_svtor, errp);
41
+}
42
+
43
+static void arm_set_init_svtor(Object *obj, Visitor *v, const char *name,
44
+ void *opaque, Error **errp)
45
+{
46
+ ARMCPU *cpu = ARM_CPU(obj);
47
+
48
+ visit_type_uint32(v, name, &cpu->init_svtor, errp);
49
+}
50
51
void arm_cpu_post_init(Object *obj)
52
{
53
@@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj)
54
qdev_prop_allow_set_link_before_realize,
55
OBJ_PROP_LINK_STRONG,
56
&error_abort);
57
- qdev_property_add_static(DEVICE(obj), &arm_cpu_initsvtor_property,
58
- &error_abort);
59
+ /*
60
+ * M profile: initial value of the Secure VTOR. We can't just use
61
+ * a simple DEFINE_PROP_UINT32 for this because we want to permit
62
+ * the property to be set after realize.
63
+ */
64
+ object_property_add(obj, "init-svtor", "uint32",
65
+ arm_get_init_svtor, arm_set_init_svtor,
66
+ NULL, NULL, &error_abort);
67
}
27
}
68
28
69
qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
29
- if (!cpu->has_el3) {
30
+ if (!arm_feature(env, ARM_FEATURE_M) && !cpu->has_el3) {
31
/* If the has_el3 CPU property is disabled then we need to disable the
32
* feature.
33
*/
70
--
34
--
71
2.20.1
35
2.20.1
72
36
73
37
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/16] target/arm: Implement VFMAL and VFMSL for aarch32
[PULL 15/36] target/arm: Implement VSCCLRM insn
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Implement the v8.1M VSCCLRM insn, which zeros floating point
2
2
registers if there is an active floating point context.
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
This requires support in write_neon_element32() for the MO_32
4
Message-id: 20190219222952.22183-4-richard.henderson@linaro.org
4
element size, so add it.
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
6
Because we want to use arm_gen_condlabel(), we need to move
7
the definition of that function up in translate.c so it is
8
before the #include of translate-vfp.c.inc.
9
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20201119215617.29887-5-peter.maydell@linaro.org
7
---
13
---
8
target/arm/cpu.h | 5 ++
14
target/arm/cpu.h | 9 ++++
9
target/arm/translate.c | 129 ++++++++++++++++++++++++++++++-----------
15
target/arm/m-nocp.decode | 8 +++-
10
2 files changed, 101 insertions(+), 33 deletions(-)
16
target/arm/translate.c | 21 +++++----
17
target/arm/translate-vfp.c.inc | 84 ++++++++++++++++++++++++++++++++++
18
4 files changed, 111 insertions(+), 11 deletions(-)
11
19
12
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
20
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
13
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/cpu.h
22
--- a/target/arm/cpu.h
15
+++ b/target/arm/cpu.h
23
+++ b/target/arm/cpu.h
16
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
24
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
17
return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
25
return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
18
}
26
}
19
27
20
+static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)
28
+static inline bool isar_feature_aa32_m_sec_state(const ARMISARegisters *id)
21
+{
29
+{
22
+ return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
30
+ /*
31
+ * Return true if M-profile state handling insns
32
+ * (VSCCLRM, CLRM, FPCTX access insns) are implemented
33
+ */
34
+ return FIELD_EX32(id->id_pfr1, ID_PFR1, SECURITY) >= 3;
23
+}
35
+}
24
+
36
+
25
static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
37
static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
26
{
38
{
27
/*
39
/* Sadly this is encoded differently for A-profile and M-profile */
40
diff --git a/target/arm/m-nocp.decode b/target/arm/m-nocp.decode
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/m-nocp.decode
43
+++ b/target/arm/m-nocp.decode
44
@@ -XXX,XX +XXX,XX @@
45
# If the coprocessor is not present or disabled then we will generate
46
# the NOCP exception; otherwise we let the insn through to the main decode.
47
48
+%vd_dp 22:1 12:4
49
+%vd_sp 12:4 22:1
50
+
51
&nocp cp
52
53
{
54
# Special cases which do not take an early NOCP: VLLDM and VLSTM
55
VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000
56
- # TODO: VSCCLRM (new in v8.1M) is similar:
57
- #VSCCLRM 1110 1100 1-01 1111 ---- 1011 ---- ---0
58
+ # VSCCLRM (new in v8.1M) is similar:
59
+ VSCCLRM 1110 1100 1.01 1111 .... 1011 imm:7 0 vd=%vd_dp size=3
60
+ VSCCLRM 1110 1100 1.01 1111 .... 1010 imm:8 vd=%vd_sp size=2
61
62
NOCP 111- 1110 ---- ---- ---- cp:4 ---- ---- &nocp
63
NOCP 111- 110- ---- ---- ---- cp:4 ---- ---- &nocp
28
diff --git a/target/arm/translate.c b/target/arm/translate.c
64
diff --git a/target/arm/translate.c b/target/arm/translate.c
29
index XXXXXXX..XXXXXXX 100644
65
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/translate.c
66
--- a/target/arm/translate.c
31
+++ b/target/arm/translate.c
67
+++ b/target/arm/translate.c
32
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
68
@@ -XXX,XX +XXX,XX @@ void arm_translate_init(void)
33
gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL;
69
a64_translate_init();
34
int rd, rn, rm, opr_sz;
70
}
35
int data = 0;
71
36
- bool q;
72
+/* Generate a label used for skipping this instruction */
73
+static void arm_gen_condlabel(DisasContext *s)
74
+{
75
+ if (!s->condjmp) {
76
+ s->condlabel = gen_new_label();
77
+ s->condjmp = 1;
78
+ }
79
+}
80
+
81
/* Flags for the disas_set_da_iss info argument:
82
* lower bits hold the Rt register number, higher bits are flags.
83
*/
84
@@ -XXX,XX +XXX,XX @@ static void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop)
85
long off = neon_element_offset(reg, ele, memop);
86
87
switch (memop) {
88
+ case MO_32:
89
+ tcg_gen_st32_i64(src, cpu_env, off);
90
+ break;
91
case MO_64:
92
tcg_gen_st_i64(src, cpu_env, off);
93
break;
94
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
95
s->base.is_jmp = DISAS_UPDATE_EXIT;
96
}
97
98
-/* Generate a label used for skipping this instruction */
99
-static void arm_gen_condlabel(DisasContext *s)
100
-{
101
- if (!s->condjmp) {
102
- s->condlabel = gen_new_label();
103
- s->condjmp = 1;
104
- }
105
-}
37
-
106
-
38
- q = extract32(insn, 6, 1);
107
/* Skip this instruction if the ARM condition is false */
39
- VFP_DREG_D(rd, insn);
108
static void arm_skip_unless(DisasContext *s, uint32_t cond)
40
- VFP_DREG_N(rn, insn);
109
{
41
- VFP_DREG_M(rm, insn);
110
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
42
- if ((rd | rn | rm) & q) {
111
index XXXXXXX..XXXXXXX 100644
43
- return 1;
112
--- a/target/arm/translate-vfp.c.inc
44
- }
113
+++ b/target/arm/translate-vfp.c.inc
45
+ int off_rn, off_rm;
114
@@ -XXX,XX +XXX,XX @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
46
+ bool is_long = false, q = extract32(insn, 6, 1);
115
return true;
47
+ bool ptr_is_env = false;
116
}
48
117
49
if ((insn & 0xfe200f10) == 0xfc200800) {
118
+static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a)
50
/* VCMLA -- 1111 110R R.1S .... .... 1000 ...0 .... */
119
+{
51
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
120
+ int btmreg, topreg;
52
return 1;
121
+ TCGv_i64 zero;
53
}
122
+ TCGv_i32 aspen, sfpa;
54
fn_gvec = u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b;
123
+
55
+ } else if ((insn & 0xff300f10) == 0xfc200810) {
124
+ if (!dc_isar_feature(aa32_m_sec_state, s)) {
56
+ /* VFM[AS]L -- 1111 1100 S.10 .... .... 1000 .Q.1 .... */
125
+ /* Before v8.1M, fall through in decode to NOCP check */
57
+ int is_s = extract32(insn, 23, 1);
126
+ return false;
58
+ if (!dc_isar_feature(aa32_fhm, s)) {
127
+ }
59
+ return 1;
128
+
60
+ }
129
+ /* Explicitly UNDEF because this takes precedence over NOCP */
61
+ is_long = true;
130
+ if (!arm_dc_feature(s, ARM_FEATURE_M_MAIN) || !s->v8m_secure) {
62
+ data = is_s; /* is_2 == 0 */
131
+ unallocated_encoding(s);
63
+ fn_gvec_ptr = gen_helper_gvec_fmlal_a32;
132
+ return true;
64
+ ptr_is_env = true;
133
+ }
65
} else {
134
+
66
return 1;
135
+ if (!dc_isar_feature(aa32_vfp_simd, s)) {
67
}
136
+ /* NOP if we have neither FP nor MVE */
68
137
+ return true;
69
+ VFP_DREG_D(rd, insn);
138
+ }
70
+ if (rd & q) {
139
+
71
+ return 1;
140
+ /*
72
+ }
141
+ * If FPCCR.ASPEN != 0 && CONTROL_S.SFPA == 0 then there is no
73
+ if (q || !is_long) {
142
+ * active floating point context so we must NOP (without doing
74
+ VFP_DREG_N(rn, insn);
143
+ * any lazy state preservation or the NOCP check).
75
+ VFP_DREG_M(rm, insn);
144
+ */
76
+ if ((rn | rm) & q & !is_long) {
145
+ aspen = load_cpu_field(v7m.fpccr[M_REG_S]);
77
+ return 1;
146
+ sfpa = load_cpu_field(v7m.control[M_REG_S]);
78
+ }
147
+ tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
79
+ off_rn = vfp_reg_offset(1, rn);
148
+ tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
80
+ off_rm = vfp_reg_offset(1, rm);
149
+ tcg_gen_andi_i32(sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK);
81
+ } else {
150
+ tcg_gen_or_i32(sfpa, sfpa, aspen);
82
+ rn = VFP_SREG_N(insn);
151
+ arm_gen_condlabel(s);
83
+ rm = VFP_SREG_M(insn);
152
+ tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel);
84
+ off_rn = vfp_reg_offset(0, rn);
153
+
85
+ off_rm = vfp_reg_offset(0, rm);
154
+ if (s->fp_excp_el != 0) {
86
+ }
155
+ gen_exception_insn(s, s->pc_curr, EXCP_NOCP,
87
+
156
+ syn_uncategorized(), s->fp_excp_el);
88
if (s->fp_excp_el) {
157
+ return true;
89
gen_exception_insn(s, 4, EXCP_UDEF,
158
+ }
90
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
159
+
91
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
160
+ topreg = a->vd + a->imm - 1;
92
161
+ btmreg = a->vd;
93
opr_sz = (1 + q) * 8;
162
+
94
if (fn_gvec_ptr) {
163
+ /* Convert to Sreg numbers if the insn specified in Dregs */
95
- TCGv_ptr fpst = get_fpstatus_ptr(1);
164
+ if (a->size == 3) {
96
- tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd),
165
+ topreg = topreg * 2 + 1;
97
- vfp_reg_offset(1, rn),
166
+ btmreg *= 2;
98
- vfp_reg_offset(1, rm), fpst,
167
+ }
99
+ TCGv_ptr ptr;
168
+
100
+ if (ptr_is_env) {
169
+ if (topreg > 63 || (topreg > 31 && !(topreg & 1))) {
101
+ ptr = cpu_env;
170
+ /* UNPREDICTABLE: we choose to undef */
102
+ } else {
171
+ unallocated_encoding(s);
103
+ ptr = get_fpstatus_ptr(1);
172
+ return true;
104
+ }
173
+ }
105
+ tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr,
174
+
106
opr_sz, opr_sz, data, fn_gvec_ptr);
175
+ /* Silently ignore requests to clear D16-D31 if they don't exist */
107
- tcg_temp_free_ptr(fpst);
176
+ if (topreg > 31 && !dc_isar_feature(aa32_simd_r32, s)) {
108
+ if (!ptr_is_env) {
177
+ topreg = 31;
109
+ tcg_temp_free_ptr(ptr);
178
+ }
110
+ }
179
+
111
} else {
180
+ if (!vfp_access_check(s)) {
112
- tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd),
181
+ return true;
113
- vfp_reg_offset(1, rn),
182
+ }
114
- vfp_reg_offset(1, rm),
183
+
115
+ tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm,
184
+ /* Zero the Sregs from btmreg to topreg inclusive. */
116
opr_sz, opr_sz, data, fn_gvec);
185
+ zero = tcg_const_i64(0);
117
}
186
+ if (btmreg & 1) {
118
return 0;
187
+ write_neon_element64(zero, btmreg >> 1, 1, MO_32);
119
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
188
+ btmreg++;
120
gen_helper_gvec_3 *fn_gvec = NULL;
189
+ }
121
gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL;
190
+ for (; btmreg + 1 <= topreg; btmreg += 2) {
122
int rd, rn, rm, opr_sz, data;
191
+ write_neon_element64(zero, btmreg >> 1, 0, MO_64);
123
- bool q;
192
+ }
124
-
193
+ if (btmreg == topreg) {
125
- q = extract32(insn, 6, 1);
194
+ write_neon_element64(zero, btmreg >> 1, 0, MO_32);
126
- VFP_DREG_D(rd, insn);
195
+ btmreg++;
127
- VFP_DREG_N(rn, insn);
196
+ }
128
- if ((rd | rn) & q) {
197
+ assert(btmreg == topreg + 1);
129
- return 1;
198
+ /* TODO: when MVE is implemented, zero VPR here */
130
- }
199
+ return true;
131
+ int off_rn, off_rm;
200
+}
132
+ bool is_long = false, q = extract32(insn, 6, 1);
201
+
133
+ bool ptr_is_env = false;
202
static bool trans_NOCP(DisasContext *s, arg_nocp *a)
134
203
{
135
if ((insn & 0xff000f10) == 0xfe000800) {
204
/*
136
/* VCMLA (indexed) -- 1111 1110 S.RR .... .... 1000 ...0 .... */
137
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
138
} else if ((insn & 0xffb00f00) == 0xfe200d00) {
139
/* V[US]DOT -- 1111 1110 0.10 .... .... 1101 .Q.U .... */
140
int u = extract32(insn, 4, 1);
141
+
142
if (!dc_isar_feature(aa32_dp, s)) {
143
return 1;
144
}
145
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
146
/* rm is just Vm, and index is M. */
147
data = extract32(insn, 5, 1); /* index */
148
rm = extract32(insn, 0, 4);
149
+ } else if ((insn & 0xffa00f10) == 0xfe000810) {
150
+ /* VFM[AS]L -- 1111 1110 0.0S .... .... 1000 .Q.1 .... */
151
+ int is_s = extract32(insn, 20, 1);
152
+ int vm20 = extract32(insn, 0, 3);
153
+ int vm3 = extract32(insn, 3, 1);
154
+ int m = extract32(insn, 5, 1);
155
+ int index;
156
+
157
+ if (!dc_isar_feature(aa32_fhm, s)) {
158
+ return 1;
159
+ }
160
+ if (q) {
161
+ rm = vm20;
162
+ index = m * 2 + vm3;
163
+ } else {
164
+ rm = vm20 * 2 + m;
165
+ index = vm3;
166
+ }
167
+ is_long = true;
168
+ data = (index << 2) | is_s; /* is_2 == 0 */
169
+ fn_gvec_ptr = gen_helper_gvec_fmlal_idx_a32;
170
+ ptr_is_env = true;
171
} else {
172
return 1;
173
}
174
175
+ VFP_DREG_D(rd, insn);
176
+ if (rd & q) {
177
+ return 1;
178
+ }
179
+ if (q || !is_long) {
180
+ VFP_DREG_N(rn, insn);
181
+ if (rn & q & !is_long) {
182
+ return 1;
183
+ }
184
+ off_rn = vfp_reg_offset(1, rn);
185
+ off_rm = vfp_reg_offset(1, rm);
186
+ } else {
187
+ rn = VFP_SREG_N(insn);
188
+ off_rn = vfp_reg_offset(0, rn);
189
+ off_rm = vfp_reg_offset(0, rm);
190
+ }
191
if (s->fp_excp_el) {
192
gen_exception_insn(s, 4, EXCP_UDEF,
193
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
194
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
195
196
opr_sz = (1 + q) * 8;
197
if (fn_gvec_ptr) {
198
- TCGv_ptr fpst = get_fpstatus_ptr(1);
199
- tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd),
200
- vfp_reg_offset(1, rn),
201
- vfp_reg_offset(1, rm), fpst,
202
+ TCGv_ptr ptr;
203
+ if (ptr_is_env) {
204
+ ptr = cpu_env;
205
+ } else {
206
+ ptr = get_fpstatus_ptr(1);
207
+ }
208
+ tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr,
209
opr_sz, opr_sz, data, fn_gvec_ptr);
210
- tcg_temp_free_ptr(fpst);
211
+ if (!ptr_is_env) {
212
+ tcg_temp_free_ptr(ptr);
213
+ }
214
} else {
215
- tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd),
216
- vfp_reg_offset(1, rn),
217
- vfp_reg_offset(1, rm),
218
+ tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm,
219
opr_sz, opr_sz, data, fn_gvec);
220
}
221
return 0;
222
--
205
--
223
2.20.1
206
2.20.1
224
207
225
208
diff view generated by jsdifflib
New patch
[PULL 16/36] target/arm: Implement CLRM instruction
1
In v8.1M the new CLRM instruction allows zeroing an arbitrary set of
2
the general-purpose registers and APSR. Implement this.
1
3
4
The encoding is a subset of the LDMIA T2 encoding, using what would
5
be Rn=0b1111 (which UNDEFs for LDMIA).
6
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20201119215617.29887-6-peter.maydell@linaro.org
10
---
11
target/arm/t32.decode | 6 +++++-
12
target/arm/translate.c | 38 ++++++++++++++++++++++++++++++++++++++
13
2 files changed, 43 insertions(+), 1 deletion(-)
14
15
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/t32.decode
18
+++ b/target/arm/t32.decode
19
@@ -XXX,XX +XXX,XX @@ UXTAB 1111 1010 0101 .... 1111 .... 10.. .... @rrr_rot
20
21
STM_t32 1110 1000 10.0 .... ................ @ldstm i=1 b=0
22
STM_t32 1110 1001 00.0 .... ................ @ldstm i=0 b=1
23
-LDM_t32 1110 1000 10.1 .... ................ @ldstm i=1 b=0
24
+{
25
+ # Rn=15 UNDEFs for LDM; M-profile CLRM uses that encoding
26
+ CLRM 1110 1000 1001 1111 list:16
27
+ LDM_t32 1110 1000 10.1 .... ................ @ldstm i=1 b=0
28
+}
29
LDM_t32 1110 1001 00.1 .... ................ @ldstm i=0 b=1
30
31
&rfe !extern rn w pu
32
diff --git a/target/arm/translate.c b/target/arm/translate.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/translate.c
35
+++ b/target/arm/translate.c
36
@@ -XXX,XX +XXX,XX @@ static bool trans_LDM_t16(DisasContext *s, arg_ldst_block *a)
37
return do_ldm(s, a, 1);
38
}
39
40
+static bool trans_CLRM(DisasContext *s, arg_CLRM *a)
41
+{
42
+ int i;
43
+ TCGv_i32 zero;
44
+
45
+ if (!dc_isar_feature(aa32_m_sec_state, s)) {
46
+ return false;
47
+ }
48
+
49
+ if (extract32(a->list, 13, 1)) {
50
+ return false;
51
+ }
52
+
53
+ if (!a->list) {
54
+ /* UNPREDICTABLE; we choose to UNDEF */
55
+ return false;
56
+ }
57
+
58
+ zero = tcg_const_i32(0);
59
+ for (i = 0; i < 15; i++) {
60
+ if (extract32(a->list, i, 1)) {
61
+ /* Clear R[i] */
62
+ tcg_gen_mov_i32(cpu_R[i], zero);
63
+ }
64
+ }
65
+ if (extract32(a->list, 15, 1)) {
66
+ /*
67
+ * Clear APSR (by calling the MSR helper with the same argument
68
+ * as for "MSR APSR_nzcvqg, Rn": mask = 0b1100, SYSM=0)
69
+ */
70
+ TCGv_i32 maskreg = tcg_const_i32(0xc << 8);
71
+ gen_helper_v7m_msr(cpu_env, maskreg, zero);
72
+ tcg_temp_free_i32(maskreg);
73
+ }
74
+ tcg_temp_free_i32(zero);
75
+ return true;
76
+}
77
+
78
/*
79
* Branch, branch with link
80
*/
81
--
82
2.20.1
83
84
diff view generated by jsdifflib
New patch
[PULL 17/36] target/arm: Enforce M-profile VMRS/VMSR register restrictions
1
For M-profile before v8.1M, the only valid register for VMSR/VMRS is
2
the FPSCR. We have a comment that states this, but the actual logic
3
to forbid accesses for any other register value is missing, so we
4
would end up with A-profile style behaviour. Add the missing check.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20201119215617.29887-7-peter.maydell@linaro.org
9
---
10
target/arm/translate-vfp.c.inc | 5 ++++-
11
1 file changed, 4 insertions(+), 1 deletion(-)
12
13
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-vfp.c.inc
16
+++ b/target/arm/translate-vfp.c.inc
17
@@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
18
* Accesses to R15 are UNPREDICTABLE; we choose to undef.
19
* (FPSCR -> r15 is a special case which writes to the PSR flags.)
20
*/
21
- if (a->rt == 15 && (!a->l || a->reg != ARM_VFP_FPSCR)) {
22
+ if (a->reg != ARM_VFP_FPSCR) {
23
+ return false;
24
+ }
25
+ if (a->rt == 15 && !a->l) {
26
return false;
27
}
28
}
29
--
30
2.20.1
31
32
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/16] target/arm: Gate "miscellaneous FP" insns by ID register field
[PULL 18/36] target/arm: Refactor M-profile VMSR/VMRS handling
1
There is a set of VFP instructions which we implement in
1
Currently M-profile borrows the A-profile code for VMSR and VMRS
2
disas_vfp_v8_insn() and gate on the ARM_FEATURE_V8 bit.
2
(access to the FP system registers), because all it needs to support
3
These were all first introduced in v8 for A-profile, but in
3
is the FPSCR. In v8.1M things become significantly more complicated
4
M-profile they appeared in v7M. Gate them on the MVFR2
4
in two ways:
5
FPMisc field instead, and rename the function appropriately.
5
6
* there are several new FP system registers; some have side effects
7
on read, and one (FPCXT_NS) needs to avoid the usual
8
vfp_access_check() and the "only if FPU implemented" check
9
10
* all sysregs are now accessible both by VMRS/VMSR (which
11
reads/writes a general purpose register) and also by VLDR/VSTR
12
(which reads/writes them directly to memory)
13
14
Refactor the structure of how we handle VMSR/VMRS to cope with this:
15
16
* keep the M-profile code entirely separate from the A-profile code
17
18
* abstract out the "read or write the general purpose register" part
19
of the code into a loadfn or storefn function pointer, so we can
20
reuse it for VLDR/VSTR.
6
21
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
23
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20190222170936.13268-3-peter.maydell@linaro.org
24
Message-id: 20201119215617.29887-8-peter.maydell@linaro.org
10
---
25
---
11
target/arm/cpu.h | 20 ++++++++++++++++++++
26
target/arm/cpu.h | 3 +
12
target/arm/translate.c | 25 +++++++++++++------------
27
target/arm/translate-vfp.c.inc | 182 ++++++++++++++++++++++++++++++---
13
2 files changed, 33 insertions(+), 12 deletions(-)
28
2 files changed, 171 insertions(+), 14 deletions(-)
14
29
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
30
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu.h
32
--- a/target/arm/cpu.h
18
+++ b/target/arm/cpu.h
33
+++ b/target/arm/cpu.h
19
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
34
@@ -XXX,XX +XXX,XX @@ enum arm_cpu_mode {
20
return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1;
35
#define ARM_VFP_FPINST 9
36
#define ARM_VFP_FPINST2 10
37
38
+/* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */
39
+#define QEMU_VFP_FPSCR_NZCV 0xffff
40
+
41
/* iwMMXt coprocessor control registers. */
42
#define ARM_IWMMXT_wCID 0
43
#define ARM_IWMMXT_wCon 1
44
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/translate-vfp.c.inc
47
+++ b/target/arm/translate-vfp.c.inc
48
@@ -XXX,XX +XXX,XX @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a)
49
return true;
21
}
50
}
22
51
23
+static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
52
+/*
24
+{
53
+ * M-profile provides two different sets of instructions that can
25
+ return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 1;
54
+ * access floating point system registers: VMSR/VMRS (which move
26
+}
55
+ * to/from a general purpose register) and VLDR/VSTR sysreg (which
27
+
56
+ * move directly to/from memory). In some cases there are also side
28
+static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id)
57
+ * effects which must happen after any write to memory (which could
29
+{
58
+ * cause an exception). So we implement the common logic for the
30
+ return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 2;
59
+ * sysreg access in gen_M_fp_sysreg_write() and gen_M_fp_sysreg_read(),
31
+}
60
+ * which take pointers to callback functions which will perform the
32
+
61
+ * actual "read/write general purpose register" and "read/write
33
+static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id)
62
+ * memory" operations.
34
+{
63
+ */
35
+ return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 3;
64
+
36
+}
65
+/*
37
+
66
+ * Emit code to store the sysreg to its final destination; frees the
38
+static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
67
+ * TCG temp 'value' it is passed.
39
+{
68
+ */
40
+ return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4;
69
+typedef void fp_sysreg_storefn(DisasContext *s, void *opaque, TCGv_i32 value);
41
+}
70
+/*
42
+
71
+ * Emit code to load the value to be copied to the sysreg; returns
43
/*
72
+ * a new TCG temporary
44
* 64-bit feature tests via id registers.
73
+ */
45
*/
74
+typedef TCGv_i32 fp_sysreg_loadfn(DisasContext *s, void *opaque);
46
diff --git a/target/arm/translate.c b/target/arm/translate.c
75
+
47
index XXXXXXX..XXXXXXX 100644
76
+/* Common decode/access checks for fp sysreg read/write */
48
--- a/target/arm/translate.c
77
+typedef enum FPSysRegCheckResult {
49
+++ b/target/arm/translate.c
78
+ FPSysRegCheckFailed, /* caller should return false */
50
@@ -XXX,XX +XXX,XX @@ static const uint8_t fp_decode_rm[] = {
79
+ FPSysRegCheckDone, /* caller should return true */
51
FPROUNDING_NEGINF,
80
+ FPSysRegCheckContinue, /* caller should continue generating code */
52
};
81
+} FPSysRegCheckResult;
53
82
+
54
-static int disas_vfp_v8_insn(DisasContext *s, uint32_t insn)
83
+static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno)
55
+static int disas_vfp_misc_insn(DisasContext *s, uint32_t insn)
84
+{
85
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
86
+ return FPSysRegCheckFailed;
87
+ }
88
+
89
+ switch (regno) {
90
+ case ARM_VFP_FPSCR:
91
+ case QEMU_VFP_FPSCR_NZCV:
92
+ break;
93
+ default:
94
+ return FPSysRegCheckFailed;
95
+ }
96
+
97
+ if (!vfp_access_check(s)) {
98
+ return FPSysRegCheckDone;
99
+ }
100
+
101
+ return FPSysRegCheckContinue;
102
+}
103
+
104
+static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
105
+
106
+ fp_sysreg_loadfn *loadfn,
107
+ void *opaque)
108
+{
109
+ /* Do a write to an M-profile floating point system register */
110
+ TCGv_i32 tmp;
111
+
112
+ switch (fp_sysreg_checks(s, regno)) {
113
+ case FPSysRegCheckFailed:
114
+ return false;
115
+ case FPSysRegCheckDone:
116
+ return true;
117
+ case FPSysRegCheckContinue:
118
+ break;
119
+ }
120
+
121
+ switch (regno) {
122
+ case ARM_VFP_FPSCR:
123
+ tmp = loadfn(s, opaque);
124
+ gen_helper_vfp_set_fpscr(cpu_env, tmp);
125
+ tcg_temp_free_i32(tmp);
126
+ gen_lookup_tb(s);
127
+ break;
128
+ default:
129
+ g_assert_not_reached();
130
+ }
131
+ return true;
132
+}
133
+
134
+static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
135
+ fp_sysreg_storefn *storefn,
136
+ void *opaque)
137
+{
138
+ /* Do a read from an M-profile floating point system register */
139
+ TCGv_i32 tmp;
140
+
141
+ switch (fp_sysreg_checks(s, regno)) {
142
+ case FPSysRegCheckFailed:
143
+ return false;
144
+ case FPSysRegCheckDone:
145
+ return true;
146
+ case FPSysRegCheckContinue:
147
+ break;
148
+ }
149
+
150
+ switch (regno) {
151
+ case ARM_VFP_FPSCR:
152
+ tmp = tcg_temp_new_i32();
153
+ gen_helper_vfp_get_fpscr(tmp, cpu_env);
154
+ storefn(s, opaque, tmp);
155
+ break;
156
+ case QEMU_VFP_FPSCR_NZCV:
157
+ /*
158
+ * Read just NZCV; this is a special case to avoid the
159
+ * helper call for the "VMRS to CPSR.NZCV" insn.
160
+ */
161
+ tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
162
+ tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
163
+ storefn(s, opaque, tmp);
164
+ break;
165
+ default:
166
+ g_assert_not_reached();
167
+ }
168
+ return true;
169
+}
170
+
171
+static void fp_sysreg_to_gpr(DisasContext *s, void *opaque, TCGv_i32 value)
172
+{
173
+ arg_VMSR_VMRS *a = opaque;
174
+
175
+ if (a->rt == 15) {
176
+ /* Set the 4 flag bits in the CPSR */
177
+ gen_set_nzcv(value);
178
+ tcg_temp_free_i32(value);
179
+ } else {
180
+ store_reg(s, a->rt, value);
181
+ }
182
+}
183
+
184
+static TCGv_i32 gpr_to_fp_sysreg(DisasContext *s, void *opaque)
185
+{
186
+ arg_VMSR_VMRS *a = opaque;
187
+
188
+ return load_reg(s, a->rt);
189
+}
190
+
191
+static bool gen_M_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
192
+{
193
+ /*
194
+ * Accesses to R15 are UNPREDICTABLE; we choose to undef.
195
+ * FPSCR -> r15 is a special case which writes to the PSR flags;
196
+ * set a->reg to a special value to tell gen_M_fp_sysreg_read()
197
+ * we only care about the top 4 bits of FPSCR there.
198
+ */
199
+ if (a->rt == 15) {
200
+ if (a->l && a->reg == ARM_VFP_FPSCR) {
201
+ a->reg = QEMU_VFP_FPSCR_NZCV;
202
+ } else {
203
+ return false;
204
+ }
205
+ }
206
+
207
+ if (a->l) {
208
+ /* VMRS, move FP system register to gp register */
209
+ return gen_M_fp_sysreg_read(s, a->reg, fp_sysreg_to_gpr, a);
210
+ } else {
211
+ /* VMSR, move gp register to FP system register */
212
+ return gen_M_fp_sysreg_write(s, a->reg, gpr_to_fp_sysreg, a);
213
+ }
214
+}
215
+
216
static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
56
{
217
{
57
uint32_t rd, rn, rm, dp = extract32(insn, 8, 1);
218
TCGv_i32 tmp;
58
219
bool ignore_vfp_enabled = false;
59
- if (!arm_dc_feature(s, ARM_FEATURE_V8)) {
220
60
- return 1;
221
- if (!dc_isar_feature(aa32_fpsp_v2, s)) {
61
- }
222
- return false;
62
-
223
+ if (arm_dc_feature(s, ARM_FEATURE_M)) {
63
if (dp) {
224
+ return gen_M_VMSR_VMRS(s, a);
64
VFP_DREG_D(rd, insn);
65
VFP_DREG_N(rn, insn);
66
@@ -XXX,XX +XXX,XX @@ static int disas_vfp_v8_insn(DisasContext *s, uint32_t insn)
67
rm = VFP_SREG_M(insn);
68
}
225
}
69
226
70
- if ((insn & 0x0f800e50) == 0x0e000a00) {
227
- if (arm_dc_feature(s, ARM_FEATURE_M)) {
71
+ if ((insn & 0x0f800e50) == 0x0e000a00 && dc_isar_feature(aa32_vsel, s)) {
228
- /*
72
return handle_vsel(insn, rd, rn, rm, dp);
229
- * The only M-profile VFP vmrs/vmsr sysreg is FPSCR.
73
- } else if ((insn & 0x0fb00e10) == 0x0e800a00) {
230
- * Accesses to R15 are UNPREDICTABLE; we choose to undef.
74
+ } else if ((insn & 0x0fb00e10) == 0x0e800a00 &&
231
- * (FPSCR -> r15 is a special case which writes to the PSR flags.)
75
+ dc_isar_feature(aa32_vminmaxnm, s)) {
232
- */
76
return handle_vminmaxnm(insn, rd, rn, rm, dp);
233
- if (a->reg != ARM_VFP_FPSCR) {
77
- } else if ((insn & 0x0fbc0ed0) == 0x0eb80a40) {
234
- return false;
78
+ } else if ((insn & 0x0fbc0ed0) == 0x0eb80a40 &&
235
- }
79
+ dc_isar_feature(aa32_vrint, s)) {
236
- if (a->rt == 15 && !a->l) {
80
/* VRINTA, VRINTN, VRINTP, VRINTM */
237
- return false;
81
int rounding = fp_decode_rm[extract32(insn, 16, 2)];
238
- }
82
return handle_vrint(insn, rd, rm, dp, rounding);
239
+ if (!dc_isar_feature(aa32_fpsp_v2, s)) {
83
- } else if ((insn & 0x0fbc0e50) == 0x0ebc0a40) {
240
+ return false;
84
+ } else if ((insn & 0x0fbc0e50) == 0x0ebc0a40 &&
85
+ dc_isar_feature(aa32_vcvt_dr, s)) {
86
/* VCVTA, VCVTN, VCVTP, VCVTM */
87
int rounding = fp_decode_rm[extract32(insn, 16, 2)];
88
return handle_vcvt(insn, rd, rm, dp, rounding);
89
@@ -XXX,XX +XXX,XX @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
90
}
241
}
91
242
92
if (extract32(insn, 28, 4) == 0xf) {
243
switch (a->reg) {
93
- /* Encodings with T=1 (Thumb) or unconditional (ARM):
94
- * only used in v8 and above.
95
+ /*
96
+ * Encodings with T=1 (Thumb) or unconditional (ARM):
97
+ * only used for the "miscellaneous VFP features" added in v8A
98
+ * and v7M (and gated on the MVFR2.FPMisc field).
99
*/
100
- return disas_vfp_v8_insn(s, insn);
101
+ return disas_vfp_misc_insn(s, insn);
102
}
103
104
dp = ((insn & 0xf00) == 0xb00);
105
--
244
--
106
2.20.1
245
2.20.1
107
246
108
247
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/16] target/arm: Add helpers for FMLAL
[PULL 19/36] target/arm: Move general-use constant expanders up in translate.c
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The constant-expander functions like negate, plus_2, etc, are
2
generally useful; move them up in translate.c so we can use them in
3
the VFP/Neon decoders as well as in the A32/T32/T16 decoders.
2
4
3
Note that float16_to_float32 rightly squashes SNaN to QNaN.
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
But of course pickNaNMulAdd, for ARM, selects SNaNs first.
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
So we have to preserve SNaN long enough for the correct NaN
7
Message-id: 20201119215617.29887-9-peter.maydell@linaro.org
6
to be selected. Thus float16_to_float32_by_bits.
8
---
9
target/arm/translate.c | 46 +++++++++++++++++++++++-------------------
10
1 file changed, 25 insertions(+), 21 deletions(-)
7
11
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
diff --git a/target/arm/translate.c b/target/arm/translate.c
9
Message-id: 20190219222952.22183-2-richard.henderson@linaro.org
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
target/arm/helper.h | 9 +++
14
target/arm/vec_helper.c | 148 ++++++++++++++++++++++++++++++++++++++++
15
2 files changed, 157 insertions(+)
16
17
diff --git a/target/arm/helper.h b/target/arm/helper.h
18
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/helper.h
14
--- a/target/arm/translate.c
20
+++ b/target/arm/helper.h
15
+++ b/target/arm/translate.c
21
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_sqsub_s, TCG_CALL_NO_RWG,
16
@@ -XXX,XX +XXX,XX @@ static void arm_gen_condlabel(DisasContext *s)
22
DEF_HELPER_FLAGS_5(gvec_sqsub_d, TCG_CALL_NO_RWG,
17
}
23
void, ptr, ptr, ptr, ptr, i32)
18
}
24
19
25
+DEF_HELPER_FLAGS_5(gvec_fmlal_a32, TCG_CALL_NO_RWG,
20
+/*
26
+ void, ptr, ptr, ptr, ptr, i32)
21
+ * Constant expanders for the decoders.
27
+DEF_HELPER_FLAGS_5(gvec_fmlal_a64, TCG_CALL_NO_RWG,
22
+ */
28
+ void, ptr, ptr, ptr, ptr, i32)
29
+DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a32, TCG_CALL_NO_RWG,
30
+ void, ptr, ptr, ptr, ptr, i32)
31
+DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a64, TCG_CALL_NO_RWG,
32
+ void, ptr, ptr, ptr, ptr, i32)
33
+
23
+
34
#ifdef TARGET_AARCH64
24
+static int negate(DisasContext *s, int x)
35
#include "helper-a64.h"
36
#include "helper-sve.h"
37
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/vec_helper.c
40
+++ b/target/arm/vec_helper.c
41
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sqsub_d)(void *vd, void *vq, void *vn,
42
}
43
clear_tail(d, oprsz, simd_maxsz(desc));
44
}
45
+
46
+/*
47
+ * Convert float16 to float32, raising no exceptions and
48
+ * preserving exceptional values, including SNaN.
49
+ * This is effectively an unpack+repack operation.
50
+ */
51
+static float32 float16_to_float32_by_bits(uint32_t f16, bool fz16)
52
+{
25
+{
53
+ const int f16_bias = 15;
26
+ return -x;
54
+ const int f32_bias = 127;
55
+ uint32_t sign = extract32(f16, 15, 1);
56
+ uint32_t exp = extract32(f16, 10, 5);
57
+ uint32_t frac = extract32(f16, 0, 10);
58
+
59
+ if (exp == 0x1f) {
60
+ /* Inf or NaN */
61
+ exp = 0xff;
62
+ } else if (exp == 0) {
63
+ /* Zero or denormal. */
64
+ if (frac != 0) {
65
+ if (fz16) {
66
+ frac = 0;
67
+ } else {
68
+ /*
69
+ * Denormal; these are all normal float32.
70
+ * Shift the fraction so that the msb is at bit 11,
71
+ * then remove bit 11 as the implicit bit of the
72
+ * normalized float32. Note that we still go through
73
+ * the shift for normal numbers below, to put the
74
+ * float32 fraction at the right place.
75
+ */
76
+ int shift = clz32(frac) - 21;
77
+ frac = (frac << shift) & 0x3ff;
78
+ exp = f32_bias - f16_bias - shift + 1;
79
+ }
80
+ }
81
+ } else {
82
+ /* Normal number; adjust the bias. */
83
+ exp += f32_bias - f16_bias;
84
+ }
85
+ sign <<= 31;
86
+ exp <<= 23;
87
+ frac <<= 23 - 10;
88
+
89
+ return sign | exp | frac;
90
+}
27
+}
91
+
28
+
92
+static uint64_t load4_f16(uint64_t *ptr, int is_q, int is_2)
29
+static int plus_2(DisasContext *s, int x)
93
+{
30
+{
94
+ /*
31
+ return x + 2;
95
+ * Branchless load of u32[0], u64[0], u32[1], or u64[1].
96
+ * Load the 2nd qword iff is_q & is_2.
97
+ * Shift to the 2nd dword iff !is_q & is_2.
98
+ * For !is_q & !is_2, the upper bits of the result are garbage.
99
+ */
100
+ return ptr[is_q & is_2] >> ((is_2 & ~is_q) << 5);
101
+}
32
+}
102
+
33
+
103
+/*
34
+static int times_2(DisasContext *s, int x)
104
+ * Note that FMLAL requires oprsz == 8 or oprsz == 16,
105
+ * as there is not yet SVE versions that might use blocking.
106
+ */
107
+
108
+static void do_fmlal(float32 *d, void *vn, void *vm, float_status *fpst,
109
+ uint32_t desc, bool fz16)
110
+{
35
+{
111
+ intptr_t i, oprsz = simd_oprsz(desc);
36
+ return x * 2;
112
+ int is_s = extract32(desc, SIMD_DATA_SHIFT, 1);
113
+ int is_2 = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
114
+ int is_q = oprsz == 16;
115
+ uint64_t n_4, m_4;
116
+
117
+ /* Pre-load all of the f16 data, avoiding overlap issues. */
118
+ n_4 = load4_f16(vn, is_q, is_2);
119
+ m_4 = load4_f16(vm, is_q, is_2);
120
+
121
+ /* Negate all inputs for FMLSL at once. */
122
+ if (is_s) {
123
+ n_4 ^= 0x8000800080008000ull;
124
+ }
125
+
126
+ for (i = 0; i < oprsz / 4; i++) {
127
+ float32 n_1 = float16_to_float32_by_bits(n_4 >> (i * 16), fz16);
128
+ float32 m_1 = float16_to_float32_by_bits(m_4 >> (i * 16), fz16);
129
+ d[H4(i)] = float32_muladd(n_1, m_1, d[H4(i)], 0, fpst);
130
+ }
131
+ clear_tail(d, oprsz, simd_maxsz(desc));
132
+}
37
+}
133
+
38
+
134
+void HELPER(gvec_fmlal_a32)(void *vd, void *vn, void *vm,
39
+static int times_4(DisasContext *s, int x)
135
+ void *venv, uint32_t desc)
136
+{
40
+{
137
+ CPUARMState *env = venv;
41
+ return x * 4;
138
+ do_fmlal(vd, vn, vm, &env->vfp.standard_fp_status, desc,
139
+ get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
140
+}
42
+}
141
+
43
+
142
+void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void *vm,
44
/* Flags for the disas_set_da_iss info argument:
143
+ void *venv, uint32_t desc)
45
* lower bits hold the Rt register number, higher bits are flags.
144
+{
46
*/
145
+ CPUARMState *env = venv;
47
@@ -XXX,XX +XXX,XX @@ static void arm_skip_unless(DisasContext *s, uint32_t cond)
146
+ do_fmlal(vd, vn, vm, &env->vfp.fp_status, desc,
48
147
+ get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
49
148
+}
50
/*
149
+
51
- * Constant expanders for the decoders.
150
+static void do_fmlal_idx(float32 *d, void *vn, void *vm, float_status *fpst,
52
+ * Constant expanders used by T16/T32 decode
151
+ uint32_t desc, bool fz16)
53
*/
152
+{
54
153
+ intptr_t i, oprsz = simd_oprsz(desc);
55
-static int negate(DisasContext *s, int x)
154
+ int is_s = extract32(desc, SIMD_DATA_SHIFT, 1);
56
-{
155
+ int is_2 = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
57
- return -x;
156
+ int index = extract32(desc, SIMD_DATA_SHIFT + 2, 3);
58
-}
157
+ int is_q = oprsz == 16;
59
-
158
+ uint64_t n_4;
60
-static int plus_2(DisasContext *s, int x)
159
+ float32 m_1;
61
-{
160
+
62
- return x + 2;
161
+ /* Pre-load all of the f16 data, avoiding overlap issues. */
63
-}
162
+ n_4 = load4_f16(vn, is_q, is_2);
64
-
163
+
65
-static int times_2(DisasContext *s, int x)
164
+ /* Negate all inputs for FMLSL at once. */
66
-{
165
+ if (is_s) {
67
- return x * 2;
166
+ n_4 ^= 0x8000800080008000ull;
68
-}
167
+ }
69
-
168
+
70
-static int times_4(DisasContext *s, int x)
169
+ m_1 = float16_to_float32_by_bits(((float16 *)vm)[H2(index)], fz16);
71
-{
170
+
72
- return x * 4;
171
+ for (i = 0; i < oprsz / 4; i++) {
73
-}
172
+ float32 n_1 = float16_to_float32_by_bits(n_4 >> (i * 16), fz16);
74
-
173
+ d[H4(i)] = float32_muladd(n_1, m_1, d[H4(i)], 0, fpst);
75
/* Return only the rotation part of T32ExpandImm. */
174
+ }
76
static int t32_expandimm_rot(DisasContext *s, int x)
175
+ clear_tail(d, oprsz, simd_maxsz(desc));
77
{
176
+}
177
+
178
+void HELPER(gvec_fmlal_idx_a32)(void *vd, void *vn, void *vm,
179
+ void *venv, uint32_t desc)
180
+{
181
+ CPUARMState *env = venv;
182
+ do_fmlal_idx(vd, vn, vm, &env->vfp.standard_fp_status, desc,
183
+ get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
184
+}
185
+
186
+void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm,
187
+ void *venv, uint32_t desc)
188
+{
189
+ CPUARMState *env = venv;
190
+ do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status, desc,
191
+ get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
192
+}
193
--
78
--
194
2.20.1
79
2.20.1
195
80
196
81
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/16] target/arm/arm-powerctl: Add new arm_set_cpu_on_and_reset()
[PULL 20/36] target/arm: Implement VLDR/VSTR system register
1
Currently the Arm arm-powerctl.h APIs allow:
1
Implement the new-in-v8.1M VLDR/VSTR variants which directly
2
* arm_set_cpu_on(), which powers on a CPU and sets its
2
read or write FP system registers to memory.
3
initial PC and other startup state
4
* arm_reset_cpu(), which resets a CPU which is already on
5
(and fails if the CPU is powered off)
6
7
but there is no way to say "power on a CPU as if it had
8
just come out of reset and don't do anything else to it".
9
10
Add a new function arm_set_cpu_on_and_reset(), which does this.
11
3
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20190219125808.25174-5-peter.maydell@linaro.org
6
Message-id: 20201119215617.29887-10-peter.maydell@linaro.org
15
---
7
---
16
target/arm/arm-powerctl.h | 16 +++++++++++
8
target/arm/vfp.decode | 14 ++++++
17
target/arm/arm-powerctl.c | 56 +++++++++++++++++++++++++++++++++++++++
9
target/arm/translate-vfp.c.inc | 91 ++++++++++++++++++++++++++++++++++
18
2 files changed, 72 insertions(+)
10
2 files changed, 105 insertions(+)
19
11
20
diff --git a/target/arm/arm-powerctl.h b/target/arm/arm-powerctl.h
12
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode
21
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/arm-powerctl.h
14
--- a/target/arm/vfp.decode
23
+++ b/target/arm/arm-powerctl.h
15
+++ b/target/arm/vfp.decode
24
@@ -XXX,XX +XXX,XX @@ int arm_set_cpu_off(uint64_t cpuid);
16
@@ -XXX,XX +XXX,XX @@ VLDR_VSTR_hp ---- 1101 u:1 .0 l:1 rn:4 .... 1001 imm:8 vd=%vd_sp
25
*/
17
VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 vd=%vd_sp
26
int arm_reset_cpu(uint64_t cpuid);
18
VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 vd=%vd_dp
27
19
28
+/*
20
+# M-profile VLDR/VSTR to sysreg
29
+ * arm_set_cpu_on_and_reset:
21
+%vldr_sysreg 22:1 13:3
30
+ * @cpuid: the id of the CPU we want to star
22
+%imm7_0x4 0:7 !function=times_4
31
+ *
32
+ * Start the cpu designated by @cpuid and put it through its normal
33
+ * CPU reset process. The CPU will start in the way it is architected
34
+ * to start after a power-on reset.
35
+ *
36
+ * Returns: QEMU_ARM_POWERCTL_RET_SUCCESS on success.
37
+ * QEMU_ARM_POWERCTL_INVALID_PARAM if there is no CPU with that ID.
38
+ * QEMU_ARM_POWERCTL_ALREADY_ON if the CPU is already on.
39
+ * QEMU_ARM_POWERCTL_ON_PENDING if the CPU is already partway through
40
+ * powering on.
41
+ */
42
+int arm_set_cpu_on_and_reset(uint64_t cpuid);
43
+
23
+
44
#endif
24
+&vldr_sysreg rn reg imm a w p
45
diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c
25
+@vldr_sysreg .... ... . a:1 . . . rn:4 ... . ... .. ....... \
26
+ reg=%vldr_sysreg imm=%imm7_0x4 &vldr_sysreg
27
+
28
+# P=0 W=0 is SEE "Related encodings", so split into two patterns
29
+VLDR_sysreg ---- 110 1 . . w:1 1 .... ... 0 111 11 ....... @vldr_sysreg p=1
30
+VLDR_sysreg ---- 110 0 . . 1 1 .... ... 0 111 11 ....... @vldr_sysreg p=0 w=1
31
+VSTR_sysreg ---- 110 1 . . w:1 0 .... ... 0 111 11 ....... @vldr_sysreg p=1
32
+VSTR_sysreg ---- 110 0 . . 1 0 .... ... 0 111 11 ....... @vldr_sysreg p=0 w=1
33
+
34
# We split the load/store multiple up into two patterns to avoid
35
# overlap with other insns in the "Advanced SIMD load/store and 64-bit move"
36
# grouping:
37
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
46
index XXXXXXX..XXXXXXX 100644
38
index XXXXXXX..XXXXXXX 100644
47
--- a/target/arm/arm-powerctl.c
39
--- a/target/arm/translate-vfp.c.inc
48
+++ b/target/arm/arm-powerctl.c
40
+++ b/target/arm/translate-vfp.c.inc
49
@@ -XXX,XX +XXX,XX @@ int arm_set_cpu_on(uint64_t cpuid, uint64_t entry, uint64_t context_id,
41
@@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
50
return QEMU_ARM_POWERCTL_RET_SUCCESS;
42
return true;
51
}
43
}
52
44
53
+static void arm_set_cpu_on_and_reset_async_work(CPUState *target_cpu_state,
45
+static void fp_sysreg_to_memory(DisasContext *s, void *opaque, TCGv_i32 value)
54
+ run_on_cpu_data data)
55
+{
46
+{
56
+ ARMCPU *target_cpu = ARM_CPU(target_cpu_state);
47
+ arg_vldr_sysreg *a = opaque;
48
+ uint32_t offset = a->imm;
49
+ TCGv_i32 addr;
57
+
50
+
58
+ /* Initialize the cpu we are turning on */
51
+ if (!a->a) {
59
+ cpu_reset(target_cpu_state);
52
+ offset = - offset;
60
+ target_cpu_state->halted = 0;
53
+ }
61
+
54
+
62
+ /* Finally set the power status */
55
+ addr = load_reg(s, a->rn);
63
+ assert(qemu_mutex_iothread_locked());
56
+ if (a->p) {
64
+ target_cpu->power_state = PSCI_ON;
57
+ tcg_gen_addi_i32(addr, addr, offset);
58
+ }
59
+
60
+ if (s->v8m_stackcheck && a->rn == 13 && a->w) {
61
+ gen_helper_v8m_stackcheck(cpu_env, addr);
62
+ }
63
+
64
+ gen_aa32_st_i32(s, value, addr, get_mem_index(s),
65
+ MO_UL | MO_ALIGN | s->be_data);
66
+ tcg_temp_free_i32(value);
67
+
68
+ if (a->w) {
69
+ /* writeback */
70
+ if (!a->p) {
71
+ tcg_gen_addi_i32(addr, addr, offset);
72
+ }
73
+ store_reg(s, a->rn, addr);
74
+ } else {
75
+ tcg_temp_free_i32(addr);
76
+ }
65
+}
77
+}
66
+
78
+
67
+int arm_set_cpu_on_and_reset(uint64_t cpuid)
79
+static TCGv_i32 memory_to_fp_sysreg(DisasContext *s, void *opaque)
68
+{
80
+{
69
+ CPUState *target_cpu_state;
81
+ arg_vldr_sysreg *a = opaque;
70
+ ARMCPU *target_cpu;
82
+ uint32_t offset = a->imm;
83
+ TCGv_i32 addr;
84
+ TCGv_i32 value = tcg_temp_new_i32();
71
+
85
+
72
+ assert(qemu_mutex_iothread_locked());
86
+ if (!a->a) {
73
+
87
+ offset = - offset;
74
+ /* Retrieve the cpu we are powering up */
75
+ target_cpu_state = arm_get_cpu_by_id(cpuid);
76
+ if (!target_cpu_state) {
77
+ /* The cpu was not found */
78
+ return QEMU_ARM_POWERCTL_INVALID_PARAM;
79
+ }
88
+ }
80
+
89
+
81
+ target_cpu = ARM_CPU(target_cpu_state);
90
+ addr = load_reg(s, a->rn);
82
+ if (target_cpu->power_state == PSCI_ON) {
91
+ if (a->p) {
83
+ qemu_log_mask(LOG_GUEST_ERROR,
92
+ tcg_gen_addi_i32(addr, addr, offset);
84
+ "[ARM]%s: CPU %" PRId64 " is already on\n",
85
+ __func__, cpuid);
86
+ return QEMU_ARM_POWERCTL_ALREADY_ON;
87
+ }
93
+ }
88
+
94
+
89
+ /*
95
+ if (s->v8m_stackcheck && a->rn == 13 && a->w) {
90
+ * If another CPU has powered the target on we are in the state
96
+ gen_helper_v8m_stackcheck(cpu_env, addr);
91
+ * ON_PENDING and additional attempts to power on the CPU should
92
+ * fail (see 6.6 Implementation CPU_ON/CPU_OFF races in the PSCI
93
+ * spec)
94
+ */
95
+ if (target_cpu->power_state == PSCI_ON_PENDING) {
96
+ qemu_log_mask(LOG_GUEST_ERROR,
97
+ "[ARM]%s: CPU %" PRId64 " is already powering on\n",
98
+ __func__, cpuid);
99
+ return QEMU_ARM_POWERCTL_ON_PENDING;
100
+ }
97
+ }
101
+
98
+
102
+ async_run_on_cpu(target_cpu_state, arm_set_cpu_on_and_reset_async_work,
99
+ gen_aa32_ld_i32(s, value, addr, get_mem_index(s),
103
+ RUN_ON_CPU_NULL);
100
+ MO_UL | MO_ALIGN | s->be_data);
104
+
101
+
105
+ /* We are good to go */
102
+ if (a->w) {
106
+ return QEMU_ARM_POWERCTL_RET_SUCCESS;
103
+ /* writeback */
104
+ if (!a->p) {
105
+ tcg_gen_addi_i32(addr, addr, offset);
106
+ }
107
+ store_reg(s, a->rn, addr);
108
+ } else {
109
+ tcg_temp_free_i32(addr);
110
+ }
111
+ return value;
107
+}
112
+}
108
+
113
+
109
static void arm_set_cpu_off_async_work(CPUState *target_cpu_state,
114
+static bool trans_VLDR_sysreg(DisasContext *s, arg_vldr_sysreg *a)
110
run_on_cpu_data data)
115
+{
116
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
117
+ return false;
118
+ }
119
+ if (a->rn == 15) {
120
+ return false;
121
+ }
122
+ return gen_M_fp_sysreg_write(s, a->reg, memory_to_fp_sysreg, a);
123
+}
124
+
125
+static bool trans_VSTR_sysreg(DisasContext *s, arg_vldr_sysreg *a)
126
+{
127
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
128
+ return false;
129
+ }
130
+ if (a->rn == 15) {
131
+ return false;
132
+ }
133
+ return gen_M_fp_sysreg_read(s, a->reg, fp_sysreg_to_memory, a);
134
+}
135
+
136
static bool trans_VMOV_half(DisasContext *s, arg_VMOV_single *a)
111
{
137
{
138
TCGv_i32 tmp;
112
--
139
--
113
2.20.1
140
2.20.1
114
141
115
142
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/16] target/arm: Implement FMLAL and FMLSL for aarch64
[PULL 21/36] target/arm: Implement M-profile FPSCR_nzcvqc
1
From: Richard Henderson <richard.henderson@linaro.org>
1
v8.1M defines a new FP system register FPSCR_nzcvqc; this behaves
2
like the existing FPSCR, except that it reads and writes only bits
3
[31:27] of the FPSCR (the N, Z, C, V and QC flag bits). (Unlike the
4
FPSCR, the special case for Rt=15 of writing the CPSR.NZCV is not
5
permitted.)
2
6
3
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Implement the register. Since we don't yet implement MVE, we handle
4
Message-id: 20190219222952.22183-3-richard.henderson@linaro.org
8
the QC bit as RES0, with todo comments for where we will need to add
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
support later.
10
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20201119215617.29887-11-peter.maydell@linaro.org
7
---
14
---
8
target/arm/cpu.h | 5 ++++
15
target/arm/cpu.h | 13 +++++++++++++
9
target/arm/translate-a64.c | 49 +++++++++++++++++++++++++++++++++++++-
16
target/arm/translate-vfp.c.inc | 27 +++++++++++++++++++++++++++
10
2 files changed, 53 insertions(+), 1 deletion(-)
17
2 files changed, 40 insertions(+)
11
18
12
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
19
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
13
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/cpu.h
21
--- a/target/arm/cpu.h
15
+++ b/target/arm/cpu.h
22
+++ b/target/arm/cpu.h
16
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
23
@@ -XXX,XX +XXX,XX @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
17
return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
24
#define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
18
}
25
#define FPCR_DN (1 << 25) /* Default NaN enable bit */
19
26
#define FPCR_QC (1 << 27) /* Cumulative saturation bit */
20
+static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id)
27
+#define FPCR_V (1 << 28) /* FP overflow flag */
21
+{
28
+#define FPCR_C (1 << 29) /* FP carry flag */
22
+ return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
29
+#define FPCR_Z (1 << 30) /* FP zero flag */
23
+}
30
+#define FPCR_N (1 << 31) /* FP negative flag */
24
+
31
+
25
static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
32
+#define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V)
33
+#define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC)
34
35
static inline uint32_t vfp_get_fpsr(CPUARMState *env)
26
{
36
{
27
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
37
@@ -XXX,XX +XXX,XX @@ enum arm_cpu_mode {
28
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
38
#define ARM_VFP_FPEXC 8
39
#define ARM_VFP_FPINST 9
40
#define ARM_VFP_FPINST2 10
41
+/* These ones are M-profile only */
42
+#define ARM_VFP_FPSCR_NZCVQC 2
43
+#define ARM_VFP_VPR 12
44
+#define ARM_VFP_P0 13
45
+#define ARM_VFP_FPCXT_NS 14
46
+#define ARM_VFP_FPCXT_S 15
47
48
/* QEMU-internal value meaning "FPSCR, but we care only about NZCV" */
49
#define QEMU_VFP_FPSCR_NZCV 0xffff
50
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
29
index XXXXXXX..XXXXXXX 100644
51
index XXXXXXX..XXXXXXX 100644
30
--- a/target/arm/translate-a64.c
52
--- a/target/arm/translate-vfp.c.inc
31
+++ b/target/arm/translate-a64.c
53
+++ b/target/arm/translate-vfp.c.inc
32
@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_float(DisasContext *s, uint32_t insn)
54
@@ -XXX,XX +XXX,XX @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno)
33
if (!fp_access_check(s)) {
55
case ARM_VFP_FPSCR:
34
return;
56
case QEMU_VFP_FPSCR_NZCV:
35
}
57
break;
36
-
58
+ case ARM_VFP_FPSCR_NZCVQC:
37
handle_3same_float(s, size, elements, fpopcode, rd, rn, rm);
59
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
38
return;
60
+ return false;
39
+
40
+ case 0x1d: /* FMLAL */
41
+ case 0x3d: /* FMLSL */
42
+ case 0x59: /* FMLAL2 */
43
+ case 0x79: /* FMLSL2 */
44
+ if (size & 1 || !dc_isar_feature(aa64_fhm, s)) {
45
+ unallocated_encoding(s);
46
+ return;
47
+ }
61
+ }
48
+ if (fp_access_check(s)) {
49
+ int is_s = extract32(insn, 23, 1);
50
+ int is_2 = extract32(insn, 29, 1);
51
+ int data = (is_2 << 1) | is_s;
52
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
53
+ vec_full_reg_offset(s, rn),
54
+ vec_full_reg_offset(s, rm), cpu_env,
55
+ is_q ? 16 : 8, vec_full_reg_size(s),
56
+ data, gen_helper_gvec_fmlal_a64);
57
+ }
58
+ return;
59
+
60
default:
61
unallocated_encoding(s);
62
return;
63
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
64
}
65
is_fp = 2;
66
break;
67
+ case 0x00: /* FMLAL */
68
+ case 0x04: /* FMLSL */
69
+ case 0x18: /* FMLAL2 */
70
+ case 0x1c: /* FMLSL2 */
71
+ if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_fhm, s)) {
72
+ unallocated_encoding(s);
73
+ return;
74
+ }
75
+ size = MO_16;
76
+ /* is_fp, but we pass cpu_env not fp_status. */
77
+ break;
62
+ break;
78
default:
63
default:
79
unallocated_encoding(s);
64
return FPSysRegCheckFailed;
80
return;
81
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
82
tcg_temp_free_ptr(fpst);
83
}
84
return;
85
+
86
+ case 0x00: /* FMLAL */
87
+ case 0x04: /* FMLSL */
88
+ case 0x18: /* FMLAL2 */
89
+ case 0x1c: /* FMLSL2 */
90
+ {
91
+ int is_s = extract32(opcode, 2, 1);
92
+ int is_2 = u;
93
+ int data = (index << 2) | (is_2 << 1) | is_s;
94
+ tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
95
+ vec_full_reg_offset(s, rn),
96
+ vec_full_reg_offset(s, rm), cpu_env,
97
+ is_q ? 16 : 8, vec_full_reg_size(s),
98
+ data, gen_helper_gvec_fmlal_idx_a64);
99
+ }
100
+ return;
101
}
65
}
102
66
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
103
if (size == 3) {
67
tcg_temp_free_i32(tmp);
68
gen_lookup_tb(s);
69
break;
70
+ case ARM_VFP_FPSCR_NZCVQC:
71
+ {
72
+ TCGv_i32 fpscr;
73
+ tmp = loadfn(s, opaque);
74
+ /*
75
+ * TODO: when we implement MVE, write the QC bit.
76
+ * For non-MVE, QC is RES0.
77
+ */
78
+ tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
79
+ fpscr = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
80
+ tcg_gen_andi_i32(fpscr, fpscr, ~FPCR_NZCV_MASK);
81
+ tcg_gen_or_i32(fpscr, fpscr, tmp);
82
+ store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]);
83
+ tcg_temp_free_i32(tmp);
84
+ break;
85
+ }
86
default:
87
g_assert_not_reached();
88
}
89
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
90
gen_helper_vfp_get_fpscr(tmp, cpu_env);
91
storefn(s, opaque, tmp);
92
break;
93
+ case ARM_VFP_FPSCR_NZCVQC:
94
+ /*
95
+ * TODO: MVE has a QC bit, which we probably won't store
96
+ * in the xregs[] field. For non-MVE, where QC is RES0,
97
+ * we can just fall through to the FPSCR_NZCV case.
98
+ */
99
case QEMU_VFP_FPSCR_NZCV:
100
/*
101
* Read just NZCV; this is a special case to avoid the
104
--
102
--
105
2.20.1
103
2.20.1
106
104
107
105
diff view generated by jsdifflib
New patch
[PULL 22/36] target/arm: Use new FPCR_NZCV_MASK constant
1
We defined a constant name for the mask of NZCV bits in the FPCR/FPSCR
2
in the previous commit; use it in a couple of places in existing code,
3
where we're masking out everything except NZCV for the "load to Rt=15
4
sets CPSR.NZCV" special case.
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20201119215617.29887-12-peter.maydell@linaro.org
9
---
10
target/arm/translate-vfp.c.inc | 4 ++--
11
1 file changed, 2 insertions(+), 2 deletions(-)
12
13
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-vfp.c.inc
16
+++ b/target/arm/translate-vfp.c.inc
17
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
18
* helper call for the "VMRS to CPSR.NZCV" insn.
19
*/
20
tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
21
- tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
22
+ tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
23
storefn(s, opaque, tmp);
24
break;
25
default:
26
@@ -XXX,XX +XXX,XX @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
27
case ARM_VFP_FPSCR:
28
if (a->rt == 15) {
29
tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
30
- tcg_gen_andi_i32(tmp, tmp, 0xf0000000);
31
+ tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
32
} else {
33
tmp = tcg_temp_new_i32();
34
gen_helper_vfp_get_fpscr(tmp, cpu_env);
35
--
36
2.20.1
37
38
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/16] hw/arm/iotkit-sysctl: Implement CPUWAIT and INITSVTOR*
[PULL 23/36] target/arm: Factor out preserve-fp-state from full_vfp_access_check()
1
The CPUWAIT register acts as a sort of power-control: if a bit
1
Factor out the code which handles M-profile lazy FP state preservation
2
in it is 1 then the CPU will have been forced into waiting
2
from full_vfp_access_check(); accesses to the FPCXT_NS register are
3
when the system was reset (which in QEMU we model as the
3
a special case which need to do just this part (corresponding in the
4
CPU starting powered off). Writing a 0 to the register will
4
pseudocode to the PreserveFPState() function), and not the full
5
allow the CPU to boot (for QEMU, we model this as powering
5
set of actions matching the pseudocode ExecuteFPCheck() which
6
it on). Note that writing 0 to the register does not power
6
normal FP instructions need to do.
7
off a CPU.
8
9
For this to work correctly we need to also honour the
10
INITSVTOR* registers, which let the guest control where the
11
CPU will load its SP and PC from when it comes out of reset.
12
7
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20190219125808.25174-8-peter.maydell@linaro.org
10
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
11
Message-id: 20201119215617.29887-13-peter.maydell@linaro.org
16
---
12
---
17
hw/misc/iotkit-sysctl.c | 41 +++++++++++++++++++++++++++++++++++++----
13
target/arm/translate-vfp.c.inc | 45 ++++++++++++++++++++--------------
18
1 file changed, 37 insertions(+), 4 deletions(-)
14
1 file changed, 27 insertions(+), 18 deletions(-)
19
15
20
diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
16
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
21
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/misc/iotkit-sysctl.c
18
--- a/target/arm/translate-vfp.c.inc
23
+++ b/hw/misc/iotkit-sysctl.c
19
+++ b/target/arm/translate-vfp.c.inc
24
@@ -XXX,XX +XXX,XX @@
20
@@ -XXX,XX +XXX,XX @@ static inline long vfp_f16_offset(unsigned reg, bool top)
25
#include "hw/sysbus.h"
21
return offs;
26
#include "hw/registerfields.h"
22
}
27
#include "hw/misc/iotkit-sysctl.h"
28
+#include "target/arm/arm-powerctl.h"
29
+#include "target/arm/cpu.h"
30
31
REG32(SECDBGSTAT, 0x0)
32
REG32(SECDBGSET, 0x4)
33
@@ -XXX,XX +XXX,XX @@ static const int sysctl_id[] = {
34
0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
35
};
36
23
37
+/*
24
+/*
38
+ * Set the initial secure vector table offset address for the core.
25
+ * Generate code for M-profile lazy FP state preservation if needed;
39
+ * This will take effect when the CPU next resets.
26
+ * this corresponds to the pseudocode PreserveFPState() function.
40
+ */
27
+ */
41
+static void set_init_vtor(uint64_t cpuid, uint32_t vtor)
28
+static void gen_preserve_fp_state(DisasContext *s)
42
+{
29
+{
43
+ Object *cpuobj = OBJECT(arm_get_cpu_by_id(cpuid));
30
+ if (s->v7m_lspact) {
44
+
31
+ /*
45
+ if (cpuobj) {
32
+ * Lazy state saving affects external memory and also the NVIC,
46
+ if (object_property_find(cpuobj, "init-svtor", NULL)) {
33
+ * so we must mark it as an IO operation for icount (and cause
47
+ object_property_set_uint(cpuobj, vtor, "init-svtor", &error_abort);
34
+ * this to be the last insn in the TB).
35
+ */
36
+ if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
37
+ s->base.is_jmp = DISAS_UPDATE_EXIT;
38
+ gen_io_start();
48
+ }
39
+ }
40
+ gen_helper_v7m_preserve_fp_state(cpu_env);
41
+ /*
42
+ * If the preserve_fp_state helper doesn't throw an exception
43
+ * then it will clear LSPACT; we don't need to repeat this for
44
+ * any further FP insns in this TB.
45
+ */
46
+ s->v7m_lspact = false;
49
+ }
47
+ }
50
+}
48
+}
51
+
49
+
52
static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
50
/*
53
unsigned size)
51
* Check that VFP access is enabled. If it is, do the necessary
54
{
52
* M-profile lazy-FP handling and then return true.
55
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
53
@@ -XXX,XX +XXX,XX @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
56
s->gretreg = value;
54
/* Handle M-profile lazy FP state mechanics */
57
break;
55
58
case A_INITSVTOR0:
56
/* Trigger lazy-state preservation if necessary */
59
- qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR0 unimplemented\n");
57
- if (s->v7m_lspact) {
60
s->initsvtor0 = value;
58
- /*
61
+ set_init_vtor(0, s->initsvtor0);
59
- * Lazy state saving affects external memory and also the NVIC,
62
break;
60
- * so we must mark it as an IO operation for icount (and cause
63
case A_CPUWAIT:
61
- * this to be the last insn in the TB).
64
- qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CPUWAIT unimplemented\n");
62
- */
65
+ if ((s->cpuwait & 1) && !(value & 1)) {
63
- if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
66
+ /* Powering up CPU 0 */
64
- s->base.is_jmp = DISAS_UPDATE_EXIT;
67
+ arm_set_cpu_on_and_reset(0);
65
- gen_io_start();
68
+ }
66
- }
69
+ if ((s->cpuwait & 2) && !(value & 2)) {
67
- gen_helper_v7m_preserve_fp_state(cpu_env);
70
+ /* Powering up CPU 1 */
68
- /*
71
+ arm_set_cpu_on_and_reset(1);
69
- * If the preserve_fp_state helper doesn't throw an exception
72
+ }
70
- * then it will clear LSPACT; we don't need to repeat this for
73
s->cpuwait = value;
71
- * any further FP insns in this TB.
74
break;
72
- */
75
case A_WICCTRL:
73
- s->v7m_lspact = false;
76
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
74
- }
77
if (!s->is_sse200) {
75
+ gen_preserve_fp_state(s);
78
goto bad_offset;
76
79
}
77
/* Update ownership of FP context: set FPCCR.S to match current state */
80
- qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR1 unimplemented\n");
78
if (s->v8m_fpccr_s_wrong) {
81
s->initsvtor1 = value;
82
+ set_init_vtor(1, s->initsvtor1);
83
break;
84
case A_EWCTRL:
85
if (!s->is_sse200) {
86
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_reset(DeviceState *dev)
87
s->gretreg = 0;
88
s->initsvtor0 = 0x10000000;
89
s->initsvtor1 = 0x10000000;
90
- s->cpuwait = 0;
91
+ if (s->is_sse200) {
92
+ /*
93
+ * CPU 0 starts on, CPU 1 starts off. In real hardware this is
94
+ * configurable by the SoC integrator as a verilog parameter.
95
+ */
96
+ s->cpuwait = 2;
97
+ } else {
98
+ /* CPU 0 starts on */
99
+ s->cpuwait = 0;
100
+ }
101
s->wicctrl = 0;
102
s->scsecctrl = 0;
103
s->fclk_div = 0;
104
--
79
--
105
2.20.1
80
2.20.1
106
81
107
82
diff view generated by jsdifflib
New patch
[PULL 24/36] target/arm: Implement FPCXT_S fp system register
1
Implement the new-in-v8.1M FPCXT_S floating point system register.
2
This is for saving and restoring the secure floating point context,
3
and it reads and writes bits [27:0] from the FPSCR and the
4
CONTROL.SFPA bit in bit [31].
1
5
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20201119215617.29887-14-peter.maydell@linaro.org
9
---
10
target/arm/translate-vfp.c.inc | 58 ++++++++++++++++++++++++++++++++++
11
1 file changed, 58 insertions(+)
12
13
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-vfp.c.inc
16
+++ b/target/arm/translate-vfp.c.inc
17
@@ -XXX,XX +XXX,XX @@ static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno)
18
return false;
19
}
20
break;
21
+ case ARM_VFP_FPCXT_S:
22
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
23
+ return false;
24
+ }
25
+ if (!s->v8m_secure) {
26
+ return false;
27
+ }
28
+ break;
29
default:
30
return FPSysRegCheckFailed;
31
}
32
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
33
tcg_temp_free_i32(tmp);
34
break;
35
}
36
+ case ARM_VFP_FPCXT_S:
37
+ {
38
+ TCGv_i32 sfpa, control, fpscr;
39
+ /* Set FPSCR[27:0] and CONTROL.SFPA from value */
40
+ tmp = loadfn(s, opaque);
41
+ sfpa = tcg_temp_new_i32();
42
+ tcg_gen_shri_i32(sfpa, tmp, 31);
43
+ control = load_cpu_field(v7m.control[M_REG_S]);
44
+ tcg_gen_deposit_i32(control, control, sfpa,
45
+ R_V7M_CONTROL_SFPA_SHIFT, 1);
46
+ store_cpu_field(control, v7m.control[M_REG_S]);
47
+ fpscr = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
48
+ tcg_gen_andi_i32(fpscr, fpscr, FPCR_NZCV_MASK);
49
+ tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
50
+ tcg_gen_or_i32(fpscr, fpscr, tmp);
51
+ store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]);
52
+ tcg_temp_free_i32(tmp);
53
+ tcg_temp_free_i32(sfpa);
54
+ break;
55
+ }
56
default:
57
g_assert_not_reached();
58
}
59
@@ -XXX,XX +XXX,XX @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
60
tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
61
storefn(s, opaque, tmp);
62
break;
63
+ case ARM_VFP_FPCXT_S:
64
+ {
65
+ TCGv_i32 control, sfpa, fpscr;
66
+ /* Bits [27:0] from FPSCR, bit [31] from CONTROL.SFPA */
67
+ tmp = tcg_temp_new_i32();
68
+ sfpa = tcg_temp_new_i32();
69
+ gen_helper_vfp_get_fpscr(tmp, cpu_env);
70
+ tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
71
+ control = load_cpu_field(v7m.control[M_REG_S]);
72
+ tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);
73
+ tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT);
74
+ tcg_gen_or_i32(tmp, tmp, sfpa);
75
+ tcg_temp_free_i32(sfpa);
76
+ /*
77
+ * Store result before updating FPSCR etc, in case
78
+ * it is a memory write which causes an exception.
79
+ */
80
+ storefn(s, opaque, tmp);
81
+ /*
82
+ * Now we must reset FPSCR from FPDSCR_NS, and clear
83
+ * CONTROL.SFPA; so we'll end the TB here.
84
+ */
85
+ tcg_gen_andi_i32(control, control, ~R_V7M_CONTROL_SFPA_MASK);
86
+ store_cpu_field(control, v7m.control[M_REG_S]);
87
+ fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);
88
+ gen_helper_vfp_set_fpscr(cpu_env, fpscr);
89
+ tcg_temp_free_i32(fpscr);
90
+ gen_lookup_tb(s);
91
+ break;
92
+ }
93
default:
94
g_assert_not_reached();
95
}
96
--
97
2.20.1
98
99
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/16] target/arm: Enable ARMv8.2-FHM for -cpu max
[PULL 25/36] hw/intc/armv7m_nvic: Update FPDSCR masking for v8.1M
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The FPDSCR register has a similar layout to the FPSCR. In v8.1M it
2
gains new fields FZ16 (if half-precision floating point is supported)
3
and LTPSIZE (always reads as 4). Update the reset value and the code
4
that handles writes to this register accordingly.
2
5
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20190219222952.22183-5-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20201119215617.29887-16-peter.maydell@linaro.org
7
---
9
---
8
target/arm/cpu.c | 1 +
10
target/arm/cpu.h | 5 +++++
9
target/arm/cpu64.c | 2 ++
11
hw/intc/armv7m_nvic.c | 9 ++++++++-
10
2 files changed, 3 insertions(+)
12
target/arm/cpu.c | 3 +++
13
3 files changed, 16 insertions(+), 1 deletion(-)
11
14
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu.h
18
+++ b/target/arm/cpu.h
19
@@ -XXX,XX +XXX,XX @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val);
20
#define FPCR_IXE (1 << 12) /* Inexact exception trap enable */
21
#define FPCR_IDE (1 << 15) /* Input Denormal exception trap enable */
22
#define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */
23
+#define FPCR_RMODE_MASK (3 << 22) /* Rounding mode */
24
#define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */
25
#define FPCR_DN (1 << 25) /* Default NaN enable bit */
26
+#define FPCR_AHP (1 << 26) /* Alternative half-precision */
27
#define FPCR_QC (1 << 27) /* Cumulative saturation bit */
28
#define FPCR_V (1 << 28) /* FP overflow flag */
29
#define FPCR_C (1 << 29) /* FP carry flag */
30
#define FPCR_Z (1 << 30) /* FP zero flag */
31
#define FPCR_N (1 << 31) /* FP negative flag */
32
33
+#define FPCR_LTPSIZE_SHIFT 16 /* LTPSIZE, M-profile only */
34
+#define FPCR_LTPSIZE_MASK (7 << FPCR_LTPSIZE_SHIFT)
35
+
36
#define FPCR_NZCV_MASK (FPCR_N | FPCR_Z | FPCR_C | FPCR_V)
37
#define FPCR_NZCVQC_MASK (FPCR_NZCV_MASK | FPCR_QC)
38
39
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
40
index XXXXXXX..XXXXXXX 100644
41
--- a/hw/intc/armv7m_nvic.c
42
+++ b/hw/intc/armv7m_nvic.c
43
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
44
break;
45
case 0xf3c: /* FPDSCR */
46
if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
47
- value &= 0x07c00000;
48
+ uint32_t mask = FPCR_AHP | FPCR_DN | FPCR_FZ | FPCR_RMODE_MASK;
49
+ if (cpu_isar_feature(any_fp16, cpu)) {
50
+ mask |= FPCR_FZ16;
51
+ }
52
+ value &= mask;
53
+ if (cpu_isar_feature(aa32_lob, cpu)) {
54
+ value |= 4 << FPCR_LTPSIZE_SHIFT;
55
+ }
56
cpu->env.v7m.fpdscr[attrs.secure] = value;
57
}
58
break;
12
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
59
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
13
index XXXXXXX..XXXXXXX 100644
60
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/cpu.c
61
--- a/target/arm/cpu.c
15
+++ b/target/arm/cpu.c
62
+++ b/target/arm/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
63
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(DeviceState *dev)
17
t = cpu->isar.id_isar6;
64
* always reset to 4.
18
t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
65
*/
19
t = FIELD_DP32(t, ID_ISAR6, DP, 1);
66
env->v7m.ltpsize = 4;
20
+ t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
67
+ /* The LTPSIZE field in FPDSCR is constant and reads as 4. */
21
cpu->isar.id_isar6 = t;
68
+ env->v7m.fpdscr[M_REG_NS] = 4 << FPCR_LTPSIZE_SHIFT;
22
69
+ env->v7m.fpdscr[M_REG_S] = 4 << FPCR_LTPSIZE_SHIFT;
23
t = cpu->id_mmfr4;
70
}
24
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
71
25
index XXXXXXX..XXXXXXX 100644
72
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
26
--- a/target/arm/cpu64.c
27
+++ b/target/arm/cpu64.c
28
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
29
t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
30
t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
31
t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
32
+ t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
33
cpu->isar.id_aa64isar0 = t;
34
35
t = cpu->isar.id_aa64isar1;
36
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
37
u = cpu->isar.id_isar6;
38
u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
39
u = FIELD_DP32(u, ID_ISAR6, DP, 1);
40
+ u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
41
cpu->isar.id_isar6 = u;
42
43
/*
44
--
73
--
45
2.20.1
74
2.20.1
46
75
47
76
diff view generated by jsdifflib
New patch
[PULL 26/36] target/arm: For v8.1M, always clear R0-R3, R12, APSR, EPSR on exception entry
1
In v8.0M, on exception entry the registers R0-R3, R12, APSR and EPSR
2
are zeroed for an exception taken to Non-secure state; for an
3
exception taken to Secure state they become UNKNOWN, and we chose to
4
leave them at their previous values.
1
5
6
In v8.1M the behaviour is specified more tightly and these registers
7
are always zeroed regardless of the security state that the exception
8
targets (see rule R_KPZV). Implement this.
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20201119215617.29887-17-peter.maydell@linaro.org
13
---
14
target/arm/m_helper.c | 16 ++++++++++++----
15
1 file changed, 12 insertions(+), 4 deletions(-)
16
17
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/m_helper.c
20
+++ b/target/arm/m_helper.c
21
@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
22
* Clear registers if necessary to prevent non-secure exception
23
* code being able to see register values from secure code.
24
* Where register values become architecturally UNKNOWN we leave
25
- * them with their previous values.
26
+ * them with their previous values. v8.1M is tighter than v8.0M
27
+ * here and always zeroes the caller-saved registers regardless
28
+ * of the security state the exception is targeting.
29
*/
30
if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {
31
- if (!targets_secure) {
32
+ if (!targets_secure || arm_feature(env, ARM_FEATURE_V8_1M)) {
33
/*
34
* Always clear the caller-saved registers (they have been
35
* pushed to the stack earlier in v7m_push_stack()).
36
@@ -XXX,XX +XXX,XX @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t lr, bool dotailchain,
37
* v7m_push_callee_stack()).
38
*/
39
int i;
40
+ /*
41
+ * r4..r11 are callee-saves, zero only if background
42
+ * state was Secure (EXCRET.S == 1) and exception
43
+ * targets Non-secure state
44
+ */
45
+ bool zero_callee_saves = !targets_secure &&
46
+ (lr & R_V7M_EXCRET_S_MASK);
47
48
for (i = 0; i < 13; i++) {
49
- /* r4..r11 are callee-saves, zero only if EXCRET.S == 1 */
50
- if (i < 4 || i > 11 || (lr & R_V7M_EXCRET_S_MASK)) {
51
+ if (i < 4 || i > 11 || zero_callee_saves) {
52
env->regs[i] = 0;
53
}
54
}
55
--
56
2.20.1
57
58
diff view generated by jsdifflib
New patch
[PULL 27/36] target/arm: In v8.1M, don't set HFSR.FORCED on vector table fetch failures
1
In v8.1M, vector table fetch failures don't set HFSR.FORCED (see rule
2
R_LLRP). (In previous versions of the architecture this was either
3
required or IMPDEF.)
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20201119215617.29887-18-peter.maydell@linaro.org
8
---
9
target/arm/m_helper.c | 6 +++++-
10
1 file changed, 5 insertions(+), 1 deletion(-)
11
12
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/m_helper.c
15
+++ b/target/arm/m_helper.c
16
@@ -XXX,XX +XXX,XX @@ load_fail:
17
* The HardFault is Secure if BFHFNMINS is 0 (meaning that all HFs are
18
* secure); otherwise it targets the same security state as the
19
* underlying exception.
20
+ * In v8.1M HardFaults from vector table fetch fails don't set FORCED.
21
*/
22
if (!(cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK)) {
23
exc_secure = true;
24
}
25
- env->v7m.hfsr |= R_V7M_HFSR_VECTTBL_MASK | R_V7M_HFSR_FORCED_MASK;
26
+ env->v7m.hfsr |= R_V7M_HFSR_VECTTBL_MASK;
27
+ if (!arm_feature(env, ARM_FEATURE_V8_1M)) {
28
+ env->v7m.hfsr |= R_V7M_HFSR_FORCED_MASK;
29
+ }
30
armv7m_nvic_set_pending_derived(env->nvic, ARMV7M_EXCP_HARD, exc_secure);
31
return false;
32
}
33
--
34
2.20.1
35
36
diff view generated by jsdifflib
New patch
[PULL 28/36] target/arm: Implement v8.1M REVIDR register
1
In v8.1M a REVIDR register is defined, which is at address 0xe00ecfc
2
and is a read-only IMPDEF register providing implementation specific
3
minor revision information, like the v8A REVIDR_EL1. Implement this.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20201119215617.29887-19-peter.maydell@linaro.org
8
---
9
hw/intc/armv7m_nvic.c | 5 +++++
10
1 file changed, 5 insertions(+)
11
12
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/hw/intc/armv7m_nvic.c
15
+++ b/hw/intc/armv7m_nvic.c
16
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
17
}
18
return val;
19
}
20
+ case 0xcfc:
21
+ if (!arm_feature(&cpu->env, ARM_FEATURE_V8_1M)) {
22
+ goto bad_offset;
23
+ }
24
+ return cpu->revidr;
25
case 0xd00: /* CPUID Base. */
26
return cpu->midr;
27
case 0xd04: /* Interrupt Control State (ICSR) */
28
--
29
2.20.1
30
31
diff view generated by jsdifflib
New patch
[PULL 29/36] target/arm: Implement new v8.1M NOCP check for exception return
1
In v8.1M a new exception return check is added which may cause a NOCP
2
UsageFault (see rule R_XLTP): before we clear s0..s15 and the FPSCR
3
we must check whether access to CP10 from the Security state of the
4
returning exception is disabled; if it is then we must take a fault.
1
5
6
(Note that for our implementation CPPWR is always RAZ/WI and so can
7
never cause CP10 accesses to fail.)
8
9
The other v8.1M change to this register-clearing code is that if MVE
10
is implemented VPR must also be cleared, so add a TODO comment to
11
that effect.
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20201119215617.29887-20-peter.maydell@linaro.org
16
---
17
target/arm/m_helper.c | 22 +++++++++++++++++++++-
18
1 file changed, 21 insertions(+), 1 deletion(-)
19
20
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/m_helper.c
23
+++ b/target/arm/m_helper.c
24
@@ -XXX,XX +XXX,XX @@ static void do_v7m_exception_exit(ARMCPU *cpu)
25
v7m_exception_taken(cpu, excret, true, false);
26
return;
27
} else {
28
- /* Clear s0..s15 and FPSCR */
29
+ if (arm_feature(env, ARM_FEATURE_V8_1M)) {
30
+ /* v8.1M adds this NOCP check */
31
+ bool nsacr_pass = exc_secure ||
32
+ extract32(env->v7m.nsacr, 10, 1);
33
+ bool cpacr_pass = v7m_cpacr_pass(env, exc_secure, true);
34
+ if (!nsacr_pass) {
35
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE, true);
36
+ env->v7m.cfsr[M_REG_S] |= R_V7M_CFSR_NOCP_MASK;
37
+ qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
38
+ "stackframe: NSACR prevents clearing FPU registers\n");
39
+ v7m_exception_taken(cpu, excret, true, false);
40
+ } else if (!cpacr_pass) {
41
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE,
42
+ exc_secure);
43
+ env->v7m.cfsr[exc_secure] |= R_V7M_CFSR_NOCP_MASK;
44
+ qemu_log_mask(CPU_LOG_INT, "...taking UsageFault on existing "
45
+ "stackframe: CPACR prevents clearing FPU registers\n");
46
+ v7m_exception_taken(cpu, excret, true, false);
47
+ }
48
+ }
49
+ /* Clear s0..s15 and FPSCR; TODO also VPR when MVE is implemented */
50
int i;
51
52
for (i = 0; i < 16; i += 2) {
53
--
54
2.20.1
55
56
diff view generated by jsdifflib
New patch
[PULL 30/36] target/arm: Implement new v8.1M VLLDM and VLSTM encodings
1
v8.1M adds new encodings of VLLDM and VLSTM (where bit 7 is set).
2
The only difference is that:
3
* the old T1 encodings UNDEF if the implementation implements 32
4
Dregs (this is currently architecturally impossible for M-profile)
5
* the new T2 encodings have the implementation-defined option to
6
read from memory (discarding the data) or write UNKNOWN values to
7
memory for the stack slots that would be D16-D31
1
8
9
We choose not to make those accesses, so for us the two
10
instructions behave identically assuming they don't UNDEF.
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20201119215617.29887-21-peter.maydell@linaro.org
15
---
16
target/arm/m-nocp.decode | 2 +-
17
target/arm/translate-vfp.c.inc | 25 +++++++++++++++++++++++++
18
2 files changed, 26 insertions(+), 1 deletion(-)
19
20
diff --git a/target/arm/m-nocp.decode b/target/arm/m-nocp.decode
21
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/m-nocp.decode
23
+++ b/target/arm/m-nocp.decode
24
@@ -XXX,XX +XXX,XX @@
25
26
{
27
# Special cases which do not take an early NOCP: VLLDM and VLSTM
28
- VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000
29
+ VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 op:1 000 0000
30
# VSCCLRM (new in v8.1M) is similar:
31
VSCCLRM 1110 1100 1.01 1111 .... 1011 imm:7 0 vd=%vd_dp size=3
32
VSCCLRM 1110 1100 1.01 1111 .... 1010 imm:8 vd=%vd_sp size=2
33
diff --git a/target/arm/translate-vfp.c.inc b/target/arm/translate-vfp.c.inc
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/translate-vfp.c.inc
36
+++ b/target/arm/translate-vfp.c.inc
37
@@ -XXX,XX +XXX,XX @@ static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
38
!arm_dc_feature(s, ARM_FEATURE_V8)) {
39
return false;
40
}
41
+
42
+ if (a->op) {
43
+ /*
44
+ * T2 encoding ({D0-D31} reglist): v8.1M and up. We choose not
45
+ * to take the IMPDEF option to make memory accesses to the stack
46
+ * slots that correspond to the D16-D31 registers (discarding
47
+ * read data and writing UNKNOWN values), so for us the T2
48
+ * encoding behaves identically to the T1 encoding.
49
+ */
50
+ if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
51
+ return false;
52
+ }
53
+ } else {
54
+ /*
55
+ * T1 encoding ({D0-D15} reglist); undef if we have 32 Dregs.
56
+ * This is currently architecturally impossible, but we add the
57
+ * check to stay in line with the pseudocode. Note that we must
58
+ * emit code for the UNDEF so it takes precedence over the NOCP.
59
+ */
60
+ if (dc_isar_feature(aa32_simd_r32, s)) {
61
+ unallocated_encoding(s);
62
+ return true;
63
+ }
64
+ }
65
+
66
/*
67
* If not secure, UNDEF. We must emit code for this
68
* rather than returning false so that this takes
69
--
70
2.20.1
71
72
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/16] Revert "arm: Allow system registers for KVM guests to be changed by QEMU code"
[PULL 31/36] hw/intc/armv7m_nvic: Support v8.1M CCR.TRD bit
1
This reverts commit 823e1b3818f9b10b824ddcd756983b6e2fa68730,
1
v8.1M introduces a new TRD flag in the CCR register, which enables
2
which introduces a regression running EDK2 guest firmware
2
checking for stack frame integrity signatures on SG instructions.
3
under KVM:
3
This bit is not banked, and is always RAZ/WI to Non-secure code.
4
Adjust the code for handling CCR reads and writes to handle this.
4
5
5
error: kvm run failed Function not implemented
6
PC=000000013f5a6208 X00=00000000404003c4 X01=000000000000003a
7
X02=0000000000000000 X03=00000000404003c4 X04=0000000000000000
8
X05=0000000096000046 X06=000000013d2ef270 X07=000000013e3d1710
9
X08=09010755ffaf8ba8 X09=ffaf8b9cfeeb5468 X10=feeb546409010756
10
X11=09010757ffaf8b90 X12=feeb50680903068b X13=090306a1ffaf8bc0
11
X14=0000000000000000 X15=0000000000000000 X16=000000013f872da0
12
X17=00000000ffffa6ab X18=0000000000000000 X19=000000013f5a92d0
13
X20=000000013f5a7a78 X21=000000000000003a X22=000000013f5a7ab2
14
X23=000000013f5a92e8 X24=000000013f631090 X25=0000000000000010
15
X26=0000000000000100 X27=000000013f89501b X28=000000013e3d14e0
16
X29=000000013e3d12a0 X30=000000013f5a2518 SP=000000013b7be0b0
17
PSTATE=404003c4 -Z-- EL1t
18
19
with
20
[ 3507.926571] kvm [35042]: load/store instruction decoding not implemented
21
in the host dmesg.
22
23
Revert the change for the moment until we can investigate the
24
cause of the regression.
25
26
Reported-by: Eric Auger <eric.auger@redhat.com>
27
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20201119215617.29887-23-peter.maydell@linaro.org
28
---
9
---
29
target/arm/cpu.h | 9 +--------
10
target/arm/cpu.h | 2 ++
30
target/arm/helper.c | 27 ++-------------------------
11
hw/intc/armv7m_nvic.c | 26 ++++++++++++++++++--------
31
target/arm/kvm32.c | 20 ++++++++++++++++++--
12
2 files changed, 20 insertions(+), 8 deletions(-)
32
target/arm/kvm64.c | 2 --
33
target/arm/machine.c | 2 +-
34
5 files changed, 22 insertions(+), 38 deletions(-)
35
13
36
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
37
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
38
--- a/target/arm/cpu.h
16
--- a/target/arm/cpu.h
39
+++ b/target/arm/cpu.h
17
+++ b/target/arm/cpu.h
40
@@ -XXX,XX +XXX,XX @@ bool write_list_to_cpustate(ARMCPU *cpu);
18
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_CCR, STKOFHFNMIGN, 10, 1)
41
/**
19
FIELD(V7M_CCR, DC, 16, 1)
42
* write_cpustate_to_list:
20
FIELD(V7M_CCR, IC, 17, 1)
43
* @cpu: ARMCPU
21
FIELD(V7M_CCR, BP, 18, 1)
44
- * @kvm_sync: true if this is for syncing back to KVM
22
+FIELD(V7M_CCR, LOB, 19, 1)
45
*
23
+FIELD(V7M_CCR, TRD, 20, 1)
46
* For each register listed in the ARMCPU cpreg_indexes list, write
24
47
* its value from the ARMCPUState structure into the cpreg_values list.
25
/* V7M SCR bits */
48
* This is used to copy info from TCG's working data structures into
26
FIELD(V7M_SCR, SLEEPONEXIT, 1, 1)
49
* KVM or for outbound migration.
27
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
50
*
51
- * @kvm_sync is true if we are doing this in order to sync the
52
- * register state back to KVM. In this case we will only update
53
- * values in the list if the previous list->cpustate sync actually
54
- * successfully wrote the CPU state. Otherwise we will keep the value
55
- * that is in the list.
56
- *
57
* Returns: true if all register values were read correctly,
58
* false if some register was unknown or could not be read.
59
* Note that we do not stop early on failure -- we will attempt
60
* reading all registers in the list.
61
*/
62
-bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
63
+bool write_cpustate_to_list(ARMCPU *cpu);
64
65
#define ARM_CPUID_TI915T 0x54029152
66
#define ARM_CPUID_TI925T 0x54029252
67
diff --git a/target/arm/helper.c b/target/arm/helper.c
68
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
69
--- a/target/arm/helper.c
29
--- a/hw/intc/armv7m_nvic.c
70
+++ b/target/arm/helper.c
30
+++ b/hw/intc/armv7m_nvic.c
71
@@ -XXX,XX +XXX,XX @@ static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
31
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
72
return true;
73
}
74
75
-bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync)
76
+bool write_cpustate_to_list(ARMCPU *cpu)
77
{
78
/* Write the coprocessor state from cpu->env to the (index,value) list. */
79
int i;
80
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync)
81
for (i = 0; i < cpu->cpreg_array_len; i++) {
82
uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
83
const ARMCPRegInfo *ri;
84
- uint64_t newval;
85
86
ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
87
if (!ri) {
88
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync)
89
if (ri->type & ARM_CP_NO_RAW) {
90
continue;
91
}
32
}
92
-
33
return cpu->env.v7m.scr[attrs.secure];
93
- newval = read_raw_cp_reg(&cpu->env, ri);
34
case 0xd14: /* Configuration Control. */
94
- if (kvm_sync) {
35
- /* The BFHFNMIGN bit is the only non-banked bit; we
95
- /*
36
- * keep it in the non-secure copy of the register.
96
- * Only sync if the previous list->cpustate sync succeeded.
37
+ /*
97
- * Rather than tracking the success/failure state for every
38
+ * Non-banked bits: BFHFNMIGN (stored in the NS copy of the register)
98
- * item in the list, we just recheck "does the raw write we must
39
+ * and TRD (stored in the S copy of the register)
99
- * have made in write_list_to_cpustate() read back OK" here.
40
*/
100
- */
41
val = cpu->env.v7m.ccr[attrs.secure];
101
- uint64_t oldval = cpu->cpreg_values[i];
42
val |= cpu->env.v7m.ccr[M_REG_NS] & R_V7M_CCR_BFHFNMIGN_MASK;
102
-
43
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
103
- if (oldval == newval) {
44
cpu->env.v7m.scr[attrs.secure] = value;
104
- continue;
45
break;
105
- }
46
case 0xd14: /* Configuration Control. */
106
-
47
+ {
107
- write_raw_cp_reg(&cpu->env, ri, oldval);
48
+ uint32_t mask;
108
- if (read_raw_cp_reg(&cpu->env, ri) != oldval) {
49
+
109
- continue;
50
if (!arm_feature(&cpu->env, ARM_FEATURE_M_MAIN)) {
110
- }
51
goto bad_offset;
111
-
112
- write_raw_cp_reg(&cpu->env, ri, newval);
113
- }
114
- cpu->cpreg_values[i] = newval;
115
+ cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
116
}
117
return ok;
118
}
119
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
120
index XXXXXXX..XXXXXXX 100644
121
--- a/target/arm/kvm32.c
122
+++ b/target/arm/kvm32.c
123
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
124
return ret;
125
}
126
127
- write_cpustate_to_list(cpu, true);
128
-
129
+ /* Note that we do not call write_cpustate_to_list()
130
+ * here, so we are only writing the tuple list back to
131
+ * KVM. This is safe because nothing can change the
132
+ * CPUARMState cp15 fields (in particular gdb accesses cannot)
133
+ * and so there are no changes to sync. In fact syncing would
134
+ * be wrong at this point: for a constant register where TCG and
135
+ * KVM disagree about its value, the preceding write_list_to_cpustate()
136
+ * would not have had any effect on the CPUARMState value (since the
137
+ * register is read-only), and a write_cpustate_to_list() here would
138
+ * then try to write the TCG value back into KVM -- this would either
139
+ * fail or incorrectly change the value the guest sees.
140
+ *
141
+ * If we ever want to allow the user to modify cp15 registers via
142
+ * the gdb stub, we would need to be more clever here (for instance
143
+ * tracking the set of registers kvm_arch_get_registers() successfully
144
+ * managed to update the CPUARMState with, and only allowing those
145
+ * to be written back up into the kernel).
146
+ */
147
if (!write_list_to_kvmstate(cpu, level)) {
148
return EINVAL;
149
}
150
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
151
index XXXXXXX..XXXXXXX 100644
152
--- a/target/arm/kvm64.c
153
+++ b/target/arm/kvm64.c
154
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
155
return ret;
156
}
157
158
- write_cpustate_to_list(cpu, true);
159
-
160
if (!write_list_to_kvmstate(cpu, level)) {
161
return EINVAL;
162
}
163
diff --git a/target/arm/machine.c b/target/arm/machine.c
164
index XXXXXXX..XXXXXXX 100644
165
--- a/target/arm/machine.c
166
+++ b/target/arm/machine.c
167
@@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque)
168
abort();
169
}
52
}
170
} else {
53
171
- if (!write_cpustate_to_list(cpu, false)) {
54
/* Enforce RAZ/WI on reserved and must-RAZ/WI bits */
172
+ if (!write_cpustate_to_list(cpu)) {
55
- value &= (R_V7M_CCR_STKALIGN_MASK |
173
/* This should never fail. */
56
- R_V7M_CCR_BFHFNMIGN_MASK |
174
abort();
57
- R_V7M_CCR_DIV_0_TRP_MASK |
175
}
58
- R_V7M_CCR_UNALIGN_TRP_MASK |
59
- R_V7M_CCR_USERSETMPEND_MASK |
60
- R_V7M_CCR_NONBASETHRDENA_MASK);
61
+ mask = R_V7M_CCR_STKALIGN_MASK |
62
+ R_V7M_CCR_BFHFNMIGN_MASK |
63
+ R_V7M_CCR_DIV_0_TRP_MASK |
64
+ R_V7M_CCR_UNALIGN_TRP_MASK |
65
+ R_V7M_CCR_USERSETMPEND_MASK |
66
+ R_V7M_CCR_NONBASETHRDENA_MASK;
67
+ if (arm_feature(&cpu->env, ARM_FEATURE_V8_1M) && attrs.secure) {
68
+ /* TRD is always RAZ/WI from NS */
69
+ mask |= R_V7M_CCR_TRD_MASK;
70
+ }
71
+ value &= mask;
72
73
if (arm_feature(&cpu->env, ARM_FEATURE_V8)) {
74
/* v8M makes NONBASETHRDENA and STKALIGN be RES1 */
75
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
76
77
cpu->env.v7m.ccr[attrs.secure] = value;
78
break;
79
+ }
80
case 0xd24: /* System Handler Control and State (SHCSR) */
81
if (!arm_feature(&cpu->env, ARM_FEATURE_V7)) {
82
goto bad_offset;
176
--
83
--
177
2.20.1
84
2.20.1
178
85
179
86
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/16] hw/misc/iotkit-sysctl: Correct typo in INITSVTOR0 register name
[PULL 32/36] target/arm: Implement CCR_S.TRD behaviour for SG insns
1
The iotkit-sysctl device has a register it names INITSVRTOR0.
1
v8.1M introduces a new TRD flag in the CCR register, which enables
2
This is actually a typo present in the IoTKit documentation
2
checking for stack frame integrity signatures on SG instructions.
3
and also in part of the SSE-200 documentation: it should be
3
Add the code in the SG insn implementation for the new behaviour.
4
INITSVTOR0 because it is specifying the initial value of the
5
Secure VTOR register in the CPU. Correct the typo.
6
4
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20190219125808.25174-6-peter.maydell@linaro.org
7
Message-id: 20201119215617.29887-24-peter.maydell@linaro.org
10
---
8
---
11
include/hw/misc/iotkit-sysctl.h | 2 +-
9
target/arm/m_helper.c | 86 +++++++++++++++++++++++++++++++++++++++++++
12
hw/misc/iotkit-sysctl.c | 16 ++++++++--------
10
1 file changed, 86 insertions(+)
13
2 files changed, 9 insertions(+), 9 deletions(-)
14
11
15
diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h
12
diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c
16
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/misc/iotkit-sysctl.h
14
--- a/target/arm/m_helper.c
18
+++ b/include/hw/misc/iotkit-sysctl.h
15
+++ b/target/arm/m_helper.c
19
@@ -XXX,XX +XXX,XX @@ typedef struct IoTKitSysCtl {
16
@@ -XXX,XX +XXX,XX @@ static bool v7m_read_half_insn(ARMCPU *cpu, ARMMMUIdx mmu_idx,
20
uint32_t reset_syndrome;
17
return true;
21
uint32_t reset_mask;
22
uint32_t gretreg;
23
- uint32_t initsvrtor0;
24
+ uint32_t initsvtor0;
25
uint32_t cpuwait;
26
uint32_t wicctrl;
27
} IoTKitSysCtl;
28
diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
29
index XXXXXXX..XXXXXXX 100644
30
--- a/hw/misc/iotkit-sysctl.c
31
+++ b/hw/misc/iotkit-sysctl.c
32
@@ -XXX,XX +XXX,XX @@ REG32(RESET_MASK, 0x104)
33
REG32(SWRESET, 0x108)
34
FIELD(SWRESET, SWRESETREQ, 9, 1)
35
REG32(GRETREG, 0x10c)
36
-REG32(INITSVRTOR0, 0x110)
37
+REG32(INITSVTOR0, 0x110)
38
REG32(CPUWAIT, 0x118)
39
REG32(BUSWAIT, 0x11c)
40
REG32(WICCTRL, 0x120)
41
@@ -XXX,XX +XXX,XX @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
42
case A_GRETREG:
43
r = s->gretreg;
44
break;
45
- case A_INITSVRTOR0:
46
- r = s->initsvrtor0;
47
+ case A_INITSVTOR0:
48
+ r = s->initsvtor0;
49
break;
50
case A_CPUWAIT:
51
r = s->cpuwait;
52
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
53
*/
54
s->gretreg = value;
55
break;
56
- case A_INITSVRTOR0:
57
- qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVRTOR0 unimplemented\n");
58
- s->initsvrtor0 = value;
59
+ case A_INITSVTOR0:
60
+ qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR0 unimplemented\n");
61
+ s->initsvtor0 = value;
62
break;
63
case A_CPUWAIT:
64
qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CPUWAIT unimplemented\n");
65
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_reset(DeviceState *dev)
66
s->reset_syndrome = 1;
67
s->reset_mask = 0;
68
s->gretreg = 0;
69
- s->initsvrtor0 = 0x10000000;
70
+ s->initsvtor0 = 0x10000000;
71
s->cpuwait = 0;
72
s->wicctrl = 0;
73
}
18
}
74
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription iotkit_sysctl_vmstate = {
19
75
VMSTATE_UINT32(reset_syndrome, IoTKitSysCtl),
20
+static bool v7m_read_sg_stack_word(ARMCPU *cpu, ARMMMUIdx mmu_idx,
76
VMSTATE_UINT32(reset_mask, IoTKitSysCtl),
21
+ uint32_t addr, uint32_t *spdata)
77
VMSTATE_UINT32(gretreg, IoTKitSysCtl),
22
+{
78
- VMSTATE_UINT32(initsvrtor0, IoTKitSysCtl),
23
+ /*
79
+ VMSTATE_UINT32(initsvtor0, IoTKitSysCtl),
24
+ * Read a word of data from the stack for the SG instruction,
80
VMSTATE_UINT32(cpuwait, IoTKitSysCtl),
25
+ * writing the value into *spdata. If the load succeeds, return
81
VMSTATE_UINT32(wicctrl, IoTKitSysCtl),
26
+ * true; otherwise pend an appropriate exception and return false.
82
VMSTATE_END_OF_LIST()
27
+ * (We can't use data load helpers here that throw an exception
28
+ * because of the context we're called in, which is halfway through
29
+ * arm_v7m_cpu_do_interrupt().)
30
+ */
31
+ CPUState *cs = CPU(cpu);
32
+ CPUARMState *env = &cpu->env;
33
+ MemTxAttrs attrs = {};
34
+ MemTxResult txres;
35
+ target_ulong page_size;
36
+ hwaddr physaddr;
37
+ int prot;
38
+ ARMMMUFaultInfo fi = {};
39
+ ARMCacheAttrs cacheattrs = {};
40
+ uint32_t value;
41
+
42
+ if (get_phys_addr(env, addr, MMU_DATA_LOAD, mmu_idx, &physaddr,
43
+ &attrs, &prot, &page_size, &fi, &cacheattrs)) {
44
+ /* MPU/SAU lookup failed */
45
+ if (fi.type == ARMFault_QEMU_SFault) {
46
+ qemu_log_mask(CPU_LOG_INT,
47
+ "...SecureFault during stack word read\n");
48
+ env->v7m.sfsr |= R_V7M_SFSR_AUVIOL_MASK | R_V7M_SFSR_SFARVALID_MASK;
49
+ env->v7m.sfar = addr;
50
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SECURE, false);
51
+ } else {
52
+ qemu_log_mask(CPU_LOG_INT,
53
+ "...MemManageFault during stack word read\n");
54
+ env->v7m.cfsr[M_REG_S] |= R_V7M_CFSR_DACCVIOL_MASK |
55
+ R_V7M_CFSR_MMARVALID_MASK;
56
+ env->v7m.mmfar[M_REG_S] = addr;
57
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM, false);
58
+ }
59
+ return false;
60
+ }
61
+ value = address_space_ldl(arm_addressspace(cs, attrs), physaddr,
62
+ attrs, &txres);
63
+ if (txres != MEMTX_OK) {
64
+ /* BusFault trying to read the data */
65
+ qemu_log_mask(CPU_LOG_INT,
66
+ "...BusFault during stack word read\n");
67
+ env->v7m.cfsr[M_REG_NS] |=
68
+ (R_V7M_CFSR_PRECISERR_MASK | R_V7M_CFSR_BFARVALID_MASK);
69
+ env->v7m.bfar = addr;
70
+ armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_BUS, false);
71
+ return false;
72
+ }
73
+
74
+ *spdata = value;
75
+ return true;
76
+}
77
+
78
static bool v7m_handle_execute_nsc(ARMCPU *cpu)
79
{
80
/*
81
@@ -XXX,XX +XXX,XX @@ static bool v7m_handle_execute_nsc(ARMCPU *cpu)
82
*/
83
qemu_log_mask(CPU_LOG_INT, "...really an SG instruction at 0x%08" PRIx32
84
", executing it\n", env->regs[15]);
85
+
86
+ if (cpu_isar_feature(aa32_m_sec_state, cpu) &&
87
+ !arm_v7m_is_handler_mode(env)) {
88
+ /*
89
+ * v8.1M exception stack frame integrity check. Note that we
90
+ * must perform the memory access even if CCR_S.TRD is zero
91
+ * and we aren't going to check what the data loaded is.
92
+ */
93
+ uint32_t spdata, sp;
94
+
95
+ /*
96
+ * We know we are currently NS, so the S stack pointers must be
97
+ * in other_ss_{psp,msp}, not in regs[13]/other_sp.
98
+ */
99
+ sp = v7m_using_psp(env) ? env->v7m.other_ss_psp : env->v7m.other_ss_msp;
100
+ if (!v7m_read_sg_stack_word(cpu, mmu_idx, sp, &spdata)) {
101
+ /* Stack access failed and an exception has been pended */
102
+ return false;
103
+ }
104
+
105
+ if (env->v7m.ccr[M_REG_S] & R_V7M_CCR_TRD_MASK) {
106
+ if (((spdata & ~1) == 0xfefa125a) ||
107
+ !(env->v7m.control[M_REG_S] & 1)) {
108
+ goto gen_invep;
109
+ }
110
+ }
111
+ }
112
+
113
env->regs[14] &= ~1;
114
env->v7m.control[M_REG_S] &= ~R_V7M_CONTROL_SFPA_MASK;
115
switch_v7m_security_state(env, true);
83
--
116
--
84
2.20.1
117
2.20.1
85
118
86
119
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/16] hw/arm/armsse: Wire up the MHUs
[PULL 33/36] hw/intc/armv7m_nvic: Fix "return from inactive handler" check
1
Create and connect the MHUs in the SSE-200.
1
In commit 077d7449100d824a4 we added code to handle the v8M
2
requirement that returns from NMI or HardFault forcibly deactivate
3
those exceptions regardless of what interrupt the guest is trying to
4
deactivate. Unfortunately this broke the handling of the "illegal
5
exception return because the returning exception number is not
6
active" check for those cases. In the pseudocode this test is done
7
on the exception the guest asks to return from, but because our
8
implementation was doing this in armv7m_nvic_complete_irq() after the
9
new "deactivate NMI/HardFault regardless" code we ended up doing the
10
test on the VecInfo for that exception instead, which usually meant
11
failing to raise the illegal exception return fault.
12
13
In the case for "configurable exception targeting the opposite
14
security state" we detected the illegal-return case but went ahead
15
and deactivated the VecInfo anyway, which is wrong because that is
16
the VecInfo for the other security state.
17
18
Rearrange the code so that we first identify the illegal return
19
cases, then see if we really need to deactivate NMI or HardFault
20
instead, and finally do the deactivation.
2
21
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
23
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20190219125808.25174-3-peter.maydell@linaro.org
24
Message-id: 20201119215617.29887-25-peter.maydell@linaro.org
6
---
25
---
7
include/hw/arm/armsse.h | 3 ++-
26
hw/intc/armv7m_nvic.c | 59 +++++++++++++++++++++++--------------------
8
hw/arm/armsse.c | 40 ++++++++++++++++++++++++++++++----------
27
1 file changed, 32 insertions(+), 27 deletions(-)
9
2 files changed, 32 insertions(+), 11 deletions(-)
10
28
11
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
29
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
12
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
13
--- a/include/hw/arm/armsse.h
31
--- a/hw/intc/armv7m_nvic.c
14
+++ b/include/hw/arm/armsse.h
32
+++ b/hw/intc/armv7m_nvic.c
15
@@ -XXX,XX +XXX,XX @@
33
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
16
#include "hw/misc/iotkit-sysctl.h"
34
{
17
#include "hw/misc/iotkit-sysinfo.h"
35
NVICState *s = (NVICState *)opaque;
18
#include "hw/misc/armsse-cpuid.h"
36
VecInfo *vec = NULL;
19
+#include "hw/misc/armsse-mhu.h"
37
- int ret;
20
#include "hw/misc/unimp.h"
38
+ int ret = 0;
21
#include "hw/or-irq.h"
39
22
#include "hw/core/split-irq.h"
40
assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
23
@@ -XXX,XX +XXX,XX @@ typedef struct ARMSSE {
41
24
IoTKitSysCtl sysctl;
42
+ trace_nvic_complete_irq(irq, secure);
25
IoTKitSysCtl sysinfo;
43
+
26
44
+ if (secure && exc_is_banked(irq)) {
27
- UnimplementedDeviceState mhu[2];
45
+ vec = &s->sec_vectors[irq];
28
+ ARMSSEMHU mhu[2];
46
+ } else {
29
UnimplementedDeviceState ppu[NUM_PPUS];
47
+ vec = &s->vectors[irq];
30
UnimplementedDeviceState cachectrl[SSE_MAX_CPUS];
48
+ }
31
UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS];
49
+
32
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
50
+ /*
33
index XXXXXXX..XXXXXXX 100644
51
+ * Identify illegal exception return cases. We can't immediately
34
--- a/hw/arm/armsse.c
52
+ * return at this point because we still need to deactivate
35
+++ b/hw/arm/armsse.c
53
+ * (either this exception or NMI/HardFault) first.
36
@@ -XXX,XX +XXX,XX @@ static void armsse_init(Object *obj)
54
+ */
37
sizeof(s->sysinfo), TYPE_IOTKIT_SYSINFO);
55
+ if (!exc_is_banked(irq) && exc_targets_secure(s, irq) != secure) {
38
if (info->has_mhus) {
56
+ /*
39
sysbus_init_child_obj(obj, "mhu0", &s->mhu[0], sizeof(s->mhu[0]),
57
+ * Return from a configurable exception targeting the opposite
40
- TYPE_UNIMPLEMENTED_DEVICE);
58
+ * security state from the one we're trying to complete it for.
41
+ TYPE_ARMSSE_MHU);
59
+ * Clear vec because it's not really the VecInfo for this
42
sysbus_init_child_obj(obj, "mhu1", &s->mhu[1], sizeof(s->mhu[1]),
60
+ * (irq, secstate) so we mustn't deactivate it.
43
- TYPE_UNIMPLEMENTED_DEVICE);
61
+ */
44
+ TYPE_ARMSSE_MHU);
62
+ ret = -1;
63
+ vec = NULL;
64
+ } else if (!vec->active) {
65
+ /* Return from an inactive interrupt */
66
+ ret = -1;
67
+ } else {
68
+ /* Legal return, we will return the RETTOBASE bit value to the caller */
69
+ ret = nvic_rettobase(s);
70
+ }
71
+
72
/*
73
* For negative priorities, v8M will forcibly deactivate the appropriate
74
* NMI or HardFault regardless of what interrupt we're being asked to
75
@@ -XXX,XX +XXX,XX @@ int armv7m_nvic_complete_irq(void *opaque, int irq, bool secure)
45
}
76
}
46
if (info->has_ppus) {
77
47
for (i = 0; i < info->num_cpus; i++) {
78
if (!vec) {
48
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
79
- if (secure && exc_is_banked(irq)) {
80
- vec = &s->sec_vectors[irq];
81
- } else {
82
- vec = &s->vectors[irq];
83
- }
84
- }
85
-
86
- trace_nvic_complete_irq(irq, secure);
87
-
88
- if (!vec->active) {
89
- /* Tell the caller this was an illegal exception return */
90
- return -1;
91
- }
92
-
93
- /*
94
- * If this is a configurable exception and it is currently
95
- * targeting the opposite security state from the one we're trying
96
- * to complete it for, this counts as an illegal exception return.
97
- * We still need to deactivate whatever vector the logic above has
98
- * selected, though, as it might not be the same as the one for the
99
- * requested exception number.
100
- */
101
- if (!exc_is_banked(irq) && exc_targets_secure(s, irq) != secure) {
102
- ret = -1;
103
- } else {
104
- ret = nvic_rettobase(s);
105
+ return ret;
49
}
106
}
50
107
51
if (info->has_mhus) {
108
vec->active = 0;
52
- for (i = 0; i < ARRAY_SIZE(s->mhu); i++) {
53
- char *name;
54
- char *port;
55
+ /*
56
+ * An SSE-200 with only one CPU should have only one MHU created,
57
+ * with the region where the second MHU usually is being RAZ/WI.
58
+ * We don't implement that SSE-200 config; if we want to support
59
+ * it then this code needs to be enhanced to handle creating the
60
+ * RAZ/WI region instead of the second MHU.
61
+ */
62
+ assert(info->num_cpus == ARRAY_SIZE(s->mhu));
63
+
64
+ for (i = 0; i < ARRAY_SIZE(s->mhu); i++) {
65
+ char *port;
66
+ int cpunum;
67
+ SysBusDevice *mhu_sbd = SYS_BUS_DEVICE(&s->mhu[i]);
68
69
- name = g_strdup_printf("MHU%d", i);
70
- qdev_prop_set_string(DEVICE(&s->mhu[i]), "name", name);
71
- qdev_prop_set_uint64(DEVICE(&s->mhu[i]), "size", 0x1000);
72
object_property_set_bool(OBJECT(&s->mhu[i]), true,
73
"realized", &err);
74
- g_free(name);
75
if (err) {
76
error_propagate(errp, err);
77
return;
78
}
79
port = g_strdup_printf("port[%d]", i + 3);
80
- mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mhu[i]), 0);
81
+ mr = sysbus_mmio_get_region(mhu_sbd, 0);
82
object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr),
83
port, &err);
84
g_free(port);
85
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
86
error_propagate(errp, err);
87
return;
88
}
89
+
90
+ /*
91
+ * Each MHU has an irq line for each CPU:
92
+ * MHU 0 irq line 0 -> CPU 0 IRQ 6
93
+ * MHU 0 irq line 1 -> CPU 1 IRQ 6
94
+ * MHU 1 irq line 0 -> CPU 0 IRQ 7
95
+ * MHU 1 irq line 1 -> CPU 1 IRQ 7
96
+ */
97
+ for (cpunum = 0; cpunum < info->num_cpus; cpunum++) {
98
+ DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]);
99
+
100
+ sysbus_connect_irq(mhu_sbd, cpunum,
101
+ qdev_get_gpio_in(cpudev, 6 + i));
102
+ }
103
}
104
}
105
106
--
109
--
107
2.20.1
110
2.20.1
108
111
109
112
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/16] target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions
[PULL 34/36] target/arm: Implement M-profile "minimal RAS implementation"
1
Instead of gating the A32/T32 FP16 conversion instructions on
1
For v8.1M the architecture mandates that CPUs must provide at
2
the ARM_FEATURE_VFP_FP16 flag, switch to our new approach of
2
least the "minimal RAS implementation" from the Reliability,
3
looking at ID register bits. In this case MVFR1 fields FPHP
3
Availability and Serviceability extension. This consists of:
4
and SIMDHP indicate the presence of these insns.
4
* an ESB instruction which is a NOP
5
5
-- since it is in the HINT space we need only add a comment
6
This change doesn't alter behaviour for any of our CPUs.
6
* an RFSR register which will RAZ/WI
7
* a RAZ/WI AIRCR.IESB bit
8
-- the code which handles writes to AIRCR does not allow setting
9
of RES0 bits, so we already treat this as RAZ/WI; add a comment
10
noting that this is deliberate
11
* minimal implementation of the RAS register block at 0xe0005000
12
-- this will be in a subsequent commit
13
* setting the ID_PFR0.RAS field to 0b0010
14
-- we will do this when we add the Cortex-M55 CPU model
7
15
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
17
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20190222170936.13268-2-peter.maydell@linaro.org
18
Message-id: 20201119215617.29887-26-peter.maydell@linaro.org
11
---
19
---
12
target/arm/cpu.h | 37 ++++++++++++++++++++++++++++++++++++-
20
target/arm/cpu.h | 14 ++++++++++++++
13
target/arm/cpu.c | 2 --
21
target/arm/t32.decode | 4 ++++
14
target/arm/kvm32.c | 3 ---
22
hw/intc/armv7m_nvic.c | 13 +++++++++++++
15
target/arm/translate.c | 26 ++++++++++++++++++--------
23
3 files changed, 31 insertions(+)
16
4 files changed, 54 insertions(+), 14 deletions(-)
17
24
18
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
25
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
19
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/cpu.h
27
--- a/target/arm/cpu.h
21
+++ b/target/arm/cpu.h
28
+++ b/target/arm/cpu.h
22
@@ -XXX,XX +XXX,XX @@ FIELD(ID_DFR0, MPROFDBG, 20, 4)
29
@@ -XXX,XX +XXX,XX @@ FIELD(ID_MMFR4, LSM, 20, 4)
23
FIELD(ID_DFR0, PERFMON, 24, 4)
30
FIELD(ID_MMFR4, CCIDX, 24, 4)
24
FIELD(ID_DFR0, TRACEFILT, 28, 4)
31
FIELD(ID_MMFR4, EVT, 28, 4)
25
32
26
+FIELD(MVFR0, SIMDREG, 0, 4)
33
+FIELD(ID_PFR0, STATE0, 0, 4)
27
+FIELD(MVFR0, FPSP, 4, 4)
34
+FIELD(ID_PFR0, STATE1, 4, 4)
28
+FIELD(MVFR0, FPDP, 8, 4)
35
+FIELD(ID_PFR0, STATE2, 8, 4)
29
+FIELD(MVFR0, FPTRAP, 12, 4)
36
+FIELD(ID_PFR0, STATE3, 12, 4)
30
+FIELD(MVFR0, FPDIVIDE, 16, 4)
37
+FIELD(ID_PFR0, CSV2, 16, 4)
31
+FIELD(MVFR0, FPSQRT, 20, 4)
38
+FIELD(ID_PFR0, AMU, 20, 4)
32
+FIELD(MVFR0, FPSHVEC, 24, 4)
39
+FIELD(ID_PFR0, DIT, 24, 4)
33
+FIELD(MVFR0, FPROUND, 28, 4)
40
+FIELD(ID_PFR0, RAS, 28, 4)
34
+
41
+
35
+FIELD(MVFR1, FPFTZ, 0, 4)
42
FIELD(ID_PFR1, PROGMOD, 0, 4)
36
+FIELD(MVFR1, FPDNAN, 4, 4)
43
FIELD(ID_PFR1, SECURITY, 4, 4)
37
+FIELD(MVFR1, SIMDLS, 8, 4)
44
FIELD(ID_PFR1, MPROGMOD, 8, 4)
38
+FIELD(MVFR1, SIMDINT, 12, 4)
45
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_predinv(const ARMISARegisters *id)
39
+FIELD(MVFR1, SIMDSP, 16, 4)
46
return FIELD_EX32(id->id_isar6, ID_ISAR6, SPECRES) != 0;
40
+FIELD(MVFR1, SIMDHP, 20, 4)
41
+FIELD(MVFR1, FPHP, 24, 4)
42
+FIELD(MVFR1, SIMDFMAC, 28, 4)
43
+
44
+FIELD(MVFR2, SIMDMISC, 0, 4)
45
+FIELD(MVFR2, FPMISC, 4, 4)
46
+
47
QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
48
49
/* If adding a feature bit which corresponds to a Linux ELF
50
@@ -XXX,XX +XXX,XX @@ enum arm_features {
51
ARM_FEATURE_THUMB2,
52
ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */
53
ARM_FEATURE_VFP3,
54
- ARM_FEATURE_VFP_FP16,
55
ARM_FEATURE_NEON,
56
ARM_FEATURE_M, /* Microcontroller profile. */
57
ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
58
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
59
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
60
}
47
}
61
48
62
+/*
49
+static inline bool isar_feature_aa32_ras(const ARMISARegisters *id)
63
+ * We always set the FP and SIMD FP16 fields to indicate identical
64
+ * levels of support (assuming SIMD is implemented at all), so
65
+ * we only need one set of accessors.
66
+ */
67
+static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id)
68
+{
50
+{
69
+ return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 0;
51
+ return FIELD_EX32(id->id_pfr0, ID_PFR0, RAS) != 0;
70
+}
52
+}
71
+
53
+
72
+static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
54
static inline bool isar_feature_aa32_mprofile(const ARMISARegisters *id)
73
+{
55
{
74
+ return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1;
56
return FIELD_EX32(id->id_pfr1, ID_PFR1, MPROGMOD) != 0;
75
+}
57
diff --git a/target/arm/t32.decode b/target/arm/t32.decode
58
index XXXXXXX..XXXXXXX 100644
59
--- a/target/arm/t32.decode
60
+++ b/target/arm/t32.decode
61
@@ -XXX,XX +XXX,XX @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .... @rdm
62
# SEV 1111 0011 1010 1111 1000 0000 0000 0100
63
# SEVL 1111 0011 1010 1111 1000 0000 0000 0101
64
65
+ # For M-profile minimal-RAS ESB can be a NOP, which is the
66
+ # default behaviour since it is in the hint space.
67
+ # ESB 1111 0011 1010 1111 1000 0000 0001 0000
76
+
68
+
77
/*
69
# The canonical nop ends in 0000 0000, but the whole rest
78
* 64-bit feature tests via id registers.
70
# of the space is "reserved hint, behaves as nop".
79
*/
71
NOP 1111 0011 1010 1111 1000 0000 ---- ----
80
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
72
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
81
index XXXXXXX..XXXXXXX 100644
73
index XXXXXXX..XXXXXXX 100644
82
--- a/target/arm/cpu.c
74
--- a/hw/intc/armv7m_nvic.c
83
+++ b/target/arm/cpu.c
75
+++ b/hw/intc/armv7m_nvic.c
84
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
76
@@ -XXX,XX +XXX,XX @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs)
77
return 0;
78
}
79
return cpu->env.v7m.sfar;
80
+ case 0xf04: /* RFSR */
81
+ if (!cpu_isar_feature(aa32_ras, cpu)) {
82
+ goto bad_offset;
83
+ }
84
+ /* We provide minimal-RAS only: RFSR is RAZ/WI */
85
+ return 0;
86
case 0xf34: /* FPCCR */
87
if (!cpu_isar_feature(aa32_vfp_simd, cpu)) {
88
return 0;
89
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
90
R_V7M_AIRCR_PRIGROUP_SHIFT,
91
R_V7M_AIRCR_PRIGROUP_LENGTH);
92
}
93
+ /* AIRCR.IESB is RAZ/WI because we implement only minimal RAS */
94
if (attrs.secure) {
95
/* These bits are only writable by secure */
96
cpu->env.v7m.aircr = value &
97
@@ -XXX,XX +XXX,XX @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value,
98
}
99
break;
85
}
100
}
86
if (arm_feature(env, ARM_FEATURE_VFP4)) {
101
+ case 0xf04: /* RFSR */
87
set_feature(env, ARM_FEATURE_VFP3);
102
+ if (!cpu_isar_feature(aa32_ras, cpu)) {
88
- set_feature(env, ARM_FEATURE_VFP_FP16);
103
+ goto bad_offset;
89
}
104
+ }
90
if (arm_feature(env, ARM_FEATURE_VFP3)) {
105
+ /* We provide minimal-RAS only: RFSR is RAZ/WI */
91
set_feature(env, ARM_FEATURE_VFP);
106
+ break;
92
@@ -XXX,XX +XXX,XX @@ static void cortex_a9_initfn(Object *obj)
107
case 0xf34: /* FPCCR */
93
cpu->dtb_compatible = "arm,cortex-a9";
108
if (cpu_isar_feature(aa32_vfp_simd, cpu)) {
94
set_feature(&cpu->env, ARM_FEATURE_V7);
109
/* Not all bits here are banked. */
95
set_feature(&cpu->env, ARM_FEATURE_VFP3);
96
- set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
97
set_feature(&cpu->env, ARM_FEATURE_NEON);
98
set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
99
set_feature(&cpu->env, ARM_FEATURE_EL3);
100
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
101
index XXXXXXX..XXXXXXX 100644
102
--- a/target/arm/kvm32.c
103
+++ b/target/arm/kvm32.c
104
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
105
if (extract32(id_pfr0, 12, 4) == 1) {
106
set_feature(&features, ARM_FEATURE_THUMB2EE);
107
}
108
- if (extract32(ahcf->isar.mvfr1, 20, 4) == 1) {
109
- set_feature(&features, ARM_FEATURE_VFP_FP16);
110
- }
111
if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
112
set_feature(&features, ARM_FEATURE_NEON);
113
}
114
diff --git a/target/arm/translate.c b/target/arm/translate.c
115
index XXXXXXX..XXXXXXX 100644
116
--- a/target/arm/translate.c
117
+++ b/target/arm/translate.c
118
@@ -XXX,XX +XXX,XX @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
119
* UNPREDICTABLE if bit 8 is set prior to ARMv8
120
* (we choose to UNDEF)
121
*/
122
- if ((dp && !arm_dc_feature(s, ARM_FEATURE_V8)) ||
123
- !arm_dc_feature(s, ARM_FEATURE_VFP_FP16)) {
124
- return 1;
125
+ if (dp) {
126
+ if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
127
+ return 1;
128
+ }
129
+ } else {
130
+ if (!dc_isar_feature(aa32_fp16_spconv, s)) {
131
+ return 1;
132
+ }
133
}
134
rm_is_dp = false;
135
break;
136
case 0x06: /* vcvtb.f16.f32, vcvtb.f16.f64 */
137
case 0x07: /* vcvtt.f16.f32, vcvtt.f16.f64 */
138
- if ((dp && !arm_dc_feature(s, ARM_FEATURE_V8)) ||
139
- !arm_dc_feature(s, ARM_FEATURE_VFP_FP16)) {
140
- return 1;
141
+ if (dp) {
142
+ if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
143
+ return 1;
144
+ }
145
+ } else {
146
+ if (!dc_isar_feature(aa32_fp16_spconv, s)) {
147
+ return 1;
148
+ }
149
}
150
rd_is_dp = false;
151
break;
152
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
153
TCGv_ptr fpst;
154
TCGv_i32 ahp;
155
156
- if (!arm_dc_feature(s, ARM_FEATURE_VFP_FP16) ||
157
+ if (!dc_isar_feature(aa32_fp16_spconv, s) ||
158
q || (rm & 1)) {
159
return 1;
160
}
161
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
162
{
163
TCGv_ptr fpst;
164
TCGv_i32 ahp;
165
- if (!arm_dc_feature(s, ARM_FEATURE_VFP_FP16) ||
166
+ if (!dc_isar_feature(aa32_fp16_spconv, s) ||
167
q || (rd & 1)) {
168
return 1;
169
}
170
--
110
--
171
2.20.1
111
2.20.1
172
112
173
113
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/16] hw/arm/iotkit-sysctl: Add SSE-200 registers
[PULL 35/36] hw/intc/armv7m_nvic: Implement read/write for RAS register block
1
The SYSCTL block in the SSE-200 has some extra registers that
1
The RAS feature has a block of memory-mapped registers at offset
2
are not present in the IoTKit version. Add these registers
2
0x5000 within the PPB. For a "minimal RAS" implementation we provide
3
(as reads-as-written stubs), enabled by a new QOM property.
3
no error records and so the only registers that exist in the block
4
are ERRIIDR and ERRDEVID.
5
6
The "RAZ/WI for privileged, BusFault for nonprivileged" behaviour
7
of the "nvic-default" region is actually valid for minimal-RAS,
8
so the main benefit of providing an explicit implementation of
9
the register block is more accurate LOG_UNIMP messages, and a
10
framework for where we could add a real RAS implementation later
11
if necessary.
4
12
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20190219125808.25174-7-peter.maydell@linaro.org
15
Message-id: 20201119215617.29887-27-peter.maydell@linaro.org
8
---
16
---
9
include/hw/misc/iotkit-sysctl.h | 20 +++
17
include/hw/intc/armv7m_nvic.h | 1 +
10
hw/arm/armsse.c | 2 +
18
hw/intc/armv7m_nvic.c | 56 +++++++++++++++++++++++++++++++++++
11
hw/misc/iotkit-sysctl.c | 245 +++++++++++++++++++++++++++++++-
19
2 files changed, 57 insertions(+)
12
3 files changed, 262 insertions(+), 5 deletions(-)
13
20
14
diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h
21
diff --git a/include/hw/intc/armv7m_nvic.h b/include/hw/intc/armv7m_nvic.h
15
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
16
--- a/include/hw/misc/iotkit-sysctl.h
23
--- a/include/hw/intc/armv7m_nvic.h
17
+++ b/include/hw/misc/iotkit-sysctl.h
24
+++ b/include/hw/intc/armv7m_nvic.h
18
@@ -XXX,XX +XXX,XX @@
25
@@ -XXX,XX +XXX,XX @@ struct NVICState {
19
* "system control register" blocks.
26
MemoryRegion sysreg_ns_mem;
20
*
27
MemoryRegion systickmem;
21
* QEMU interface:
28
MemoryRegion systick_ns_mem;
22
+ * + QOM property "SYS_VERSION": value of the SYS_VERSION register of the
29
+ MemoryRegion ras_mem;
23
+ * system information block of the SSE
30
MemoryRegion container;
24
+ * (used to identify whether to provide SSE-200-only registers)
31
MemoryRegion defaultmem;
25
* + sysbus MMIO region 0: the system information register bank
32
26
* + sysbus MMIO region 1: the system control register bank
33
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
27
*/
34
index XXXXXXX..XXXXXXX 100644
28
@@ -XXX,XX +XXX,XX @@ typedef struct IoTKitSysCtl {
35
--- a/hw/intc/armv7m_nvic.c
29
uint32_t initsvtor0;
36
+++ b/hw/intc/armv7m_nvic.c
30
uint32_t cpuwait;
37
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps nvic_systick_ops = {
31
uint32_t wicctrl;
38
.endianness = DEVICE_NATIVE_ENDIAN,
32
+ uint32_t scsecctrl;
39
};
33
+ uint32_t fclk_div;
40
34
+ uint32_t sysclk_div;
35
+ uint32_t clock_force;
36
+ uint32_t initsvtor1;
37
+ uint32_t nmi_enable;
38
+ uint32_t ewctrl;
39
+ uint32_t pdcm_pd_sys_sense;
40
+ uint32_t pdcm_pd_sram0_sense;
41
+ uint32_t pdcm_pd_sram1_sense;
42
+ uint32_t pdcm_pd_sram2_sense;
43
+ uint32_t pdcm_pd_sram3_sense;
44
+
41
+
45
+ /* Properties */
42
+static MemTxResult ras_read(void *opaque, hwaddr addr,
46
+ uint32_t sys_version;
43
+ uint64_t *data, unsigned size,
44
+ MemTxAttrs attrs)
45
+{
46
+ if (attrs.user) {
47
+ return MEMTX_ERROR;
48
+ }
47
+
49
+
48
+ bool is_sse200;
50
+ switch (addr) {
49
} IoTKitSysCtl;
51
+ case 0xe10: /* ERRIIDR */
50
52
+ /* architect field = Arm; product/variant/revision 0 */
51
#endif
53
+ *data = 0x43b;
52
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/hw/arm/armsse.c
55
+++ b/hw/arm/armsse.c
56
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
57
/* System information registers */
58
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysinfo), 0, 0x40020000);
59
/* System control registers */
60
+ object_property_set_int(OBJECT(&s->sysctl), info->sys_version,
61
+ "SYS_VERSION", &err);
62
object_property_set_bool(OBJECT(&s->sysctl), true, "realized", &err);
63
if (err) {
64
error_propagate(errp, err);
65
diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
66
index XXXXXXX..XXXXXXX 100644
67
--- a/hw/misc/iotkit-sysctl.c
68
+++ b/hw/misc/iotkit-sysctl.c
69
@@ -XXX,XX +XXX,XX @@
70
*/
71
72
#include "qemu/osdep.h"
73
+#include "qemu/bitops.h"
74
#include "qemu/log.h"
75
#include "trace.h"
76
#include "qapi/error.h"
77
@@ -XXX,XX +XXX,XX @@
78
REG32(SECDBGSTAT, 0x0)
79
REG32(SECDBGSET, 0x4)
80
REG32(SECDBGCLR, 0x8)
81
+REG32(SCSECCTRL, 0xc)
82
+REG32(FCLK_DIV, 0x10)
83
+REG32(SYSCLK_DIV, 0x14)
84
+REG32(CLOCK_FORCE, 0x18)
85
REG32(RESET_SYNDROME, 0x100)
86
REG32(RESET_MASK, 0x104)
87
REG32(SWRESET, 0x108)
88
FIELD(SWRESET, SWRESETREQ, 9, 1)
89
REG32(GRETREG, 0x10c)
90
REG32(INITSVTOR0, 0x110)
91
+REG32(INITSVTOR1, 0x114)
92
REG32(CPUWAIT, 0x118)
93
-REG32(BUSWAIT, 0x11c)
94
+REG32(NMI_ENABLE, 0x11c) /* BUSWAIT in IoTKit */
95
REG32(WICCTRL, 0x120)
96
+REG32(EWCTRL, 0x124)
97
+REG32(PDCM_PD_SYS_SENSE, 0x200)
98
+REG32(PDCM_PD_SRAM0_SENSE, 0x20c)
99
+REG32(PDCM_PD_SRAM1_SENSE, 0x210)
100
+REG32(PDCM_PD_SRAM2_SENSE, 0x214)
101
+REG32(PDCM_PD_SRAM3_SENSE, 0x218)
102
REG32(PID4, 0xfd0)
103
REG32(PID5, 0xfd4)
104
REG32(PID6, 0xfd8)
105
@@ -XXX,XX +XXX,XX @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
106
case A_SECDBGSTAT:
107
r = s->secure_debug;
108
break;
109
+ case A_SCSECCTRL:
110
+ if (!s->is_sse200) {
111
+ goto bad_offset;
112
+ }
113
+ r = s->scsecctrl;
114
+ break;
54
+ break;
115
+ case A_FCLK_DIV:
55
+ case 0xfc8: /* ERRDEVID */
116
+ if (!s->is_sse200) {
56
+ /* Minimal RAS: we implement 0 error record indexes */
117
+ goto bad_offset;
57
+ *data = 0;
118
+ }
119
+ r = s->fclk_div;
120
+ break;
58
+ break;
121
+ case A_SYSCLK_DIV:
59
+ default:
122
+ if (!s->is_sse200) {
60
+ qemu_log_mask(LOG_UNIMP, "Read RAS register offset 0x%x\n",
123
+ goto bad_offset;
61
+ (uint32_t)addr);
124
+ }
62
+ *data = 0;
125
+ r = s->sysclk_div;
126
+ break;
63
+ break;
127
+ case A_CLOCK_FORCE:
128
+ if (!s->is_sse200) {
129
+ goto bad_offset;
130
+ }
131
+ r = s->clock_force;
132
+ break;
133
case A_RESET_SYNDROME:
134
r = s->reset_syndrome;
135
break;
136
@@ -XXX,XX +XXX,XX @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
137
case A_INITSVTOR0:
138
r = s->initsvtor0;
139
break;
140
+ case A_INITSVTOR1:
141
+ if (!s->is_sse200) {
142
+ goto bad_offset;
143
+ }
144
+ r = s->initsvtor1;
145
+ break;
146
case A_CPUWAIT:
147
r = s->cpuwait;
148
break;
149
- case A_BUSWAIT:
150
- /* In IoTKit BUSWAIT is reserved, R/O, zero */
151
- r = 0;
152
+ case A_NMI_ENABLE:
153
+ /* In IoTKit this is named BUSWAIT but is marked reserved, R/O, zero */
154
+ if (!s->is_sse200) {
155
+ r = 0;
156
+ break;
157
+ }
158
+ r = s->nmi_enable;
159
break;
160
case A_WICCTRL:
161
r = s->wicctrl;
162
break;
163
+ case A_EWCTRL:
164
+ if (!s->is_sse200) {
165
+ goto bad_offset;
166
+ }
167
+ r = s->ewctrl;
168
+ break;
169
+ case A_PDCM_PD_SYS_SENSE:
170
+ if (!s->is_sse200) {
171
+ goto bad_offset;
172
+ }
173
+ r = s->pdcm_pd_sys_sense;
174
+ break;
175
+ case A_PDCM_PD_SRAM0_SENSE:
176
+ if (!s->is_sse200) {
177
+ goto bad_offset;
178
+ }
179
+ r = s->pdcm_pd_sram0_sense;
180
+ break;
181
+ case A_PDCM_PD_SRAM1_SENSE:
182
+ if (!s->is_sse200) {
183
+ goto bad_offset;
184
+ }
185
+ r = s->pdcm_pd_sram1_sense;
186
+ break;
187
+ case A_PDCM_PD_SRAM2_SENSE:
188
+ if (!s->is_sse200) {
189
+ goto bad_offset;
190
+ }
191
+ r = s->pdcm_pd_sram2_sense;
192
+ break;
193
+ case A_PDCM_PD_SRAM3_SENSE:
194
+ if (!s->is_sse200) {
195
+ goto bad_offset;
196
+ }
197
+ r = s->pdcm_pd_sram3_sense;
198
+ break;
199
case A_PID4 ... A_CID3:
200
r = sysctl_id[(offset - A_PID4) / 4];
201
break;
202
@@ -XXX,XX +XXX,XX @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
203
r = 0;
204
break;
205
default:
206
+ bad_offset:
207
qemu_log_mask(LOG_GUEST_ERROR,
208
"IoTKit SysCtl read: bad offset %x\n", (int)offset);
209
r = 0;
210
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
211
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
212
}
213
break;
214
- case A_BUSWAIT: /* In IoTKit BUSWAIT is reserved, R/O, zero */
215
+ case A_SCSECCTRL:
216
+ if (!s->is_sse200) {
217
+ goto bad_offset;
218
+ }
219
+ qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SCSECCTRL unimplemented\n");
220
+ s->scsecctrl = value;
221
+ break;
222
+ case A_FCLK_DIV:
223
+ if (!s->is_sse200) {
224
+ goto bad_offset;
225
+ }
226
+ qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl FCLK_DIV unimplemented\n");
227
+ s->fclk_div = value;
228
+ break;
229
+ case A_SYSCLK_DIV:
230
+ if (!s->is_sse200) {
231
+ goto bad_offset;
232
+ }
233
+ qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SYSCLK_DIV unimplemented\n");
234
+ s->sysclk_div = value;
235
+ break;
236
+ case A_CLOCK_FORCE:
237
+ if (!s->is_sse200) {
238
+ goto bad_offset;
239
+ }
240
+ qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CLOCK_FORCE unimplemented\n");
241
+ s->clock_force = value;
242
+ break;
243
+ case A_INITSVTOR1:
244
+ if (!s->is_sse200) {
245
+ goto bad_offset;
246
+ }
247
+ qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR1 unimplemented\n");
248
+ s->initsvtor1 = value;
249
+ break;
250
+ case A_EWCTRL:
251
+ if (!s->is_sse200) {
252
+ goto bad_offset;
253
+ }
254
+ qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl EWCTRL unimplemented\n");
255
+ s->ewctrl = value;
256
+ break;
257
+ case A_PDCM_PD_SYS_SENSE:
258
+ if (!s->is_sse200) {
259
+ goto bad_offset;
260
+ }
261
+ qemu_log_mask(LOG_UNIMP,
262
+ "IoTKit SysCtl PDCM_PD_SYS_SENSE unimplemented\n");
263
+ s->pdcm_pd_sys_sense = value;
264
+ break;
265
+ case A_PDCM_PD_SRAM0_SENSE:
266
+ if (!s->is_sse200) {
267
+ goto bad_offset;
268
+ }
269
+ qemu_log_mask(LOG_UNIMP,
270
+ "IoTKit SysCtl PDCM_PD_SRAM0_SENSE unimplemented\n");
271
+ s->pdcm_pd_sram0_sense = value;
272
+ break;
273
+ case A_PDCM_PD_SRAM1_SENSE:
274
+ if (!s->is_sse200) {
275
+ goto bad_offset;
276
+ }
277
+ qemu_log_mask(LOG_UNIMP,
278
+ "IoTKit SysCtl PDCM_PD_SRAM1_SENSE unimplemented\n");
279
+ s->pdcm_pd_sram1_sense = value;
280
+ break;
281
+ case A_PDCM_PD_SRAM2_SENSE:
282
+ if (!s->is_sse200) {
283
+ goto bad_offset;
284
+ }
285
+ qemu_log_mask(LOG_UNIMP,
286
+ "IoTKit SysCtl PDCM_PD_SRAM2_SENSE unimplemented\n");
287
+ s->pdcm_pd_sram2_sense = value;
288
+ break;
289
+ case A_PDCM_PD_SRAM3_SENSE:
290
+ if (!s->is_sse200) {
291
+ goto bad_offset;
292
+ }
293
+ qemu_log_mask(LOG_UNIMP,
294
+ "IoTKit SysCtl PDCM_PD_SRAM3_SENSE unimplemented\n");
295
+ s->pdcm_pd_sram3_sense = value;
296
+ break;
297
+ case A_NMI_ENABLE:
298
+ /* In IoTKit this is BUSWAIT: reserved, R/O, zero */
299
+ if (!s->is_sse200) {
300
+ goto ro_offset;
301
+ }
302
+ qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE unimplemented\n");
303
+ s->nmi_enable = value;
304
+ break;
305
case A_SECDBGSTAT:
306
case A_PID4 ... A_CID3:
307
+ ro_offset:
308
qemu_log_mask(LOG_GUEST_ERROR,
309
"IoTKit SysCtl write: write of RO offset %x\n",
310
(int)offset);
311
break;
312
default:
313
+ bad_offset:
314
qemu_log_mask(LOG_GUEST_ERROR,
315
"IoTKit SysCtl write: bad offset %x\n", (int)offset);
316
break;
317
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_reset(DeviceState *dev)
318
s->reset_mask = 0;
319
s->gretreg = 0;
320
s->initsvtor0 = 0x10000000;
321
+ s->initsvtor1 = 0x10000000;
322
s->cpuwait = 0;
323
s->wicctrl = 0;
324
+ s->scsecctrl = 0;
325
+ s->fclk_div = 0;
326
+ s->sysclk_div = 0;
327
+ s->clock_force = 0;
328
+ s->nmi_enable = 0;
329
+ s->ewctrl = 0;
330
+ s->pdcm_pd_sys_sense = 0x7f;
331
+ s->pdcm_pd_sram0_sense = 0;
332
+ s->pdcm_pd_sram1_sense = 0;
333
+ s->pdcm_pd_sram2_sense = 0;
334
+ s->pdcm_pd_sram3_sense = 0;
335
}
336
337
static void iotkit_sysctl_init(Object *obj)
338
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_init(Object *obj)
339
sysbus_init_mmio(sbd, &s->iomem);
340
}
341
342
+static void iotkit_sysctl_realize(DeviceState *dev, Error **errp)
343
+{
344
+ IoTKitSysCtl *s = IOTKIT_SYSCTL(dev);
345
+
346
+ /* The top 4 bits of the SYS_VERSION register tell us if we're an SSE-200 */
347
+ if (extract32(s->sys_version, 28, 4) == 2) {
348
+ s->is_sse200 = true;
349
+ }
64
+ }
65
+ return MEMTX_OK;
350
+}
66
+}
351
+
67
+
352
+static bool sse200_needed(void *opaque)
68
+static MemTxResult ras_write(void *opaque, hwaddr addr,
69
+ uint64_t value, unsigned size,
70
+ MemTxAttrs attrs)
353
+{
71
+{
354
+ IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque);
72
+ if (attrs.user) {
73
+ return MEMTX_ERROR;
74
+ }
355
+
75
+
356
+ return s->is_sse200;
76
+ switch (addr) {
77
+ default:
78
+ qemu_log_mask(LOG_UNIMP, "Write to RAS register offset 0x%x\n",
79
+ (uint32_t)addr);
80
+ break;
81
+ }
82
+ return MEMTX_OK;
357
+}
83
+}
358
+
84
+
359
+static const VMStateDescription iotkit_sysctl_sse200_vmstate = {
85
+static const MemoryRegionOps ras_ops = {
360
+ .name = "iotkit-sysctl/sse-200",
86
+ .read_with_attrs = ras_read,
361
+ .version_id = 1,
87
+ .write_with_attrs = ras_write,
362
+ .minimum_version_id = 1,
88
+ .endianness = DEVICE_NATIVE_ENDIAN,
363
+ .needed = sse200_needed,
364
+ .fields = (VMStateField[]) {
365
+ VMSTATE_UINT32(scsecctrl, IoTKitSysCtl),
366
+ VMSTATE_UINT32(fclk_div, IoTKitSysCtl),
367
+ VMSTATE_UINT32(sysclk_div, IoTKitSysCtl),
368
+ VMSTATE_UINT32(clock_force, IoTKitSysCtl),
369
+ VMSTATE_UINT32(initsvtor1, IoTKitSysCtl),
370
+ VMSTATE_UINT32(nmi_enable, IoTKitSysCtl),
371
+ VMSTATE_UINT32(pdcm_pd_sys_sense, IoTKitSysCtl),
372
+ VMSTATE_UINT32(pdcm_pd_sram0_sense, IoTKitSysCtl),
373
+ VMSTATE_UINT32(pdcm_pd_sram1_sense, IoTKitSysCtl),
374
+ VMSTATE_UINT32(pdcm_pd_sram2_sense, IoTKitSysCtl),
375
+ VMSTATE_UINT32(pdcm_pd_sram3_sense, IoTKitSysCtl),
376
+ VMSTATE_END_OF_LIST()
377
+ }
378
+};
89
+};
379
+
90
+
380
static const VMStateDescription iotkit_sysctl_vmstate = {
91
/*
381
.name = "iotkit-sysctl",
92
* Unassigned portions of the PPB space are RAZ/WI for privileged
382
.version_id = 1,
93
* accesses, and fault for non-privileged accesses.
383
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription iotkit_sysctl_vmstate = {
94
@@ -XXX,XX +XXX,XX @@ static void armv7m_nvic_realize(DeviceState *dev, Error **errp)
384
VMSTATE_UINT32(cpuwait, IoTKitSysCtl),
95
&s->systick_ns_mem, 1);
385
VMSTATE_UINT32(wicctrl, IoTKitSysCtl),
386
VMSTATE_END_OF_LIST()
387
+ },
388
+ .subsections = (const VMStateDescription*[]) {
389
+ &iotkit_sysctl_sse200_vmstate,
390
+ NULL
391
}
96
}
392
};
97
393
98
+ if (cpu_isar_feature(aa32_ras, s->cpu)) {
394
+static Property iotkit_sysctl_props[] = {
99
+ memory_region_init_io(&s->ras_mem, OBJECT(s),
395
+ DEFINE_PROP_UINT32("SYS_VERSION", IoTKitSysCtl, sys_version, 0),
100
+ &ras_ops, s, "nvic_ras", 0x1000);
396
+ DEFINE_PROP_END_OF_LIST()
101
+ memory_region_add_subregion(&s->container, 0x5000, &s->ras_mem);
397
+};
102
+ }
398
+
103
+
399
static void iotkit_sysctl_class_init(ObjectClass *klass, void *data)
104
sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->container);
400
{
401
DeviceClass *dc = DEVICE_CLASS(klass);
402
403
dc->vmsd = &iotkit_sysctl_vmstate;
404
dc->reset = iotkit_sysctl_reset;
405
+ dc->props = iotkit_sysctl_props;
406
+ dc->realize = iotkit_sysctl_realize;
407
}
105
}
408
106
409
static const TypeInfo iotkit_sysctl_info = {
410
--
107
--
411
2.20.1
108
2.20.1
412
109
413
110
diff view generated by jsdifflib
New patch
[PULL 36/36] hw/arm/armv7m: Correct typo in QOM object name
1
Correct a typo in the name we give the NVIC object.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20201119215617.29887-28-peter.maydell@linaro.org
7
---
8
hw/arm/armv7m.c | 2 +-
9
1 file changed, 1 insertion(+), 1 deletion(-)
10
11
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/hw/arm/armv7m.c
14
+++ b/hw/arm/armv7m.c
15
@@ -XXX,XX +XXX,XX @@ static void armv7m_instance_init(Object *obj)
16
17
memory_region_init(&s->container, obj, "armv7m-container", UINT64_MAX);
18
19
- object_initialize_child(obj, "nvnic", &s->nvic, TYPE_NVIC);
20
+ object_initialize_child(obj, "nvic", &s->nvic, TYPE_NVIC);
21
object_property_add_alias(obj, "num-irq",
22
OBJECT(&s->nvic), "num-irq");
23
24
--
25
2.20.1
26
27
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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