Series comparison

-[Qemu-devel] [PULL 00/16] target-arm queue
+[Qemu-devel] [PULL 00/12] target-arm queue
-The following changes since commit adf2e451f357e993f173ba9b4176dbf3e65fee7e:
+Not very much here, but several people have fallen over
 the vector operation segfault bug, so let's get the fix
 into master.
-  Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2019-02-26 19:04:47 +0000)
+thanks
 -- PMM
 The following changes since commit d418238dca7b4e0b124135827ead3076233052b1:
   Merge remote-tracking branch 'remotes/rth/tags/pull-rng-20190522' into staging (2019-05-23 12:57:17 +0100)
 are available in the Git repository at:
-  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190228-1
+  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190523
-for you to fetch changes up to 1c9af3a9e05c1607a36df4943f8f5393d7621a91:
+for you to fetch changes up to 98e4f4fdb8ea05d840f51f47125924c2bb9df2df:
-  linux-user: Enable HWCAP_ASIMDFHM, HWCAP_JSCVT (2019-02-28 11:03:05 +0000)
+  hw/arm/exynos4210: QOM'ify the Exynos4210 SoC (2019-05-23 14:47:44 +0100)
 ----------------------------------------------------------------
 target-arm queue:
- * add MHU and dual-core support to Musca boards
+ * exynos4210: QOM'ify the Exynos4210 SoC
- * refactor some VFP insns to be gated by ID registers
+ * exynos4210: Add DMA support for the Exynos4210
- * Revert "arm: Allow system registers for KVM guests to be changed by QEMU code"
+ * arm_gicv3: Fix writes to ICC_CTLR_EL3
- * Implement ARMv8.2-FHM extension
+ * arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
- * Advertise JSCVT via HWCAP for linux-user
+ * target/arm: Fix vector operation segfault
  * target/arm: Minor improvements to BFXIL, EXTR
 ----------------------------------------------------------------
-Peter Maydell (11):
+Alistair Francis (1):
-      hw/misc/armsse-mhu.c: Model the SSE-200 Message Handling Unit
+      target/arm: Fix vector operation segfault
       hw/arm/armsse: Wire up the MHUs
       target/arm/cpu: Allow init-svtor property to be set after realize
       target/arm/arm-powerctl: Add new arm_set_cpu_on_and_reset()
       hw/misc/iotkit-sysctl: Correct typo in INITSVTOR0 register name
       hw/arm/iotkit-sysctl: Add SSE-200 registers
       hw/arm/iotkit-sysctl: Implement CPUWAIT and INITSVTOR*
       hw/arm/armsse: Unify init-svtor and cpuwait handling
       target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions
       target/arm: Gate "miscellaneous FP" insns by ID register field
       Revert "arm: Allow system registers for KVM guests to be changed by QEMU code"
-Richard Henderson (5):
+Guenter Roeck (1):
-      target/arm: Add helpers for FMLAL
+      hw/arm/exynos4210: Add DMA support for the Exynos4210
       target/arm: Implement FMLAL and FMLSL for aarch64
       target/arm: Implement VFMAL and VFMSL for aarch32
       target/arm: Enable ARMv8.2-FHM for -cpu max
       linux-user: Enable HWCAP_ASIMDFHM, HWCAP_JSCVT
- hw/misc/Makefile.objs           |   1 +
+Peter Maydell (5):
- include/hw/arm/armsse.h         |   3 +-
+      arm: Move system_clock_scale to armv7m_systick.h
- include/hw/misc/armsse-mhu.h    |  44 ++++++
+      arm: Remove unnecessary includes of hw/arm/arm.h
- include/hw/misc/iotkit-sysctl.h |  25 +++-
+      arm: Rename hw/arm/arm.h to hw/arm/boot.h
- target/arm/arm-powerctl.h       |  16 +++
+      hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
- target/arm/cpu.h                |  76 +++++++++--
+      hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3
  target/arm/helper.h             |   9 ++
  hw/arm/armsse.c                 |  91 +++++++++----
  hw/misc/armsse-mhu.c            | 198 +++++++++++++++++++++++++++
  hw/misc/iotkit-sysctl.c         | 294 ++++++++++++++++++++++++++++++++++++++--
  linux-user/elfload.c            |   2 +
  target/arm/arm-powerctl.c       |  56 ++++++++
  target/arm/cpu.c                |  32 ++++-
  target/arm/cpu64.c              |   2 +
  target/arm/helper.c             |  27 +---
  target/arm/kvm32.c              |  23 +++-
  target/arm/kvm64.c              |   2 -
  target/arm/machine.c            |   2 +-
  target/arm/translate-a64.c      |  49 ++++++-
  target/arm/translate.c          | 180 ++++++++++++++++--------
  target/arm/vec_helper.c         | 148 ++++++++++++++++++++
  MAINTAINERS                     |   2 +
  default-configs/arm-softmmu.mak |   1 +
  hw/misc/trace-events            |   4 +
 files changed, 1139 insertions(+), 148 deletions(-)
  create mode 100644 include/hw/misc/armsse-mhu.h
  create mode 100644 hw/misc/armsse-mhu.c
+Philippe Mathieu-Daudé (3):
+      hw/arm/exynos4: Remove unuseful debug code
+      hw/arm/exynos4: Use the IEC binary prefix definitions
+      hw/arm/exynos4210: QOM'ify the Exynos4210 SoC
+Richard Henderson (2):
+      target/arm: Use extract2 for EXTR
+      target/arm: Simplify BFXIL expansion
+ include/hw/arm/allwinner-a10.h    |  2 +-
+ include/hw/arm/aspeed_soc.h       |  1 -
+ include/hw/arm/bcm2836.h          |  1 -
+ include/hw/arm/{arm.h => boot.h}  | 12 +++------
+ include/hw/arm/exynos4210.h       |  9 +++++--
+ include/hw/arm/fsl-imx25.h        |  2 +-
+ include/hw/arm/fsl-imx31.h        |  2 +-
+ include/hw/arm/fsl-imx6.h         |  2 +-
+ include/hw/arm/fsl-imx6ul.h       |  2 +-
+ include/hw/arm/fsl-imx7.h         |  2 +-
+ include/hw/arm/virt.h             |  2 +-
+ include/hw/arm/xlnx-versal.h      |  2 +-
+ include/hw/arm/xlnx-zynqmp.h      |  2 +-
+ include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++
+ hw/arm/armsse.c                   |  2 +-
+ hw/arm/armv7m.c                   |  2 +-
+ hw/arm/aspeed.c                   |  2 +-
+ hw/arm/boot.c                     |  2 +-
+ hw/arm/collie.c                   |  2 +-
+ hw/arm/exynos4210.c               | 54 ++++++++++++++++++++++++++++++++++++---
+ hw/arm/exynos4_boards.c           | 40 ++++++++---------------------
+ hw/arm/highbank.c                 |  2 +-
+ hw/arm/integratorcp.c             |  2 +-
+ hw/arm/mainstone.c                |  2 +-
+ hw/arm/microbit.c                 |  2 +-
+ hw/arm/mps2-tz.c                  |  2 +-
+ hw/arm/mps2.c                     |  2 +-
+ hw/arm/msf2-soc.c                 |  1 -
+ hw/arm/msf2-som.c                 |  2 +-
+ hw/arm/musca.c                    |  2 +-
+ hw/arm/musicpal.c                 |  2 +-
+ hw/arm/netduino2.c                |  2 +-
+ hw/arm/nrf51_soc.c                |  2 +-
+ hw/arm/nseries.c                  |  2 +-
+ hw/arm/omap1.c                    |  2 +-
+ hw/arm/omap2.c                    |  2 +-
+ hw/arm/omap_sx1.c                 |  2 +-
+ hw/arm/palm.c                     |  2 +-
+ hw/arm/raspi.c                    |  2 +-
+ hw/arm/realview.c                 |  2 +-
+ hw/arm/spitz.c                    |  2 +-
+ hw/arm/stellaris.c                |  2 +-
+ hw/arm/stm32f205_soc.c            |  2 +-
+ hw/arm/strongarm.c                |  2 +-
+ hw/arm/tosa.c                     |  2 +-
+ hw/arm/versatilepb.c              |  2 +-
+ hw/arm/vexpress.c                 |  2 +-
+ hw/arm/virt.c                     |  2 +-
+ hw/arm/xilinx_zynq.c              |  2 +-
+ hw/arm/xlnx-versal.c              |  2 +-
+ hw/arm/z2.c                       |  2 +-
+ hw/intc/arm_gicv3_cpuif.c         |  6 ++---
+ hw/intc/armv7m_nvic.c             |  1 -
+ target/arm/arm-semi.c             |  1 -
+ target/arm/cpu.c                  |  1 -
+ target/arm/cpu64.c                |  1 -
+ target/arm/kvm.c                  |  1 -
+ target/arm/kvm32.c                |  1 -
+ target/arm/kvm64.c                |  1 -
+ target/arm/translate-a64.c        | 44 ++++++++++++++++---------------
+ target/arm/translate.c            |  4 +--
+files changed, 164 insertions(+), 123 deletions(-)
+ rename include/hw/arm/{arm.h => boot.h} (96%)

-[Qemu-devel] [PULL 15/16] target/arm: Enable ARMv8.2-FHM for -cpu max
+[Qemu-devel] [PULL 01/12] target/arm: Use extract2 for EXTR
 From: Richard Henderson <richard.henderson@linaro.org>
+This is, after all, how we implement extract2 in tcg/aarch64.
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20190219222952.22183-5-richard.henderson@linaro.org
+Message-id: 20190514011129.11330-2-richard.henderson@linaro.org
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.c   | 1 +
+ target/arm/translate-a64.c | 38 ++++++++++++++++++++------------------
- target/arm/cpu64.c | 2 ++
+file changed, 20 insertions(+), 18 deletions(-)
 files changed, 3 insertions(+)
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
+diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
+--- a/target/arm/translate-a64.c
-+++ b/target/arm/cpu.c
++++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
+@@ -XXX,XX +XXX,XX @@ static void disas_extract(DisasContext *s, uint32_t insn)
-             t = cpu->isar.id_isar6;
+             } else {
-             t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
+                 tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));
-             t = FIELD_DP32(t, ID_ISAR6, DP, 1);
+             }
-+            t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
+-        } else if (rm == rn) { /* ROR */
-             cpu->isar.id_isar6 = t;
+-            tcg_rm = cpu_reg(s, rm);
+-            if (sf) {
-             t = cpu->id_mmfr4;
+-                tcg_gen_rotri_i64(tcg_rd, tcg_rm, imm);
-diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
+-            } else {
-index XXXXXXX..XXXXXXX 100644
+-                TCGv_i32 tmp = tcg_temp_new_i32();
---- a/target/arm/cpu64.c
+-                tcg_gen_extrl_i64_i32(tmp, tcg_rm);
-+++ b/target/arm/cpu64.c
+-                tcg_gen_rotri_i32(tmp, tmp, imm);
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
+-                tcg_gen_extu_i32_i64(tcg_rd, tmp);
-         t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
+-                tcg_temp_free_i32(tmp);
-         t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
+-            }
-         t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
+         } else {
-+        t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
+-            tcg_rm = read_cpu_reg(s, rm, sf);
-         cpu->isar.id_aa64isar0 = t;
+-            tcg_rn = read_cpu_reg(s, rn, sf);
+-            tcg_gen_shri_i64(tcg_rm, tcg_rm, imm);
-         t = cpu->isar.id_aa64isar1;
+-            tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm);
-@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
+-            tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn);
-         u = cpu->isar.id_isar6;
+-            if (!sf) {
-         u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
+-                tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
-         u = FIELD_DP32(u, ID_ISAR6, DP, 1);
++            tcg_rm = cpu_reg(s, rm);
-+        u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
++            tcg_rn = cpu_reg(s, rn);
-         cpu->isar.id_isar6 = u;
++
++            if (sf) {
-         /*
++                /* Specialization to ROR happens in EXTRACT2.  */
 +                tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, imm);
 +            } else {
 +                TCGv_i32 t0 = tcg_temp_new_i32();
 +
 +                tcg_gen_extrl_i64_i32(t0, tcg_rm);
 +                if (rm == rn) {
 +                    tcg_gen_rotri_i32(t0, t0, imm);
 +                } else {
 +                    TCGv_i32 t1 = tcg_temp_new_i32();
 +                    tcg_gen_extrl_i64_i32(t1, tcg_rn);
 +                    tcg_gen_extract2_i32(t0, t0, t1, imm);
 +                    tcg_temp_free_i32(t1);
 +                }
 +                tcg_gen_extu_i32_i64(tcg_rd, t0);
 +                tcg_temp_free_i32(t0);
              }
          }
      }
 --
 .20.1

-[Qemu-devel] [PULL 13/16] target/arm: Implement FMLAL and FMLSL for aarch64
+[Qemu-devel] [PULL 02/12] target/arm: Simplify BFXIL expansion
 From: Richard Henderson <richard.henderson@linaro.org>
+The mask implied by the extract is redundant with the one
+implied by the deposit.  Also, fix spelling of BFXIL.
+Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
 Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20190219222952.22183-3-richard.henderson@linaro.org
+Message-id: 20190514011129.11330-3-richard.henderson@linaro.org
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.h           |  5 ++++
+ target/arm/translate-a64.c | 6 +++---
- target/arm/translate-a64.c | 49 +++++++++++++++++++++++++++++++++++++-
+file changed, 3 insertions(+), 3 deletions(-)
 files changed, 53 insertions(+), 1 deletion(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
-+++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_dp(const ARMISARegisters *id)
-     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0;
- }
-+static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id)
-+{
-+    return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0;
-+}
-+
- static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
- {
-     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate-a64.c
 +++ b/target/arm/translate-a64.c
-@@ -XXX,XX +XXX,XX @@ static void disas_simd_3same_float(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
-         if (!fp_access_check(s)) {
+             tcg_gen_extract_i64(tcg_rd, tcg_tmp, ri, len);
              return;
          }
--
+-        /* opc == 1, BXFIL fall through to deposit */
-         handle_3same_float(s, size, elements, fpopcode, rd, rn, rm);
+-        tcg_gen_extract_i64(tcg_tmp, tcg_tmp, ri, len);
-         return;
++        /* opc == 1, BFXIL fall through to deposit */
-+
++        tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri);
-+    case 0x1d: /* FMLAL  */
+         pos = 0;
-+    case 0x3d: /* FMLSL  */
+     } else {
-+    case 0x59: /* FMLAL2 */
+         /* Handle the ri > si case with a deposit
-+    case 0x79: /* FMLSL2 */
+@@ -XXX,XX +XXX,XX @@ static void disas_bitfield(DisasContext *s, uint32_t insn)
-+        if (size & 1 || !dc_isar_feature(aa64_fhm, s)) {
+         len = ri;
 +            unallocated_encoding(s);
 +            return;
 +        }
 +        if (fp_access_check(s)) {
 +            int is_s = extract32(insn, 23, 1);
 +            int is_2 = extract32(insn, 29, 1);
 +            int data = (is_2 << 1) | is_s;
 +            tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
 +                               vec_full_reg_offset(s, rn),
 +                               vec_full_reg_offset(s, rm), cpu_env,
 +                               is_q ? 16 : 8, vec_full_reg_size(s),
 +                               data, gen_helper_gvec_fmlal_a64);
 +        }
 +        return;
 +
      default:
          unallocated_encoding(s);
          return;
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
          }
          is_fp = 2;
          break;
 +    case 0x00: /* FMLAL */
 +    case 0x04: /* FMLSL */
 +    case 0x18: /* FMLAL2 */
 +    case 0x1c: /* FMLSL2 */
 +        if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_fhm, s)) {
 +            unallocated_encoding(s);
 +            return;
 +        }
 +        size = MO_16;
 +        /* is_fp, but we pass cpu_env not fp_status.  */
 +        break;
      default:
          unallocated_encoding(s);
          return;
@@ -XXX,XX +XXX,XX @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
              tcg_temp_free_ptr(fpst);
          }
          return;
 +
 +    case 0x00: /* FMLAL */
 +    case 0x04: /* FMLSL */
 +    case 0x18: /* FMLAL2 */
 +    case 0x1c: /* FMLSL2 */
 +        {
 +            int is_s = extract32(opcode, 2, 1);
 +            int is_2 = u;
 +            int data = (index << 2) | (is_2 << 1) | is_s;
 +            tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
 +                               vec_full_reg_offset(s, rn),
 +                               vec_full_reg_offset(s, rm), cpu_env,
 +                               is_q ? 16 : 8, vec_full_reg_size(s),
 +                               data, gen_helper_gvec_fmlal_idx_a64);
 +        }
 +        return;
      }
-     if (size == 3) {
+-    if (opc == 1) { /* BFM, BXFIL */
 +    if (opc == 1) { /* BFM, BFXIL */
          tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len);
      } else {
          /* SBFM or UBFM: We start with zero, and we haven't modified
 --
 .20.1

-[Qemu-devel] [PULL 10/16] target/arm: Gate "miscellaneous FP" insns by ID register field
+[Qemu-devel] [PULL 03/12] target/arm: Fix vector operation segfault
-There is a set of VFP instructions which we implement in
+From: Alistair Francis <alistair.francis@wdc.com>
 disas_vfp_v8_insn() and gate on the ARM_FEATURE_V8 bit.
 These were all first introduced in v8 for A-profile, but in
 M-profile they appeared in v7M. Gate them on the MVFR2
 FPMisc field instead, and rename the function appropriately.
+Commit 89e68b575 "target/arm: Use vector operations for saturation"
+causes this abort() when booting QEMU ARM with a Cortex-A15:
+0x00007ffff4c2382f in raise () at /usr/lib/libc.so.6
+0x00007ffff4c0e672 in abort () at /usr/lib/libc.so.6
+0x00005555559c1839 in disas_neon_data_insn (insn=<optimized out>, s=<optimized out>) at ./target/arm/translate.c:6673
+0x00005555559c1839 in disas_neon_data_insn (s=<optimized out>, insn=<optimized out>) at ./target/arm/translate.c:6386
+0x00005555559cd8a4 in disas_arm_insn (insn=4081107068, s=0x7fffe59a9510) at ./target/arm/translate.c:9289
+0x00005555559cd8a4 in arm_tr_translate_insn (dcbase=0x7fffe59a9510, cpu=<optimized out>) at ./target/arm/translate.c:13612
+0x00005555558d1d39 in translator_loop (ops=0x5555561cc580 <arm_translator_ops>, db=0x7fffe59a9510, cpu=0x55555686a2f0, tb=<optimized out>, max_insns=<optimized out>) at ./accel/tcg/translator.c:96
+0x00005555559d10d4 in gen_intermediate_code (cpu=cpu@entry=0x55555686a2f0, tb=tb@entry=0x7fffd7840080 <code_gen_buffer+126091347>, max_insns=max_insns@entry=512) at ./target/arm/translate.c:13901
+0x00005555558d06b9 in tb_gen_code (cpu=cpu@entry=0x55555686a2f0, pc=3067096216, cs_base=0, flags=192, cflags=-16252928, cflags@entry=524288) at ./accel/tcg/translate-all.c:1736
+0x00005555558ce467 in tb_find (cf_mask=524288, tb_exit=1, last_tb=0x7fffd783e640 <code_gen_buffer+126084627>, cpu=0x1) at ./accel/tcg/cpu-exec.c:407
+0x00005555558ce467 in cpu_exec (cpu=cpu@entry=0x55555686a2f0) at ./accel/tcg/cpu-exec.c:728
+0x000055555588b0cf in tcg_cpu_exec (cpu=0x55555686a2f0) at ./cpus.c:1431
+0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=0x55555686a2f0) at ./cpus.c:1735
+0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=arg@entry=0x55555686a2f0) at ./cpus.c:1709
+0x0000555555d2629a in qemu_thread_start (args=<optimized out>) at ./util/qemu-thread-posix.c:502
+0x00007ffff4db8a92 in start_thread () at /usr/lib/libpthread.
+This patch ensures that we don't hit the abort() in the second switch
+case in disas_neon_data_insn() as we will return from the first case.
+Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
+Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
+Tested-by: Alex Bennée <alex.bennee@linaro.org>
+Message-id: ad91b397f360b2fc7f4087e476f7df5b04d42ddb.1558021877.git.alistair.francis@wdc.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20190222170936.13268-3-peter.maydell@linaro.org
 ---
- target/arm/cpu.h       | 20 ++++++++++++++++++++
+ target/arm/translate.c | 4 ++--
- target/arm/translate.c | 25 +++++++++++++------------
+file changed, 2 insertions(+), 2 deletions(-)
 files changed, 33 insertions(+), 12 deletions(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
-+++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
-     return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1;
- }
-+static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id)
-+{
-+    return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 1;
-+}
-+
-+static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id)
-+{
-+    return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 2;
-+}
-+
-+static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id)
-+{
-+    return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 3;
-+}
-+
-+static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
-+{
-+    return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >= 4;
-+}
-+
- /*
-  * 64-bit feature tests via id registers.
-  */
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/translate.c
 +++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static const uint8_t fp_decode_rm[] = {
+@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
-     FPROUNDING_NEGINF,
+             tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
- };
+                            rn_ofs, rm_ofs, vec_size, vec_size,
+                            (u ? uqadd_op : sqadd_op) + size);
--static int disas_vfp_v8_insn(DisasContext *s, uint32_t insn)
+-            break;
-+static int disas_vfp_misc_insn(DisasContext *s, uint32_t insn)
++            return 0;
- {
-     uint32_t rd, rn, rm, dp = extract32(insn, 8, 1);
+         case NEON_3R_VQSUB:
+             tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
--    if (!arm_dc_feature(s, ARM_FEATURE_V8)) {
+                            rn_ofs, rm_ofs, vec_size, vec_size,
--        return 1;
+                            (u ? uqsub_op : sqsub_op) + size);
--    }
+-            break;
--
++            return 0;
-     if (dp) {
-         VFP_DREG_D(rd, insn);
+         case NEON_3R_VMUL: /* VMUL */
-         VFP_DREG_N(rn, insn);
+             if (u) {
@@ -XXX,XX +XXX,XX @@ static int disas_vfp_v8_insn(DisasContext *s, uint32_t insn)
          rm = VFP_SREG_M(insn);
      }
 -    if ((insn & 0x0f800e50) == 0x0e000a00) {
 +    if ((insn & 0x0f800e50) == 0x0e000a00 && dc_isar_feature(aa32_vsel, s)) {
          return handle_vsel(insn, rd, rn, rm, dp);
 -    } else if ((insn & 0x0fb00e10) == 0x0e800a00) {
 +    } else if ((insn & 0x0fb00e10) == 0x0e800a00 &&
 +               dc_isar_feature(aa32_vminmaxnm, s)) {
          return handle_vminmaxnm(insn, rd, rn, rm, dp);
 -    } else if ((insn & 0x0fbc0ed0) == 0x0eb80a40) {
 +    } else if ((insn & 0x0fbc0ed0) == 0x0eb80a40 &&
 +               dc_isar_feature(aa32_vrint, s)) {
          /* VRINTA, VRINTN, VRINTP, VRINTM */
          int rounding = fp_decode_rm[extract32(insn, 16, 2)];
          return handle_vrint(insn, rd, rm, dp, rounding);
 -    } else if ((insn & 0x0fbc0e50) == 0x0ebc0a40) {
 +    } else if ((insn & 0x0fbc0e50) == 0x0ebc0a40 &&
 +               dc_isar_feature(aa32_vcvt_dr, s)) {
          /* VCVTA, VCVTN, VCVTP, VCVTM */
          int rounding = fp_decode_rm[extract32(insn, 16, 2)];
          return handle_vcvt(insn, rd, rm, dp, rounding);
@@ -XXX,XX +XXX,XX @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
      }
      if (extract32(insn, 28, 4) == 0xf) {
 -        /* Encodings with T=1 (Thumb) or unconditional (ARM):
 -         * only used in v8 and above.
 +        /*
 +         * Encodings with T=1 (Thumb) or unconditional (ARM):
 +         * only used for the "miscellaneous VFP features" added in v8A
 +         * and v7M (and gated on the MVFR2.FPMisc field).
           */
 -        return disas_vfp_v8_insn(s, insn);
 +        return disas_vfp_misc_insn(s, insn);
      }
      dp = ((insn & 0xf00) == 0xb00);
 --
 .20.1

-[Qemu-devel] [PULL 04/16] target/arm/arm-powerctl: Add new arm_set_cpu_on_and_reset()
+[Qemu-devel] [PULL 04/12] arm: Move system_clock_scale to armv7m_systick.h
-Currently the Arm arm-powerctl.h APIs allow:
+The system_clock_scale global is used only by the armv7m systick
- * arm_set_cpu_on(), which powers on a CPU and sets its
+device; move the extern declaration to the armv7m_systick.h header,
-   initial PC and other startup state
+and expand the comment to explain what it is and that it should
- * arm_reset_cpu(), which resets a CPU which is already on
+ideally be replaced with a different approach.
    (and fails if the CPU is powered off)
 but there is no way to say "power on a CPU as if it had
 just come out of reset and don't do anything else to it".
 Add a new function arm_set_cpu_on_and_reset(), which does this.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Message-id: 20190219125808.25174-5-peter.maydell@linaro.org
+Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Message-id: 20190516163857.6430-2-peter.maydell@linaro.org
 ---
- target/arm/arm-powerctl.h | 16 +++++++++++
+ include/hw/arm/arm.h              |  4 ----
- target/arm/arm-powerctl.c | 56 +++++++++++++++++++++++++++++++++++++++
+ include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++++++++
-files changed, 72 insertions(+)
+files changed, 22 insertions(+), 4 deletions(-)
-diff --git a/target/arm/arm-powerctl.h b/target/arm/arm-powerctl.h
+diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/arm-powerctl.h
+--- a/include/hw/arm/arm.h
-+++ b/target/arm/arm-powerctl.h
++++ b/include/hw/arm/arm.h
-@@ -XXX,XX +XXX,XX @@ int arm_set_cpu_off(uint64_t cpuid);
+@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
-  */
+                                             const struct arm_boot_info *info,
- int arm_reset_cpu(uint64_t cpuid);
+                                             hwaddr mvbar_addr);
 -/* Multiplication factor to convert from system clock ticks to qemu timer
 -   ticks.  */
 -extern int system_clock_scale;
 -
  #endif /* HW_ARM_H */
 diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/timer/armv7m_systick.h
 +++ b/include/hw/timer/armv7m_systick.h
@@ -XXX,XX +XXX,XX @@ typedef struct SysTickState {
      qemu_irq irq;
  } SysTickState;
 +/*
-+ * arm_set_cpu_on_and_reset:
++ * Multiplication factor to convert from system clock ticks to qemu timer
-+ * @cpuid: the id of the CPU we want to star
++ * ticks. This should be set (by board code, usually) to a value
 + * equal to NANOSECONDS_PER_SECOND / frq, where frq is the clock frequency
 + * in Hz of the CPU.
 + *
-+ * Start the cpu designated by @cpuid and put it through its normal
++ * This value is used by the systick device when it is running in
-+ * CPU reset process. The CPU will start in the way it is architected
++ * its "use the CPU clock" mode (ie when SYST_CSR.CLKSOURCE == 1) to
-+ * to start after a power-on reset.
++ * set how fast the timer should tick.
 + *
-+ * Returns: QEMU_ARM_POWERCTL_RET_SUCCESS on success.
++ * TODO: we should refactor this so that rather than using a global
-+ * QEMU_ARM_POWERCTL_INVALID_PARAM if there is no CPU with that ID.
++ * we use a device property or something similar. This is complicated
-+ * QEMU_ARM_POWERCTL_ALREADY_ON if the CPU is already on.
++ * because (a) the property would need to be plumbed through from the
-+ * QEMU_ARM_POWERCTL_ON_PENDING if the CPU is already partway through
++ * board code down through various layers to the systick device
-+ * powering on.
++ * and (b) the property needs to be modifiable after realize, because
 + * the stellaris board uses this to implement the behaviour where the
 + * guest can reprogram the PLL registers to downclock the CPU, and the
 + * systick device needs to react accordingly. Possibly this should
 + * be deferred until we have a good API for modelling clock trees.
 + */
-+int arm_set_cpu_on_and_reset(uint64_t cpuid);
++extern int system_clock_scale;
 +
  #endif
-diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/arm-powerctl.c
-+++ b/target/arm/arm-powerctl.c
-@@ -XXX,XX +XXX,XX @@ int arm_set_cpu_on(uint64_t cpuid, uint64_t entry, uint64_t context_id,
-     return QEMU_ARM_POWERCTL_RET_SUCCESS;
- }
-+static void arm_set_cpu_on_and_reset_async_work(CPUState *target_cpu_state,
-+                                                run_on_cpu_data data)
-+{
-+    ARMCPU *target_cpu = ARM_CPU(target_cpu_state);
-+
-+    /* Initialize the cpu we are turning on */
-+    cpu_reset(target_cpu_state);
-+    target_cpu_state->halted = 0;
-+
-+    /* Finally set the power status */
-+    assert(qemu_mutex_iothread_locked());
-+    target_cpu->power_state = PSCI_ON;
-+}
-+
-+int arm_set_cpu_on_and_reset(uint64_t cpuid)
-+{
-+    CPUState *target_cpu_state;
-+    ARMCPU *target_cpu;
-+
-+    assert(qemu_mutex_iothread_locked());
-+
-+    /* Retrieve the cpu we are powering up */
-+    target_cpu_state = arm_get_cpu_by_id(cpuid);
-+    if (!target_cpu_state) {
-+        /* The cpu was not found */
-+        return QEMU_ARM_POWERCTL_INVALID_PARAM;
-+    }
-+
-+    target_cpu = ARM_CPU(target_cpu_state);
-+    if (target_cpu->power_state == PSCI_ON) {
-+        qemu_log_mask(LOG_GUEST_ERROR,
-+                      "[ARM]%s: CPU %" PRId64 " is already on\n",
-+                      __func__, cpuid);
-+        return QEMU_ARM_POWERCTL_ALREADY_ON;
-+    }
-+
-+    /*
-+     * If another CPU has powered the target on we are in the state
-+     * ON_PENDING and additional attempts to power on the CPU should
-+     * fail (see 6.6 Implementation CPU_ON/CPU_OFF races in the PSCI
-+     * spec)
-+     */
-+    if (target_cpu->power_state == PSCI_ON_PENDING) {
-+        qemu_log_mask(LOG_GUEST_ERROR,
-+                      "[ARM]%s: CPU %" PRId64 " is already powering on\n",
-+                      __func__, cpuid);
-+        return QEMU_ARM_POWERCTL_ON_PENDING;
-+    }
-+
-+    async_run_on_cpu(target_cpu_state, arm_set_cpu_on_and_reset_async_work,
-+                     RUN_ON_CPU_NULL);
-+
-+    /* We are good to go */
-+    return QEMU_ARM_POWERCTL_RET_SUCCESS;
-+}
-+
- static void arm_set_cpu_off_async_work(CPUState *target_cpu_state,
-                                        run_on_cpu_data data)
- {
 --
 .20.1

-[Qemu-devel] [PULL 09/16] target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions
+[Qemu-devel] [PULL 05/12] arm: Remove unnecessary includes of hw/arm/arm.h
-Instead of gating the A32/T32 FP16 conversion instructions on
+The hw/arm/arm.h header now only includes declarations relating
-the ARM_FEATURE_VFP_FP16 flag, switch to our new approach of
+to boot.c code, so it is only needed by Arm board or SoC code.
-looking at ID register bits. In this case MVFR1 fields FPHP
+Remove some unnecessary inclusions of it from target/arm files
-and SIMDHP indicate the presence of these insns.
+and from hw/intc/armv7m_nvic.c.
 This change doesn't alter behaviour for any of our CPUs.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Message-id: 20190222170936.13268-2-peter.maydell@linaro.org
+Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Message-id: 20190516163857.6430-3-peter.maydell@linaro.org
 ---
- target/arm/cpu.h       | 37 ++++++++++++++++++++++++++++++++++++-
+ hw/intc/armv7m_nvic.c | 1 -
- target/arm/cpu.c       |  2 --
+ target/arm/arm-semi.c | 1 -
- target/arm/kvm32.c     |  3 ---
+ target/arm/cpu.c      | 1 -
- target/arm/translate.c | 26 ++++++++++++++++++--------
+ target/arm/cpu64.c    | 1 -
-files changed, 54 insertions(+), 14 deletions(-)
+ target/arm/kvm.c      | 1 -
  target/arm/kvm32.c    | 1 -
  target/arm/kvm64.c    | 1 -
 files changed, 7 deletions(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/hw/intc/armv7m_nvic.c
-+++ b/target/arm/cpu.h
++++ b/hw/intc/armv7m_nvic.c
-@@ -XXX,XX +XXX,XX @@ FIELD(ID_DFR0, MPROFDBG, 20, 4)
+@@ -XXX,XX +XXX,XX @@
- FIELD(ID_DFR0, PERFMON, 24, 4)
+ #include "cpu.h"
- FIELD(ID_DFR0, TRACEFILT, 28, 4)
+ #include "hw/sysbus.h"
+ #include "qemu/timer.h"
-+FIELD(MVFR0, SIMDREG, 0, 4)
+-#include "hw/arm/arm.h"
-+FIELD(MVFR0, FPSP, 4, 4)
+ #include "hw/intc/armv7m_nvic.h"
-+FIELD(MVFR0, FPDP, 8, 4)
+ #include "target/arm/cpu.h"
-+FIELD(MVFR0, FPTRAP, 12, 4)
+ #include "exec/exec-all.h"
-+FIELD(MVFR0, FPDIVIDE, 16, 4)
+diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
-+FIELD(MVFR0, FPSQRT, 20, 4)
+index XXXXXXX..XXXXXXX 100644
-+FIELD(MVFR0, FPSHVEC, 24, 4)
+--- a/target/arm/arm-semi.c
-+FIELD(MVFR0, FPROUND, 28, 4)
++++ b/target/arm/arm-semi.c
-+
+@@ -XXX,XX +XXX,XX @@
-+FIELD(MVFR1, FPFTZ, 0, 4)
+ #else
-+FIELD(MVFR1, FPDNAN, 4, 4)
+ #include "qemu-common.h"
-+FIELD(MVFR1, SIMDLS, 8, 4)
+ #include "exec/gdbstub.h"
-+FIELD(MVFR1, SIMDINT, 12, 4)
+-#include "hw/arm/arm.h"
-+FIELD(MVFR1, SIMDSP, 16, 4)
+ #include "qemu/cutils.h"
-+FIELD(MVFR1, SIMDHP, 20, 4)
+ #endif
-+FIELD(MVFR1, FPHP, 24, 4)
 +FIELD(MVFR1, SIMDFMAC, 28, 4)
 +
 +FIELD(MVFR2, SIMDMISC, 0, 4)
 +FIELD(MVFR2, FPMISC, 4, 4)
 +
  QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
  /* If adding a feature bit which corresponds to a Linux ELF
@@ -XXX,XX +XXX,XX @@ enum arm_features {
      ARM_FEATURE_THUMB2,
      ARM_FEATURE_PMSA,   /* no MMU; may have Memory Protection Unit */
      ARM_FEATURE_VFP3,
 -    ARM_FEATURE_VFP_FP16,
      ARM_FEATURE_NEON,
      ARM_FEATURE_M, /* Microcontroller profile.  */
      ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
      return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
  }
 +/*
 + * We always set the FP and SIMD FP16 fields to indicate identical
 + * levels of support (assuming SIMD is implemented at all), so
 + * we only need one set of accessors.
 + */
 +static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id)
 +{
 +    return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 0;
 +}
 +
 +static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
 +{
 +    return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1;
 +}
 +
  /*
   * 64-bit feature tests via id registers.
   */
 diff --git a/target/arm/cpu.c b/target/arm/cpu.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/cpu.c
 +++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
+@@ -XXX,XX +XXX,XX @@
-     }
+ #if !defined(CONFIG_USER_ONLY)
-     if (arm_feature(env, ARM_FEATURE_VFP4)) {
+ #include "hw/loader.h"
-         set_feature(env, ARM_FEATURE_VFP3);
+ #endif
--        set_feature(env, ARM_FEATURE_VFP_FP16);
+-#include "hw/arm/arm.h"
-     }
+ #include "sysemu/sysemu.h"
-     if (arm_feature(env, ARM_FEATURE_VFP3)) {
+ #include "sysemu/hw_accel.h"
-         set_feature(env, ARM_FEATURE_VFP);
+ #include "kvm_arm.h"
-@@ -XXX,XX +XXX,XX @@ static void cortex_a9_initfn(Object *obj)
+diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
-     cpu->dtb_compatible = "arm,cortex-a9";
+index XXXXXXX..XXXXXXX 100644
-     set_feature(&cpu->env, ARM_FEATURE_V7);
+--- a/target/arm/cpu64.c
-     set_feature(&cpu->env, ARM_FEATURE_VFP3);
++++ b/target/arm/cpu64.c
--    set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
+@@ -XXX,XX +XXX,XX @@
-     set_feature(&cpu->env, ARM_FEATURE_NEON);
+ #if !defined(CONFIG_USER_ONLY)
-     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
+ #include "hw/loader.h"
-     set_feature(&cpu->env, ARM_FEATURE_EL3);
+ #endif
 -#include "hw/arm/arm.h"
  #include "sysemu/sysemu.h"
  #include "sysemu/kvm.h"
  #include "kvm_arm.h"
 diff --git a/target/arm/kvm.c b/target/arm/kvm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm.c
 +++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@
  #include "cpu.h"
  #include "trace.h"
  #include "internals.h"
 -#include "hw/arm/arm.h"
  #include "hw/pci/pci.h"
  #include "exec/memattrs.h"
  #include "exec/address-spaces.h"
 diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
 index XXXXXXX..XXXXXXX 100644
 --- a/target/arm/kvm32.c
 +++ b/target/arm/kvm32.c
-@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
+@@ -XXX,XX +XXX,XX @@
-     if (extract32(id_pfr0, 12, 4) == 1) {
+ #include "sysemu/kvm.h"
-         set_feature(&features, ARM_FEATURE_THUMB2EE);
+ #include "kvm_arm.h"
-     }
+ #include "internals.h"
--    if (extract32(ahcf->isar.mvfr1, 20, 4) == 1) {
+-#include "hw/arm/arm.h"
--        set_feature(&features, ARM_FEATURE_VFP_FP16);
+ #include "qemu/log.h"
--    }
-     if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
+ static inline void set_feature(uint64_t *features, int feature)
-         set_feature(&features, ARM_FEATURE_NEON);
+diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
      }
 diff --git a/target/arm/translate.c b/target/arm/translate.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/translate.c
+--- a/target/arm/kvm64.c
-+++ b/target/arm/translate.c
++++ b/target/arm/kvm64.c
-@@ -XXX,XX +XXX,XX @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
+@@ -XXX,XX +XXX,XX @@
-                      * UNPREDICTABLE if bit 8 is set prior to ARMv8
+ #include "sysemu/kvm.h"
-                      * (we choose to UNDEF)
+ #include "kvm_arm.h"
-                      */
+ #include "internals.h"
--                    if ((dp && !arm_dc_feature(s, ARM_FEATURE_V8)) ||
+-#include "hw/arm/arm.h"
--                        !arm_dc_feature(s, ARM_FEATURE_VFP_FP16)) {
--                        return 1;
+ static bool have_guest_debug;
-+                    if (dp) {
 +                        if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
 +                            return 1;
 +                        }
 +                    } else {
 +                        if (!dc_isar_feature(aa32_fp16_spconv, s)) {
 +                            return 1;
 +                        }
                      }
                      rm_is_dp = false;
                      break;
                  case 0x06: /* vcvtb.f16.f32, vcvtb.f16.f64 */
                  case 0x07: /* vcvtt.f16.f32, vcvtt.f16.f64 */
 -                    if ((dp && !arm_dc_feature(s, ARM_FEATURE_V8)) ||
 -                        !arm_dc_feature(s, ARM_FEATURE_VFP_FP16)) {
 -                        return 1;
 +                    if (dp) {
 +                        if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
 +                            return 1;
 +                        }
 +                    } else {
 +                        if (!dc_isar_feature(aa32_fp16_spconv, s)) {
 +                            return 1;
 +                        }
                      }
                      rd_is_dp = false;
                      break;
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                      TCGv_ptr fpst;
                      TCGv_i32 ahp;
 -                    if (!arm_dc_feature(s, ARM_FEATURE_VFP_FP16) ||
 +                    if (!dc_isar_feature(aa32_fp16_spconv, s) ||
                          q || (rm & 1)) {
                          return 1;
                      }
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                  {
                      TCGv_ptr fpst;
                      TCGv_i32 ahp;
 -                    if (!arm_dc_feature(s, ARM_FEATURE_VFP_FP16) ||
 +                    if (!dc_isar_feature(aa32_fp16_spconv, s) ||
                          q || (rd & 1)) {
                          return 1;
                      }
 --
 .20.1

-[Qemu-devel] [PULL 08/16] hw/arm/armsse: Unify init-svtor and cpuwait handling
+[Qemu-devel] [PULL 06/12] arm: Rename hw/arm/arm.h to hw/arm/boot.h
-At the moment the handling of init-svtor and cpuwait initial
+The header file hw/arm/arm.h now includes only declarations
-values is split between armsse.c and iotkit-sysctl.c:
+relating to hw/arm/boot.c functionality. Rename it accordingly,
-the code in armsse.c sets the initial state of the CPU
+and adjust its header comment.
 object by setting the init-svtor and start-powered-off
 properties, but the iotkit-sysctl.c code has its own
 code setting the reset values of its registers (which are
 then used when updating the CPU when the guest makes
 runtime changes).
-Clean this up by making the armsse.c code set properties on the
+The bulk of this commit was created via
-iotkit-sysctl object to define the initial values of the
+ perl -pi -e 's|hw/arm/arm.h|hw/arm/boot.h|' hw/arm/*.c include/hw/arm/*.h
-registers, so they always match the initial CPU state,
-and update the comments in armsse.c accordingly.
+In a few cases we can just delete the #include:
 hw/arm/msf2-soc.c, include/hw/arm/aspeed_soc.h and
 include/hw/arm/bcm2836.h did not require it.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Message-id: 20190219125808.25174-9-peter.maydell@linaro.org
+Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Message-id: 20190516163857.6430-4-peter.maydell@linaro.org
 ---
- include/hw/misc/iotkit-sysctl.h |  3 ++
+ include/hw/arm/allwinner-a10.h   | 2 +-
- hw/arm/armsse.c                 | 49 +++++++++++++++++++++------------
+ include/hw/arm/aspeed_soc.h      | 1 -
- hw/misc/iotkit-sysctl.c         | 20 ++++++--------
+ include/hw/arm/bcm2836.h         | 1 -
-files changed, 42 insertions(+), 30 deletions(-)
+ include/hw/arm/{arm.h => boot.h} | 8 ++++----
  include/hw/arm/fsl-imx25.h       | 2 +-
  include/hw/arm/fsl-imx31.h       | 2 +-
  include/hw/arm/fsl-imx6.h        | 2 +-
  include/hw/arm/fsl-imx6ul.h      | 2 +-
  include/hw/arm/fsl-imx7.h        | 2 +-
  include/hw/arm/virt.h            | 2 +-
  include/hw/arm/xlnx-versal.h     | 2 +-
  include/hw/arm/xlnx-zynqmp.h     | 2 +-
  hw/arm/armsse.c                  | 2 +-
  hw/arm/armv7m.c                  | 2 +-
  hw/arm/aspeed.c                  | 2 +-
  hw/arm/boot.c                    | 2 +-
  hw/arm/collie.c                  | 2 +-
  hw/arm/exynos4210.c              | 2 +-
  hw/arm/exynos4_boards.c          | 2 +-
  hw/arm/highbank.c                | 2 +-
  hw/arm/integratorcp.c            | 2 +-
  hw/arm/mainstone.c               | 2 +-
  hw/arm/microbit.c                | 2 +-
  hw/arm/mps2-tz.c                 | 2 +-
  hw/arm/mps2.c                    | 2 +-
  hw/arm/msf2-soc.c                | 1 -
  hw/arm/msf2-som.c                | 2 +-
  hw/arm/musca.c                   | 2 +-
  hw/arm/musicpal.c                | 2 +-
  hw/arm/netduino2.c               | 2 +-
  hw/arm/nrf51_soc.c               | 2 +-
  hw/arm/nseries.c                 | 2 +-
  hw/arm/omap1.c                   | 2 +-
  hw/arm/omap2.c                   | 2 +-
  hw/arm/omap_sx1.c                | 2 +-
  hw/arm/palm.c                    | 2 +-
  hw/arm/raspi.c                   | 2 +-
  hw/arm/realview.c                | 2 +-
  hw/arm/spitz.c                   | 2 +-
  hw/arm/stellaris.c               | 2 +-
  hw/arm/stm32f205_soc.c           | 2 +-
  hw/arm/strongarm.c               | 2 +-
  hw/arm/tosa.c                    | 2 +-
  hw/arm/versatilepb.c             | 2 +-
  hw/arm/vexpress.c                | 2 +-
  hw/arm/virt.c                    | 2 +-
  hw/arm/xilinx_zynq.c             | 2 +-
  hw/arm/xlnx-versal.c             | 2 +-
  hw/arm/z2.c                      | 2 +-
 files changed, 49 insertions(+), 52 deletions(-)
  rename include/hw/arm/{arm.h => boot.h} (98%)
-diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h
+diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/misc/iotkit-sysctl.h
+--- a/include/hw/arm/allwinner-a10.h
-+++ b/include/hw/misc/iotkit-sysctl.h
++++ b/include/hw/arm/allwinner-a10.h
-@@ -XXX,XX +XXX,XX @@ typedef struct IoTKitSysCtl {
+@@ -XXX,XX +XXX,XX @@
+ #include "qemu-common.h"
-     /* Properties */
+ #include "qemu/error-report.h"
-     uint32_t sys_version;
+ #include "hw/char/serial.h"
-+    uint32_t cpuwait_rst;
+-#include "hw/arm/arm.h"
-+    uint32_t initsvtor0_rst;
++#include "hw/arm/boot.h"
-+    uint32_t initsvtor1_rst;
+ #include "hw/timer/allwinner-a10-pit.h"
+ #include "hw/intc/allwinner-a10-pic.h"
-     bool is_sse200;
+ #include "hw/net/allwinner_emac.h"
- } IoTKitSysCtl;
+diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/aspeed_soc.h
 +++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@
  #ifndef ASPEED_SOC_H
  #define ASPEED_SOC_H
 -#include "hw/arm/arm.h"
  #include "hw/intc/aspeed_vic.h"
  #include "hw/misc/aspeed_scu.h"
  #include "hw/misc/aspeed_sdmc.h"
 diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/bcm2836.h
 +++ b/include/hw/arm/bcm2836.h
@@ -XXX,XX +XXX,XX @@
  #ifndef BCM2836_H
  #define BCM2836_H
 -#include "hw/arm/arm.h"
  #include "hw/arm/bcm2835_peripherals.h"
  #include "hw/intc/bcm2836_control.h"
 diff --git a/include/hw/arm/arm.h b/include/hw/arm/boot.h
 similarity index 98%
 rename from include/hw/arm/arm.h
 rename to include/hw/arm/boot.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/arm.h
 +++ b/include/hw/arm/boot.h
@@ -XXX,XX +XXX,XX @@
  /*
 - * Misc ARM declarations
 + * ARM kernel loader.
   *
   * Copyright (c) 2006 CodeSourcery.
   * Written by Paul Brook
@@ -XXX,XX +XXX,XX @@
   *
   */
 -#ifndef HW_ARM_H
 -#define HW_ARM_H
 +#ifndef HW_ARM_BOOT_H
 +#define HW_ARM_BOOT_H
  #include "exec/memory.h"
  #include "target/arm/cpu-qom.h"
@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
                                              const struct arm_boot_info *info,
                                              hwaddr mvbar_addr);
 -#endif /* HW_ARM_H */
 +#endif /* HW_ARM_BOOT_H */
 diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/fsl-imx25.h
 +++ b/include/hw/arm/fsl-imx25.h
@@ -XXX,XX +XXX,XX @@
  #ifndef FSL_IMX25_H
  #define FSL_IMX25_H
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/intc/imx_avic.h"
  #include "hw/misc/imx25_ccm.h"
  #include "hw/char/imx_serial.h"
 diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/fsl-imx31.h
 +++ b/include/hw/arm/fsl-imx31.h
@@ -XXX,XX +XXX,XX @@
  #ifndef FSL_IMX31_H
  #define FSL_IMX31_H
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/intc/imx_avic.h"
  #include "hw/misc/imx31_ccm.h"
  #include "hw/char/imx_serial.h"
 diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/fsl-imx6.h
 +++ b/include/hw/arm/fsl-imx6.h
@@ -XXX,XX +XXX,XX @@
  #ifndef FSL_IMX6_H
  #define FSL_IMX6_H
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/cpu/a9mpcore.h"
  #include "hw/misc/imx6_ccm.h"
  #include "hw/misc/imx6_src.h"
 diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/fsl-imx6ul.h
 +++ b/include/hw/arm/fsl-imx6ul.h
@@ -XXX,XX +XXX,XX @@
  #ifndef FSL_IMX6UL_H
  #define FSL_IMX6UL_H
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/cpu/a15mpcore.h"
  #include "hw/misc/imx6ul_ccm.h"
  #include "hw/misc/imx6_src.h"
 diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/fsl-imx7.h
 +++ b/include/hw/arm/fsl-imx7.h
@@ -XXX,XX +XXX,XX @@
  #ifndef FSL_IMX7_H
  #define FSL_IMX7_H
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/cpu/a15mpcore.h"
  #include "hw/intc/imx_gpcv2.h"
  #include "hw/misc/imx7_ccm.h"
 diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/virt.h
 +++ b/include/hw/arm/virt.h
@@ -XXX,XX +XXX,XX @@
  #include "exec/hwaddr.h"
  #include "qemu/notify.h"
  #include "hw/boards.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/block/flash.h"
  #include "sysemu/kvm.h"
  #include "hw/intc/arm_gicv3_common.h"
 diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/xlnx-versal.h
 +++ b/include/hw/arm/xlnx-versal.h
@@ -XXX,XX +XXX,XX @@
  #define XLNX_VERSAL_H
  #include "hw/sysbus.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/intc/arm_gicv3.h"
  #define TYPE_XLNX_VERSAL "xlnx-versal"
 diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
 index XXXXXXX..XXXXXXX 100644
 --- a/include/hw/arm/xlnx-zynqmp.h
 +++ b/include/hw/arm/xlnx-zynqmp.h
@@ -XXX,XX +XXX,XX @@
  #ifndef XLNX_ZYNQMP_H
  #include "qemu-common.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/intc/arm_gic.h"
  #include "hw/net/cadence_gem.h"
  #include "hw/char/cadence_uart.h"
 diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/armsse.c
 +++ b/hw/arm/armsse.c
 @@ -XXX,XX +XXX,XX @@
+ #include "hw/sysbus.h"
  #include "hw/registerfields.h"
  #include "hw/arm/armsse.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  /* Format of the System Information block SYS_CONFIG register */
  typedef enum SysConfigFormat {
 diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/armv7m.c
 +++ b/hw/arm/armv7m.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu-common.h"
  #include "cpu.h"
  #include "hw/sysbus.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/loader.h"
  #include "elf.h"
  #include "sysemu/qtest.h"
 diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/aspeed.c
 +++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu-common.h"
  #include "cpu.h"
  #include "exec/address-spaces.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/arm/aspeed.h"
  #include "hw/arm/aspeed_soc.h"
  #include "hw/boards.h"
 diff --git a/hw/arm/boot.c b/hw/arm/boot.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/boot.c
 +++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@
  #include "qapi/error.h"
  #include <libfdt.h>
  #include "hw/hw.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/arm/linux-boot-if.h"
  #include "sysemu/kvm.h"
  #include "sysemu/sysemu.h"
 diff --git a/hw/arm/collie.c b/hw/arm/collie.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/collie.c
 +++ b/hw/arm/collie.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/sysbus.h"
  #include "hw/boards.h"
  #include "strongarm.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/block/flash.h"
  #include "exec/address-spaces.h"
  #include "cpu.h"
 diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/exynos4210.c
 +++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/boards.h"
  #include "sysemu/sysemu.h"
  #include "hw/sysbus.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/loader.h"
  #include "hw/arm/exynos4210.h"
  #include "hw/sd/sdhci.h"
 diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/exynos4_boards.c
 +++ b/hw/arm/exynos4_boards.c
@@ -XXX,XX +XXX,XX @@
  #include "sysemu/sysemu.h"
  #include "hw/sysbus.h"
  #include "net/net.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "exec/address-spaces.h"
  #include "hw/arm/exynos4210.h"
  #include "hw/net/lan9118.h"
 diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/highbank.c
 +++ b/hw/arm/highbank.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/osdep.h"
- #include "qemu/log.h"
+ #include "qapi/error.h"
-+#include "qemu/bitops.h"
+ #include "hw/sysbus.h"
- #include "qapi/error.h"
+-#include "hw/arm/arm.h"
- #include "trace.h"
++#include "hw/arm/boot.h"
- #include "hw/sysbus.h"
+ #include "hw/loader.h"
-@@ -XXX,XX +XXX,XX @@ struct ARMSSEInfo {
+ #include "net/net.h"
-     int sram_banks;
+ #include "sysemu/kvm.h"
-     int num_cpus;
+diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
-     uint32_t sys_version;
+index XXXXXXX..XXXXXXX 100644
-+    uint32_t cpuwait_rst;
+--- a/hw/arm/integratorcp.c
-     SysConfigFormat sys_config_format;
++++ b/hw/arm/integratorcp.c
-     bool has_mhus;
+@@ -XXX,XX +XXX,XX @@
-     bool has_ppus;
+ #include "cpu.h"
-@@ -XXX,XX +XXX,XX @@ static const ARMSSEInfo armsse_variants[] = {
+ #include "hw/sysbus.h"
-         .sram_banks = 1,
+ #include "hw/boards.h"
-         .num_cpus = 1,
+-#include "hw/arm/arm.h"
-         .sys_version = 0x41743,
++#include "hw/arm/boot.h"
-+        .cpuwait_rst = 0,
+ #include "hw/misc/arm_integrator_debug.h"
-         .sys_config_format = IoTKitFormat,
+ #include "hw/net/smc91c111.h"
-         .has_mhus = false,
+ #include "net/net.h"
-         .has_ppus = false,
+diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
-@@ -XXX,XX +XXX,XX @@ static const ARMSSEInfo armsse_variants[] = {
+index XXXXXXX..XXXXXXX 100644
-         .sram_banks = 4,
+--- a/hw/arm/mainstone.c
-         .num_cpus = 2,
++++ b/hw/arm/mainstone.c
-         .sys_version = 0x22041743,
+@@ -XXX,XX +XXX,XX @@
-+        .cpuwait_rst = 2,
+ #include "qapi/error.h"
-         .sys_config_format = SSE200Format,
+ #include "hw/hw.h"
-         .has_mhus = true,
+ #include "hw/arm/pxa.h"
-         .has_ppus = true,
+-#include "hw/arm/arm.h"
-@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
++#include "hw/arm/boot.h"
+ #include "net/net.h"
-         qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + 32);
+ #include "hw/net/smc91c111.h"
-         /*
+ #include "hw/boards.h"
--         * In real hardware the initial Secure VTOR is set from the INITSVTOR0
+diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
--         * register in the IoT Kit System Control Register block, and the
+index XXXXXXX..XXXXXXX 100644
--         * initial value of that is in turn specifiable by the FPGA that
+--- a/hw/arm/microbit.c
--         * instantiates the IoT Kit. In QEMU we don't implement this wrinkle,
++++ b/hw/arm/microbit.c
--         * and simply set the CPU's init-svtor to the IoT Kit default value.
+@@ -XXX,XX +XXX,XX @@
--         * In SSE-200 the situation is similar, except that the default value
+ #include "qemu/osdep.h"
--         * is a reset-time signal input. Typically a board using the SSE-200
+ #include "qapi/error.h"
--         * will have a system control processor whose boot firmware initializes
+ #include "hw/boards.h"
--         * the INITSVTOR* registers before powering up the CPUs in any case,
+-#include "hw/arm/arm.h"
--         * so the hardware's default value doesn't matter. QEMU doesn't emulate
++#include "hw/arm/boot.h"
-+         * In real hardware the initial Secure VTOR is set from the INITSVTOR*
+ #include "sysemu/sysemu.h"
-+         * registers in the IoT Kit System Control Register block. In QEMU
+ #include "exec/address-spaces.h"
-+         * we set the initial value here, and also the reset value of the
-+         * sysctl register, from this object's QOM init-svtor property.
+diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
-+         * If the guest changes the INITSVTOR* registers at runtime then the
+index XXXXXXX..XXXXXXX 100644
-+         * code in iotkit-sysctl.c will update the CPU init-svtor property
+--- a/hw/arm/mps2-tz.c
-+         * (which will then take effect on the next CPU warm-reset).
++++ b/hw/arm/mps2-tz.c
-+         *
+@@ -XXX,XX +XXX,XX @@
-+         * Note that typically a board using the SSE-200 will have a system
+ #include "qemu/osdep.h"
-+         * control processor whose boot firmware initializes the INITSVTOR*
+ #include "qapi/error.h"
-+         * registers before powering up the CPUs. QEMU doesn't emulate
+ #include "qemu/error-report.h"
-          * the control processor, so instead we behave in the way that the
+-#include "hw/arm/arm.h"
--         * firmware does. The initial value is configurable by the board code
++#include "hw/arm/boot.h"
--         * to match whatever its firmware does.
+ #include "hw/arm/armv7m.h"
-+         * firmware does: the initial value should be set by the board code
+ #include "hw/or-irq.h"
-+         * (using the init-svtor property on the ARMSSE object) to match
+ #include "hw/boards.h"
-+         * whatever its firmware does.
+diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
-          */
+index XXXXXXX..XXXXXXX 100644
-         qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor);
+--- a/hw/arm/mps2.c
-         /*
++++ b/hw/arm/mps2.c
--         * Start all CPUs except CPU0 powered down. In real hardware it is
+@@ -XXX,XX +XXX,XX @@
--         * a configurable property of the SSE-200 which CPUs start powered up
+ #include "qemu/osdep.h"
--         * (via the CPUWAIT0_RST and CPUWAIT1_RST parameters), but since all
+ #include "qapi/error.h"
--         * the boards we care about start CPU0 and leave CPU1 powered off,
+ #include "qemu/error-report.h"
--         * we hard-code that for now. We can add QOM properties for this
+-#include "hw/arm/arm.h"
-+         * CPUs start powered down if the corresponding bit in the CPUWAIT
++#include "hw/arm/boot.h"
-+         * register is 1. In real hardware the CPUWAIT register reset value is
+ #include "hw/arm/armv7m.h"
-+         * a configurable property of the SSE-200 (via the CPUWAIT0_RST and
+ #include "hw/or-irq.h"
-+         * CPUWAIT1_RST parameters), but since all the boards we care about
+ #include "hw/boards.h"
-+         * start CPU0 and leave CPU1 powered off, we hard-code that in
+diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
-+         * info->cpuwait_rst for now. We can add QOM properties for this
+index XXXXXXX..XXXXXXX 100644
-          * later if necessary.
+--- a/hw/arm/msf2-soc.c
-          */
++++ b/hw/arm/msf2-soc.c
--        if (i > 0) {
+@@ -XXX,XX +XXX,XX @@
-+        if (extract32(info->cpuwait_rst, i, 1)) {
+ #include "qemu/units.h"
-             object_property_set_bool(cpuobj, true, "start-powered-off", &err);
+ #include "qapi/error.h"
-             if (err) {
+ #include "qemu-common.h"
-                 error_propagate(errp, err);
+-#include "hw/arm/arm.h"
-@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
+ #include "exec/address-spaces.h"
-     /* System control registers */
+ #include "hw/char/serial.h"
-     object_property_set_int(OBJECT(&s->sysctl), info->sys_version,
+ #include "hw/boards.h"
-                             "SYS_VERSION", &err);
+diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
-+    object_property_set_int(OBJECT(&s->sysctl), info->cpuwait_rst,
+index XXXXXXX..XXXXXXX 100644
-+                            "CPUWAIT_RST", &err);
+--- a/hw/arm/msf2-som.c
-+    object_property_set_int(OBJECT(&s->sysctl), s->init_svtor,
++++ b/hw/arm/msf2-som.c
-+                            "INITSVTOR0_RST", &err);
+@@ -XXX,XX +XXX,XX @@
-+    object_property_set_int(OBJECT(&s->sysctl), s->init_svtor,
+ #include "qapi/error.h"
-+                            "INITSVTOR1_RST", &err);
+ #include "qemu/error-report.h"
-     object_property_set_bool(OBJECT(&s->sysctl), true, "realized", &err);
+ #include "hw/boards.h"
-     if (err) {
+-#include "hw/arm/arm.h"
-         error_propagate(errp, err);
++#include "hw/arm/boot.h"
-diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
+ #include "exec/address-spaces.h"
-index XXXXXXX..XXXXXXX 100644
+ #include "hw/arm/msf2-soc.h"
---- a/hw/misc/iotkit-sysctl.c
+ #include "cpu.h"
-+++ b/hw/misc/iotkit-sysctl.c
+diff --git a/hw/arm/musca.c b/hw/arm/musca.c
-@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_reset(DeviceState *dev)
+index XXXXXXX..XXXXXXX 100644
-     s->reset_syndrome = 1;
+--- a/hw/arm/musca.c
-     s->reset_mask = 0;
++++ b/hw/arm/musca.c
-     s->gretreg = 0;
+@@ -XXX,XX +XXX,XX @@
--    s->initsvtor0 = 0x10000000;
+ #include "qapi/error.h"
--    s->initsvtor1 = 0x10000000;
+ #include "exec/address-spaces.h"
--    if (s->is_sse200) {
+ #include "sysemu/sysemu.h"
--        /*
+-#include "hw/arm/arm.h"
--         * CPU 0 starts on, CPU 1 starts off. In real hardware this is
++#include "hw/arm/boot.h"
--         * configurable by the SoC integrator as a verilog parameter.
+ #include "hw/arm/armsse.h"
--         */
+ #include "hw/boards.h"
--        s->cpuwait = 2;
+ #include "hw/char/pl011.h"
--    } else {
+diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
--        /* CPU 0 starts on */
+index XXXXXXX..XXXXXXX 100644
--        s->cpuwait = 0;
+--- a/hw/arm/musicpal.c
--    }
++++ b/hw/arm/musicpal.c
-+    s->initsvtor0 = s->initsvtor0_rst;
+@@ -XXX,XX +XXX,XX @@
-+    s->initsvtor1 = s->initsvtor1_rst;
+ #include "qemu-common.h"
-+    s->cpuwait = s->cpuwait_rst;
+ #include "cpu.h"
-     s->wicctrl = 0;
+ #include "hw/sysbus.h"
-     s->scsecctrl = 0;
+-#include "hw/arm/arm.h"
-     s->fclk_div = 0;
++#include "hw/arm/boot.h"
-@@ -XXX,XX +XXX,XX @@ static const VMStateDescription iotkit_sysctl_vmstate = {
+ #include "net/net.h"
+ #include "sysemu/sysemu.h"
- static Property iotkit_sysctl_props[] = {
+ #include "hw/boards.h"
-     DEFINE_PROP_UINT32("SYS_VERSION", IoTKitSysCtl, sys_version, 0),
+diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
-+    DEFINE_PROP_UINT32("CPUWAIT_RST", IoTKitSysCtl, cpuwait_rst, 0),
+index XXXXXXX..XXXXXXX 100644
-+    DEFINE_PROP_UINT32("INITSVTOR0_RST", IoTKitSysCtl, initsvtor0_rst,
+--- a/hw/arm/netduino2.c
-+                       0x10000000),
++++ b/hw/arm/netduino2.c
-+    DEFINE_PROP_UINT32("INITSVTOR1_RST", IoTKitSysCtl, initsvtor1_rst,
+@@ -XXX,XX +XXX,XX @@
-+                       0x10000000),
+ #include "hw/boards.h"
-     DEFINE_PROP_END_OF_LIST()
+ #include "qemu/error-report.h"
- };
+ #include "hw/arm/stm32f205_soc.h"
+-#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  static void netduino2_init(MachineState *machine)
  {
 diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/nrf51_soc.c
 +++ b/hw/arm/nrf51_soc.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/osdep.h"
  #include "qapi/error.h"
  #include "qemu-common.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/sysbus.h"
  #include "hw/boards.h"
  #include "hw/misc/unimp.h"
 diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/nseries.c
 +++ b/hw/arm/nseries.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/bswap.h"
  #include "sysemu/sysemu.h"
  #include "hw/arm/omap.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/irq.h"
  #include "ui/console.h"
  #include "hw/boards.h"
 diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/omap1.c
 +++ b/hw/arm/omap1.c
@@ -XXX,XX +XXX,XX @@
  #include "cpu.h"
  #include "hw/boards.h"
  #include "hw/hw.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/arm/omap.h"
  #include "sysemu/sysemu.h"
  #include "hw/arm/soc_dma.h"
 diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/omap2.c
 +++ b/hw/arm/omap2.c
@@ -XXX,XX +XXX,XX @@
  #include "sysemu/qtest.h"
  #include "hw/boards.h"
  #include "hw/hw.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/arm/omap.h"
  #include "sysemu/sysemu.h"
  #include "qemu/timer.h"
 diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/omap_sx1.c
 +++ b/hw/arm/omap_sx1.c
@@ -XXX,XX +XXX,XX @@
  #include "ui/console.h"
  #include "hw/arm/omap.h"
  #include "hw/boards.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/block/flash.h"
  #include "sysemu/qtest.h"
  #include "exec/address-spaces.h"
 diff --git a/hw/arm/palm.c b/hw/arm/palm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/palm.c
 +++ b/hw/arm/palm.c
@@ -XXX,XX +XXX,XX @@
  #include "ui/console.h"
  #include "hw/arm/omap.h"
  #include "hw/boards.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/input/tsc2xxx.h"
  #include "hw/loader.h"
  #include "exec/address-spaces.h"
 diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/raspi.c
 +++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/error-report.h"
  #include "hw/boards.h"
  #include "hw/loader.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "sysemu/sysemu.h"
  #define SMPBOOT_ADDR    0x300 /* this should leave enough space for ATAGS */
 diff --git a/hw/arm/realview.c b/hw/arm/realview.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/realview.c
 +++ b/hw/arm/realview.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu-common.h"
  #include "cpu.h"
  #include "hw/sysbus.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/arm/primecell.h"
  #include "hw/net/lan9118.h"
  #include "hw/net/smc91c111.h"
 diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/spitz.c
 +++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@
  #include "qapi/error.h"
  #include "hw/hw.h"
  #include "hw/arm/pxa.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "sysemu/sysemu.h"
  #include "hw/pcmcia.h"
  #include "hw/i2c/i2c.h"
 diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/stellaris.c
 +++ b/hw/arm/stellaris.c
@@ -XXX,XX +XXX,XX @@
  #include "qapi/error.h"
  #include "hw/sysbus.h"
  #include "hw/ssi/ssi.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "qemu/timer.h"
  #include "hw/i2c/i2c.h"
  #include "net/net.h"
 diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/stm32f205_soc.c
 +++ b/hw/arm/stm32f205_soc.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/osdep.h"
  #include "qapi/error.h"
  #include "qemu-common.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "exec/address-spaces.h"
  #include "hw/arm/stm32f205_soc.h"
 diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/strongarm.c
 +++ b/hw/arm/strongarm.c
@@ -XXX,XX +XXX,XX @@
  #include "hw/sysbus.h"
  #include "strongarm.h"
  #include "qemu/error-report.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "chardev/char-fe.h"
  #include "chardev/char-serial.h"
  #include "sysemu/sysemu.h"
 diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/tosa.c
 +++ b/hw/arm/tosa.c
@@ -XXX,XX +XXX,XX @@
  #include "qapi/error.h"
  #include "hw/hw.h"
  #include "hw/arm/pxa.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/arm/sharpsl.h"
  #include "hw/pcmcia.h"
  #include "hw/boards.h"
 diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/versatilepb.c
 +++ b/hw/arm/versatilepb.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu-common.h"
  #include "cpu.h"
  #include "hw/sysbus.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/net/smc91c111.h"
  #include "net/net.h"
  #include "sysemu/sysemu.h"
 diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/vexpress.c
 +++ b/hw/arm/vexpress.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu-common.h"
  #include "cpu.h"
  #include "hw/sysbus.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/arm/primecell.h"
  #include "hw/net/lan9118.h"
  #include "hw/i2c/i2c.h"
 diff --git a/hw/arm/virt.c b/hw/arm/virt.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/virt.c
 +++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/option.h"
  #include "qapi/error.h"
  #include "hw/sysbus.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/arm/primecell.h"
  #include "hw/arm/virt.h"
  #include "hw/block/flash.h"
 diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/xilinx_zynq.c
 +++ b/hw/arm/xilinx_zynq.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu-common.h"
  #include "cpu.h"
  #include "hw/sysbus.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "net/net.h"
  #include "exec/address-spaces.h"
  #include "sysemu/sysemu.h"
 diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/xlnx-versal.c
 +++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@
  #include "net/net.h"
  #include "sysemu/sysemu.h"
  #include "sysemu/kvm.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "kvm_arm.h"
  #include "hw/misc/unimp.h"
  #include "hw/intc/arm_gicv3_common.h"
 diff --git a/hw/arm/z2.c b/hw/arm/z2.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/z2.c
 +++ b/hw/arm/z2.c
@@ -XXX,XX +XXX,XX @@
  #include "qemu/osdep.h"
  #include "hw/hw.h"
  #include "hw/arm/pxa.h"
 -#include "hw/arm/arm.h"
 +#include "hw/arm/boot.h"
  #include "hw/i2c/i2c.h"
  #include "hw/ssi/ssi.h"
  #include "hw/boards.h"
 --
 .20.1

-[Qemu-devel] [PULL 07/16] hw/arm/iotkit-sysctl: Implement CPUWAIT and INITSVTOR*
+[Qemu-devel] [PULL 07/12] hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
-The CPUWAIT register acts as a sort of power-control: if a bit
+In ich_vmcr_write() we enforce "writes of BPR fields to less than
-in it is 1 then the CPU will have been forced into waiting
+their minimum sets them to the minimum" by doing a "read vbpr and
-when the system was reset (which in QEMU we model as the
+write it back" operation.  A typo here meant that we weren't handling
-CPU starting powered off). Writing a 0 to the register will
+writes to these fields correctly, because we were reading from VBPR0
-allow the CPU to boot (for QEMU, we model this as powering
+but writing to VBPR1.
 it on). Note that writing 0 to the register does not power
 off a CPU.
 For this to work correctly we need to also honour the
 INITSVTOR* registers, which let the guest control where the
 CPU will load its SP and PC from when it comes out of reset.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Message-id: 20190219125808.25174-8-peter.maydell@linaro.org
+Message-id: 20190520162809.2677-4-peter.maydell@linaro.org
 ---
- hw/misc/iotkit-sysctl.c | 41 +++++++++++++++++++++++++++++++++++++----
+ hw/intc/arm_gicv3_cpuif.c | 2 +-
-file changed, 37 insertions(+), 4 deletions(-)
+file changed, 1 insertion(+), 1 deletion(-)
-diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
+diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
 index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/iotkit-sysctl.c
+--- a/hw/intc/arm_gicv3_cpuif.c
-+++ b/hw/misc/iotkit-sysctl.c
++++ b/hw/intc/arm_gicv3_cpuif.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void ich_vmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
- #include "hw/sysbus.h"
+     /* Enforce "writing BPRs to less than minimum sets them to the minimum"
- #include "hw/registerfields.h"
+      * by reading and writing back the fields.
- #include "hw/misc/iotkit-sysctl.h"
+      */
-+#include "target/arm/arm-powerctl.h"
+-    write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G0));
-+#include "target/arm/cpu.h"
++    write_vbpr(cs, GICV3_G0, read_vbpr(cs, GICV3_G0));
+     write_vbpr(cs, GICV3_G1, read_vbpr(cs, GICV3_G1));
- REG32(SECDBGSTAT, 0x0)
- REG32(SECDBGSET, 0x4)
+     gicv3_cpuif_virt_update(cs);
@@ -XXX,XX +XXX,XX @@ static const int sysctl_id[] = {
 x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
  };
 +/*
 + * Set the initial secure vector table offset address for the core.
 + * This will take effect when the CPU next resets.
 + */
 +static void set_init_vtor(uint64_t cpuid, uint32_t vtor)
 +{
 +    Object *cpuobj = OBJECT(arm_get_cpu_by_id(cpuid));
 +
 +    if (cpuobj) {
 +        if (object_property_find(cpuobj, "init-svtor", NULL)) {
 +            object_property_set_uint(cpuobj, vtor, "init-svtor", &error_abort);
 +        }
 +    }
 +}
 +
  static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
                                      unsigned size)
  {
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
          s->gretreg = value;
          break;
      case A_INITSVTOR0:
 -        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR0 unimplemented\n");
          s->initsvtor0 = value;
 +        set_init_vtor(0, s->initsvtor0);
          break;
      case A_CPUWAIT:
 -        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CPUWAIT unimplemented\n");
 +        if ((s->cpuwait & 1) && !(value & 1)) {
 +            /* Powering up CPU 0 */
 +            arm_set_cpu_on_and_reset(0);
 +        }
 +        if ((s->cpuwait & 2) && !(value & 2)) {
 +            /* Powering up CPU 1 */
 +            arm_set_cpu_on_and_reset(1);
 +        }
          s->cpuwait = value;
          break;
      case A_WICCTRL:
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
          if (!s->is_sse200) {
              goto bad_offset;
          }
 -        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR1 unimplemented\n");
          s->initsvtor1 = value;
 +        set_init_vtor(1, s->initsvtor1);
          break;
      case A_EWCTRL:
          if (!s->is_sse200) {
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_reset(DeviceState *dev)
      s->gretreg = 0;
      s->initsvtor0 = 0x10000000;
      s->initsvtor1 = 0x10000000;
 -    s->cpuwait = 0;
 +    if (s->is_sse200) {
 +        /*
 +         * CPU 0 starts on, CPU 1 starts off. In real hardware this is
 +         * configurable by the SoC integrator as a verilog parameter.
 +         */
 +        s->cpuwait = 2;
 +    } else {
 +        /* CPU 0 starts on */
 +        s->cpuwait = 0;
 +    }
      s->wicctrl = 0;
      s->scsecctrl = 0;
      s->fclk_div = 0;
 --
 .20.1

-[Qemu-devel] [PULL 02/16] hw/arm/armsse: Wire up the MHUs
+[Qemu-devel] [PULL 08/12] hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3
-Create and connect the MHUs in the SSE-200.
+The ICC_CTLR_EL3 register includes some bits which are aliases
 of bits in the ICC_CTLR_EL1(S) and (NS) registers. QEMU chooses
 to keep those bits in the cs->icc_ctlr_el1[] struct fields.
 Unfortunately a missing '~' in the code to update the bits
 in those fields meant that writing to ICC_CTLR_EL3 would corrupt
 the ICC_CLTR_EL1 register values.
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
+Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Message-id: 20190219125808.25174-3-peter.maydell@linaro.org
+Message-id: 20190520162809.2677-5-peter.maydell@linaro.org
 ---
- include/hw/arm/armsse.h |  3 ++-
+ hw/intc/arm_gicv3_cpuif.c | 4 ++--
- hw/arm/armsse.c         | 40 ++++++++++++++++++++++++++++++----------
+file changed, 2 insertions(+), 2 deletions(-)
 files changed, 32 insertions(+), 11 deletions(-)
-diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
+diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/arm/armsse.h
+--- a/hw/intc/arm_gicv3_cpuif.c
-+++ b/include/hw/arm/armsse.h
++++ b/hw/intc/arm_gicv3_cpuif.c
-@@ -XXX,XX +XXX,XX @@
+@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
- #include "hw/misc/iotkit-sysctl.h"
+     trace_gicv3_icc_ctlr_el3_write(gicv3_redist_affid(cs), value);
- #include "hw/misc/iotkit-sysinfo.h"
- #include "hw/misc/armsse-cpuid.h"
+     /* *_EL1NS and *_EL1S bits are aliases into the ICC_CTLR_EL1 bits. */
-+#include "hw/misc/armsse-mhu.h"
+-    cs->icc_ctlr_el1[GICV3_NS] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
- #include "hw/misc/unimp.h"
++    cs->icc_ctlr_el1[GICV3_NS] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
- #include "hw/or-irq.h"
+     if (value & ICC_CTLR_EL3_EOIMODE_EL1NS) {
- #include "hw/core/split-irq.h"
+         cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE;
@@ -XXX,XX +XXX,XX @@ typedef struct ARMSSE {
      IoTKitSysCtl sysctl;
      IoTKitSysCtl sysinfo;
 -    UnimplementedDeviceState mhu[2];
 +    ARMSSEMHU mhu[2];
      UnimplementedDeviceState ppu[NUM_PPUS];
      UnimplementedDeviceState cachectrl[SSE_MAX_CPUS];
      UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS];
 diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/armsse.c
 +++ b/hw/arm/armsse.c
@@ -XXX,XX +XXX,XX @@ static void armsse_init(Object *obj)
                            sizeof(s->sysinfo), TYPE_IOTKIT_SYSINFO);
      if (info->has_mhus) {
          sysbus_init_child_obj(obj, "mhu0", &s->mhu[0], sizeof(s->mhu[0]),
 -                              TYPE_UNIMPLEMENTED_DEVICE);
 +                              TYPE_ARMSSE_MHU);
          sysbus_init_child_obj(obj, "mhu1", &s->mhu[1], sizeof(s->mhu[1]),
 -                              TYPE_UNIMPLEMENTED_DEVICE);
 +                              TYPE_ARMSSE_MHU);
      }
-     if (info->has_ppus) {
+@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
-         for (i = 0; i < info->num_cpus; i++) {
+         cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_CBPR;
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
      }
-     if (info->has_mhus) {
+-    cs->icc_ctlr_el1[GICV3_S] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
--        for (i = 0; i < ARRAY_SIZE(s->mhu); i++) {
++    cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
--            char *name;
+     if (value & ICC_CTLR_EL3_EOIMODE_EL1S) {
--            char *port;
+         cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_EOIMODE;
 +        /*
 +         * An SSE-200 with only one CPU should have only one MHU created,
 +         * with the region where the second MHU usually is being RAZ/WI.
 +         * We don't implement that SSE-200 config; if we want to support
 +         * it then this code needs to be enhanced to handle creating the
 +         * RAZ/WI region instead of the second MHU.
 +         */
 +        assert(info->num_cpus == ARRAY_SIZE(s->mhu));
 +
 +        for (i = 0; i < ARRAY_SIZE(s->mhu); i++) {
 +            char *port;
 +            int cpunum;
 +            SysBusDevice *mhu_sbd = SYS_BUS_DEVICE(&s->mhu[i]);
 -            name = g_strdup_printf("MHU%d", i);
 -            qdev_prop_set_string(DEVICE(&s->mhu[i]), "name", name);
 -            qdev_prop_set_uint64(DEVICE(&s->mhu[i]), "size", 0x1000);
              object_property_set_bool(OBJECT(&s->mhu[i]), true,
                                       "realized", &err);
 -            g_free(name);
              if (err) {
                  error_propagate(errp, err);
                  return;
              }
              port = g_strdup_printf("port[%d]", i + 3);
 -            mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mhu[i]), 0);
 +            mr = sysbus_mmio_get_region(mhu_sbd, 0);
              object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr),
                                       port, &err);
              g_free(port);
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
                  error_propagate(errp, err);
                  return;
              }
 +
 +            /*
 +             * Each MHU has an irq line for each CPU:
 +             *  MHU 0 irq line 0 -> CPU 0 IRQ 6
 +             *  MHU 0 irq line 1 -> CPU 1 IRQ 6
 +             *  MHU 1 irq line 0 -> CPU 0 IRQ 7
 +             *  MHU 1 irq line 1 -> CPU 1 IRQ 7
 +             */
 +            for (cpunum = 0; cpunum < info->num_cpus; cpunum++) {
 +                DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]);
 +
 +                sysbus_connect_irq(mhu_sbd, cpunum,
 +                                   qdev_get_gpio_in(cpudev, 6 + i));
 +            }
          }
      }
 --
 .20.1

-[Qemu-devel] [PULL 16/16] linux-user: Enable HWCAP_ASIMDFHM, HWCAP_JSCVT
+[Qemu-devel] [PULL 09/12] hw/arm/exynos4: Remove unuseful debug code
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Philippe Mathieu-Daudé <philmd@redhat.com>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
-Message-id: 20190219222952.22183-6-richard.henderson@linaro.org
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
+Message-id: 20190520214342.13709-2-philmd@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- linux-user/elfload.c | 2 ++
+ hw/arm/exynos4_boards.c | 24 ------------------------
-file changed, 2 insertions(+)
+file changed, 24 deletions(-)
-diff --git a/linux-user/elfload.c b/linux-user/elfload.c
+diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
 index XXXXXXX..XXXXXXX 100644
---- a/linux-user/elfload.c
+--- a/hw/arm/exynos4_boards.c
-+++ b/linux-user/elfload.c
++++ b/hw/arm/exynos4_boards.c
-@@ -XXX,XX +XXX,XX @@ static uint32_t get_elf_hwcap(void)
+@@ -XXX,XX +XXX,XX @@
-     GET_FEATURE_ID(aa64_fcma, ARM_HWCAP_A64_FCMA);
+ #include "hw/net/lan9118.h"
-     GET_FEATURE_ID(aa64_sve, ARM_HWCAP_A64_SVE);
+ #include "hw/boards.h"
-     GET_FEATURE_ID(aa64_pauth, ARM_HWCAP_A64_PACA | ARM_HWCAP_A64_PACG);
-+    GET_FEATURE_ID(aa64_fhm, ARM_HWCAP_A64_ASIMDFHM);
+-#undef DEBUG
-+    GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT);
+-
+-//#define DEBUG
- #undef GET_FEATURE_ID
+-
 -#ifdef DEBUG
 -    #undef PRINT_DEBUG
 -    #define  PRINT_DEBUG(fmt, args...) \
 -        do { \
 -            fprintf(stderr, "  [%s:%d]   "fmt, __func__, __LINE__, ##args); \
 -        } while (0)
 -#else
 -    #define  PRINT_DEBUG(fmt, args...)  do {} while (0)
 -#endif
 -
  #define SMDK_LAN9118_BASE_ADDR      0x05000000
  typedef enum Exynos4BoardType {
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
      exynos4_board_binfo.gic_cpu_if_addr =
              EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100;
 -    PRINT_DEBUG("\n ram_size: %luMiB [0x%08lx]\n"
 -            " kernel_filename: %s\n"
 -            " kernel_cmdline: %s\n"
 -            " initrd_filename: %s\n",
 -            exynos4_board_ram_size[board_type] / 1048576,
 -            exynos4_board_ram_size[board_type],
 -            machine->kernel_filename,
 -            machine->kernel_cmdline,
 -            machine->initrd_filename);
 -
      exynos4_boards_init_ram(s, get_system_memory(),
                              exynos4_board_ram_size[board_type]);
 --
 .20.1

-[Qemu-devel] [PULL 06/16] hw/arm/iotkit-sysctl: Add SSE-200 registers
+[Qemu-devel] [PULL 10/12] hw/arm/exynos4: Use the IEC binary prefix definitions
-The SYSCTL block in the SSE-200 has some extra registers that
+From: Philippe Mathieu-Daudé <philmd@redhat.com>
 are not present in the IoTKit version. Add these registers
 (as reads-as-written stubs), enabled by a new QOM property.
+It eases code review, unit is explicit.
+Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20190520214342.13709-3-philmd@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20190219125808.25174-7-peter.maydell@linaro.org
 ---
- include/hw/misc/iotkit-sysctl.h |  20 +++
+ hw/arm/exynos4_boards.c | 5 +++--
- hw/arm/armsse.c                 |   2 +
+file changed, 3 insertions(+), 2 deletions(-)
  hw/misc/iotkit-sysctl.c         | 245 +++++++++++++++++++++++++++++++-
 files changed, 262 insertions(+), 5 deletions(-)
-diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h
+diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
 index XXXXXXX..XXXXXXX 100644
---- a/include/hw/misc/iotkit-sysctl.h
+--- a/hw/arm/exynos4_boards.c
-+++ b/include/hw/misc/iotkit-sysctl.h
++++ b/hw/arm/exynos4_boards.c
@@ -XXX,XX +XXX,XX @@
   * "system control register" blocks.
   *
   * QEMU interface:
 + *  + QOM property "SYS_VERSION": value of the SYS_VERSION register of the
 + *    system information block of the SSE
 + *    (used to identify whether to provide SSE-200-only registers)
   *  + sysbus MMIO region 0: the system information register bank
   *  + sysbus MMIO region 1: the system control register bank
   */
@@ -XXX,XX +XXX,XX @@ typedef struct IoTKitSysCtl {
      uint32_t initsvtor0;
      uint32_t cpuwait;
      uint32_t wicctrl;
 +    uint32_t scsecctrl;
 +    uint32_t fclk_div;
 +    uint32_t sysclk_div;
 +    uint32_t clock_force;
 +    uint32_t initsvtor1;
 +    uint32_t nmi_enable;
 +    uint32_t ewctrl;
 +    uint32_t pdcm_pd_sys_sense;
 +    uint32_t pdcm_pd_sram0_sense;
 +    uint32_t pdcm_pd_sram1_sense;
 +    uint32_t pdcm_pd_sram2_sense;
 +    uint32_t pdcm_pd_sram3_sense;
 +
 +    /* Properties */
 +    uint32_t sys_version;
 +
 +    bool is_sse200;
  } IoTKitSysCtl;
  #endif
 diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/armsse.c
 +++ b/hw/arm/armsse.c
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
      /* System information registers */
      sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysinfo), 0, 0x40020000);
      /* System control registers */
 +    object_property_set_int(OBJECT(&s->sysctl), info->sys_version,
 +                            "SYS_VERSION", &err);
      object_property_set_bool(OBJECT(&s->sysctl), true, "realized", &err);
      if (err) {
          error_propagate(errp, err);
 diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/misc/iotkit-sysctl.c
 +++ b/hw/misc/iotkit-sysctl.c
 @@ -XXX,XX +XXX,XX @@
   */
  #include "qemu/osdep.h"
-+#include "qemu/bitops.h"
++#include "qemu/units.h"
  #include "qemu/log.h"
  #include "trace.h"
  #include "qapi/error.h"
-@@ -XXX,XX +XXX,XX @@
+ #include "qemu/error-report.h"
- REG32(SECDBGSTAT, 0x0)
+ #include "qemu-common.h"
- REG32(SECDBGSET, 0x4)
+@@ -XXX,XX +XXX,XX @@ static int exynos4_board_smp_bootreg_addr[EXYNOS4_NUM_OF_BOARDS] = {
  REG32(SECDBGCLR, 0x8)
 +REG32(SCSECCTRL, 0xc)
 +REG32(FCLK_DIV, 0x10)
 +REG32(SYSCLK_DIV, 0x14)
 +REG32(CLOCK_FORCE, 0x18)
  REG32(RESET_SYNDROME, 0x100)
  REG32(RESET_MASK, 0x104)
  REG32(SWRESET, 0x108)
      FIELD(SWRESET, SWRESETREQ, 9, 1)
  REG32(GRETREG, 0x10c)
  REG32(INITSVTOR0, 0x110)
 +REG32(INITSVTOR1, 0x114)
  REG32(CPUWAIT, 0x118)
 -REG32(BUSWAIT, 0x11c)
 +REG32(NMI_ENABLE, 0x11c) /* BUSWAIT in IoTKit */
  REG32(WICCTRL, 0x120)
 +REG32(EWCTRL, 0x124)
 +REG32(PDCM_PD_SYS_SENSE, 0x200)
 +REG32(PDCM_PD_SRAM0_SENSE, 0x20c)
 +REG32(PDCM_PD_SRAM1_SENSE, 0x210)
 +REG32(PDCM_PD_SRAM2_SENSE, 0x214)
 +REG32(PDCM_PD_SRAM3_SENSE, 0x218)
  REG32(PID4, 0xfd0)
  REG32(PID5, 0xfd4)
  REG32(PID6, 0xfd8)
@@ -XXX,XX +XXX,XX @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
      case A_SECDBGSTAT:
          r = s->secure_debug;
          break;
 +    case A_SCSECCTRL:
 +        if (!s->is_sse200) {
 +            goto bad_offset;
 +        }
 +        r = s->scsecctrl;
 +        break;
 +    case A_FCLK_DIV:
 +        if (!s->is_sse200) {
 +            goto bad_offset;
 +        }
 +        r = s->fclk_div;
 +        break;
 +    case A_SYSCLK_DIV:
 +        if (!s->is_sse200) {
 +            goto bad_offset;
 +        }
 +        r = s->sysclk_div;
 +        break;
 +    case A_CLOCK_FORCE:
 +        if (!s->is_sse200) {
 +            goto bad_offset;
 +        }
 +        r = s->clock_force;
 +        break;
      case A_RESET_SYNDROME:
          r = s->reset_syndrome;
          break;
@@ -XXX,XX +XXX,XX @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
      case A_INITSVTOR0:
          r = s->initsvtor0;
          break;
 +    case A_INITSVTOR1:
 +        if (!s->is_sse200) {
 +            goto bad_offset;
 +        }
 +        r = s->initsvtor1;
 +        break;
      case A_CPUWAIT:
          r = s->cpuwait;
          break;
 -    case A_BUSWAIT:
 -        /* In IoTKit BUSWAIT is reserved, R/O, zero */
 -        r = 0;
 +    case A_NMI_ENABLE:
 +        /* In IoTKit this is named BUSWAIT but is marked reserved, R/O, zero */
 +        if (!s->is_sse200) {
 +            r = 0;
 +            break;
 +        }
 +        r = s->nmi_enable;
          break;
      case A_WICCTRL:
          r = s->wicctrl;
          break;
 +    case A_EWCTRL:
 +        if (!s->is_sse200) {
 +            goto bad_offset;
 +        }
 +        r = s->ewctrl;
 +        break;
 +    case A_PDCM_PD_SYS_SENSE:
 +        if (!s->is_sse200) {
 +            goto bad_offset;
 +        }
 +        r = s->pdcm_pd_sys_sense;
 +        break;
 +    case A_PDCM_PD_SRAM0_SENSE:
 +        if (!s->is_sse200) {
 +            goto bad_offset;
 +        }
 +        r = s->pdcm_pd_sram0_sense;
 +        break;
 +    case A_PDCM_PD_SRAM1_SENSE:
 +        if (!s->is_sse200) {
 +            goto bad_offset;
 +        }
 +        r = s->pdcm_pd_sram1_sense;
 +        break;
 +    case A_PDCM_PD_SRAM2_SENSE:
 +        if (!s->is_sse200) {
 +            goto bad_offset;
 +        }
 +        r = s->pdcm_pd_sram2_sense;
 +        break;
 +    case A_PDCM_PD_SRAM3_SENSE:
 +        if (!s->is_sse200) {
 +            goto bad_offset;
 +        }
 +        r = s->pdcm_pd_sram3_sense;
 +        break;
      case A_PID4 ... A_CID3:
          r = sysctl_id[(offset - A_PID4) / 4];
          break;
@@ -XXX,XX +XXX,XX @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
          r = 0;
          break;
      default:
 +    bad_offset:
          qemu_log_mask(LOG_GUEST_ERROR,
                        "IoTKit SysCtl read: bad offset %x\n", (int)offset);
          r = 0;
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
              qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
          }
          break;
 -    case A_BUSWAIT:        /* In IoTKit BUSWAIT is reserved, R/O, zero */
 +    case A_SCSECCTRL:
 +        if (!s->is_sse200) {
 +            goto bad_offset;
 +        }
 +        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SCSECCTRL unimplemented\n");
 +        s->scsecctrl = value;
 +        break;
 +    case A_FCLK_DIV:
 +        if (!s->is_sse200) {
 +            goto bad_offset;
 +        }
 +        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl FCLK_DIV unimplemented\n");
 +        s->fclk_div = value;
 +        break;
 +    case A_SYSCLK_DIV:
 +        if (!s->is_sse200) {
 +            goto bad_offset;
 +        }
 +        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SYSCLK_DIV unimplemented\n");
 +        s->sysclk_div = value;
 +        break;
 +    case A_CLOCK_FORCE:
 +        if (!s->is_sse200) {
 +            goto bad_offset;
 +        }
 +        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CLOCK_FORCE unimplemented\n");
 +        s->clock_force = value;
 +        break;
 +    case A_INITSVTOR1:
 +        if (!s->is_sse200) {
 +            goto bad_offset;
 +        }
 +        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR1 unimplemented\n");
 +        s->initsvtor1 = value;
 +        break;
 +    case A_EWCTRL:
 +        if (!s->is_sse200) {
 +            goto bad_offset;
 +        }
 +        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl EWCTRL unimplemented\n");
 +        s->ewctrl = value;
 +        break;
 +    case A_PDCM_PD_SYS_SENSE:
 +        if (!s->is_sse200) {
 +            goto bad_offset;
 +        }
 +        qemu_log_mask(LOG_UNIMP,
 +                      "IoTKit SysCtl PDCM_PD_SYS_SENSE unimplemented\n");
 +        s->pdcm_pd_sys_sense = value;
 +        break;
 +    case A_PDCM_PD_SRAM0_SENSE:
 +        if (!s->is_sse200) {
 +            goto bad_offset;
 +        }
 +        qemu_log_mask(LOG_UNIMP,
 +                      "IoTKit SysCtl PDCM_PD_SRAM0_SENSE unimplemented\n");
 +        s->pdcm_pd_sram0_sense = value;
 +        break;
 +    case A_PDCM_PD_SRAM1_SENSE:
 +        if (!s->is_sse200) {
 +            goto bad_offset;
 +        }
 +        qemu_log_mask(LOG_UNIMP,
 +                      "IoTKit SysCtl PDCM_PD_SRAM1_SENSE unimplemented\n");
 +        s->pdcm_pd_sram1_sense = value;
 +        break;
 +    case A_PDCM_PD_SRAM2_SENSE:
 +        if (!s->is_sse200) {
 +            goto bad_offset;
 +        }
 +        qemu_log_mask(LOG_UNIMP,
 +                      "IoTKit SysCtl PDCM_PD_SRAM2_SENSE unimplemented\n");
 +        s->pdcm_pd_sram2_sense = value;
 +        break;
 +    case A_PDCM_PD_SRAM3_SENSE:
 +        if (!s->is_sse200) {
 +            goto bad_offset;
 +        }
 +        qemu_log_mask(LOG_UNIMP,
 +                      "IoTKit SysCtl PDCM_PD_SRAM3_SENSE unimplemented\n");
 +        s->pdcm_pd_sram3_sense = value;
 +        break;
 +    case A_NMI_ENABLE:
 +        /* In IoTKit this is BUSWAIT: reserved, R/O, zero */
 +        if (!s->is_sse200) {
 +            goto ro_offset;
 +        }
 +        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE unimplemented\n");
 +        s->nmi_enable = value;
 +        break;
      case A_SECDBGSTAT:
      case A_PID4 ... A_CID3:
 +    ro_offset:
          qemu_log_mask(LOG_GUEST_ERROR,
                        "IoTKit SysCtl write: write of RO offset %x\n",
                        (int)offset);
          break;
      default:
 +    bad_offset:
          qemu_log_mask(LOG_GUEST_ERROR,
                        "IoTKit SysCtl write: bad offset %x\n", (int)offset);
          break;
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_reset(DeviceState *dev)
      s->reset_mask = 0;
      s->gretreg = 0;
      s->initsvtor0 = 0x10000000;
 +    s->initsvtor1 = 0x10000000;
      s->cpuwait = 0;
      s->wicctrl = 0;
 +    s->scsecctrl = 0;
 +    s->fclk_div = 0;
 +    s->sysclk_div = 0;
 +    s->clock_force = 0;
 +    s->nmi_enable = 0;
 +    s->ewctrl = 0;
 +    s->pdcm_pd_sys_sense = 0x7f;
 +    s->pdcm_pd_sram0_sense = 0;
 +    s->pdcm_pd_sram1_sense = 0;
 +    s->pdcm_pd_sram2_sense = 0;
 +    s->pdcm_pd_sram3_sense = 0;
  }
  static void iotkit_sysctl_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_init(Object *obj)
      sysbus_init_mmio(sbd, &s->iomem);
  }
 +static void iotkit_sysctl_realize(DeviceState *dev, Error **errp)
 +{
 +    IoTKitSysCtl *s = IOTKIT_SYSCTL(dev);
 +
 +    /* The top 4 bits of the SYS_VERSION register tell us if we're an SSE-200 */
 +    if (extract32(s->sys_version, 28, 4) == 2) {
 +        s->is_sse200 = true;
 +    }
 +}
 +
 +static bool sse200_needed(void *opaque)
 +{
 +    IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque);
 +
 +    return s->is_sse200;
 +}
 +
 +static const VMStateDescription iotkit_sysctl_sse200_vmstate = {
 +    .name = "iotkit-sysctl/sse-200",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .needed = sse200_needed,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32(scsecctrl, IoTKitSysCtl),
 +        VMSTATE_UINT32(fclk_div, IoTKitSysCtl),
 +        VMSTATE_UINT32(sysclk_div, IoTKitSysCtl),
 +        VMSTATE_UINT32(clock_force, IoTKitSysCtl),
 +        VMSTATE_UINT32(initsvtor1, IoTKitSysCtl),
 +        VMSTATE_UINT32(nmi_enable, IoTKitSysCtl),
 +        VMSTATE_UINT32(pdcm_pd_sys_sense, IoTKitSysCtl),
 +        VMSTATE_UINT32(pdcm_pd_sram0_sense, IoTKitSysCtl),
 +        VMSTATE_UINT32(pdcm_pd_sram1_sense, IoTKitSysCtl),
 +        VMSTATE_UINT32(pdcm_pd_sram2_sense, IoTKitSysCtl),
 +        VMSTATE_UINT32(pdcm_pd_sram3_sense, IoTKitSysCtl),
 +        VMSTATE_END_OF_LIST()
 +    }
 +};
 +
  static const VMStateDescription iotkit_sysctl_vmstate = {
      .name = "iotkit-sysctl",
      .version_id = 1,
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription iotkit_sysctl_vmstate = {
          VMSTATE_UINT32(cpuwait, IoTKitSysCtl),
          VMSTATE_UINT32(wicctrl, IoTKitSysCtl),
          VMSTATE_END_OF_LIST()
 +    },
 +    .subsections = (const VMStateDescription*[]) {
 +        &iotkit_sysctl_sse200_vmstate,
 +        NULL
      }
  };
-+static Property iotkit_sysctl_props[] = {
+ static unsigned long exynos4_board_ram_size[EXYNOS4_NUM_OF_BOARDS] = {
-+    DEFINE_PROP_UINT32("SYS_VERSION", IoTKitSysCtl, sys_version, 0),
+-    [EXYNOS4_BOARD_NURI]     = 0x40000000,
-+    DEFINE_PROP_END_OF_LIST()
+-    [EXYNOS4_BOARD_SMDKC210] = 0x40000000,
-+};
++    [EXYNOS4_BOARD_NURI]     = 1 * GiB,
-+
++    [EXYNOS4_BOARD_SMDKC210] = 1 * GiB,
- static void iotkit_sysctl_class_init(ObjectClass *klass, void *data)
+ };
- {
-     DeviceClass *dc = DEVICE_CLASS(klass);
+ static struct arm_boot_info exynos4_board_binfo = {
      dc->vmsd = &iotkit_sysctl_vmstate;
      dc->reset = iotkit_sysctl_reset;
 +    dc->props = iotkit_sysctl_props;
 +    dc->realize = iotkit_sysctl_realize;
  }
  static const TypeInfo iotkit_sysctl_info = {
 --
 .20.1

-[Qemu-devel] [PULL 14/16] target/arm: Implement VFMAL and VFMSL for aarch32
+[Qemu-devel] [PULL 11/12] hw/arm/exynos4210: Add DMA support for the Exynos4210
-From: Richard Henderson <richard.henderson@linaro.org>
+From: Guenter Roeck <linux@roeck-us.net>
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
+QEMU already supports pl330. Instantiate it for Exynos4210.
-Message-id: 20190219222952.22183-4-richard.henderson@linaro.org
 Relevant part of Linux arch/arm/boot/dts/exynos4.dtsi:
 / {
     soc: soc {
         amba {
             pdma0: pdma@12680000 {
                 compatible = "arm,pl330", "arm,primecell";
                 reg = <0x12680000 0x1000>;
                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&clock CLK_PDMA0>;
                 clock-names = "apb_pclk";
                 #dma-cells = <1>;
                 #dma-channels = <8>;
                 #dma-requests = <32>;
             };
             pdma1: pdma@12690000 {
                 compatible = "arm,pl330", "arm,primecell";
                 reg = <0x12690000 0x1000>;
                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&clock CLK_PDMA1>;
                 clock-names = "apb_pclk";
                 #dma-cells = <1>;
                 #dma-channels = <8>;
                 #dma-requests = <32>;
             };
             mdma1: mdma@12850000 {
                 compatible = "arm,pl330", "arm,primecell";
                 reg = <0x12850000 0x1000>;
                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
                 clocks = <&clock CLK_MDMA>;
                 clock-names = "apb_pclk";
                 #dma-cells = <1>;
                 #dma-channels = <8>;
                 #dma-requests = <1>;
             };
         };
     };
 };
 Signed-off-by: Guenter Roeck <linux@roeck-us.net>
 Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Message-id: 20190520214342.13709-4-philmd@redhat.com
 [PMD: Do not set default qdev properties, create the controllers in the SoC
       rather than the board (Peter Maydell), add dtsi in commit message]
 Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
 Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
 ---
- target/arm/cpu.h       |   5 ++
+ hw/arm/exynos4210.c | 26 ++++++++++++++++++++++++++
- target/arm/translate.c | 129 ++++++++++++++++++++++++++++++-----------
+file changed, 26 insertions(+)
 files changed, 101 insertions(+), 33 deletions(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
+diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
 index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
+--- a/hw/arm/exynos4210.c
-+++ b/target/arm/cpu.h
++++ b/hw/arm/exynos4210.c
-@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
+@@ -XXX,XX +XXX,XX @@
-     return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
+ /* EHCI */
  #define EXYNOS4210_EHCI_BASE_ADDR           0x12580000
 +/* DMA */
 +#define EXYNOS4210_PL330_BASE0_ADDR         0x12680000
 +#define EXYNOS4210_PL330_BASE1_ADDR         0x12690000
 +#define EXYNOS4210_PL330_BASE2_ADDR         0x12850000
 +
  static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
 x09, 0x00, 0x00, 0x00 };
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu)
      return (0x9 << ARM_AFF1_SHIFT) | cpu;
  }
-+static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)
++static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
 +{
-+    return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
++    SysBusDevice *busdev;
 +    DeviceState *dev;
 +
 +    dev = qdev_create(NULL, "pl330");
 +    qdev_prop_set_uint8(dev, "num_periph_req",  nreq);
 +    qdev_init_nofail(dev);
 +    busdev = SYS_BUS_DEVICE(dev);
 +    sysbus_mmio_map(busdev, 0, base);
 +    sysbus_connect_irq(busdev, 0, irq);
 +}
 +
- static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
+ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
  {
-     /*
+     Exynos4210State *s = g_new0(Exynos4210State, 1);
-diff --git a/target/arm/translate.c b/target/arm/translate.c
+@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
-index XXXXXXX..XXXXXXX 100644
+     sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
---- a/target/arm/translate.c
+             s->irq_table[exynos4210_get_irq(28, 3)]);
-+++ b/target/arm/translate.c
-@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
++    /*** DMA controllers ***/
-     gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL;
++    pl330_create(EXYNOS4210_PL330_BASE0_ADDR,
-     int rd, rn, rm, opr_sz;
++                 qemu_irq_invert(s->irq_table[exynos4210_get_irq(35, 1)]), 32);
-     int data = 0;
++    pl330_create(EXYNOS4210_PL330_BASE1_ADDR,
--    bool q;
++                 qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
--
++    pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
--    q = extract32(insn, 6, 1);
++                 qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
 -    VFP_DREG_D(rd, insn);
 -    VFP_DREG_N(rn, insn);
 -    VFP_DREG_M(rm, insn);
 -    if ((rd | rn | rm) & q) {
 -        return 1;
 -    }
 +    int off_rn, off_rm;
 +    bool is_long = false, q = extract32(insn, 6, 1);
 +    bool ptr_is_env = false;
      if ((insn & 0xfe200f10) == 0xfc200800) {
          /* VCMLA -- 1111 110R R.1S .... .... 1000 ...0 .... */
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
              return 1;
          }
          fn_gvec = u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b;
 +    } else if ((insn & 0xff300f10) == 0xfc200810) {
 +        /* VFM[AS]L -- 1111 1100 S.10 .... .... 1000 .Q.1 .... */
 +        int is_s = extract32(insn, 23, 1);
 +        if (!dc_isar_feature(aa32_fhm, s)) {
 +            return 1;
 +        }
 +        is_long = true;
 +        data = is_s; /* is_2 == 0 */
 +        fn_gvec_ptr = gen_helper_gvec_fmlal_a32;
 +        ptr_is_env = true;
      } else {
          return 1;
      }
 +    VFP_DREG_D(rd, insn);
 +    if (rd & q) {
 +        return 1;
 +    }
 +    if (q || !is_long) {
 +        VFP_DREG_N(rn, insn);
 +        VFP_DREG_M(rm, insn);
 +        if ((rn | rm) & q & !is_long) {
 +            return 1;
 +        }
 +        off_rn = vfp_reg_offset(1, rn);
 +        off_rm = vfp_reg_offset(1, rm);
 +    } else {
 +        rn = VFP_SREG_N(insn);
 +        rm = VFP_SREG_M(insn);
 +        off_rn = vfp_reg_offset(0, rn);
 +        off_rm = vfp_reg_offset(0, rm);
 +    }
 +
-     if (s->fp_excp_el) {
+     return s;
-         gen_exception_insn(s, 4, EXCP_UDEF,
+ }
                             syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
      opr_sz = (1 + q) * 8;
      if (fn_gvec_ptr) {
 -        TCGv_ptr fpst = get_fpstatus_ptr(1);
 -        tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd),
 -                           vfp_reg_offset(1, rn),
 -                           vfp_reg_offset(1, rm), fpst,
 +        TCGv_ptr ptr;
 +        if (ptr_is_env) {
 +            ptr = cpu_env;
 +        } else {
 +            ptr = get_fpstatus_ptr(1);
 +        }
 +        tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr,
                             opr_sz, opr_sz, data, fn_gvec_ptr);
 -        tcg_temp_free_ptr(fpst);
 +        if (!ptr_is_env) {
 +            tcg_temp_free_ptr(ptr);
 +        }
      } else {
 -        tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd),
 -                           vfp_reg_offset(1, rn),
 -                           vfp_reg_offset(1, rm),
 +        tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm,
                             opr_sz, opr_sz, data, fn_gvec);
      }
      return 0;
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
      gen_helper_gvec_3 *fn_gvec = NULL;
      gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL;
      int rd, rn, rm, opr_sz, data;
 -    bool q;
 -
 -    q = extract32(insn, 6, 1);
 -    VFP_DREG_D(rd, insn);
 -    VFP_DREG_N(rn, insn);
 -    if ((rd | rn) & q) {
 -        return 1;
 -    }
 +    int off_rn, off_rm;
 +    bool is_long = false, q = extract32(insn, 6, 1);
 +    bool ptr_is_env = false;
      if ((insn & 0xff000f10) == 0xfe000800) {
          /* VCMLA (indexed) -- 1111 1110 S.RR .... .... 1000 ...0 .... */
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
      } else if ((insn & 0xffb00f00) == 0xfe200d00) {
          /* V[US]DOT -- 1111 1110 0.10 .... .... 1101 .Q.U .... */
          int u = extract32(insn, 4, 1);
 +
          if (!dc_isar_feature(aa32_dp, s)) {
              return 1;
          }
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
          /* rm is just Vm, and index is M.  */
          data = extract32(insn, 5, 1); /* index */
          rm = extract32(insn, 0, 4);
 +    } else if ((insn & 0xffa00f10) == 0xfe000810) {
 +        /* VFM[AS]L -- 1111 1110 0.0S .... .... 1000 .Q.1 .... */
 +        int is_s = extract32(insn, 20, 1);
 +        int vm20 = extract32(insn, 0, 3);
 +        int vm3 = extract32(insn, 3, 1);
 +        int m = extract32(insn, 5, 1);
 +        int index;
 +
 +        if (!dc_isar_feature(aa32_fhm, s)) {
 +            return 1;
 +        }
 +        if (q) {
 +            rm = vm20;
 +            index = m * 2 + vm3;
 +        } else {
 +            rm = vm20 * 2 + m;
 +            index = vm3;
 +        }
 +        is_long = true;
 +        data = (index << 2) | is_s; /* is_2 == 0 */
 +        fn_gvec_ptr = gen_helper_gvec_fmlal_idx_a32;
 +        ptr_is_env = true;
      } else {
          return 1;
      }
 +    VFP_DREG_D(rd, insn);
 +    if (rd & q) {
 +        return 1;
 +    }
 +    if (q || !is_long) {
 +        VFP_DREG_N(rn, insn);
 +        if (rn & q & !is_long) {
 +            return 1;
 +        }
 +        off_rn = vfp_reg_offset(1, rn);
 +        off_rm = vfp_reg_offset(1, rm);
 +    } else {
 +        rn = VFP_SREG_N(insn);
 +        off_rn = vfp_reg_offset(0, rn);
 +        off_rm = vfp_reg_offset(0, rm);
 +    }
      if (s->fp_excp_el) {
          gen_exception_insn(s, 4, EXCP_UDEF,
                             syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
      opr_sz = (1 + q) * 8;
      if (fn_gvec_ptr) {
 -        TCGv_ptr fpst = get_fpstatus_ptr(1);
 -        tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd),
 -                           vfp_reg_offset(1, rn),
 -                           vfp_reg_offset(1, rm), fpst,
 +        TCGv_ptr ptr;
 +        if (ptr_is_env) {
 +            ptr = cpu_env;
 +        } else {
 +            ptr = get_fpstatus_ptr(1);
 +        }
 +        tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr,
                             opr_sz, opr_sz, data, fn_gvec_ptr);
 -        tcg_temp_free_ptr(fpst);
 +        if (!ptr_is_env) {
 +            tcg_temp_free_ptr(ptr);
 +        }
      } else {
 -        tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd),
 -                           vfp_reg_offset(1, rn),
 -                           vfp_reg_offset(1, rm),
 +        tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm,
                             opr_sz, opr_sz, data, fn_gvec);
      }
      return 0;
 --
 .20.1

-[Qemu-devel] [PULL 01/16] hw/misc/armsse-mhu.c: Model the SSE-200 Message Handling Unit
+[Qemu-devel] [PULL 12/12] hw/arm/exynos4210: QOM'ify the Exynos4210 SoC
-Implement a model of the Message Handling Unit (MHU) found in
+From: Philippe Mathieu-Daudé <philmd@redhat.com>
 the Arm SSE-200. This is a simple device which just contains
 some registers which allow the two cores of the SSE-200
 to raise interrupts on each other.
+Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
+Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
+Message-id: 20190520214342.13709-5-philmd@redhat.com
 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20190219125808.25174-2-peter.maydell@linaro.org
 ---
- hw/misc/Makefile.objs           |   1 +
+ include/hw/arm/exynos4210.h |  9 +++++++--
- include/hw/misc/armsse-mhu.h    |  44 +++++++
+ hw/arm/exynos4210.c         | 28 ++++++++++++++++++++++++----
- hw/misc/armsse-mhu.c            | 198 ++++++++++++++++++++++++++++++++
+ hw/arm/exynos4_boards.c     |  9 ++++++---
- MAINTAINERS                     |   2 +
+files changed, 37 insertions(+), 9 deletions(-)
  default-configs/arm-softmmu.mak |   1 +
  hw/misc/trace-events            |   4 +
 files changed, 250 insertions(+)
  create mode 100644 include/hw/misc/armsse-mhu.h
  create mode 100644 hw/misc/armsse-mhu.c
-diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
+diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
 index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/Makefile.objs
+--- a/include/hw/arm/exynos4210.h
-+++ b/hw/misc/Makefile.objs
++++ b/include/hw/arm/exynos4210.h
-@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_IOTKIT_SECCTL) += iotkit-secctl.o
+@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210Irq {
- obj-$(CONFIG_IOTKIT_SYSCTL) += iotkit-sysctl.o
+ } Exynos4210Irq;
- obj-$(CONFIG_IOTKIT_SYSINFO) += iotkit-sysinfo.o
- obj-$(CONFIG_ARMSSE_CPUID) += armsse-cpuid.o
+ typedef struct Exynos4210State {
 +obj-$(CONFIG_ARMSSE_MHU) += armsse-mhu.o
  obj-$(CONFIG_PVPANIC) += pvpanic.o
  obj-$(CONFIG_AUX) += auxbus.o
 diff --git a/include/hw/misc/armsse-mhu.h b/include/hw/misc/armsse-mhu.h
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/include/hw/misc/armsse-mhu.h
@@ -XXX,XX +XXX,XX @@
 +/*
 + * ARM SSE-200 Message Handling Unit (MHU)
 + *
 + * Copyright (c) 2019 Linaro Limited
 + * Written by Peter Maydell
 + *
 + *  This program is free software; you can redistribute it and/or modify
 + *  it under the terms of the GNU General Public License version 2 or
 + *  (at your option) any later version.
 + */
 +
 +/*
 + * This is a model of the Message Handling Unit (MHU) which is part of the
 + * Arm SSE-200 and documented in
 + * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
 + *
 + * QEMU interface:
 + *  + sysbus MMIO region 0: the system information register bank
 + *  + sysbus IRQ 0: interrupt for CPU 0
 + *  + sysbus IRQ 1: interrupt for CPU 1
 + */
 +
 +#ifndef HW_MISC_SSE_MHU_H
 +#define HW_MISC_SSE_MHU_H
 +
 +#include "hw/sysbus.h"
 +
 +#define TYPE_ARMSSE_MHU "armsse-mhu"
 +#define ARMSSE_MHU(obj) OBJECT_CHECK(ARMSSEMHU, (obj), TYPE_ARMSSE_MHU)
 +
 +typedef struct ARMSSEMHU {
 +    /*< private >*/
 +    SysBusDevice parent_obj;
++    /*< public >*/
+     ARMCPU *cpu[EXYNOS4210_NCPUS];
+     Exynos4210Irq irqs;
+     qemu_irq *irq_table;
+@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210State {
+     I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
+ } Exynos4210State;
++#define TYPE_EXYNOS4210_SOC "exynos4210"
++#define EXYNOS4210_SOC(obj) \
++    OBJECT_CHECK(Exynos4210State, obj, TYPE_EXYNOS4210_SOC)
 +
-+    /*< public >*/
+ void exynos4210_write_secondary(ARMCPU *cpu,
-+    MemoryRegion iomem;
+         const struct arm_boot_info *info);
-+    qemu_irq cpu0irq;
-+    qemu_irq cpu1irq;
+-Exynos4210State *exynos4210_init(MemoryRegion *system_mem);
 -
  /* Initialize exynos4210 IRQ subsystem stub */
  qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
 diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
 index XXXXXXX..XXXXXXX 100644
 --- a/hw/arm/exynos4210.c
 +++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
      sysbus_connect_irq(busdev, 0, irq);
  }
 -Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
 +static void exynos4210_realize(DeviceState *socdev, Error **errp)
  {
 -    Exynos4210State *s = g_new0(Exynos4210State, 1);
 +    Exynos4210State *s = EXYNOS4210_SOC(socdev);
 +    MemoryRegion *system_mem = get_system_memory();
      qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
      SysBusDevice *busdev;
      DeviceState *dev;
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
                   qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
      pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
                   qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
 -
 -    return s;
  }
 +
-+    uint32_t cpu0intr;
++static void exynos4210_class_init(ObjectClass *klass, void *data)
 +    uint32_t cpu1intr;
 +} ARMSSEMHU;
 +
 +#endif
 diff --git a/hw/misc/armsse-mhu.c b/hw/misc/armsse-mhu.c
 new file mode 100644
 index XXXXXXX..XXXXXXX
 --- /dev/null
 +++ b/hw/misc/armsse-mhu.c
@@ -XXX,XX +XXX,XX @@
 +/*
 + * ARM SSE-200 Message Handling Unit (MHU)
 + *
 + * Copyright (c) 2019 Linaro Limited
 + * Written by Peter Maydell
 + *
 + *  This program is free software; you can redistribute it and/or modify
 + *  it under the terms of the GNU General Public License version 2 or
 + *  (at your option) any later version.
 + */
 +
 +/*
 + * This is a model of the Message Handling Unit (MHU) which is part of the
 + * Arm SSE-200 and documented in
 + * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
 + */
 +
 +#include "qemu/osdep.h"
 +#include "qemu/log.h"
 +#include "trace.h"
 +#include "qapi/error.h"
 +#include "sysemu/sysemu.h"
 +#include "hw/sysbus.h"
 +#include "hw/registerfields.h"
 +#include "hw/misc/armsse-mhu.h"
 +
 +REG32(CPU0INTR_STAT, 0x0)
 +REG32(CPU0INTR_SET, 0x4)
 +REG32(CPU0INTR_CLR, 0x8)
 +REG32(CPU1INTR_STAT, 0x10)
 +REG32(CPU1INTR_SET, 0x14)
 +REG32(CPU1INTR_CLR, 0x18)
 +REG32(PID4, 0xfd0)
 +REG32(PID5, 0xfd4)
 +REG32(PID6, 0xfd8)
 +REG32(PID7, 0xfdc)
 +REG32(PID0, 0xfe0)
 +REG32(PID1, 0xfe4)
 +REG32(PID2, 0xfe8)
 +REG32(PID3, 0xfec)
 +REG32(CID0, 0xff0)
 +REG32(CID1, 0xff4)
 +REG32(CID2, 0xff8)
 +REG32(CID3, 0xffc)
 +
 +/* Valid bits in the interrupt registers. If any are set the IRQ is raised */
 +#define INTR_MASK 0xf
 +
 +/* PID/CID values */
 +static const int armsse_mhu_id[] = {
 +    0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
 +    0x56, 0xb8, 0x0b, 0x00, /* PID0..PID3 */
 +    0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
 +};
 +
 +static void armsse_mhu_update(ARMSSEMHU *s)
 +{
 +    qemu_set_irq(s->cpu0irq, s->cpu0intr != 0);
 +    qemu_set_irq(s->cpu1irq, s->cpu1intr != 0);
 +}
 +
 +static uint64_t armsse_mhu_read(void *opaque, hwaddr offset, unsigned size)
 +{
 +    ARMSSEMHU *s = ARMSSE_MHU(opaque);
 +    uint64_t r;
 +
 +    switch (offset) {
 +    case A_CPU0INTR_STAT:
 +        r = s->cpu0intr;
 +        break;
 +
 +    case A_CPU1INTR_STAT:
 +        r = s->cpu1intr;
 +        break;
 +
 +    case A_PID4 ... A_CID3:
 +        r = armsse_mhu_id[(offset - A_PID4) / 4];
 +        break;
 +
 +    case A_CPU0INTR_SET:
 +    case A_CPU0INTR_CLR:
 +    case A_CPU1INTR_SET:
 +    case A_CPU1INTR_CLR:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "SSE MHU: read of write-only register at offset 0x%x\n",
 +                      (int)offset);
 +        r = 0;
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "SSE MHU read: bad offset 0x%x\n", (int)offset);
 +        r = 0;
 +        break;
 +    }
 +    trace_armsse_mhu_read(offset, r, size);
 +    return r;
 +}
 +
 +static void armsse_mhu_write(void *opaque, hwaddr offset,
 +                             uint64_t value, unsigned size)
 +{
 +    ARMSSEMHU *s = ARMSSE_MHU(opaque);
 +
 +    trace_armsse_mhu_write(offset, value, size);
 +
 +    switch (offset) {
 +    case A_CPU0INTR_SET:
 +        s->cpu0intr |= (value & INTR_MASK);
 +        break;
 +    case A_CPU0INTR_CLR:
 +        s->cpu0intr &= ~(value & INTR_MASK);
 +        break;
 +    case A_CPU1INTR_SET:
 +        s->cpu1intr |= (value & INTR_MASK);
 +        break;
 +    case A_CPU1INTR_CLR:
 +        s->cpu1intr &= ~(value & INTR_MASK);
 +        break;
 +
 +    case A_CPU0INTR_STAT:
 +    case A_CPU1INTR_STAT:
 +    case A_PID4 ... A_CID3:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "SSE MHU: write to read-only register at offset 0x%x\n",
 +                      (int)offset);
 +        break;
 +
 +    default:
 +        qemu_log_mask(LOG_GUEST_ERROR,
 +                      "SSE MHU write: bad offset 0x%x\n", (int)offset);
 +        break;
 +    }
 +
 +    armsse_mhu_update(s);
 +}
 +
 +static const MemoryRegionOps armsse_mhu_ops = {
 +    .read = armsse_mhu_read,
 +    .write = armsse_mhu_write,
 +    .endianness = DEVICE_LITTLE_ENDIAN,
 +    .valid.min_access_size = 4,
 +    .valid.max_access_size = 4,
 +};
 +
 +static void armsse_mhu_reset(DeviceState *dev)
 +{
 +    ARMSSEMHU *s = ARMSSE_MHU(dev);
 +
 +    s->cpu0intr = 0;
 +    s->cpu1intr = 0;
 +}
 +
 +static const VMStateDescription armsse_mhu_vmstate = {
 +    .name = "armsse-mhu",
 +    .version_id = 1,
 +    .minimum_version_id = 1,
 +    .fields = (VMStateField[]) {
 +        VMSTATE_UINT32(cpu0intr, ARMSSEMHU),
 +        VMSTATE_UINT32(cpu1intr, ARMSSEMHU),
 +        VMSTATE_END_OF_LIST()
 +    },
 +};
 +
 +static void armsse_mhu_init(Object *obj)
 +{
 +    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 +    ARMSSEMHU *s = ARMSSE_MHU(obj);
 +
 +    memory_region_init_io(&s->iomem, obj, &armsse_mhu_ops,
 +                          s, "armsse-mhu", 0x1000);
 +    sysbus_init_mmio(sbd, &s->iomem);
 +    sysbus_init_irq(sbd, &s->cpu0irq);
 +    sysbus_init_irq(sbd, &s->cpu1irq);
 +}
 +
 +static void armsse_mhu_class_init(ObjectClass *klass, void *data)
 +{
 +    DeviceClass *dc = DEVICE_CLASS(klass);
 +
-+    dc->reset = armsse_mhu_reset;
++    dc->realize = exynos4210_realize;
 +    dc->vmsd = &armsse_mhu_vmstate;
 +}
 +
-+static const TypeInfo armsse_mhu_info = {
++static const TypeInfo exynos4210_info = {
-+    .name = TYPE_ARMSSE_MHU,
++    .name = TYPE_EXYNOS4210_SOC,
 +    .parent = TYPE_SYS_BUS_DEVICE,
-+    .instance_size = sizeof(ARMSSEMHU),
++    .instance_size = sizeof(Exynos4210State),
-+    .instance_init = armsse_mhu_init,
++    .class_init = exynos4210_class_init,
 +    .class_init = armsse_mhu_class_init,
 +};
 +
-+static void armsse_mhu_register_types(void)
++static void exynos4210_register_types(void)
 +{
-+    type_register_static(&armsse_mhu_info);
++    type_register_static(&exynos4210_info);
 +}
 +
-+type_init(armsse_mhu_register_types);
++type_init(exynos4210_register_types)
-diff --git a/MAINTAINERS b/MAINTAINERS
+diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
 index XXXXXXX..XXXXXXX 100644
---- a/MAINTAINERS
+--- a/hw/arm/exynos4_boards.c
-+++ b/MAINTAINERS
++++ b/hw/arm/exynos4_boards.c
-@@ -XXX,XX +XXX,XX @@ F: hw/misc/iotkit-sysinfo.c
+@@ -XXX,XX +XXX,XX @@ typedef enum Exynos4BoardType {
- F: include/hw/misc/iotkit-sysinfo.h
+ } Exynos4BoardType;
- F: hw/misc/armsse-cpuid.c
- F: include/hw/misc/armsse-cpuid.h
+ typedef struct Exynos4BoardState {
-+F: hw/misc/armsse-mhu.c
+-    Exynos4210State *soc;
-+F: include/hw/misc/armsse-mhu.h
++    Exynos4210State soc;
+     MemoryRegion dram0_mem;
- Musca
+     MemoryRegion dram1_mem;
- M: Peter Maydell <peter.maydell@linaro.org>
+ } Exynos4BoardState;
-diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
+@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
-index XXXXXXX..XXXXXXX 100644
+     exynos4_boards_init_ram(s, get_system_memory(),
---- a/default-configs/arm-softmmu.mak
+                             exynos4_board_ram_size[board_type]);
-+++ b/default-configs/arm-softmmu.mak
-@@ -XXX,XX +XXX,XX @@ CONFIG_IOTKIT_SECCTL=y
+-    s->soc = exynos4210_init(get_system_memory());
- CONFIG_IOTKIT_SYSCTL=y
++    object_initialize(&s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC);
- CONFIG_IOTKIT_SYSINFO=y
++    qdev_set_parent_bus(DEVICE(&s->soc), sysbus_get_default());
- CONFIG_ARMSSE_CPUID=y
++    object_property_set_bool(OBJECT(&s->soc), true, "realized",
-+CONFIG_ARMSSE_MHU=y
++                             &error_fatal);
- CONFIG_VERSATILE=y
+     return s;
- CONFIG_VERSATILE_PCI=y
+ }
-diff --git a/hw/misc/trace-events b/hw/misc/trace-events
+@@ -XXX,XX +XXX,XX @@ static void smdkc210_init(MachineState *machine)
-index XXXXXXX..XXXXXXX 100644
+                                                       EXYNOS4_BOARD_SMDKC210);
---- a/hw/misc/trace-events
-+++ b/hw/misc/trace-events
+     lan9215_init(SMDK_LAN9118_BASE_ADDR,
-@@ -XXX,XX +XXX,XX @@ iotkit_sysctl_reset(void) "IoTKit SysCtl: reset"
+-            qemu_irq_invert(s->soc->irq_table[exynos4210_get_irq(37, 1)]));
- # hw/misc/armsse-cpuid.c
++            qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)]));
- armsse_cpuid_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
+     arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo);
- armsse_cpuid_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
+ }
-+
 +# hw/misc/armsse-mhu.c
 +armsse_mhu_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
 +armsse_mhu_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
 --
 .20.1

-[Qemu-devel] [PULL 03/16] target/arm/cpu: Allow init-svtor property to be set after realize
+Deleted patch
-Make the M-profile "init-svtor" property be settable after realize.
-This matches the hardware, where this is a config signal which
-is sampled on CPU reset and can thus be changed between one
-reset and another. To do this we have to change the API we
-use to add the property.
-(We will need this capability for the SSE-200.)
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20190219125808.25174-4-peter.maydell@linaro.org
----
- target/arm/cpu.c | 29 ++++++++++++++++++++++++-----
-file changed, 24 insertions(+), 5 deletions(-)
-diff --git a/target/arm/cpu.c b/target/arm/cpu.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.c
-+++ b/target/arm/cpu.c
-@@ -XXX,XX +XXX,XX @@
- #include "target/arm/idau.h"
- #include "qemu/error-report.h"
- #include "qapi/error.h"
-+#include "qapi/visitor.h"
- #include "cpu.h"
- #include "internals.h"
- #include "qemu-common.h"
-@@ -XXX,XX +XXX,XX @@ static Property arm_cpu_pmsav7_dregion_property =
-                                            pmsav7_dregion,
-                                            qdev_prop_uint32, uint32_t);
--/* M profile: initial value of the Secure VTOR */
--static Property arm_cpu_initsvtor_property =
--            DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0);
-+static void arm_get_init_svtor(Object *obj, Visitor *v, const char *name,
-+                               void *opaque, Error **errp)
-+{
-+    ARMCPU *cpu = ARM_CPU(obj);
-+
-+    visit_type_uint32(v, name, &cpu->init_svtor, errp);
-+}
-+
-+static void arm_set_init_svtor(Object *obj, Visitor *v, const char *name,
-+                               void *opaque, Error **errp)
-+{
-+    ARMCPU *cpu = ARM_CPU(obj);
-+
-+    visit_type_uint32(v, name, &cpu->init_svtor, errp);
-+}
- void arm_cpu_post_init(Object *obj)
- {
-@@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj)
-                                  qdev_prop_allow_set_link_before_realize,
-                                  OBJ_PROP_LINK_STRONG,
-                                  &error_abort);
--        qdev_property_add_static(DEVICE(obj), &arm_cpu_initsvtor_property,
--                                 &error_abort);
-+        /*
-+         * M profile: initial value of the Secure VTOR. We can't just use
-+         * a simple DEFINE_PROP_UINT32 for this because we want to permit
-+         * the property to be set after realize.
-+         */
-+        object_property_add(obj, "init-svtor", "uint32",
-+                            arm_get_init_svtor, arm_set_init_svtor,
-+                            NULL, NULL, &error_abort);
-     }
-     qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
---
-.20.1

-[Qemu-devel] [PULL 05/16] hw/misc/iotkit-sysctl: Correct typo in INITSVTOR0 register name
+Deleted patch
-The iotkit-sysctl device has a register it names INITSVRTOR0.
-This is actually a typo present in the IoTKit documentation
-and also in part of the SSE-200 documentation:  it should be
-INITSVTOR0 because it is specifying the initial value of the
-Secure VTOR register in the CPU. Correct the typo.
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20190219125808.25174-6-peter.maydell@linaro.org
----
- include/hw/misc/iotkit-sysctl.h |  2 +-
- hw/misc/iotkit-sysctl.c         | 16 ++++++++--------
-files changed, 9 insertions(+), 9 deletions(-)
-diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h
-index XXXXXXX..XXXXXXX 100644
---- a/include/hw/misc/iotkit-sysctl.h
-+++ b/include/hw/misc/iotkit-sysctl.h
-@@ -XXX,XX +XXX,XX @@ typedef struct IoTKitSysCtl {
-     uint32_t reset_syndrome;
-     uint32_t reset_mask;
-     uint32_t gretreg;
--    uint32_t initsvrtor0;
-+    uint32_t initsvtor0;
-     uint32_t cpuwait;
-     uint32_t wicctrl;
- } IoTKitSysCtl;
-diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
-index XXXXXXX..XXXXXXX 100644
---- a/hw/misc/iotkit-sysctl.c
-+++ b/hw/misc/iotkit-sysctl.c
-@@ -XXX,XX +XXX,XX @@ REG32(RESET_MASK, 0x104)
- REG32(SWRESET, 0x108)
-     FIELD(SWRESET, SWRESETREQ, 9, 1)
- REG32(GRETREG, 0x10c)
--REG32(INITSVRTOR0, 0x110)
-+REG32(INITSVTOR0, 0x110)
- REG32(CPUWAIT, 0x118)
- REG32(BUSWAIT, 0x11c)
- REG32(WICCTRL, 0x120)
-@@ -XXX,XX +XXX,XX @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
-     case A_GRETREG:
-         r = s->gretreg;
-         break;
--    case A_INITSVRTOR0:
--        r = s->initsvrtor0;
-+    case A_INITSVTOR0:
-+        r = s->initsvtor0;
-         break;
-     case A_CPUWAIT:
-         r = s->cpuwait;
-@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
-          */
-         s->gretreg = value;
-         break;
--    case A_INITSVRTOR0:
--        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVRTOR0 unimplemented\n");
--        s->initsvrtor0 = value;
-+    case A_INITSVTOR0:
-+        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR0 unimplemented\n");
-+        s->initsvtor0 = value;
-         break;
-     case A_CPUWAIT:
-         qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CPUWAIT unimplemented\n");
-@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_reset(DeviceState *dev)
-     s->reset_syndrome = 1;
-     s->reset_mask = 0;
-     s->gretreg = 0;
--    s->initsvrtor0 = 0x10000000;
-+    s->initsvtor0 = 0x10000000;
-     s->cpuwait = 0;
-     s->wicctrl = 0;
- }
-@@ -XXX,XX +XXX,XX @@ static const VMStateDescription iotkit_sysctl_vmstate = {
-         VMSTATE_UINT32(reset_syndrome, IoTKitSysCtl),
-         VMSTATE_UINT32(reset_mask, IoTKitSysCtl),
-         VMSTATE_UINT32(gretreg, IoTKitSysCtl),
--        VMSTATE_UINT32(initsvrtor0, IoTKitSysCtl),
-+        VMSTATE_UINT32(initsvtor0, IoTKitSysCtl),
-         VMSTATE_UINT32(cpuwait, IoTKitSysCtl),
-         VMSTATE_UINT32(wicctrl, IoTKitSysCtl),
-         VMSTATE_END_OF_LIST()
---
-.20.1

-[Qemu-devel] [PULL 11/16] Revert "arm: Allow system registers for KVM guests to be changed by QEMU code"
+Deleted patch
-This reverts commit 823e1b3818f9b10b824ddcd756983b6e2fa68730,
-which introduces a regression running EDK2 guest firmware
-under KVM:
-error: kvm run failed Function not implemented
- PC=000000013f5a6208 X00=00000000404003c4 X01=000000000000003a
-X02=0000000000000000 X03=00000000404003c4 X04=0000000000000000
-X05=0000000096000046 X06=000000013d2ef270 X07=000000013e3d1710
-X08=09010755ffaf8ba8 X09=ffaf8b9cfeeb5468 X10=feeb546409010756
-X11=09010757ffaf8b90 X12=feeb50680903068b X13=090306a1ffaf8bc0
-X14=0000000000000000 X15=0000000000000000 X16=000000013f872da0
-X17=00000000ffffa6ab X18=0000000000000000 X19=000000013f5a92d0
-X20=000000013f5a7a78 X21=000000000000003a X22=000000013f5a7ab2
-X23=000000013f5a92e8 X24=000000013f631090 X25=0000000000000010
-X26=0000000000000100 X27=000000013f89501b X28=000000013e3d14e0
-X29=000000013e3d12a0 X30=000000013f5a2518  SP=000000013b7be0b0
-PSTATE=404003c4 -Z-- EL1t
-with
-[ 3507.926571] kvm [35042]: load/store instruction decoding not implemented
-in the host dmesg.
-Revert the change for the moment until we can investigate the
-cause of the regression.
-Reported-by: Eric Auger <eric.auger@redhat.com>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/cpu.h     |  9 +--------
- target/arm/helper.c  | 27 ++-------------------------
- target/arm/kvm32.c   | 20 ++++++++++++++++++--
- target/arm/kvm64.c   |  2 --
- target/arm/machine.c |  2 +-
-files changed, 22 insertions(+), 38 deletions(-)
-diff --git a/target/arm/cpu.h b/target/arm/cpu.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/cpu.h
-+++ b/target/arm/cpu.h
-@@ -XXX,XX +XXX,XX @@ bool write_list_to_cpustate(ARMCPU *cpu);
- /**
-  * write_cpustate_to_list:
-  * @cpu: ARMCPU
-- * @kvm_sync: true if this is for syncing back to KVM
-  *
-  * For each register listed in the ARMCPU cpreg_indexes list, write
-  * its value from the ARMCPUState structure into the cpreg_values list.
-  * This is used to copy info from TCG's working data structures into
-  * KVM or for outbound migration.
-  *
-- * @kvm_sync is true if we are doing this in order to sync the
-- * register state back to KVM. In this case we will only update
-- * values in the list if the previous list->cpustate sync actually
-- * successfully wrote the CPU state. Otherwise we will keep the value
-- * that is in the list.
-- *
-  * Returns: true if all register values were read correctly,
-  * false if some register was unknown or could not be read.
-  * Note that we do not stop early on failure -- we will attempt
-  * reading all registers in the list.
-  */
--bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
-+bool write_cpustate_to_list(ARMCPU *cpu);
- #define ARM_CPUID_TI915T      0x54029152
- #define ARM_CPUID_TI925T      0x54029252
-diff --git a/target/arm/helper.c b/target/arm/helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.c
-+++ b/target/arm/helper.c
-@@ -XXX,XX +XXX,XX @@ static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
-     return true;
- }
--bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync)
-+bool write_cpustate_to_list(ARMCPU *cpu)
- {
-     /* Write the coprocessor state from cpu->env to the (index,value) list. */
-     int i;
-@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync)
-     for (i = 0; i < cpu->cpreg_array_len; i++) {
-         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
-         const ARMCPRegInfo *ri;
--        uint64_t newval;
-         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
-         if (!ri) {
-@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync)
-         if (ri->type & ARM_CP_NO_RAW) {
-             continue;
-         }
--
--        newval = read_raw_cp_reg(&cpu->env, ri);
--        if (kvm_sync) {
--            /*
--             * Only sync if the previous list->cpustate sync succeeded.
--             * Rather than tracking the success/failure state for every
--             * item in the list, we just recheck "does the raw write we must
--             * have made in write_list_to_cpustate() read back OK" here.
--             */
--            uint64_t oldval = cpu->cpreg_values[i];
--
--            if (oldval == newval) {
--                continue;
--            }
--
--            write_raw_cp_reg(&cpu->env, ri, oldval);
--            if (read_raw_cp_reg(&cpu->env, ri) != oldval) {
--                continue;
--            }
--
--            write_raw_cp_reg(&cpu->env, ri, newval);
--        }
--        cpu->cpreg_values[i] = newval;
-+        cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
-     }
-     return ok;
- }
-diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/kvm32.c
-+++ b/target/arm/kvm32.c
-@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
-         return ret;
-     }
--    write_cpustate_to_list(cpu, true);
--
-+    /* Note that we do not call write_cpustate_to_list()
-+     * here, so we are only writing the tuple list back to
-+     * KVM. This is safe because nothing can change the
-+     * CPUARMState cp15 fields (in particular gdb accesses cannot)
-+     * and so there are no changes to sync. In fact syncing would
-+     * be wrong at this point: for a constant register where TCG and
-+     * KVM disagree about its value, the preceding write_list_to_cpustate()
-+     * would not have had any effect on the CPUARMState value (since the
-+     * register is read-only), and a write_cpustate_to_list() here would
-+     * then try to write the TCG value back into KVM -- this would either
-+     * fail or incorrectly change the value the guest sees.
-+     *
-+     * If we ever want to allow the user to modify cp15 registers via
-+     * the gdb stub, we would need to be more clever here (for instance
-+     * tracking the set of registers kvm_arch_get_registers() successfully
-+     * managed to update the CPUARMState with, and only allowing those
-+     * to be written back up into the kernel).
-+     */
-     if (!write_list_to_kvmstate(cpu, level)) {
-         return EINVAL;
-     }
-diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/kvm64.c
-+++ b/target/arm/kvm64.c
-@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
-         return ret;
-     }
--    write_cpustate_to_list(cpu, true);
--
-     if (!write_list_to_kvmstate(cpu, level)) {
-         return EINVAL;
-     }
-diff --git a/target/arm/machine.c b/target/arm/machine.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/machine.c
-+++ b/target/arm/machine.c
-@@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque)
-             abort();
-         }
-     } else {
--        if (!write_cpustate_to_list(cpu, false)) {
-+        if (!write_cpustate_to_list(cpu)) {
-             /* This should never fail. */
-             abort();
-         }
---
-.20.1

-[Qemu-devel] [PULL 12/16] target/arm: Add helpers for FMLAL
+Deleted patch
-From: Richard Henderson <richard.henderson@linaro.org>
-Note that float16_to_float32 rightly squashes SNaN to QNaN.
-But of course pickNaNMulAdd, for ARM, selects SNaNs first.
-So we have to preserve SNaN long enough for the correct NaN
-to be selected.  Thus float16_to_float32_by_bits.
-Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-Message-id: 20190219222952.22183-2-richard.henderson@linaro.org
-Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
-Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
----
- target/arm/helper.h     |   9 +++
- target/arm/vec_helper.c | 148 ++++++++++++++++++++++++++++++++++++++++
-files changed, 157 insertions(+)
-diff --git a/target/arm/helper.h b/target/arm/helper.h
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/helper.h
-+++ b/target/arm/helper.h
-@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_sqsub_s, TCG_CALL_NO_RWG,
- DEF_HELPER_FLAGS_5(gvec_sqsub_d, TCG_CALL_NO_RWG,
-                    void, ptr, ptr, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_5(gvec_fmlal_a32, TCG_CALL_NO_RWG,
-+                   void, ptr, ptr, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_5(gvec_fmlal_a64, TCG_CALL_NO_RWG,
-+                   void, ptr, ptr, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a32, TCG_CALL_NO_RWG,
-+                   void, ptr, ptr, ptr, ptr, i32)
-+DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a64, TCG_CALL_NO_RWG,
-+                   void, ptr, ptr, ptr, ptr, i32)
-+
- #ifdef TARGET_AARCH64
- #include "helper-a64.h"
- #include "helper-sve.h"
-diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
-index XXXXXXX..XXXXXXX 100644
---- a/target/arm/vec_helper.c
-+++ b/target/arm/vec_helper.c
-@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sqsub_d)(void *vd, void *vq, void *vn,
-     }
-     clear_tail(d, oprsz, simd_maxsz(desc));
- }
-+
-+/*
-+ * Convert float16 to float32, raising no exceptions and
-+ * preserving exceptional values, including SNaN.
-+ * This is effectively an unpack+repack operation.
-+ */
-+static float32 float16_to_float32_by_bits(uint32_t f16, bool fz16)
-+{
-+    const int f16_bias = 15;
-+    const int f32_bias = 127;
-+    uint32_t sign = extract32(f16, 15, 1);
-+    uint32_t exp = extract32(f16, 10, 5);
-+    uint32_t frac = extract32(f16, 0, 10);
-+
-+    if (exp == 0x1f) {
-+        /* Inf or NaN */
-+        exp = 0xff;
-+    } else if (exp == 0) {
-+        /* Zero or denormal.  */
-+        if (frac != 0) {
-+            if (fz16) {
-+                frac = 0;
-+            } else {
-+                /*
-+                 * Denormal; these are all normal float32.
-+                 * Shift the fraction so that the msb is at bit 11,
-+                 * then remove bit 11 as the implicit bit of the
-+                 * normalized float32.  Note that we still go through
-+                 * the shift for normal numbers below, to put the
-+                 * float32 fraction at the right place.
-+                 */
-+                int shift = clz32(frac) - 21;
-+                frac = (frac << shift) & 0x3ff;
-+                exp = f32_bias - f16_bias - shift + 1;
-+            }
-+        }
-+    } else {
-+        /* Normal number; adjust the bias.  */
-+        exp += f32_bias - f16_bias;
-+    }
-+    sign <<= 31;
-+    exp <<= 23;
-+    frac <<= 23 - 10;
-+
-+    return sign | exp | frac;
-+}
-+
-+static uint64_t load4_f16(uint64_t *ptr, int is_q, int is_2)
-+{
-+    /*
-+     * Branchless load of u32[0], u64[0], u32[1], or u64[1].
-+     * Load the 2nd qword iff is_q & is_2.
-+     * Shift to the 2nd dword iff !is_q & is_2.
-+     * For !is_q & !is_2, the upper bits of the result are garbage.
-+     */
-+    return ptr[is_q & is_2] >> ((is_2 & ~is_q) << 5);
-+}
-+
-+/*
-+ * Note that FMLAL requires oprsz == 8 or oprsz == 16,
-+ * as there is not yet SVE versions that might use blocking.
-+ */
-+
-+static void do_fmlal(float32 *d, void *vn, void *vm, float_status *fpst,
-+                     uint32_t desc, bool fz16)
-+{
-+    intptr_t i, oprsz = simd_oprsz(desc);
-+    int is_s = extract32(desc, SIMD_DATA_SHIFT, 1);
-+    int is_2 = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
-+    int is_q = oprsz == 16;
-+    uint64_t n_4, m_4;
-+
-+    /* Pre-load all of the f16 data, avoiding overlap issues.  */
-+    n_4 = load4_f16(vn, is_q, is_2);
-+    m_4 = load4_f16(vm, is_q, is_2);
-+
-+    /* Negate all inputs for FMLSL at once.  */
-+    if (is_s) {
-+        n_4 ^= 0x8000800080008000ull;
-+    }
-+
-+    for (i = 0; i < oprsz / 4; i++) {
-+        float32 n_1 = float16_to_float32_by_bits(n_4 >> (i * 16), fz16);
-+        float32 m_1 = float16_to_float32_by_bits(m_4 >> (i * 16), fz16);
-+        d[H4(i)] = float32_muladd(n_1, m_1, d[H4(i)], 0, fpst);
-+    }
-+    clear_tail(d, oprsz, simd_maxsz(desc));
-+}
-+
-+void HELPER(gvec_fmlal_a32)(void *vd, void *vn, void *vm,
-+                            void *venv, uint32_t desc)
-+{
-+    CPUARMState *env = venv;
-+    do_fmlal(vd, vn, vm, &env->vfp.standard_fp_status, desc,
-+             get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
-+}
-+
-+void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void *vm,
-+                            void *venv, uint32_t desc)
-+{
-+    CPUARMState *env = venv;
-+    do_fmlal(vd, vn, vm, &env->vfp.fp_status, desc,
-+             get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
-+}
-+
-+static void do_fmlal_idx(float32 *d, void *vn, void *vm, float_status *fpst,
-+                         uint32_t desc, bool fz16)
-+{
-+    intptr_t i, oprsz = simd_oprsz(desc);
-+    int is_s = extract32(desc, SIMD_DATA_SHIFT, 1);
-+    int is_2 = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
-+    int index = extract32(desc, SIMD_DATA_SHIFT + 2, 3);
-+    int is_q = oprsz == 16;
-+    uint64_t n_4;
-+    float32 m_1;
-+
-+    /* Pre-load all of the f16 data, avoiding overlap issues.  */
-+    n_4 = load4_f16(vn, is_q, is_2);
-+
-+    /* Negate all inputs for FMLSL at once.  */
-+    if (is_s) {
-+        n_4 ^= 0x8000800080008000ull;
-+    }
-+
-+    m_1 = float16_to_float32_by_bits(((float16 *)vm)[H2(index)], fz16);
-+
-+    for (i = 0; i < oprsz / 4; i++) {
-+        float32 n_1 = float16_to_float32_by_bits(n_4 >> (i * 16), fz16);
-+        d[H4(i)] = float32_muladd(n_1, m_1, d[H4(i)], 0, fpst);
-+    }
-+    clear_tail(d, oprsz, simd_maxsz(desc));
-+}
-+
-+void HELPER(gvec_fmlal_idx_a32)(void *vd, void *vn, void *vm,
-+                                void *venv, uint32_t desc)
-+{
-+    CPUARMState *env = venv;
-+    do_fmlal_idx(vd, vn, vm, &env->vfp.standard_fp_status, desc,
-+                 get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
-+}
-+
-+void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm,
-+                                void *venv, uint32_t desc)
-+{
-+    CPUARMState *env = venv;
-+    do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status, desc,
-+                 get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
-+}
---
-.20.1

The following changes since commit adf2e451f357e993f173ba9b4176dbf3e65fee7e:

Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2019-02-26 19:04:47 +0000)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190228-1

for you to fetch changes up to 1c9af3a9e05c1607a36df4943f8f5393d7621a91:

linux-user: Enable HWCAP_ASIMDFHM, HWCAP_JSCVT (2019-02-28 11:03:05 +0000)

----------------------------------------------------------------
target-arm queue:
 * add MHU and dual-core support to Musca boards
 * refactor some VFP insns to be gated by ID registers
 * Revert "arm: Allow system registers for KVM guests to be changed by QEMU code"
 * Implement ARMv8.2-FHM extension
 * Advertise JSCVT via HWCAP for linux-user

----------------------------------------------------------------
Peter Maydell (11):
      hw/misc/armsse-mhu.c: Model the SSE-200 Message Handling Unit
      hw/arm/armsse: Wire up the MHUs
      target/arm/cpu: Allow init-svtor property to be set after realize
      target/arm/arm-powerctl: Add new arm_set_cpu_on_and_reset()
      hw/misc/iotkit-sysctl: Correct typo in INITSVTOR0 register name
      hw/arm/iotkit-sysctl: Add SSE-200 registers
      hw/arm/iotkit-sysctl: Implement CPUWAIT and INITSVTOR*
      hw/arm/armsse: Unify init-svtor and cpuwait handling
      target/arm: Use MVFR1 feature bits to gate A32/T32 FP16 instructions
      target/arm: Gate "miscellaneous FP" insns by ID register field
      Revert "arm: Allow system registers for KVM guests to be changed by QEMU code"

Richard Henderson (5):
      target/arm: Add helpers for FMLAL
      target/arm: Implement FMLAL and FMLSL for aarch64
      target/arm: Implement VFMAL and VFMSL for aarch32
      target/arm: Enable ARMv8.2-FHM for -cpu max
      linux-user: Enable HWCAP_ASIMDFHM, HWCAP_JSCVT

Implement a model of the Message Handling Unit (MHU) found in
the Arm SSE-200. This is a simple device which just contains
some registers which allow the two cores of the SSE-200
to raise interrupts on each other.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190219125808.25174-2-peter.maydell@linaro.org
---
 hw/misc/Makefile.objs           |   1 +
 include/hw/misc/armsse-mhu.h    |  44 +++++++
 hw/misc/armsse-mhu.c            | 198 ++++++++++++++++++++++++++++++++
 MAINTAINERS                     |   2 +
 default-configs/arm-softmmu.mak |   1 +
 hw/misc/trace-events            |   4 +
 6 files changed, 250 insertions(+)
 create mode 100644 include/hw/misc/armsse-mhu.h
 create mode 100644 hw/misc/armsse-mhu.c

diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -XXX,XX +XXX,XX @@ obj-$(CONFIG_IOTKIT_SECCTL) += iotkit-secctl.o
 obj-$(CONFIG_IOTKIT_SYSCTL) += iotkit-sysctl.o
 obj-$(CONFIG_IOTKIT_SYSINFO) += iotkit-sysinfo.o
 obj-$(CONFIG_ARMSSE_CPUID) += armsse-cpuid.o
+obj-$(CONFIG_ARMSSE_MHU) += armsse-mhu.o
 
 obj-$(CONFIG_PVPANIC) += pvpanic.o
 obj-$(CONFIG_AUX) += auxbus.o
diff --git a/include/hw/misc/armsse-mhu.h b/include/hw/misc/armsse-mhu.h
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/include/hw/misc/armsse-mhu.h
@@ -XXX,XX +XXX,XX @@
+/*
+ * ARM SSE-200 Message Handling Unit (MHU)
+ *
+ * Copyright (c) 2019 Linaro Limited
+ * Written by Peter Maydell
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 or
+ *  (at your option) any later version.
+ */
+
+/*
+ * This is a model of the Message Handling Unit (MHU) which is part of the
+ * Arm SSE-200 and documented in
+ * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
+ *
+ * QEMU interface:
+ *  + sysbus MMIO region 0: the system information register bank
+ *  + sysbus IRQ 0: interrupt for CPU 0
+ *  + sysbus IRQ 1: interrupt for CPU 1
+ */
+
+#ifndef HW_MISC_SSE_MHU_H
+#define HW_MISC_SSE_MHU_H
+
+#include "hw/sysbus.h"
+
+#define TYPE_ARMSSE_MHU "armsse-mhu"
+#define ARMSSE_MHU(obj) OBJECT_CHECK(ARMSSEMHU, (obj), TYPE_ARMSSE_MHU)
+
+typedef struct ARMSSEMHU {
+    /*< private >*/
+    SysBusDevice parent_obj;
+
+    /*< public >*/
+    MemoryRegion iomem;
+    qemu_irq cpu0irq;
+    qemu_irq cpu1irq;
+
+    uint32_t cpu0intr;
+    uint32_t cpu1intr;
+} ARMSSEMHU;
+
+#endif
diff --git a/hw/misc/armsse-mhu.c b/hw/misc/armsse-mhu.c
new file mode 100644
index XXXXXXX..XXXXXXX
--- /dev/null
+++ b/hw/misc/armsse-mhu.c
@@ -XXX,XX +XXX,XX @@
+/*
+ * ARM SSE-200 Message Handling Unit (MHU)
+ *
+ * Copyright (c) 2019 Linaro Limited
+ * Written by Peter Maydell
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 or
+ *  (at your option) any later version.
+ */
+
+/*
+ * This is a model of the Message Handling Unit (MHU) which is part of the
+ * Arm SSE-200 and documented in
+ * http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "trace.h"
+#include "qapi/error.h"
+#include "sysemu/sysemu.h"
+#include "hw/sysbus.h"
+#include "hw/registerfields.h"
+#include "hw/misc/armsse-mhu.h"
+
+REG32(CPU0INTR_STAT, 0x0)
+REG32(CPU0INTR_SET, 0x4)
+REG32(CPU0INTR_CLR, 0x8)
+REG32(CPU1INTR_STAT, 0x10)
+REG32(CPU1INTR_SET, 0x14)
+REG32(CPU1INTR_CLR, 0x18)
+REG32(PID4, 0xfd0)
+REG32(PID5, 0xfd4)
+REG32(PID6, 0xfd8)
+REG32(PID7, 0xfdc)
+REG32(PID0, 0xfe0)
+REG32(PID1, 0xfe4)
+REG32(PID2, 0xfe8)
+REG32(PID3, 0xfec)
+REG32(CID0, 0xff0)
+REG32(CID1, 0xff4)
+REG32(CID2, 0xff8)
+REG32(CID3, 0xffc)
+
+/* Valid bits in the interrupt registers. If any are set the IRQ is raised */
+#define INTR_MASK 0xf
+
+/* PID/CID values */
+static const int armsse_mhu_id[] = {
+    0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
+    0x56, 0xb8, 0x0b, 0x00, /* PID0..PID3 */
+    0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
+};
+
+static void armsse_mhu_update(ARMSSEMHU *s)
+{
+    qemu_set_irq(s->cpu0irq, s->cpu0intr != 0);
+    qemu_set_irq(s->cpu1irq, s->cpu1intr != 0);
+}
+
+static uint64_t armsse_mhu_read(void *opaque, hwaddr offset, unsigned size)
+{
+    ARMSSEMHU *s = ARMSSE_MHU(opaque);
+    uint64_t r;
+
+    switch (offset) {
+    case A_CPU0INTR_STAT:
+        r = s->cpu0intr;
+        break;
+
+    case A_CPU1INTR_STAT:
+        r = s->cpu1intr;
+        break;
+
+    case A_PID4 ... A_CID3:
+        r = armsse_mhu_id[(offset - A_PID4) / 4];
+        break;
+
+    case A_CPU0INTR_SET:
+    case A_CPU0INTR_CLR:
+    case A_CPU1INTR_SET:
+    case A_CPU1INTR_CLR:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "SSE MHU: read of write-only register at offset 0x%x\n",
+                      (int)offset);
+        r = 0;
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "SSE MHU read: bad offset 0x%x\n", (int)offset);
+        r = 0;
+        break;
+    }
+    trace_armsse_mhu_read(offset, r, size);
+    return r;
+}
+
+static void armsse_mhu_write(void *opaque, hwaddr offset,
+                             uint64_t value, unsigned size)
+{
+    ARMSSEMHU *s = ARMSSE_MHU(opaque);
+
+    trace_armsse_mhu_write(offset, value, size);
+
+    switch (offset) {
+    case A_CPU0INTR_SET:
+        s->cpu0intr |= (value & INTR_MASK);
+        break;
+    case A_CPU0INTR_CLR:
+        s->cpu0intr &= ~(value & INTR_MASK);
+        break;
+    case A_CPU1INTR_SET:
+        s->cpu1intr |= (value & INTR_MASK);
+        break;
+    case A_CPU1INTR_CLR:
+        s->cpu1intr &= ~(value & INTR_MASK);
+        break;
+
+    case A_CPU0INTR_STAT:
+    case A_CPU1INTR_STAT:
+    case A_PID4 ... A_CID3:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "SSE MHU: write to read-only register at offset 0x%x\n",
+                      (int)offset);
+        break;
+
+    default:
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "SSE MHU write: bad offset 0x%x\n", (int)offset);
+        break;
+    }
+
+    armsse_mhu_update(s);
+}
+
+static const MemoryRegionOps armsse_mhu_ops = {
+    .read = armsse_mhu_read,
+    .write = armsse_mhu_write,
+    .endianness = DEVICE_LITTLE_ENDIAN,
+    .valid.min_access_size = 4,
+    .valid.max_access_size = 4,
+};
+
+static void armsse_mhu_reset(DeviceState *dev)
+{
+    ARMSSEMHU *s = ARMSSE_MHU(dev);
+
+    s->cpu0intr = 0;
+    s->cpu1intr = 0;
+}
+
+static const VMStateDescription armsse_mhu_vmstate = {
+    .name = "armsse-mhu",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(cpu0intr, ARMSSEMHU),
+        VMSTATE_UINT32(cpu1intr, ARMSSEMHU),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
+static void armsse_mhu_init(Object *obj)
+{
+    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+    ARMSSEMHU *s = ARMSSE_MHU(obj);
+
+    memory_region_init_io(&s->iomem, obj, &armsse_mhu_ops,
+                          s, "armsse-mhu", 0x1000);
+    sysbus_init_mmio(sbd, &s->iomem);
+    sysbus_init_irq(sbd, &s->cpu0irq);
+    sysbus_init_irq(sbd, &s->cpu1irq);
+}
+
+static void armsse_mhu_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->reset = armsse_mhu_reset;
+    dc->vmsd = &armsse_mhu_vmstate;
+}
+
+static const TypeInfo armsse_mhu_info = {
+    .name = TYPE_ARMSSE_MHU,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(ARMSSEMHU),
+    .instance_init = armsse_mhu_init,
+    .class_init = armsse_mhu_class_init,
+};
+
+static void armsse_mhu_register_types(void)
+{
+    type_register_static(&armsse_mhu_info);
+}
+
+type_init(armsse_mhu_register_types);
diff --git a/MAINTAINERS b/MAINTAINERS
index XXXXXXX..XXXXXXX 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -XXX,XX +XXX,XX @@ F: hw/misc/iotkit-sysinfo.c
 F: include/hw/misc/iotkit-sysinfo.h
 F: hw/misc/armsse-cpuid.c
 F: include/hw/misc/armsse-cpuid.h
+F: hw/misc/armsse-mhu.c
+F: include/hw/misc/armsse-mhu.h
 
 Musca
 M: Peter Maydell <peter.maydell@linaro.org>
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.mak
index XXXXXXX..XXXXXXX 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -XXX,XX +XXX,XX @@ CONFIG_IOTKIT_SECCTL=y
 CONFIG_IOTKIT_SYSCTL=y
 CONFIG_IOTKIT_SYSINFO=y
 CONFIG_ARMSSE_CPUID=y
+CONFIG_ARMSSE_MHU=y
 
 CONFIG_VERSATILE=y
 CONFIG_VERSATILE_PCI=y
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -XXX,XX +XXX,XX @@ iotkit_sysctl_reset(void) "IoTKit SysCtl: reset"
 # hw/misc/armsse-cpuid.c
 armsse_cpuid_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
 armsse_cpuid_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 CPU_IDENTITY write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
+
+# hw/misc/armsse-mhu.c
+armsse_mhu_read(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
+armsse_mhu_write(uint64_t offset, uint64_t data, unsigned size) "SSE-200 MHU write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
-- 
2.20.1

Create and connect the MHUs in the SSE-200.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190219125808.25174-3-peter.maydell@linaro.org
---
 include/hw/arm/armsse.h |  3 ++-
 hw/arm/armsse.c         | 40 ++++++++++++++++++++++++++++++----------
 2 files changed, 32 insertions(+), 11 deletions(-)

diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/armsse.h
+++ b/include/hw/arm/armsse.h
@@ -XXX,XX +XXX,XX @@
 #include "hw/misc/iotkit-sysctl.h"
 #include "hw/misc/iotkit-sysinfo.h"
 #include "hw/misc/armsse-cpuid.h"
+#include "hw/misc/armsse-mhu.h"
 #include "hw/misc/unimp.h"
 #include "hw/or-irq.h"
 #include "hw/core/split-irq.h"
@@ -XXX,XX +XXX,XX @@ typedef struct ARMSSE {
     IoTKitSysCtl sysctl;
     IoTKitSysCtl sysinfo;
 
-    UnimplementedDeviceState mhu[2];
+    ARMSSEMHU mhu[2];
     UnimplementedDeviceState ppu[NUM_PPUS];
     UnimplementedDeviceState cachectrl[SSE_MAX_CPUS];
     UnimplementedDeviceState cpusecctrl[SSE_MAX_CPUS];
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -XXX,XX +XXX,XX @@ static void armsse_init(Object *obj)
                           sizeof(s->sysinfo), TYPE_IOTKIT_SYSINFO);
     if (info->has_mhus) {
         sysbus_init_child_obj(obj, "mhu0", &s->mhu[0], sizeof(s->mhu[0]),
-                              TYPE_UNIMPLEMENTED_DEVICE);
+                              TYPE_ARMSSE_MHU);
         sysbus_init_child_obj(obj, "mhu1", &s->mhu[1], sizeof(s->mhu[1]),
-                              TYPE_UNIMPLEMENTED_DEVICE);
+                              TYPE_ARMSSE_MHU);
     }
     if (info->has_ppus) {
         for (i = 0; i < info->num_cpus; i++) {
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
     }
 
     if (info->has_mhus) {
-        for (i = 0; i < ARRAY_SIZE(s->mhu); i++) {
-            char *name;
-            char *port;
+        /*
+         * An SSE-200 with only one CPU should have only one MHU created,
+         * with the region where the second MHU usually is being RAZ/WI.
+         * We don't implement that SSE-200 config; if we want to support
+         * it then this code needs to be enhanced to handle creating the
+         * RAZ/WI region instead of the second MHU.
+         */
+        assert(info->num_cpus == ARRAY_SIZE(s->mhu));
+
+        for (i = 0; i < ARRAY_SIZE(s->mhu); i++) {
+            char *port;
+            int cpunum;
+            SysBusDevice *mhu_sbd = SYS_BUS_DEVICE(&s->mhu[i]);
 
-            name = g_strdup_printf("MHU%d", i);
-            qdev_prop_set_string(DEVICE(&s->mhu[i]), "name", name);
-            qdev_prop_set_uint64(DEVICE(&s->mhu[i]), "size", 0x1000);
             object_property_set_bool(OBJECT(&s->mhu[i]), true,
                                      "realized", &err);
-            g_free(name);
             if (err) {
                 error_propagate(errp, err);
                 return;
             }
             port = g_strdup_printf("port[%d]", i + 3);
-            mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mhu[i]), 0);
+            mr = sysbus_mmio_get_region(mhu_sbd, 0);
             object_property_set_link(OBJECT(&s->apb_ppc0), OBJECT(mr),
                                      port, &err);
             g_free(port);
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
                 error_propagate(errp, err);
                 return;
             }
+
+            /*
+             * Each MHU has an irq line for each CPU:
+             *  MHU 0 irq line 0 -> CPU 0 IRQ 6
+             *  MHU 0 irq line 1 -> CPU 1 IRQ 6
+             *  MHU 1 irq line 0 -> CPU 0 IRQ 7
+             *  MHU 1 irq line 1 -> CPU 1 IRQ 7
+             */
+            for (cpunum = 0; cpunum < info->num_cpus; cpunum++) {
+                DeviceState *cpudev = DEVICE(&s->armv7m[cpunum]);
+
+                sysbus_connect_irq(mhu_sbd, cpunum,
+                                   qdev_get_gpio_in(cpudev, 6 + i));
+            }
         }
     }
 
-- 
2.20.1

Make the M-profile "init-svtor" property be settable after realize.
This matches the hardware, where this is a config signal which
is sampled on CPU reset and can thus be changed between one
reset and another. To do this we have to change the API we
use to add the property.

(We will need this capability for the SSE-200.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190219125808.25174-4-peter.maydell@linaro.org
---
 target/arm/cpu.c | 29 ++++++++++++++++++++++++-----
 1 file changed, 24 insertions(+), 5 deletions(-)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
 #include "target/arm/idau.h"
 #include "qemu/error-report.h"
 #include "qapi/error.h"
+#include "qapi/visitor.h"
 #include "cpu.h"
 #include "internals.h"
 #include "qemu-common.h"
@@ -XXX,XX +XXX,XX @@ static Property arm_cpu_pmsav7_dregion_property =
                                            pmsav7_dregion,
                                            qdev_prop_uint32, uint32_t);
 
-/* M profile: initial value of the Secure VTOR */
-static Property arm_cpu_initsvtor_property =
-            DEFINE_PROP_UINT32("init-svtor", ARMCPU, init_svtor, 0);
+static void arm_get_init_svtor(Object *obj, Visitor *v, const char *name,
+                               void *opaque, Error **errp)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    visit_type_uint32(v, name, &cpu->init_svtor, errp);
+}
+
+static void arm_set_init_svtor(Object *obj, Visitor *v, const char *name,
+                               void *opaque, Error **errp)
+{
+    ARMCPU *cpu = ARM_CPU(obj);
+
+    visit_type_uint32(v, name, &cpu->init_svtor, errp);
+}
 
 void arm_cpu_post_init(Object *obj)
 {
@@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj)
                                  qdev_prop_allow_set_link_before_realize,
                                  OBJ_PROP_LINK_STRONG,
                                  &error_abort);
-        qdev_property_add_static(DEVICE(obj), &arm_cpu_initsvtor_property,
-                                 &error_abort);
+        /*
+         * M profile: initial value of the Secure VTOR. We can't just use
+         * a simple DEFINE_PROP_UINT32 for this because we want to permit
+         * the property to be set after realize.
+         */
+        object_property_add(obj, "init-svtor", "uint32",
+                            arm_get_init_svtor, arm_set_init_svtor,
+                            NULL, NULL, &error_abort);
     }
 
     qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property,
-- 
2.20.1

Currently the Arm arm-powerctl.h APIs allow:
 * arm_set_cpu_on(), which powers on a CPU and sets its
   initial PC and other startup state
 * arm_reset_cpu(), which resets a CPU which is already on
   (and fails if the CPU is powered off)

but there is no way to say "power on a CPU as if it had
just come out of reset and don't do anything else to it".

Add a new function arm_set_cpu_on_and_reset(), which does this.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190219125808.25174-5-peter.maydell@linaro.org
---
 target/arm/arm-powerctl.h | 16 +++++++++++
 target/arm/arm-powerctl.c | 56 +++++++++++++++++++++++++++++++++++++++
 2 files changed, 72 insertions(+)

diff --git a/target/arm/arm-powerctl.h b/target/arm/arm-powerctl.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/arm-powerctl.h
+++ b/target/arm/arm-powerctl.h
@@ -XXX,XX +XXX,XX @@ int arm_set_cpu_off(uint64_t cpuid);
  */
 int arm_reset_cpu(uint64_t cpuid);
 
+/*
+ * arm_set_cpu_on_and_reset:
+ * @cpuid: the id of the CPU we want to star
+ *
+ * Start the cpu designated by @cpuid and put it through its normal
+ * CPU reset process. The CPU will start in the way it is architected
+ * to start after a power-on reset.
+ *
+ * Returns: QEMU_ARM_POWERCTL_RET_SUCCESS on success.
+ * QEMU_ARM_POWERCTL_INVALID_PARAM if there is no CPU with that ID.
+ * QEMU_ARM_POWERCTL_ALREADY_ON if the CPU is already on.
+ * QEMU_ARM_POWERCTL_ON_PENDING if the CPU is already partway through
+ * powering on.
+ */
+int arm_set_cpu_on_and_reset(uint64_t cpuid);
+
 #endif
diff --git a/target/arm/arm-powerctl.c b/target/arm/arm-powerctl.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/arm-powerctl.c
+++ b/target/arm/arm-powerctl.c
@@ -XXX,XX +XXX,XX @@ int arm_set_cpu_on(uint64_t cpuid, uint64_t entry, uint64_t context_id,
     return QEMU_ARM_POWERCTL_RET_SUCCESS;
 }
 
+static void arm_set_cpu_on_and_reset_async_work(CPUState *target_cpu_state,
+                                                run_on_cpu_data data)
+{
+    ARMCPU *target_cpu = ARM_CPU(target_cpu_state);
+
+    /* Initialize the cpu we are turning on */
+    cpu_reset(target_cpu_state);
+    target_cpu_state->halted = 0;
+
+    /* Finally set the power status */
+    assert(qemu_mutex_iothread_locked());
+    target_cpu->power_state = PSCI_ON;
+}
+
+int arm_set_cpu_on_and_reset(uint64_t cpuid)
+{
+    CPUState *target_cpu_state;
+    ARMCPU *target_cpu;
+
+    assert(qemu_mutex_iothread_locked());
+
+    /* Retrieve the cpu we are powering up */
+    target_cpu_state = arm_get_cpu_by_id(cpuid);
+    if (!target_cpu_state) {
+        /* The cpu was not found */
+        return QEMU_ARM_POWERCTL_INVALID_PARAM;
+    }
+
+    target_cpu = ARM_CPU(target_cpu_state);
+    if (target_cpu->power_state == PSCI_ON) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "[ARM]%s: CPU %" PRId64 " is already on\n",
+                      __func__, cpuid);
+        return QEMU_ARM_POWERCTL_ALREADY_ON;
+    }
+
+    /*
+     * If another CPU has powered the target on we are in the state
+     * ON_PENDING and additional attempts to power on the CPU should
+     * fail (see 6.6 Implementation CPU_ON/CPU_OFF races in the PSCI
+     * spec)
+     */
+    if (target_cpu->power_state == PSCI_ON_PENDING) {
+        qemu_log_mask(LOG_GUEST_ERROR,
+                      "[ARM]%s: CPU %" PRId64 " is already powering on\n",
+                      __func__, cpuid);
+        return QEMU_ARM_POWERCTL_ON_PENDING;
+    }
+
+    async_run_on_cpu(target_cpu_state, arm_set_cpu_on_and_reset_async_work,
+                     RUN_ON_CPU_NULL);
+
+    /* We are good to go */
+    return QEMU_ARM_POWERCTL_RET_SUCCESS;
+}
+
 static void arm_set_cpu_off_async_work(CPUState *target_cpu_state,
                                        run_on_cpu_data data)
 {
-- 
2.20.1

The iotkit-sysctl device has a register it names INITSVRTOR0.
This is actually a typo present in the IoTKit documentation
and also in part of the SSE-200 documentation:  it should be
INITSVTOR0 because it is specifying the initial value of the
Secure VTOR register in the CPU. Correct the typo.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190219125808.25174-6-peter.maydell@linaro.org
---
 include/hw/misc/iotkit-sysctl.h |  2 +-
 hw/misc/iotkit-sysctl.c         | 16 ++++++++--------
 2 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/misc/iotkit-sysctl.h
+++ b/include/hw/misc/iotkit-sysctl.h
@@ -XXX,XX +XXX,XX @@ typedef struct IoTKitSysCtl {
     uint32_t reset_syndrome;
     uint32_t reset_mask;
     uint32_t gretreg;
-    uint32_t initsvrtor0;
+    uint32_t initsvtor0;
     uint32_t cpuwait;
     uint32_t wicctrl;
 } IoTKitSysCtl;
diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/iotkit-sysctl.c
+++ b/hw/misc/iotkit-sysctl.c
@@ -XXX,XX +XXX,XX @@ REG32(RESET_MASK, 0x104)
 REG32(SWRESET, 0x108)
     FIELD(SWRESET, SWRESETREQ, 9, 1)
 REG32(GRETREG, 0x10c)
-REG32(INITSVRTOR0, 0x110)
+REG32(INITSVTOR0, 0x110)
 REG32(CPUWAIT, 0x118)
 REG32(BUSWAIT, 0x11c)
 REG32(WICCTRL, 0x120)
@@ -XXX,XX +XXX,XX @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
     case A_GRETREG:
         r = s->gretreg;
         break;
-    case A_INITSVRTOR0:
-        r = s->initsvrtor0;
+    case A_INITSVTOR0:
+        r = s->initsvtor0;
         break;
     case A_CPUWAIT:
         r = s->cpuwait;
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
          */
         s->gretreg = value;
         break;
-    case A_INITSVRTOR0:
-        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVRTOR0 unimplemented\n");
-        s->initsvrtor0 = value;
+    case A_INITSVTOR0:
+        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR0 unimplemented\n");
+        s->initsvtor0 = value;
         break;
     case A_CPUWAIT:
         qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CPUWAIT unimplemented\n");
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_reset(DeviceState *dev)
     s->reset_syndrome = 1;
     s->reset_mask = 0;
     s->gretreg = 0;
-    s->initsvrtor0 = 0x10000000;
+    s->initsvtor0 = 0x10000000;
     s->cpuwait = 0;
     s->wicctrl = 0;
 }
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription iotkit_sysctl_vmstate = {
         VMSTATE_UINT32(reset_syndrome, IoTKitSysCtl),
         VMSTATE_UINT32(reset_mask, IoTKitSysCtl),
         VMSTATE_UINT32(gretreg, IoTKitSysCtl),
-        VMSTATE_UINT32(initsvrtor0, IoTKitSysCtl),
+        VMSTATE_UINT32(initsvtor0, IoTKitSysCtl),
         VMSTATE_UINT32(cpuwait, IoTKitSysCtl),
         VMSTATE_UINT32(wicctrl, IoTKitSysCtl),
         VMSTATE_END_OF_LIST()
-- 
2.20.1

The SYSCTL block in the SSE-200 has some extra registers that
are not present in the IoTKit version. Add these registers
(as reads-as-written stubs), enabled by a new QOM property.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190219125808.25174-7-peter.maydell@linaro.org
---
 include/hw/misc/iotkit-sysctl.h |  20 +++
 hw/arm/armsse.c                 |   2 +
 hw/misc/iotkit-sysctl.c         | 245 +++++++++++++++++++++++++++++++-
 3 files changed, 262 insertions(+), 5 deletions(-)

diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/misc/iotkit-sysctl.h
+++ b/include/hw/misc/iotkit-sysctl.h
@@ -XXX,XX +XXX,XX @@
  * "system control register" blocks.
  *
  * QEMU interface:
+ *  + QOM property "SYS_VERSION": value of the SYS_VERSION register of the
+ *    system information block of the SSE
+ *    (used to identify whether to provide SSE-200-only registers)
  *  + sysbus MMIO region 0: the system information register bank
  *  + sysbus MMIO region 1: the system control register bank
  */
@@ -XXX,XX +XXX,XX @@ typedef struct IoTKitSysCtl {
     uint32_t initsvtor0;
     uint32_t cpuwait;
     uint32_t wicctrl;
+    uint32_t scsecctrl;
+    uint32_t fclk_div;
+    uint32_t sysclk_div;
+    uint32_t clock_force;
+    uint32_t initsvtor1;
+    uint32_t nmi_enable;
+    uint32_t ewctrl;
+    uint32_t pdcm_pd_sys_sense;
+    uint32_t pdcm_pd_sram0_sense;
+    uint32_t pdcm_pd_sram1_sense;
+    uint32_t pdcm_pd_sram2_sense;
+    uint32_t pdcm_pd_sram3_sense;
+
+    /* Properties */
+    uint32_t sys_version;
+
+    bool is_sse200;
 } IoTKitSysCtl;
 
 #endif
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
     /* System information registers */
     sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysinfo), 0, 0x40020000);
     /* System control registers */
+    object_property_set_int(OBJECT(&s->sysctl), info->sys_version,
+                            "SYS_VERSION", &err);
     object_property_set_bool(OBJECT(&s->sysctl), true, "realized", &err);
     if (err) {
         error_propagate(errp, err);
diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/iotkit-sysctl.c
+++ b/hw/misc/iotkit-sysctl.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/bitops.h"
 #include "qemu/log.h"
 #include "trace.h"
 #include "qapi/error.h"
@@ -XXX,XX +XXX,XX @@
 REG32(SECDBGSTAT, 0x0)
 REG32(SECDBGSET, 0x4)
 REG32(SECDBGCLR, 0x8)
+REG32(SCSECCTRL, 0xc)
+REG32(FCLK_DIV, 0x10)
+REG32(SYSCLK_DIV, 0x14)
+REG32(CLOCK_FORCE, 0x18)
 REG32(RESET_SYNDROME, 0x100)
 REG32(RESET_MASK, 0x104)
 REG32(SWRESET, 0x108)
     FIELD(SWRESET, SWRESETREQ, 9, 1)
 REG32(GRETREG, 0x10c)
 REG32(INITSVTOR0, 0x110)
+REG32(INITSVTOR1, 0x114)
 REG32(CPUWAIT, 0x118)
-REG32(BUSWAIT, 0x11c)
+REG32(NMI_ENABLE, 0x11c) /* BUSWAIT in IoTKit */
 REG32(WICCTRL, 0x120)
+REG32(EWCTRL, 0x124)
+REG32(PDCM_PD_SYS_SENSE, 0x200)
+REG32(PDCM_PD_SRAM0_SENSE, 0x20c)
+REG32(PDCM_PD_SRAM1_SENSE, 0x210)
+REG32(PDCM_PD_SRAM2_SENSE, 0x214)
+REG32(PDCM_PD_SRAM3_SENSE, 0x218)
 REG32(PID4, 0xfd0)
 REG32(PID5, 0xfd4)
 REG32(PID6, 0xfd8)
@@ -XXX,XX +XXX,XX @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
     case A_SECDBGSTAT:
         r = s->secure_debug;
         break;
+    case A_SCSECCTRL:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        r = s->scsecctrl;
+        break;
+    case A_FCLK_DIV:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        r = s->fclk_div;
+        break;
+    case A_SYSCLK_DIV:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        r = s->sysclk_div;
+        break;
+    case A_CLOCK_FORCE:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        r = s->clock_force;
+        break;
     case A_RESET_SYNDROME:
         r = s->reset_syndrome;
         break;
@@ -XXX,XX +XXX,XX @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
     case A_INITSVTOR0:
         r = s->initsvtor0;
         break;
+    case A_INITSVTOR1:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        r = s->initsvtor1;
+        break;
     case A_CPUWAIT:
         r = s->cpuwait;
         break;
-    case A_BUSWAIT:
-        /* In IoTKit BUSWAIT is reserved, R/O, zero */
-        r = 0;
+    case A_NMI_ENABLE:
+        /* In IoTKit this is named BUSWAIT but is marked reserved, R/O, zero */
+        if (!s->is_sse200) {
+            r = 0;
+            break;
+        }
+        r = s->nmi_enable;
         break;
     case A_WICCTRL:
         r = s->wicctrl;
         break;
+    case A_EWCTRL:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        r = s->ewctrl;
+        break;
+    case A_PDCM_PD_SYS_SENSE:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        r = s->pdcm_pd_sys_sense;
+        break;
+    case A_PDCM_PD_SRAM0_SENSE:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        r = s->pdcm_pd_sram0_sense;
+        break;
+    case A_PDCM_PD_SRAM1_SENSE:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        r = s->pdcm_pd_sram1_sense;
+        break;
+    case A_PDCM_PD_SRAM2_SENSE:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        r = s->pdcm_pd_sram2_sense;
+        break;
+    case A_PDCM_PD_SRAM3_SENSE:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        r = s->pdcm_pd_sram3_sense;
+        break;
     case A_PID4 ... A_CID3:
         r = sysctl_id[(offset - A_PID4) / 4];
         break;
@@ -XXX,XX +XXX,XX @@ static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
         r = 0;
         break;
     default:
+    bad_offset:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "IoTKit SysCtl read: bad offset %x\n", (int)offset);
         r = 0;
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
             qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
         }
         break;
-    case A_BUSWAIT:        /* In IoTKit BUSWAIT is reserved, R/O, zero */
+    case A_SCSECCTRL:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SCSECCTRL unimplemented\n");
+        s->scsecctrl = value;
+        break;
+    case A_FCLK_DIV:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl FCLK_DIV unimplemented\n");
+        s->fclk_div = value;
+        break;
+    case A_SYSCLK_DIV:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl SYSCLK_DIV unimplemented\n");
+        s->sysclk_div = value;
+        break;
+    case A_CLOCK_FORCE:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CLOCK_FORCE unimplemented\n");
+        s->clock_force = value;
+        break;
+    case A_INITSVTOR1:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR1 unimplemented\n");
+        s->initsvtor1 = value;
+        break;
+    case A_EWCTRL:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl EWCTRL unimplemented\n");
+        s->ewctrl = value;
+        break;
+    case A_PDCM_PD_SYS_SENSE:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        qemu_log_mask(LOG_UNIMP,
+                      "IoTKit SysCtl PDCM_PD_SYS_SENSE unimplemented\n");
+        s->pdcm_pd_sys_sense = value;
+        break;
+    case A_PDCM_PD_SRAM0_SENSE:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        qemu_log_mask(LOG_UNIMP,
+                      "IoTKit SysCtl PDCM_PD_SRAM0_SENSE unimplemented\n");
+        s->pdcm_pd_sram0_sense = value;
+        break;
+    case A_PDCM_PD_SRAM1_SENSE:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        qemu_log_mask(LOG_UNIMP,
+                      "IoTKit SysCtl PDCM_PD_SRAM1_SENSE unimplemented\n");
+        s->pdcm_pd_sram1_sense = value;
+        break;
+    case A_PDCM_PD_SRAM2_SENSE:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        qemu_log_mask(LOG_UNIMP,
+                      "IoTKit SysCtl PDCM_PD_SRAM2_SENSE unimplemented\n");
+        s->pdcm_pd_sram2_sense = value;
+        break;
+    case A_PDCM_PD_SRAM3_SENSE:
+        if (!s->is_sse200) {
+            goto bad_offset;
+        }
+        qemu_log_mask(LOG_UNIMP,
+                      "IoTKit SysCtl PDCM_PD_SRAM3_SENSE unimplemented\n");
+        s->pdcm_pd_sram3_sense = value;
+        break;
+    case A_NMI_ENABLE:
+        /* In IoTKit this is BUSWAIT: reserved, R/O, zero */
+        if (!s->is_sse200) {
+            goto ro_offset;
+        }
+        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl NMI_ENABLE unimplemented\n");
+        s->nmi_enable = value;
+        break;
     case A_SECDBGSTAT:
     case A_PID4 ... A_CID3:
+    ro_offset:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "IoTKit SysCtl write: write of RO offset %x\n",
                       (int)offset);
         break;
     default:
+    bad_offset:
         qemu_log_mask(LOG_GUEST_ERROR,
                       "IoTKit SysCtl write: bad offset %x\n", (int)offset);
         break;
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_reset(DeviceState *dev)
     s->reset_mask = 0;
     s->gretreg = 0;
     s->initsvtor0 = 0x10000000;
+    s->initsvtor1 = 0x10000000;
     s->cpuwait = 0;
     s->wicctrl = 0;
+    s->scsecctrl = 0;
+    s->fclk_div = 0;
+    s->sysclk_div = 0;
+    s->clock_force = 0;
+    s->nmi_enable = 0;
+    s->ewctrl = 0;
+    s->pdcm_pd_sys_sense = 0x7f;
+    s->pdcm_pd_sram0_sense = 0;
+    s->pdcm_pd_sram1_sense = 0;
+    s->pdcm_pd_sram2_sense = 0;
+    s->pdcm_pd_sram3_sense = 0;
 }
 
 static void iotkit_sysctl_init(Object *obj)
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_init(Object *obj)
     sysbus_init_mmio(sbd, &s->iomem);
 }
 
+static void iotkit_sysctl_realize(DeviceState *dev, Error **errp)
+{
+    IoTKitSysCtl *s = IOTKIT_SYSCTL(dev);
+
+    /* The top 4 bits of the SYS_VERSION register tell us if we're an SSE-200 */
+    if (extract32(s->sys_version, 28, 4) == 2) {
+        s->is_sse200 = true;
+    }
+}
+
+static bool sse200_needed(void *opaque)
+{
+    IoTKitSysCtl *s = IOTKIT_SYSCTL(opaque);
+
+    return s->is_sse200;
+}
+
+static const VMStateDescription iotkit_sysctl_sse200_vmstate = {
+    .name = "iotkit-sysctl/sse-200",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = sse200_needed,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT32(scsecctrl, IoTKitSysCtl),
+        VMSTATE_UINT32(fclk_div, IoTKitSysCtl),
+        VMSTATE_UINT32(sysclk_div, IoTKitSysCtl),
+        VMSTATE_UINT32(clock_force, IoTKitSysCtl),
+        VMSTATE_UINT32(initsvtor1, IoTKitSysCtl),
+        VMSTATE_UINT32(nmi_enable, IoTKitSysCtl),
+        VMSTATE_UINT32(pdcm_pd_sys_sense, IoTKitSysCtl),
+        VMSTATE_UINT32(pdcm_pd_sram0_sense, IoTKitSysCtl),
+        VMSTATE_UINT32(pdcm_pd_sram1_sense, IoTKitSysCtl),
+        VMSTATE_UINT32(pdcm_pd_sram2_sense, IoTKitSysCtl),
+        VMSTATE_UINT32(pdcm_pd_sram3_sense, IoTKitSysCtl),
+        VMSTATE_END_OF_LIST()
+    }
+};
+
 static const VMStateDescription iotkit_sysctl_vmstate = {
     .name = "iotkit-sysctl",
     .version_id = 1,
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription iotkit_sysctl_vmstate = {
         VMSTATE_UINT32(cpuwait, IoTKitSysCtl),
         VMSTATE_UINT32(wicctrl, IoTKitSysCtl),
         VMSTATE_END_OF_LIST()
+    },
+    .subsections = (const VMStateDescription*[]) {
+        &iotkit_sysctl_sse200_vmstate,
+        NULL
     }
 };
 
+static Property iotkit_sysctl_props[] = {
+    DEFINE_PROP_UINT32("SYS_VERSION", IoTKitSysCtl, sys_version, 0),
+    DEFINE_PROP_END_OF_LIST()
+};
+
 static void iotkit_sysctl_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
 
     dc->vmsd = &iotkit_sysctl_vmstate;
     dc->reset = iotkit_sysctl_reset;
+    dc->props = iotkit_sysctl_props;
+    dc->realize = iotkit_sysctl_realize;
 }
 
 static const TypeInfo iotkit_sysctl_info = {
-- 
2.20.1

The CPUWAIT register acts as a sort of power-control: if a bit
in it is 1 then the CPU will have been forced into waiting
when the system was reset (which in QEMU we model as the
CPU starting powered off). Writing a 0 to the register will
allow the CPU to boot (for QEMU, we model this as powering
it on). Note that writing 0 to the register does not power
off a CPU.

For this to work correctly we need to also honour the
INITSVTOR* registers, which let the guest control where the
CPU will load its SP and PC from when it comes out of reset.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190219125808.25174-8-peter.maydell@linaro.org
---
 hw/misc/iotkit-sysctl.c | 41 +++++++++++++++++++++++++++++++++++++----
 1 file changed, 37 insertions(+), 4 deletions(-)

diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/iotkit-sysctl.c
+++ b/hw/misc/iotkit-sysctl.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "hw/registerfields.h"
 #include "hw/misc/iotkit-sysctl.h"
+#include "target/arm/arm-powerctl.h"
+#include "target/arm/cpu.h"
 
 REG32(SECDBGSTAT, 0x0)
 REG32(SECDBGSET, 0x4)
@@ -XXX,XX +XXX,XX @@ static const int sysctl_id[] = {
     0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
 };
 
+/*
+ * Set the initial secure vector table offset address for the core.
+ * This will take effect when the CPU next resets.
+ */
+static void set_init_vtor(uint64_t cpuid, uint32_t vtor)
+{
+    Object *cpuobj = OBJECT(arm_get_cpu_by_id(cpuid));
+
+    if (cpuobj) {
+        if (object_property_find(cpuobj, "init-svtor", NULL)) {
+            object_property_set_uint(cpuobj, vtor, "init-svtor", &error_abort);
+        }
+    }
+}
+
 static uint64_t iotkit_sysctl_read(void *opaque, hwaddr offset,
                                     unsigned size)
 {
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
         s->gretreg = value;
         break;
     case A_INITSVTOR0:
-        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR0 unimplemented\n");
         s->initsvtor0 = value;
+        set_init_vtor(0, s->initsvtor0);
         break;
     case A_CPUWAIT:
-        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl CPUWAIT unimplemented\n");
+        if ((s->cpuwait & 1) && !(value & 1)) {
+            /* Powering up CPU 0 */
+            arm_set_cpu_on_and_reset(0);
+        }
+        if ((s->cpuwait & 2) && !(value & 2)) {
+            /* Powering up CPU 1 */
+            arm_set_cpu_on_and_reset(1);
+        }
         s->cpuwait = value;
         break;
     case A_WICCTRL:
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_write(void *opaque, hwaddr offset,
         if (!s->is_sse200) {
             goto bad_offset;
         }
-        qemu_log_mask(LOG_UNIMP, "IoTKit SysCtl INITSVTOR1 unimplemented\n");
         s->initsvtor1 = value;
+        set_init_vtor(1, s->initsvtor1);
         break;
     case A_EWCTRL:
         if (!s->is_sse200) {
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_reset(DeviceState *dev)
     s->gretreg = 0;
     s->initsvtor0 = 0x10000000;
     s->initsvtor1 = 0x10000000;
-    s->cpuwait = 0;
+    if (s->is_sse200) {
+        /*
+         * CPU 0 starts on, CPU 1 starts off. In real hardware this is
+         * configurable by the SoC integrator as a verilog parameter.
+         */
+        s->cpuwait = 2;
+    } else {
+        /* CPU 0 starts on */
+        s->cpuwait = 0;
+    }
     s->wicctrl = 0;
     s->scsecctrl = 0;
     s->fclk_div = 0;
-- 
2.20.1

At the moment the handling of init-svtor and cpuwait initial
values is split between armsse.c and iotkit-sysctl.c:
the code in armsse.c sets the initial state of the CPU
object by setting the init-svtor and start-powered-off
properties, but the iotkit-sysctl.c code has its own
code setting the reset values of its registers (which are
then used when updating the CPU when the guest makes
runtime changes).

Clean this up by making the armsse.c code set properties on the
iotkit-sysctl object to define the initial values of the
registers, so they always match the initial CPU state,
and update the comments in armsse.c accordingly.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190219125808.25174-9-peter.maydell@linaro.org
---
 include/hw/misc/iotkit-sysctl.h |  3 ++
 hw/arm/armsse.c                 | 49 +++++++++++++++++++++------------
 hw/misc/iotkit-sysctl.c         | 20 ++++++--------
 3 files changed, 42 insertions(+), 30 deletions(-)

diff --git a/include/hw/misc/iotkit-sysctl.h b/include/hw/misc/iotkit-sysctl.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/misc/iotkit-sysctl.h
+++ b/include/hw/misc/iotkit-sysctl.h
@@ -XXX,XX +XXX,XX @@ typedef struct IoTKitSysCtl {
 
     /* Properties */
     uint32_t sys_version;
+    uint32_t cpuwait_rst;
+    uint32_t initsvtor0_rst;
+    uint32_t initsvtor1_rst;
 
     bool is_sse200;
 } IoTKitSysCtl;
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -XXX,XX +XXX,XX @@
 
 #include "qemu/osdep.h"
 #include "qemu/log.h"
+#include "qemu/bitops.h"
 #include "qapi/error.h"
 #include "trace.h"
 #include "hw/sysbus.h"
@@ -XXX,XX +XXX,XX @@ struct ARMSSEInfo {
     int sram_banks;
     int num_cpus;
     uint32_t sys_version;
+    uint32_t cpuwait_rst;
     SysConfigFormat sys_config_format;
     bool has_mhus;
     bool has_ppus;
@@ -XXX,XX +XXX,XX @@ static const ARMSSEInfo armsse_variants[] = {
         .sram_banks = 1,
         .num_cpus = 1,
         .sys_version = 0x41743,
+        .cpuwait_rst = 0,
         .sys_config_format = IoTKitFormat,
         .has_mhus = false,
         .has_ppus = false,
@@ -XXX,XX +XXX,XX @@ static const ARMSSEInfo armsse_variants[] = {
         .sram_banks = 4,
         .num_cpus = 2,
         .sys_version = 0x22041743,
+        .cpuwait_rst = 2,
         .sys_config_format = SSE200Format,
         .has_mhus = true,
         .has_ppus = true,
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
 
         qdev_prop_set_uint32(cpudev, "num-irq", s->exp_numirq + 32);
         /*
-         * In real hardware the initial Secure VTOR is set from the INITSVTOR0
-         * register in the IoT Kit System Control Register block, and the
-         * initial value of that is in turn specifiable by the FPGA that
-         * instantiates the IoT Kit. In QEMU we don't implement this wrinkle,
-         * and simply set the CPU's init-svtor to the IoT Kit default value.
-         * In SSE-200 the situation is similar, except that the default value
-         * is a reset-time signal input. Typically a board using the SSE-200
-         * will have a system control processor whose boot firmware initializes
-         * the INITSVTOR* registers before powering up the CPUs in any case,
-         * so the hardware's default value doesn't matter. QEMU doesn't emulate
+         * In real hardware the initial Secure VTOR is set from the INITSVTOR*
+         * registers in the IoT Kit System Control Register block. In QEMU
+         * we set the initial value here, and also the reset value of the
+         * sysctl register, from this object's QOM init-svtor property.
+         * If the guest changes the INITSVTOR* registers at runtime then the
+         * code in iotkit-sysctl.c will update the CPU init-svtor property
+         * (which will then take effect on the next CPU warm-reset).
+         *
+         * Note that typically a board using the SSE-200 will have a system
+         * control processor whose boot firmware initializes the INITSVTOR*
+         * registers before powering up the CPUs. QEMU doesn't emulate
          * the control processor, so instead we behave in the way that the
-         * firmware does. The initial value is configurable by the board code
-         * to match whatever its firmware does.
+         * firmware does: the initial value should be set by the board code
+         * (using the init-svtor property on the ARMSSE object) to match
+         * whatever its firmware does.
          */
         qdev_prop_set_uint32(cpudev, "init-svtor", s->init_svtor);
         /*
-         * Start all CPUs except CPU0 powered down. In real hardware it is
-         * a configurable property of the SSE-200 which CPUs start powered up
-         * (via the CPUWAIT0_RST and CPUWAIT1_RST parameters), but since all
-         * the boards we care about start CPU0 and leave CPU1 powered off,
-         * we hard-code that for now. We can add QOM properties for this
+         * CPUs start powered down if the corresponding bit in the CPUWAIT
+         * register is 1. In real hardware the CPUWAIT register reset value is
+         * a configurable property of the SSE-200 (via the CPUWAIT0_RST and
+         * CPUWAIT1_RST parameters), but since all the boards we care about
+         * start CPU0 and leave CPU1 powered off, we hard-code that in
+         * info->cpuwait_rst for now. We can add QOM properties for this
          * later if necessary.
          */
-        if (i > 0) {
+        if (extract32(info->cpuwait_rst, i, 1)) {
             object_property_set_bool(cpuobj, true, "start-powered-off", &err);
             if (err) {
                 error_propagate(errp, err);
@@ -XXX,XX +XXX,XX @@ static void armsse_realize(DeviceState *dev, Error **errp)
     /* System control registers */
     object_property_set_int(OBJECT(&s->sysctl), info->sys_version,
                             "SYS_VERSION", &err);
+    object_property_set_int(OBJECT(&s->sysctl), info->cpuwait_rst,
+                            "CPUWAIT_RST", &err);
+    object_property_set_int(OBJECT(&s->sysctl), s->init_svtor,
+                            "INITSVTOR0_RST", &err);
+    object_property_set_int(OBJECT(&s->sysctl), s->init_svtor,
+                            "INITSVTOR1_RST", &err);
     object_property_set_bool(OBJECT(&s->sysctl), true, "realized", &err);
     if (err) {
         error_propagate(errp, err);
diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/misc/iotkit-sysctl.c
+++ b/hw/misc/iotkit-sysctl.c
@@ -XXX,XX +XXX,XX @@ static void iotkit_sysctl_reset(DeviceState *dev)
     s->reset_syndrome = 1;
     s->reset_mask = 0;
     s->gretreg = 0;
-    s->initsvtor0 = 0x10000000;
-    s->initsvtor1 = 0x10000000;
-    if (s->is_sse200) {
-        /*
-         * CPU 0 starts on, CPU 1 starts off. In real hardware this is
-         * configurable by the SoC integrator as a verilog parameter.
-         */
-        s->cpuwait = 2;
-    } else {
-        /* CPU 0 starts on */
-        s->cpuwait = 0;
-    }
+    s->initsvtor0 = s->initsvtor0_rst;
+    s->initsvtor1 = s->initsvtor1_rst;
+    s->cpuwait = s->cpuwait_rst;
     s->wicctrl = 0;
     s->scsecctrl = 0;
     s->fclk_div = 0;
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription iotkit_sysctl_vmstate = {
 
 static Property iotkit_sysctl_props[] = {
     DEFINE_PROP_UINT32("SYS_VERSION", IoTKitSysCtl, sys_version, 0),
+    DEFINE_PROP_UINT32("CPUWAIT_RST", IoTKitSysCtl, cpuwait_rst, 0),
+    DEFINE_PROP_UINT32("INITSVTOR0_RST", IoTKitSysCtl, initsvtor0_rst,
+                       0x10000000),
+    DEFINE_PROP_UINT32("INITSVTOR1_RST", IoTKitSysCtl, initsvtor1_rst,
+                       0x10000000),
     DEFINE_PROP_END_OF_LIST()
 };
 
-- 
2.20.1

Instead of gating the A32/T32 FP16 conversion instructions on
the ARM_FEATURE_VFP_FP16 flag, switch to our new approach of
looking at ID register bits. In this case MVFR1 fields FPHP
and SIMDHP indicate the presence of these insns.

This change doesn't alter behaviour for any of our CPUs.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190222170936.13268-2-peter.maydell@linaro.org
---
 target/arm/cpu.h       | 37 ++++++++++++++++++++++++++++++++++++-
 target/arm/cpu.c       |  2 --
 target/arm/kvm32.c     |  3 ---
 target/arm/translate.c | 26 ++++++++++++++++++--------
 4 files changed, 54 insertions(+), 14 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ FIELD(ID_DFR0, MPROFDBG, 20, 4)
 FIELD(ID_DFR0, PERFMON, 24, 4)
 FIELD(ID_DFR0, TRACEFILT, 28, 4)
 
+FIELD(MVFR0, SIMDREG, 0, 4)
+FIELD(MVFR0, FPSP, 4, 4)
+FIELD(MVFR0, FPDP, 8, 4)
+FIELD(MVFR0, FPTRAP, 12, 4)
+FIELD(MVFR0, FPDIVIDE, 16, 4)
+FIELD(MVFR0, FPSQRT, 20, 4)
+FIELD(MVFR0, FPSHVEC, 24, 4)
+FIELD(MVFR0, FPROUND, 28, 4)
+
+FIELD(MVFR1, FPFTZ, 0, 4)
+FIELD(MVFR1, FPDNAN, 4, 4)
+FIELD(MVFR1, SIMDLS, 8, 4)
+FIELD(MVFR1, SIMDINT, 12, 4)
+FIELD(MVFR1, SIMDSP, 16, 4)
+FIELD(MVFR1, SIMDHP, 20, 4)
+FIELD(MVFR1, FPHP, 24, 4)
+FIELD(MVFR1, SIMDFMAC, 28, 4)
+
+FIELD(MVFR2, SIMDMISC, 0, 4)
+FIELD(MVFR2, FPMISC, 4, 4)
+
 QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
 
 /* If adding a feature bit which corresponds to a Linux ELF
@@ -XXX,XX +XXX,XX @@ enum arm_features {
     ARM_FEATURE_THUMB2,
     ARM_FEATURE_PMSA,   /* no MMU; may have Memory Protection Unit */
     ARM_FEATURE_VFP3,
-    ARM_FEATURE_VFP_FP16,
     ARM_FEATURE_NEON,
     ARM_FEATURE_M, /* Microcontroller profile.  */
     ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling.  */
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) == 1;
 }
 
+/*
+ * We always set the FP and SIMD FP16 fields to indicate identical
+ * levels of support (assuming SIMD is implemented at all), so
+ * we only need one set of accessors.
+ */
+static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 0;
+}
+
+static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1;
+}
+
 /*
  * 64-bit feature tests via id registers.
  */
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
     }
     if (arm_feature(env, ARM_FEATURE_VFP4)) {
         set_feature(env, ARM_FEATURE_VFP3);
-        set_feature(env, ARM_FEATURE_VFP_FP16);
     }
     if (arm_feature(env, ARM_FEATURE_VFP3)) {
         set_feature(env, ARM_FEATURE_VFP);
@@ -XXX,XX +XXX,XX @@ static void cortex_a9_initfn(Object *obj)
     cpu->dtb_compatible = "arm,cortex-a9";
     set_feature(&cpu->env, ARM_FEATURE_V7);
     set_feature(&cpu->env, ARM_FEATURE_VFP3);
-    set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
     set_feature(&cpu->env, ARM_FEATURE_NEON);
     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
     set_feature(&cpu->env, ARM_FEATURE_EL3);
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
     if (extract32(id_pfr0, 12, 4) == 1) {
         set_feature(&features, ARM_FEATURE_THUMB2EE);
     }
-    if (extract32(ahcf->isar.mvfr1, 20, 4) == 1) {
-        set_feature(&features, ARM_FEATURE_VFP_FP16);
-    }
     if (extract32(ahcf->isar.mvfr1, 12, 4) == 1) {
         set_feature(&features, ARM_FEATURE_NEON);
     }
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn)
                      * UNPREDICTABLE if bit 8 is set prior to ARMv8
                      * (we choose to UNDEF)
                      */
-                    if ((dp && !arm_dc_feature(s, ARM_FEATURE_V8)) ||
-                        !arm_dc_feature(s, ARM_FEATURE_VFP_FP16)) {
-                        return 1;
+                    if (dp) {
+                        if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
+                            return 1;
+                        }
+                    } else {
+                        if (!dc_isar_feature(aa32_fp16_spconv, s)) {
+                            return 1;
+                        }
                     }
                     rm_is_dp = false;
                     break;
                 case 0x06: /* vcvtb.f16.f32, vcvtb.f16.f64 */
                 case 0x07: /* vcvtt.f16.f32, vcvtt.f16.f64 */
-                    if ((dp && !arm_dc_feature(s, ARM_FEATURE_V8)) ||
-                        !arm_dc_feature(s, ARM_FEATURE_VFP_FP16)) {
-                        return 1;
+                    if (dp) {
+                        if (!dc_isar_feature(aa32_fp16_dpconv, s)) {
+                            return 1;
+                        }
+                    } else {
+                        if (!dc_isar_feature(aa32_fp16_spconv, s)) {
+                            return 1;
+                        }
                     }
                     rd_is_dp = false;
                     break;
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                     TCGv_ptr fpst;
                     TCGv_i32 ahp;
 
-                    if (!arm_dc_feature(s, ARM_FEATURE_VFP_FP16) ||
+                    if (!dc_isar_feature(aa32_fp16_spconv, s) ||
                         q || (rm & 1)) {
                         return 1;
                     }
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
                 {
                     TCGv_ptr fpst;
                     TCGv_i32 ahp;
-                    if (!arm_dc_feature(s, ARM_FEATURE_VFP_FP16) ||
+                    if (!dc_isar_feature(aa32_fp16_spconv, s) ||
                         q || (rd & 1)) {
                         return 1;
                     }
-- 
2.20.1

There is a set of VFP instructions which we implement in
disas_vfp_v8_insn() and gate on the ARM_FEATURE_V8 bit.
These were all first introduced in v8 for A-profile, but in
M-profile they appeared in v7M. Gate them on the MVFR2
FPMisc field instead, and rename the function appropriately.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190222170936.13268-3-peter.maydell@linaro.org
---
 target/arm/cpu.h       | 20 ++++++++++++++++++++
 target/arm/translate.c | 25 +++++++++++++------------
 2 files changed, 33 insertions(+), 12 deletions(-)

This reverts commit 823e1b3818f9b10b824ddcd756983b6e2fa68730,
which introduces a regression running EDK2 guest firmware
under KVM:

error: kvm run failed Function not implemented
 PC=000000013f5a6208 X00=00000000404003c4 X01=000000000000003a
X02=0000000000000000 X03=00000000404003c4 X04=0000000000000000
X05=0000000096000046 X06=000000013d2ef270 X07=000000013e3d1710
X08=09010755ffaf8ba8 X09=ffaf8b9cfeeb5468 X10=feeb546409010756
X11=09010757ffaf8b90 X12=feeb50680903068b X13=090306a1ffaf8bc0
X14=0000000000000000 X15=0000000000000000 X16=000000013f872da0
X17=00000000ffffa6ab X18=0000000000000000 X19=000000013f5a92d0
X20=000000013f5a7a78 X21=000000000000003a X22=000000013f5a7ab2
X23=000000013f5a92e8 X24=000000013f631090 X25=0000000000000010
X26=0000000000000100 X27=000000013f89501b X28=000000013e3d14e0
X29=000000013e3d12a0 X30=000000013f5a2518  SP=000000013b7be0b0
PSTATE=404003c4 -Z-- EL1t

with
[ 3507.926571] kvm [35042]: load/store instruction decoding not implemented
in the host dmesg.

Revert the change for the moment until we can investigate the
cause of the regression.

Reported-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h     |  9 +--------
 target/arm/helper.c  | 27 ++-------------------------
 target/arm/kvm32.c   | 20 ++++++++++++++++++--
 target/arm/kvm64.c   |  2 --
 target/arm/machine.c |  2 +-
 5 files changed, 22 insertions(+), 38 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ bool write_list_to_cpustate(ARMCPU *cpu);
 /**
  * write_cpustate_to_list:
  * @cpu: ARMCPU
- * @kvm_sync: true if this is for syncing back to KVM
  *
  * For each register listed in the ARMCPU cpreg_indexes list, write
  * its value from the ARMCPUState structure into the cpreg_values list.
  * This is used to copy info from TCG's working data structures into
  * KVM or for outbound migration.
  *
- * @kvm_sync is true if we are doing this in order to sync the
- * register state back to KVM. In this case we will only update
- * values in the list if the previous list->cpustate sync actually
- * successfully wrote the CPU state. Otherwise we will keep the value
- * that is in the list.
- *
  * Returns: true if all register values were read correctly,
  * false if some register was unknown or could not be read.
  * Note that we do not stop early on failure -- we will attempt
  * reading all registers in the list.
  */
-bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync);
+bool write_cpustate_to_list(ARMCPU *cpu);
 
 #define ARM_CPUID_TI915T      0x54029152
 #define ARM_CPUID_TI925T      0x54029252
diff --git a/target/arm/helper.c b/target/arm/helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -XXX,XX +XXX,XX @@ static bool raw_accessors_invalid(const ARMCPRegInfo *ri)
     return true;
 }
 
-bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync)
+bool write_cpustate_to_list(ARMCPU *cpu)
 {
     /* Write the coprocessor state from cpu->env to the (index,value) list. */
     int i;
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync)
     for (i = 0; i < cpu->cpreg_array_len; i++) {
         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
         const ARMCPRegInfo *ri;
-        uint64_t newval;
 
         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
         if (!ri) {
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync)
         if (ri->type & ARM_CP_NO_RAW) {
             continue;
         }
-
-        newval = read_raw_cp_reg(&cpu->env, ri);
-        if (kvm_sync) {
-            /*
-             * Only sync if the previous list->cpustate sync succeeded.
-             * Rather than tracking the success/failure state for every
-             * item in the list, we just recheck "does the raw write we must
-             * have made in write_list_to_cpustate() read back OK" here.
-             */
-            uint64_t oldval = cpu->cpreg_values[i];
-
-            if (oldval == newval) {
-                continue;
-            }
-
-            write_raw_cp_reg(&cpu->env, ri, oldval);
-            if (read_raw_cp_reg(&cpu->env, ri) != oldval) {
-                continue;
-            }
-
-            write_raw_cp_reg(&cpu->env, ri, newval);
-        }
-        cpu->cpreg_values[i] = newval;
+        cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
     }
     return ok;
 }
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
         return ret;
     }
 
-    write_cpustate_to_list(cpu, true);
-
+    /* Note that we do not call write_cpustate_to_list()
+     * here, so we are only writing the tuple list back to
+     * KVM. This is safe because nothing can change the
+     * CPUARMState cp15 fields (in particular gdb accesses cannot)
+     * and so there are no changes to sync. In fact syncing would
+     * be wrong at this point: for a constant register where TCG and
+     * KVM disagree about its value, the preceding write_list_to_cpustate()
+     * would not have had any effect on the CPUARMState value (since the
+     * register is read-only), and a write_cpustate_to_list() here would
+     * then try to write the TCG value back into KVM -- this would either
+     * fail or incorrectly change the value the guest sees.
+     *
+     * If we ever want to allow the user to modify cp15 registers via
+     * the gdb stub, we would need to be more clever here (for instance
+     * tracking the set of registers kvm_arch_get_registers() successfully
+     * managed to update the CPUARMState with, and only allowing those
+     * to be written back up into the kernel).
+     */
     if (!write_list_to_kvmstate(cpu, level)) {
         return EINVAL;
     }
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
         return ret;
     }
 
-    write_cpustate_to_list(cpu, true);
-
     if (!write_list_to_kvmstate(cpu, level)) {
         return EINVAL;
     }
diff --git a/target/arm/machine.c b/target/arm/machine.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/machine.c
+++ b/target/arm/machine.c
@@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque)
             abort();
         }
     } else {
-        if (!write_cpustate_to_list(cpu, false)) {
+        if (!write_cpustate_to_list(cpu)) {
             /* This should never fail. */
             abort();
         }
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

Note that float16_to_float32 rightly squashes SNaN to QNaN.
But of course pickNaNMulAdd, for ARM, selects SNaNs first.
So we have to preserve SNaN long enough for the correct NaN
to be selected.  Thus float16_to_float32_by_bits.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190219222952.22183-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/helper.h     |   9 +++
 target/arm/vec_helper.c | 148 ++++++++++++++++++++++++++++++++++++++++
 2 files changed, 157 insertions(+)

diff --git a/target/arm/helper.h b/target/arm/helper.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_5(gvec_sqsub_s, TCG_CALL_NO_RWG,
 DEF_HELPER_FLAGS_5(gvec_sqsub_d, TCG_CALL_NO_RWG,
                    void, ptr, ptr, ptr, ptr, i32)
 
+DEF_HELPER_FLAGS_5(gvec_fmlal_a32, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_fmlal_a64, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a32, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_5(gvec_fmlal_idx_a64, TCG_CALL_NO_RWG,
+                   void, ptr, ptr, ptr, ptr, i32)
+
 #ifdef TARGET_AARCH64
 #include "helper-a64.h"
 #include "helper-sve.h"
diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/vec_helper.c
+++ b/target/arm/vec_helper.c
@@ -XXX,XX +XXX,XX @@ void HELPER(gvec_sqsub_d)(void *vd, void *vq, void *vn,
     }
     clear_tail(d, oprsz, simd_maxsz(desc));
 }
+
+/*
+ * Convert float16 to float32, raising no exceptions and
+ * preserving exceptional values, including SNaN.
+ * This is effectively an unpack+repack operation.
+ */
+static float32 float16_to_float32_by_bits(uint32_t f16, bool fz16)
+{
+    const int f16_bias = 15;
+    const int f32_bias = 127;
+    uint32_t sign = extract32(f16, 15, 1);
+    uint32_t exp = extract32(f16, 10, 5);
+    uint32_t frac = extract32(f16, 0, 10);
+
+    if (exp == 0x1f) {
+        /* Inf or NaN */
+        exp = 0xff;
+    } else if (exp == 0) {
+        /* Zero or denormal.  */
+        if (frac != 0) {
+            if (fz16) {
+                frac = 0;
+            } else {
+                /*
+                 * Denormal; these are all normal float32.
+                 * Shift the fraction so that the msb is at bit 11,
+                 * then remove bit 11 as the implicit bit of the
+                 * normalized float32.  Note that we still go through
+                 * the shift for normal numbers below, to put the
+                 * float32 fraction at the right place.
+                 */
+                int shift = clz32(frac) - 21;
+                frac = (frac << shift) & 0x3ff;
+                exp = f32_bias - f16_bias - shift + 1;
+            }
+        }
+    } else {
+        /* Normal number; adjust the bias.  */
+        exp += f32_bias - f16_bias;
+    }
+    sign <<= 31;
+    exp <<= 23;
+    frac <<= 23 - 10;
+
+    return sign | exp | frac;
+}
+
+static uint64_t load4_f16(uint64_t *ptr, int is_q, int is_2)
+{
+    /*
+     * Branchless load of u32[0], u64[0], u32[1], or u64[1].
+     * Load the 2nd qword iff is_q & is_2.
+     * Shift to the 2nd dword iff !is_q & is_2.
+     * For !is_q & !is_2, the upper bits of the result are garbage.
+     */
+    return ptr[is_q & is_2] >> ((is_2 & ~is_q) << 5);
+}
+
+/*
+ * Note that FMLAL requires oprsz == 8 or oprsz == 16,
+ * as there is not yet SVE versions that might use blocking.
+ */
+
+static void do_fmlal(float32 *d, void *vn, void *vm, float_status *fpst,
+                     uint32_t desc, bool fz16)
+{
+    intptr_t i, oprsz = simd_oprsz(desc);
+    int is_s = extract32(desc, SIMD_DATA_SHIFT, 1);
+    int is_2 = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
+    int is_q = oprsz == 16;
+    uint64_t n_4, m_4;
+
+    /* Pre-load all of the f16 data, avoiding overlap issues.  */
+    n_4 = load4_f16(vn, is_q, is_2);
+    m_4 = load4_f16(vm, is_q, is_2);
+
+    /* Negate all inputs for FMLSL at once.  */
+    if (is_s) {
+        n_4 ^= 0x8000800080008000ull;
+    }
+
+    for (i = 0; i < oprsz / 4; i++) {
+        float32 n_1 = float16_to_float32_by_bits(n_4 >> (i * 16), fz16);
+        float32 m_1 = float16_to_float32_by_bits(m_4 >> (i * 16), fz16);
+        d[H4(i)] = float32_muladd(n_1, m_1, d[H4(i)], 0, fpst);
+    }
+    clear_tail(d, oprsz, simd_maxsz(desc));
+}
+
+void HELPER(gvec_fmlal_a32)(void *vd, void *vn, void *vm,
+                            void *venv, uint32_t desc)
+{
+    CPUARMState *env = venv;
+    do_fmlal(vd, vn, vm, &env->vfp.standard_fp_status, desc,
+             get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
+}
+
+void HELPER(gvec_fmlal_a64)(void *vd, void *vn, void *vm,
+                            void *venv, uint32_t desc)
+{
+    CPUARMState *env = venv;
+    do_fmlal(vd, vn, vm, &env->vfp.fp_status, desc,
+             get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
+}
+
+static void do_fmlal_idx(float32 *d, void *vn, void *vm, float_status *fpst,
+                         uint32_t desc, bool fz16)
+{
+    intptr_t i, oprsz = simd_oprsz(desc);
+    int is_s = extract32(desc, SIMD_DATA_SHIFT, 1);
+    int is_2 = extract32(desc, SIMD_DATA_SHIFT + 1, 1);
+    int index = extract32(desc, SIMD_DATA_SHIFT + 2, 3);
+    int is_q = oprsz == 16;
+    uint64_t n_4;
+    float32 m_1;
+
+    /* Pre-load all of the f16 data, avoiding overlap issues.  */
+    n_4 = load4_f16(vn, is_q, is_2);
+
+    /* Negate all inputs for FMLSL at once.  */
+    if (is_s) {
+        n_4 ^= 0x8000800080008000ull;
+    }
+
+    m_1 = float16_to_float32_by_bits(((float16 *)vm)[H2(index)], fz16);
+
+    for (i = 0; i < oprsz / 4; i++) {
+        float32 n_1 = float16_to_float32_by_bits(n_4 >> (i * 16), fz16);
+        d[H4(i)] = float32_muladd(n_1, m_1, d[H4(i)], 0, fpst);
+    }
+    clear_tail(d, oprsz, simd_maxsz(desc));
+}
+
+void HELPER(gvec_fmlal_idx_a32)(void *vd, void *vn, void *vm,
+                                void *venv, uint32_t desc)
+{
+    CPUARMState *env = venv;
+    do_fmlal_idx(vd, vn, vm, &env->vfp.standard_fp_status, desc,
+                 get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
+}
+
+void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, void *vm,
+                                void *venv, uint32_t desc)
+{
+    CPUARMState *env = venv;
+    do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status, desc,
+                 get_flush_inputs_to_zero(&env->vfp.fp_status_f16));
+}
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190219222952.22183-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h           |  5 ++++
 target/arm/translate-a64.c | 49 +++++++++++++++++++++++++++++++++++++-
 2 files changed, 53 insertions(+), 1 deletion(-)

From: Richard Henderson <richard.henderson@linaro.org>

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190219222952.22183-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.h       |   5 ++
 target/arm/translate.c | 129 ++++++++++++++++++++++++++++++-----------
 2 files changed, 101 insertions(+), 33 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa32_dp(const ARMISARegisters *id)
     return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0;
 }
 
+static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id)
+{
+    return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0;
+}
+
 static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id)
 {
     /*
diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
     gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL;
     int rd, rn, rm, opr_sz;
     int data = 0;
-    bool q;
-
-    q = extract32(insn, 6, 1);
-    VFP_DREG_D(rd, insn);
-    VFP_DREG_N(rn, insn);
-    VFP_DREG_M(rm, insn);
-    if ((rd | rn | rm) & q) {
-        return 1;
-    }
+    int off_rn, off_rm;
+    bool is_long = false, q = extract32(insn, 6, 1);
+    bool ptr_is_env = false;
 
     if ((insn & 0xfe200f10) == 0xfc200800) {
         /* VCMLA -- 1111 110R R.1S .... .... 1000 ...0 .... */
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
             return 1;
         }
         fn_gvec = u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b;
+    } else if ((insn & 0xff300f10) == 0xfc200810) {
+        /* VFM[AS]L -- 1111 1100 S.10 .... .... 1000 .Q.1 .... */
+        int is_s = extract32(insn, 23, 1);
+        if (!dc_isar_feature(aa32_fhm, s)) {
+            return 1;
+        }
+        is_long = true;
+        data = is_s; /* is_2 == 0 */
+        fn_gvec_ptr = gen_helper_gvec_fmlal_a32;
+        ptr_is_env = true;
     } else {
         return 1;
     }
 
+    VFP_DREG_D(rd, insn);
+    if (rd & q) {
+        return 1;
+    }
+    if (q || !is_long) {
+        VFP_DREG_N(rn, insn);
+        VFP_DREG_M(rm, insn);
+        if ((rn | rm) & q & !is_long) {
+            return 1;
+        }
+        off_rn = vfp_reg_offset(1, rn);
+        off_rm = vfp_reg_offset(1, rm);
+    } else {
+        rn = VFP_SREG_N(insn);
+        rm = VFP_SREG_M(insn);
+        off_rn = vfp_reg_offset(0, rn);
+        off_rm = vfp_reg_offset(0, rm);
+    }
+
     if (s->fp_excp_el) {
         gen_exception_insn(s, 4, EXCP_UDEF,
                            syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
 
     opr_sz = (1 + q) * 8;
     if (fn_gvec_ptr) {
-        TCGv_ptr fpst = get_fpstatus_ptr(1);
-        tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd),
-                           vfp_reg_offset(1, rn),
-                           vfp_reg_offset(1, rm), fpst,
+        TCGv_ptr ptr;
+        if (ptr_is_env) {
+            ptr = cpu_env;
+        } else {
+            ptr = get_fpstatus_ptr(1);
+        }
+        tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr,
                            opr_sz, opr_sz, data, fn_gvec_ptr);
-        tcg_temp_free_ptr(fpst);
+        if (!ptr_is_env) {
+            tcg_temp_free_ptr(ptr);
+        }
     } else {
-        tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd),
-                           vfp_reg_offset(1, rn),
-                           vfp_reg_offset(1, rm),
+        tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm,
                            opr_sz, opr_sz, data, fn_gvec);
     }
     return 0;
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
     gen_helper_gvec_3 *fn_gvec = NULL;
     gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL;
     int rd, rn, rm, opr_sz, data;
-    bool q;
-
-    q = extract32(insn, 6, 1);
-    VFP_DREG_D(rd, insn);
-    VFP_DREG_N(rn, insn);
-    if ((rd | rn) & q) {
-        return 1;
-    }
+    int off_rn, off_rm;
+    bool is_long = false, q = extract32(insn, 6, 1);
+    bool ptr_is_env = false;
 
     if ((insn & 0xff000f10) == 0xfe000800) {
         /* VCMLA (indexed) -- 1111 1110 S.RR .... .... 1000 ...0 .... */
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
     } else if ((insn & 0xffb00f00) == 0xfe200d00) {
         /* V[US]DOT -- 1111 1110 0.10 .... .... 1101 .Q.U .... */
         int u = extract32(insn, 4, 1);
+
         if (!dc_isar_feature(aa32_dp, s)) {
             return 1;
         }
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
         /* rm is just Vm, and index is M.  */
         data = extract32(insn, 5, 1); /* index */
         rm = extract32(insn, 0, 4);
+    } else if ((insn & 0xffa00f10) == 0xfe000810) {
+        /* VFM[AS]L -- 1111 1110 0.0S .... .... 1000 .Q.1 .... */
+        int is_s = extract32(insn, 20, 1);
+        int vm20 = extract32(insn, 0, 3);
+        int vm3 = extract32(insn, 3, 1);
+        int m = extract32(insn, 5, 1);
+        int index;
+
+        if (!dc_isar_feature(aa32_fhm, s)) {
+            return 1;
+        }
+        if (q) {
+            rm = vm20;
+            index = m * 2 + vm3;
+        } else {
+            rm = vm20 * 2 + m;
+            index = vm3;
+        }
+        is_long = true;
+        data = (index << 2) | is_s; /* is_2 == 0 */
+        fn_gvec_ptr = gen_helper_gvec_fmlal_idx_a32;
+        ptr_is_env = true;
     } else {
         return 1;
     }
 
+    VFP_DREG_D(rd, insn);
+    if (rd & q) {
+        return 1;
+    }
+    if (q || !is_long) {
+        VFP_DREG_N(rn, insn);
+        if (rn & q & !is_long) {
+            return 1;
+        }
+        off_rn = vfp_reg_offset(1, rn);
+        off_rm = vfp_reg_offset(1, rm);
+    } else {
+        rn = VFP_SREG_N(insn);
+        off_rn = vfp_reg_offset(0, rn);
+        off_rm = vfp_reg_offset(0, rm);
+    }
     if (s->fp_excp_el) {
         gen_exception_insn(s, 4, EXCP_UDEF,
                            syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
 
     opr_sz = (1 + q) * 8;
     if (fn_gvec_ptr) {
-        TCGv_ptr fpst = get_fpstatus_ptr(1);
-        tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd),
-                           vfp_reg_offset(1, rn),
-                           vfp_reg_offset(1, rm), fpst,
+        TCGv_ptr ptr;
+        if (ptr_is_env) {
+            ptr = cpu_env;
+        } else {
+            ptr = get_fpstatus_ptr(1);
+        }
+        tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr,
                            opr_sz, opr_sz, data, fn_gvec_ptr);
-        tcg_temp_free_ptr(fpst);
+        if (!ptr_is_env) {
+            tcg_temp_free_ptr(ptr);
+        }
     } else {
-        tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd),
-                           vfp_reg_offset(1, rn),
-                           vfp_reg_offset(1, rm),
+        tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm,
                            opr_sz, opr_sz, data, fn_gvec);
     }
     return 0;
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190219222952.22183-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/cpu.c   | 1 +
 target/arm/cpu64.c | 2 ++
 2 files changed, 3 insertions(+)

diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
             t = cpu->isar.id_isar6;
             t = FIELD_DP32(t, ID_ISAR6, JSCVT, 1);
             t = FIELD_DP32(t, ID_ISAR6, DP, 1);
+            t = FIELD_DP32(t, ID_ISAR6, FHM, 1);
             cpu->isar.id_isar6 = t;
 
             t = cpu->id_mmfr4;
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
         t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1);
         t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
         t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
+        t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
         cpu->isar.id_aa64isar0 = t;
 
         t = cpu->isar.id_aa64isar1;
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
         u = cpu->isar.id_isar6;
         u = FIELD_DP32(u, ID_ISAR6, JSCVT, 1);
         u = FIELD_DP32(u, ID_ISAR6, DP, 1);
+        u = FIELD_DP32(u, ID_ISAR6, FHM, 1);
         cpu->isar.id_isar6 = u;
 
         /*
-- 
2.20.1

Not very much here, but several people have fallen over
the vector operation segfault bug, so let's get the fix
into master.

thanks
-- PMM

The following changes since commit d418238dca7b4e0b124135827ead3076233052b1:

Merge remote-tracking branch 'remotes/rth/tags/pull-rng-20190522' into staging (2019-05-23 12:57:17 +0100)

are available in the Git repository at:

https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190523

for you to fetch changes up to 98e4f4fdb8ea05d840f51f47125924c2bb9df2df:

hw/arm/exynos4210: QOM'ify the Exynos4210 SoC (2019-05-23 14:47:44 +0100)

----------------------------------------------------------------
target-arm queue:
 * exynos4210: QOM'ify the Exynos4210 SoC
 * exynos4210: Add DMA support for the Exynos4210
 * arm_gicv3: Fix writes to ICC_CTLR_EL3
 * arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
 * target/arm: Fix vector operation segfault
 * target/arm: Minor improvements to BFXIL, EXTR

----------------------------------------------------------------
Alistair Francis (1):
      target/arm: Fix vector operation segfault

Guenter Roeck (1):
      hw/arm/exynos4210: Add DMA support for the Exynos4210

Peter Maydell (5):
      arm: Move system_clock_scale to armv7m_systick.h
      arm: Remove unnecessary includes of hw/arm/arm.h
      arm: Rename hw/arm/arm.h to hw/arm/boot.h
      hw/intc/arm_gicv3: Fix write of ICH_VMCR_EL2.{VBPR0, VBPR1}
      hw/intc/arm_gicv3: Fix writes to ICC_CTLR_EL3

Philippe Mathieu-Daudé (3):
      hw/arm/exynos4: Remove unuseful debug code
      hw/arm/exynos4: Use the IEC binary prefix definitions
      hw/arm/exynos4210: QOM'ify the Exynos4210 SoC

Richard Henderson (2):
      target/arm: Use extract2 for EXTR
      target/arm: Simplify BFXIL expansion

include/hw/arm/allwinner-a10.h    |  2 +-
 include/hw/arm/aspeed_soc.h       |  1 -
 include/hw/arm/bcm2836.h          |  1 -
 include/hw/arm/{arm.h => boot.h}  | 12 +++------
 include/hw/arm/exynos4210.h       |  9 +++++--
 include/hw/arm/fsl-imx25.h        |  2 +-
 include/hw/arm/fsl-imx31.h        |  2 +-
 include/hw/arm/fsl-imx6.h         |  2 +-
 include/hw/arm/fsl-imx6ul.h       |  2 +-
 include/hw/arm/fsl-imx7.h         |  2 +-
 include/hw/arm/virt.h             |  2 +-
 include/hw/arm/xlnx-versal.h      |  2 +-
 include/hw/arm/xlnx-zynqmp.h      |  2 +-
 include/hw/timer/armv7m_systick.h | 22 ++++++++++++++++
 hw/arm/armsse.c                   |  2 +-
 hw/arm/armv7m.c                   |  2 +-
 hw/arm/aspeed.c                   |  2 +-
 hw/arm/boot.c                     |  2 +-
 hw/arm/collie.c                   |  2 +-
 hw/arm/exynos4210.c               | 54 ++++++++++++++++++++++++++++++++++++---
 hw/arm/exynos4_boards.c           | 40 ++++++++---------------------
 hw/arm/highbank.c                 |  2 +-
 hw/arm/integratorcp.c             |  2 +-
 hw/arm/mainstone.c                |  2 +-
 hw/arm/microbit.c                 |  2 +-
 hw/arm/mps2-tz.c                  |  2 +-
 hw/arm/mps2.c                     |  2 +-
 hw/arm/msf2-soc.c                 |  1 -
 hw/arm/msf2-som.c                 |  2 +-
 hw/arm/musca.c                    |  2 +-
 hw/arm/musicpal.c                 |  2 +-
 hw/arm/netduino2.c                |  2 +-
 hw/arm/nrf51_soc.c                |  2 +-
 hw/arm/nseries.c                  |  2 +-
 hw/arm/omap1.c                    |  2 +-
 hw/arm/omap2.c                    |  2 +-
 hw/arm/omap_sx1.c                 |  2 +-
 hw/arm/palm.c                     |  2 +-
 hw/arm/raspi.c                    |  2 +-
 hw/arm/realview.c                 |  2 +-
 hw/arm/spitz.c                    |  2 +-
 hw/arm/stellaris.c                |  2 +-
 hw/arm/stm32f205_soc.c            |  2 +-
 hw/arm/strongarm.c                |  2 +-
 hw/arm/tosa.c                     |  2 +-
 hw/arm/versatilepb.c              |  2 +-
 hw/arm/vexpress.c                 |  2 +-
 hw/arm/virt.c                     |  2 +-
 hw/arm/xilinx_zynq.c              |  2 +-
 hw/arm/xlnx-versal.c              |  2 +-
 hw/arm/z2.c                       |  2 +-
 hw/intc/arm_gicv3_cpuif.c         |  6 ++---
 hw/intc/armv7m_nvic.c             |  1 -
 target/arm/arm-semi.c             |  1 -
 target/arm/cpu.c                  |  1 -
 target/arm/cpu64.c                |  1 -
 target/arm/kvm.c                  |  1 -
 target/arm/kvm32.c                |  1 -
 target/arm/kvm64.c                |  1 -
 target/arm/translate-a64.c        | 44 ++++++++++++++++---------------
 target/arm/translate.c            |  4 +--
 61 files changed, 164 insertions(+), 123 deletions(-)
 rename include/hw/arm/{arm.h => boot.h} (96%)

From: Richard Henderson <richard.henderson@linaro.org>

This is, after all, how we implement extract2 in tcg/aarch64.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190514011129.11330-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 38 ++++++++++++++++++++------------------
 1 file changed, 20 insertions(+), 18 deletions(-)

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -XXX,XX +XXX,XX @@ static void disas_extract(DisasContext *s, uint32_t insn)
             } else {
                 tcg_gen_ext32u_i64(tcg_rd, cpu_reg(s, rm));
             }
-        } else if (rm == rn) { /* ROR */
-            tcg_rm = cpu_reg(s, rm);
-            if (sf) {
-                tcg_gen_rotri_i64(tcg_rd, tcg_rm, imm);
-            } else {
-                TCGv_i32 tmp = tcg_temp_new_i32();
-                tcg_gen_extrl_i64_i32(tmp, tcg_rm);
-                tcg_gen_rotri_i32(tmp, tmp, imm);
-                tcg_gen_extu_i32_i64(tcg_rd, tmp);
-                tcg_temp_free_i32(tmp);
-            }
         } else {
-            tcg_rm = read_cpu_reg(s, rm, sf);
-            tcg_rn = read_cpu_reg(s, rn, sf);
-            tcg_gen_shri_i64(tcg_rm, tcg_rm, imm);
-            tcg_gen_shli_i64(tcg_rn, tcg_rn, bitsize - imm);
-            tcg_gen_or_i64(tcg_rd, tcg_rm, tcg_rn);
-            if (!sf) {
-                tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
+            tcg_rm = cpu_reg(s, rm);
+            tcg_rn = cpu_reg(s, rn);
+
+            if (sf) {
+                /* Specialization to ROR happens in EXTRACT2.  */
+                tcg_gen_extract2_i64(tcg_rd, tcg_rm, tcg_rn, imm);
+            } else {
+                TCGv_i32 t0 = tcg_temp_new_i32();
+
+                tcg_gen_extrl_i64_i32(t0, tcg_rm);
+                if (rm == rn) {
+                    tcg_gen_rotri_i32(t0, t0, imm);
+                } else {
+                    TCGv_i32 t1 = tcg_temp_new_i32();
+                    tcg_gen_extrl_i64_i32(t1, tcg_rn);
+                    tcg_gen_extract2_i32(t0, t0, t1, imm);
+                    tcg_temp_free_i32(t1);
+                }
+                tcg_gen_extu_i32_i64(tcg_rd, t0);
+                tcg_temp_free_i32(t0);
             }
         }
     }
-- 
2.20.1

From: Richard Henderson <richard.henderson@linaro.org>

The mask implied by the extract is redundant with the one
implied by the deposit.  Also, fix spelling of BFXIL.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20190514011129.11330-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate-a64.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

From: Alistair Francis <alistair.francis@wdc.com>

Commit 89e68b575 "target/arm: Use vector operations for saturation"
causes this abort() when booting QEMU ARM with a Cortex-A15:

0  0x00007ffff4c2382f in raise () at /usr/lib/libc.so.6
1  0x00007ffff4c0e672 in abort () at /usr/lib/libc.so.6
2  0x00005555559c1839 in disas_neon_data_insn (insn=<optimized out>, s=<optimized out>) at ./target/arm/translate.c:6673
3  0x00005555559c1839 in disas_neon_data_insn (s=<optimized out>, insn=<optimized out>) at ./target/arm/translate.c:6386
4  0x00005555559cd8a4 in disas_arm_insn (insn=4081107068, s=0x7fffe59a9510) at ./target/arm/translate.c:9289
5  0x00005555559cd8a4 in arm_tr_translate_insn (dcbase=0x7fffe59a9510, cpu=<optimized out>) at ./target/arm/translate.c:13612
6  0x00005555558d1d39 in translator_loop (ops=0x5555561cc580 <arm_translator_ops>, db=0x7fffe59a9510, cpu=0x55555686a2f0, tb=<optimized out>, max_insns=<optimized out>) at ./accel/tcg/translator.c:96
7  0x00005555559d10d4 in gen_intermediate_code (cpu=cpu@entry=0x55555686a2f0, tb=tb@entry=0x7fffd7840080 <code_gen_buffer+126091347>, max_insns=max_insns@entry=512) at ./target/arm/translate.c:13901
8  0x00005555558d06b9 in tb_gen_code (cpu=cpu@entry=0x55555686a2f0, pc=3067096216, cs_base=0, flags=192, cflags=-16252928, cflags@entry=524288) at ./accel/tcg/translate-all.c:1736
9  0x00005555558ce467 in tb_find (cf_mask=524288, tb_exit=1, last_tb=0x7fffd783e640 <code_gen_buffer+126084627>, cpu=0x1) at ./accel/tcg/cpu-exec.c:407
10 0x00005555558ce467 in cpu_exec (cpu=cpu@entry=0x55555686a2f0) at ./accel/tcg/cpu-exec.c:728
11 0x000055555588b0cf in tcg_cpu_exec (cpu=0x55555686a2f0) at ./cpus.c:1431
12 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=0x55555686a2f0) at ./cpus.c:1735
13 0x000055555588d223 in qemu_tcg_cpu_thread_fn (arg=arg@entry=0x55555686a2f0) at ./cpus.c:1709
14 0x0000555555d2629a in qemu_thread_start (args=<optimized out>) at ./util/qemu-thread-posix.c:502
15 0x00007ffff4db8a92 in start_thread () at /usr/lib/libpthread.

This patch ensures that we don't hit the abort() in the second switch
case in disas_neon_data_insn() as we will return from the first case.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: ad91b397f360b2fc7f4087e476f7df5b04d42ddb.1558021877.git.alistair.francis@wdc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/translate.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/arm/translate.c b/target/arm/translate.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
             tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
                            rn_ofs, rm_ofs, vec_size, vec_size,
                            (u ? uqadd_op : sqadd_op) + size);
-            break;
+            return 0;
 
         case NEON_3R_VQSUB:
             tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc),
                            rn_ofs, rm_ofs, vec_size, vec_size,
                            (u ? uqsub_op : sqsub_op) + size);
-            break;
+            return 0;
 
         case NEON_3R_VMUL: /* VMUL */
             if (u) {
-- 
2.20.1

The system_clock_scale global is used only by the armv7m systick
device; move the extern declaration to the armv7m_systick.h header,
and expand the comment to explain what it is and that it should
ideally be replaced with a different approach.

diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/arm.h
+++ b/include/hw/arm/arm.h
@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
                                             const struct arm_boot_info *info,
                                             hwaddr mvbar_addr);
 
-/* Multiplication factor to convert from system clock ticks to qemu timer
-   ticks.  */
-extern int system_clock_scale;
-
 #endif /* HW_ARM_H */
diff --git a/include/hw/timer/armv7m_systick.h b/include/hw/timer/armv7m_systick.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/timer/armv7m_systick.h
+++ b/include/hw/timer/armv7m_systick.h
@@ -XXX,XX +XXX,XX @@ typedef struct SysTickState {
     qemu_irq irq;
 } SysTickState;
 
+/*
+ * Multiplication factor to convert from system clock ticks to qemu timer
+ * ticks. This should be set (by board code, usually) to a value
+ * equal to NANOSECONDS_PER_SECOND / frq, where frq is the clock frequency
+ * in Hz of the CPU.
+ *
+ * This value is used by the systick device when it is running in
+ * its "use the CPU clock" mode (ie when SYST_CSR.CLKSOURCE == 1) to
+ * set how fast the timer should tick.
+ *
+ * TODO: we should refactor this so that rather than using a global
+ * we use a device property or something similar. This is complicated
+ * because (a) the property would need to be plumbed through from the
+ * board code down through various layers to the systick device
+ * and (b) the property needs to be modifiable after realize, because
+ * the stellaris board uses this to implement the behaviour where the
+ * guest can reprogram the PLL registers to downclock the CPU, and the
+ * systick device needs to react accordingly. Possibly this should
+ * be deferred until we have a good API for modelling clock trees.
+ */
+extern int system_clock_scale;
+
 #endif
-- 
2.20.1

The hw/arm/arm.h header now only includes declarations relating
to boot.c code, so it is only needed by Arm board or SoC code.
Remove some unnecessary inclusions of it from target/arm files
and from hw/intc/armv7m_nvic.c.

diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -XXX,XX +XXX,XX @@
 #include "cpu.h"
 #include "hw/sysbus.h"
 #include "qemu/timer.h"
-#include "hw/arm/arm.h"
 #include "hw/intc/armv7m_nvic.h"
 #include "target/arm/cpu.h"
 #include "exec/exec-all.h"
diff --git a/target/arm/arm-semi.c b/target/arm/arm-semi.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/arm-semi.c
+++ b/target/arm/arm-semi.c
@@ -XXX,XX +XXX,XX @@
 #else
 #include "qemu-common.h"
 #include "exec/gdbstub.h"
-#include "hw/arm/arm.h"
 #include "qemu/cutils.h"
 #endif
 
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -XXX,XX +XXX,XX @@
 #if !defined(CONFIG_USER_ONLY)
 #include "hw/loader.h"
 #endif
-#include "hw/arm/arm.h"
 #include "sysemu/sysemu.h"
 #include "sysemu/hw_accel.h"
 #include "kvm_arm.h"
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -XXX,XX +XXX,XX @@
 #if !defined(CONFIG_USER_ONLY)
 #include "hw/loader.h"
 #endif
-#include "hw/arm/arm.h"
 #include "sysemu/sysemu.h"
 #include "sysemu/kvm.h"
 #include "kvm_arm.h"
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -XXX,XX +XXX,XX @@
 #include "cpu.h"
 #include "trace.h"
 #include "internals.h"
-#include "hw/arm/arm.h"
 #include "hw/pci/pci.h"
 #include "exec/memattrs.h"
 #include "exec/address-spaces.h"
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/kvm.h"
 #include "kvm_arm.h"
 #include "internals.h"
-#include "hw/arm/arm.h"
 #include "qemu/log.h"
 
 static inline void set_feature(uint64_t *features, int feature)
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index XXXXXXX..XXXXXXX 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/kvm.h"
 #include "kvm_arm.h"
 #include "internals.h"
-#include "hw/arm/arm.h"
 
 static bool have_guest_debug;
 
-- 
2.20.1

The header file hw/arm/arm.h now includes only declarations
relating to hw/arm/boot.c functionality. Rename it accordingly,
and adjust its header comment.

The bulk of this commit was created via
 perl -pi -e 's|hw/arm/arm.h|hw/arm/boot.h|' hw/arm/*.c include/hw/arm/*.h

In a few cases we can just delete the #include:
hw/arm/msf2-soc.c, include/hw/arm/aspeed_soc.h and
include/hw/arm/bcm2836.h did not require it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190516163857.6430-4-peter.maydell@linaro.org
---
 include/hw/arm/allwinner-a10.h   | 2 +-
 include/hw/arm/aspeed_soc.h      | 1 -
 include/hw/arm/bcm2836.h         | 1 -
 include/hw/arm/{arm.h => boot.h} | 8 ++++----
 include/hw/arm/fsl-imx25.h       | 2 +-
 include/hw/arm/fsl-imx31.h       | 2 +-
 include/hw/arm/fsl-imx6.h        | 2 +-
 include/hw/arm/fsl-imx6ul.h      | 2 +-
 include/hw/arm/fsl-imx7.h        | 2 +-
 include/hw/arm/virt.h            | 2 +-
 include/hw/arm/xlnx-versal.h     | 2 +-
 include/hw/arm/xlnx-zynqmp.h     | 2 +-
 hw/arm/armsse.c                  | 2 +-
 hw/arm/armv7m.c                  | 2 +-
 hw/arm/aspeed.c                  | 2 +-
 hw/arm/boot.c                    | 2 +-
 hw/arm/collie.c                  | 2 +-
 hw/arm/exynos4210.c              | 2 +-
 hw/arm/exynos4_boards.c          | 2 +-
 hw/arm/highbank.c                | 2 +-
 hw/arm/integratorcp.c            | 2 +-
 hw/arm/mainstone.c               | 2 +-
 hw/arm/microbit.c                | 2 +-
 hw/arm/mps2-tz.c                 | 2 +-
 hw/arm/mps2.c                    | 2 +-
 hw/arm/msf2-soc.c                | 1 -
 hw/arm/msf2-som.c                | 2 +-
 hw/arm/musca.c                   | 2 +-
 hw/arm/musicpal.c                | 2 +-
 hw/arm/netduino2.c               | 2 +-
 hw/arm/nrf51_soc.c               | 2 +-
 hw/arm/nseries.c                 | 2 +-
 hw/arm/omap1.c                   | 2 +-
 hw/arm/omap2.c                   | 2 +-
 hw/arm/omap_sx1.c                | 2 +-
 hw/arm/palm.c                    | 2 +-
 hw/arm/raspi.c                   | 2 +-
 hw/arm/realview.c                | 2 +-
 hw/arm/spitz.c                   | 2 +-
 hw/arm/stellaris.c               | 2 +-
 hw/arm/stm32f205_soc.c           | 2 +-
 hw/arm/strongarm.c               | 2 +-
 hw/arm/tosa.c                    | 2 +-
 hw/arm/versatilepb.c             | 2 +-
 hw/arm/vexpress.c                | 2 +-
 hw/arm/virt.c                    | 2 +-
 hw/arm/xilinx_zynq.c             | 2 +-
 hw/arm/xlnx-versal.c             | 2 +-
 hw/arm/z2.c                      | 2 +-
 49 files changed, 49 insertions(+), 52 deletions(-)
 rename include/hw/arm/{arm.h => boot.h} (98%)

diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/allwinner-a10.h
+++ b/include/hw/arm/allwinner-a10.h
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "qemu/error-report.h"
 #include "hw/char/serial.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/timer/allwinner-a10-pit.h"
 #include "hw/intc/allwinner-a10-pic.h"
 #include "hw/net/allwinner_emac.h"
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -XXX,XX +XXX,XX @@
 #ifndef ASPEED_SOC_H
 #define ASPEED_SOC_H
 
-#include "hw/arm/arm.h"
 #include "hw/intc/aspeed_vic.h"
 #include "hw/misc/aspeed_scu.h"
 #include "hw/misc/aspeed_sdmc.h"
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/bcm2836.h
+++ b/include/hw/arm/bcm2836.h
@@ -XXX,XX +XXX,XX @@
 #ifndef BCM2836_H
 #define BCM2836_H
 
-#include "hw/arm/arm.h"
 #include "hw/arm/bcm2835_peripherals.h"
 #include "hw/intc/bcm2836_control.h"
 
diff --git a/include/hw/arm/arm.h b/include/hw/arm/boot.h
similarity index 98%
rename from include/hw/arm/arm.h
rename to include/hw/arm/boot.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/arm.h
+++ b/include/hw/arm/boot.h
@@ -XXX,XX +XXX,XX @@
 /*
- * Misc ARM declarations
+ * ARM kernel loader.
  *
  * Copyright (c) 2006 CodeSourcery.
  * Written by Paul Brook
@@ -XXX,XX +XXX,XX @@
  *
  */
 
-#ifndef HW_ARM_H
-#define HW_ARM_H
+#ifndef HW_ARM_BOOT_H
+#define HW_ARM_BOOT_H
 
 #include "exec/memory.h"
 #include "target/arm/cpu-qom.h"
@@ -XXX,XX +XXX,XX @@ void arm_write_secure_board_setup_dummy_smc(ARMCPU *cpu,
                                             const struct arm_boot_info *info,
                                             hwaddr mvbar_addr);
 
-#endif /* HW_ARM_H */
+#endif /* HW_ARM_BOOT_H */
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx25.h
+++ b/include/hw/arm/fsl-imx25.h
@@ -XXX,XX +XXX,XX @@
 #ifndef FSL_IMX25_H
 #define FSL_IMX25_H
 
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/intc/imx_avic.h"
 #include "hw/misc/imx25_ccm.h"
 #include "hw/char/imx_serial.h"
diff --git a/include/hw/arm/fsl-imx31.h b/include/hw/arm/fsl-imx31.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx31.h
+++ b/include/hw/arm/fsl-imx31.h
@@ -XXX,XX +XXX,XX @@
 #ifndef FSL_IMX31_H
 #define FSL_IMX31_H
 
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/intc/imx_avic.h"
 #include "hw/misc/imx31_ccm.h"
 #include "hw/char/imx_serial.h"
diff --git a/include/hw/arm/fsl-imx6.h b/include/hw/arm/fsl-imx6.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6.h
+++ b/include/hw/arm/fsl-imx6.h
@@ -XXX,XX +XXX,XX @@
 #ifndef FSL_IMX6_H
 #define FSL_IMX6_H
 
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/cpu/a9mpcore.h"
 #include "hw/misc/imx6_ccm.h"
 #include "hw/misc/imx6_src.h"
diff --git a/include/hw/arm/fsl-imx6ul.h b/include/hw/arm/fsl-imx6ul.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx6ul.h
+++ b/include/hw/arm/fsl-imx6ul.h
@@ -XXX,XX +XXX,XX @@
 #ifndef FSL_IMX6UL_H
 #define FSL_IMX6UL_H
 
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/cpu/a15mpcore.h"
 #include "hw/misc/imx6ul_ccm.h"
 #include "hw/misc/imx6_src.h"
diff --git a/include/hw/arm/fsl-imx7.h b/include/hw/arm/fsl-imx7.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/fsl-imx7.h
+++ b/include/hw/arm/fsl-imx7.h
@@ -XXX,XX +XXX,XX @@
 #ifndef FSL_IMX7_H
 #define FSL_IMX7_H
 
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/cpu/a15mpcore.h"
 #include "hw/intc/imx_gpcv2.h"
 #include "hw/misc/imx7_ccm.h"
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -XXX,XX +XXX,XX @@
 #include "exec/hwaddr.h"
 #include "qemu/notify.h"
 #include "hw/boards.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/block/flash.h"
 #include "sysemu/kvm.h"
 #include "hw/intc/arm_gicv3_common.h"
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/xlnx-versal.h
+++ b/include/hw/arm/xlnx-versal.h
@@ -XXX,XX +XXX,XX @@
 #define XLNX_VERSAL_H
 
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/intc/arm_gicv3.h"
 
 #define TYPE_XLNX_VERSAL "xlnx-versal"
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -XXX,XX +XXX,XX @@
 #ifndef XLNX_ZYNQMP_H
 
 #include "qemu-common.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/intc/arm_gic.h"
 #include "hw/net/cadence_gem.h"
 #include "hw/char/cadence_uart.h"
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "hw/registerfields.h"
 #include "hw/arm/armsse.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 
 /* Format of the System Information block SYS_CONFIG register */
 typedef enum SysConfigFormat {
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/armv7m.c
+++ b/hw/arm/armv7m.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/loader.h"
 #include "elf.h"
 #include "sysemu/qtest.h"
diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/aspeed.c
+++ b/hw/arm/aspeed.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "exec/address-spaces.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/aspeed.h"
 #include "hw/arm/aspeed_soc.h"
 #include "hw/boards.h"
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include <libfdt.h>
 #include "hw/hw.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/linux-boot-if.h"
 #include "sysemu/kvm.h"
 #include "sysemu/sysemu.h"
diff --git a/hw/arm/collie.c b/hw/arm/collie.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/collie.c
+++ b/hw/arm/collie.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "hw/boards.h"
 #include "strongarm.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/block/flash.h"
 #include "exec/address-spaces.h"
 #include "cpu.h"
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/boards.h"
 #include "sysemu/sysemu.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/loader.h"
 #include "hw/arm/exynos4210.h"
 #include "hw/sd/sdhci.h"
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/sysemu.h"
 #include "hw/sysbus.h"
 #include "net/net.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "exec/address-spaces.h"
 #include "hw/arm/exynos4210.h"
 #include "hw/net/lan9118.h"
diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/highbank.c
+++ b/hw/arm/highbank.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/loader.h"
 #include "net/net.h"
 #include "sysemu/kvm.h"
diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/integratorcp.c
+++ b/hw/arm/integratorcp.c
@@ -XXX,XX +XXX,XX @@
 #include "cpu.h"
 #include "hw/sysbus.h"
 #include "hw/boards.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/misc/arm_integrator_debug.h"
 #include "hw/net/smc91c111.h"
 #include "net/net.h"
diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mainstone.c
+++ b/hw/arm/mainstone.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "hw/hw.h"
 #include "hw/arm/pxa.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "net/net.h"
 #include "hw/net/smc91c111.h"
 #include "hw/boards.h"
diff --git a/hw/arm/microbit.c b/hw/arm/microbit.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/microbit.c
+++ b/hw/arm/microbit.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "hw/boards.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "sysemu/sysemu.h"
 #include "exec/address-spaces.h"
 
diff --git a/hw/arm/mps2-tz.c b/hw/arm/mps2-tz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps2-tz.c
+++ b/hw/arm/mps2-tz.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "qemu/error-report.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/armv7m.h"
 #include "hw/or-irq.h"
 #include "hw/boards.h"
diff --git a/hw/arm/mps2.c b/hw/arm/mps2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/mps2.c
+++ b/hw/arm/mps2.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "qemu/error-report.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/armv7m.h"
 #include "hw/or-irq.h"
 #include "hw/boards.h"
diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/msf2-soc.c
+++ b/hw/arm/msf2-soc.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/units.h"
 #include "qapi/error.h"
 #include "qemu-common.h"
-#include "hw/arm/arm.h"
 #include "exec/address-spaces.h"
 #include "hw/char/serial.h"
 #include "hw/boards.h"
diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/msf2-som.c
+++ b/hw/arm/msf2-som.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "qemu/error-report.h"
 #include "hw/boards.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "exec/address-spaces.h"
 #include "hw/arm/msf2-soc.h"
 #include "cpu.h"
diff --git a/hw/arm/musca.c b/hw/arm/musca.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/musca.c
+++ b/hw/arm/musca.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "exec/address-spaces.h"
 #include "sysemu/sysemu.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/armsse.h"
 #include "hw/boards.h"
 #include "hw/char/pl011.h"
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/musicpal.c
+++ b/hw/arm/musicpal.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "net/net.h"
 #include "sysemu/sysemu.h"
 #include "hw/boards.h"
diff --git a/hw/arm/netduino2.c b/hw/arm/netduino2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/netduino2.c
+++ b/hw/arm/netduino2.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/boards.h"
 #include "qemu/error-report.h"
 #include "hw/arm/stm32f205_soc.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 
 static void netduino2_init(MachineState *machine)
 {
diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/nrf51_soc.c
+++ b/hw/arm/nrf51_soc.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "qemu-common.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/sysbus.h"
 #include "hw/boards.h"
 #include "hw/misc/unimp.h"
diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/nseries.c
+++ b/hw/arm/nseries.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/bswap.h"
 #include "sysemu/sysemu.h"
 #include "hw/arm/omap.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/irq.h"
 #include "ui/console.h"
 #include "hw/boards.h"
diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/omap1.c
+++ b/hw/arm/omap1.c
@@ -XXX,XX +XXX,XX @@
 #include "cpu.h"
 #include "hw/boards.h"
 #include "hw/hw.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/omap.h"
 #include "sysemu/sysemu.h"
 #include "hw/arm/soc_dma.h"
diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/omap2.c
+++ b/hw/arm/omap2.c
@@ -XXX,XX +XXX,XX @@
 #include "sysemu/qtest.h"
 #include "hw/boards.h"
 #include "hw/hw.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/omap.h"
 #include "sysemu/sysemu.h"
 #include "qemu/timer.h"
diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/omap_sx1.c
+++ b/hw/arm/omap_sx1.c
@@ -XXX,XX +XXX,XX @@
 #include "ui/console.h"
 #include "hw/arm/omap.h"
 #include "hw/boards.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/block/flash.h"
 #include "sysemu/qtest.h"
 #include "exec/address-spaces.h"
diff --git a/hw/arm/palm.c b/hw/arm/palm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/palm.c
+++ b/hw/arm/palm.c
@@ -XXX,XX +XXX,XX @@
 #include "ui/console.h"
 #include "hw/arm/omap.h"
 #include "hw/boards.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/input/tsc2xxx.h"
 #include "hw/loader.h"
 #include "exec/address-spaces.h"
diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/raspi.c
+++ b/hw/arm/raspi.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/error-report.h"
 #include "hw/boards.h"
 #include "hw/loader.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "sysemu/sysemu.h"
 
 #define SMPBOOT_ADDR    0x300 /* this should leave enough space for ATAGS */
diff --git a/hw/arm/realview.c b/hw/arm/realview.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/realview.c
+++ b/hw/arm/realview.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/primecell.h"
 #include "hw/net/lan9118.h"
 #include "hw/net/smc91c111.h"
diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/spitz.c
+++ b/hw/arm/spitz.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "hw/hw.h"
 #include "hw/arm/pxa.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "sysemu/sysemu.h"
 #include "hw/pcmcia.h"
 #include "hw/i2c/i2c.h"
diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/stellaris.c
+++ b/hw/arm/stellaris.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "hw/sysbus.h"
 #include "hw/ssi/ssi.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "qemu/timer.h"
 #include "hw/i2c/i2c.h"
 #include "net/net.h"
diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/stm32f205_soc.c
+++ b/hw/arm/stm32f205_soc.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "qapi/error.h"
 #include "qemu-common.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "exec/address-spaces.h"
 #include "hw/arm/stm32f205_soc.h"
 
diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/strongarm.c
+++ b/hw/arm/strongarm.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/sysbus.h"
 #include "strongarm.h"
 #include "qemu/error-report.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "chardev/char-fe.h"
 #include "chardev/char-serial.h"
 #include "sysemu/sysemu.h"
diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/tosa.c
+++ b/hw/arm/tosa.c
@@ -XXX,XX +XXX,XX @@
 #include "qapi/error.h"
 #include "hw/hw.h"
 #include "hw/arm/pxa.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/sharpsl.h"
 #include "hw/pcmcia.h"
 #include "hw/boards.h"
diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/versatilepb.c
+++ b/hw/arm/versatilepb.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/net/smc91c111.h"
 #include "net/net.h"
 #include "sysemu/sysemu.h"
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/vexpress.c
+++ b/hw/arm/vexpress.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/primecell.h"
 #include "hw/net/lan9118.h"
 #include "hw/i2c/i2c.h"
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/option.h"
 #include "qapi/error.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/arm/primecell.h"
 #include "hw/arm/virt.h"
 #include "hw/block/flash.h"
diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xilinx_zynq.c
+++ b/hw/arm/xilinx_zynq.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu-common.h"
 #include "cpu.h"
 #include "hw/sysbus.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "net/net.h"
 #include "exec/address-spaces.h"
 #include "sysemu/sysemu.h"
diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/xlnx-versal.c
+++ b/hw/arm/xlnx-versal.c
@@ -XXX,XX +XXX,XX @@
 #include "net/net.h"
 #include "sysemu/sysemu.h"
 #include "sysemu/kvm.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "kvm_arm.h"
 #include "hw/misc/unimp.h"
 #include "hw/intc/arm_gicv3_common.h"
diff --git a/hw/arm/z2.c b/hw/arm/z2.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/z2.c
+++ b/hw/arm/z2.c
@@ -XXX,XX +XXX,XX @@
 #include "qemu/osdep.h"
 #include "hw/hw.h"
 #include "hw/arm/pxa.h"
-#include "hw/arm/arm.h"
+#include "hw/arm/boot.h"
 #include "hw/i2c/i2c.h"
 #include "hw/ssi/ssi.h"
 #include "hw/boards.h"
-- 
2.20.1

In ich_vmcr_write() we enforce "writes of BPR fields to less than
their minimum sets them to the minimum" by doing a "read vbpr and
write it back" operation.  A typo here meant that we weren't handling
writes to these fields correctly, because we were reading from VBPR0
but writing to VBPR1.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190520162809.2677-4-peter.maydell@linaro.org
---
 hw/intc/arm_gicv3_cpuif.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

The ICC_CTLR_EL3 register includes some bits which are aliases
of bits in the ICC_CTLR_EL1(S) and (NS) registers. QEMU chooses
to keep those bits in the cs->icc_ctlr_el1[] struct fields.
Unfortunately a missing '~' in the code to update the bits
in those fields meant that writing to ICC_CTLR_EL3 would corrupt
the ICC_CLTR_EL1 register values.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190520162809.2677-5-peter.maydell@linaro.org
---
 hw/intc/arm_gicv3_cpuif.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
     trace_gicv3_icc_ctlr_el3_write(gicv3_redist_affid(cs), value);
 
     /* *_EL1NS and *_EL1S bits are aliases into the ICC_CTLR_EL1 bits. */
-    cs->icc_ctlr_el1[GICV3_NS] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
+    cs->icc_ctlr_el1[GICV3_NS] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
     if (value & ICC_CTLR_EL3_EOIMODE_EL1NS) {
         cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_EOIMODE;
     }
@@ -XXX,XX +XXX,XX @@ static void icc_ctlr_el3_write(CPUARMState *env, const ARMCPRegInfo *ri,
         cs->icc_ctlr_el1[GICV3_NS] |= ICC_CTLR_EL1_CBPR;
     }
 
-    cs->icc_ctlr_el1[GICV3_S] &= (ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
+    cs->icc_ctlr_el1[GICV3_S] &= ~(ICC_CTLR_EL1_CBPR | ICC_CTLR_EL1_EOIMODE);
     if (value & ICC_CTLR_EL3_EOIMODE_EL1S) {
         cs->icc_ctlr_el1[GICV3_S] |= ICC_CTLR_EL1_EOIMODE;
     }
-- 
2.20.1

From: Philippe Mathieu-Daudé <philmd@redhat.com>

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20190520214342.13709-2-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/exynos4_boards.c | 24 ------------------------
 1 file changed, 24 deletions(-)

diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -XXX,XX +XXX,XX @@
 #include "hw/net/lan9118.h"
 #include "hw/boards.h"
 
-#undef DEBUG
-
-//#define DEBUG
-
-#ifdef DEBUG
-    #undef PRINT_DEBUG
-    #define  PRINT_DEBUG(fmt, args...) \
-        do { \
-            fprintf(stderr, "  [%s:%d]   "fmt, __func__, __LINE__, ##args); \
-        } while (0)
-#else
-    #define  PRINT_DEBUG(fmt, args...)  do {} while (0)
-#endif
-
 #define SMDK_LAN9118_BASE_ADDR      0x05000000
 
 typedef enum Exynos4BoardType {
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
     exynos4_board_binfo.gic_cpu_if_addr =
             EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100;
 
-    PRINT_DEBUG("\n ram_size: %luMiB [0x%08lx]\n"
-            " kernel_filename: %s\n"
-            " kernel_cmdline: %s\n"
-            " initrd_filename: %s\n",
-            exynos4_board_ram_size[board_type] / 1048576,
-            exynos4_board_ram_size[board_type],
-            machine->kernel_filename,
-            machine->kernel_cmdline,
-            machine->initrd_filename);
-
     exynos4_boards_init_ram(s, get_system_memory(),
                             exynos4_board_ram_size[board_type]);
 
-- 
2.20.1

From: Philippe Mathieu-Daudé <philmd@redhat.com>

It eases code review, unit is explicit.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20190520214342.13709-3-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/exynos4_boards.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -XXX,XX +XXX,XX @@
  */
 
 #include "qemu/osdep.h"
+#include "qemu/units.h"
 #include "qapi/error.h"
 #include "qemu/error-report.h"
 #include "qemu-common.h"
@@ -XXX,XX +XXX,XX @@ static int exynos4_board_smp_bootreg_addr[EXYNOS4_NUM_OF_BOARDS] = {
 };
 
 static unsigned long exynos4_board_ram_size[EXYNOS4_NUM_OF_BOARDS] = {
-    [EXYNOS4_BOARD_NURI]     = 0x40000000,
-    [EXYNOS4_BOARD_SMDKC210] = 0x40000000,
+    [EXYNOS4_BOARD_NURI]     = 1 * GiB,
+    [EXYNOS4_BOARD_SMDKC210] = 1 * GiB,
 };
 
 static struct arm_boot_info exynos4_board_binfo = {
-- 
2.20.1

From: Guenter Roeck <linux@roeck-us.net>

QEMU already supports pl330. Instantiate it for Exynos4210.

Relevant part of Linux arch/arm/boot/dts/exynos4.dtsi:

/ {
    soc: soc {
        amba {
            pdma0: pdma@12680000 {
                compatible = "arm,pl330", "arm,primecell";
                reg = <0x12680000 0x1000>;
                interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&clock CLK_PDMA0>;
                clock-names = "apb_pclk";
                #dma-cells = <1>;
                #dma-channels = <8>;
                #dma-requests = <32>;
            };
            pdma1: pdma@12690000 {
                compatible = "arm,pl330", "arm,primecell";
                reg = <0x12690000 0x1000>;
                interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&clock CLK_PDMA1>;
                clock-names = "apb_pclk";
                #dma-cells = <1>;
                #dma-channels = <8>;
                #dma-requests = <32>;
            };
            mdma1: mdma@12850000 {
                compatible = "arm,pl330", "arm,primecell";
                reg = <0x12850000 0x1000>;
                interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&clock CLK_MDMA>;
                clock-names = "apb_pclk";
                #dma-cells = <1>;
                #dma-channels = <8>;
                #dma-requests = <1>;
            };
        };
    };
};

Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20190520214342.13709-4-philmd@redhat.com
[PMD: Do not set default qdev properties, create the controllers in the SoC
      rather than the board (Peter Maydell), add dtsi in commit message]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 hw/arm/exynos4210.c | 26 ++++++++++++++++++++++++++
 1 file changed, 26 insertions(+)

diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@
 /* EHCI */
 #define EXYNOS4210_EHCI_BASE_ADDR           0x12580000
 
+/* DMA */
+#define EXYNOS4210_PL330_BASE0_ADDR         0x12680000
+#define EXYNOS4210_PL330_BASE1_ADDR         0x12690000
+#define EXYNOS4210_PL330_BASE2_ADDR         0x12850000
+
 static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43,
                                     0x09, 0x00, 0x00, 0x00 };
 
@@ -XXX,XX +XXX,XX @@ static uint64_t exynos4210_calc_affinity(int cpu)
     return (0x9 << ARM_AFF1_SHIFT) | cpu;
 }
 
+static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
+{
+    SysBusDevice *busdev;
+    DeviceState *dev;
+
+    dev = qdev_create(NULL, "pl330");
+    qdev_prop_set_uint8(dev, "num_periph_req",  nreq);
+    qdev_init_nofail(dev);
+    busdev = SYS_BUS_DEVICE(dev);
+    sysbus_mmio_map(busdev, 0, base);
+    sysbus_connect_irq(busdev, 0, irq);
+}
+
 Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
 {
     Exynos4210State *s = g_new0(Exynos4210State, 1);
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
     sysbus_create_simple(TYPE_EXYNOS4210_EHCI, EXYNOS4210_EHCI_BASE_ADDR,
             s->irq_table[exynos4210_get_irq(28, 3)]);
 
+    /*** DMA controllers ***/
+    pl330_create(EXYNOS4210_PL330_BASE0_ADDR,
+                 qemu_irq_invert(s->irq_table[exynos4210_get_irq(35, 1)]), 32);
+    pl330_create(EXYNOS4210_PL330_BASE1_ADDR,
+                 qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
+    pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
+                 qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
+
     return s;
 }
-- 
2.20.1

From: Philippe Mathieu-Daudé <philmd@redhat.com>

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20190520214342.13709-5-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 include/hw/arm/exynos4210.h |  9 +++++++--
 hw/arm/exynos4210.c         | 28 ++++++++++++++++++++++++----
 hw/arm/exynos4_boards.c     |  9 ++++++---
 3 files changed, 37 insertions(+), 9 deletions(-)

diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index XXXXXXX..XXXXXXX 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210Irq {
 } Exynos4210Irq;
 
 typedef struct Exynos4210State {
+    /*< private >*/
+    SysBusDevice parent_obj;
+    /*< public >*/
     ARMCPU *cpu[EXYNOS4210_NCPUS];
     Exynos4210Irq irqs;
     qemu_irq *irq_table;
@@ -XXX,XX +XXX,XX @@ typedef struct Exynos4210State {
     I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
 } Exynos4210State;
 
+#define TYPE_EXYNOS4210_SOC "exynos4210"
+#define EXYNOS4210_SOC(obj) \
+    OBJECT_CHECK(Exynos4210State, obj, TYPE_EXYNOS4210_SOC)
+
 void exynos4210_write_secondary(ARMCPU *cpu,
         const struct arm_boot_info *info);
 
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem);
-
 /* Initialize exynos4210 IRQ subsystem stub */
 qemu_irq *exynos4210_init_irq(Exynos4210Irq *env);
 
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -XXX,XX +XXX,XX @@ static void pl330_create(uint32_t base, qemu_irq irq, int nreq)
     sysbus_connect_irq(busdev, 0, irq);
 }
 
-Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
+static void exynos4210_realize(DeviceState *socdev, Error **errp)
 {
-    Exynos4210State *s = g_new0(Exynos4210State, 1);
+    Exynos4210State *s = EXYNOS4210_SOC(socdev);
+    MemoryRegion *system_mem = get_system_memory();
     qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS];
     SysBusDevice *busdev;
     DeviceState *dev;
@@ -XXX,XX +XXX,XX @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem)
                  qemu_irq_invert(s->irq_table[exynos4210_get_irq(36, 1)]), 32);
     pl330_create(EXYNOS4210_PL330_BASE2_ADDR,
                  qemu_irq_invert(s->irq_table[exynos4210_get_irq(34, 1)]), 1);
-
-    return s;
 }
+
+static void exynos4210_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+
+    dc->realize = exynos4210_realize;
+}
+
+static const TypeInfo exynos4210_info = {
+    .name = TYPE_EXYNOS4210_SOC,
+    .parent = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(Exynos4210State),
+    .class_init = exynos4210_class_init,
+};
+
+static void exynos4210_register_types(void)
+{
+    type_register_static(&exynos4210_info);
+}
+
+type_init(exynos4210_register_types)
diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c
index XXXXXXX..XXXXXXX 100644
--- a/hw/arm/exynos4_boards.c
+++ b/hw/arm/exynos4_boards.c
@@ -XXX,XX +XXX,XX @@ typedef enum Exynos4BoardType {
 } Exynos4BoardType;
 
 typedef struct Exynos4BoardState {
-    Exynos4210State *soc;
+    Exynos4210State soc;
     MemoryRegion dram0_mem;
     MemoryRegion dram1_mem;
 } Exynos4BoardState;
@@ -XXX,XX +XXX,XX @@ exynos4_boards_init_common(MachineState *machine,
     exynos4_boards_init_ram(s, get_system_memory(),
                             exynos4_board_ram_size[board_type]);
 
-    s->soc = exynos4210_init(get_system_memory());
+    object_initialize(&s->soc, sizeof(s->soc), TYPE_EXYNOS4210_SOC);
+    qdev_set_parent_bus(DEVICE(&s->soc), sysbus_get_default());
+    object_property_set_bool(OBJECT(&s->soc), true, "realized",
+                             &error_fatal);
 
     return s;
 }
@@ -XXX,XX +XXX,XX @@ static void smdkc210_init(MachineState *machine)
                                                       EXYNOS4_BOARD_SMDKC210);
 
     lan9215_init(SMDK_LAN9118_BASE_ADDR,
-            qemu_irq_invert(s->soc->irq_table[exynos4210_get_irq(37, 1)]));
+            qemu_irq_invert(s->soc.irq_table[exynos4210_get_irq(37, 1)]));
     arm_load_kernel(ARM_CPU(first_cpu), &exynos4_board_binfo);
 }
 
-- 
2.20.1