[Qemu-devel] [PULL 0/2] tcg patch queue
[PULL v2 00/21] tcg patch queue
1
The following changes since commit fc3dbb90f2eb069801bfb4cfe9cbc83cf9c5f4a9:
1
Version 2: Drop signed 32-bit guest patches while CI failure examined.
2
2
3
Merge remote-tracking branch 'remotes/jnsnow/tags/bitmaps-pull-request' into staging (2019-02-21 13:09:33 +0000)
3
4
5
The following changes since commit 3d1fbc59665ff8a5d74b0fd30583044fe99e1117:
6
7
Merge remote-tracking branch 'remotes/nvme/tags/nvme-next-pull-request' into staging (2022-03-04 15:31:23 +0000)
4
8
5
are available in the Git repository at:
9
are available in the Git repository at:
6
10
7
https://github.com/rth7680/qemu.git tags/pull-tcg-20190221
11
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20220304
8
12
9
for you to fetch changes up to 8c6edfdd90522caa4fc429144d393aba5b99f584:
13
for you to fetch changes up to cf320769476c3e2820be2a6280bfa1e15baf396f:
10
14
11
include/exec/helper-head.h: support "const void *" in helper calls (2019-02-21 10:22:24 -0800)
15
tcg/i386: Implement bitsel for avx512 (2022-03-04 08:50:41 -1000)
12
16
13
----------------------------------------------------------------
17
----------------------------------------------------------------
14
Allow const void * as argument to helpers.
18
Reorder do_constant_folding_cond test to satisfy valgrind.
15
Remove obsolete TODO file.
19
Fix value of MAX_OPC_PARAM_IARGS.
20
Add opcodes for vector nand, nor, eqv.
21
Support vector nand, nor, eqv on PPC and S390X hosts.
22
Support AVX512VL, AVX512BW, AVX512DQ, and AVX512VBMI2.
16
23
17
----------------------------------------------------------------
24
----------------------------------------------------------------
18
David Hildenbrand (1):
25
Alex Bennée (1):
19
include/exec/helper-head.h: support "const void *" in helper calls
26
tcg/optimize: only read val after const check
20
27
21
Richard Henderson (1):
28
Richard Henderson (19):
22
tcg: Remove TODO file
29
tcg: Add opcodes for vector nand, nor, eqv
30
tcg/ppc: Implement vector NAND, NOR, EQV
31
tcg/s390x: Implement vector NAND, NOR, EQV
32
tcg/i386: Detect AVX512
33
tcg/i386: Add tcg_out_evex_opc
34
tcg/i386: Use tcg_can_emit_vec_op in expand_vec_cmp_noinv
35
tcg/i386: Implement avx512 variable shifts
36
tcg/i386: Implement avx512 scalar shift
37
tcg/i386: Implement avx512 immediate sari shift
38
tcg/i386: Implement avx512 immediate rotate
39
tcg/i386: Implement avx512 variable rotate
40
tcg/i386: Support avx512vbmi2 vector shift-double instructions
41
tcg/i386: Expand vector word rotate as avx512vbmi2 shift-double
42
tcg/i386: Remove rotls_vec from tcg_target_op_def
43
tcg/i386: Expand scalar rotate with avx512 insns
44
tcg/i386: Implement avx512 min/max/abs
45
tcg/i386: Implement avx512 multiply
46
tcg/i386: Implement more logical operations for avx512
47
tcg/i386: Implement bitsel for avx512
23
48
24
include/exec/helper-head.h | 5 +++++
49
Ziqiao Kong (1):
25
tcg/TODO | 14 --------------
50
tcg: Set MAX_OPC_PARAM_IARGS to 7
26
2 files changed, 5 insertions(+), 14 deletions(-)
27
delete mode 100644 tcg/TODO
28
51
52
include/qemu/cpuid.h | 20 ++-
53
include/tcg/tcg-opc.h | 3 +
54
include/tcg/tcg.h | 5 +-
55
tcg/aarch64/tcg-target.h | 3 +
56
tcg/arm/tcg-target.h | 3 +
57
tcg/i386/tcg-target-con-set.h | 1 +
58
tcg/i386/tcg-target.h | 17 +-
59
tcg/i386/tcg-target.opc.h | 3 +
60
tcg/ppc/tcg-target.h | 3 +
61
tcg/s390x/tcg-target.h | 3 +
62
tcg/optimize.c | 20 +--
63
tcg/tcg-op-vec.c | 27 ++-
64
tcg/tcg.c | 6 +
65
tcg/i386/tcg-target.c.inc | 387 +++++++++++++++++++++++++++++++++++-------
66
tcg/ppc/tcg-target.c.inc | 15 ++
67
tcg/s390x/tcg-target.c.inc | 17 ++
68
tcg/tci/tcg-target.c.inc | 2 +-
69
17 files changed, 441 insertions(+), 94 deletions(-)
70
diff view generated by jsdifflib
[Qemu-devel] [PULL 1/2] tcg: Remove TODO file
Deleted patch
1
The last update to this file was 9 years ago. In the meantime,
2
4 of the 6 ideas have actually been completed. The lat two do
3
not actually make sense anymore.
4
1
5
Suggested-by: Thomas Huth <thuth@redhat.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
tcg/TODO | 14 --------------
9
1 file changed, 14 deletions(-)
10
delete mode 100644 tcg/TODO
11
12
diff --git a/tcg/TODO b/tcg/TODO
13
deleted file mode 100644
14
index XXXXXXX..XXXXXXX
15
--- a/tcg/TODO
16
+++ /dev/null
17
@@ -XXX,XX +XXX,XX @@
18
-- Add new instructions such as: clz, ctz, popcnt.
19
-
20
-- See if it is worth exporting mul2, mulu2, div2, divu2.
21
-
22
-- Support of globals saved in fixed registers between TBs.
23
-
24
-Ideas:
25
-
26
-- Move the slow part of the qemu_ld/st ops after the end of the TB.
27
-
28
-- Change exception syntax to get closer to QOP system (exception
29
- parameters given with a specific instruction).
30
-
31
-- Add float and vector support.
32
--
33
2.17.2
34
35
diff view generated by jsdifflib
[Qemu-devel] [PULL 2/2] include/exec/helper-head.h: support "const void *" in helper calls
Deleted patch
1
From: David Hildenbrand <david@redhat.com>
2
1
3
Especially when dealing with out-of-line gvec helpers, it is often
4
helpful to specify some vector pointers as constant. E.g. when
5
we have two inputs and one output, marking the two inputs as consts
6
pointers helps to avoid bugs.
7
8
Const pointers can be specified via "cptr", however behave in TCG just
9
like ordinary pointers. We can specify helpers like:
10
11
DEF_HELPER_FLAGS_4(gvec_vbperm, TCG_CALL_NO_RWG, void, ptr, cptr, cptr, i32)
12
13
void HELPER(gvec_vbperm)(void *v1, const void *v2, const void *v3,
14
uint32_t desc)
15
16
And make sure that here, only v1 will be written (as long as const is
17
not casted away, of course).
18
19
Signed-off-by: David Hildenbrand <david@redhat.com>
20
Message-Id: <20190221093459.22547-1-david@redhat.com>
21
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
22
---
23
include/exec/helper-head.h | 5 +++++
24
1 file changed, 5 insertions(+)
25
26
diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
27
index XXXXXXX..XXXXXXX 100644
28
--- a/include/exec/helper-head.h
29
+++ b/include/exec/helper-head.h
30
@@ -XXX,XX +XXX,XX @@
31
#define dh_alias_f32 i32
32
#define dh_alias_f64 i64
33
#define dh_alias_ptr ptr
34
+#define dh_alias_cptr ptr
35
#define dh_alias_void void
36
#define dh_alias_noreturn noreturn
37
#define dh_alias(t) glue(dh_alias_, t)
38
@@ -XXX,XX +XXX,XX @@
39
#define dh_ctype_f32 float32
40
#define dh_ctype_f64 float64
41
#define dh_ctype_ptr void *
42
+#define dh_ctype_cptr const void *
43
#define dh_ctype_void void
44
#define dh_ctype_noreturn void QEMU_NORETURN
45
#define dh_ctype(t) dh_ctype_##t
46
@@ -XXX,XX +XXX,XX @@
47
#define dh_is_64bit_i32 0
48
#define dh_is_64bit_i64 1
49
#define dh_is_64bit_ptr (sizeof(void *) == 8)
50
+#define dh_is_64bit_cptr dh_is_64bit_ptr
51
#define dh_is_64bit(t) glue(dh_is_64bit_, dh_alias(t))
52
53
#define dh_is_signed_void 0
54
@@ -XXX,XX +XXX,XX @@
55
extension instructions that may be required, e.g. ia64's addp4. But
56
for now we don't support any 64-bit targets with 32-bit pointers. */
57
#define dh_is_signed_ptr 0
58
+#define dh_is_signed_cptr dh_is_signed_ptr
59
#define dh_is_signed_env dh_is_signed_ptr
60
#define dh_is_signed(t) dh_is_signed_##t
61
62
@@ -XXX,XX +XXX,XX @@
63
#define dh_callflag_f32 0
64
#define dh_callflag_f64 0
65
#define dh_callflag_ptr 0
66
+#define dh_callflag_cptr dh_callflag_ptr
67
#define dh_callflag_void 0
68
#define dh_callflag_noreturn TCG_CALL_NO_RETURN
69
#define dh_callflag(t) glue(dh_callflag_, dh_alias(t))
70
--
71
2.17.2
72
73
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

© 2016 - 2025 Red Hat, Inc.