[Qemu-devel] [PULL v2 00/25] target-arm queue
[PULL v2 00/29] target-arm queue
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v2: drop a couple of RTH's patches that he wants to rework.
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v2: drop pvpanic-pci patches.
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The following changes since commit 0266c739abbed804deabb4ccde2aa449466ac3b4:
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The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c:
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Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-feb-14-2019' into staging (2019-02-14 18:33:00 +0000)
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Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190215
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119-1
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for you to fetch changes up to 0f8b09b22234460cb5b8766a25066cf6b5f06842:
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for you to fetch changes up to b93f4fbdc48283a39089469c44a5529d79dc40a8:
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gdbstub: Send a reply to the vKill packet. (2019-02-15 09:56:41 +0000)
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docs: Build and install all the docs in a single manual (2021-01-19 15:45:14 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* gdbstub: Send a reply to the vKill packet
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* Implement IMPDEF pauth algorithm
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* Improve codegen for neon min/max and saturating arithmetic
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* Support ARMv8.4-SEL2
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* Fix a bug in clearing FPSCR exception status bits
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* Fix bug where we were truncating predicate vector lengths in SVE insns
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* hw/arm/armsse: Fix miswiring of expansion IRQs
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* npcm7xx_adc-test: Fix memleak in adc_qom_set
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* hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
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* target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
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* MAINTAINERS: Remove Peter Crosthwaite from various entries
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* docs: Build and install all the docs in a single manual
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* arm: Allow system registers for KVM guests to be changed by QEMU code
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* linux-user: support HWCAP_CPUID which exposes ID registers to user code
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* Fix bug in 128-bit cmpxchg for BE Arm guests
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* Implement (no-op) HACR_EL2
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* Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
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----------------------------------------------------------------
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----------------------------------------------------------------
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Aaron Lindsay OS (1):
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Gan Qixin (1):
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target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
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npcm7xx_adc-test: Fix memleak in adc_qom_set
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Alex Bennée (5):
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Peter Maydell (1):
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target/arm: relax permission checks for HWCAP_CPUID registers
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docs: Build and install all the docs in a single manual
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target/arm: expose CPUID registers to userspace
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target/arm: expose MPIDR_EL1 to userspace
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target/arm: expose remaining CPUID registers as RAZ
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linux-user/elfload: enable HWCAP_CPUID for AArch64
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Catherine Ho (1):
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Philippe Mathieu-Daudé (1):
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target/arm: Fix int128_make128 lo, hi order in paired_cmpxchg64_be
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target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
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Peter Maydell (5):
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Richard Henderson (7):
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target/arm: Implement HACR_EL2
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target/arm: Implement an IMPDEF pauth algorithm
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arm: Allow system registers for KVM guests to be changed by QEMU code
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target/arm: Add cpu properties to control pauth
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MAINTAINERS: Remove Peter Crosthwaite from various entries
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target/arm: Use object_property_add_bool for "sve" property
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hw/intc/armv7m_nvic: Allow byte accesses to SHPR1
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target/arm: Introduce PREDDESC field definitions
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hw/arm/armsse: Fix miswiring of expansion IRQs
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target/arm: Update PFIRST, PNEXT for pred_desc
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target/arm: Update ZIP, UZP, TRN for pred_desc
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target/arm: Update REV, PUNPK for pred_desc
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Richard Henderson (12):
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Rémi Denis-Courmont (19):
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target/arm: Rely on optimization within tcg_gen_gvec_or
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target/arm: remove redundant tests
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target/arm: Use vector minmax expanders for aarch64
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target/arm: add arm_is_el2_enabled() helper
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target/arm: Use vector minmax expanders for aarch32
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target/arm: use arm_is_el2_enabled() where applicable
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target/arm: Use tcg integer min/max primitives for neon
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target/arm: use arm_hcr_el2_eff() where applicable
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target/arm: Remove neon min/max helpers
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target/arm: factor MDCR_EL2 common handling
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target/arm: Fix vfp_gdb_get/set_reg vs FPSCR
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target/arm: Define isar_feature function to test for presence of SEL2
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target/arm: Fix arm_cpu_dump_state vs FPSCR
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target/arm: add 64-bit S-EL2 to EL exception table
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target/arm: Split out flags setting from vfp compares
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target/arm: add MMU stage 1 for Secure EL2
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target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR]
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target/arm: add ARMv8.4-SEL2 system registers
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target/arm: Split out FPSCR.QC to a vector field
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target/arm: handle VMID change in secure state
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target/arm: Use vector operations for saturation
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target/arm: do S1_ptw_translate() before address space lookup
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target/arm: Add missing clear_tail calls
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target/arm: translate NS bit in page-walks
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target/arm: generalize 2-stage page-walk condition
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target/arm: secure stage 2 translation regime
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target/arm: set HPFAR_EL2.NS on secure stage 2 faults
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target/arm: revector to run-time pick target EL
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target/arm: Implement SCR_EL2.EEL2
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target/arm: enable Secure EL2 in max CPU
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target/arm: refactor vae1_tlbmask()
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Sandra Loosemore (1):
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docs/conf.py | 46 ++++-
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gdbstub: Send a reply to the vKill packet.
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docs/devel/conf.py | 15 --
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docs/index.html.in | 17 --
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docs/interop/conf.py | 28 ---
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docs/meson.build | 64 +++---
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docs/specs/conf.py | 16 --
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docs/system/arm/cpu-features.rst | 21 ++
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docs/system/conf.py | 28 ---
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docs/tools/conf.py | 37 ----
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docs/user/conf.py | 15 --
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include/qemu/xxhash.h | 98 +++++++++
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target/arm/cpu-param.h | 2 +-
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target/arm/cpu.h | 107 ++++++++--
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target/arm/internals.h | 45 +++++
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target/arm/cpu.c | 23 ++-
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target/arm/cpu64.c | 65 ++++--
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target/arm/helper-a64.c | 8 +-
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target/arm/helper.c | 414 ++++++++++++++++++++++++++-------------
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target/arm/m_helper.c | 2 +-
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target/arm/monitor.c | 1 +
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target/arm/op_helper.c | 4 +-
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target/arm/pauth_helper.c | 27 ++-
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target/arm/sve_helper.c | 33 ++--
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target/arm/tlb_helper.c | 3 +
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target/arm/translate-a64.c | 4 +
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target/arm/translate-sve.c | 31 ++-
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target/arm/translate.c | 36 +++-
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tests/qtest/arm-cpu-features.c | 13 ++
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tests/qtest/npcm7xx_adc-test.c | 1 +
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.gitlab-ci.yml | 4 +-
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30 files changed, 770 insertions(+), 438 deletions(-)
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delete mode 100644 docs/devel/conf.py
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delete mode 100644 docs/index.html.in
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delete mode 100644 docs/interop/conf.py
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delete mode 100644 docs/specs/conf.py
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delete mode 100644 docs/system/conf.py
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delete mode 100644 docs/tools/conf.py
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delete mode 100644 docs/user/conf.py
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target/arm/cpu.h | 50 +++++++++-
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target/arm/helper.h | 45 ++++++---
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target/arm/translate.h | 4 +
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gdbstub.c | 1 +
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hw/arm/armsse.c | 2 +-
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hw/intc/armv7m_nvic.c | 4 +-
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linux-user/elfload.c | 1 +
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target/arm/helper-a64.c | 4 +-
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target/arm/helper.c | 228 ++++++++++++++++++++++++++++++++++++---------
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target/arm/kvm32.c | 20 +---
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target/arm/kvm64.c | 2 +
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target/arm/machine.c | 2 +-
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target/arm/neon_helper.c | 14 +--
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target/arm/translate-a64.c | 77 ++++++---------
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target/arm/translate-sve.c | 6 +-
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target/arm/translate.c | 219 ++++++++++++++++++++++++++++++++++---------
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target/arm/vec_helper.c | 134 +++++++++++++++++++++++++-
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MAINTAINERS | 4 -
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18 files changed, 622 insertions(+), 195 deletions(-)
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