1. Patchew
  2. QEMU
  3. View series

[Qemu-devel] [PATCH] target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR

Aaron Lindsay OS posted 1 patch 5 years, 2 months ago
Test docker-mingw@fedora passed
Test asan passed
Test checkpatch passed
Test docker-clang@ubuntu passed
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20190205135129.19338-1-aaron@os.amperecomputing.com
Maintainers: Peter Maydell <peter.maydell@linaro.org>
target/arm/helper.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
[Qemu-devel] [PATCH] target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
Posted by Aaron Lindsay OS 5 years, 2 months ago 
This bug was introduced in:
    commit 5ecdd3e47cadae83a62dc92b472f1fe163b56f59
    target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER

Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
---
 target/arm/helper.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/arm/helper.c b/target/arm/helper.c
index d070879894..ec2d17093c 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5855,25 +5855,25 @@ void register_cp_regs_for_features(ARMCPU *cpu)
             char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i);
             char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i);
             ARMCPRegInfo pmev_regs[] = {
-                { .name = pmevcntr_name, .cp = 15, .crn = 15,
+                { .name = pmevcntr_name, .cp = 15, .crn = 14,
                   .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
                   .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
                   .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
                   .accessfn = pmreg_access },
                 { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64,
-                  .opc0 = 3, .opc1 = 3, .crn = 15, .crm = 8 | (3 & (i >> 3)),
+                  .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)),
                   .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
                   .type = ARM_CP_IO,
                   .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
                   .raw_readfn = pmevcntr_rawread,
                   .raw_writefn = pmevcntr_rawwrite },
-                { .name = pmevtyper_name, .cp = 15, .crn = 15,
+                { .name = pmevtyper_name, .cp = 15, .crn = 14,
                   .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
                   .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
                   .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
                   .accessfn = pmreg_access },
                 { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64,
-                  .opc0 = 3, .opc1 = 3, .crn = 15, .crm = 12 | (3 & (i >> 3)),
+                  .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)),
                   .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
                   .type = ARM_CP_IO,
                   .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
-- 
2.20.1
Re: [Qemu-devel] [PATCH] target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
Posted by Laurent Desnogues 5 years, 2 months ago 
On Tue, Feb 5, 2019 at 2:51 PM Aaron Lindsay OS
<aaron@os.amperecomputing.com> wrote:
>
> This bug was introduced in:
>     commit 5ecdd3e47cadae83a62dc92b472f1fe163b56f59
>     target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER
>
> Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
> Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>

Thanks,

Laurent

> ---
>  target/arm/helper.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/arm/helper.c b/target/arm/helper.c
> index d070879894..ec2d17093c 100644
> --- a/target/arm/helper.c
> +++ b/target/arm/helper.c
> @@ -5855,25 +5855,25 @@ void register_cp_regs_for_features(ARMCPU *cpu)
>              char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i);
>              char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i);
>              ARMCPRegInfo pmev_regs[] = {
> -                { .name = pmevcntr_name, .cp = 15, .crn = 15,
> +                { .name = pmevcntr_name, .cp = 15, .crn = 14,
>                    .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
>                    .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
>                    .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
>                    .accessfn = pmreg_access },
>                  { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64,
> -                  .opc0 = 3, .opc1 = 3, .crn = 15, .crm = 8 | (3 & (i >> 3)),
> +                  .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 8 | (3 & (i >> 3)),
>                    .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
>                    .type = ARM_CP_IO,
>                    .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
>                    .raw_readfn = pmevcntr_rawread,
>                    .raw_writefn = pmevcntr_rawwrite },
> -                { .name = pmevtyper_name, .cp = 15, .crn = 15,
> +                { .name = pmevtyper_name, .cp = 15, .crn = 14,
>                    .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
>                    .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
>                    .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
>                    .accessfn = pmreg_access },
>                  { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64,
> -                  .opc0 = 3, .opc1 = 3, .crn = 15, .crm = 12 | (3 & (i >> 3)),
> +                  .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 12 | (3 & (i >> 3)),
>                    .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
>                    .type = ARM_CP_IO,
>                    .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
> --
> 2.20.1
>
Re: [Qemu-devel] [PATCH] target/arm: Fix CRn to be 14 for PMEVTYPER/PMEVCNTR
Posted by Peter Maydell 5 years, 2 months ago 
On Tue, 5 Feb 2019 at 13:51, Aaron Lindsay OS
<aaron@os.amperecomputing.com> wrote:
>
> This bug was introduced in:
>     commit 5ecdd3e47cadae83a62dc92b472f1fe163b56f59
>     target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER
>
> Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
> Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>




Applied to target-arm.next, thanks.

-- PMM

Patchew 2.1-devel-0870f84

© 2016 - 2024 Red Hat, Inc.