Hello,

this series adds SMP-capable interrupt controller model amd instantiates
it on the XTFPGA boards when more than one CPU is specified in command
line. It also adds an MMUv2 SMP-capable xtensa core.

Max Filippov (4):
  target/xtensa: expose core runstall as an IRQ line
  target/xtensa: add MX interrupt controller
  hw/xtensa: xtfpga: use MX PIC for SMP
  target-xtensa: add test_mmuhifi_c3 core

 hw/xtensa/Makefile.objs                            |     1 +
 hw/xtensa/mx_pic.c                                 |   354 +
 hw/xtensa/pic_cpu.c                                |    12 +
 hw/xtensa/xtfpga.c                                 |    22 +-
 include/hw/xtensa/mx_pic.h                         |    44 +
 target/xtensa/Makefile.objs                        |     1 +
 target/xtensa/core-test_mmuhifi_c3.c               |    53 +
 target/xtensa/core-test_mmuhifi_c3/core-isa.h      |   384 +
 .../xtensa/core-test_mmuhifi_c3/gdb-config.inc.c   |   140 +
 .../core-test_mmuhifi_c3/xtensa-modules.inc.c      | 36403 +++++++++++++++++++
 target/xtensa/cpu.h                                |     2 +
 11 files changed, 37415 insertions(+), 1 deletion(-)
 create mode 100644 hw/xtensa/mx_pic.c
 create mode 100644 include/hw/xtensa/mx_pic.h
 create mode 100644 target/xtensa/core-test_mmuhifi_c3.c
 create mode 100644 target/xtensa/core-test_mmuhifi_c3/core-isa.h
 create mode 100644 target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c
 create mode 100644 target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c

-- 
2.11.0