aspeed/smc: add fast read support under User command mode.

[Qemu-devel] [PATCH 0/4] aspeed/smc: add fast read support under User command mode.

Cédric Le Goater posted 4 patches 6 years, 9 months ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20190124140519.13838-1-clg@kaod.org

Maintainers: Peter Crosthwaite <crosthwaite.peter@gmail.com>, Andrew Jeffery <andrew@aj.id.au>, Alistair Francis <alistair@alistair23.me>, "Cédric Le Goater" <clg@kaod.org>, Peter Maydell <peter.maydell@linaro.org>, Joel Stanley <joel@jms.id.au>

include/hw/ssi/aspeed_smc.h |   3 +
hw/ssi/aspeed_smc.c         | 128 +++++++++++++++++++++++++++++++++---
2 files changed, 123 insertions(+), 8 deletions(-)

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[Qemu-devel] [PATCH 0/4] aspeed/smc: add fast read support under User command mode.

Posted by Cédric Le Goater 6 years, 9 months ago

Hello,

When in the User command mode, the Aspeed SMC controller driver
performs the dummy cycles of a fast read command using byte transfers,
that is ony byte for eight cycles. But, the QEMU m25p80 models one
dummy cycle with one byte transfer.

To restore the correct number of cycles, this series adds a function
snooping the SPI transfers to catch commands requiring dummy cycles
and replaces them with byte transfers compatible with the m25p80 model.

Thanks,

C.

Cédric Le Goater (4):
  aspeed/smc: fix default read value
  aspeed/smc: define registers for all possible CS
  aspeed/smc: Add dummy data register
  aspeed/smc: snoop transfers to fake dummy cycles

 include/hw/ssi/aspeed_smc.h |   3 +
 hw/ssi/aspeed_smc.c         | 128 +++++++++++++++++++++++++++++++++---
 2 files changed, 123 insertions(+), 8 deletions(-)

-- 
2.20.1

Re: [Qemu-devel] [PATCH 0/4] aspeed/smc: add fast read support under User command mode.

Posted by Peter Maydell 6 years, 9 months ago

On Thu, 24 Jan 2019 at 14:08, Cédric Le Goater <clg@kaod.org> wrote:
>
> Hello,
>
> When in the User command mode, the Aspeed SMC controller driver
> performs the dummy cycles of a fast read command using byte transfers,
> that is ony byte for eight cycles. But, the QEMU m25p80 models one
> dummy cycle with one byte transfer.
>
> To restore the correct number of cycles, this series adds a function
> snooping the SPI transfers to catch commands requiring dummy cycles
> and replaces them with byte transfers compatible with the m25p80 model.
>
> Thanks,
>
> C.
>
> Cédric Le Goater (4):
>   aspeed/smc: fix default read value
>   aspeed/smc: define registers for all possible CS
>   aspeed/smc: Add dummy data register
>   aspeed/smc: snoop transfers to fake dummy cycles


Applied to target-arm.next, thanks.

-- PMM