Hi,

this patchset converts the RISC-V decoder to decodetree in four major steps:

1) Convert 32-bit instructions to decodetree [Patch 1-16]:
    Many of the gen_* functions are called by the decode functions for 16-bit
    and 32-bit functions. If we move translation code from the gen_*
    functions to the generated trans_* functions of decode-tree, we get a lot of
    duplication. Therefore, we mostly generate calls to the old gen_* function
    which are properly replaced after step 2).

    Each of the trans_ functions are grouped into files corresponding to their
    ISA extension, e.g. addi which is in RV32I is translated in the file
    'trans_rvi.inc.c'.

2) Convert 16-bit instructions to decodetree [Patch 17-19]:
    All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
    we convert the arguments in the 16 bit trans_ function to the arguments of
    the corresponding 32 bit instruction and call the 32 bit trans_ function.

3) Remove old manual decoding in gen_* function [Patch 20-30]:
    this move all manual translation code into the trans_* instructions of
    decode tree, such that we can remove the old decode_* functions.

4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested
   by Richard. [Patch 31-35]

full tree available at
https://github.com/bkoppelmann/qemu/tree/riscv-dt-v6

Cheers,
Bastian

v5 -> v6:
    - fixed funky indentation


Bastian Koppelmann (35):
  target/riscv: Move CPURISCVState pointer to DisasContext
  target/riscv: Activate decodetree and implemnt LUI & AUIPC
  target/riscv: Convert RVXI branch insns to decodetree
  target/riscv: Convert RV32I load/store insns to decodetree
  target/riscv: Convert RV64I load/store insns to decodetree
  target/riscv: Convert RVXI arithmetic insns to decodetree
  target/riscv: Convert RVXI fence insns to decodetree
  target/riscv: Convert RVXI csr insns to decodetree
  target/riscv: Convert RVXM insns to decodetree
  target/riscv: Convert RV32A insns to decodetree
  target/riscv: Convert RV64A insns to decodetree
  target/riscv: Convert RV32F insns to decodetree
  target/riscv: Convert RV64F insns to decodetree
  target/riscv: Convert RV32D insns to decodetree
  target/riscv: Convert RV64D insns to decodetree
  target/riscv: Convert RV priv insns to decodetree
  target/riscv: Convert quadrant 0 of RVXC insns to decodetree
  target/riscv: Convert quadrant 1 of RVXC insns to decodetree
  target/riscv: Convert quadrant 2 of RVXC insns to decodetree
  target/riscv: Remove gen_jalr()
  target/riscv: Remove manual decoding from gen_branch()
  target/riscv: Remove manual decoding from gen_load()
  target/riscv: Remove manual decoding from gen_store()
  target/riscv: Move gen_arith_imm() decoding into trans_* functions
  target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
  target/riscv: Remove shift and slt insn manual decoding
  target/riscv: Remove manual decoding of RV32/64M insn
  target/riscv: Rename trans_arith to gen_arith
  target/riscv: Remove gen_system()
  target/riscv: Remove decode_RV32_64G()
  target/riscv: Convert @cs_2 insns to share translation functions
  target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
  target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
  target/riscv: Splice remaining compressed insn pairs for riscv32 vs
    riscv64
  target/riscv: Remaining rvc insn reuse 32 bit translators

 target/riscv/Makefile.objs                    |   22 +
 target/riscv/insn16-32.decode                 |   31 +
 target/riscv/insn16-64.decode                 |   33 +
 target/riscv/insn16.decode                    |  114 ++
 target/riscv/insn32-64.decode                 |   72 +
 target/riscv/insn32.decode                    |  203 ++
 .../riscv/insn_trans/trans_privileged.inc.c   |  110 +
 target/riscv/insn_trans/trans_rva.inc.c       |  207 ++
 target/riscv/insn_trans/trans_rvc.inc.c       |  149 ++
 target/riscv/insn_trans/trans_rvd.inc.c       |  388 ++++
 target/riscv/insn_trans/trans_rvf.inc.c       |  388 ++++
 target/riscv/insn_trans/trans_rvi.inc.c       |  568 ++++++
 target/riscv/insn_trans/trans_rvm.inc.c       |  107 +
 target/riscv/translate.c                      | 1781 ++---------------
 14 files changed, 2611 insertions(+), 1562 deletions(-)
 create mode 100644 target/riscv/insn16-32.decode
 create mode 100644 target/riscv/insn16-64.decode
 create mode 100644 target/riscv/insn16.decode
 create mode 100644 target/riscv/insn32-64.decode
 create mode 100644 target/riscv/insn32.decode
 create mode 100644 target/riscv/insn_trans/trans_privileged.inc.c
 create mode 100644 target/riscv/insn_trans/trans_rva.inc.c
 create mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
 create mode 100644 target/riscv/insn_trans/trans_rvd.inc.c
 create mode 100644 target/riscv/insn_trans/trans_rvf.inc.c
 create mode 100644 target/riscv/insn_trans/trans_rvi.inc.c
 create mode 100644 target/riscv/insn_trans/trans_rvm.inc.c

-- 
2.20.1

On Wed, 23 Jan 2019 01:25:03 PST (-0800), Bastian Koppelmann wrote:
> Hi,
>
> this patchset converts the RISC-V decoder to decodetree in four major steps:
>
> 1) Convert 32-bit instructions to decodetree [Patch 1-16]:
>     Many of the gen_* functions are called by the decode functions for 16-bit
>     and 32-bit functions. If we move translation code from the gen_*
>     functions to the generated trans_* functions of decode-tree, we get a lot of
>     duplication. Therefore, we mostly generate calls to the old gen_* function
>     which are properly replaced after step 2).
>
>     Each of the trans_ functions are grouped into files corresponding to their
>     ISA extension, e.g. addi which is in RV32I is translated in the file
>     'trans_rvi.inc.c'.
>
> 2) Convert 16-bit instructions to decodetree [Patch 17-19]:
>     All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
>     we convert the arguments in the 16 bit trans_ function to the arguments of
>     the corresponding 32 bit instruction and call the 32 bit trans_ function.
>
> 3) Remove old manual decoding in gen_* function [Patch 20-30]:
>     this move all manual translation code into the trans_* instructions of
>     decode tree, such that we can remove the old decode_* functions.
>
> 4) Simplify RVC by reusing as much as possible from the RVG decoder as suggested
>    by Richard. [Patch 31-35]
>
> full tree available at
> https://github.com/bkoppelmann/qemu/tree/riscv-dt-v6
>
> Cheers,
> Bastian
>
> v5 -> v6:
>     - fixed funky indentation
>
>
> Bastian Koppelmann (35):
>   target/riscv: Move CPURISCVState pointer to DisasContext
>   target/riscv: Activate decodetree and implemnt LUI & AUIPC
>   target/riscv: Convert RVXI branch insns to decodetree
>   target/riscv: Convert RV32I load/store insns to decodetree
>   target/riscv: Convert RV64I load/store insns to decodetree
>   target/riscv: Convert RVXI arithmetic insns to decodetree
>   target/riscv: Convert RVXI fence insns to decodetree
>   target/riscv: Convert RVXI csr insns to decodetree
>   target/riscv: Convert RVXM insns to decodetree
>   target/riscv: Convert RV32A insns to decodetree
>   target/riscv: Convert RV64A insns to decodetree
>   target/riscv: Convert RV32F insns to decodetree
>   target/riscv: Convert RV64F insns to decodetree
>   target/riscv: Convert RV32D insns to decodetree
>   target/riscv: Convert RV64D insns to decodetree
>   target/riscv: Convert RV priv insns to decodetree
>   target/riscv: Convert quadrant 0 of RVXC insns to decodetree
>   target/riscv: Convert quadrant 1 of RVXC insns to decodetree
>   target/riscv: Convert quadrant 2 of RVXC insns to decodetree
>   target/riscv: Remove gen_jalr()
>   target/riscv: Remove manual decoding from gen_branch()
>   target/riscv: Remove manual decoding from gen_load()
>   target/riscv: Remove manual decoding from gen_store()
>   target/riscv: Move gen_arith_imm() decoding into trans_* functions
>   target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
>   target/riscv: Remove shift and slt insn manual decoding
>   target/riscv: Remove manual decoding of RV32/64M insn
>   target/riscv: Rename trans_arith to gen_arith
>   target/riscv: Remove gen_system()
>   target/riscv: Remove decode_RV32_64G()
>   target/riscv: Convert @cs_2 insns to share translation functions
>   target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
>   target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
>   target/riscv: Splice remaining compressed insn pairs for riscv32 vs
>     riscv64
>   target/riscv: Remaining rvc insn reuse 32 bit translators
>
>  target/riscv/Makefile.objs                    |   22 +
>  target/riscv/insn16-32.decode                 |   31 +
>  target/riscv/insn16-64.decode                 |   33 +
>  target/riscv/insn16.decode                    |  114 ++
>  target/riscv/insn32-64.decode                 |   72 +
>  target/riscv/insn32.decode                    |  203 ++
>  .../riscv/insn_trans/trans_privileged.inc.c   |  110 +
>  target/riscv/insn_trans/trans_rva.inc.c       |  207 ++
>  target/riscv/insn_trans/trans_rvc.inc.c       |  149 ++
>  target/riscv/insn_trans/trans_rvd.inc.c       |  388 ++++
>  target/riscv/insn_trans/trans_rvf.inc.c       |  388 ++++
>  target/riscv/insn_trans/trans_rvi.inc.c       |  568 ++++++
>  target/riscv/insn_trans/trans_rvm.inc.c       |  107 +
>  target/riscv/translate.c                      | 1781 ++---------------
>  14 files changed, 2611 insertions(+), 1562 deletions(-)
>  create mode 100644 target/riscv/insn16-32.decode
>  create mode 100644 target/riscv/insn16-64.decode
>  create mode 100644 target/riscv/insn16.decode
>  create mode 100644 target/riscv/insn32-64.decode
>  create mode 100644 target/riscv/insn32.decode
>  create mode 100644 target/riscv/insn_trans/trans_privileged.inc.c
>  create mode 100644 target/riscv/insn_trans/trans_rva.inc.c
>  create mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
>  create mode 100644 target/riscv/insn_trans/trans_rvd.inc.c
>  create mode 100644 target/riscv/insn_trans/trans_rvf.inc.c
>  create mode 100644 target/riscv/insn_trans/trans_rvi.inc.c
>  create mode 100644 target/riscv/insn_trans/trans_rvm.inc.c

Do you, by any chance, have a v7?  It looks like there's quite a few merge 
conflicts here, and while I'm OK fixing them I don't want to do it if you 
already have.

On Tue, Feb 12, 2019 at 3:21 PM Palmer Dabbelt <palmer@sifive.com> wrote:

> On Wed, 23 Jan 2019 01:25:03 PST (-0800), Bastian Koppelmann wrote:
> > Hi,
> >
> > this patchset converts the RISC-V decoder to decodetree in four major
> steps:
> >
> > 1) Convert 32-bit instructions to decodetree [Patch 1-16]:
> >     Many of the gen_* functions are called by the decode functions for
> 16-bit
> >     and 32-bit functions. If we move translation code from the gen_*
> >     functions to the generated trans_* functions of decode-tree, we get
> a lot of
> >     duplication. Therefore, we mostly generate calls to the old gen_*
> function
> >     which are properly replaced after step 2).
> >
> >     Each of the trans_ functions are grouped into files corresponding to
> their
> >     ISA extension, e.g. addi which is in RV32I is translated in the file
> >     'trans_rvi.inc.c'.
> >
> > 2) Convert 16-bit instructions to decodetree [Patch 17-19]:
> >     All 16 bit instructions have a direct mapping to a 32 bit
> instruction. Thus,
> >     we convert the arguments in the 16 bit trans_ function to the
> arguments of
> >     the corresponding 32 bit instruction and call the 32 bit trans_
> function.
> >
> > 3) Remove old manual decoding in gen_* function [Patch 20-30]:
> >     this move all manual translation code into the trans_* instructions
> of
> >     decode tree, such that we can remove the old decode_* functions.
> >
> > 4) Simplify RVC by reusing as much as possible from the RVG decoder as
> suggested
> >    by Richard. [Patch 31-35]
> >
> > full tree available at
> > https://github.com/bkoppelmann/qemu/tree/riscv-dt-v6
> >
> > Cheers,
> > Bastian
> >
> > v5 -> v6:
> >     - fixed funky indentation
> >
> >
> > Bastian Koppelmann (35):
> >   target/riscv: Move CPURISCVState pointer to DisasContext
> >   target/riscv: Activate decodetree and implemnt LUI & AUIPC
> >   target/riscv: Convert RVXI branch insns to decodetree
> >   target/riscv: Convert RV32I load/store insns to decodetree
> >   target/riscv: Convert RV64I load/store insns to decodetree
> >   target/riscv: Convert RVXI arithmetic insns to decodetree
> >   target/riscv: Convert RVXI fence insns to decodetree
> >   target/riscv: Convert RVXI csr insns to decodetree
> >   target/riscv: Convert RVXM insns to decodetree
> >   target/riscv: Convert RV32A insns to decodetree
> >   target/riscv: Convert RV64A insns to decodetree
> >   target/riscv: Convert RV32F insns to decodetree
> >   target/riscv: Convert RV64F insns to decodetree
> >   target/riscv: Convert RV32D insns to decodetree
> >   target/riscv: Convert RV64D insns to decodetree
> >   target/riscv: Convert RV priv insns to decodetree
> >   target/riscv: Convert quadrant 0 of RVXC insns to decodetree
> >   target/riscv: Convert quadrant 1 of RVXC insns to decodetree
> >   target/riscv: Convert quadrant 2 of RVXC insns to decodetree
> >   target/riscv: Remove gen_jalr()
> >   target/riscv: Remove manual decoding from gen_branch()
> >   target/riscv: Remove manual decoding from gen_load()
> >   target/riscv: Remove manual decoding from gen_store()
> >   target/riscv: Move gen_arith_imm() decoding into trans_* functions
> >   target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
> >   target/riscv: Remove shift and slt insn manual decoding
> >   target/riscv: Remove manual decoding of RV32/64M insn
> >   target/riscv: Rename trans_arith to gen_arith
> >   target/riscv: Remove gen_system()
> >   target/riscv: Remove decode_RV32_64G()
> >   target/riscv: Convert @cs_2 insns to share translation functions
> >   target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
> >   target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
> >   target/riscv: Splice remaining compressed insn pairs for riscv32 vs
> >     riscv64
> >   target/riscv: Remaining rvc insn reuse 32 bit translators
> >
> >  target/riscv/Makefile.objs                    |   22 +
> >  target/riscv/insn16-32.decode                 |   31 +
> >  target/riscv/insn16-64.decode                 |   33 +
> >  target/riscv/insn16.decode                    |  114 ++
> >  target/riscv/insn32-64.decode                 |   72 +
> >  target/riscv/insn32.decode                    |  203 ++
> >  .../riscv/insn_trans/trans_privileged.inc.c   |  110 +
> >  target/riscv/insn_trans/trans_rva.inc.c       |  207 ++
> >  target/riscv/insn_trans/trans_rvc.inc.c       |  149 ++
> >  target/riscv/insn_trans/trans_rvd.inc.c       |  388 ++++
> >  target/riscv/insn_trans/trans_rvf.inc.c       |  388 ++++
> >  target/riscv/insn_trans/trans_rvi.inc.c       |  568 ++++++
> >  target/riscv/insn_trans/trans_rvm.inc.c       |  107 +
> >  target/riscv/translate.c                      | 1781 ++---------------
> >  14 files changed, 2611 insertions(+), 1562 deletions(-)
> >  create mode 100644 target/riscv/insn16-32.decode
> >  create mode 100644 target/riscv/insn16-64.decode
> >  create mode 100644 target/riscv/insn16.decode
> >  create mode 100644 target/riscv/insn32-64.decode
> >  create mode 100644 target/riscv/insn32.decode
> >  create mode 100644 target/riscv/insn_trans/trans_privileged.inc.c
> >  create mode 100644 target/riscv/insn_trans/trans_rva.inc.c
> >  create mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
> >  create mode 100644 target/riscv/insn_trans/trans_rvd.inc.c
> >  create mode 100644 target/riscv/insn_trans/trans_rvf.inc.c
> >  create mode 100644 target/riscv/insn_trans/trans_rvi.inc.c
> >  create mode 100644 target/riscv/insn_trans/trans_rvm.inc.c
>
> Do you, by any chance, have a v7?  It looks like there's quite a few merge
> conflicts here, and while I'm OK fixing them I don't want to do it if you
> already have.
>

I made it through my rebase, so unless you want to send out a v7 I will.
There were some meaningful changes so I'd like to get a round of review
just so everyone is on the same page.

On 2/13/19 3:15 AM, Palmer Dabbelt wrote:
> On Tue, Feb 12, 2019 at 3:21 PM Palmer Dabbelt <palmer@sifive.com> wrote:
[snip]
>>
>> Do you, by any chance, have a v7?  It looks like there's quite a few merge
>> conflicts here, and while I'm OK fixing them I don't want to do it if you
>> already have.
>>
> I made it through my rebase, so unless you want to send out a v7 I will.
> There were some meaningful changes so I'd like to get a round of review
> just so everyone is on the same page.


Thanks for doing this work. I don't have a v7 yet, since I was waiting 
on your current pull-request to get merged. So please do send a v7, I'm 
happy to review/test it.

Cheers,

Bastian

On Wed, 13 Feb 2019 01:06:41 PST (-0800), Bastian Koppelmann wrote:
>
> On 2/13/19 3:15 AM, Palmer Dabbelt wrote:
>> On Tue, Feb 12, 2019 at 3:21 PM Palmer Dabbelt <palmer@sifive.com> wrote:
> [snip]
>>>
>>> Do you, by any chance, have a v7?  It looks like there's quite a few merge
>>> conflicts here, and while I'm OK fixing them I don't want to do it if you
>>> already have.
>>>
>> I made it through my rebase, so unless you want to send out a v7 I will.
>> There were some meaningful changes so I'd like to get a round of review
>> just so everyone is on the same page.
>
>
> Thanks for doing this work. I don't have a v7 yet, since I was waiting
> on your current pull-request to get merged. So please do send a v7, I'm
> happy to review/test it.

No problem, they're my merge conflicts :).  It's on the list.

On Wed, 13 Feb 2019 01:06:41 PST (-0800), Bastian Koppelmann wrote:
>
> On 2/13/19 3:15 AM, Palmer Dabbelt wrote:
>> On Tue, Feb 12, 2019 at 3:21 PM Palmer Dabbelt <palmer@sifive.com> wrote:
> [snip]
>>>
>>> Do you, by any chance, have a v7?  It looks like there's quite a few merge
>>> conflicts here, and while I'm OK fixing them I don't want to do it if you
>>> already have.
>>>
>> I made it through my rebase, so unless you want to send out a v7 I will.
>> There were some meaningful changes so I'd like to get a round of review
>> just so everyone is on the same page.
>
>
> Thanks for doing this work. I don't have a v7 yet, since I was waiting
> on your current pull-request to get merged. So please do send a v7, I'm
> happy to review/test it.

Sounds good.  It definitely deserves a review, as I was sort of just fumbling 
around in the dark here :)

Patchew URL: https://patchew.org/QEMU/20190123092538.8004-1-kbastian@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190123092538.8004-1-kbastian@mail.uni-paderborn.de

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
278051918f target/riscv: Remaining rvc insn reuse 32 bit translators
a87e6e35fb target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
24bff9f4ba target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
726e1f43c1 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
9420608fc4 target/riscv: Convert @cs_2 insns to share translation functions
0a0f1b7336 target/riscv: Remove decode_RV32_64G()
5c1a51d989 target/riscv: Remove gen_system()
a68220d0d8 target/riscv: Rename trans_arith to gen_arith
c0ff41680c target/riscv: Remove manual decoding of RV32/64M insn
aceeea6940 target/riscv: Remove shift and slt insn manual decoding
4177aa12cb target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
31b5b053d0 target/riscv: Move gen_arith_imm() decoding into trans_* functions
b09a386410 target/riscv: Remove manual decoding from gen_store()
4a66d1683e target/riscv: Remove manual decoding from gen_load()
1504f31cfb target/riscv: Remove manual decoding from gen_branch()
3fc86b5718 target/riscv: Remove gen_jalr()
862c038e96 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
dadd6fd1cf target/riscv: Convert quadrant 1 of RVXC insns to decodetree
bbbd541526 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
22275dc23a target/riscv: Convert RV priv insns to decodetree
6bd6eba713 target/riscv: Convert RV64D insns to decodetree
ae069ba722 target/riscv: Convert RV32D insns to decodetree
1589e74dbf target/riscv: Convert RV64F insns to decodetree
8857eb324d target/riscv: Convert RV32F insns to decodetree
b9b3a0b782 target/riscv: Convert RV64A insns to decodetree
098d10b6b7 target/riscv: Convert RV32A insns to decodetree
a23ebbba2f target/riscv: Convert RVXM insns to decodetree
11f193d691 target/riscv: Convert RVXI csr insns to decodetree
65c828ac40 target/riscv: Convert RVXI fence insns to decodetree
c99c1e3a78 target/riscv: Convert RVXI arithmetic insns to decodetree
1629aa4d6e target/riscv: Convert RV64I load/store insns to decodetree
49279f7f05 target/riscv: Convert RV32I load/store insns to decodetree
4af4026ba5 target/riscv: Convert RVXI branch insns to decodetree
9ea6816814 target/riscv: Activate decodetree and implemnt LUI & AUIPC
9b28c37658 target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit 9b28c3765893 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 9ea68168149f (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#33: 
new file mode 100644

ERROR: externs should be avoided in .c files
#124: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit 4af4026ba501 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 49279f7f055e (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 1629aa4d6ed2 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#38: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit c99c1e3a7803 (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 65c828ac4004 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 11f193d69175 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit a23ebbba2fe1 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#47: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 098d10b6b754 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#53: 
new file mode 100644

total: 0 errors, 1 warnings, 188 lines checked

Patch 10/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit b9b3a0b782df (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 8857eb324d81 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#77: 
new file mode 100644

total: 0 errors, 1 warnings, 397 lines checked

Patch 12/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 1589e74dbfc1 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit ae069ba72242 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#50: 
new file mode 100644

total: 0 errors, 1 warnings, 353 lines checked

Patch 14/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 6bd6eba7131e (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 22275dc23a4d (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#40: 
new file mode 100644

total: 0 errors, 1 warnings, 214 lines checked

Patch 16/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit bbbd541526d7 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#30: 
new file mode 100644

ERROR: externs should be avoided in .c files
#245: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);

total: 1 errors, 1 warnings, 227 lines checked

Patch 17/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

18/35 Checking commit dadd6fd1cff0 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 862c038e96e5 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 3fc86b57189a (target/riscv: Remove gen_jalr())
21/35 Checking commit 1504f31cfb10 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 4a66d1683e0d (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit b09a3864104f (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit 31b5b053d0b4 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 4177aa12cb00 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit aceeea694040 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit c0ff41680ca5 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit a68220d0d81f (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 5c1a51d989de (target/riscv: Remove gen_system())
30/35 Checking commit 0a0f1b73365b (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 9420608fc4c4 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41: 
new file mode 100644

ERROR: externs should be avoided in .c files
#181: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);

total: 1 errors, 1 warnings, 164 lines checked

Patch 31/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

32/35 Checking commit 726e1f43c1ae (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 24bff9f4baf8 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#27: 
new file mode 100644

total: 0 errors, 1 warnings, 287 lines checked

Patch 33/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit a87e6e35fb57 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 278051918fff (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20190123092538.8004-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com

Patchew URL: https://patchew.org/QEMU/20190123092538.8004-1-kbastian@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree
Message-id: 20190123092538.8004-1-kbastian@mail.uni-paderborn.de
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Submodule 'capstone' (https://git.qemu.org/git/capstone.git) registered for path 'capstone'
Submodule 'dtc' (https://git.qemu.org/git/dtc.git) registered for path 'dtc'
Submodule 'roms/QemuMacDrivers' (https://git.qemu.org/git/QemuMacDrivers.git) registered for path 'roms/QemuMacDrivers'
Submodule 'roms/SLOF' (https://git.qemu.org/git/SLOF.git) registered for path 'roms/SLOF'
Submodule 'roms/ipxe' (https://git.qemu.org/git/ipxe.git) registered for path 'roms/ipxe'
Submodule 'roms/openbios' (https://git.qemu.org/git/openbios.git) registered for path 'roms/openbios'
Submodule 'roms/openhackware' (https://git.qemu.org/git/openhackware.git) registered for path 'roms/openhackware'
Submodule 'roms/qemu-palcode' (https://git.qemu.org/git/qemu-palcode.git) registered for path 'roms/qemu-palcode'
Submodule 'roms/seabios' (https://git.qemu.org/git/seabios.git/) registered for path 'roms/seabios'
Submodule 'roms/seabios-hppa' (https://github.com/hdeller/seabios-hppa.git) registered for path 'roms/seabios-hppa'
Submodule 'roms/sgabios' (https://git.qemu.org/git/sgabios.git) registered for path 'roms/sgabios'
Submodule 'roms/skiboot' (https://git.qemu.org/git/skiboot.git) registered for path 'roms/skiboot'
Submodule 'roms/u-boot' (https://git.qemu.org/git/u-boot.git) registered for path 'roms/u-boot'
Submodule 'roms/u-boot-sam460ex' (https://git.qemu.org/git/u-boot-sam460ex.git) registered for path 'roms/u-boot-sam460ex'
Submodule 'tests/fp/berkeley-softfloat-3' (https://github.com/cota/berkeley-softfloat-3) registered for path 'tests/fp/berkeley-softfloat-3'
Submodule 'tests/fp/berkeley-testfloat-3' (https://github.com/cota/berkeley-testfloat-3) registered for path 'tests/fp/berkeley-testfloat-3'
Submodule 'ui/keycodemapdb' (https://git.qemu.org/git/keycodemapdb.git) registered for path 'ui/keycodemapdb'
Cloning into 'capstone'...
Submodule path 'capstone': checked out '22ead3e0bfdb87516656453336160e0a37b066bf'
Cloning into 'dtc'...
Submodule path 'dtc': checked out '88f18909db731a627456f26d779445f84e449536'
Cloning into 'roms/QemuMacDrivers'...
Submodule path 'roms/QemuMacDrivers': checked out 'd4e7d7ac663fcb55f1b93575445fcbca372f17a7'
Cloning into 'roms/SLOF'...
Submodule path 'roms/SLOF': checked out '9b7ab2fa020341dee8bf9df6c9cf40003e0136df'
Cloning into 'roms/ipxe'...
Submodule path 'roms/ipxe': checked out 'de4565cbe76ea9f7913a01f331be3ee901bb6e17'
Cloning into 'roms/openbios'...
Submodule path 'roms/openbios': checked out '441a84d3a642a10b948369c63f32367e8ff6395b'
Cloning into 'roms/openhackware'...
Submodule path 'roms/openhackware': checked out 'c559da7c8eec5e45ef1f67978827af6f0b9546f5'
Cloning into 'roms/qemu-palcode'...
Submodule path 'roms/qemu-palcode': checked out '51c237d7e20d05100eacadee2f61abc17e6bc097'
Cloning into 'roms/seabios'...
Submodule path 'roms/seabios': checked out 'a698c8995ffb2838296ec284fe3c4ad33dfca307'
Cloning into 'roms/seabios-hppa'...
Submodule path 'roms/seabios-hppa': checked out '1ef99a01572c2581c30e16e6fe69e9ea2ef92ce0'
Cloning into 'roms/sgabios'...
Submodule path 'roms/sgabios': checked out 'cbaee52287e5f32373181cff50a00b6c4ac9015a'
Cloning into 'roms/skiboot'...
Submodule path 'roms/skiboot': checked out 'e0ee24c27a172bcf482f6f2bc905e6211c134bcc'
Cloning into 'roms/u-boot'...
Submodule path 'roms/u-boot': checked out 'd85ca029f257b53a96da6c2fb421e78a003a9943'
Cloning into 'roms/u-boot-sam460ex'...
Submodule path 'roms/u-boot-sam460ex': checked out '60b3916f33e617a815973c5a6df77055b2e3a588'
Cloning into 'tests/fp/berkeley-softfloat-3'...
Submodule path 'tests/fp/berkeley-softfloat-3': checked out 'b64af41c3276f97f0e181920400ee056b9c88037'
Cloning into 'tests/fp/berkeley-testfloat-3'...
Submodule path 'tests/fp/berkeley-testfloat-3': checked out '5a59dcec19327396a011a17fd924aed4fec416b3'
Cloning into 'ui/keycodemapdb'...
Submodule path 'ui/keycodemapdb': checked out '6b3d716e2b6472eb7189d3220552280ef3d832ce'
Switched to a new branch 'test'
2780519 target/riscv: Remaining rvc insn reuse 32 bit translators
a87e6e3 target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
24bff9f target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
726e1f4 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
9420608 target/riscv: Convert @cs_2 insns to share translation functions
0a0f1b7 target/riscv: Remove decode_RV32_64G()
5c1a51d target/riscv: Remove gen_system()
a68220d target/riscv: Rename trans_arith to gen_arith
c0ff416 target/riscv: Remove manual decoding of RV32/64M insn
aceeea6 target/riscv: Remove shift and slt insn manual decoding
4177aa1 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
31b5b05 target/riscv: Move gen_arith_imm() decoding into trans_* functions
b09a386 target/riscv: Remove manual decoding from gen_store()
4a66d16 target/riscv: Remove manual decoding from gen_load()
1504f31 target/riscv: Remove manual decoding from gen_branch()
3fc86b5 target/riscv: Remove gen_jalr()
862c038 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
dadd6fd target/riscv: Convert quadrant 1 of RVXC insns to decodetree
bbbd541 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
22275dc target/riscv: Convert RV priv insns to decodetree
6bd6eba target/riscv: Convert RV64D insns to decodetree
ae069ba target/riscv: Convert RV32D insns to decodetree
1589e74 target/riscv: Convert RV64F insns to decodetree
8857eb3 target/riscv: Convert RV32F insns to decodetree
b9b3a0b target/riscv: Convert RV64A insns to decodetree
098d10b target/riscv: Convert RV32A insns to decodetree
a23ebbb target/riscv: Convert RVXM insns to decodetree
11f193d target/riscv: Convert RVXI csr insns to decodetree
65c828a target/riscv: Convert RVXI fence insns to decodetree
c99c1e3 target/riscv: Convert RVXI arithmetic insns to decodetree
1629aa4 target/riscv: Convert RV64I load/store insns to decodetree
49279f7 target/riscv: Convert RV32I load/store insns to decodetree
4af4026 target/riscv: Convert RVXI branch insns to decodetree
9ea6816 target/riscv: Activate decodetree and implemnt LUI & AUIPC
9b28c37 target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit 9b28c3765893 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 9ea68168149f (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#33: 
new file mode 100644

ERROR: externs should be avoided in .c files
#124: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit 4af4026ba501 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 49279f7f055e (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 1629aa4d6ed2 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#38: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit c99c1e3a7803 (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 65c828ac4004 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 11f193d69175 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit a23ebbba2fe1 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#47: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 098d10b6b754 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#53: 
new file mode 100644

total: 0 errors, 1 warnings, 188 lines checked

Patch 10/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit b9b3a0b782df (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 8857eb324d81 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#77: 
new file mode 100644

total: 0 errors, 1 warnings, 397 lines checked

Patch 12/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 1589e74dbfc1 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit ae069ba72242 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#50: 
new file mode 100644

total: 0 errors, 1 warnings, 353 lines checked

Patch 14/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 6bd6eba7131e (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 22275dc23a4d (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#40: 
new file mode 100644

total: 0 errors, 1 warnings, 214 lines checked

Patch 16/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit bbbd541526d7 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#30: 
new file mode 100644

ERROR: externs should be avoided in .c files
#245: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);

total: 1 errors, 1 warnings, 227 lines checked

Patch 17/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

18/35 Checking commit dadd6fd1cff0 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 862c038e96e5 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 3fc86b57189a (target/riscv: Remove gen_jalr())
21/35 Checking commit 1504f31cfb10 (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 4a66d1683e0d (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit b09a3864104f (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit 31b5b053d0b4 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit 4177aa12cb00 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit aceeea694040 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit c0ff41680ca5 (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit a68220d0d81f (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 5c1a51d989de (target/riscv: Remove gen_system())
30/35 Checking commit 0a0f1b73365b (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 9420608fc4c4 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41: 
new file mode 100644

ERROR: externs should be avoided in .c files
#181: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);

total: 1 errors, 1 warnings, 164 lines checked

Patch 31/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

32/35 Checking commit 726e1f43c1ae (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 24bff9f4baf8 (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#27: 
new file mode 100644

total: 0 errors, 1 warnings, 287 lines checked

Patch 33/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit a87e6e35fb57 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit 278051918fff (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20190123092538.8004-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com

Patchew URL: https://patchew.org/QEMU/20190123092538.8004-1-kbastian@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v6 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190123092538.8004-1-kbastian@mail.uni-paderborn.de

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
a6f2515ae7 target/riscv: Remaining rvc insn reuse 32 bit translators
93fb3eb825 target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
5ef563612b target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
9dd8991561 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
953afe2701 target/riscv: Convert @cs_2 insns to share translation functions
0bceda7177 target/riscv: Remove decode_RV32_64G()
940985f42b target/riscv: Remove gen_system()
bb4e34c120 target/riscv: Rename trans_arith to gen_arith
4427b58cf1 target/riscv: Remove manual decoding of RV32/64M insn
8e1e88f2ab target/riscv: Remove shift and slt insn manual decoding
afe60ebe74 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
4d43443e2d target/riscv: Move gen_arith_imm() decoding into trans_* functions
de56786c84 target/riscv: Remove manual decoding from gen_store()
4fc18f5eb2 target/riscv: Remove manual decoding from gen_load()
66425abdcd target/riscv: Remove manual decoding from gen_branch()
4ca0a5af54 target/riscv: Remove gen_jalr()
19988a3346 target/riscv: Convert quadrant 2 of RVXC insns to decodetree
a7aded6fd3 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
fd3e32e7e8 target/riscv: Convert quadrant 0 of RVXC insns to decodetree
a56aa5a849 target/riscv: Convert RV priv insns to decodetree
c2b742260a target/riscv: Convert RV64D insns to decodetree
7c715e34ff target/riscv: Convert RV32D insns to decodetree
556d60b104 target/riscv: Convert RV64F insns to decodetree
7f43f5d073 target/riscv: Convert RV32F insns to decodetree
be015ccb8b target/riscv: Convert RV64A insns to decodetree
7bc964b2c5 target/riscv: Convert RV32A insns to decodetree
24b2b53919 target/riscv: Convert RVXM insns to decodetree
fcc4af623a target/riscv: Convert RVXI csr insns to decodetree
a2d032d8b4 target/riscv: Convert RVXI fence insns to decodetree
609b7bd70a target/riscv: Convert RVXI arithmetic insns to decodetree
8cd785fa06 target/riscv: Convert RV64I load/store insns to decodetree
0769f03796 target/riscv: Convert RV32I load/store insns to decodetree
3a1daf706a target/riscv: Convert RVXI branch insns to decodetree
a351b2d421 target/riscv: Activate decodetree and implemnt LUI & AUIPC
6d6ac91f67 target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit 6d6ac91f67ff (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit a351b2d4210b (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#33: 
new file mode 100644

ERROR: externs should be avoided in .c files
#124: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit 3a1daf706aa1 (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit 0769f037965c (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit 8cd785fa0678 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#38: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 609b7bd70a36 (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit a2d032d8b47f (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit fcc4af623a98 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit 24b2b5391954 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#47: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 7bc964b2c549 (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#53: 
new file mode 100644

total: 0 errors, 1 warnings, 188 lines checked

Patch 10/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit be015ccb8b64 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 7f43f5d07372 (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#77: 
new file mode 100644

total: 0 errors, 1 warnings, 397 lines checked

Patch 12/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit 556d60b104a3 (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 7c715e34ff54 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#50: 
new file mode 100644

total: 0 errors, 1 warnings, 353 lines checked

Patch 14/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit c2b742260a63 (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit a56aa5a84908 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#40: 
new file mode 100644

total: 0 errors, 1 warnings, 214 lines checked

Patch 16/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit fd3e32e7e801 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#30: 
new file mode 100644

ERROR: externs should be avoided in .c files
#245: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);

total: 1 errors, 1 warnings, 227 lines checked

Patch 17/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

18/35 Checking commit a7aded6fd326 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 19988a334621 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 4ca0a5af54a0 (target/riscv: Remove gen_jalr())
21/35 Checking commit 66425abdcddc (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit 4fc18f5eb222 (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit de56786c8435 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit 4d43443e2d92 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit afe60ebe74d0 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 8e1e88f2ab38 (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit 4427b58cf10d (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit bb4e34c120a3 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 940985f42bd3 (target/riscv: Remove gen_system())
30/35 Checking commit 0bceda71773b (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 953afe2701e0 (target/riscv: Convert @cs_2 insns to share translation functions)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41: 
new file mode 100644

ERROR: externs should be avoided in .c files
#181: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);

total: 1 errors, 1 warnings, 164 lines checked

Patch 31/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

32/35 Checking commit 9dd899156136 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 5ef563612bba (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#27: 
new file mode 100644

total: 0 errors, 1 warnings, 287 lines checked

Patch 33/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit 93fb3eb8256e (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit a6f2515ae7e6 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20190123092538.8004-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
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