[Qemu-devel] [PULL v2 00/48] target-arm queue
[PULL v2 00/57] target-arm queue
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v1->v2 changes: fix a clang warning about bitfields;
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Squashed in a trivial fix for 32-bit hosts:
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drop a patch from Julia that I accidentally included
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(it will likely be in a future series).
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The following changes since commit a8d2b0685681e2f291faaa501efbbd76875f8ec8:
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--- a/target/arm/mve_helper.c
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+++ b/target/arm/mve_helper.c
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@@ -XXX,XX +XXX,XX @@ DO_LDAV(vmlsldavxsw, 4, int32_t, true, +=, -=)
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acc = EVENACC(acc, TO128(n[H##ESIZE(e + 1 * XCHG)] * \
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m[H##ESIZE(e)])); \
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} \
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- acc = int128_add(acc, 1 << 7); \
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+ acc = int128_add(acc, int128_make64(1 << 7)); \
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} \
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} \
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mve_advance_vpt(env); \
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Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190118' into staging (2019-01-18 16:56:15 +0000)
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-- PMM
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The following changes since commit 53f306f316549d20c76886903181413d20842423:
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Merge remote-tracking branch 'remotes/ehabkost-gl/tags/x86-next-pull-request' into staging (2021-06-21 11:26:04 +0100)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190121
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210624
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for you to fetch changes up to 0d4bfd7df809863b1f45fad35229fb9419527d06:
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for you to fetch changes up to 90a76c6316cfe6416fc33814a838fb3928f746ee:
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target/arm: Implement PMSWINC (2019-01-21 10:38:56 +0000)
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docs/system: arm: Add nRF boards description (2021-06-24 14:58:48 +0100)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* hw/char/stm32f2xx_usart: Do not update data register when device is disabled
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* Don't require 'virt' board to be compiled in for ACPI GHES code
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* hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node
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* docs: Document which architecture extensions we emulate
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* target/arm: Allow Aarch32 exception return to switch from Mon->Hyp
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* Fix bugs in M-profile FPCXT_NS accesses
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* ftgmac100: implement the new MDIO interface on Aspeed SoC
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* First slice of MVE patches
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* implement the ARMv8.3-PAuth extension
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* Implement MTE3
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* improve emulation of the ARM PMU
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* docs/system: arm: Add nRF boards description
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----------------------------------------------------------------
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----------------------------------------------------------------
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Aaron Lindsay (13):
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Alexandre Iooss (1):
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migration: Add post_save function to VMStateDescription
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docs/system: arm: Add nRF boards description
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target/arm: Reorganize PMCCNTR accesses
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target/arm: Swap PMU values before/after migrations
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target/arm: Filter cycle counter based on PMCCFILTR_EL0
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target/arm: Allow AArch32 access for PMCCFILTR
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target/arm: Implement PMOVSSET
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target/arm: Define FIELDs for ID_DFR0
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target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23]
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target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0
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target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER
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target/arm: PMU: Add instruction and cycle events
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target/arm: PMU: Set PMCR.N to 4
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target/arm: Implement PMSWINC
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Alexander Graf (1):
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Peter Collingbourne (1):
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target/arm: Allow Aarch32 exception return to switch from Mon->Hyp
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target/arm: Implement MTE3
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Cédric Le Goater (1):
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Peter Maydell (55):
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ftgmac100: implement the new MDIO interface on Aspeed SoC
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hw/acpi: Provide stub version of acpi_ghes_record_errors()
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hw/acpi: Provide function acpi_ghes_present()
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target/arm: Use acpi_ghes_present() to see if we report ACPI memory errors
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docs/system/arm: Document which architecture extensions we emulate
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target/arm/translate-vfp.c: Whitespace fixes
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target/arm: Handle FPU being disabled in FPCXT_NS accesses
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target/arm: Don't NOCP fault for FPCXT_NS accesses
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target/arm: Handle writeback in VLDR/VSTR sysreg with no memory access
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target/arm: Factor FP context update code out into helper function
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target/arm: Split vfp_access_check() into A and M versions
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target/arm: Handle FPU check for FPCXT_NS insns via vfp_access_check_m()
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target/arm: Implement MVE VLDR/VSTR (non-widening forms)
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target/arm: Implement widening/narrowing MVE VLDR/VSTR insns
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target/arm: Implement MVE VCLZ
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target/arm: Implement MVE VCLS
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target/arm: Implement MVE VREV16, VREV32, VREV64
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target/arm: Implement MVE VMVN (register)
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target/arm: Implement MVE VABS
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target/arm: Implement MVE VNEG
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tcg: Make gen_dup_i32/i64() public as tcg_gen_dup_i32/i64
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target/arm: Implement MVE VDUP
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target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR
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target/arm: Implement MVE VADD, VSUB, VMUL
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target/arm: Implement MVE VMULH
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target/arm: Implement MVE VRMULH
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target/arm: Implement MVE VMAX, VMIN
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target/arm: Implement MVE VABD
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target/arm: Implement MVE VHADD, VHSUB
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target/arm: Implement MVE VMULL
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target/arm: Implement MVE VMLALDAV
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target/arm: Implement MVE VMLSLDAV
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target/arm: Implement MVE VRMLALDAVH, VRMLSLDAVH
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target/arm: Implement MVE VADD (scalar)
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target/arm: Implement MVE VSUB, VMUL (scalar)
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target/arm: Implement MVE VHADD, VHSUB (scalar)
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target/arm: Implement MVE VBRSR
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target/arm: Implement MVE VPST
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target/arm: Implement MVE VQADD and VQSUB
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target/arm: Implement MVE VQDMULH and VQRDMULH (scalar)
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target/arm: Implement MVE VQDMULL scalar
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target/arm: Implement MVE VQDMULH, VQRDMULH (vector)
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target/arm: Implement MVE VQADD, VQSUB (vector)
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target/arm: Implement MVE VQSHL (vector)
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target/arm: Implement MVE VQRSHL
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target/arm: Implement MVE VSHL insn
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target/arm: Implement MVE VRSHL
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target/arm: Implement MVE VQDMLADH and VQRDMLADH
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target/arm: Implement MVE VQDMLSDH and VQRDMLSDH
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target/arm: Implement MVE VQDMULL (vector)
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target/arm: Implement MVE VRHADD
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target/arm: Implement MVE VADC, VSBC
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target/arm: Implement MVE VCADD
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target/arm: Implement MVE VHCADD
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target/arm: Implement MVE VADDV
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target/arm: Make VMOV scalar <-> gpreg beatwise for MVE
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Eric Auger (1):
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docs/system/arm/emulation.rst | 103 ++++
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hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node
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docs/system/arm/nrf.rst | 51 ++
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docs/system/target-arm.rst | 7 +
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include/hw/acpi/ghes.h | 9 +
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include/tcg/tcg-op.h | 8 +
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include/tcg/tcg.h | 1 -
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target/arm/helper-mve.h | 357 +++++++++++++
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target/arm/helper.h | 2 +
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target/arm/internals.h | 11 +
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target/arm/translate-a32.h | 3 +
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target/arm/translate.h | 10 +
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target/arm/m-nocp.decode | 24 +
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target/arm/mve.decode | 240 +++++++++
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target/arm/vfp.decode | 14 -
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hw/acpi/ghes-stub.c | 22 +
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hw/acpi/ghes.c | 17 +
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target/arm/cpu64.c | 2 +-
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target/arm/kvm64.c | 6 +-
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target/arm/mte_helper.c | 82 +--
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target/arm/mve_helper.c | 1160 +++++++++++++++++++++++++++++++++++++++++
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target/arm/translate-m-nocp.c | 550 +++++++++++++++++++
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target/arm/translate-mve.c | 759 +++++++++++++++++++++++++++
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target/arm/translate-vfp.c | 741 +++++++-------------------
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tcg/tcg-op-gvec.c | 20 +-
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MAINTAINERS | 1 +
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hw/acpi/meson.build | 6 +-
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target/arm/meson.build | 1 +
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27 files changed, 3578 insertions(+), 629 deletions(-)
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create mode 100644 docs/system/arm/emulation.rst
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create mode 100644 docs/system/arm/nrf.rst
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create mode 100644 target/arm/helper-mve.h
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create mode 100644 hw/acpi/ghes-stub.c
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create mode 100644 target/arm/mve_helper.c
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135
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Philippe Mathieu-Daudé (1):
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hw/char/stm32f2xx_usart: Do not update data register when device is disabled
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Richard Henderson (31):
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target/arm: Add state for the ARMv8.3-PAuth extension
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target/arm: Add SCTLR bits through ARMv8.5
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target/arm: Add PAuth active bit to tbflags
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target/arm: Introduce raise_exception_ra
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target/arm: Add PAuth helpers
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target/arm: Decode PAuth within system hint space
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target/arm: Rearrange decode in disas_data_proc_1src
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target/arm: Decode PAuth within disas_data_proc_1src
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target/arm: Decode PAuth within disas_data_proc_2src
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target/arm: Move helper_exception_return to helper-a64.c
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target/arm: Add new_pc argument to helper_exception_return
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target/arm: Rearrange decode in disas_uncond_b_reg
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target/arm: Decode PAuth within disas_uncond_b_reg
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target/arm: Decode Load/store register (pac)
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target/arm: Move cpu_mmu_index out of line
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target/arm: Introduce arm_mmu_idx
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target/arm: Introduce arm_stage1_mmu_idx
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target/arm: Create ARMVAParameters and helpers
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target/arm: Merge TBFLAG_AA_TB{0, 1} to TBII
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target/arm: Export aa64_va_parameters to internals.h
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target/arm: Add aa64_va_parameters_both
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target/arm: Decode TBID from TCR
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target/arm: Reuse aa64_va_parameters for setting tbflags
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target/arm: Implement pauth_strip
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target/arm: Implement pauth_auth
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target/arm: Implement pauth_addpac
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target/arm: Implement pauth_computepac
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target/arm: Add PAuth system registers
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target/arm: Enable PAuth for -cpu max
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target/arm: Enable PAuth for user-only
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target/arm: Tidy TBI handling in gen_a64_set_pc
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target/arm/Makefile.objs | 1 +
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include/hw/acpi/acpi-defs.h | 2 +
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include/migration/vmstate.h | 1 +
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target/arm/cpu.h | 244 +++++----
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target/arm/helper-a64.h | 14 +
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target/arm/helper.h | 1 -
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target/arm/internals.h | 77 +++
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target/arm/translate.h | 5 +-
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hw/arm/virt-acpi-build.c | 1 +
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hw/char/stm32f2xx_usart.c | 3 +-
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hw/net/ftgmac100.c | 80 ++-
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migration/vmstate.c | 13 +-
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target/arm/cpu.c | 19 +-
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target/arm/cpu64.c | 68 ++-
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target/arm/helper-a64.c | 155 ++++++
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target/arm/helper.c | 1222 +++++++++++++++++++++++++++++++++----------
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target/arm/machine.c | 24 +
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target/arm/op_helper.c | 174 +-----
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target/arm/pauth_helper.c | 497 ++++++++++++++++++
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target/arm/translate-a64.c | 537 ++++++++++++++++---
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docs/devel/migration.rst | 9 +-
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21 files changed, 2515 insertions(+), 632 deletions(-)
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create mode 100644 target/arm/pauth_helper.c
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