[Qemu-devel] [PULL v2 00/48] target-arm queue
[PULL v2 00/29] target-arm queue
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v1->v2 changes: fix a clang warning about bitfields;
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v2: drop pvpanic-pci patches.
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drop a patch from Julia that I accidentally included
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(it will likely be in a future series).
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The following changes since commit a8d2b0685681e2f291faaa501efbbd76875f8ec8:
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The following changes since commit f1fcb6851aba6dd9838886dc179717a11e344a1c:
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Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20190118' into staging (2019-01-18 16:56:15 +0000)
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Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2021-01-19' into staging (2021-01-19 11:57:07 +0000)
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are available in the Git repository at:
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are available in the Git repository at:
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190121
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20210119-1
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for you to fetch changes up to 0d4bfd7df809863b1f45fad35229fb9419527d06:
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for you to fetch changes up to b93f4fbdc48283a39089469c44a5529d79dc40a8:
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target/arm: Implement PMSWINC (2019-01-21 10:38:56 +0000)
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docs: Build and install all the docs in a single manual (2021-01-19 15:45:14 +0000)
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----------------------------------------------------------------
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----------------------------------------------------------------
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target-arm queue:
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target-arm queue:
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* hw/char/stm32f2xx_usart: Do not update data register when device is disabled
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* Implement IMPDEF pauth algorithm
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* hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node
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* Support ARMv8.4-SEL2
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* target/arm: Allow Aarch32 exception return to switch from Mon->Hyp
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* Fix bug where we were truncating predicate vector lengths in SVE insns
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* ftgmac100: implement the new MDIO interface on Aspeed SoC
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* npcm7xx_adc-test: Fix memleak in adc_qom_set
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* implement the ARMv8.3-PAuth extension
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* target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
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* improve emulation of the ARM PMU
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* docs: Build and install all the docs in a single manual
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----------------------------------------------------------------
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----------------------------------------------------------------
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Aaron Lindsay (13):
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Gan Qixin (1):
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migration: Add post_save function to VMStateDescription
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npcm7xx_adc-test: Fix memleak in adc_qom_set
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target/arm: Reorganize PMCCNTR accesses
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target/arm: Swap PMU values before/after migrations
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target/arm: Filter cycle counter based on PMCCFILTR_EL0
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target/arm: Allow AArch32 access for PMCCFILTR
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target/arm: Implement PMOVSSET
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target/arm: Define FIELDs for ID_DFR0
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target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23]
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target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0
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target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER
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target/arm: PMU: Add instruction and cycle events
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target/arm: PMU: Set PMCR.N to 4
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target/arm: Implement PMSWINC
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Alexander Graf (1):
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Peter Maydell (1):
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target/arm: Allow Aarch32 exception return to switch from Mon->Hyp
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docs: Build and install all the docs in a single manual
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Cédric Le Goater (1):
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ftgmac100: implement the new MDIO interface on Aspeed SoC
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Eric Auger (1):
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hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node
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Philippe Mathieu-Daudé (1):
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Philippe Mathieu-Daudé (1):
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hw/char/stm32f2xx_usart: Do not update data register when device is disabled
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target/arm/m_helper: Silence GCC 10 maybe-uninitialized error
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Richard Henderson (31):
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Richard Henderson (7):
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target/arm: Add state for the ARMv8.3-PAuth extension
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target/arm: Implement an IMPDEF pauth algorithm
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target/arm: Add SCTLR bits through ARMv8.5
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target/arm: Add cpu properties to control pauth
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target/arm: Add PAuth active bit to tbflags
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target/arm: Use object_property_add_bool for "sve" property
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target/arm: Introduce raise_exception_ra
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target/arm: Introduce PREDDESC field definitions
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target/arm: Add PAuth helpers
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target/arm: Update PFIRST, PNEXT for pred_desc
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target/arm: Decode PAuth within system hint space
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target/arm: Update ZIP, UZP, TRN for pred_desc
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target/arm: Rearrange decode in disas_data_proc_1src
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target/arm: Update REV, PUNPK for pred_desc
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target/arm: Decode PAuth within disas_data_proc_1src
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target/arm: Decode PAuth within disas_data_proc_2src
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target/arm: Move helper_exception_return to helper-a64.c
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target/arm: Add new_pc argument to helper_exception_return
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target/arm: Rearrange decode in disas_uncond_b_reg
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target/arm: Decode PAuth within disas_uncond_b_reg
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target/arm: Decode Load/store register (pac)
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target/arm: Move cpu_mmu_index out of line
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target/arm: Introduce arm_mmu_idx
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target/arm: Introduce arm_stage1_mmu_idx
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target/arm: Create ARMVAParameters and helpers
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target/arm: Merge TBFLAG_AA_TB{0, 1} to TBII
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target/arm: Export aa64_va_parameters to internals.h
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target/arm: Add aa64_va_parameters_both
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target/arm: Decode TBID from TCR
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target/arm: Reuse aa64_va_parameters for setting tbflags
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target/arm: Implement pauth_strip
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target/arm: Implement pauth_auth
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target/arm: Implement pauth_addpac
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target/arm: Implement pauth_computepac
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target/arm: Add PAuth system registers
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target/arm: Enable PAuth for -cpu max
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target/arm: Enable PAuth for user-only
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target/arm: Tidy TBI handling in gen_a64_set_pc
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target/arm/Makefile.objs | 1 +
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Rémi Denis-Courmont (19):
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include/hw/acpi/acpi-defs.h | 2 +
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target/arm: remove redundant tests
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include/migration/vmstate.h | 1 +
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target/arm: add arm_is_el2_enabled() helper
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target/arm/cpu.h | 244 +++++----
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target/arm: use arm_is_el2_enabled() where applicable
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target/arm/helper-a64.h | 14 +
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target/arm: use arm_hcr_el2_eff() where applicable
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target/arm/helper.h | 1 -
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target/arm: factor MDCR_EL2 common handling
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target/arm/internals.h | 77 +++
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target/arm: Define isar_feature function to test for presence of SEL2
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target/arm/translate.h | 5 +-
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target/arm: add 64-bit S-EL2 to EL exception table
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hw/arm/virt-acpi-build.c | 1 +
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target/arm: add MMU stage 1 for Secure EL2
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hw/char/stm32f2xx_usart.c | 3 +-
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target/arm: add ARMv8.4-SEL2 system registers
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hw/net/ftgmac100.c | 80 ++-
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target/arm: handle VMID change in secure state
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migration/vmstate.c | 13 +-
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target/arm: do S1_ptw_translate() before address space lookup
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target/arm/cpu.c | 19 +-
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target/arm: translate NS bit in page-walks
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target/arm/cpu64.c | 68 ++-
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target/arm: generalize 2-stage page-walk condition
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target/arm/helper-a64.c | 155 ++++++
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target/arm: secure stage 2 translation regime
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target/arm/helper.c | 1222 +++++++++++++++++++++++++++++++++----------
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target/arm: set HPFAR_EL2.NS on secure stage 2 faults
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target/arm/machine.c | 24 +
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target/arm: revector to run-time pick target EL
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target/arm/op_helper.c | 174 +-----
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target/arm: Implement SCR_EL2.EEL2
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target/arm/pauth_helper.c | 497 ++++++++++++++++++
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target/arm: enable Secure EL2 in max CPU
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target/arm/translate-a64.c | 537 ++++++++++++++++---
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target/arm: refactor vae1_tlbmask()
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docs/devel/migration.rst | 9 +-
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21 files changed, 2515 insertions(+), 632 deletions(-)
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create mode 100644 target/arm/pauth_helper.c
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docs/conf.py | 46 ++++-
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docs/devel/conf.py | 15 --
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docs/index.html.in | 17 --
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docs/interop/conf.py | 28 ---
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docs/meson.build | 64 +++---
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docs/specs/conf.py | 16 --
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docs/system/arm/cpu-features.rst | 21 ++
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docs/system/conf.py | 28 ---
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docs/tools/conf.py | 37 ----
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docs/user/conf.py | 15 --
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include/qemu/xxhash.h | 98 +++++++++
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target/arm/cpu-param.h | 2 +-
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target/arm/cpu.h | 107 ++++++++--
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target/arm/internals.h | 45 +++++
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target/arm/cpu.c | 23 ++-
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target/arm/cpu64.c | 65 ++++--
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target/arm/helper-a64.c | 8 +-
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target/arm/helper.c | 414 ++++++++++++++++++++++++++-------------
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target/arm/m_helper.c | 2 +-
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target/arm/monitor.c | 1 +
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target/arm/op_helper.c | 4 +-
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target/arm/pauth_helper.c | 27 ++-
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target/arm/sve_helper.c | 33 ++--
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target/arm/tlb_helper.c | 3 +
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target/arm/translate-a64.c | 4 +
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target/arm/translate-sve.c | 31 ++-
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target/arm/translate.c | 36 +++-
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tests/qtest/arm-cpu-features.c | 13 ++
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tests/qtest/npcm7xx_adc-test.c | 1 +
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.gitlab-ci.yml | 4 +-
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30 files changed, 770 insertions(+), 438 deletions(-)
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delete mode 100644 docs/devel/conf.py
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delete mode 100644 docs/index.html.in
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delete mode 100644 docs/interop/conf.py
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delete mode 100644 docs/specs/conf.py
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delete mode 100644 docs/system/conf.py
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delete mode 100644 docs/tools/conf.py
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delete mode 100644 docs/user/conf.py
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