[Qemu-devel] [PULL 00/49] target-arm queue
[PULL 00/72] target-arm queue
1
A largish pull request: the big things are Richard's PAuth work
1
First arm pullreq of the cycle; this is mostly my softfloat NaN
2
and Aaron's PMU emulation improvements.
2
handling series. (Lots more in my to-review queue, but I don't
3
like pullreqs growing too close to a hundred patches at a time :-))
3
4
4
thanks
5
thanks
5
-- PMM
6
-- PMM
6
7
8
The following changes since commit 97f2796a3736ed37a1b85dc1c76a6c45b829dd17:
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The following changes since commit 681d61362d3f766a00806b89d6581869041f73cb:
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Open 10.0 development tree (2024-12-10 17:41:17 +0000)
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10
Merge remote-tracking branch 'remotes/jnsnow/tags/bitmaps-pull-request' into staging (2019-01-17 12:48:42 +0000)
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are available in the Git repository at:
12
are available in the Git repository at:
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13
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190118
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https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20241211
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15
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for you to fetch changes up to 2a0ed2804e2c77a1c4e255f05ab739618e05c85d:
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for you to fetch changes up to 1abe28d519239eea5cf9620bb13149423e5665f8:
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17
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tests/libqtest: Introduce qtest_init_with_serial() (2019-01-18 14:17:38 +0000)
18
MAINTAINERS: Add correct email address for Vikram Garhwal (2024-12-11 15:31:09 +0000)
19
19
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----------------------------------------------------------------
20
----------------------------------------------------------------
21
target-arm queue:
21
target-arm queue:
22
* hw/char/stm32f2xx_usart: Do not update data register when device is disabled
22
* hw/net/lan9118: Extract PHY model, reuse with imx_fec, fix bugs
23
* hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node
23
* fpu: Make muladd NaN handling runtime-selected, not compile-time
24
* target/arm: Allow Aarch32 exception return to switch from Mon->Hyp
24
* fpu: Make default NaN pattern runtime-selected, not compile-time
25
* ftgmac100: implement the new MDIO interface on Aspeed SoC
25
* fpu: Minor NaN-related cleanups
26
* implement the ARMv8.3-PAuth extension
26
* MAINTAINERS: email address updates
27
* improve emulation of the ARM PMU
28
27
29
----------------------------------------------------------------
28
----------------------------------------------------------------
30
Aaron Lindsay (13):
29
Bernhard Beschow (5):
31
migration: Add post_save function to VMStateDescription
30
hw/net/lan9118: Extract lan9118_phy
32
target/arm: Reorganize PMCCNTR accesses
31
hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations
33
target/arm: Swap PMU values before/after migrations
32
hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register
34
target/arm: Filter cycle counter based on PMCCFILTR_EL0
33
hw/net/lan9118_phy: Reuse MII constants
35
target/arm: Allow AArch32 access for PMCCFILTR
34
hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement
36
target/arm: Implement PMOVSSET
37
target/arm: Define FIELDs for ID_DFR0
38
target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23]
39
target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0
40
target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER
41
target/arm: PMU: Add instruction and cycle events
42
target/arm: PMU: Set PMCR.N to 4
43
target/arm: Implement PMSWINC
44
35
45
Alexander Graf (1):
36
Leif Lindholm (1):
46
target/arm: Allow Aarch32 exception return to switch from Mon->Hyp
37
MAINTAINERS: update email address for Leif Lindholm
47
38
48
Cédric Le Goater (1):
39
Peter Maydell (54):
49
ftgmac100: implement the new MDIO interface on Aspeed SoC
40
fpu: handle raising Invalid for infzero in pick_nan_muladd
41
fpu: Check for default_nan_mode before calling pickNaNMulAdd
42
softfloat: Allow runtime choice of inf * 0 + NaN result
43
tests/fp: Explicitly set inf-zero-nan rule
44
target/arm: Set FloatInfZeroNaNRule explicitly
45
target/s390: Set FloatInfZeroNaNRule explicitly
46
target/ppc: Set FloatInfZeroNaNRule explicitly
47
target/mips: Set FloatInfZeroNaNRule explicitly
48
target/sparc: Set FloatInfZeroNaNRule explicitly
49
target/xtensa: Set FloatInfZeroNaNRule explicitly
50
target/x86: Set FloatInfZeroNaNRule explicitly
51
target/loongarch: Set FloatInfZeroNaNRule explicitly
52
target/hppa: Set FloatInfZeroNaNRule explicitly
53
softfloat: Pass have_snan to pickNaNMulAdd
54
softfloat: Allow runtime choice of NaN propagation for muladd
55
tests/fp: Explicitly set 3-NaN propagation rule
56
target/arm: Set Float3NaNPropRule explicitly
57
target/loongarch: Set Float3NaNPropRule explicitly
58
target/ppc: Set Float3NaNPropRule explicitly
59
target/s390x: Set Float3NaNPropRule explicitly
60
target/sparc: Set Float3NaNPropRule explicitly
61
target/mips: Set Float3NaNPropRule explicitly
62
target/xtensa: Set Float3NaNPropRule explicitly
63
target/i386: Set Float3NaNPropRule explicitly
64
target/hppa: Set Float3NaNPropRule explicitly
65
fpu: Remove use_first_nan field from float_status
66
target/m68k: Don't pass NULL float_status to floatx80_default_nan()
67
softfloat: Create floatx80 default NaN from parts64_default_nan
68
target/loongarch: Use normal float_status in fclass_s and fclass_d helpers
69
target/m68k: In frem helper, initialize local float_status from env->fp_status
70
target/m68k: Init local float_status from env fp_status in gdb get/set reg
71
target/sparc: Initialize local scratch float_status from env->fp_status
72
target/ppc: Use env->fp_status in helper_compute_fprf functions
73
fpu: Allow runtime choice of default NaN value
74
tests/fp: Set default NaN pattern explicitly
75
target/microblaze: Set default NaN pattern explicitly
76
target/i386: Set default NaN pattern explicitly
77
target/hppa: Set default NaN pattern explicitly
78
target/alpha: Set default NaN pattern explicitly
79
target/arm: Set default NaN pattern explicitly
80
target/loongarch: Set default NaN pattern explicitly
81
target/m68k: Set default NaN pattern explicitly
82
target/mips: Set default NaN pattern explicitly
83
target/openrisc: Set default NaN pattern explicitly
84
target/ppc: Set default NaN pattern explicitly
85
target/sh4: Set default NaN pattern explicitly
86
target/rx: Set default NaN pattern explicitly
87
target/s390x: Set default NaN pattern explicitly
88
target/sparc: Set default NaN pattern explicitly
89
target/xtensa: Set default NaN pattern explicitly
90
target/hexagon: Set default NaN pattern explicitly
91
target/riscv: Set default NaN pattern explicitly
92
target/tricore: Set default NaN pattern explicitly
93
fpu: Remove default handling for dnan_pattern
50
94
51
Eric Auger (1):
95
Richard Henderson (11):
52
hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node
96
target/arm: Copy entire float_status in is_ebf
97
softfloat: Inline pickNaNMulAdd
98
softfloat: Use goto for default nan case in pick_nan_muladd
99
softfloat: Remove which from parts_pick_nan_muladd
100
softfloat: Pad array size in pick_nan_muladd
101
softfloat: Move propagateFloatx80NaN to softfloat.c
102
softfloat: Use parts_pick_nan in propagateFloatx80NaN
103
softfloat: Inline pickNaN
104
softfloat: Share code between parts_pick_nan cases
105
softfloat: Sink frac_cmp in parts_pick_nan until needed
106
softfloat: Replace WHICH with RET in parts_pick_nan
53
107
54
Julia Suvorova (1):
108
Vikram Garhwal (1):
55
tests/libqtest: Introduce qtest_init_with_serial()
109
MAINTAINERS: Add correct email address for Vikram Garhwal
56
110
57
Philippe Mathieu-Daudé (1):
111
MAINTAINERS | 4 +-
58
hw/char/stm32f2xx_usart: Do not update data register when device is disabled
112
include/fpu/softfloat-helpers.h | 38 +++-
59
113
include/fpu/softfloat-types.h | 89 +++++++-
60
Richard Henderson (31):
114
include/hw/net/imx_fec.h | 9 +-
61
target/arm: Add state for the ARMv8.3-PAuth extension
115
include/hw/net/lan9118_phy.h | 37 ++++
62
target/arm: Add SCTLR bits through ARMv8.5
116
include/hw/net/mii.h | 6 +
63
target/arm: Add PAuth active bit to tbflags
117
target/mips/fpu_helper.h | 20 ++
64
target/arm: Introduce raise_exception_ra
118
target/sparc/helper.h | 4 +-
65
target/arm: Add PAuth helpers
119
fpu/softfloat.c | 19 ++
66
target/arm: Decode PAuth within system hint space
120
hw/net/imx_fec.c | 146 ++------------
67
target/arm: Rearrange decode in disas_data_proc_1src
121
hw/net/lan9118.c | 137 ++-----------
68
target/arm: Decode PAuth within disas_data_proc_1src
122
hw/net/lan9118_phy.c | 222 ++++++++++++++++++++
69
target/arm: Decode PAuth within disas_data_proc_2src
123
linux-user/arm/nwfpe/fpa11.c | 5 +
70
target/arm: Move helper_exception_return to helper-a64.c
124
target/alpha/cpu.c | 2 +
71
target/arm: Add new_pc argument to helper_exception_return
125
target/arm/cpu.c | 10 +
72
target/arm: Rearrange decode in disas_uncond_b_reg
126
target/arm/tcg/vec_helper.c | 20 +-
73
target/arm: Decode PAuth within disas_uncond_b_reg
127
target/hexagon/cpu.c | 2 +
74
target/arm: Decode Load/store register (pac)
128
target/hppa/fpu_helper.c | 12 ++
75
target/arm: Move cpu_mmu_index out of line
129
target/i386/tcg/fpu_helper.c | 12 ++
76
target/arm: Introduce arm_mmu_idx
130
target/loongarch/tcg/fpu_helper.c | 14 +-
77
target/arm: Introduce arm_stage1_mmu_idx
131
target/m68k/cpu.c | 14 +-
78
target/arm: Create ARMVAParameters and helpers
132
target/m68k/fpu_helper.c | 6 +-
79
target/arm: Merge TBFLAG_AA_TB{0, 1} to TBII
133
target/m68k/helper.c | 6 +-
80
target/arm: Export aa64_va_parameters to internals.h
134
target/microblaze/cpu.c | 2 +
81
target/arm: Add aa64_va_parameters_both
135
target/mips/msa.c | 10 +
82
target/arm: Decode TBID from TCR
136
target/openrisc/cpu.c | 2 +
83
target/arm: Reuse aa64_va_parameters for setting tbflags
137
target/ppc/cpu_init.c | 19 ++
84
target/arm: Implement pauth_strip
138
target/ppc/fpu_helper.c | 3 +-
85
target/arm: Implement pauth_auth
139
target/riscv/cpu.c | 2 +
86
target/arm: Implement pauth_addpac
140
target/rx/cpu.c | 2 +
87
target/arm: Implement pauth_computepac
141
target/s390x/cpu.c | 5 +
88
target/arm: Add PAuth system registers
142
target/sh4/cpu.c | 2 +
89
target/arm: Enable PAuth for -cpu max
143
target/sparc/cpu.c | 6 +
90
target/arm: Enable PAuth for user-only
144
target/sparc/fop_helper.c | 8 +-
91
target/arm: Tidy TBI handling in gen_a64_set_pc
145
target/sparc/translate.c | 4 +-
92
146
target/tricore/helper.c | 2 +
93
target/arm/Makefile.objs | 1 +
147
target/xtensa/cpu.c | 4 +
94
include/hw/acpi/acpi-defs.h | 2 +
148
target/xtensa/fpu_helper.c | 3 +-
95
include/migration/vmstate.h | 1 +
149
tests/fp/fp-bench.c | 7 +
96
target/arm/cpu.h | 244 +++++----
150
tests/fp/fp-test-log2.c | 1 +
97
target/arm/helper-a64.h | 14 +
151
tests/fp/fp-test.c | 7 +
98
target/arm/helper.h | 1 -
152
fpu/softfloat-parts.c.inc | 152 +++++++++++---
99
target/arm/internals.h | 77 +++
153
fpu/softfloat-specialize.c.inc | 412 ++------------------------------------
100
target/arm/translate.h | 5 +-
154
.mailmap | 5 +-
101
tests/libqtest.h | 11 +
155
hw/net/Kconfig | 5 +
102
hw/arm/virt-acpi-build.c | 1 +
156
hw/net/meson.build | 1 +
103
hw/char/stm32f2xx_usart.c | 3 +-
157
hw/net/trace-events | 10 +-
104
hw/net/ftgmac100.c | 80 ++-
158
47 files changed, 778 insertions(+), 730 deletions(-)
105
migration/vmstate.c | 13 +-
159
create mode 100644 include/hw/net/lan9118_phy.h
106
target/arm/cpu.c | 19 +-
160
create mode 100644 hw/net/lan9118_phy.c
107
target/arm/cpu64.c | 68 ++-
108
target/arm/helper-a64.c | 155 ++++++
109
target/arm/helper.c | 1222 +++++++++++++++++++++++++++++++++----------
110
target/arm/machine.c | 24 +
111
target/arm/op_helper.c | 174 +-----
112
target/arm/pauth_helper.c | 497 ++++++++++++++++++
113
target/arm/translate-a64.c | 537 ++++++++++++++++---
114
tests/libqtest.c | 26 +
115
docs/devel/migration.rst | 9 +-
116
23 files changed, 2552 insertions(+), 632 deletions(-)
117
create mode 100644 target/arm/pauth_helper.c
118
diff view generated by jsdifflib
[Qemu-devel] [PULL 27/49] target/arm: Reuse aa64_va_parameters for setting tbflags
[PULL 01/72] hw/net/lan9118: Extract lan9118_phy
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
The arm_regime_tbi{0,1} functions are replacable with the new function
3
A very similar implementation of the same device exists in imx_fec. Prepare for
4
by giving the lowest and highest address.
4
a common implementation by extracting a device model into its own files.
5
5
6
Some migration state has been moved into the new device model which breaks
7
migration compatibility for the following machines:
8
* smdkc210
9
* realview-*
10
* vexpress-*
11
* kzm
12
* mps2-*
13
14
While breaking migration ABI, fix the size of the MII registers to be 16 bit,
15
as defined by IEEE 802.3u.
16
17
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
18
Tested-by: Guenter Roeck <linux@roeck-us.net>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
20
Message-id: 20241102125724.532843-2-shentey@gmail.com
8
Message-id: 20190108223129.5570-24-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
21
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
22
---
11
target/arm/cpu.h | 35 -----------------------
23
include/hw/net/lan9118_phy.h | 37 ++++++++
12
target/arm/helper.c | 70 ++++++++++++++++-----------------------------
24
hw/net/lan9118.c | 137 +++++-----------------------
13
2 files changed, 24 insertions(+), 81 deletions(-)
25
hw/net/lan9118_phy.c | 169 +++++++++++++++++++++++++++++++++++
26
hw/net/Kconfig | 4 +
27
hw/net/meson.build | 1 +
28
5 files changed, 233 insertions(+), 115 deletions(-)
29
create mode 100644 include/hw/net/lan9118_phy.h
30
create mode 100644 hw/net/lan9118_phy.c
14
31
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
32
diff --git a/include/hw/net/lan9118_phy.h b/include/hw/net/lan9118_phy.h
33
new file mode 100644
34
index XXXXXXX..XXXXXXX
35
--- /dev/null
36
+++ b/include/hw/net/lan9118_phy.h
37
@@ -XXX,XX +XXX,XX @@
38
+/*
39
+ * SMSC LAN9118 PHY emulation
40
+ *
41
+ * Copyright (c) 2009 CodeSourcery, LLC.
42
+ * Written by Paul Brook
43
+ *
44
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
45
+ * See the COPYING file in the top-level directory.
46
+ */
47
+
48
+#ifndef HW_NET_LAN9118_PHY_H
49
+#define HW_NET_LAN9118_PHY_H
50
+
51
+#include "qom/object.h"
52
+#include "hw/sysbus.h"
53
+
54
+#define TYPE_LAN9118_PHY "lan9118-phy"
55
+OBJECT_DECLARE_SIMPLE_TYPE(Lan9118PhyState, LAN9118_PHY)
56
+
57
+typedef struct Lan9118PhyState {
58
+ SysBusDevice parent_obj;
59
+
60
+ uint16_t status;
61
+ uint16_t control;
62
+ uint16_t advertise;
63
+ uint16_t ints;
64
+ uint16_t int_mask;
65
+ qemu_irq irq;
66
+ bool link_down;
67
+} Lan9118PhyState;
68
+
69
+void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down);
70
+void lan9118_phy_reset(Lan9118PhyState *s);
71
+uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg);
72
+void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val);
73
+
74
+#endif
75
diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c
16
index XXXXXXX..XXXXXXX 100644
76
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu.h
77
--- a/hw/net/lan9118.c
18
+++ b/target/arm/cpu.h
78
+++ b/hw/net/lan9118.c
19
@@ -XXX,XX +XXX,XX @@ static inline bool arm_cpu_bswap_data(CPUARMState *env)
79
@@ -XXX,XX +XXX,XX @@
80
#include "net/net.h"
81
#include "net/eth.h"
82
#include "hw/irq.h"
83
+#include "hw/net/lan9118_phy.h"
84
#include "hw/net/lan9118.h"
85
#include "hw/ptimer.h"
86
#include "hw/qdev-properties.h"
87
@@ -XXX,XX +XXX,XX @@ do { printf("lan9118: " fmt , ## __VA_ARGS__); } while (0)
88
#define MAC_CR_RXEN 0x00000004
89
#define MAC_CR_RESERVED 0x7f404213
90
91
-#define PHY_INT_ENERGYON 0x80
92
-#define PHY_INT_AUTONEG_COMPLETE 0x40
93
-#define PHY_INT_FAULT 0x20
94
-#define PHY_INT_DOWN 0x10
95
-#define PHY_INT_AUTONEG_LP 0x08
96
-#define PHY_INT_PARFAULT 0x04
97
-#define PHY_INT_AUTONEG_PAGE 0x02
98
-
99
#define GPT_TIMER_EN 0x20000000
100
101
/*
102
@@ -XXX,XX +XXX,XX @@ struct lan9118_state {
103
uint32_t mac_mii_data;
104
uint32_t mac_flow;
105
106
- uint32_t phy_status;
107
- uint32_t phy_control;
108
- uint32_t phy_advertise;
109
- uint32_t phy_int;
110
- uint32_t phy_int_mask;
111
+ Lan9118PhyState mii;
112
+ IRQState mii_irq;
113
114
int32_t eeprom_writable;
115
uint8_t eeprom[128];
116
@@ -XXX,XX +XXX,XX @@ struct lan9118_state {
117
118
static const VMStateDescription vmstate_lan9118 = {
119
.name = "lan9118",
120
- .version_id = 2,
121
- .minimum_version_id = 1,
122
+ .version_id = 3,
123
+ .minimum_version_id = 3,
124
.fields = (const VMStateField[]) {
125
VMSTATE_PTIMER(timer, lan9118_state),
126
VMSTATE_UINT32(irq_cfg, lan9118_state),
127
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118 = {
128
VMSTATE_UINT32(mac_mii_acc, lan9118_state),
129
VMSTATE_UINT32(mac_mii_data, lan9118_state),
130
VMSTATE_UINT32(mac_flow, lan9118_state),
131
- VMSTATE_UINT32(phy_status, lan9118_state),
132
- VMSTATE_UINT32(phy_control, lan9118_state),
133
- VMSTATE_UINT32(phy_advertise, lan9118_state),
134
- VMSTATE_UINT32(phy_int, lan9118_state),
135
- VMSTATE_UINT32(phy_int_mask, lan9118_state),
136
VMSTATE_INT32(eeprom_writable, lan9118_state),
137
VMSTATE_UINT8_ARRAY(eeprom, lan9118_state, 128),
138
VMSTATE_INT32(tx_fifo_size, lan9118_state),
139
@@ -XXX,XX +XXX,XX @@ static void lan9118_reload_eeprom(lan9118_state *s)
140
lan9118_mac_changed(s);
20
}
141
}
21
#endif
142
22
143
-static void phy_update_irq(lan9118_state *s)
23
-#ifndef CONFIG_USER_ONLY
144
+static void lan9118_update_irq(void *opaque, int n, int level)
24
-/**
145
{
25
- * arm_regime_tbi0:
146
- if (s->phy_int & s->phy_int_mask) {
26
- * @env: CPUARMState
147
+ lan9118_state *s = opaque;
27
- * @mmu_idx: MMU index indicating required translation regime
148
+
28
- *
149
+ if (level) {
29
- * Extracts the TBI0 value from the appropriate TCR for the current EL
150
s->int_sts |= PHY_INT;
30
- *
151
} else {
31
- * Returns: the TBI0 value.
152
s->int_sts &= ~PHY_INT;
32
- */
153
@@ -XXX,XX +XXX,XX @@ static void phy_update_irq(lan9118_state *s)
33
-uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx);
154
lan9118_update(s);
34
-
155
}
35
-/**
156
36
- * arm_regime_tbi1:
157
-static void phy_update_link(lan9118_state *s)
37
- * @env: CPUARMState
38
- * @mmu_idx: MMU index indicating required translation regime
39
- *
40
- * Extracts the TBI1 value from the appropriate TCR for the current EL
41
- *
42
- * Returns: the TBI1 value.
43
- */
44
-uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx);
45
-#else
46
-/* We can't handle tagged addresses properly in user-only mode */
47
-static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx)
48
-{
158
-{
49
- return 0;
159
- /* Autonegotiation status mirrors link status. */
160
- if (qemu_get_queue(s->nic)->link_down) {
161
- s->phy_status &= ~0x0024;
162
- s->phy_int |= PHY_INT_DOWN;
163
- } else {
164
- s->phy_status |= 0x0024;
165
- s->phy_int |= PHY_INT_ENERGYON;
166
- s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
167
- }
168
- phy_update_irq(s);
50
-}
169
-}
51
-
170
-
52
-static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx)
171
static void lan9118_set_link(NetClientState *nc)
172
{
173
- phy_update_link(qemu_get_nic_opaque(nc));
174
-}
175
-
176
-static void phy_reset(lan9118_state *s)
53
-{
177
-{
54
- return 0;
178
- s->phy_status = 0x7809;
55
-}
179
- s->phy_control = 0x3000;
56
-#endif
180
- s->phy_advertise = 0x01e1;
57
-
181
- s->phy_int_mask = 0;
58
void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
182
- s->phy_int = 0;
59
target_ulong *cs_base, uint32_t *flags);
183
- phy_update_link(s);
60
184
+ lan9118_phy_update_link(&LAN9118(qemu_get_nic_opaque(nc))->mii,
61
diff --git a/target/arm/helper.c b/target/arm/helper.c
185
+ nc->link_down);
62
index XXXXXXX..XXXXXXX 100644
63
--- a/target/arm/helper.c
64
+++ b/target/arm/helper.c
65
@@ -XXX,XX +XXX,XX @@ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx)
66
return mmu_idx;
67
}
186
}
68
187
69
-/* Returns TBI0 value for current regime el */
188
static void lan9118_reset(DeviceState *d)
70
-uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx)
189
@@ -XXX,XX +XXX,XX @@ static void lan9118_reset(DeviceState *d)
190
s->read_word_n = 0;
191
s->write_word_n = 0;
192
193
- phy_reset(s);
194
-
195
s->eeprom_writable = 0;
196
lan9118_reload_eeprom(s);
197
}
198
@@ -XXX,XX +XXX,XX @@ static void do_tx_packet(lan9118_state *s)
199
uint32_t status;
200
201
/* FIXME: Honor TX disable, and allow queueing of packets. */
202
- if (s->phy_control & 0x4000) {
203
+ if (s->mii.control & 0x4000) {
204
/* This assumes the receive routine doesn't touch the VLANClient. */
205
qemu_receive_packet(qemu_get_queue(s->nic), s->txp->data, s->txp->len);
206
} else {
207
@@ -XXX,XX +XXX,XX @@ static void tx_fifo_push(lan9118_state *s, uint32_t val)
208
}
209
}
210
211
-static uint32_t do_phy_read(lan9118_state *s, int reg)
71
-{
212
-{
72
- TCR *tcr;
213
- uint32_t val;
73
- uint32_t el;
214
-
74
-
215
- switch (reg) {
75
- /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
216
- case 0: /* Basic Control */
76
- * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
217
- return s->phy_control;
77
- */
218
- case 1: /* Basic Status */
78
- mmu_idx = stage_1_mmu_idx(mmu_idx);
219
- return s->phy_status;
79
-
220
- case 2: /* ID1 */
80
- tcr = regime_tcr(env, mmu_idx);
221
- return 0x0007;
81
- el = regime_el(env, mmu_idx);
222
- case 3: /* ID2 */
82
-
223
- return 0xc0d1;
83
- if (el > 1) {
224
- case 4: /* Auto-neg advertisement */
84
- return extract64(tcr->raw_tcr, 20, 1);
225
- return s->phy_advertise;
85
- } else {
226
- case 5: /* Auto-neg Link Partner Ability */
86
- return extract64(tcr->raw_tcr, 37, 1);
227
- return 0x0f71;
228
- case 6: /* Auto-neg Expansion */
229
- return 1;
230
- /* TODO 17, 18, 27, 29, 30, 31 */
231
- case 29: /* Interrupt source. */
232
- val = s->phy_int;
233
- s->phy_int = 0;
234
- phy_update_irq(s);
235
- return val;
236
- case 30: /* Interrupt mask */
237
- return s->phy_int_mask;
238
- default:
239
- qemu_log_mask(LOG_GUEST_ERROR,
240
- "do_phy_read: PHY read reg %d\n", reg);
241
- return 0;
87
- }
242
- }
88
-}
243
-}
89
-
244
-
90
-/* Returns TBI1 value for current regime el */
245
-static void do_phy_write(lan9118_state *s, int reg, uint32_t val)
91
-uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx)
92
-{
246
-{
93
- TCR *tcr;
247
- switch (reg) {
94
- uint32_t el;
248
- case 0: /* Basic Control */
95
-
249
- if (val & 0x8000) {
96
- /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
250
- phy_reset(s);
97
- * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
251
- break;
98
- */
252
- }
99
- mmu_idx = stage_1_mmu_idx(mmu_idx);
253
- s->phy_control = val & 0x7980;
100
-
254
- /* Complete autonegotiation immediately. */
101
- tcr = regime_tcr(env, mmu_idx);
255
- if (val & 0x1000) {
102
- el = regime_el(env, mmu_idx);
256
- s->phy_status |= 0x0020;
103
-
257
- }
104
- if (el > 1) {
258
- break;
105
- return 0;
259
- case 4: /* Auto-neg advertisement */
106
- } else {
260
- s->phy_advertise = (val & 0x2d7f) | 0x80;
107
- return extract64(tcr->raw_tcr, 38, 1);
261
- break;
262
- /* TODO 17, 18, 27, 31 */
263
- case 30: /* Interrupt mask */
264
- s->phy_int_mask = val & 0xff;
265
- phy_update_irq(s);
266
- break;
267
- default:
268
- qemu_log_mask(LOG_GUEST_ERROR,
269
- "do_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
108
- }
270
- }
109
-}
271
-}
110
-
272
-
111
/* Return the TTBR associated with this translation regime */
273
static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
112
static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
274
{
113
int ttbrn)
275
switch (reg) {
114
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
276
@@ -XXX,XX +XXX,XX @@ static void do_mac_write(lan9118_state *s, int reg, uint32_t val)
115
277
if (val & 2) {
116
*pc = env->pc;
278
DPRINTF("PHY write %d = 0x%04x\n",
117
flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1);
279
(val >> 6) & 0x1f, s->mac_mii_data);
118
- /* Get control bits for tagged addresses */
280
- do_phy_write(s, (val >> 6) & 0x1f, s->mac_mii_data);
119
- flags = FIELD_DP32(flags, TBFLAG_A64, TBII,
281
+ lan9118_phy_write(&s->mii, (val >> 6) & 0x1f, s->mac_mii_data);
120
- (arm_regime_tbi1(env, mmu_idx) << 1) |
282
} else {
121
- arm_regime_tbi0(env, mmu_idx));
283
- s->mac_mii_data = do_phy_read(s, (val >> 6) & 0x1f);
122
+
284
+ s->mac_mii_data = lan9118_phy_read(&s->mii, (val >> 6) & 0x1f);
123
+#ifndef CONFIG_USER_ONLY
285
DPRINTF("PHY read %d = 0x%04x\n",
124
+ /*
286
(val >> 6) & 0x1f, s->mac_mii_data);
125
+ * Get control bits for tagged addresses. Note that the
287
}
126
+ * translator only uses this for instruction addresses.
288
@@ -XXX,XX +XXX,XX @@ static void lan9118_writel(void *opaque, hwaddr offset,
127
+ */
289
break;
128
+ {
290
case CSR_PMT_CTRL:
129
+ ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx);
291
if (val & 0x400) {
130
+ ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1);
292
- phy_reset(s);
131
+ int tbii, tbid;
293
+ lan9118_phy_reset(&s->mii);
132
+
294
}
133
+ /* FIXME: ARMv8.1-VHE S2 translation regime. */
295
s->pmt_ctrl &= ~0x34e;
134
+ if (regime_el(env, stage1) < 2) {
296
s->pmt_ctrl |= (val & 0x34e);
135
+ ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1);
297
@@ -XXX,XX +XXX,XX @@ static void lan9118_realize(DeviceState *dev, Error **errp)
136
+ tbid = (p1.tbi << 1) | p0.tbi;
298
const MemoryRegionOps *mem_ops =
137
+ tbii = tbid & ~((p1.tbid << 1) | p0.tbid);
299
s->mode_16bit ? &lan9118_16bit_mem_ops : &lan9118_mem_ops;
138
+ } else {
300
139
+ tbid = p0.tbi;
301
+ qemu_init_irq(&s->mii_irq, lan9118_update_irq, s, 0);
140
+ tbii = tbid & !p0.tbid;
302
+ object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY);
141
+ }
303
+ if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) {
142
+
304
+ return;
143
+ flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii);
305
+ }
306
+ qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq);
307
+
308
memory_region_init_io(&s->mmio, OBJECT(dev), mem_ops, s,
309
"lan9118-mmio", 0x100);
310
sysbus_init_mmio(sbd, &s->mmio);
311
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
312
new file mode 100644
313
index XXXXXXX..XXXXXXX
314
--- /dev/null
315
+++ b/hw/net/lan9118_phy.c
316
@@ -XXX,XX +XXX,XX @@
317
+/*
318
+ * SMSC LAN9118 PHY emulation
319
+ *
320
+ * Copyright (c) 2009 CodeSourcery, LLC.
321
+ * Written by Paul Brook
322
+ *
323
+ * This code is licensed under the GNU GPL v2
324
+ *
325
+ * Contributions after 2012-01-13 are licensed under the terms of the
326
+ * GNU GPL, version 2 or (at your option) any later version.
327
+ */
328
+
329
+#include "qemu/osdep.h"
330
+#include "hw/net/lan9118_phy.h"
331
+#include "hw/irq.h"
332
+#include "hw/resettable.h"
333
+#include "migration/vmstate.h"
334
+#include "qemu/log.h"
335
+
336
+#define PHY_INT_ENERGYON (1 << 7)
337
+#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
338
+#define PHY_INT_FAULT (1 << 5)
339
+#define PHY_INT_DOWN (1 << 4)
340
+#define PHY_INT_AUTONEG_LP (1 << 3)
341
+#define PHY_INT_PARFAULT (1 << 2)
342
+#define PHY_INT_AUTONEG_PAGE (1 << 1)
343
+
344
+static void lan9118_phy_update_irq(Lan9118PhyState *s)
345
+{
346
+ qemu_set_irq(s->irq, !!(s->ints & s->int_mask));
347
+}
348
+
349
+uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
350
+{
351
+ uint16_t val;
352
+
353
+ switch (reg) {
354
+ case 0: /* Basic Control */
355
+ return s->control;
356
+ case 1: /* Basic Status */
357
+ return s->status;
358
+ case 2: /* ID1 */
359
+ return 0x0007;
360
+ case 3: /* ID2 */
361
+ return 0xc0d1;
362
+ case 4: /* Auto-neg advertisement */
363
+ return s->advertise;
364
+ case 5: /* Auto-neg Link Partner Ability */
365
+ return 0x0f71;
366
+ case 6: /* Auto-neg Expansion */
367
+ return 1;
368
+ /* TODO 17, 18, 27, 29, 30, 31 */
369
+ case 29: /* Interrupt source. */
370
+ val = s->ints;
371
+ s->ints = 0;
372
+ lan9118_phy_update_irq(s);
373
+ return val;
374
+ case 30: /* Interrupt mask */
375
+ return s->int_mask;
376
+ default:
377
+ qemu_log_mask(LOG_GUEST_ERROR,
378
+ "lan9118_phy_read: PHY read reg %d\n", reg);
379
+ return 0;
380
+ }
381
+}
382
+
383
+void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
384
+{
385
+ switch (reg) {
386
+ case 0: /* Basic Control */
387
+ if (val & 0x8000) {
388
+ lan9118_phy_reset(s);
389
+ break;
144
+ }
390
+ }
145
+#endif
391
+ s->control = val & 0x7980;
146
392
+ /* Complete autonegotiation immediately. */
147
if (cpu_isar_feature(aa64_sve, cpu)) {
393
+ if (val & 0x1000) {
148
int sve_el = sve_exception_el(env, current_el);
394
+ s->status |= 0x0020;
395
+ }
396
+ break;
397
+ case 4: /* Auto-neg advertisement */
398
+ s->advertise = (val & 0x2d7f) | 0x80;
399
+ break;
400
+ /* TODO 17, 18, 27, 31 */
401
+ case 30: /* Interrupt mask */
402
+ s->int_mask = val & 0xff;
403
+ lan9118_phy_update_irq(s);
404
+ break;
405
+ default:
406
+ qemu_log_mask(LOG_GUEST_ERROR,
407
+ "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
408
+ }
409
+}
410
+
411
+void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
412
+{
413
+ s->link_down = link_down;
414
+
415
+ /* Autonegotiation status mirrors link status. */
416
+ if (link_down) {
417
+ s->status &= ~0x0024;
418
+ s->ints |= PHY_INT_DOWN;
419
+ } else {
420
+ s->status |= 0x0024;
421
+ s->ints |= PHY_INT_ENERGYON;
422
+ s->ints |= PHY_INT_AUTONEG_COMPLETE;
423
+ }
424
+ lan9118_phy_update_irq(s);
425
+}
426
+
427
+void lan9118_phy_reset(Lan9118PhyState *s)
428
+{
429
+ s->control = 0x3000;
430
+ s->status = 0x7809;
431
+ s->advertise = 0x01e1;
432
+ s->int_mask = 0;
433
+ s->ints = 0;
434
+ lan9118_phy_update_link(s, s->link_down);
435
+}
436
+
437
+static void lan9118_phy_reset_hold(Object *obj, ResetType type)
438
+{
439
+ Lan9118PhyState *s = LAN9118_PHY(obj);
440
+
441
+ lan9118_phy_reset(s);
442
+}
443
+
444
+static void lan9118_phy_init(Object *obj)
445
+{
446
+ Lan9118PhyState *s = LAN9118_PHY(obj);
447
+
448
+ qdev_init_gpio_out(DEVICE(s), &s->irq, 1);
449
+}
450
+
451
+static const VMStateDescription vmstate_lan9118_phy = {
452
+ .name = "lan9118-phy",
453
+ .version_id = 1,
454
+ .minimum_version_id = 1,
455
+ .fields = (const VMStateField[]) {
456
+ VMSTATE_UINT16(control, Lan9118PhyState),
457
+ VMSTATE_UINT16(status, Lan9118PhyState),
458
+ VMSTATE_UINT16(advertise, Lan9118PhyState),
459
+ VMSTATE_UINT16(ints, Lan9118PhyState),
460
+ VMSTATE_UINT16(int_mask, Lan9118PhyState),
461
+ VMSTATE_BOOL(link_down, Lan9118PhyState),
462
+ VMSTATE_END_OF_LIST()
463
+ }
464
+};
465
+
466
+static void lan9118_phy_class_init(ObjectClass *klass, void *data)
467
+{
468
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
469
+ DeviceClass *dc = DEVICE_CLASS(klass);
470
+
471
+ rc->phases.hold = lan9118_phy_reset_hold;
472
+ dc->vmsd = &vmstate_lan9118_phy;
473
+}
474
+
475
+static const TypeInfo types[] = {
476
+ {
477
+ .name = TYPE_LAN9118_PHY,
478
+ .parent = TYPE_SYS_BUS_DEVICE,
479
+ .instance_size = sizeof(Lan9118PhyState),
480
+ .instance_init = lan9118_phy_init,
481
+ .class_init = lan9118_phy_class_init,
482
+ }
483
+};
484
+
485
+DEFINE_TYPES(types)
486
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
487
index XXXXXXX..XXXXXXX 100644
488
--- a/hw/net/Kconfig
489
+++ b/hw/net/Kconfig
490
@@ -XXX,XX +XXX,XX @@ config VMXNET3_PCI
491
config SMC91C111
492
bool
493
494
+config LAN9118_PHY
495
+ bool
496
+
497
config LAN9118
498
bool
499
+ select LAN9118_PHY
500
select PTIMER
501
502
config NE2000_ISA
503
diff --git a/hw/net/meson.build b/hw/net/meson.build
504
index XXXXXXX..XXXXXXX 100644
505
--- a/hw/net/meson.build
506
+++ b/hw/net/meson.build
507
@@ -XXX,XX +XXX,XX @@ system_ss.add(when: 'CONFIG_VMXNET3_PCI', if_true: files('vmxnet3.c'))
508
509
system_ss.add(when: 'CONFIG_SMC91C111', if_true: files('smc91c111.c'))
510
system_ss.add(when: 'CONFIG_LAN9118', if_true: files('lan9118.c'))
511
+system_ss.add(when: 'CONFIG_LAN9118_PHY', if_true: files('lan9118_phy.c'))
512
system_ss.add(when: 'CONFIG_NE2000_ISA', if_true: files('ne2000-isa.c'))
513
system_ss.add(when: 'CONFIG_OPENCORES_ETH', if_true: files('opencores_eth.c'))
514
system_ss.add(when: 'CONFIG_XGMAC', if_true: files('xgmac.c'))
149
--
515
--
150
2.20.1
516
2.34.1
151
152
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/49] ftgmac100: implement the new MDIO interface on Aspeed SoC
[PULL 02/72] hw/net/lan9118_phy: Reuse in imx_fec and consolidate implementations
1
From: Cédric Le Goater <clg@kaod.org>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
The PHY behind the MAC of an Aspeed SoC can be controlled using two
3
imx_fec models the same PHY as lan9118_phy. The code is almost the same with
4
different MDC/MDIO interfaces. The same registers PHYCR (MAC60) and
4
imx_fec having more logging and tracing. Merge these improvements into
5
PHYDATA (MAC64) are involved but they have a different layout.
5
lan9118_phy and reuse in imx_fec to fix the code duplication.
6
6
7
BIT31 of the Feature Register (MAC40) controls which MDC/MDIO
7
Some migration state how resides in the new device model which breaks migration
8
interface is active.
8
compatibility for the following machines:
9
* imx25-pdk
10
* sabrelite
11
* mcimx7d-sabre
12
* mcimx6ul-evk
9
13
10
Signed-off-by: Cédric Le Goater <clg@kaod.org>
14
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
11
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
15
Tested-by: Guenter Roeck <linux@roeck-us.net>
12
Reviewed-by: Joel Stanley <joel@jms.id.au>
16
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Message-id: 20190111125759.31577-1-clg@kaod.org
17
Message-id: 20241102125724.532843-3-shentey@gmail.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
19
---
16
hw/net/ftgmac100.c | 80 +++++++++++++++++++++++++++++++++++++++-------
20
include/hw/net/imx_fec.h | 9 ++-
17
1 file changed, 68 insertions(+), 12 deletions(-)
21
hw/net/imx_fec.c | 146 ++++-----------------------------------
22
hw/net/lan9118_phy.c | 82 ++++++++++++++++------
23
hw/net/Kconfig | 1 +
24
hw/net/trace-events | 10 +--
25
5 files changed, 85 insertions(+), 163 deletions(-)
18
26
19
diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c
27
diff --git a/include/hw/net/imx_fec.h b/include/hw/net/imx_fec.h
20
index XXXXXXX..XXXXXXX 100644
28
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/net/ftgmac100.c
29
--- a/include/hw/net/imx_fec.h
22
+++ b/hw/net/ftgmac100.c
30
+++ b/include/hw/net/imx_fec.h
23
@@ -XXX,XX +XXX,XX @@
31
@@ -XXX,XX +XXX,XX @@ OBJECT_DECLARE_SIMPLE_TYPE(IMXFECState, IMX_FEC)
24
#define FTGMAC100_PHYDATA_MIIWDATA(x) ((x) & 0xffff)
32
#define TYPE_IMX_ENET "imx.enet"
25
#define FTGMAC100_PHYDATA_MIIRDATA(x) (((x) >> 16) & 0xffff)
33
26
34
#include "hw/sysbus.h"
27
+/*
35
+#include "hw/net/lan9118_phy.h"
28
+ * PHY control register - New MDC/MDIO interface
36
+#include "hw/irq.h"
29
+ */
37
#include "net/net.h"
30
+#define FTGMAC100_PHYCR_NEW_DATA(x) (((x) >> 16) & 0xffff)
38
31
+#define FTGMAC100_PHYCR_NEW_FIRE (1 << 15)
39
#define ENET_EIR 1
32
+#define FTGMAC100_PHYCR_NEW_ST_22 (1 << 12)
40
@@ -XXX,XX +XXX,XX @@ struct IMXFECState {
33
+#define FTGMAC100_PHYCR_NEW_OP(x) (((x) >> 10) & 3)
41
uint32_t tx_descriptor[ENET_TX_RING_NUM];
34
+#define FTGMAC100_PHYCR_NEW_OP_WRITE 0x1
42
uint32_t tx_ring_num;
35
+#define FTGMAC100_PHYCR_NEW_OP_READ 0x2
43
36
+#define FTGMAC100_PHYCR_NEW_DEV(x) (((x) >> 5) & 0x1f)
44
- uint32_t phy_status;
37
+#define FTGMAC100_PHYCR_NEW_REG(x) ((x) & 0x1f)
45
- uint32_t phy_control;
38
+
46
- uint32_t phy_advertise;
47
- uint32_t phy_int;
48
- uint32_t phy_int_mask;
49
+ Lan9118PhyState mii;
50
+ IRQState mii_irq;
51
uint32_t phy_num;
52
bool phy_connected;
53
struct IMXFECState *phy_consumer;
54
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
55
index XXXXXXX..XXXXXXX 100644
56
--- a/hw/net/imx_fec.c
57
+++ b/hw/net/imx_fec.c
58
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth_txdescs = {
59
60
static const VMStateDescription vmstate_imx_eth = {
61
.name = TYPE_IMX_FEC,
62
- .version_id = 2,
63
- .minimum_version_id = 2,
64
+ .version_id = 3,
65
+ .minimum_version_id = 3,
66
.fields = (const VMStateField[]) {
67
VMSTATE_UINT32_ARRAY(regs, IMXFECState, ENET_MAX),
68
VMSTATE_UINT32(rx_descriptor, IMXFECState),
69
VMSTATE_UINT32(tx_descriptor[0], IMXFECState),
70
- VMSTATE_UINT32(phy_status, IMXFECState),
71
- VMSTATE_UINT32(phy_control, IMXFECState),
72
- VMSTATE_UINT32(phy_advertise, IMXFECState),
73
- VMSTATE_UINT32(phy_int, IMXFECState),
74
- VMSTATE_UINT32(phy_int_mask, IMXFECState),
75
VMSTATE_END_OF_LIST()
76
},
77
.subsections = (const VMStateDescription * const []) {
78
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_imx_eth = {
79
},
80
};
81
82
-#define PHY_INT_ENERGYON (1 << 7)
83
-#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
84
-#define PHY_INT_FAULT (1 << 5)
85
-#define PHY_INT_DOWN (1 << 4)
86
-#define PHY_INT_AUTONEG_LP (1 << 3)
87
-#define PHY_INT_PARFAULT (1 << 2)
88
-#define PHY_INT_AUTONEG_PAGE (1 << 1)
89
-
90
static void imx_eth_update(IMXFECState *s);
91
39
/*
92
/*
40
* Feature Register
93
@@ -XXX,XX +XXX,XX @@ static void imx_eth_update(IMXFECState *s);
94
* For now we don't handle any GPIO/interrupt line, so the OS will
95
* have to poll for the PHY status.
41
*/
96
*/
42
@@ -XXX,XX +XXX,XX @@ static void phy_reset(FTGMAC100State *s)
97
-static void imx_phy_update_irq(IMXFECState *s)
43
s->phy_int = 0;
98
+static void imx_phy_update_irq(void *opaque, int n, int level)
44
}
99
{
45
100
- imx_eth_update(s);
46
-static uint32_t do_phy_read(FTGMAC100State *s, int reg)
101
-}
47
+static uint16_t do_phy_read(FTGMAC100State *s, uint8_t reg)
102
-
103
-static void imx_phy_update_link(IMXFECState *s)
104
-{
105
- /* Autonegotiation status mirrors link status. */
106
- if (qemu_get_queue(s->nic)->link_down) {
107
- trace_imx_phy_update_link("down");
108
- s->phy_status &= ~0x0024;
109
- s->phy_int |= PHY_INT_DOWN;
110
- } else {
111
- trace_imx_phy_update_link("up");
112
- s->phy_status |= 0x0024;
113
- s->phy_int |= PHY_INT_ENERGYON;
114
- s->phy_int |= PHY_INT_AUTONEG_COMPLETE;
115
- }
116
- imx_phy_update_irq(s);
117
+ imx_eth_update(opaque);
118
}
119
120
static void imx_eth_set_link(NetClientState *nc)
121
{
122
- imx_phy_update_link(IMX_FEC(qemu_get_nic_opaque(nc)));
123
-}
124
-
125
-static void imx_phy_reset(IMXFECState *s)
126
-{
127
- trace_imx_phy_reset();
128
-
129
- s->phy_status = 0x7809;
130
- s->phy_control = 0x3000;
131
- s->phy_advertise = 0x01e1;
132
- s->phy_int_mask = 0;
133
- s->phy_int = 0;
134
- imx_phy_update_link(s);
135
+ lan9118_phy_update_link(&IMX_FEC(qemu_get_nic_opaque(nc))->mii,
136
+ nc->link_down);
137
}
138
139
static uint32_t imx_phy_read(IMXFECState *s, int reg)
48
{
140
{
49
- uint32_t val;
141
- uint32_t val;
50
+ uint16_t val;
142
uint32_t phy = reg / 32;
51
143
52
switch (reg) {
144
if (!s->phy_connected) {
53
case MII_BMCR: /* Basic Control */
145
@@ -XXX,XX +XXX,XX @@ static uint32_t imx_phy_read(IMXFECState *s, int reg)
54
@@ -XXX,XX +XXX,XX @@ static uint32_t do_phy_read(FTGMAC100State *s, int reg)
146
55
MII_BMCR_FD | MII_BMCR_CTST)
147
reg %= 32;
56
#define MII_ANAR_MASK 0x2d7f
148
57
149
- switch (reg) {
58
-static void do_phy_write(FTGMAC100State *s, int reg, uint32_t val)
150
- case 0: /* Basic Control */
59
+static void do_phy_write(FTGMAC100State *s, uint8_t reg, uint16_t val)
151
- val = s->phy_control;
60
{
152
- break;
61
switch (reg) {
153
- case 1: /* Basic Status */
62
case MII_BMCR: /* Basic Control */
154
- val = s->phy_status;
63
@@ -XXX,XX +XXX,XX @@ static void do_phy_write(FTGMAC100State *s, int reg, uint32_t val)
155
- break;
64
}
156
- case 2: /* ID1 */
65
}
157
- val = 0x0007;
66
158
- break;
67
+static void do_phy_new_ctl(FTGMAC100State *s)
159
- case 3: /* ID2 */
68
+{
160
- val = 0xc0d1;
69
+ uint8_t reg;
161
- break;
70
+ uint16_t data;
162
- case 4: /* Auto-neg advertisement */
71
+
163
- val = s->phy_advertise;
72
+ if (!(s->phycr & FTGMAC100_PHYCR_NEW_ST_22)) {
164
- break;
73
+ qemu_log_mask(LOG_UNIMP, "%s: unsupported ST code\n", __func__);
165
- case 5: /* Auto-neg Link Partner Ability */
166
- val = 0x0f71;
167
- break;
168
- case 6: /* Auto-neg Expansion */
169
- val = 1;
170
- break;
171
- case 29: /* Interrupt source. */
172
- val = s->phy_int;
173
- s->phy_int = 0;
174
- imx_phy_update_irq(s);
175
- break;
176
- case 30: /* Interrupt mask */
177
- val = s->phy_int_mask;
178
- break;
179
- case 17:
180
- case 18:
181
- case 27:
182
- case 31:
183
- qemu_log_mask(LOG_UNIMP, "[%s.phy]%s: reg %d not implemented\n",
184
- TYPE_IMX_FEC, __func__, reg);
185
- val = 0;
186
- break;
187
- default:
188
- qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n",
189
- TYPE_IMX_FEC, __func__, reg);
190
- val = 0;
191
- break;
192
- }
193
-
194
- trace_imx_phy_read(val, phy, reg);
195
-
196
- return val;
197
+ return lan9118_phy_read(&s->mii, reg);
198
}
199
200
static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
201
@@ -XXX,XX +XXX,XX @@ static void imx_phy_write(IMXFECState *s, int reg, uint32_t val)
202
203
reg %= 32;
204
205
- trace_imx_phy_write(val, phy, reg);
206
-
207
- switch (reg) {
208
- case 0: /* Basic Control */
209
- if (val & 0x8000) {
210
- imx_phy_reset(s);
211
- } else {
212
- s->phy_control = val & 0x7980;
213
- /* Complete autonegotiation immediately. */
214
- if (val & 0x1000) {
215
- s->phy_status |= 0x0020;
216
- }
217
- }
218
- break;
219
- case 4: /* Auto-neg advertisement */
220
- s->phy_advertise = (val & 0x2d7f) | 0x80;
221
- break;
222
- case 30: /* Interrupt mask */
223
- s->phy_int_mask = val & 0xff;
224
- imx_phy_update_irq(s);
225
- break;
226
- case 17:
227
- case 18:
228
- case 27:
229
- case 31:
230
- qemu_log_mask(LOG_UNIMP, "[%s.phy)%s: reg %d not implemented\n",
231
- TYPE_IMX_FEC, __func__, reg);
232
- break;
233
- default:
234
- qemu_log_mask(LOG_GUEST_ERROR, "[%s.phy]%s: Bad address at offset %d\n",
235
- TYPE_IMX_FEC, __func__, reg);
236
- break;
237
- }
238
+ lan9118_phy_write(&s->mii, reg, val);
239
}
240
241
static void imx_fec_read_bd(IMXFECBufDesc *bd, dma_addr_t addr)
242
@@ -XXX,XX +XXX,XX @@ static void imx_eth_reset(DeviceState *d)
243
244
s->rx_descriptor = 0;
245
memset(s->tx_descriptor, 0, sizeof(s->tx_descriptor));
246
-
247
- /* We also reset the PHY */
248
- imx_phy_reset(s);
249
}
250
251
static uint32_t imx_default_read(IMXFECState *s, uint32_t index)
252
@@ -XXX,XX +XXX,XX @@ static void imx_eth_realize(DeviceState *dev, Error **errp)
253
sysbus_init_irq(sbd, &s->irq[0]);
254
sysbus_init_irq(sbd, &s->irq[1]);
255
256
+ qemu_init_irq(&s->mii_irq, imx_phy_update_irq, s, 0);
257
+ object_initialize_child(OBJECT(s), "mii", &s->mii, TYPE_LAN9118_PHY);
258
+ if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(&s->mii), errp)) {
74
+ return;
259
+ return;
75
+ }
260
+ }
76
+
261
+ qdev_connect_gpio_out(DEVICE(&s->mii), 0, &s->mii_irq);
77
+ /* Nothing to do */
262
+
78
+ if (!(s->phycr & FTGMAC100_PHYCR_NEW_FIRE)) {
263
qemu_macaddr_default_if_unset(&s->conf.macaddr);
79
+ return;
264
80
+ }
265
s->nic = qemu_new_nic(&imx_eth_net_info, &s->conf,
81
+
266
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
82
+ reg = FTGMAC100_PHYCR_NEW_REG(s->phycr);
267
index XXXXXXX..XXXXXXX 100644
83
+ data = FTGMAC100_PHYCR_NEW_DATA(s->phycr);
268
--- a/hw/net/lan9118_phy.c
84
+
269
+++ b/hw/net/lan9118_phy.c
85
+ switch (FTGMAC100_PHYCR_NEW_OP(s->phycr)) {
270
@@ -XXX,XX +XXX,XX @@
86
+ case FTGMAC100_PHYCR_NEW_OP_WRITE:
271
* Copyright (c) 2009 CodeSourcery, LLC.
87
+ do_phy_write(s, reg, data);
272
* Written by Paul Brook
88
+ break;
273
*
89
+ case FTGMAC100_PHYCR_NEW_OP_READ:
274
+ * Copyright (c) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
90
+ s->phydata = do_phy_read(s, reg) & 0xffff;
275
+ *
91
+ break;
276
* This code is licensed under the GNU GPL v2
92
+ default:
277
*
93
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid OP code %08x\n",
278
* Contributions after 2012-01-13 are licensed under the terms of the
94
+ __func__, s->phycr);
279
@@ -XXX,XX +XXX,XX @@
95
+ }
280
#include "hw/resettable.h"
96
+
281
#include "migration/vmstate.h"
97
+ s->phycr &= ~FTGMAC100_PHYCR_NEW_FIRE;
282
#include "qemu/log.h"
98
+}
283
+#include "trace.h"
99
+
284
100
+static void do_phy_ctl(FTGMAC100State *s)
285
#define PHY_INT_ENERGYON (1 << 7)
101
+{
286
#define PHY_INT_AUTONEG_COMPLETE (1 << 6)
102
+ uint8_t reg = FTGMAC100_PHYCR_REG(s->phycr);
287
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
103
+
288
104
+ if (s->phycr & FTGMAC100_PHYCR_MIIWR) {
289
switch (reg) {
105
+ do_phy_write(s, reg, s->phydata & 0xffff);
290
case 0: /* Basic Control */
106
+ s->phycr &= ~FTGMAC100_PHYCR_MIIWR;
291
- return s->control;
107
+ } else if (s->phycr & FTGMAC100_PHYCR_MIIRD) {
292
+ val = s->control;
108
+ s->phydata = do_phy_read(s, reg) << 16;
293
+ break;
109
+ s->phycr &= ~FTGMAC100_PHYCR_MIIRD;
294
case 1: /* Basic Status */
110
+ } else {
295
- return s->status;
111
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: no OP code %08x\n",
296
+ val = s->status;
112
+ __func__, s->phycr);
297
+ break;
113
+ }
298
case 2: /* ID1 */
114
+}
299
- return 0x0007;
115
+
300
+ val = 0x0007;
116
static int ftgmac100_read_bd(FTGMAC100Desc *bd, dma_addr_t addr)
301
+ break;
302
case 3: /* ID2 */
303
- return 0xc0d1;
304
+ val = 0xc0d1;
305
+ break;
306
case 4: /* Auto-neg advertisement */
307
- return s->advertise;
308
+ val = s->advertise;
309
+ break;
310
case 5: /* Auto-neg Link Partner Ability */
311
- return 0x0f71;
312
+ val = 0x0f71;
313
+ break;
314
case 6: /* Auto-neg Expansion */
315
- return 1;
316
- /* TODO 17, 18, 27, 29, 30, 31 */
317
+ val = 1;
318
+ break;
319
case 29: /* Interrupt source. */
320
val = s->ints;
321
s->ints = 0;
322
lan9118_phy_update_irq(s);
323
- return val;
324
+ break;
325
case 30: /* Interrupt mask */
326
- return s->int_mask;
327
+ val = s->int_mask;
328
+ break;
329
+ case 17:
330
+ case 18:
331
+ case 27:
332
+ case 31:
333
+ qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
334
+ __func__, reg);
335
+ val = 0;
336
+ break;
337
default:
338
- qemu_log_mask(LOG_GUEST_ERROR,
339
- "lan9118_phy_read: PHY read reg %d\n", reg);
340
- return 0;
341
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
342
+ __func__, reg);
343
+ val = 0;
344
+ break;
345
}
346
+
347
+ trace_lan9118_phy_read(val, reg);
348
+
349
+ return val;
350
}
351
352
void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
117
{
353
{
118
if (dma_memory_read(&address_space_memory, addr, bd, sizeof(*bd))) {
354
+ trace_lan9118_phy_write(val, reg);
119
@@ -XXX,XX +XXX,XX @@ static void ftgmac100_write(void *opaque, hwaddr addr,
355
+
120
uint64_t value, unsigned size)
356
switch (reg) {
121
{
357
case 0: /* Basic Control */
122
FTGMAC100State *s = FTGMAC100(opaque);
358
if (val & 0x8000) {
123
- int reg;
359
lan9118_phy_reset(s);
124
360
- break;
125
switch (addr & 0xff) {
361
- }
126
case FTGMAC100_ISR: /* Interrupt status */
362
- s->control = val & 0x7980;
127
@@ -XXX,XX +XXX,XX @@ static void ftgmac100_write(void *opaque, hwaddr addr,
363
- /* Complete autonegotiation immediately. */
128
break;
364
- if (val & 0x1000) {
129
365
- s->status |= 0x0020;
130
case FTGMAC100_PHYCR: /* PHY Device control */
366
+ } else {
131
- reg = FTGMAC100_PHYCR_REG(value);
367
+ s->control = val & 0x7980;
132
s->phycr = value;
368
+ /* Complete autonegotiation immediately. */
133
- if (value & FTGMAC100_PHYCR_MIIWR) {
369
+ if (val & 0x1000) {
134
- do_phy_write(s, reg, s->phydata & 0xffff);
370
+ s->status |= 0x0020;
135
- s->phycr &= ~FTGMAC100_PHYCR_MIIWR;
371
+ }
136
+ if (s->revr & FTGMAC100_REVR_NEW_MDIO_INTERFACE) {
137
+ do_phy_new_ctl(s);
138
} else {
139
- s->phydata = do_phy_read(s, reg) << 16;
140
- s->phycr &= ~FTGMAC100_PHYCR_MIIRD;
141
+ do_phy_ctl(s);
142
}
372
}
143
break;
373
break;
144
case FTGMAC100_PHYDATA:
374
case 4: /* Auto-neg advertisement */
145
@@ -XXX,XX +XXX,XX @@ static void ftgmac100_write(void *opaque, hwaddr addr,
375
s->advertise = (val & 0x2d7f) | 0x80;
146
s->dblac = value;
147
break;
376
break;
148
case FTGMAC100_REVR: /* Feature Register */
377
- /* TODO 17, 18, 27, 31 */
149
- /* TODO: Only Old MDIO interface is supported */
378
case 30: /* Interrupt mask */
150
- s->revr = value & ~FTGMAC100_REVR_NEW_MDIO_INTERFACE;
379
s->int_mask = val & 0xff;
151
+ s->revr = value;
380
lan9118_phy_update_irq(s);
152
break;
381
break;
153
case FTGMAC100_FEAR1: /* Feature Register 1 */
382
+ case 17:
154
s->fear1 = value;
383
+ case 18:
384
+ case 27:
385
+ case 31:
386
+ qemu_log_mask(LOG_UNIMP, "%s: reg %d not implemented\n",
387
+ __func__, reg);
388
+ break;
389
default:
390
- qemu_log_mask(LOG_GUEST_ERROR,
391
- "lan9118_phy_write: PHY write reg %d = 0x%04x\n", reg, val);
392
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad address at offset %d\n",
393
+ __func__, reg);
394
+ break;
395
}
396
}
397
398
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
399
400
/* Autonegotiation status mirrors link status. */
401
if (link_down) {
402
+ trace_lan9118_phy_update_link("down");
403
s->status &= ~0x0024;
404
s->ints |= PHY_INT_DOWN;
405
} else {
406
+ trace_lan9118_phy_update_link("up");
407
s->status |= 0x0024;
408
s->ints |= PHY_INT_ENERGYON;
409
s->ints |= PHY_INT_AUTONEG_COMPLETE;
410
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
411
412
void lan9118_phy_reset(Lan9118PhyState *s)
413
{
414
+ trace_lan9118_phy_reset();
415
+
416
s->control = 0x3000;
417
s->status = 0x7809;
418
s->advertise = 0x01e1;
419
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_lan9118_phy = {
420
.version_id = 1,
421
.minimum_version_id = 1,
422
.fields = (const VMStateField[]) {
423
- VMSTATE_UINT16(control, Lan9118PhyState),
424
VMSTATE_UINT16(status, Lan9118PhyState),
425
+ VMSTATE_UINT16(control, Lan9118PhyState),
426
VMSTATE_UINT16(advertise, Lan9118PhyState),
427
VMSTATE_UINT16(ints, Lan9118PhyState),
428
VMSTATE_UINT16(int_mask, Lan9118PhyState),
429
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
430
index XXXXXXX..XXXXXXX 100644
431
--- a/hw/net/Kconfig
432
+++ b/hw/net/Kconfig
433
@@ -XXX,XX +XXX,XX @@ config ALLWINNER_SUN8I_EMAC
434
435
config IMX_FEC
436
bool
437
+ select LAN9118_PHY
438
439
config CADENCE
440
bool
441
diff --git a/hw/net/trace-events b/hw/net/trace-events
442
index XXXXXXX..XXXXXXX 100644
443
--- a/hw/net/trace-events
444
+++ b/hw/net/trace-events
445
@@ -XXX,XX +XXX,XX @@ allwinner_sun8i_emac_set_link(bool active) "Set link: active=%u"
446
allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offset=0x%" PRIx64 " value=0x%" PRIx64
447
allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: offset=0x%" PRIx64 " value=0x%" PRIx64
448
449
+# lan9118_phy.c
450
+lan9118_phy_read(uint16_t val, int reg) "[0x%02x] -> 0x%04" PRIx16
451
+lan9118_phy_write(uint16_t val, int reg) "[0x%02x] <- 0x%04" PRIx16
452
+lan9118_phy_update_link(const char *s) "%s"
453
+lan9118_phy_reset(void) ""
454
+
455
# lance.c
456
lance_mem_readw(uint64_t addr, uint32_t ret) "addr=0x%"PRIx64"val=0x%04x"
457
lance_mem_writew(uint64_t addr, uint32_t val) "addr=0x%"PRIx64"val=0x%04x"
458
@@ -XXX,XX +XXX,XX @@ i82596_set_multicast(uint16_t count) "Added %d multicast entries"
459
i82596_channel_attention(void *s) "%p: Received CHANNEL ATTENTION"
460
461
# imx_fec.c
462
-imx_phy_read(uint32_t val, int phy, int reg) "0x%04"PRIx32" <= phy[%d].reg[%d]"
463
imx_phy_read_num(int phy, int configured) "read request from unconfigured phy %d (configured %d)"
464
-imx_phy_write(uint32_t val, int phy, int reg) "0x%04"PRIx32" => phy[%d].reg[%d]"
465
imx_phy_write_num(int phy, int configured) "write request to unconfigured phy %d (configured %d)"
466
-imx_phy_update_link(const char *s) "%s"
467
-imx_phy_reset(void) ""
468
imx_fec_read_bd(uint64_t addr, int flags, int len, int data) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x"
469
imx_enet_read_bd(uint64_t addr, int flags, int len, int data, int options, int status) "tx_bd 0x%"PRIx64" flags 0x%04x len %d data 0x%08x option 0x%04x status 0x%04x"
470
imx_eth_tx_bd_busy(void) "tx_bd ran out of descriptors to transmit"
155
--
471
--
156
2.20.1
472
2.34.1
157
158
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/49] target/arm: Allow Aarch32 exception return to switch from Mon->Hyp
[PULL 03/72] hw/net/lan9118_phy: Fix off-by-one error in MII_ANLPAR register
1
From: Alexander Graf <agraf@suse.de>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
In U-boot, we switch from S-SVC -> Mon -> Hyp mode when we want to
3
Turns 0x70 into 0xe0 (== 0x70 << 1) which adds the missing MII_ANLPAR_TX and
4
enter Hyp mode. The change into Hyp mode is done by doing an
4
fixes the MSB of selector field to be zero, as specified in the datasheet.
5
exception return from Mon. This doesn't work with current QEMU.
6
5
7
The problem is that in bad_mode_switch() we refuse to allow
6
Fixes: 2a424990170b "LAN9118 emulation"
8
the change of mode.
7
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
9
8
Tested-by: Guenter Roeck <linux@roeck-us.net>
10
Note that bad_mode_switch() is used to do validation for two situations:
11
12
(1) changes to mode by instructions writing to CPSR.M
13
(ie not exception take/return) -- this corresponds to the
14
Armv8 Arm ARM pseudocode Arch32.WriteModeByInstr
15
(2) changes to mode by exception return
16
17
Attempting to enter or leave Hyp mode via case (1) is forbidden in
18
v8 and UNPREDICTABLE in v7, and QEMU is correct to disallow it
19
there. However, we're already doing that check at the top of the
20
bad_mode_switch() function, so if that passes then we should allow
21
the case (2) exception return mode changes to switch into Hyp mode.
22
23
We want to test whether we're trying to return to the nonexistent
24
"secure Hyp" mode, so we need to look at arm_is_secure_below_el3()
25
rather than arm_is_secure(), since the latter is always true if
26
we're in Mon (EL3).
27
28
Signed-off-by: Alexander Graf <agraf@suse.de>
29
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
30
Message-id: 20190109152430.32359-1-agraf@suse.de
10
Message-id: 20241102125724.532843-4-shentey@gmail.com
31
[PMM: rewrote commit message]
32
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
33
---
12
---
34
target/arm/helper.c | 2 +-
13
hw/net/lan9118_phy.c | 2 +-
35
1 file changed, 1 insertion(+), 1 deletion(-)
14
1 file changed, 1 insertion(+), 1 deletion(-)
36
15
37
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
38
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/helper.c
18
--- a/hw/net/lan9118_phy.c
40
+++ b/target/arm/helper.c
19
+++ b/hw/net/lan9118_phy.c
41
@@ -XXX,XX +XXX,XX @@ static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
20
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
42
return 0;
21
val = s->advertise;
43
case ARM_CPU_MODE_HYP:
22
break;
44
return !arm_feature(env, ARM_FEATURE_EL2)
23
case 5: /* Auto-neg Link Partner Ability */
45
- || arm_current_el(env) < 2 || arm_is_secure(env);
24
- val = 0x0f71;
46
+ || arm_current_el(env) < 2 || arm_is_secure_below_el3(env);
25
+ val = 0x0fe1;
47
case ARM_CPU_MODE_MON:
26
break;
48
return arm_current_el(env) < 3;
27
case 6: /* Auto-neg Expansion */
49
default:
28
val = 1;
50
--
29
--
51
2.20.1
30
2.34.1
52
53
diff view generated by jsdifflib
[Qemu-devel] [PULL 17/49] target/arm: Decode PAuth within disas_uncond_b_reg
[PULL 04/72] hw/net/lan9118_phy: Reuse MII constants
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Bernhard Beschow <shentey@gmail.com>
2
3
Prefer named constants over magic values for better readability.
2
4
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
5
Message-id: 20190108223129.5570-14-richard.henderson@linaro.org
7
Tested-by: Guenter Roeck <linux@roeck-us.net>
8
Message-id: 20241102125724.532843-5-shentey@gmail.com
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
10
---
8
target/arm/translate-a64.c | 82 +++++++++++++++++++++++++++++++++++++-
11
include/hw/net/mii.h | 6 +++++
9
1 file changed, 81 insertions(+), 1 deletion(-)
12
hw/net/lan9118_phy.c | 63 ++++++++++++++++++++++++++++----------------
13
2 files changed, 46 insertions(+), 23 deletions(-)
10
14
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
diff --git a/include/hw/net/mii.h b/include/hw/net/mii.h
12
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
17
--- a/include/hw/net/mii.h
14
+++ b/target/arm/translate-a64.c
18
+++ b/include/hw/net/mii.h
15
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
19
@@ -XXX,XX +XXX,XX @@
16
{
20
#define MII_BMSR_JABBER (1 << 1) /* Jabber detected */
17
unsigned int opc, op2, op3, rn, op4;
21
#define MII_BMSR_EXTCAP (1 << 0) /* Ext-reg capability */
18
TCGv_i64 dst;
22
19
+ TCGv_i64 modifier;
23
+#define MII_ANAR_RFAULT (1 << 13) /* Say we can detect faults */
20
24
#define MII_ANAR_PAUSE_ASYM (1 << 11) /* Try for asymmetric pause */
21
opc = extract32(insn, 21, 4);
25
#define MII_ANAR_PAUSE (1 << 10) /* Try for pause */
22
op2 = extract32(insn, 16, 5);
26
#define MII_ANAR_TXFD (1 << 8)
23
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
27
@@ -XXX,XX +XXX,XX @@
24
case 2: /* RET */
28
#define MII_ANAR_10FD (1 << 6)
25
switch (op3) {
29
#define MII_ANAR_10 (1 << 5)
26
case 0:
30
#define MII_ANAR_CSMACD (1 << 0)
27
+ /* BR, BLR, RET */
31
+#define MII_ANAR_SELECT (0x001f) /* Selector bits */
28
if (op4 != 0) {
32
29
goto do_unallocated;
33
#define MII_ANLPAR_ACK (1 << 14)
34
#define MII_ANLPAR_PAUSEASY (1 << 11) /* can pause asymmetrically */
35
@@ -XXX,XX +XXX,XX @@
36
#define RTL8201CP_PHYID1 0x0000
37
#define RTL8201CP_PHYID2 0x8201
38
39
+/* SMSC LAN9118 */
40
+#define SMSCLAN9118_PHYID1 0x0007
41
+#define SMSCLAN9118_PHYID2 0xc0d1
42
+
43
/* RealTek 8211E */
44
#define RTL8211E_PHYID1 0x001c
45
#define RTL8211E_PHYID2 0xc915
46
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/hw/net/lan9118_phy.c
49
+++ b/hw/net/lan9118_phy.c
50
@@ -XXX,XX +XXX,XX @@
51
52
#include "qemu/osdep.h"
53
#include "hw/net/lan9118_phy.h"
54
+#include "hw/net/mii.h"
55
#include "hw/irq.h"
56
#include "hw/resettable.h"
57
#include "migration/vmstate.h"
58
@@ -XXX,XX +XXX,XX @@ uint16_t lan9118_phy_read(Lan9118PhyState *s, int reg)
59
uint16_t val;
60
61
switch (reg) {
62
- case 0: /* Basic Control */
63
+ case MII_BMCR:
64
val = s->control;
65
break;
66
- case 1: /* Basic Status */
67
+ case MII_BMSR:
68
val = s->status;
69
break;
70
- case 2: /* ID1 */
71
- val = 0x0007;
72
+ case MII_PHYID1:
73
+ val = SMSCLAN9118_PHYID1;
74
break;
75
- case 3: /* ID2 */
76
- val = 0xc0d1;
77
+ case MII_PHYID2:
78
+ val = SMSCLAN9118_PHYID2;
79
break;
80
- case 4: /* Auto-neg advertisement */
81
+ case MII_ANAR:
82
val = s->advertise;
83
break;
84
- case 5: /* Auto-neg Link Partner Ability */
85
- val = 0x0fe1;
86
+ case MII_ANLPAR:
87
+ val = MII_ANLPAR_PAUSEASY | MII_ANLPAR_PAUSE | MII_ANLPAR_T4 |
88
+ MII_ANLPAR_TXFD | MII_ANLPAR_TX | MII_ANLPAR_10FD |
89
+ MII_ANLPAR_10 | MII_ANLPAR_CSMACD;
90
break;
91
- case 6: /* Auto-neg Expansion */
92
- val = 1;
93
+ case MII_ANER:
94
+ val = MII_ANER_NWAY;
95
break;
96
case 29: /* Interrupt source. */
97
val = s->ints;
98
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
99
trace_lan9118_phy_write(val, reg);
100
101
switch (reg) {
102
- case 0: /* Basic Control */
103
- if (val & 0x8000) {
104
+ case MII_BMCR:
105
+ if (val & MII_BMCR_RESET) {
106
lan9118_phy_reset(s);
107
} else {
108
- s->control = val & 0x7980;
109
+ s->control = val & (MII_BMCR_LOOPBACK | MII_BMCR_SPEED100 |
110
+ MII_BMCR_AUTOEN | MII_BMCR_PDOWN | MII_BMCR_FD |
111
+ MII_BMCR_CTST);
112
/* Complete autonegotiation immediately. */
113
- if (val & 0x1000) {
114
- s->status |= 0x0020;
115
+ if (val & MII_BMCR_AUTOEN) {
116
+ s->status |= MII_BMSR_AN_COMP;
30
}
117
}
31
dst = cpu_reg(s, rn);
32
break;
33
34
+ case 2:
35
+ case 3:
36
+ if (!dc_isar_feature(aa64_pauth, s)) {
37
+ goto do_unallocated;
38
+ }
39
+ if (opc == 2) {
40
+ /* RETAA, RETAB */
41
+ if (rn != 0x1f || op4 != 0x1f) {
42
+ goto do_unallocated;
43
+ }
44
+ rn = 30;
45
+ modifier = cpu_X[31];
46
+ } else {
47
+ /* BRAAZ, BRABZ, BLRAAZ, BLRABZ */
48
+ if (op4 != 0x1f) {
49
+ goto do_unallocated;
50
+ }
51
+ modifier = new_tmp_a64_zero(s);
52
+ }
53
+ if (s->pauth_active) {
54
+ dst = new_tmp_a64(s);
55
+ if (op3 == 2) {
56
+ gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier);
57
+ } else {
58
+ gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier);
59
+ }
60
+ } else {
61
+ dst = cpu_reg(s, rn);
62
+ }
63
+ break;
64
+
65
default:
66
goto do_unallocated;
67
}
68
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
69
}
118
}
70
break;
119
break;
71
120
- case 4: /* Auto-neg advertisement */
72
+ case 8: /* BRAA */
121
- s->advertise = (val & 0x2d7f) | 0x80;
73
+ case 9: /* BLRAA */
122
+ case MII_ANAR:
74
+ if (!dc_isar_feature(aa64_pauth, s)) {
123
+ s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM |
75
+ goto do_unallocated;
124
+ MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 |
76
+ }
125
+ MII_ANAR_SELECT))
77
+ if (op3 != 2 || op3 != 3) {
126
+ | MII_ANAR_TX;
78
+ goto do_unallocated;
127
break;
79
+ }
128
case 30: /* Interrupt mask */
80
+ if (s->pauth_active) {
129
s->int_mask = val & 0xff;
81
+ dst = new_tmp_a64(s);
130
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_update_link(Lan9118PhyState *s, bool link_down)
82
+ modifier = cpu_reg_sp(s, op4);
131
/* Autonegotiation status mirrors link status. */
83
+ if (op3 == 2) {
132
if (link_down) {
84
+ gen_helper_autia(dst, cpu_env, cpu_reg(s, rn), modifier);
133
trace_lan9118_phy_update_link("down");
85
+ } else {
134
- s->status &= ~0x0024;
86
+ gen_helper_autib(dst, cpu_env, cpu_reg(s, rn), modifier);
135
+ s->status &= ~(MII_BMSR_AN_COMP | MII_BMSR_LINK_ST);
87
+ }
136
s->ints |= PHY_INT_DOWN;
88
+ } else {
137
} else {
89
+ dst = cpu_reg(s, rn);
138
trace_lan9118_phy_update_link("up");
90
+ }
139
- s->status |= 0x0024;
91
+ gen_a64_set_pc(s, dst);
140
+ s->status |= MII_BMSR_AN_COMP | MII_BMSR_LINK_ST;
92
+ /* BLRAA also needs to load return address */
141
s->ints |= PHY_INT_ENERGYON;
93
+ if (opc == 9) {
142
s->ints |= PHY_INT_AUTONEG_COMPLETE;
94
+ tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
143
}
95
+ }
144
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_reset(Lan9118PhyState *s)
96
+ break;
145
{
97
+
146
trace_lan9118_phy_reset();
98
case 4: /* ERET */
147
99
if (s->current_el == 0) {
148
- s->control = 0x3000;
100
goto do_unallocated;
149
- s->status = 0x7809;
101
}
150
- s->advertise = 0x01e1;
102
switch (op3) {
151
+ s->control = MII_BMCR_AUTOEN | MII_BMCR_SPEED100;
103
- case 0:
152
+ s->status = MII_BMSR_100TX_FD
104
+ case 0: /* ERET */
153
+ | MII_BMSR_100TX_HD
105
if (op4 != 0) {
154
+ | MII_BMSR_10T_FD
106
goto do_unallocated;
155
+ | MII_BMSR_10T_HD
107
}
156
+ | MII_BMSR_AUTONEG
108
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
157
+ | MII_BMSR_EXTCAP;
109
offsetof(CPUARMState, elr_el[s->current_el]));
158
+ s->advertise = MII_ANAR_TXFD
110
break;
159
+ | MII_ANAR_TX
111
160
+ | MII_ANAR_10FD
112
+ case 2: /* ERETAA */
161
+ | MII_ANAR_10
113
+ case 3: /* ERETAB */
162
+ | MII_ANAR_CSMACD;
114
+ if (!dc_isar_feature(aa64_pauth, s)) {
163
s->int_mask = 0;
115
+ goto do_unallocated;
164
s->ints = 0;
116
+ }
165
lan9118_phy_update_link(s, s->link_down);
117
+ if (rn != 0x1f || op4 != 0x1f) {
118
+ goto do_unallocated;
119
+ }
120
+ dst = tcg_temp_new_i64();
121
+ tcg_gen_ld_i64(dst, cpu_env,
122
+ offsetof(CPUARMState, elr_el[s->current_el]));
123
+ if (s->pauth_active) {
124
+ modifier = cpu_X[31];
125
+ if (op3 == 2) {
126
+ gen_helper_autia(dst, cpu_env, dst, modifier);
127
+ } else {
128
+ gen_helper_autib(dst, cpu_env, dst, modifier);
129
+ }
130
+ }
131
+ break;
132
+
133
default:
134
goto do_unallocated;
135
}
136
--
166
--
137
2.20.1
167
2.34.1
138
139
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/49] target/arm: Add PAuth active bit to tbflags
[PULL 05/72] hw/net/lan9118_phy: Add missing 100 mbps full duplex advertisement
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Bernhard Beschow <shentey@gmail.com>
2
2
3
There are 5 bits of state that could be added, but to save
3
The real device advertises this mode and the device model already advertises
4
space within tbflags, add only a single enable bit.
4
100 mbps half duplex and 10 mbps full+half duplex. So advertise this mode to
5
Helpers will determine the rest of the state at runtime.
5
make the model more realistic.
6
6
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Bernhard Beschow <shentey@gmail.com>
9
Message-id: 20190108223129.5570-4-richard.henderson@linaro.org
9
Tested-by: Guenter Roeck <linux@roeck-us.net>
10
Message-id: 20241102125724.532843-6-shentey@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
---
12
target/arm/cpu.h | 1 +
13
hw/net/lan9118_phy.c | 4 ++--
13
target/arm/translate.h | 2 ++
14
1 file changed, 2 insertions(+), 2 deletions(-)
14
target/arm/helper.c | 19 +++++++++++++++++++
15
target/arm/translate-a64.c | 1 +
16
4 files changed, 23 insertions(+)
17
15
18
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
16
diff --git a/hw/net/lan9118_phy.c b/hw/net/lan9118_phy.c
19
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/cpu.h
18
--- a/hw/net/lan9118_phy.c
21
+++ b/target/arm/cpu.h
19
+++ b/hw/net/lan9118_phy.c
22
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A64, TBI0, 0, 1)
20
@@ -XXX,XX +XXX,XX @@ void lan9118_phy_write(Lan9118PhyState *s, int reg, uint16_t val)
23
FIELD(TBFLAG_A64, TBI1, 1, 1)
21
break;
24
FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
22
case MII_ANAR:
25
FIELD(TBFLAG_A64, ZCR_LEN, 4, 4)
23
s->advertise = (val & (MII_ANAR_RFAULT | MII_ANAR_PAUSE_ASYM |
26
+FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
24
- MII_ANAR_PAUSE | MII_ANAR_10FD | MII_ANAR_10 |
27
25
- MII_ANAR_SELECT))
28
static inline bool bswap_code(bool sctlr_b)
26
+ MII_ANAR_PAUSE | MII_ANAR_TXFD | MII_ANAR_10FD |
29
{
27
+ MII_ANAR_10 | MII_ANAR_SELECT))
30
diff --git a/target/arm/translate.h b/target/arm/translate.h
28
| MII_ANAR_TX;
31
index XXXXXXX..XXXXXXX 100644
29
break;
32
--- a/target/arm/translate.h
30
case 30: /* Interrupt mask */
33
+++ b/target/arm/translate.h
34
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
35
bool is_ldex;
36
/* True if a single-step exception will be taken to the current EL */
37
bool ss_same_el;
38
+ /* True if v8.3-PAuth is active. */
39
+ bool pauth_active;
40
/* Bottom two bits of XScale c15_cpar coprocessor access control reg */
41
int c15_cpar;
42
/* TCG op of the current insn_start. */
43
diff --git a/target/arm/helper.c b/target/arm/helper.c
44
index XXXXXXX..XXXXXXX 100644
45
--- a/target/arm/helper.c
46
+++ b/target/arm/helper.c
47
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
48
flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el);
49
flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len);
50
}
51
+
52
+ if (cpu_isar_feature(aa64_pauth, cpu)) {
53
+ /*
54
+ * In order to save space in flags, we record only whether
55
+ * pauth is "inactive", meaning all insns are implemented as
56
+ * a nop, or "active" when some action must be performed.
57
+ * The decision of which action to take is left to a helper.
58
+ */
59
+ uint64_t sctlr;
60
+ if (current_el == 0) {
61
+ /* FIXME: ARMv8.1-VHE S2 translation regime. */
62
+ sctlr = env->cp15.sctlr_el[1];
63
+ } else {
64
+ sctlr = env->cp15.sctlr_el[current_el];
65
+ }
66
+ if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) {
67
+ flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1);
68
+ }
69
+ }
70
} else {
71
*pc = env->regs[15];
72
flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb);
73
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
74
index XXXXXXX..XXXXXXX 100644
75
--- a/target/arm/translate-a64.c
76
+++ b/target/arm/translate-a64.c
77
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
78
dc->fp_excp_el = FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL);
79
dc->sve_excp_el = FIELD_EX32(tb_flags, TBFLAG_A64, SVEEXC_EL);
80
dc->sve_len = (FIELD_EX32(tb_flags, TBFLAG_A64, ZCR_LEN) + 1) * 16;
81
+ dc->pauth_active = FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE);
82
dc->vec_len = 0;
83
dc->vec_stride = 0;
84
dc->cp_regs = arm_cpu->cp_regs;
85
--
31
--
86
2.20.1
32
2.34.1
87
88
diff view generated by jsdifflib
[Qemu-devel] [PULL 30/49] target/arm: Implement pauth_addpac
[PULL 06/72] fpu: handle raising Invalid for infzero in pick_nan_muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
For IEEE fused multiply-add, the (0 * inf) + NaN case should raise
2
Invalid for the multiplication of 0 by infinity. Currently we handle
3
this in the per-architecture ifdef ladder in pickNaNMulAdd().
4
However, since this isn't really architecture specific we can hoist
5
it up to the generic code.
2
6
3
This is not really functional yet, because the crypto is not yet
7
For the cases where the infzero test in pickNaNMulAdd was
4
implemented. This, however follows the AddPAC pseudo function.
8
returning 2, we can delete the check entirely and allow the
9
code to fall into the normal pick-a-NaN handling, because this
10
will return 2 anyway (input 'c' being the only NaN in this case).
11
For the cases where infzero was returning 3 to indicate "return
12
the default NaN", we must retain that "return 3".
5
13
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
For Arm, this looks like it might be a behaviour change because we
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
15
used to set float_flag_invalid | float_flag_invalid_imz only if C is
8
Message-id: 20190108223129.5570-27-richard.henderson@linaro.org
16
a quiet NaN. However, it is not, because Arm target code never looks
17
at float_flag_invalid_imz, and for the (0 * inf) + SNaN case we
18
already raised float_flag_invalid via the "abc_mask &
19
float_cmask_snan" check in pick_nan_muladd.
20
21
For any target architecture using the "default implementation" at the
22
bottom of the ifdef, this is a behaviour change but will be fixing a
23
bug (where we failed to raise the Invalid exception for (0 * inf +
24
QNaN). The architectures using the default case are:
25
* hppa
26
* i386
27
* sh4
28
* tricore
29
30
The x86, Tricore and SH4 CPU architecture manuals are clear that this
31
should have raised Invalid; HPPA is a bit vaguer but still seems
32
clear enough.
33
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
34
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
36
Message-id: 20241202131347.498124-2-peter.maydell@linaro.org
10
---
37
---
11
target/arm/pauth_helper.c | 42 ++++++++++++++++++++++++++++++++++++++-
38
fpu/softfloat-parts.c.inc | 13 +++++++------
12
1 file changed, 41 insertions(+), 1 deletion(-)
39
fpu/softfloat-specialize.c.inc | 29 +----------------------------
40
2 files changed, 8 insertions(+), 34 deletions(-)
13
41
14
diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c
42
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
15
index XXXXXXX..XXXXXXX 100644
43
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/pauth_helper.c
44
--- a/fpu/softfloat-parts.c.inc
17
+++ b/target/arm/pauth_helper.c
45
+++ b/fpu/softfloat-parts.c.inc
18
@@ -XXX,XX +XXX,XX @@ static uint64_t pauth_computepac(uint64_t data, uint64_t modifier,
46
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
19
static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier,
47
int ab_mask, int abc_mask)
20
ARMPACKey *key, bool data)
21
{
48
{
22
- g_assert_not_reached(); /* FIXME */
49
int which;
23
+ ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env);
50
+ bool infzero = (ab_mask == float_cmask_infzero);
24
+ ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data);
51
25
+ uint64_t pac, ext_ptr, ext, test;
52
if (unlikely(abc_mask & float_cmask_snan)) {
26
+ int bot_bit, top_bit;
53
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
27
+
54
}
28
+ /* If tagged pointers are in use, use ptr<55>, otherwise ptr<63>. */
55
29
+ if (param.tbi) {
56
- which = pickNaNMulAdd(a->cls, b->cls, c->cls,
30
+ ext = sextract64(ptr, 55, 1);
57
- ab_mask == float_cmask_infzero, s);
31
+ } else {
58
+ if (infzero) {
32
+ ext = sextract64(ptr, 63, 1);
59
+ /* This is (0 * inf) + NaN or (inf * 0) + NaN */
60
+ float_raise(float_flag_invalid | float_flag_invalid_imz, s);
33
+ }
61
+ }
34
+
62
+
35
+ /* Build a pointer with known good extension bits. */
63
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
36
+ top_bit = 64 - 8 * param.tbi;
64
37
+ bot_bit = 64 - param.tsz;
65
if (s->default_nan_mode || which == 3) {
38
+ ext_ptr = deposit64(ptr, bot_bit, top_bit - bot_bit, ext);
66
- /*
67
- * Note that this check is after pickNaNMulAdd so that function
68
- * has an opportunity to set the Invalid flag for infzero.
69
- */
70
parts_default_nan(a, s);
71
return a;
72
}
73
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
74
index XXXXXXX..XXXXXXX 100644
75
--- a/fpu/softfloat-specialize.c.inc
76
+++ b/fpu/softfloat-specialize.c.inc
77
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
78
* the default NaN
79
*/
80
if (infzero && is_qnan(c_cls)) {
81
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
82
return 3;
83
}
84
85
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
86
* case sets InvalidOp and returns the default NaN
87
*/
88
if (infzero) {
89
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
90
return 3;
91
}
92
/* Prefer sNaN over qNaN, in the a, b, c order. */
93
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
94
* For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
95
* case sets InvalidOp and returns the input value 'c'
96
*/
97
- if (infzero) {
98
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
99
- return 2;
100
- }
101
/* Prefer sNaN over qNaN, in the c, a, b order. */
102
if (is_snan(c_cls)) {
103
return 2;
104
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
105
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
106
* case sets InvalidOp and returns the input value 'c'
107
*/
108
- if (infzero) {
109
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
110
- return 2;
111
- }
39
+
112
+
40
+ pac = pauth_computepac(ext_ptr, modifier, *key);
113
/* Prefer sNaN over qNaN, in the c, a, b order. */
41
+
114
if (is_snan(c_cls)) {
42
+ /*
115
return 2;
43
+ * Check if the ptr has good extension bits and corrupt the
116
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
44
+ * pointer authentication code if not.
117
* to return an input NaN if we have one (ie c) rather than generating
45
+ */
118
* a default NaN
46
+ test = sextract64(ptr, bot_bit, top_bit - bot_bit);
119
*/
47
+ if (test != 0 && test != -1) {
120
- if (infzero) {
48
+ pac ^= MAKE_64BIT_MASK(top_bit - 1, 1);
121
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
49
+ }
122
- return 2;
50
+
123
- }
51
+ /*
124
52
+ * Preserve the determination between upper and lower at bit 55,
125
/* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
53
+ * and insert pointer authentication code.
126
* otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
54
+ */
127
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
55
+ if (param.tbi) {
128
return 1;
56
+ ptr &= ~MAKE_64BIT_MASK(bot_bit, 55 - bot_bit + 1);
129
}
57
+ pac &= MAKE_64BIT_MASK(bot_bit, 54 - bot_bit + 1);
130
#elif defined(TARGET_RISCV)
58
+ } else {
131
- /* For RISC-V, InvalidOp is set when multiplicands are Inf and zero */
59
+ ptr &= MAKE_64BIT_MASK(0, bot_bit);
132
- if (infzero) {
60
+ pac &= ~(MAKE_64BIT_MASK(55, 1) | MAKE_64BIT_MASK(0, bot_bit));
133
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
61
+ }
134
- }
62
+ ext &= MAKE_64BIT_MASK(55, 1);
135
return 3; /* default NaN */
63
+ return pac | ext | ptr;
136
#elif defined(TARGET_S390X)
64
}
137
if (infzero) {
65
138
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
66
static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)
139
return 3;
140
}
141
142
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
143
return 2;
144
}
145
#elif defined(TARGET_SPARC)
146
- /* For (inf,0,nan) return c. */
147
- if (infzero) {
148
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
149
- return 2;
150
- }
151
/* Prefer SNaN over QNaN, order C, B, A. */
152
if (is_snan(c_cls)) {
153
return 2;
154
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
155
* For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
156
* an input NaN if we have one (ie c).
157
*/
158
- if (infzero) {
159
- float_raise(float_flag_invalid | float_flag_invalid_imz, status);
160
- return 2;
161
- }
162
if (status->use_first_nan) {
163
if (is_nan(a_cls)) {
164
return 0;
67
--
165
--
68
2.20.1
166
2.34.1
69
70
diff view generated by jsdifflib
New patch
[PULL 07/72] fpu: Check for default_nan_mode before calling pickNaNMulAdd
1
If the target sets default_nan_mode then we're always going to return
2
the default NaN, and pickNaNMulAdd() no longer has any side effects.
3
For consistency with pickNaN(), check for default_nan_mode before
4
calling pickNaNMulAdd().
1
5
6
When we convert pickNaNMulAdd() to allow runtime selection of the NaN
7
propagation rule, this means we won't have to make the targets which
8
use default_nan_mode also set a propagation rule.
9
10
Since RiscV always uses default_nan_mode, this allows us to remove
11
its ifdef case from pickNaNMulAdd().
12
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20241202131347.498124-3-peter.maydell@linaro.org
16
---
17
fpu/softfloat-parts.c.inc | 8 ++++++--
18
fpu/softfloat-specialize.c.inc | 9 +++++++--
19
2 files changed, 13 insertions(+), 4 deletions(-)
20
21
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
22
index XXXXXXX..XXXXXXX 100644
23
--- a/fpu/softfloat-parts.c.inc
24
+++ b/fpu/softfloat-parts.c.inc
25
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
26
float_raise(float_flag_invalid | float_flag_invalid_imz, s);
27
}
28
29
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
30
+ if (s->default_nan_mode) {
31
+ which = 3;
32
+ } else {
33
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
34
+ }
35
36
- if (s->default_nan_mode || which == 3) {
37
+ if (which == 3) {
38
parts_default_nan(a, s);
39
return a;
40
}
41
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
42
index XXXXXXX..XXXXXXX 100644
43
--- a/fpu/softfloat-specialize.c.inc
44
+++ b/fpu/softfloat-specialize.c.inc
45
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
46
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
47
bool infzero, float_status *status)
48
{
49
+ /*
50
+ * We guarantee not to require the target to tell us how to
51
+ * pick a NaN if we're always returning the default NaN.
52
+ * But if we're not in default-NaN mode then the target must
53
+ * specify.
54
+ */
55
+ assert(!status->default_nan_mode);
56
#if defined(TARGET_ARM)
57
/* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
58
* the default NaN
59
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
60
} else {
61
return 1;
62
}
63
-#elif defined(TARGET_RISCV)
64
- return 3; /* default NaN */
65
#elif defined(TARGET_S390X)
66
if (infzero) {
67
return 3;
68
--
69
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 48/49] target/arm: Implement PMSWINC
[PULL 08/72] softfloat: Allow runtime choice of inf * 0 + NaN result
1
From: Aaron Lindsay <aaron@os.amperecomputing.com>
1
IEEE 758 does not define a fixed rule for what NaN to return in
2
2
the case of a fused multiply-add of inf * 0 + NaN. Different
3
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
3
architectures thus do different things:
4
* some return the default NaN
5
* some return the input NaN
6
* Arm returns the default NaN if the input NaN is quiet,
7
and the input NaN if it is signalling
8
9
We want to make this logic be runtime selected rather than
10
hardcoded into the binary, because:
11
* this will let us have multiple targets in one QEMU binary
12
* the Arm FEAT_AFP architectural feature includes letting
13
the guest select a NaN propagation rule at runtime
14
15
In this commit we add an enum for the propagation rule, the field in
16
float_status, and the corresponding getters and setters. We change
17
pickNaNMulAdd to honour this, but because all targets still leave
18
this field at its default 0 value, the fallback logic will pick the
19
rule type with the old ifdef ladder.
20
21
Note that four architectures both use the muladd softfloat functions
22
and did not have a branch of the ifdef ladder to specify their
23
behaviour (and so were ending up with the "default" case, probably
24
wrongly): i386, HPPA, SH4 and Tricore. SH4 and Tricore both set
25
default_nan_mode, and so will never get into pickNaNMulAdd(). For
26
HPPA and i386 we retain the same behaviour as the old default-case,
27
which is to not ever return the default NaN. This might not be
28
correct but it is not a behaviour change.
29
30
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
31
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20181211151945.29137-14-aaron@os.amperecomputing.com
32
Message-id: 20241202131347.498124-4-peter.maydell@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
33
---
8
target/arm/helper.c | 39 +++++++++++++++++++++++++++++++++++++--
34
include/fpu/softfloat-helpers.h | 11 ++++
9
1 file changed, 37 insertions(+), 2 deletions(-)
35
include/fpu/softfloat-types.h | 23 +++++++++
10
36
fpu/softfloat-specialize.c.inc | 91 ++++++++++++++++++++++-----------
11
diff --git a/target/arm/helper.c b/target/arm/helper.c
37
3 files changed, 95 insertions(+), 30 deletions(-)
38
39
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
12
index XXXXXXX..XXXXXXX 100644
40
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/helper.c
41
--- a/include/fpu/softfloat-helpers.h
14
+++ b/target/arm/helper.c
42
+++ b/include/fpu/softfloat-helpers.h
15
@@ -XXX,XX +XXX,XX @@ static bool event_always_supported(CPUARMState *env)
43
@@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule,
16
return true;
44
status->float_2nan_prop_rule = rule;
17
}
45
}
18
46
19
+static uint64_t swinc_get_count(CPUARMState *env)
47
+static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
48
+ float_status *status)
20
+{
49
+{
21
+ /*
50
+ status->float_infzeronan_rule = rule;
22
+ * SW_INCR events are written directly to the pmevcntr's by writes to
23
+ * PMSWINC, so there is no underlying count maintained by the PMU itself
24
+ */
25
+ return 0;
26
+}
51
+}
27
+
52
+
53
static inline void set_flush_to_zero(bool val, float_status *status)
54
{
55
status->flush_to_zero = val;
56
@@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status)
57
return status->float_2nan_prop_rule;
58
}
59
60
+static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status)
61
+{
62
+ return status->float_infzeronan_rule;
63
+}
64
+
65
static inline bool get_flush_to_zero(float_status *status)
66
{
67
return status->flush_to_zero;
68
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
69
index XXXXXXX..XXXXXXX 100644
70
--- a/include/fpu/softfloat-types.h
71
+++ b/include/fpu/softfloat-types.h
72
@@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) {
73
float_2nan_prop_x87,
74
} Float2NaNPropRule;
75
76
+/*
77
+ * Rule for result of fused multiply-add 0 * Inf + NaN.
78
+ * This must be a NaN, but implementations differ on whether this
79
+ * is the input NaN or the default NaN.
80
+ *
81
+ * You don't need to set this if default_nan_mode is enabled.
82
+ * When not in default-NaN mode, it is an error for the target
83
+ * not to set the rule in float_status if it uses muladd, and we
84
+ * will assert if we need to handle an input NaN and no rule was
85
+ * selected.
86
+ */
87
+typedef enum __attribute__((__packed__)) {
88
+ /* No propagation rule specified */
89
+ float_infzeronan_none = 0,
90
+ /* Result is never the default NaN (so always the input NaN) */
91
+ float_infzeronan_dnan_never,
92
+ /* Result is always the default NaN */
93
+ float_infzeronan_dnan_always,
94
+ /* Result is the default NaN if the input NaN is quiet */
95
+ float_infzeronan_dnan_if_qnan,
96
+} FloatInfZeroNaNRule;
97
+
28
/*
98
/*
29
* Return the underlying cycle count for the PMU cycle counters. If we're in
99
* Floating Point Status. Individual architectures may maintain
30
* usermode, simply return 0.
100
* several versions of float_status for different functions. The
31
@@ -XXX,XX +XXX,XX @@ static uint64_t instructions_get_count(CPUARMState *env)
101
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
32
#endif
102
FloatRoundMode float_rounding_mode;
33
103
FloatX80RoundPrec floatx80_rounding_precision;
34
static const pm_event pm_events[] = {
104
Float2NaNPropRule float_2nan_prop_rule;
35
+ { .number = 0x000, /* SW_INCR */
105
+ FloatInfZeroNaNRule float_infzeronan_rule;
36
+ .supported = event_always_supported,
106
bool tininess_before_rounding;
37
+ .get_count = swinc_get_count,
107
/* should denormalised results go to zero and set the inexact flag? */
38
+ },
108
bool flush_to_zero;
39
#ifndef CONFIG_USER_ONLY
109
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
40
{ .number = 0x008, /* INST_RETIRED, Instruction architecturally executed */
110
index XXXXXXX..XXXXXXX 100644
41
.supported = instructions_supported,
111
--- a/fpu/softfloat-specialize.c.inc
42
@@ -XXX,XX +XXX,XX @@ static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
112
+++ b/fpu/softfloat-specialize.c.inc
43
pmu_op_finish(env);
113
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
44
}
114
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
45
115
bool infzero, float_status *status)
46
+static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri,
116
{
47
+ uint64_t value)
117
+ FloatInfZeroNaNRule rule = status->float_infzeronan_rule;
48
+{
118
+
49
+ unsigned int i;
119
/*
50
+ for (i = 0; i < pmu_num_counters(env); i++) {
120
* We guarantee not to require the target to tell us how to
51
+ /* Increment a counter's count iff: */
121
* pick a NaN if we're always returning the default NaN.
52
+ if ((value & (1 << i)) && /* counter's bit is set */
122
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
53
+ /* counter is enabled and not filtered */
123
* specify.
54
+ pmu_counter_enabled(env, i) &&
124
*/
55
+ /* counter is SW_INCR */
125
assert(!status->default_nan_mode);
56
+ (env->cp15.c14_pmevtyper[i] & PMXEVTYPER_EVTCOUNT) == 0x0) {
126
+
57
+ pmevcntr_op_start(env, i);
127
+ if (rule == float_infzeronan_none) {
58
+ env->cp15.c14_pmevcntr[i]++;
128
+ /*
59
+ pmevcntr_op_finish(env, i);
129
+ * Temporarily fall back to ifdef ladder
130
+ */
131
#if defined(TARGET_ARM)
132
- /* For ARM, the (inf,zero,qnan) case sets InvalidOp and returns
133
- * the default NaN
134
- */
135
- if (infzero && is_qnan(c_cls)) {
136
- return 3;
137
+ /*
138
+ * For ARM, the (inf,zero,qnan) case returns the default NaN,
139
+ * but (inf,zero,snan) returns the input NaN.
140
+ */
141
+ rule = float_infzeronan_dnan_if_qnan;
142
+#elif defined(TARGET_MIPS)
143
+ if (snan_bit_is_one(status)) {
144
+ /*
145
+ * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
146
+ * case sets InvalidOp and returns the default NaN
147
+ */
148
+ rule = float_infzeronan_dnan_always;
149
+ } else {
150
+ /*
151
+ * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
152
+ * case sets InvalidOp and returns the input value 'c'
153
+ */
154
+ rule = float_infzeronan_dnan_never;
155
+ }
156
+#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \
157
+ defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
158
+ defined(TARGET_I386) || defined(TARGET_LOONGARCH)
159
+ /*
160
+ * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
161
+ * case sets InvalidOp and returns the input value 'c'
162
+ */
163
+ /*
164
+ * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
165
+ * to return an input NaN if we have one (ie c) rather than generating
166
+ * a default NaN
167
+ */
168
+ rule = float_infzeronan_dnan_never;
169
+#elif defined(TARGET_S390X)
170
+ rule = float_infzeronan_dnan_always;
171
+#endif
172
}
173
174
+ if (infzero) {
175
+ /*
176
+ * Inf * 0 + NaN -- some implementations return the default NaN here,
177
+ * and some return the input NaN.
178
+ */
179
+ switch (rule) {
180
+ case float_infzeronan_dnan_never:
181
+ return 2;
182
+ case float_infzeronan_dnan_always:
183
+ return 3;
184
+ case float_infzeronan_dnan_if_qnan:
185
+ return is_qnan(c_cls) ? 3 : 2;
186
+ default:
187
+ g_assert_not_reached();
60
+ }
188
+ }
61
+ }
189
+ }
62
+}
190
+
63
+
191
+#if defined(TARGET_ARM)
64
static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
192
+
65
{
193
/* This looks different from the ARM ARM pseudocode, because the ARM ARM
66
uint64_t ret;
194
* puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
67
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
195
*/
68
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
196
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
69
.writefn = pmovsr_write,
197
}
70
.raw_writefn = raw_write },
198
#elif defined(TARGET_MIPS)
71
- /* Unimplemented so WI. */
199
if (snan_bit_is_one(status)) {
72
{ .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
200
- /*
73
- .access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NOP },
201
- * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
74
+ .access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NO_RAW,
202
- * case sets InvalidOp and returns the default NaN
75
+ .writefn = pmswinc_write },
203
- */
76
+ { .name = "PMSWINC_EL0", .state = ARM_CP_STATE_AA64,
204
- if (infzero) {
77
+ .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 4,
205
- return 3;
78
+ .access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NO_RAW,
206
- }
79
+ .writefn = pmswinc_write },
207
/* Prefer sNaN over qNaN, in the a, b, c order. */
80
{ .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
208
if (is_snan(a_cls)) {
81
.access = PL0_RW, .type = ARM_CP_ALIAS,
209
return 0;
82
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr),
210
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
211
return 2;
212
}
213
} else {
214
- /*
215
- * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
216
- * case sets InvalidOp and returns the input value 'c'
217
- */
218
/* Prefer sNaN over qNaN, in the c, a, b order. */
219
if (is_snan(c_cls)) {
220
return 2;
221
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
222
}
223
}
224
#elif defined(TARGET_LOONGARCH64)
225
- /*
226
- * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
227
- * case sets InvalidOp and returns the input value 'c'
228
- */
229
-
230
/* Prefer sNaN over qNaN, in the c, a, b order. */
231
if (is_snan(c_cls)) {
232
return 2;
233
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
234
return 1;
235
}
236
#elif defined(TARGET_PPC)
237
- /* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
238
- * to return an input NaN if we have one (ie c) rather than generating
239
- * a default NaN
240
- */
241
-
242
/* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
243
* otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
244
*/
245
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
246
return 1;
247
}
248
#elif defined(TARGET_S390X)
249
- if (infzero) {
250
- return 3;
251
- }
252
-
253
if (is_snan(a_cls)) {
254
return 0;
255
} else if (is_snan(b_cls)) {
83
--
256
--
84
2.20.1
257
2.34.1
85
86
diff view generated by jsdifflib
New patch
[PULL 09/72] tests/fp: Explicitly set inf-zero-nan rule
1
Explicitly set a rule in the softfloat tests for the inf-zero-nan
2
muladd special case. In meson.build we put -DTARGET_ARM in fpcflags,
3
and so we should select here the Arm rule of
4
float_infzeronan_dnan_if_qnan.
1
5
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20241202131347.498124-5-peter.maydell@linaro.org
9
---
10
tests/fp/fp-bench.c | 5 +++++
11
tests/fp/fp-test.c | 5 +++++
12
2 files changed, 10 insertions(+)
13
14
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
15
index XXXXXXX..XXXXXXX 100644
16
--- a/tests/fp/fp-bench.c
17
+++ b/tests/fp/fp-bench.c
18
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
19
{
20
bench_func_t f;
21
22
+ /*
23
+ * These implementation-defined choices for various things IEEE
24
+ * doesn't specify match those used by the Arm architecture.
25
+ */
26
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
27
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
28
29
f = bench_funcs[operation][precision];
30
g_assert(f);
31
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
32
index XXXXXXX..XXXXXXX 100644
33
--- a/tests/fp/fp-test.c
34
+++ b/tests/fp/fp-test.c
35
@@ -XXX,XX +XXX,XX @@ void run_test(void)
36
{
37
unsigned int i;
38
39
+ /*
40
+ * These implementation-defined choices for various things IEEE
41
+ * doesn't specify match those used by the Arm architecture.
42
+ */
43
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
44
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
45
46
genCases_setLevel(test_level);
47
verCases_maxErrorCount = n_max_errors;
48
--
49
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 34/49] target/arm: Enable PAuth for user-only
[PULL 10/72] target/arm: Set FloatInfZeroNaNRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the FloatInfZeroNaNRule explicitly for the Arm target,
2
so we can remove the ifdef from pickNaNMulAdd().
2
3
3
Add 4 attributes that controls the EL1 enable bits, as we may not
4
always want to turn on pointer authentication with -cpu max.
5
However, by default they are enabled.
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20190108223129.5570-31-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-6-peter.maydell@linaro.org
11
---
7
---
12
target/arm/cpu.c | 3 +++
8
target/arm/cpu.c | 3 +++
13
target/arm/cpu64.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++
9
fpu/softfloat-specialize.c.inc | 8 +-------
14
2 files changed, 63 insertions(+)
10
2 files changed, 4 insertions(+), 7 deletions(-)
15
11
16
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
12
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
17
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu.c
14
--- a/target/arm/cpu.c
19
+++ b/target/arm/cpu.c
15
+++ b/target/arm/cpu.c
20
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_reset(CPUState *s)
16
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
21
env->pstate = PSTATE_MODE_EL0t;
17
* * tininess-before-rounding
22
/* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
18
* * 2-input NaN propagation prefers SNaN over QNaN, and then
23
env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
19
* operand A over operand B (see FPProcessNaNs() pseudocode)
24
+ /* Enable all PAC instructions */
20
+ * * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
25
+ env->cp15.hcr_el2 |= HCR_API;
21
+ * and the input NaN if it is signalling
26
+ env->cp15.scr_el3 |= SCR_API;
22
*/
27
/* and to the FP/Neon instructions */
23
static void arm_set_default_fp_behaviours(float_status *s)
28
env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
24
{
29
/* and to the SVE instructions */
25
set_float_detect_tininess(float_tininess_before_rounding, s);
30
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
26
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
27
+ set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
28
}
29
30
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
31
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
31
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
32
--- a/target/arm/cpu64.c
33
--- a/fpu/softfloat-specialize.c.inc
33
+++ b/target/arm/cpu64.c
34
+++ b/fpu/softfloat-specialize.c.inc
34
@@ -XXX,XX +XXX,XX @@ static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name,
35
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
35
error_propagate(errp, err);
36
/*
36
}
37
* Temporarily fall back to ifdef ladder
37
38
+#ifdef CONFIG_USER_ONLY
39
+static void cpu_max_get_packey(Object *obj, Visitor *v, const char *name,
40
+ void *opaque, Error **errp)
41
+{
42
+ ARMCPU *cpu = ARM_CPU(obj);
43
+ const uint64_t *bit = opaque;
44
+ bool enabled = (cpu->env.cp15.sctlr_el[1] & *bit) != 0;
45
+
46
+ visit_type_bool(v, name, &enabled, errp);
47
+}
48
+
49
+static void cpu_max_set_packey(Object *obj, Visitor *v, const char *name,
50
+ void *opaque, Error **errp)
51
+{
52
+ ARMCPU *cpu = ARM_CPU(obj);
53
+ Error *err = NULL;
54
+ const uint64_t *bit = opaque;
55
+ bool enabled;
56
+
57
+ visit_type_bool(v, name, &enabled, errp);
58
+
59
+ if (!err) {
60
+ if (enabled) {
61
+ cpu->env.cp15.sctlr_el[1] |= *bit;
62
+ } else {
63
+ cpu->env.cp15.sctlr_el[1] &= ~*bit;
64
+ }
65
+ }
66
+ error_propagate(errp, err);
67
+}
68
+#endif
69
+
70
/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
71
* otherwise, a CPU with as many features enabled as our emulation supports.
72
* The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
73
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
74
*/
38
*/
75
cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
39
-#if defined(TARGET_ARM)
76
cpu->dcz_blocksize = 7; /* 512 bytes */
40
- /*
77
+
41
- * For ARM, the (inf,zero,qnan) case returns the default NaN,
78
+ /*
42
- * but (inf,zero,snan) returns the input NaN.
79
+ * Note that Linux will enable enable all of the keys at once.
43
- */
80
+ * But doing it this way will allow experimentation beyond that.
44
- rule = float_infzeronan_dnan_if_qnan;
81
+ */
45
-#elif defined(TARGET_MIPS)
82
+ {
46
+#if defined(TARGET_MIPS)
83
+ static const uint64_t apia_bit = SCTLR_EnIA;
47
if (snan_bit_is_one(status)) {
84
+ static const uint64_t apib_bit = SCTLR_EnIB;
48
/*
85
+ static const uint64_t apda_bit = SCTLR_EnDA;
49
* For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
86
+ static const uint64_t apdb_bit = SCTLR_EnDB;
87
+
88
+ object_property_add(obj, "apia", "bool", cpu_max_get_packey,
89
+ cpu_max_set_packey, NULL,
90
+ (void *)&apia_bit, &error_fatal);
91
+ object_property_add(obj, "apib", "bool", cpu_max_get_packey,
92
+ cpu_max_set_packey, NULL,
93
+ (void *)&apib_bit, &error_fatal);
94
+ object_property_add(obj, "apda", "bool", cpu_max_get_packey,
95
+ cpu_max_set_packey, NULL,
96
+ (void *)&apda_bit, &error_fatal);
97
+ object_property_add(obj, "apdb", "bool", cpu_max_get_packey,
98
+ cpu_max_set_packey, NULL,
99
+ (void *)&apdb_bit, &error_fatal);
100
+
101
+ /* Enable all PAC keys by default. */
102
+ cpu->env.cp15.sctlr_el[1] |= SCTLR_EnIA | SCTLR_EnIB;
103
+ cpu->env.cp15.sctlr_el[1] |= SCTLR_EnDA | SCTLR_EnDB;
104
+ }
105
#endif
106
107
cpu->sve_max_vq = ARM_MAX_VQ;
108
--
50
--
109
2.20.1
51
2.34.1
110
111
diff view generated by jsdifflib
New patch
[PULL 11/72] target/s390: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for s390, so we
2
can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-7-peter.maydell@linaro.org
7
---
8
target/s390x/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 2 insertions(+), 2 deletions(-)
11
12
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/s390x/cpu.c
15
+++ b/target/s390x/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
17
set_float_detect_tininess(float_tininess_before_rounding,
18
&env->fpu_status);
19
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status);
20
+ set_float_infzeronan_rule(float_infzeronan_dnan_always,
21
+ &env->fpu_status);
22
/* fall through */
23
case RESET_TYPE_S390_CPU_NORMAL:
24
env->psw.mask &= ~PSW_MASK_RI;
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
* a default NaN
31
*/
32
rule = float_infzeronan_dnan_never;
33
-#elif defined(TARGET_S390X)
34
- rule = float_infzeronan_dnan_always;
35
#endif
36
}
37
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 12/72] target/ppc: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the PPC target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-8-peter.maydell@linaro.org
7
---
8
target/ppc/cpu_init.c | 7 +++++++
9
fpu/softfloat-specialize.c.inc | 7 +------
10
2 files changed, 8 insertions(+), 6 deletions(-)
11
12
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/ppc/cpu_init.c
15
+++ b/target/ppc/cpu_init.c
16
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status);
20
+ /*
21
+ * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
22
+ * to return an input NaN if we have one (ie c) rather than generating
23
+ * a default NaN
24
+ */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
26
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status);
27
28
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
29
ppc_spr_t *spr = &env->spr_cb[i];
30
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
31
index XXXXXXX..XXXXXXX 100644
32
--- a/fpu/softfloat-specialize.c.inc
33
+++ b/fpu/softfloat-specialize.c.inc
34
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
35
*/
36
rule = float_infzeronan_dnan_never;
37
}
38
-#elif defined(TARGET_PPC) || defined(TARGET_SPARC) || \
39
+#elif defined(TARGET_SPARC) || \
40
defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
41
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
42
/*
43
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
44
* case sets InvalidOp and returns the input value 'c'
45
*/
46
- /*
47
- * For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
48
- * to return an input NaN if we have one (ie c) rather than generating
49
- * a default NaN
50
- */
51
rule = float_infzeronan_dnan_never;
52
#endif
53
}
54
--
55
2.34.1
diff view generated by jsdifflib
New patch
[PULL 13/72] target/mips: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the MIPS target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-9-peter.maydell@linaro.org
7
---
8
target/mips/fpu_helper.h | 9 +++++++++
9
target/mips/msa.c | 4 ++++
10
fpu/softfloat-specialize.c.inc | 16 +---------------
11
3 files changed, 14 insertions(+), 15 deletions(-)
12
13
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
14
index XXXXXXX..XXXXXXX 100644
15
--- a/target/mips/fpu_helper.h
16
+++ b/target/mips/fpu_helper.h
17
@@ -XXX,XX +XXX,XX @@ static inline void restore_flush_mode(CPUMIPSState *env)
18
static inline void restore_snan_bit_mode(CPUMIPSState *env)
19
{
20
bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008);
21
+ FloatInfZeroNaNRule izn_rule;
22
23
/*
24
* With nan2008, SNaNs are silenced in the usual way.
25
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
26
*/
27
set_snan_bit_is_one(!nan2008, &env->active_fpu.fp_status);
28
set_default_nan_mode(!nan2008, &env->active_fpu.fp_status);
29
+ /*
30
+ * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
31
+ * case sets InvalidOp and returns the default NaN.
32
+ * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
33
+ * case sets InvalidOp and returns the input value 'c'.
34
+ */
35
+ izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always;
36
+ set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
37
}
38
39
static inline void restore_fp_status(CPUMIPSState *env)
40
diff --git a/target/mips/msa.c b/target/mips/msa.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/mips/msa.c
43
+++ b/target/mips/msa.c
44
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
45
46
/* set proper signanling bit meaning ("1" means "quiet") */
47
set_snan_bit_is_one(0, &env->active_tc.msa_fp_status);
48
+
49
+ /* Inf * 0 + NaN returns the input NaN */
50
+ set_float_infzeronan_rule(float_infzeronan_dnan_never,
51
+ &env->active_tc.msa_fp_status);
52
}
53
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
54
index XXXXXXX..XXXXXXX 100644
55
--- a/fpu/softfloat-specialize.c.inc
56
+++ b/fpu/softfloat-specialize.c.inc
57
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
58
/*
59
* Temporarily fall back to ifdef ladder
60
*/
61
-#if defined(TARGET_MIPS)
62
- if (snan_bit_is_one(status)) {
63
- /*
64
- * For MIPS systems that conform to IEEE754-1985, the (inf,zero,nan)
65
- * case sets InvalidOp and returns the default NaN
66
- */
67
- rule = float_infzeronan_dnan_always;
68
- } else {
69
- /*
70
- * For MIPS systems that conform to IEEE754-2008, the (inf,zero,nan)
71
- * case sets InvalidOp and returns the input value 'c'
72
- */
73
- rule = float_infzeronan_dnan_never;
74
- }
75
-#elif defined(TARGET_SPARC) || \
76
+#if defined(TARGET_SPARC) || \
77
defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
78
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
79
/*
80
--
81
2.34.1
diff view generated by jsdifflib
New patch
[PULL 14/72] target/sparc: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the SPARC target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-10-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 +--
10
2 files changed, 3 insertions(+), 2 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
* the CPU state struct so it won't get zeroed on reset.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status);
20
+ /* For inf * 0 + NaN, return the input NaN */
21
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
22
23
cpu_exec_realizefn(cs, &local_err);
24
if (local_err != NULL) {
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
/*
31
* Temporarily fall back to ifdef ladder
32
*/
33
-#if defined(TARGET_SPARC) || \
34
- defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
35
+#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
36
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
37
/*
38
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
39
--
40
2.34.1
diff view generated by jsdifflib
New patch
[PULL 15/72] target/xtensa: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the xtensa target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-11-peter.maydell@linaro.org
7
---
8
target/xtensa/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 +-
10
2 files changed, 3 insertions(+), 1 deletion(-)
11
12
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/xtensa/cpu.c
15
+++ b/target/xtensa/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
17
reset_mmu(env);
18
cs->halted = env->runstall;
19
#endif
20
+ /* For inf * 0 + NaN, return the input NaN */
21
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
22
set_no_signaling_nans(!dfpu, &env->fp_status);
23
xtensa_use_first_nan(env, !dfpu);
24
}
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
/*
31
* Temporarily fall back to ifdef ladder
32
*/
33
-#if defined(TARGET_XTENSA) || defined(TARGET_HPPA) || \
34
+#if defined(TARGET_HPPA) || \
35
defined(TARGET_I386) || defined(TARGET_LOONGARCH)
36
/*
37
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
38
--
39
2.34.1
diff view generated by jsdifflib
New patch
[PULL 16/72] target/x86: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the x86 target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-12-peter.maydell@linaro.org
6
---
7
target/i386/tcg/fpu_helper.c | 7 +++++++
8
fpu/softfloat-specialize.c.inc | 2 +-
9
2 files changed, 8 insertions(+), 1 deletion(-)
10
11
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/i386/tcg/fpu_helper.c
14
+++ b/target/i386/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
16
*/
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->mmx_status);
18
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->sse_status);
19
+ /*
20
+ * Only SSE has multiply-add instructions. In the SDM Section 14.5.2
21
+ * "Fused-Multiply-ADD (FMA) Numeric Behavior" the NaN handling is
22
+ * specified -- for 0 * inf + NaN the input NaN is selected, and if
23
+ * there are multiple input NaNs they are selected in the order a, b, c.
24
+ */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
26
}
27
28
static inline uint8_t save_exception_flags(CPUX86State *env)
29
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
30
index XXXXXXX..XXXXXXX 100644
31
--- a/fpu/softfloat-specialize.c.inc
32
+++ b/fpu/softfloat-specialize.c.inc
33
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
34
* Temporarily fall back to ifdef ladder
35
*/
36
#if defined(TARGET_HPPA) || \
37
- defined(TARGET_I386) || defined(TARGET_LOONGARCH)
38
+ defined(TARGET_LOONGARCH)
39
/*
40
* For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
41
* case sets InvalidOp and returns the input value 'c'
42
--
43
2.34.1
diff view generated by jsdifflib
New patch
[PULL 17/72] target/loongarch: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the loongarch target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-13-peter.maydell@linaro.org
6
---
7
target/loongarch/tcg/fpu_helper.c | 5 +++++
8
fpu/softfloat-specialize.c.inc | 7 +------
9
2 files changed, 6 insertions(+), 6 deletions(-)
10
11
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/loongarch/tcg/fpu_helper.c
14
+++ b/target/loongarch/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
16
&env->fp_status);
17
set_flush_to_zero(0, &env->fp_status);
18
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
19
+ /*
20
+ * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
21
+ * case sets InvalidOp and returns the input value 'c'
22
+ */
23
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
24
}
25
26
int ieee_ex_to_loongarch(int xcpt)
27
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
28
index XXXXXXX..XXXXXXX 100644
29
--- a/fpu/softfloat-specialize.c.inc
30
+++ b/fpu/softfloat-specialize.c.inc
31
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
32
/*
33
* Temporarily fall back to ifdef ladder
34
*/
35
-#if defined(TARGET_HPPA) || \
36
- defined(TARGET_LOONGARCH)
37
- /*
38
- * For LoongArch systems that conform to IEEE754-2008, the (inf,zero,nan)
39
- * case sets InvalidOp and returns the input value 'c'
40
- */
41
+#if defined(TARGET_HPPA)
42
rule = float_infzeronan_dnan_never;
43
#endif
44
}
45
--
46
2.34.1
diff view generated by jsdifflib
New patch
[PULL 18/72] target/hppa: Set FloatInfZeroNaNRule explicitly
1
Set the FloatInfZeroNaNRule explicitly for the HPPA target,
2
so we can remove the ifdef from pickNaNMulAdd().
1
3
4
As this is the last target to be converted to explicitly setting
5
the rule, we can remove the fallback code in pickNaNMulAdd()
6
entirely.
7
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
10
Message-id: 20241202131347.498124-14-peter.maydell@linaro.org
11
---
12
target/hppa/fpu_helper.c | 2 ++
13
fpu/softfloat-specialize.c.inc | 13 +------------
14
2 files changed, 3 insertions(+), 12 deletions(-)
15
16
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/hppa/fpu_helper.c
19
+++ b/target/hppa/fpu_helper.c
20
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
21
* HPPA does note implement a CPU reset method at all...
22
*/
23
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
24
+ /* For inf * 0 + NaN, return the input NaN */
25
+ set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
26
}
27
28
void cpu_hppa_loaded_fr0(CPUHPPAState *env)
29
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
30
index XXXXXXX..XXXXXXX 100644
31
--- a/fpu/softfloat-specialize.c.inc
32
+++ b/fpu/softfloat-specialize.c.inc
33
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
34
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
35
bool infzero, float_status *status)
36
{
37
- FloatInfZeroNaNRule rule = status->float_infzeronan_rule;
38
-
39
/*
40
* We guarantee not to require the target to tell us how to
41
* pick a NaN if we're always returning the default NaN.
42
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
43
*/
44
assert(!status->default_nan_mode);
45
46
- if (rule == float_infzeronan_none) {
47
- /*
48
- * Temporarily fall back to ifdef ladder
49
- */
50
-#if defined(TARGET_HPPA)
51
- rule = float_infzeronan_dnan_never;
52
-#endif
53
- }
54
-
55
if (infzero) {
56
/*
57
* Inf * 0 + NaN -- some implementations return the default NaN here,
58
* and some return the input NaN.
59
*/
60
- switch (rule) {
61
+ switch (status->float_infzeronan_rule) {
62
case float_infzeronan_dnan_never:
63
return 2;
64
case float_infzeronan_dnan_always:
65
--
66
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/49] target/arm: Rearrange decode in disas_data_proc_1src
[PULL 19/72] softfloat: Pass have_snan to pickNaNMulAdd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The new implementation of pickNaNMulAdd() will find it convenient
2
to know whether at least one of the three arguments to the muladd
3
was a signaling NaN. We already calculate that in the caller,
4
so pass it in as a new bool have_snan.
2
5
3
Now properly signals unallocated for REV64 with SF=0.
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Allows for the opcode2 field to be decoded shortly.
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-15-peter.maydell@linaro.org
9
---
10
fpu/softfloat-parts.c.inc | 5 +++--
11
fpu/softfloat-specialize.c.inc | 2 +-
12
2 files changed, 4 insertions(+), 3 deletions(-)
5
13
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20190108223129.5570-8-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/translate-a64.c | 31 ++++++++++++++++++++++---------
12
1 file changed, 22 insertions(+), 9 deletions(-)
13
14
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/translate-a64.c
16
--- a/fpu/softfloat-parts.c.inc
17
+++ b/target/arm/translate-a64.c
17
+++ b/fpu/softfloat-parts.c.inc
18
@@ -XXX,XX +XXX,XX @@ static void handle_rev16(DisasContext *s, unsigned int sf,
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
19
*/
20
static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
21
{
19
{
22
- unsigned int sf, opcode, rn, rd;
20
int which;
23
+ unsigned int sf, opcode, opcode2, rn, rd;
21
bool infzero = (ab_mask == float_cmask_infzero);
24
22
+ bool have_snan = (abc_mask & float_cmask_snan);
25
- if (extract32(insn, 29, 1) || extract32(insn, 16, 5)) {
23
26
+ if (extract32(insn, 29, 1)) {
24
- if (unlikely(abc_mask & float_cmask_snan)) {
27
unallocated_encoding(s);
25
+ if (unlikely(have_snan)) {
28
return;
26
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
29
}
27
}
30
28
31
sf = extract32(insn, 31, 1);
29
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
32
opcode = extract32(insn, 10, 6);
30
if (s->default_nan_mode) {
33
+ opcode2 = extract32(insn, 16, 5);
31
which = 3;
34
rn = extract32(insn, 5, 5);
32
} else {
35
rd = extract32(insn, 0, 5);
33
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, s);
36
34
+ which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s);
37
- switch (opcode) {
38
- case 0: /* RBIT */
39
+#define MAP(SF, O2, O1) ((SF) | (O1 << 1) | (O2 << 7))
40
+
41
+ switch (MAP(sf, opcode2, opcode)) {
42
+ case MAP(0, 0x00, 0x00): /* RBIT */
43
+ case MAP(1, 0x00, 0x00):
44
handle_rbit(s, sf, rn, rd);
45
break;
46
- case 1: /* REV16 */
47
+ case MAP(0, 0x00, 0x01): /* REV16 */
48
+ case MAP(1, 0x00, 0x01):
49
handle_rev16(s, sf, rn, rd);
50
break;
51
- case 2: /* REV32 */
52
+ case MAP(0, 0x00, 0x02): /* REV/REV32 */
53
+ case MAP(1, 0x00, 0x02):
54
handle_rev32(s, sf, rn, rd);
55
break;
56
- case 3: /* REV64 */
57
+ case MAP(1, 0x00, 0x03): /* REV64 */
58
handle_rev64(s, sf, rn, rd);
59
break;
60
- case 4: /* CLZ */
61
+ case MAP(0, 0x00, 0x04): /* CLZ */
62
+ case MAP(1, 0x00, 0x04):
63
handle_clz(s, sf, rn, rd);
64
break;
65
- case 5: /* CLS */
66
+ case MAP(0, 0x00, 0x05): /* CLS */
67
+ case MAP(1, 0x00, 0x05):
68
handle_cls(s, sf, rn, rd);
69
break;
70
+ default:
71
+ unallocated_encoding(s);
72
+ break;
73
}
35
}
74
+
36
75
+#undef MAP
37
if (which == 3) {
76
}
38
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
77
39
index XXXXXXX..XXXXXXX 100644
78
static void handle_div(DisasContext *s, bool is_signed, unsigned int sf,
40
--- a/fpu/softfloat-specialize.c.inc
41
+++ b/fpu/softfloat-specialize.c.inc
42
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
43
| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
44
*----------------------------------------------------------------------------*/
45
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
46
- bool infzero, float_status *status)
47
+ bool infzero, bool have_snan, float_status *status)
48
{
49
/*
50
* We guarantee not to require the target to tell us how to
79
--
51
--
80
2.20.1
52
2.34.1
81
82
diff view generated by jsdifflib
[Qemu-devel] [PULL 32/49] target/arm: Add PAuth system registers
[PULL 20/72] softfloat: Allow runtime choice of NaN propagation for muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
IEEE 758 does not define a fixed rule for which NaN to pick as the
2
2
result if both operands of a 3-operand fused multiply-add operation
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
3
are NaNs. As a result different architectures have ended up with
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
4
different rules for propagating NaNs.
5
Message-id: 20190108223129.5570-29-richard.henderson@linaro.org
5
6
QEMU currently hardcodes the NaN propagation logic into the binary
7
because pickNaNMulAdd() has an ifdef ladder for different targets.
8
We want to make the propagation rule instead be selectable at
9
runtime, because:
10
* this will let us have multiple targets in one QEMU binary
11
* the Arm FEAT_AFP architectural feature includes letting
12
the guest select a NaN propagation rule at runtime
13
14
In this commit we add an enum for the propagation rule, the field in
15
float_status, and the corresponding getters and setters. We change
16
pickNaNMulAdd to honour this, but because all targets still leave
17
this field at its default 0 value, the fallback logic will pick the
18
rule type with the old ifdef ladder.
19
20
It's valid not to set a propagation rule if default_nan_mode is
21
enabled, because in that case there's no need to pick a NaN; all the
22
callers of pickNaNMulAdd() catch this case and skip calling it.
23
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
24
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
26
Message-id: 20241202131347.498124-16-peter.maydell@linaro.org
7
---
27
---
8
target/arm/helper.c | 70 +++++++++++++++++++++++++++++++++++++++++++++
28
include/fpu/softfloat-helpers.h | 11 +++
9
1 file changed, 70 insertions(+)
29
include/fpu/softfloat-types.h | 55 +++++++++++
10
30
fpu/softfloat-specialize.c.inc | 167 ++++++++------------------------
11
diff --git a/target/arm/helper.c b/target/arm/helper.c
31
3 files changed, 107 insertions(+), 126 deletions(-)
32
33
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
12
index XXXXXXX..XXXXXXX 100644
34
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/helper.c
35
--- a/include/fpu/softfloat-helpers.h
14
+++ b/target/arm/helper.c
36
+++ b/include/fpu/softfloat-helpers.h
15
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_lor_other(CPUARMState *env,
37
@@ -XXX,XX +XXX,XX @@ static inline void set_float_2nan_prop_rule(Float2NaNPropRule rule,
16
return access_lor_ns(env);
38
status->float_2nan_prop_rule = rule;
17
}
39
}
18
40
19
+#ifdef TARGET_AARCH64
41
+static inline void set_float_3nan_prop_rule(Float3NaNPropRule rule,
20
+static CPAccessResult access_pauth(CPUARMState *env, const ARMCPRegInfo *ri,
42
+ float_status *status)
21
+ bool isread)
22
+{
43
+{
23
+ int el = arm_current_el(env);
44
+ status->float_3nan_prop_rule = rule;
24
+
25
+ if (el < 2 &&
26
+ arm_feature(env, ARM_FEATURE_EL2) &&
27
+ !(arm_hcr_el2_eff(env) & HCR_APK)) {
28
+ return CP_ACCESS_TRAP_EL2;
29
+ }
30
+ if (el < 3 &&
31
+ arm_feature(env, ARM_FEATURE_EL3) &&
32
+ !(env->cp15.scr_el3 & SCR_APK)) {
33
+ return CP_ACCESS_TRAP_EL3;
34
+ }
35
+ return CP_ACCESS_OK;
36
+}
45
+}
37
+
46
+
38
+static const ARMCPRegInfo pauth_reginfo[] = {
47
static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
39
+ { .name = "APDAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
48
float_status *status)
40
+ .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 0,
41
+ .access = PL1_RW, .accessfn = access_pauth,
42
+ .fieldoffset = offsetof(CPUARMState, apda_key.lo) },
43
+ { .name = "APDAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
44
+ .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 1,
45
+ .access = PL1_RW, .accessfn = access_pauth,
46
+ .fieldoffset = offsetof(CPUARMState, apda_key.hi) },
47
+ { .name = "APDBKEYLO_EL1", .state = ARM_CP_STATE_AA64,
48
+ .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 2,
49
+ .access = PL1_RW, .accessfn = access_pauth,
50
+ .fieldoffset = offsetof(CPUARMState, apdb_key.lo) },
51
+ { .name = "APDBKEYHI_EL1", .state = ARM_CP_STATE_AA64,
52
+ .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 2, .opc2 = 3,
53
+ .access = PL1_RW, .accessfn = access_pauth,
54
+ .fieldoffset = offsetof(CPUARMState, apdb_key.hi) },
55
+ { .name = "APGAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
56
+ .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 0,
57
+ .access = PL1_RW, .accessfn = access_pauth,
58
+ .fieldoffset = offsetof(CPUARMState, apga_key.lo) },
59
+ { .name = "APGAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
60
+ .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 3, .opc2 = 1,
61
+ .access = PL1_RW, .accessfn = access_pauth,
62
+ .fieldoffset = offsetof(CPUARMState, apga_key.hi) },
63
+ { .name = "APIAKEYLO_EL1", .state = ARM_CP_STATE_AA64,
64
+ .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 0,
65
+ .access = PL1_RW, .accessfn = access_pauth,
66
+ .fieldoffset = offsetof(CPUARMState, apia_key.lo) },
67
+ { .name = "APIAKEYHI_EL1", .state = ARM_CP_STATE_AA64,
68
+ .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 1,
69
+ .access = PL1_RW, .accessfn = access_pauth,
70
+ .fieldoffset = offsetof(CPUARMState, apia_key.hi) },
71
+ { .name = "APIBKEYLO_EL1", .state = ARM_CP_STATE_AA64,
72
+ .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 2,
73
+ .access = PL1_RW, .accessfn = access_pauth,
74
+ .fieldoffset = offsetof(CPUARMState, apib_key.lo) },
75
+ { .name = "APIBKEYHI_EL1", .state = ARM_CP_STATE_AA64,
76
+ .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 1, .opc2 = 3,
77
+ .access = PL1_RW, .accessfn = access_pauth,
78
+ .fieldoffset = offsetof(CPUARMState, apib_key.hi) },
79
+ REGINFO_SENTINEL
80
+};
81
+#endif
82
+
83
void register_cp_regs_for_features(ARMCPU *cpu)
84
{
49
{
85
/* Register all the coprocessor registers based on feature bits */
50
@@ -XXX,XX +XXX,XX @@ static inline Float2NaNPropRule get_float_2nan_prop_rule(float_status *status)
86
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
51
return status->float_2nan_prop_rule;
87
define_one_arm_cp_reg(cpu, &zcr_el3_reginfo);
52
}
53
54
+static inline Float3NaNPropRule get_float_3nan_prop_rule(float_status *status)
55
+{
56
+ return status->float_3nan_prop_rule;
57
+}
58
+
59
static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status)
60
{
61
return status->float_infzeronan_rule;
62
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
63
index XXXXXXX..XXXXXXX 100644
64
--- a/include/fpu/softfloat-types.h
65
+++ b/include/fpu/softfloat-types.h
66
@@ -XXX,XX +XXX,XX @@ this code that are retained.
67
#ifndef SOFTFLOAT_TYPES_H
68
#define SOFTFLOAT_TYPES_H
69
70
+#include "hw/registerfields.h"
71
+
72
/*
73
* Software IEC/IEEE floating-point types.
74
*/
75
@@ -XXX,XX +XXX,XX @@ typedef enum __attribute__((__packed__)) {
76
float_2nan_prop_x87,
77
} Float2NaNPropRule;
78
79
+/*
80
+ * 3-input NaN propagation rule, for fused multiply-add. Individual
81
+ * architectures have different rules for which input NaN is
82
+ * propagated to the output when there is more than one NaN on the
83
+ * input.
84
+ *
85
+ * If default_nan_mode is enabled then it is valid not to set a NaN
86
+ * propagation rule, because the softfloat code guarantees not to try
87
+ * to pick a NaN to propagate in default NaN mode. When not in
88
+ * default-NaN mode, it is an error for the target not to set the rule
89
+ * in float_status if it uses a muladd, and we will assert if we need
90
+ * to handle an input NaN and no rule was selected.
91
+ *
92
+ * The naming scheme for Float3NaNPropRule values is:
93
+ * float_3nan_prop_s_abc:
94
+ * = "Prefer SNaN over QNaN, then operand A over B over C"
95
+ * float_3nan_prop_abc:
96
+ * = "Prefer A over B over C regardless of SNaN vs QNAN"
97
+ *
98
+ * For QEMU, the multiply-add operation is A * B + C.
99
+ */
100
+
101
+/*
102
+ * We set the Float3NaNPropRule enum values up so we can select the
103
+ * right value in pickNaNMulAdd in a data driven way.
104
+ */
105
+FIELD(3NAN, 1ST, 0, 2) /* which operand is most preferred ? */
106
+FIELD(3NAN, 2ND, 2, 2) /* which operand is next most preferred ? */
107
+FIELD(3NAN, 3RD, 4, 2) /* which operand is least preferred ? */
108
+FIELD(3NAN, SNAN, 6, 1) /* do we prefer SNaN over QNaN ? */
109
+
110
+#define PROPRULE(X, Y, Z) \
111
+ ((X << R_3NAN_1ST_SHIFT) | (Y << R_3NAN_2ND_SHIFT) | (Z << R_3NAN_3RD_SHIFT))
112
+
113
+typedef enum __attribute__((__packed__)) {
114
+ float_3nan_prop_none = 0, /* No propagation rule specified */
115
+ float_3nan_prop_abc = PROPRULE(0, 1, 2),
116
+ float_3nan_prop_acb = PROPRULE(0, 2, 1),
117
+ float_3nan_prop_bac = PROPRULE(1, 0, 2),
118
+ float_3nan_prop_bca = PROPRULE(1, 2, 0),
119
+ float_3nan_prop_cab = PROPRULE(2, 0, 1),
120
+ float_3nan_prop_cba = PROPRULE(2, 1, 0),
121
+ float_3nan_prop_s_abc = float_3nan_prop_abc | R_3NAN_SNAN_MASK,
122
+ float_3nan_prop_s_acb = float_3nan_prop_acb | R_3NAN_SNAN_MASK,
123
+ float_3nan_prop_s_bac = float_3nan_prop_bac | R_3NAN_SNAN_MASK,
124
+ float_3nan_prop_s_bca = float_3nan_prop_bca | R_3NAN_SNAN_MASK,
125
+ float_3nan_prop_s_cab = float_3nan_prop_cab | R_3NAN_SNAN_MASK,
126
+ float_3nan_prop_s_cba = float_3nan_prop_cba | R_3NAN_SNAN_MASK,
127
+} Float3NaNPropRule;
128
+
129
+#undef PROPRULE
130
+
131
/*
132
* Rule for result of fused multiply-add 0 * Inf + NaN.
133
* This must be a NaN, but implementations differ on whether this
134
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
135
FloatRoundMode float_rounding_mode;
136
FloatX80RoundPrec floatx80_rounding_precision;
137
Float2NaNPropRule float_2nan_prop_rule;
138
+ Float3NaNPropRule float_3nan_prop_rule;
139
FloatInfZeroNaNRule float_infzeronan_rule;
140
bool tininess_before_rounding;
141
/* should denormalised results go to zero and set the inexact flag? */
142
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
143
index XXXXXXX..XXXXXXX 100644
144
--- a/fpu/softfloat-specialize.c.inc
145
+++ b/fpu/softfloat-specialize.c.inc
146
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
147
static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
148
bool infzero, bool have_snan, float_status *status)
149
{
150
+ FloatClass cls[3] = { a_cls, b_cls, c_cls };
151
+ Float3NaNPropRule rule = status->float_3nan_prop_rule;
152
+ int which;
153
+
154
/*
155
* We guarantee not to require the target to tell us how to
156
* pick a NaN if we're always returning the default NaN.
157
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
88
}
158
}
89
}
159
}
90
+
160
91
+#ifdef TARGET_AARCH64
161
+ if (rule == float_3nan_prop_none) {
92
+ if (cpu_isar_feature(aa64_pauth, cpu)) {
162
#if defined(TARGET_ARM)
93
+ define_arm_cp_regs(cpu, pauth_reginfo);
163
-
164
- /* This looks different from the ARM ARM pseudocode, because the ARM ARM
165
- * puts the operands to a fused mac operation (a*b)+c in the order c,a,b.
166
- */
167
- if (is_snan(c_cls)) {
168
- return 2;
169
- } else if (is_snan(a_cls)) {
170
- return 0;
171
- } else if (is_snan(b_cls)) {
172
- return 1;
173
- } else if (is_qnan(c_cls)) {
174
- return 2;
175
- } else if (is_qnan(a_cls)) {
176
- return 0;
177
- } else {
178
- return 1;
179
- }
180
+ /*
181
+ * This looks different from the ARM ARM pseudocode, because the ARM ARM
182
+ * puts the operands to a fused mac operation (a*b)+c in the order c,a,b
183
+ */
184
+ rule = float_3nan_prop_s_cab;
185
#elif defined(TARGET_MIPS)
186
- if (snan_bit_is_one(status)) {
187
- /* Prefer sNaN over qNaN, in the a, b, c order. */
188
- if (is_snan(a_cls)) {
189
- return 0;
190
- } else if (is_snan(b_cls)) {
191
- return 1;
192
- } else if (is_snan(c_cls)) {
193
- return 2;
194
- } else if (is_qnan(a_cls)) {
195
- return 0;
196
- } else if (is_qnan(b_cls)) {
197
- return 1;
198
+ if (snan_bit_is_one(status)) {
199
+ rule = float_3nan_prop_s_abc;
200
} else {
201
- return 2;
202
+ rule = float_3nan_prop_s_cab;
203
}
204
- } else {
205
- /* Prefer sNaN over qNaN, in the c, a, b order. */
206
- if (is_snan(c_cls)) {
207
- return 2;
208
- } else if (is_snan(a_cls)) {
209
- return 0;
210
- } else if (is_snan(b_cls)) {
211
- return 1;
212
- } else if (is_qnan(c_cls)) {
213
- return 2;
214
- } else if (is_qnan(a_cls)) {
215
- return 0;
216
- } else {
217
- return 1;
218
- }
219
- }
220
#elif defined(TARGET_LOONGARCH64)
221
- /* Prefer sNaN over qNaN, in the c, a, b order. */
222
- if (is_snan(c_cls)) {
223
- return 2;
224
- } else if (is_snan(a_cls)) {
225
- return 0;
226
- } else if (is_snan(b_cls)) {
227
- return 1;
228
- } else if (is_qnan(c_cls)) {
229
- return 2;
230
- } else if (is_qnan(a_cls)) {
231
- return 0;
232
- } else {
233
- return 1;
234
- }
235
+ rule = float_3nan_prop_s_cab;
236
#elif defined(TARGET_PPC)
237
- /* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
238
- * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
239
- */
240
- if (is_nan(a_cls)) {
241
- return 0;
242
- } else if (is_nan(c_cls)) {
243
- return 2;
244
- } else {
245
- return 1;
246
- }
247
+ /*
248
+ * If fRA is a NaN return it; otherwise if fRB is a NaN return it;
249
+ * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
250
+ */
251
+ rule = float_3nan_prop_acb;
252
#elif defined(TARGET_S390X)
253
- if (is_snan(a_cls)) {
254
- return 0;
255
- } else if (is_snan(b_cls)) {
256
- return 1;
257
- } else if (is_snan(c_cls)) {
258
- return 2;
259
- } else if (is_qnan(a_cls)) {
260
- return 0;
261
- } else if (is_qnan(b_cls)) {
262
- return 1;
263
- } else {
264
- return 2;
265
- }
266
+ rule = float_3nan_prop_s_abc;
267
#elif defined(TARGET_SPARC)
268
- /* Prefer SNaN over QNaN, order C, B, A. */
269
- if (is_snan(c_cls)) {
270
- return 2;
271
- } else if (is_snan(b_cls)) {
272
- return 1;
273
- } else if (is_snan(a_cls)) {
274
- return 0;
275
- } else if (is_qnan(c_cls)) {
276
- return 2;
277
- } else if (is_qnan(b_cls)) {
278
- return 1;
279
- } else {
280
- return 0;
281
- }
282
+ rule = float_3nan_prop_s_cba;
283
#elif defined(TARGET_XTENSA)
284
- /*
285
- * For Xtensa, the (inf,zero,nan) case sets InvalidOp and returns
286
- * an input NaN if we have one (ie c).
287
- */
288
- if (status->use_first_nan) {
289
- if (is_nan(a_cls)) {
290
- return 0;
291
- } else if (is_nan(b_cls)) {
292
- return 1;
293
+ if (status->use_first_nan) {
294
+ rule = float_3nan_prop_abc;
295
} else {
296
- return 2;
297
+ rule = float_3nan_prop_cba;
298
}
299
- } else {
300
- if (is_nan(c_cls)) {
301
- return 2;
302
- } else if (is_nan(b_cls)) {
303
- return 1;
304
- } else {
305
- return 0;
306
- }
307
- }
308
#else
309
- /* A default implementation: prefer a to b to c.
310
- * This is unlikely to actually match any real implementation.
311
- */
312
- if (is_nan(a_cls)) {
313
- return 0;
314
- } else if (is_nan(b_cls)) {
315
- return 1;
316
- } else {
317
- return 2;
318
- }
319
+ rule = float_3nan_prop_abc;
320
#endif
94
+ }
321
+ }
95
+#endif
322
+
323
+ assert(rule != float_3nan_prop_none);
324
+ if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
325
+ /* We have at least one SNaN input and should prefer it */
326
+ do {
327
+ which = rule & R_3NAN_1ST_MASK;
328
+ rule >>= R_3NAN_1ST_LENGTH;
329
+ } while (!is_snan(cls[which]));
330
+ } else {
331
+ do {
332
+ which = rule & R_3NAN_1ST_MASK;
333
+ rule >>= R_3NAN_1ST_LENGTH;
334
+ } while (!is_nan(cls[which]));
335
+ }
336
+ return which;
96
}
337
}
97
338
98
void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
339
/*----------------------------------------------------------------------------
99
--
340
--
100
2.20.1
341
2.34.1
101
102
diff view generated by jsdifflib
New patch
[PULL 21/72] tests/fp: Explicitly set 3-NaN propagation rule
1
Explicitly set a rule in the softfloat tests for propagating NaNs in
2
the muladd case. In meson.build we put -DTARGET_ARM in fpcflags, and
3
so we should select here the Arm rule of float_3nan_prop_s_cab.
1
4
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-17-peter.maydell@linaro.org
8
---
9
tests/fp/fp-bench.c | 1 +
10
tests/fp/fp-test.c | 1 +
11
2 files changed, 2 insertions(+)
12
13
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
14
index XXXXXXX..XXXXXXX 100644
15
--- a/tests/fp/fp-bench.c
16
+++ b/tests/fp/fp-bench.c
17
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
18
* doesn't specify match those used by the Arm architecture.
19
*/
20
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
21
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status);
22
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
23
24
f = bench_funcs[operation][precision];
25
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
26
index XXXXXXX..XXXXXXX 100644
27
--- a/tests/fp/fp-test.c
28
+++ b/tests/fp/fp-test.c
29
@@ -XXX,XX +XXX,XX @@ void run_test(void)
30
* doesn't specify match those used by the Arm architecture.
31
*/
32
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
33
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf);
34
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
35
36
genCases_setLevel(test_level);
37
--
38
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 39/49] target/arm: Filter cycle counter based on PMCCFILTR_EL0
[PULL 22/72] target/arm: Set Float3NaNPropRule explicitly
1
From: Aaron Lindsay <aaron@os.amperecomputing.com>
1
Set the Float3NaNPropRule explicitly for Arm, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
Rename arm_ccnt_enabled to pmu_counter_enabled, and add logic to only
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
return 'true' if the specified counter is enabled and neither prohibited
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
or filtered.
6
Message-id: 20241202131347.498124-18-peter.maydell@linaro.org
7
---
8
target/arm/cpu.c | 5 +++++
9
fpu/softfloat-specialize.c.inc | 8 +-------
10
2 files changed, 6 insertions(+), 7 deletions(-)
6
11
7
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
8
Signed-off-by: Aaron Lindsay <aclindsa@gmail.com>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20181211151945.29137-5-aaron@os.amperecomputing.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/cpu.h | 10 ++++-
15
target/arm/cpu.c | 3 ++
16
target/arm/helper.c | 96 +++++++++++++++++++++++++++++++++++++++++----
17
3 files changed, 101 insertions(+), 8 deletions(-)
18
19
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/cpu.h
22
+++ b/target/arm/cpu.h
23
@@ -XXX,XX +XXX,XX @@ void pmccntr_op_finish(CPUARMState *env);
24
void pmu_op_start(CPUARMState *env);
25
void pmu_op_finish(CPUARMState *env);
26
27
+/**
28
+ * Functions to register as EL change hooks for PMU mode filtering
29
+ */
30
+void pmu_pre_el_change(ARMCPU *cpu, void *ignored);
31
+void pmu_post_el_change(ARMCPU *cpu, void *ignored);
32
+
33
/* SCTLR bit meanings. Several bits have been reused in newer
34
* versions of the architecture; in that case we define constants
35
* for both old and new bit meanings. Code which tests against those
36
@@ -XXX,XX +XXX,XX @@ void pmu_op_finish(CPUARMState *env);
37
38
#define MDCR_EPMAD (1U << 21)
39
#define MDCR_EDAD (1U << 20)
40
-#define MDCR_SPME (1U << 17)
41
+#define MDCR_SPME (1U << 17) /* MDCR_EL3 */
42
+#define MDCR_HPMD (1U << 17) /* MDCR_EL2 */
43
#define MDCR_SDD (1U << 16)
44
#define MDCR_SPD (3U << 14)
45
#define MDCR_TDRA (1U << 11)
46
@@ -XXX,XX +XXX,XX @@ void pmu_op_finish(CPUARMState *env);
47
#define MDCR_HPME (1U << 7)
48
#define MDCR_TPM (1U << 6)
49
#define MDCR_TPMCR (1U << 5)
50
+#define MDCR_HPMN (0x1fU)
51
52
/* Not all of the MDCR_EL3 bits are present in the 32-bit SDCR */
53
#define SDCR_VALID_MASK (MDCR_EPMAD | MDCR_EDAD | MDCR_SPME | MDCR_SPD)
54
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
12
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
55
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
56
--- a/target/arm/cpu.c
14
--- a/target/arm/cpu.c
57
+++ b/target/arm/cpu.c
15
+++ b/target/arm/cpu.c
58
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
16
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
59
if (!cpu->has_pmu) {
17
* * tininess-before-rounding
60
unset_feature(env, ARM_FEATURE_PMU);
18
* * 2-input NaN propagation prefers SNaN over QNaN, and then
61
cpu->id_aa64dfr0 &= ~0xf00;
19
* operand A over operand B (see FPProcessNaNs() pseudocode)
62
+ } else if (!kvm_enabled()) {
20
+ * * 3-input NaN propagation prefers SNaN over QNaN, and then
63
+ arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0);
21
+ * operand C over A over B (see FPProcessNaNs3() pseudocode,
64
+ arm_register_el_change_hook(cpu, &pmu_post_el_change, 0);
22
+ * but note that for QEMU muladd is a * b + c, whereas for
23
+ * the pseudocode function the arguments are in the order c, a, b.
24
* * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
25
* and the input NaN if it is signalling
26
*/
27
@@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s)
28
{
29
set_float_detect_tininess(float_tininess_before_rounding, s);
30
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
31
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, s);
32
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
33
}
34
35
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
36
index XXXXXXX..XXXXXXX 100644
37
--- a/fpu/softfloat-specialize.c.inc
38
+++ b/fpu/softfloat-specialize.c.inc
39
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
65
}
40
}
66
41
67
if (!arm_feature(env, ARM_FEATURE_EL2)) {
42
if (rule == float_3nan_prop_none) {
68
diff --git a/target/arm/helper.c b/target/arm/helper.c
43
-#if defined(TARGET_ARM)
69
index XXXXXXX..XXXXXXX 100644
44
- /*
70
--- a/target/arm/helper.c
45
- * This looks different from the ARM ARM pseudocode, because the ARM ARM
71
+++ b/target/arm/helper.c
46
- * puts the operands to a fused mac operation (a*b)+c in the order c,a,b
72
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
47
- */
73
/* Definitions for the PMU registers */
48
- rule = float_3nan_prop_s_cab;
74
#define PMCRN_MASK 0xf800
49
-#elif defined(TARGET_MIPS)
75
#define PMCRN_SHIFT 11
50
+#if defined(TARGET_MIPS)
76
+#define PMCRDP 0x10
51
if (snan_bit_is_one(status)) {
77
#define PMCRD 0x8
52
rule = float_3nan_prop_s_abc;
78
#define PMCRC 0x4
53
} else {
79
#define PMCRE 0x1
80
81
+#define PMXEVTYPER_P 0x80000000
82
+#define PMXEVTYPER_U 0x40000000
83
+#define PMXEVTYPER_NSK 0x20000000
84
+#define PMXEVTYPER_NSU 0x10000000
85
+#define PMXEVTYPER_NSH 0x08000000
86
+#define PMXEVTYPER_M 0x04000000
87
+#define PMXEVTYPER_MT 0x02000000
88
+#define PMXEVTYPER_EVTCOUNT 0x0000ffff
89
+#define PMXEVTYPER_MASK (PMXEVTYPER_P | PMXEVTYPER_U | PMXEVTYPER_NSK | \
90
+ PMXEVTYPER_NSU | PMXEVTYPER_NSH | \
91
+ PMXEVTYPER_M | PMXEVTYPER_MT | \
92
+ PMXEVTYPER_EVTCOUNT)
93
+
94
static inline uint32_t pmu_num_counters(CPUARMState *env)
95
{
96
return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT;
97
@@ -XXX,XX +XXX,XX @@ static CPAccessResult pmreg_access_ccntr(CPUARMState *env,
98
return pmreg_access(env, ri, isread);
99
}
100
101
-static inline bool arm_ccnt_enabled(CPUARMState *env)
102
+/* Returns true if the counter (pass 31 for PMCCNTR) should count events using
103
+ * the current EL, security state, and register configuration.
104
+ */
105
+static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
106
{
107
- /* This does not support checking PMCCFILTR_EL0 register */
108
+ uint64_t filter;
109
+ bool e, p, u, nsk, nsu, nsh, m;
110
+ bool enabled, prohibited, filtered;
111
+ bool secure = arm_is_secure(env);
112
+ int el = arm_current_el(env);
113
+ uint8_t hpmn = env->cp15.mdcr_el2 & MDCR_HPMN;
114
115
- if (!(env->cp15.c9_pmcr & PMCRE) || !(env->cp15.c9_pmcnten & (1 << 31))) {
116
- return false;
117
+ if (!arm_feature(env, ARM_FEATURE_EL2) ||
118
+ (counter < hpmn || counter == 31)) {
119
+ e = env->cp15.c9_pmcr & PMCRE;
120
+ } else {
121
+ e = env->cp15.mdcr_el2 & MDCR_HPME;
122
+ }
123
+ enabled = e && (env->cp15.c9_pmcnten & (1 << counter));
124
+
125
+ if (!secure) {
126
+ if (el == 2 && (counter < hpmn || counter == 31)) {
127
+ prohibited = env->cp15.mdcr_el2 & MDCR_HPMD;
128
+ } else {
129
+ prohibited = false;
130
+ }
131
+ } else {
132
+ prohibited = arm_feature(env, ARM_FEATURE_EL3) &&
133
+ (env->cp15.mdcr_el3 & MDCR_SPME);
134
}
135
136
- return true;
137
+ if (prohibited && counter == 31) {
138
+ prohibited = env->cp15.c9_pmcr & PMCRDP;
139
+ }
140
+
141
+ /* TODO Remove assert, set filter to correct PMEVTYPER */
142
+ assert(counter == 31);
143
+ filter = env->cp15.pmccfiltr_el0;
144
+
145
+ p = filter & PMXEVTYPER_P;
146
+ u = filter & PMXEVTYPER_U;
147
+ nsk = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSK);
148
+ nsu = arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_NSU);
149
+ nsh = arm_feature(env, ARM_FEATURE_EL2) && (filter & PMXEVTYPER_NSH);
150
+ m = arm_el_is_aa64(env, 1) &&
151
+ arm_feature(env, ARM_FEATURE_EL3) && (filter & PMXEVTYPER_M);
152
+
153
+ if (el == 0) {
154
+ filtered = secure ? u : u != nsu;
155
+ } else if (el == 1) {
156
+ filtered = secure ? p : p != nsk;
157
+ } else if (el == 2) {
158
+ filtered = !nsh;
159
+ } else { /* EL3 */
160
+ filtered = m != p;
161
+ }
162
+
163
+ return enabled && !prohibited && !filtered;
164
}
165
+
166
/*
167
* Ensure c15_ccnt is the guest-visible count so that operations such as
168
* enabling/disabling the counter or filtering, modifying the count itself,
169
@@ -XXX,XX +XXX,XX @@ void pmccntr_op_start(CPUARMState *env)
170
cycles = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
171
ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
172
173
- if (arm_ccnt_enabled(env)) {
174
+ if (pmu_counter_enabled(env, 31)) {
175
uint64_t eff_cycles = cycles;
176
if (env->cp15.c9_pmcr & PMCRD) {
177
/* Increment once every 64 processor clock cycles */
178
@@ -XXX,XX +XXX,XX @@ void pmccntr_op_start(CPUARMState *env)
179
*/
180
void pmccntr_op_finish(CPUARMState *env)
181
{
182
- if (arm_ccnt_enabled(env)) {
183
+ if (pmu_counter_enabled(env, 31)) {
184
uint64_t prev_cycles = env->cp15.c15_ccnt_delta;
185
186
if (env->cp15.c9_pmcr & PMCRD) {
187
@@ -XXX,XX +XXX,XX @@ void pmu_op_finish(CPUARMState *env)
188
pmccntr_op_finish(env);
189
}
190
191
+void pmu_pre_el_change(ARMCPU *cpu, void *ignored)
192
+{
193
+ pmu_op_start(&cpu->env);
194
+}
195
+
196
+void pmu_post_el_change(ARMCPU *cpu, void *ignored)
197
+{
198
+ pmu_op_finish(&cpu->env);
199
+}
200
+
201
static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
202
uint64_t value)
203
{
204
@@ -XXX,XX +XXX,XX @@ void pmu_op_finish(CPUARMState *env)
205
{
206
}
207
208
+void pmu_pre_el_change(ARMCPU *cpu, void *ignored)
209
+{
210
+}
211
+
212
+void pmu_post_el_change(ARMCPU *cpu, void *ignored)
213
+{
214
+}
215
+
216
#endif
217
218
static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
219
--
54
--
220
2.20.1
55
2.34.1
221
222
diff view generated by jsdifflib
[Qemu-devel] [PULL 41/49] target/arm: Implement PMOVSSET
[PULL 23/72] target/loongarch: Set Float3NaNPropRule explicitly
1
From: Aaron Lindsay <aaron@os.amperecomputing.com>
1
Set the Float3NaNPropRule explicitly for loongarch, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
Add an array for PMOVSSET so we only define it for v7ve+ platforms
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-19-peter.maydell@linaro.org
7
---
8
target/loongarch/tcg/fpu_helper.c | 1 +
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 1 insertion(+), 2 deletions(-)
4
11
5
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
12
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20181211151945.29137-7-aaron@os.amperecomputing.com
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/helper.c | 28 ++++++++++++++++++++++++++++
11
1 file changed, 28 insertions(+)
12
13
diff --git a/target/arm/helper.c b/target/arm/helper.c
14
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper.c
14
--- a/target/loongarch/tcg/fpu_helper.c
16
+++ b/target/arm/helper.c
15
+++ b/target/loongarch/tcg/fpu_helper.c
17
@@ -XXX,XX +XXX,XX @@ static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
16
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
18
env->cp15.c9_pmovsr &= ~value;
17
* case sets InvalidOp and returns the input value 'c'
18
*/
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status);
19
}
21
}
20
22
21
+static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri,
23
int ieee_ex_to_loongarch(int xcpt)
22
+ uint64_t value)
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
23
+{
25
index XXXXXXX..XXXXXXX 100644
24
+ value &= pmu_counter_mask(env);
26
--- a/fpu/softfloat-specialize.c.inc
25
+ env->cp15.c9_pmovsr |= value;
27
+++ b/fpu/softfloat-specialize.c.inc
26
+}
28
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
27
+
29
} else {
28
static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
30
rule = float_3nan_prop_s_cab;
29
uint64_t value)
31
}
30
{
32
-#elif defined(TARGET_LOONGARCH64)
31
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7mp_cp_reginfo[] = {
33
- rule = float_3nan_prop_s_cab;
32
REGINFO_SENTINEL
34
#elif defined(TARGET_PPC)
33
};
35
/*
34
36
* If fRA is a NaN return it; otherwise if fRB is a NaN return it;
35
+static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
36
+ /* PMOVSSET is not implemented in v7 before v7ve */
37
+ { .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3,
38
+ .access = PL0_RW, .accessfn = pmreg_access,
39
+ .type = ARM_CP_ALIAS,
40
+ .fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
41
+ .writefn = pmovsset_write,
42
+ .raw_writefn = raw_write },
43
+ { .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64,
44
+ .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3,
45
+ .access = PL0_RW, .accessfn = pmreg_access,
46
+ .type = ARM_CP_ALIAS,
47
+ .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
48
+ .writefn = pmovsset_write,
49
+ .raw_writefn = raw_write },
50
+ REGINFO_SENTINEL
51
+};
52
+
53
static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
54
uint64_t value)
55
{
56
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
57
!arm_feature(env, ARM_FEATURE_PMSA)) {
58
define_arm_cp_regs(cpu, v7mp_cp_reginfo);
59
}
60
+ if (arm_feature(env, ARM_FEATURE_V7VE)) {
61
+ define_arm_cp_regs(cpu, pmovsset_cp_reginfo);
62
+ }
63
if (arm_feature(env, ARM_FEATURE_V7)) {
64
/* v7 performance monitor control register: same implementor
65
* field as main ID register, and we implement only the cycle
66
--
37
--
67
2.20.1
38
2.34.1
68
69
diff view generated by jsdifflib
New patch
[PULL 24/72] target/ppc: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for PPC, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-20-peter.maydell@linaro.org
7
---
8
target/ppc/cpu_init.c | 8 ++++++++
9
fpu/softfloat-specialize.c.inc | 6 ------
10
2 files changed, 8 insertions(+), 6 deletions(-)
11
12
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/ppc/cpu_init.c
15
+++ b/target/ppc/cpu_init.c
16
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->vec_status);
20
+ /*
21
+ * NaN propagation for fused multiply-add:
22
+ * if fRA is a NaN return it; otherwise if fRB is a NaN return it;
23
+ * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
24
+ * whereas QEMU labels the operands as (a * b) + c.
25
+ */
26
+ set_float_3nan_prop_rule(float_3nan_prop_acb, &env->fp_status);
27
+ set_float_3nan_prop_rule(float_3nan_prop_acb, &env->vec_status);
28
/*
29
* For PPC, the (inf,zero,qnan) case sets InvalidOp, but we prefer
30
* to return an input NaN if we have one (ie c) rather than generating
31
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
32
index XXXXXXX..XXXXXXX 100644
33
--- a/fpu/softfloat-specialize.c.inc
34
+++ b/fpu/softfloat-specialize.c.inc
35
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
36
} else {
37
rule = float_3nan_prop_s_cab;
38
}
39
-#elif defined(TARGET_PPC)
40
- /*
41
- * If fRA is a NaN return it; otherwise if fRB is a NaN return it;
42
- * otherwise return fRC. Note that muladd on PPC is (fRA * fRC) + frB
43
- */
44
- rule = float_3nan_prop_acb;
45
#elif defined(TARGET_S390X)
46
rule = float_3nan_prop_s_abc;
47
#elif defined(TARGET_SPARC)
48
--
49
2.34.1
diff view generated by jsdifflib
New patch
[PULL 25/72] target/s390x: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for s390x, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-21-peter.maydell@linaro.org
7
---
8
target/s390x/cpu.c | 1 +
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 1 insertion(+), 2 deletions(-)
11
12
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/s390x/cpu.c
15
+++ b/target/s390x/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
17
set_float_detect_tininess(float_tininess_before_rounding,
18
&env->fpu_status);
19
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fpu_status);
20
+ set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status);
21
set_float_infzeronan_rule(float_infzeronan_dnan_always,
22
&env->fpu_status);
23
/* fall through */
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
29
} else {
30
rule = float_3nan_prop_s_cab;
31
}
32
-#elif defined(TARGET_S390X)
33
- rule = float_3nan_prop_s_abc;
34
#elif defined(TARGET_SPARC)
35
rule = float_3nan_prop_s_cba;
36
#elif defined(TARGET_XTENSA)
37
--
38
2.34.1
diff view generated by jsdifflib
New patch
[PULL 26/72] target/sparc: Set Float3NaNPropRule explicitly
1
Set the Float3NaNPropRule explicitly for SPARC, and remove the
2
ifdef from pickNaNMulAdd().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-22-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 2 --
10
2 files changed, 2 insertions(+), 2 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
* the CPU state struct so it won't get zeroed on reset.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &env->fp_status);
20
+ /* For fused-multiply add, prefer SNaN over QNaN, then C->B->A */
21
+ set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status);
22
/* For inf * 0 + NaN, return the input NaN */
23
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
24
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
} else {
31
rule = float_3nan_prop_s_cab;
32
}
33
-#elif defined(TARGET_SPARC)
34
- rule = float_3nan_prop_s_cba;
35
#elif defined(TARGET_XTENSA)
36
if (status->use_first_nan) {
37
rule = float_3nan_prop_abc;
38
--
39
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 40/49] target/arm: Allow AArch32 access for PMCCFILTR
[PULL 27/72] target/mips: Set Float3NaNPropRule explicitly
1
From: Aaron Lindsay <aaron@os.amperecomputing.com>
1
Set the Float3NaNPropRule explicitly for Arm, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20181211151945.29137-6-aaron@os.amperecomputing.com
6
Message-id: 20241202131347.498124-23-peter.maydell@linaro.org
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
---
7
---
9
target/arm/helper.c | 27 ++++++++++++++++++++++++++-
8
target/mips/fpu_helper.h | 4 ++++
10
1 file changed, 26 insertions(+), 1 deletion(-)
9
target/mips/msa.c | 3 +++
10
fpu/softfloat-specialize.c.inc | 8 +-------
11
3 files changed, 8 insertions(+), 7 deletions(-)
11
12
12
diff --git a/target/arm/helper.c b/target/arm/helper.c
13
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
13
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/helper.c
15
--- a/target/mips/fpu_helper.h
15
+++ b/target/arm/helper.c
16
+++ b/target/mips/fpu_helper.h
16
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
17
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
17
PMXEVTYPER_M | PMXEVTYPER_MT | \
18
{
18
PMXEVTYPER_EVTCOUNT)
19
bool nan2008 = env->active_fpu.fcr31 & (1 << FCR31_NAN2008);
19
20
FloatInfZeroNaNRule izn_rule;
20
+#define PMCCFILTR 0xf8000000
21
+ Float3NaNPropRule nan3_rule;
21
+#define PMCCFILTR_M PMXEVTYPER_M
22
22
+#define PMCCFILTR_EL0 (PMCCFILTR | PMCCFILTR_M)
23
/*
24
* With nan2008, SNaNs are silenced in the usual way.
25
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
26
*/
27
izn_rule = nan2008 ? float_infzeronan_dnan_never : float_infzeronan_dnan_always;
28
set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
29
+ nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc;
30
+ set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status);
23
+
31
+
24
static inline uint32_t pmu_num_counters(CPUARMState *env)
25
{
26
return (env->cp15.c9_pmcr & PMCRN_MASK) >> PMCRN_SHIFT;
27
@@ -XXX,XX +XXX,XX @@ static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
28
uint64_t value)
29
{
30
pmccntr_op_start(env);
31
- env->cp15.pmccfiltr_el0 = value & 0xfc000000;
32
+ env->cp15.pmccfiltr_el0 = value & PMCCFILTR_EL0;
33
pmccntr_op_finish(env);
34
}
32
}
35
33
36
+static void pmccfiltr_write_a32(CPUARMState *env, const ARMCPRegInfo *ri,
34
static inline void restore_fp_status(CPUMIPSState *env)
37
+ uint64_t value)
35
diff --git a/target/mips/msa.c b/target/mips/msa.c
38
+{
36
index XXXXXXX..XXXXXXX 100644
39
+ pmccntr_op_start(env);
37
--- a/target/mips/msa.c
40
+ /* M is not accessible from AArch32 */
38
+++ b/target/mips/msa.c
41
+ env->cp15.pmccfiltr_el0 = (env->cp15.pmccfiltr_el0 & PMCCFILTR_M) |
39
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
42
+ (value & PMCCFILTR);
40
set_float_2nan_prop_rule(float_2nan_prop_s_ab,
43
+ pmccntr_op_finish(env);
41
&env->active_tc.msa_fp_status);
44
+}
42
43
+ set_float_3nan_prop_rule(float_3nan_prop_s_cab,
44
+ &env->active_tc.msa_fp_status);
45
+
45
+
46
+static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *ri)
46
/* clear float_status exception flags */
47
+{
47
set_float_exception_flags(0, &env->active_tc.msa_fp_status);
48
+ /* M is not visible in AArch32 */
48
49
+ return env->cp15.pmccfiltr_el0 & PMCCFILTR;
49
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
50
+}
50
index XXXXXXX..XXXXXXX 100644
51
+
51
--- a/fpu/softfloat-specialize.c.inc
52
static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
52
+++ b/fpu/softfloat-specialize.c.inc
53
uint64_t value)
53
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
54
{
54
}
55
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
55
56
.readfn = pmccntr_read, .writefn = pmccntr_write,
56
if (rule == float_3nan_prop_none) {
57
.raw_readfn = raw_read, .raw_writefn = raw_write, },
57
-#if defined(TARGET_MIPS)
58
#endif
58
- if (snan_bit_is_one(status)) {
59
+ { .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7,
59
- rule = float_3nan_prop_s_abc;
60
+ .writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32,
60
- } else {
61
+ .access = PL0_RW, .accessfn = pmreg_access,
61
- rule = float_3nan_prop_s_cab;
62
+ .type = ARM_CP_ALIAS | ARM_CP_IO,
62
- }
63
+ .resetvalue = 0, },
63
-#elif defined(TARGET_XTENSA)
64
{ .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
64
+#if defined(TARGET_XTENSA)
65
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
65
if (status->use_first_nan) {
66
.writefn = pmccfiltr_write, .raw_writefn = raw_write,
66
rule = float_3nan_prop_abc;
67
} else {
67
--
68
--
68
2.20.1
69
2.34.1
69
70
diff view generated by jsdifflib
[Qemu-devel] [PULL 31/49] target/arm: Implement pauth_computepac
[PULL 28/72] target/xtensa: Set Float3NaNPropRule explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the Float3NaNPropRule explicitly for xtensa, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
This is the main crypto routine, an implementation of QARMA.
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
This matches, as much as possible, ARM pseudocode.
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-24-peter.maydell@linaro.org
7
---
8
target/xtensa/fpu_helper.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 8 --------
10
2 files changed, 2 insertions(+), 8 deletions(-)
5
11
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20190108223129.5570-28-richard.henderson@linaro.org
9
[PMM: fixed minor checkpatch nits]
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/pauth_helper.c | 242 +++++++++++++++++++++++++++++++++++++-
13
1 file changed, 241 insertions(+), 1 deletion(-)
14
15
diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c
16
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/pauth_helper.c
14
--- a/target/xtensa/fpu_helper.c
18
+++ b/target/arm/pauth_helper.c
15
+++ b/target/xtensa/fpu_helper.c
19
@@ -XXX,XX +XXX,XX @@
16
@@ -XXX,XX +XXX,XX @@ void xtensa_use_first_nan(CPUXtensaState *env, bool use_first)
20
#include "tcg/tcg-gvec-desc.h"
17
set_use_first_nan(use_first, &env->fp_status);
21
18
set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba,
22
19
&env->fp_status);
23
+static uint64_t pac_cell_shuffle(uint64_t i)
20
+ set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba,
24
+{
21
+ &env->fp_status);
25
+ uint64_t o = 0;
26
+
27
+ o |= extract64(i, 52, 4);
28
+ o |= extract64(i, 24, 4) << 4;
29
+ o |= extract64(i, 44, 4) << 8;
30
+ o |= extract64(i, 0, 4) << 12;
31
+
32
+ o |= extract64(i, 28, 4) << 16;
33
+ o |= extract64(i, 48, 4) << 20;
34
+ o |= extract64(i, 4, 4) << 24;
35
+ o |= extract64(i, 40, 4) << 28;
36
+
37
+ o |= extract64(i, 32, 4) << 32;
38
+ o |= extract64(i, 12, 4) << 36;
39
+ o |= extract64(i, 56, 4) << 40;
40
+ o |= extract64(i, 20, 4) << 44;
41
+
42
+ o |= extract64(i, 8, 4) << 48;
43
+ o |= extract64(i, 36, 4) << 52;
44
+ o |= extract64(i, 16, 4) << 56;
45
+ o |= extract64(i, 60, 4) << 60;
46
+
47
+ return o;
48
+}
49
+
50
+static uint64_t pac_cell_inv_shuffle(uint64_t i)
51
+{
52
+ uint64_t o = 0;
53
+
54
+ o |= extract64(i, 12, 4);
55
+ o |= extract64(i, 24, 4) << 4;
56
+ o |= extract64(i, 48, 4) << 8;
57
+ o |= extract64(i, 36, 4) << 12;
58
+
59
+ o |= extract64(i, 56, 4) << 16;
60
+ o |= extract64(i, 44, 4) << 20;
61
+ o |= extract64(i, 4, 4) << 24;
62
+ o |= extract64(i, 16, 4) << 28;
63
+
64
+ o |= i & MAKE_64BIT_MASK(32, 4);
65
+ o |= extract64(i, 52, 4) << 36;
66
+ o |= extract64(i, 28, 4) << 40;
67
+ o |= extract64(i, 8, 4) << 44;
68
+
69
+ o |= extract64(i, 20, 4) << 48;
70
+ o |= extract64(i, 0, 4) << 52;
71
+ o |= extract64(i, 40, 4) << 56;
72
+ o |= i & MAKE_64BIT_MASK(60, 4);
73
+
74
+ return o;
75
+}
76
+
77
+static uint64_t pac_sub(uint64_t i)
78
+{
79
+ static const uint8_t sub[16] = {
80
+ 0xb, 0x6, 0x8, 0xf, 0xc, 0x0, 0x9, 0xe,
81
+ 0x3, 0x7, 0x4, 0x5, 0xd, 0x2, 0x1, 0xa,
82
+ };
83
+ uint64_t o = 0;
84
+ int b;
85
+
86
+ for (b = 0; b < 64; b += 16) {
87
+ o |= (uint64_t)sub[(i >> b) & 0xf] << b;
88
+ }
89
+ return o;
90
+}
91
+
92
+static uint64_t pac_inv_sub(uint64_t i)
93
+{
94
+ static const uint8_t inv_sub[16] = {
95
+ 0x5, 0xe, 0xd, 0x8, 0xa, 0xb, 0x1, 0x9,
96
+ 0x2, 0x6, 0xf, 0x0, 0x4, 0xc, 0x7, 0x3,
97
+ };
98
+ uint64_t o = 0;
99
+ int b;
100
+
101
+ for (b = 0; b < 64; b += 16) {
102
+ o |= (uint64_t)inv_sub[(i >> b) & 0xf] << b;
103
+ }
104
+ return o;
105
+}
106
+
107
+static int rot_cell(int cell, int n)
108
+{
109
+ /* 4-bit rotate left by n. */
110
+ cell |= cell << 4;
111
+ return extract32(cell, 4 - n, 4);
112
+}
113
+
114
+static uint64_t pac_mult(uint64_t i)
115
+{
116
+ uint64_t o = 0;
117
+ int b;
118
+
119
+ for (b = 0; b < 4 * 4; b += 4) {
120
+ int i0, i4, i8, ic, t0, t1, t2, t3;
121
+
122
+ i0 = extract64(i, b, 4);
123
+ i4 = extract64(i, b + 4 * 4, 4);
124
+ i8 = extract64(i, b + 8 * 4, 4);
125
+ ic = extract64(i, b + 12 * 4, 4);
126
+
127
+ t0 = rot_cell(i8, 1) ^ rot_cell(i4, 2) ^ rot_cell(i0, 1);
128
+ t1 = rot_cell(ic, 1) ^ rot_cell(i4, 1) ^ rot_cell(i0, 2);
129
+ t2 = rot_cell(ic, 2) ^ rot_cell(i8, 1) ^ rot_cell(i0, 1);
130
+ t3 = rot_cell(ic, 1) ^ rot_cell(i8, 2) ^ rot_cell(i4, 1);
131
+
132
+ o |= (uint64_t)t3 << b;
133
+ o |= (uint64_t)t2 << (b + 4 * 4);
134
+ o |= (uint64_t)t1 << (b + 8 * 4);
135
+ o |= (uint64_t)t0 << (b + 12 * 4);
136
+ }
137
+ return o;
138
+}
139
+
140
+static uint64_t tweak_cell_rot(uint64_t cell)
141
+{
142
+ return (cell >> 1) | (((cell ^ (cell >> 1)) & 1) << 3);
143
+}
144
+
145
+static uint64_t tweak_shuffle(uint64_t i)
146
+{
147
+ uint64_t o = 0;
148
+
149
+ o |= extract64(i, 16, 4) << 0;
150
+ o |= extract64(i, 20, 4) << 4;
151
+ o |= tweak_cell_rot(extract64(i, 24, 4)) << 8;
152
+ o |= extract64(i, 28, 4) << 12;
153
+
154
+ o |= tweak_cell_rot(extract64(i, 44, 4)) << 16;
155
+ o |= extract64(i, 8, 4) << 20;
156
+ o |= extract64(i, 12, 4) << 24;
157
+ o |= tweak_cell_rot(extract64(i, 32, 4)) << 28;
158
+
159
+ o |= extract64(i, 48, 4) << 32;
160
+ o |= extract64(i, 52, 4) << 36;
161
+ o |= extract64(i, 56, 4) << 40;
162
+ o |= tweak_cell_rot(extract64(i, 60, 4)) << 44;
163
+
164
+ o |= tweak_cell_rot(extract64(i, 0, 4)) << 48;
165
+ o |= extract64(i, 4, 4) << 52;
166
+ o |= tweak_cell_rot(extract64(i, 40, 4)) << 56;
167
+ o |= tweak_cell_rot(extract64(i, 36, 4)) << 60;
168
+
169
+ return o;
170
+}
171
+
172
+static uint64_t tweak_cell_inv_rot(uint64_t cell)
173
+{
174
+ return ((cell << 1) & 0xf) | ((cell & 1) ^ (cell >> 3));
175
+}
176
+
177
+static uint64_t tweak_inv_shuffle(uint64_t i)
178
+{
179
+ uint64_t o = 0;
180
+
181
+ o |= tweak_cell_inv_rot(extract64(i, 48, 4));
182
+ o |= extract64(i, 52, 4) << 4;
183
+ o |= extract64(i, 20, 4) << 8;
184
+ o |= extract64(i, 24, 4) << 12;
185
+
186
+ o |= extract64(i, 0, 4) << 16;
187
+ o |= extract64(i, 4, 4) << 20;
188
+ o |= tweak_cell_inv_rot(extract64(i, 8, 4)) << 24;
189
+ o |= extract64(i, 12, 4) << 28;
190
+
191
+ o |= tweak_cell_inv_rot(extract64(i, 28, 4)) << 32;
192
+ o |= tweak_cell_inv_rot(extract64(i, 60, 4)) << 36;
193
+ o |= tweak_cell_inv_rot(extract64(i, 56, 4)) << 40;
194
+ o |= tweak_cell_inv_rot(extract64(i, 16, 4)) << 44;
195
+
196
+ o |= extract64(i, 32, 4) << 48;
197
+ o |= extract64(i, 36, 4) << 52;
198
+ o |= extract64(i, 40, 4) << 56;
199
+ o |= tweak_cell_inv_rot(extract64(i, 44, 4)) << 60;
200
+
201
+ return o;
202
+}
203
+
204
static uint64_t pauth_computepac(uint64_t data, uint64_t modifier,
205
ARMPACKey key)
206
{
207
- g_assert_not_reached(); /* FIXME */
208
+ static const uint64_t RC[5] = {
209
+ 0x0000000000000000ull,
210
+ 0x13198A2E03707344ull,
211
+ 0xA4093822299F31D0ull,
212
+ 0x082EFA98EC4E6C89ull,
213
+ 0x452821E638D01377ull,
214
+ };
215
+ const uint64_t alpha = 0xC0AC29B7C97C50DDull;
216
+ /*
217
+ * Note that in the ARM pseudocode, key0 contains bits <127:64>
218
+ * and key1 contains bits <63:0> of the 128-bit key.
219
+ */
220
+ uint64_t key0 = key.hi, key1 = key.lo;
221
+ uint64_t workingval, runningmod, roundkey, modk0;
222
+ int i;
223
+
224
+ modk0 = (key0 << 63) | ((key0 >> 1) ^ (key0 >> 63));
225
+ runningmod = modifier;
226
+ workingval = data ^ key0;
227
+
228
+ for (i = 0; i <= 4; ++i) {
229
+ roundkey = key1 ^ runningmod;
230
+ workingval ^= roundkey;
231
+ workingval ^= RC[i];
232
+ if (i > 0) {
233
+ workingval = pac_cell_shuffle(workingval);
234
+ workingval = pac_mult(workingval);
235
+ }
236
+ workingval = pac_sub(workingval);
237
+ runningmod = tweak_shuffle(runningmod);
238
+ }
239
+ roundkey = modk0 ^ runningmod;
240
+ workingval ^= roundkey;
241
+ workingval = pac_cell_shuffle(workingval);
242
+ workingval = pac_mult(workingval);
243
+ workingval = pac_sub(workingval);
244
+ workingval = pac_cell_shuffle(workingval);
245
+ workingval = pac_mult(workingval);
246
+ workingval ^= key1;
247
+ workingval = pac_cell_inv_shuffle(workingval);
248
+ workingval = pac_inv_sub(workingval);
249
+ workingval = pac_mult(workingval);
250
+ workingval = pac_cell_inv_shuffle(workingval);
251
+ workingval ^= key0;
252
+ workingval ^= runningmod;
253
+ for (i = 0; i <= 4; ++i) {
254
+ workingval = pac_inv_sub(workingval);
255
+ if (i < 4) {
256
+ workingval = pac_mult(workingval);
257
+ workingval = pac_cell_inv_shuffle(workingval);
258
+ }
259
+ runningmod = tweak_inv_shuffle(runningmod);
260
+ roundkey = key1 ^ runningmod;
261
+ workingval ^= RC[4 - i];
262
+ workingval ^= roundkey;
263
+ workingval ^= alpha;
264
+ }
265
+ workingval ^= modk0;
266
+
267
+ return workingval;
268
}
22
}
269
23
270
static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier,
24
void HELPER(wur_fpu2k_fcr)(CPUXtensaState *env, uint32_t v)
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
30
}
31
32
if (rule == float_3nan_prop_none) {
33
-#if defined(TARGET_XTENSA)
34
- if (status->use_first_nan) {
35
- rule = float_3nan_prop_abc;
36
- } else {
37
- rule = float_3nan_prop_cba;
38
- }
39
-#else
40
rule = float_3nan_prop_abc;
41
-#endif
42
}
43
44
assert(rule != float_3nan_prop_none);
271
--
45
--
272
2.20.1
46
2.34.1
273
274
diff view generated by jsdifflib
[Qemu-devel] [PULL 49/49] tests/libqtest: Introduce qtest_init_with_serial()
[PULL 29/72] target/i386: Set Float3NaNPropRule explicitly
1
From: Julia Suvorova <jusual@mail.ru>
1
Set the Float3NaNPropRule explicitly for i386. We had no
2
i386-specific behaviour in the old ifdef ladder, so we were using the
3
default "prefer a then b then c" fallback; this is actually the
4
correct per-the-spec handling for i386.
2
5
3
Run qtest with a socket that connects QEMU chardev and test code.
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-25-peter.maydell@linaro.org
9
---
10
target/i386/tcg/fpu_helper.c | 1 +
11
1 file changed, 1 insertion(+)
4
12
5
Signed-off-by: Julia Suvorova <jusual@mail.ru>
13
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
6
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
7
Message-id: 20190117161640.5496-2-jusual@mail.ru
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
tests/libqtest.h | 11 +++++++++++
11
tests/libqtest.c | 26 ++++++++++++++++++++++++++
12
2 files changed, 37 insertions(+)
13
14
diff --git a/tests/libqtest.h b/tests/libqtest.h
15
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
16
--- a/tests/libqtest.h
15
--- a/target/i386/tcg/fpu_helper.c
17
+++ b/tests/libqtest.h
16
+++ b/target/i386/tcg/fpu_helper.c
18
@@ -XXX,XX +XXX,XX @@ QTestState *qtest_init(const char *extra_args);
17
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
19
*/
18
* there are multiple input NaNs they are selected in the order a, b, c.
20
QTestState *qtest_init_without_qmp_handshake(const char *extra_args);
19
*/
21
20
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
22
+/**
21
+ set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status);
23
+ * qtest_init_with_serial:
24
+ * @extra_args: other arguments to pass to QEMU. CAUTION: these
25
+ * arguments are subject to word splitting and shell evaluation.
26
+ * @sock_fd: pointer to store the socket file descriptor for
27
+ * connection with serial.
28
+ *
29
+ * Returns: #QTestState instance.
30
+ */
31
+QTestState *qtest_init_with_serial(const char *extra_args, int *sock_fd);
32
+
33
/**
34
* qtest_quit:
35
* @s: #QTestState instance to operate on.
36
diff --git a/tests/libqtest.c b/tests/libqtest.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/tests/libqtest.c
39
+++ b/tests/libqtest.c
40
@@ -XXX,XX +XXX,XX @@ QTestState *qtest_initf(const char *fmt, ...)
41
return s;
42
}
22
}
43
23
44
+QTestState *qtest_init_with_serial(const char *extra_args, int *sock_fd)
24
static inline uint8_t save_exception_flags(CPUX86State *env)
45
+{
46
+ int sock_fd_init;
47
+ char *sock_path, sock_dir[] = "/tmp/qtest-serial-XXXXXX";
48
+ QTestState *qts;
49
+
50
+ g_assert(mkdtemp(sock_dir));
51
+ sock_path = g_strdup_printf("%s/sock", sock_dir);
52
+
53
+ sock_fd_init = init_socket(sock_path);
54
+
55
+ qts = qtest_initf("-chardev socket,id=s0,path=%s,nowait "
56
+ "-serial chardev:s0 %s",
57
+ sock_path, extra_args);
58
+
59
+ *sock_fd = socket_accept(sock_fd_init);
60
+
61
+ unlink(sock_path);
62
+ g_free(sock_path);
63
+ rmdir(sock_dir);
64
+
65
+ g_assert(*sock_fd >= 0);
66
+
67
+ return qts;
68
+}
69
+
70
void qtest_quit(QTestState *s)
71
{
72
g_hook_destroy_link(&abrt_hooks, g_hook_find_data(&abrt_hooks, TRUE, s));
73
--
25
--
74
2.20.1
26
2.34.1
75
76
diff view generated by jsdifflib
[Qemu-devel] [PULL 36/49] migration: Add post_save function to VMStateDescription
[PULL 30/72] target/hppa: Set Float3NaNPropRule explicitly
1
From: Aaron Lindsay <aaron@os.amperecomputing.com>
1
Set the Float3NaNPropRule explicitly for HPPA, and remove the
2
ifdef from pickNaNMulAdd().
2
3
3
In some cases it may be helpful to modify state before saving it for
4
HPPA is the only target that was using the default branch of the
4
migration, and then modify the state back after it has been saved. The
5
ifdef ladder (other targets either do not use muladd or set
5
existing pre_save function provides half of this functionality. This
6
default_nan_mode), so we can remove the ifdef fallback entirely now
6
patch adds a post_save function to provide the second half.
7
(allowing the "rule not set" case to fall into the default of the
8
switch statement and assert).
7
9
8
Signed-off-by: Aaron Lindsay <aclindsa@gmail.com>
10
We add a TODO note that the HPPA rule is probably wrong; this is
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
not a behavioural change for this refactoring.
10
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
12
11
Message-id: 20181211151945.29137-2-aaron@os.amperecomputing.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
15
Message-id: 20241202131347.498124-26-peter.maydell@linaro.org
13
---
16
---
14
include/migration/vmstate.h | 1 +
17
target/hppa/fpu_helper.c | 8 ++++++++
15
migration/vmstate.c | 13 ++++++++++++-
18
fpu/softfloat-specialize.c.inc | 4 ----
16
docs/devel/migration.rst | 9 +++++++--
19
2 files changed, 8 insertions(+), 4 deletions(-)
17
3 files changed, 20 insertions(+), 3 deletions(-)
18
20
19
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
21
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
20
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
21
--- a/include/migration/vmstate.h
23
--- a/target/hppa/fpu_helper.c
22
+++ b/include/migration/vmstate.h
24
+++ b/target/hppa/fpu_helper.c
23
@@ -XXX,XX +XXX,XX @@ struct VMStateDescription {
25
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
24
int (*pre_load)(void *opaque);
26
* HPPA does note implement a CPU reset method at all...
25
int (*post_load)(void *opaque, int version_id);
27
*/
26
int (*pre_save)(void *opaque);
28
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &env->fp_status);
27
+ int (*post_save)(void *opaque);
29
+ /*
28
bool (*needed)(void *opaque);
30
+ * TODO: The HPPA architecture reference only documents its NaN
29
const VMStateField *fields;
31
+ * propagation rule for 2-operand operations. Testing on real hardware
30
const VMStateDescription **subsections;
32
+ * might be necessary to confirm whether this order for muladd is correct.
31
diff --git a/migration/vmstate.c b/migration/vmstate.c
33
+ * Not preferring the SNaN is almost certainly incorrect as it diverges
34
+ * from the documented rules for 2-operand operations.
35
+ */
36
+ set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status);
37
/* For inf * 0 + NaN, return the input NaN */
38
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
39
}
40
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
32
index XXXXXXX..XXXXXXX 100644
41
index XXXXXXX..XXXXXXX 100644
33
--- a/migration/vmstate.c
42
--- a/fpu/softfloat-specialize.c.inc
34
+++ b/migration/vmstate.c
43
+++ b/fpu/softfloat-specialize.c.inc
35
@@ -XXX,XX +XXX,XX @@ int vmstate_save_state_v(QEMUFile *f, const VMStateDescription *vmsd,
44
@@ -XXX,XX +XXX,XX @@ static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
36
if (ret) {
45
}
37
error_report("Save of field %s/%s failed",
38
vmsd->name, field->name);
39
+ if (vmsd->post_save) {
40
+ vmsd->post_save(opaque);
41
+ }
42
return ret;
43
}
44
45
@@ -XXX,XX +XXX,XX @@ int vmstate_save_state_v(QEMUFile *f, const VMStateDescription *vmsd,
46
json_end_array(vmdesc);
47
}
46
}
48
47
49
- return vmstate_subsection_save(f, vmsd, opaque, vmdesc);
48
- if (rule == float_3nan_prop_none) {
50
+ ret = vmstate_subsection_save(f, vmsd, opaque, vmdesc);
49
- rule = float_3nan_prop_abc;
51
+
50
- }
52
+ if (vmsd->post_save) {
51
-
53
+ int ps_ret = vmsd->post_save(opaque);
52
assert(rule != float_3nan_prop_none);
54
+ if (!ret) {
53
if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
55
+ ret = ps_ret;
54
/* We have at least one SNaN input and should prefer it */
56
+ }
57
+ }
58
+ return ret;
59
}
60
61
static const VMStateDescription *
62
diff --git a/docs/devel/migration.rst b/docs/devel/migration.rst
63
index XXXXXXX..XXXXXXX 100644
64
--- a/docs/devel/migration.rst
65
+++ b/docs/devel/migration.rst
66
@@ -XXX,XX +XXX,XX @@ The functions to do that are inside a vmstate definition, and are called:
67
68
This function is called before we save the state of one device.
69
70
-Example: You can look at hpet.c, that uses the three function to
71
-massage the state that is transferred.
72
+- ``int (*post_save)(void *opaque);``
73
+
74
+ This function is called after we save the state of one device
75
+ (even upon failure, unless the call to pre_save returned an error).
76
+
77
+Example: You can look at hpet.c, that uses the first three functions
78
+to massage the state that is transferred.
79
80
The ``VMSTATE_WITH_TMP`` macro may be useful when the migration
81
data doesn't match the stored device data well; it allows an
82
--
55
--
83
2.20.1
56
2.34.1
84
85
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/49] target/arm: Add SCTLR bits through ARMv8.5
[PULL 31/72] fpu: Remove use_first_nan field from float_status
1
From: Richard Henderson <richard.henderson@linaro.org>
1
The use_first_nan field in float_status was an xtensa-specific way to
2
select at runtime from two different NaN propagation rules. Now that
3
xtensa is using the target-agnostic NaN propagation rule selection
4
that we've just added, we can remove use_first_nan, because there is
5
no longer any code that reads it.
2
6
3
Post v8.4 bits taken from SysReg_v85_xml-00bet8.
7
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20241202131347.498124-27-peter.maydell@linaro.org
10
---
11
include/fpu/softfloat-helpers.h | 5 -----
12
include/fpu/softfloat-types.h | 1 -
13
target/xtensa/fpu_helper.c | 1 -
14
3 files changed, 7 deletions(-)
4
15
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20190108223129.5570-3-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/cpu.h | 45 +++++++++++++++++++++++++++++++++------------
11
1 file changed, 33 insertions(+), 12 deletions(-)
12
13
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/cpu.h
18
--- a/include/fpu/softfloat-helpers.h
16
+++ b/target/arm/cpu.h
19
+++ b/include/fpu/softfloat-helpers.h
17
@@ -XXX,XX +XXX,XX @@ void pmccntr_sync(CPUARMState *env);
20
@@ -XXX,XX +XXX,XX @@ static inline void set_snan_bit_is_one(bool val, float_status *status)
18
#define SCTLR_A (1U << 1)
21
status->snan_bit_is_one = val;
19
#define SCTLR_C (1U << 2)
22
}
20
#define SCTLR_W (1U << 3) /* up to v6; RAO in v7 */
23
21
-#define SCTLR_SA (1U << 3)
24
-static inline void set_use_first_nan(bool val, float_status *status)
22
+#define SCTLR_nTLSMD_32 (1U << 3) /* v8.2-LSMAOC, AArch32 only */
25
-{
23
+#define SCTLR_SA (1U << 3) /* AArch64 only */
26
- status->use_first_nan = val;
24
#define SCTLR_P (1U << 4) /* up to v5; RAO in v6 and v7 */
27
-}
25
+#define SCTLR_LSMAOE_32 (1U << 4) /* v8.2-LSMAOC, AArch32 only */
28
-
26
#define SCTLR_SA0 (1U << 4) /* v8 onward, AArch64 only */
29
static inline void set_no_signaling_nans(bool val, float_status *status)
27
#define SCTLR_D (1U << 5) /* up to v5; RAO in v6 */
30
{
28
#define SCTLR_CP15BEN (1U << 5) /* v7 onward */
31
status->no_signaling_nans = val;
29
#define SCTLR_L (1U << 6) /* up to v5; RAO in v6 and v7; RAZ in v8 */
32
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
30
+#define SCTLR_nAA (1U << 6) /* when v8.4-LSE is implemented */
33
index XXXXXXX..XXXXXXX 100644
31
#define SCTLR_B (1U << 7) /* up to v6; RAZ in v7 */
34
--- a/include/fpu/softfloat-types.h
32
#define SCTLR_ITD (1U << 7) /* v8 onward */
35
+++ b/include/fpu/softfloat-types.h
33
#define SCTLR_S (1U << 8) /* up to v6; RAZ in v7 */
36
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
34
@@ -XXX,XX +XXX,XX @@ void pmccntr_sync(CPUARMState *env);
37
* softfloat-specialize.inc.c)
35
#define SCTLR_R (1U << 9) /* up to v6; RAZ in v7 */
38
*/
36
#define SCTLR_UMA (1U << 9) /* v8 onward, AArch64 only */
39
bool snan_bit_is_one;
37
#define SCTLR_F (1U << 10) /* up to v6 */
40
- bool use_first_nan;
38
-#define SCTLR_SW (1U << 10) /* v7 onward */
41
bool no_signaling_nans;
39
-#define SCTLR_Z (1U << 11)
42
/* should overflowed results subtract re_bias to its exponent? */
40
+#define SCTLR_SW (1U << 10) /* v7, RES0 in v8 */
43
bool rebias_overflow;
41
+#define SCTLR_Z (1U << 11) /* in v7, RES1 in v8 */
44
diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c
42
+#define SCTLR_EOS (1U << 11) /* v8.5-ExS */
45
index XXXXXXX..XXXXXXX 100644
43
#define SCTLR_I (1U << 12)
46
--- a/target/xtensa/fpu_helper.c
44
-#define SCTLR_V (1U << 13)
47
+++ b/target/xtensa/fpu_helper.c
45
+#define SCTLR_V (1U << 13) /* AArch32 only */
48
@@ -XXX,XX +XXX,XX @@ static const struct {
46
+#define SCTLR_EnDB (1U << 13) /* v8.3, AArch64 only */
49
47
#define SCTLR_RR (1U << 14) /* up to v7 */
50
void xtensa_use_first_nan(CPUXtensaState *env, bool use_first)
48
#define SCTLR_DZE (1U << 14) /* v8 onward, AArch64 only */
51
{
49
#define SCTLR_L4 (1U << 15) /* up to v6; RAZ in v7 */
52
- set_use_first_nan(use_first, &env->fp_status);
50
#define SCTLR_UCT (1U << 15) /* v8 onward, AArch64 only */
53
set_float_2nan_prop_rule(use_first ? float_2nan_prop_ab : float_2nan_prop_ba,
51
#define SCTLR_DT (1U << 16) /* up to ??, RAO in v6 and v7 */
54
&env->fp_status);
52
#define SCTLR_nTWI (1U << 16) /* v8 onward */
55
set_float_3nan_prop_rule(use_first ? float_3nan_prop_abc : float_3nan_prop_cba,
53
-#define SCTLR_HA (1U << 17)
54
+#define SCTLR_HA (1U << 17) /* up to v7, RES0 in v8 */
55
#define SCTLR_BR (1U << 17) /* PMSA only */
56
#define SCTLR_IT (1U << 18) /* up to ??, RAO in v6 and v7 */
57
#define SCTLR_nTWE (1U << 18) /* v8 onward */
58
#define SCTLR_WXN (1U << 19)
59
#define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */
60
-#define SCTLR_UWXN (1U << 20) /* v7 onward */
61
-#define SCTLR_FI (1U << 21)
62
-#define SCTLR_U (1U << 22)
63
+#define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */
64
+#define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */
65
+#define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */
66
+#define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */
67
+#define SCTLR_EIS (1U << 22) /* v8.5-ExS */
68
#define SCTLR_XP (1U << 23) /* up to v6; v7 onward RAO */
69
+#define SCTLR_SPAN (1U << 23) /* v8.1-PAN */
70
#define SCTLR_VE (1U << 24) /* up to v7 */
71
#define SCTLR_E0E (1U << 24) /* v8 onward, AArch64 only */
72
#define SCTLR_EE (1U << 25)
73
#define SCTLR_L2 (1U << 26) /* up to v6, RAZ in v7 */
74
#define SCTLR_UCI (1U << 26) /* v8 onward, AArch64 only */
75
-#define SCTLR_NMFI (1U << 27)
76
-#define SCTLR_TRE (1U << 28)
77
-#define SCTLR_AFE (1U << 29)
78
-#define SCTLR_TE (1U << 30)
79
+#define SCTLR_NMFI (1U << 27) /* up to v7, RAZ in v7VE and v8 */
80
+#define SCTLR_EnDA (1U << 27) /* v8.3, AArch64 only */
81
+#define SCTLR_TRE (1U << 28) /* AArch32 only */
82
+#define SCTLR_nTLSMD_64 (1U << 28) /* v8.2-LSMAOC, AArch64 only */
83
+#define SCTLR_AFE (1U << 29) /* AArch32 only */
84
+#define SCTLR_LSMAOE_64 (1U << 29) /* v8.2-LSMAOC, AArch64 only */
85
+#define SCTLR_TE (1U << 30) /* AArch32 only */
86
+#define SCTLR_EnIB (1U << 30) /* v8.3, AArch64 only */
87
+#define SCTLR_EnIA (1U << 31) /* v8.3, AArch64 only */
88
+#define SCTLR_BT0 (1ULL << 35) /* v8.5-BTI */
89
+#define SCTLR_BT1 (1ULL << 36) /* v8.5-BTI */
90
+#define SCTLR_ITFSB (1ULL << 37) /* v8.5-MemTag */
91
+#define SCTLR_TCF0 (3ULL << 38) /* v8.5-MemTag */
92
+#define SCTLR_TCF (3ULL << 40) /* v8.5-MemTag */
93
+#define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */
94
+#define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */
95
+#define SCTLR_DSSBS (1ULL << 44) /* v8.5 */
96
97
#define CPTR_TCPAC (1U << 31)
98
#define CPTR_TTA (1U << 20)
99
--
56
--
100
2.20.1
57
2.34.1
101
102
diff view generated by jsdifflib
New patch
[PULL 32/72] target/m68k: Don't pass NULL float_status to floatx80_default_nan()
1
Currently m68k_cpu_reset_hold() calls floatx80_default_nan(NULL)
2
to get the NaN bit pattern to reset the FPU registers. This
3
works because it happens that our implementation of
4
floatx80_default_nan() doesn't actually look at the float_status
5
pointer except for TARGET_MIPS. However, this isn't guaranteed,
6
and to be able to remove the ifdef in floatx80_default_nan()
7
we're going to need a real float_status here.
1
8
9
Rearrange m68k_cpu_reset_hold() so that we initialize env->fp_status
10
earlier, and thus can pass it to floatx80_default_nan().
11
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20241202131347.498124-28-peter.maydell@linaro.org
15
---
16
target/m68k/cpu.c | 12 +++++++-----
17
1 file changed, 7 insertions(+), 5 deletions(-)
18
19
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/target/m68k/cpu.c
22
+++ b/target/m68k/cpu.c
23
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
24
CPUState *cs = CPU(obj);
25
M68kCPUClass *mcc = M68K_CPU_GET_CLASS(obj);
26
CPUM68KState *env = cpu_env(cs);
27
- floatx80 nan = floatx80_default_nan(NULL);
28
+ floatx80 nan;
29
int i;
30
31
if (mcc->parent_phases.hold) {
32
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
33
#else
34
cpu_m68k_set_sr(env, SR_S | SR_I);
35
#endif
36
- for (i = 0; i < 8; i++) {
37
- env->fregs[i].d = nan;
38
- }
39
- cpu_m68k_set_fpcr(env, 0);
40
/*
41
* M68000 FAMILY PROGRAMMER'S REFERENCE MANUAL
42
* 3.4 FLOATING-POINT INSTRUCTION DETAILS
43
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
44
* preceding paragraph for nonsignaling NaNs.
45
*/
46
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
47
+
48
+ nan = floatx80_default_nan(&env->fp_status);
49
+ for (i = 0; i < 8; i++) {
50
+ env->fregs[i].d = nan;
51
+ }
52
+ cpu_m68k_set_fpcr(env, 0);
53
env->fpsr = 0;
54
55
/* TODO: We should set PC from the interrupt vector. */
56
--
57
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 38/49] target/arm: Swap PMU values before/after migrations
[PULL 33/72] softfloat: Create floatx80 default NaN from parts64_default_nan
1
From: Aaron Lindsay <aaron@os.amperecomputing.com>
1
We create our 128-bit default NaN by calling parts64_default_nan()
2
and then adjusting the result. We can do the same trick for creating
3
the floatx80 default NaN, which lets us drop a target ifdef.
2
4
3
Because of the PMU's design, many register accesses have side effects
5
floatx80 is used only by:
4
which are inter-related, meaning that the normal method of saving CP
6
i386
5
registers can result in inconsistent state. These side-effects are
7
m68k
6
largely handled in pmu_op_start/finish functions which can be called
8
arm nwfpe old floating-point emulation emulation support
7
before and after the state is saved/restored. By doing this and adding
9
(which is essentially dead, especially the parts involving floatx80)
8
raw read/write functions for the affected registers, we avoid
10
PPC (only in the xsrqpxp instruction, which just rounds an input
9
migration-related inconsistencies.
11
value by converting to floatx80 and back, so will never generate
12
the default NaN)
10
13
11
Signed-off-by: Aaron Lindsay <aclindsa@gmail.com>
14
The floatx80 default NaN as currently implemented is:
12
Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
15
m68k: sign = 0, exp = 1...1, int = 1, frac = 1....1
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
16
i386: sign = 1, exp = 1...1, int = 1, frac = 10...0
14
Message-id: 20181211151945.29137-4-aaron@os.amperecomputing.com
17
18
These are the same as the parts64_default_nan for these architectures.
19
20
This is technically a possible behaviour change for arm linux-user
21
nwfpe emulation emulation, because the default NaN will now have the
22
sign bit clear. But we were already generating a different floatx80
23
default NaN from the real kernel emulation we are supposedly
24
following, which appears to use an all-bits-1 value:
25
https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L267
26
27
This won't affect the only "real" use of the nwfpe emulation, which
28
is ancient binaries that used it as part of the old floating point
29
calling convention; that only uses loads and stores of 32 and 64 bit
30
floats, not any of the floatx80 behaviour the original hardware had.
31
We also get the nwfpe float64 default NaN value wrong:
32
https://elixir.bootlin.com/linux/v6.12/source/arch/arm/nwfpe/softfloat-specialize#L166
33
so if we ever cared about this obscure corner the right fix would be
34
to correct that so nwfpe used its own default-NaN setting rather
35
than the Arm VFP one.
36
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
37
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
38
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
39
Message-id: 20241202131347.498124-29-peter.maydell@linaro.org
16
---
40
---
17
target/arm/helper.c | 6 ++++--
41
fpu/softfloat-specialize.c.inc | 20 ++++++++++----------
18
target/arm/machine.c | 24 ++++++++++++++++++++++++
42
1 file changed, 10 insertions(+), 10 deletions(-)
19
2 files changed, 28 insertions(+), 2 deletions(-)
20
43
21
diff --git a/target/arm/helper.c b/target/arm/helper.c
44
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
22
index XXXXXXX..XXXXXXX 100644
45
index XXXXXXX..XXXXXXX 100644
23
--- a/target/arm/helper.c
46
--- a/fpu/softfloat-specialize.c.inc
24
+++ b/target/arm/helper.c
47
+++ b/fpu/softfloat-specialize.c.inc
25
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
48
@@ -XXX,XX +XXX,XX @@ static void parts128_silence_nan(FloatParts128 *p, float_status *status)
26
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 0,
49
floatx80 floatx80_default_nan(float_status *status)
27
.access = PL0_RW, .accessfn = pmreg_access_ccntr,
28
.type = ARM_CP_IO,
29
- .readfn = pmccntr_read, .writefn = pmccntr_write, },
30
+ .fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt),
31
+ .readfn = pmccntr_read, .writefn = pmccntr_write,
32
+ .raw_readfn = raw_read, .raw_writefn = raw_write, },
33
#endif
34
{ .name = "PMCCFILTR_EL0", .state = ARM_CP_STATE_AA64,
35
.opc0 = 3, .opc1 = 3, .crn = 14, .crm = 15, .opc2 = 7,
36
- .writefn = pmccfiltr_write,
37
+ .writefn = pmccfiltr_write, .raw_writefn = raw_write,
38
.access = PL0_RW, .accessfn = pmreg_access,
39
.type = ARM_CP_IO,
40
.fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
41
diff --git a/target/arm/machine.c b/target/arm/machine.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/machine.c
44
+++ b/target/arm/machine.c
45
@@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque)
46
{
50
{
47
ARMCPU *cpu = opaque;
51
floatx80 r;
48
52
+ /*
49
+ if (!kvm_enabled()) {
53
+ * Extrapolate from the choices made by parts64_default_nan to fill
50
+ pmu_op_start(&cpu->env);
54
+ * in the floatx80 format. We assume that floatx80's explicit
51
+ }
55
+ * integer bit is always set (this is true for i386 and m68k,
52
+
56
+ * which are the only real users of this format).
53
if (kvm_enabled()) {
57
+ */
54
if (!write_kvmstate_to_list(cpu)) {
58
+ FloatParts64 p64;
55
/* This should never fail */
59
+ parts64_default_nan(&p64, status);
56
@@ -XXX,XX +XXX,XX @@ static int cpu_pre_save(void *opaque)
60
57
return 0;
61
- /* None of the targets that have snan_bit_is_one use floatx80. */
62
- assert(!snan_bit_is_one(status));
63
-#if defined(TARGET_M68K)
64
- r.low = UINT64_C(0xFFFFFFFFFFFFFFFF);
65
- r.high = 0x7FFF;
66
-#else
67
- /* X86 */
68
- r.low = UINT64_C(0xC000000000000000);
69
- r.high = 0xFFFF;
70
-#endif
71
+ r.high = 0x7FFF | (p64.sign << 15);
72
+ r.low = (1ULL << DECOMPOSED_BINARY_POINT) | p64.frac;
73
return r;
58
}
74
}
59
75
60
+static int cpu_post_save(void *opaque)
61
+{
62
+ ARMCPU *cpu = opaque;
63
+
64
+ if (!kvm_enabled()) {
65
+ pmu_op_finish(&cpu->env);
66
+ }
67
+
68
+ return 0;
69
+}
70
+
71
static int cpu_pre_load(void *opaque)
72
{
73
ARMCPU *cpu = opaque;
74
@@ -XXX,XX +XXX,XX @@ static int cpu_pre_load(void *opaque)
75
*/
76
env->irq_line_state = UINT32_MAX;
77
78
+ if (!kvm_enabled()) {
79
+ pmu_op_start(&cpu->env);
80
+ }
81
+
82
return 0;
83
}
84
85
@@ -XXX,XX +XXX,XX @@ static int cpu_post_load(void *opaque, int version_id)
86
hw_breakpoint_update_all(cpu);
87
hw_watchpoint_update_all(cpu);
88
89
+ if (!kvm_enabled()) {
90
+ pmu_op_finish(&cpu->env);
91
+ }
92
+
93
return 0;
94
}
95
96
@@ -XXX,XX +XXX,XX @@ const VMStateDescription vmstate_arm_cpu = {
97
.version_id = 22,
98
.minimum_version_id = 22,
99
.pre_save = cpu_pre_save,
100
+ .post_save = cpu_post_save,
101
.pre_load = cpu_pre_load,
102
.post_load = cpu_post_load,
103
.fields = (VMStateField[]) {
104
--
76
--
105
2.20.1
77
2.34.1
106
107
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/49] target/arm: Decode PAuth within disas_data_proc_2src
[PULL 34/72] target/loongarch: Use normal float_status in fclass_s and fclass_d helpers
1
From: Richard Henderson <richard.henderson@linaro.org>
1
In target/loongarch's helper_fclass_s() and helper_fclass_d() we pass
2
a zero-initialized float_status struct to float32_is_quiet_nan() and
3
float64_is_quiet_nan(), with the cryptic comment "for
4
snan_bit_is_one".
2
5
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
This pattern appears to have been copied from target/riscv, where it
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
is used because the functions there do not have ready access to the
5
Message-id: 20190108223129.5570-10-richard.henderson@linaro.org
8
CPU state struct. The comment presumably refers to the fact that the
9
main reason the is_quiet_nan() functions want the float_state is
10
because they want to know about the snan_bit_is_one config.
11
12
In the loongarch helpers, though, we have the CPU state struct
13
to hand. Use the usual env->fp_status here. This avoids our needing
14
to track that we need to update the initializer of the local
15
float_status structs when the core softfloat code adds new
16
options for targets to configure their behaviour.
17
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
20
Message-id: 20241202131347.498124-30-peter.maydell@linaro.org
7
---
21
---
8
target/arm/translate-a64.c | 8 ++++++++
22
target/loongarch/tcg/fpu_helper.c | 6 ++----
9
1 file changed, 8 insertions(+)
23
1 file changed, 2 insertions(+), 4 deletions(-)
10
24
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
25
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
12
index XXXXXXX..XXXXXXX 100644
26
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
27
--- a/target/loongarch/tcg/fpu_helper.c
14
+++ b/target/arm/translate-a64.c
28
+++ b/target/loongarch/tcg/fpu_helper.c
15
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
29
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_s(CPULoongArchState *env, uint64_t fj)
16
case 11: /* RORV */
30
} else if (float32_is_zero_or_denormal(f)) {
17
handle_shift_reg(s, A64_SHIFT_TYPE_ROR, sf, rm, rn, rd);
31
return sign ? 1 << 4 : 1 << 8;
18
break;
32
} else if (float32_is_any_nan(f)) {
19
+ case 12: /* PACGA */
33
- float_status s = { }; /* for snan_bit_is_one */
20
+ if (sf == 0 || !dc_isar_feature(aa64_pauth, s)) {
34
- return float32_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0;
21
+ goto do_unallocated;
35
+ return float32_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0;
22
+ }
36
} else {
23
+ gen_helper_pacga(cpu_reg(s, rd), cpu_env,
37
return sign ? 1 << 3 : 1 << 7;
24
+ cpu_reg(s, rn), cpu_reg_sp(s, rm));
25
+ break;
26
case 16:
27
case 17:
28
case 18:
29
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
30
break;
31
}
38
}
32
default:
39
@@ -XXX,XX +XXX,XX @@ uint64_t helper_fclass_d(CPULoongArchState *env, uint64_t fj)
33
+ do_unallocated:
40
} else if (float64_is_zero_or_denormal(f)) {
34
unallocated_encoding(s);
41
return sign ? 1 << 4 : 1 << 8;
35
break;
42
} else if (float64_is_any_nan(f)) {
43
- float_status s = { }; /* for snan_bit_is_one */
44
- return float64_is_quiet_nan(f, &s) ? 1 << 1 : 1 << 0;
45
+ return float64_is_quiet_nan(f, &env->fp_status) ? 1 << 1 : 1 << 0;
46
} else {
47
return sign ? 1 << 3 : 1 << 7;
36
}
48
}
37
--
49
--
38
2.20.1
50
2.34.1
39
40
diff view generated by jsdifflib
New patch
[PULL 35/72] target/m68k: In frem helper, initialize local float_status from env->fp_status
1
In the frem helper, we have a local float_status because we want to
2
execute the floatx80_div() with a custom rounding mode. Instead of
3
zero-initializing the local float_status and then having to set it up
4
with the m68k standard behaviour (including the NaN propagation rule
5
and copying the rounding precision from env->fp_status), initialize
6
it as a complete copy of env->fp_status. This will avoid our having
7
to add new code in this function for every new config knob we add
8
to fp_status.
1
9
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-31-peter.maydell@linaro.org
13
---
14
target/m68k/fpu_helper.c | 6 ++----
15
1 file changed, 2 insertions(+), 4 deletions(-)
16
17
diff --git a/target/m68k/fpu_helper.c b/target/m68k/fpu_helper.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/target/m68k/fpu_helper.c
20
+++ b/target/m68k/fpu_helper.c
21
@@ -XXX,XX +XXX,XX @@ void HELPER(frem)(CPUM68KState *env, FPReg *res, FPReg *val0, FPReg *val1)
22
23
fp_rem = floatx80_rem(val1->d, val0->d, &env->fp_status);
24
if (!floatx80_is_any_nan(fp_rem)) {
25
- float_status fp_status = { };
26
+ /* Use local temporary fp_status to set different rounding mode */
27
+ float_status fp_status = env->fp_status;
28
uint32_t quotient;
29
int sign;
30
31
/* Calculate quotient directly using round to nearest mode */
32
- set_float_2nan_prop_rule(float_2nan_prop_ab, &fp_status);
33
set_float_rounding_mode(float_round_nearest_even, &fp_status);
34
- set_floatx80_rounding_precision(
35
- get_floatx80_rounding_precision(&env->fp_status), &fp_status);
36
fp_quot.d = floatx80_div(val1->d, val0->d, &fp_status);
37
38
sign = extractFloatx80Sign(fp_quot.d);
39
--
40
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/49] target/arm: Decode PAuth within disas_data_proc_1src
[PULL 36/72] target/m68k: Init local float_status from env fp_status in gdb get/set reg
1
From: Richard Henderson <richard.henderson@linaro.org>
1
In cf_fpu_gdb_get_reg() and cf_fpu_gdb_set_reg() we do the conversion
2
from float64 to floatx80 using a scratch float_status, because we
3
don't want the conversion to affect the CPU's floating point exception
4
status. Currently we use a zero-initialized float_status. This will
5
get steadily more awkward as we add config knobs to float_status
6
that the target must initialize. Avoid having to add any of that
7
configuration here by instead initializing our local float_status
8
from the env->fp_status.
2
9
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20190108223129.5570-9-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-32-peter.maydell@linaro.org
7
---
13
---
8
target/arm/translate-a64.c | 146 +++++++++++++++++++++++++++++++++++++
14
target/m68k/helper.c | 6 ++++--
9
1 file changed, 146 insertions(+)
15
1 file changed, 4 insertions(+), 2 deletions(-)
10
16
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
17
diff --git a/target/m68k/helper.c b/target/m68k/helper.c
12
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
19
--- a/target/m68k/helper.c
14
+++ b/target/arm/translate-a64.c
20
+++ b/target/m68k/helper.c
15
@@ -XXX,XX +XXX,XX @@ static void handle_rev16(DisasContext *s, unsigned int sf,
21
@@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n)
16
static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
22
CPUM68KState *env = &cpu->env;
17
{
23
18
unsigned int sf, opcode, opcode2, rn, rd;
24
if (n < 8) {
19
+ TCGv_i64 tcg_rd;
25
- float_status s = {};
20
26
+ /* Use scratch float_status so any exceptions don't change CPU state */
21
if (extract32(insn, 29, 1)) {
27
+ float_status s = env->fp_status;
22
unallocated_encoding(s);
28
return gdb_get_reg64(mem_buf, floatx80_to_float64(env->fregs[n].d, &s));
23
@@ -XXX,XX +XXX,XX @@ static void disas_data_proc_1src(DisasContext *s, uint32_t insn)
29
}
24
case MAP(1, 0x00, 0x05):
30
switch (n) {
25
handle_cls(s, sf, rn, rd);
31
@@ -XXX,XX +XXX,XX @@ static int cf_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n)
26
break;
32
CPUM68KState *env = &cpu->env;
27
+ case MAP(1, 0x01, 0x00): /* PACIA */
33
28
+ if (s->pauth_active) {
34
if (n < 8) {
29
+ tcg_rd = cpu_reg(s, rd);
35
- float_status s = {};
30
+ gen_helper_pacia(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn));
36
+ /* Use scratch float_status so any exceptions don't change CPU state */
31
+ } else if (!dc_isar_feature(aa64_pauth, s)) {
37
+ float_status s = env->fp_status;
32
+ goto do_unallocated;
38
env->fregs[n].d = float64_to_floatx80(ldq_be_p(mem_buf), &s);
33
+ }
39
return 8;
34
+ break;
35
+ case MAP(1, 0x01, 0x01): /* PACIB */
36
+ if (s->pauth_active) {
37
+ tcg_rd = cpu_reg(s, rd);
38
+ gen_helper_pacib(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn));
39
+ } else if (!dc_isar_feature(aa64_pauth, s)) {
40
+ goto do_unallocated;
41
+ }
42
+ break;
43
+ case MAP(1, 0x01, 0x02): /* PACDA */
44
+ if (s->pauth_active) {
45
+ tcg_rd = cpu_reg(s, rd);
46
+ gen_helper_pacda(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn));
47
+ } else if (!dc_isar_feature(aa64_pauth, s)) {
48
+ goto do_unallocated;
49
+ }
50
+ break;
51
+ case MAP(1, 0x01, 0x03): /* PACDB */
52
+ if (s->pauth_active) {
53
+ tcg_rd = cpu_reg(s, rd);
54
+ gen_helper_pacdb(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn));
55
+ } else if (!dc_isar_feature(aa64_pauth, s)) {
56
+ goto do_unallocated;
57
+ }
58
+ break;
59
+ case MAP(1, 0x01, 0x04): /* AUTIA */
60
+ if (s->pauth_active) {
61
+ tcg_rd = cpu_reg(s, rd);
62
+ gen_helper_autia(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn));
63
+ } else if (!dc_isar_feature(aa64_pauth, s)) {
64
+ goto do_unallocated;
65
+ }
66
+ break;
67
+ case MAP(1, 0x01, 0x05): /* AUTIB */
68
+ if (s->pauth_active) {
69
+ tcg_rd = cpu_reg(s, rd);
70
+ gen_helper_autib(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn));
71
+ } else if (!dc_isar_feature(aa64_pauth, s)) {
72
+ goto do_unallocated;
73
+ }
74
+ break;
75
+ case MAP(1, 0x01, 0x06): /* AUTDA */
76
+ if (s->pauth_active) {
77
+ tcg_rd = cpu_reg(s, rd);
78
+ gen_helper_autda(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn));
79
+ } else if (!dc_isar_feature(aa64_pauth, s)) {
80
+ goto do_unallocated;
81
+ }
82
+ break;
83
+ case MAP(1, 0x01, 0x07): /* AUTDB */
84
+ if (s->pauth_active) {
85
+ tcg_rd = cpu_reg(s, rd);
86
+ gen_helper_autdb(tcg_rd, cpu_env, tcg_rd, cpu_reg_sp(s, rn));
87
+ } else if (!dc_isar_feature(aa64_pauth, s)) {
88
+ goto do_unallocated;
89
+ }
90
+ break;
91
+ case MAP(1, 0x01, 0x08): /* PACIZA */
92
+ if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
93
+ goto do_unallocated;
94
+ } else if (s->pauth_active) {
95
+ tcg_rd = cpu_reg(s, rd);
96
+ gen_helper_pacia(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s));
97
+ }
98
+ break;
99
+ case MAP(1, 0x01, 0x09): /* PACIZB */
100
+ if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
101
+ goto do_unallocated;
102
+ } else if (s->pauth_active) {
103
+ tcg_rd = cpu_reg(s, rd);
104
+ gen_helper_pacib(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s));
105
+ }
106
+ break;
107
+ case MAP(1, 0x01, 0x0a): /* PACDZA */
108
+ if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
109
+ goto do_unallocated;
110
+ } else if (s->pauth_active) {
111
+ tcg_rd = cpu_reg(s, rd);
112
+ gen_helper_pacda(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s));
113
+ }
114
+ break;
115
+ case MAP(1, 0x01, 0x0b): /* PACDZB */
116
+ if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
117
+ goto do_unallocated;
118
+ } else if (s->pauth_active) {
119
+ tcg_rd = cpu_reg(s, rd);
120
+ gen_helper_pacdb(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s));
121
+ }
122
+ break;
123
+ case MAP(1, 0x01, 0x0c): /* AUTIZA */
124
+ if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
125
+ goto do_unallocated;
126
+ } else if (s->pauth_active) {
127
+ tcg_rd = cpu_reg(s, rd);
128
+ gen_helper_autia(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s));
129
+ }
130
+ break;
131
+ case MAP(1, 0x01, 0x0d): /* AUTIZB */
132
+ if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
133
+ goto do_unallocated;
134
+ } else if (s->pauth_active) {
135
+ tcg_rd = cpu_reg(s, rd);
136
+ gen_helper_autib(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s));
137
+ }
138
+ break;
139
+ case MAP(1, 0x01, 0x0e): /* AUTDZA */
140
+ if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
141
+ goto do_unallocated;
142
+ } else if (s->pauth_active) {
143
+ tcg_rd = cpu_reg(s, rd);
144
+ gen_helper_autda(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s));
145
+ }
146
+ break;
147
+ case MAP(1, 0x01, 0x0f): /* AUTDZB */
148
+ if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
149
+ goto do_unallocated;
150
+ } else if (s->pauth_active) {
151
+ tcg_rd = cpu_reg(s, rd);
152
+ gen_helper_autdb(tcg_rd, cpu_env, tcg_rd, new_tmp_a64_zero(s));
153
+ }
154
+ break;
155
+ case MAP(1, 0x01, 0x10): /* XPACI */
156
+ if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
157
+ goto do_unallocated;
158
+ } else if (s->pauth_active) {
159
+ tcg_rd = cpu_reg(s, rd);
160
+ gen_helper_xpaci(tcg_rd, cpu_env, tcg_rd);
161
+ }
162
+ break;
163
+ case MAP(1, 0x01, 0x11): /* XPACD */
164
+ if (!dc_isar_feature(aa64_pauth, s) || rn != 31) {
165
+ goto do_unallocated;
166
+ } else if (s->pauth_active) {
167
+ tcg_rd = cpu_reg(s, rd);
168
+ gen_helper_xpacd(tcg_rd, cpu_env, tcg_rd);
169
+ }
170
+ break;
171
default:
172
+ do_unallocated:
173
unallocated_encoding(s);
174
break;
175
}
40
}
176
--
41
--
177
2.20.1
42
2.34.1
178
179
diff view generated by jsdifflib
[Qemu-devel] [PULL 37/49] target/arm: Reorganize PMCCNTR accesses
[PULL 37/72] target/sparc: Initialize local scratch float_status from env->fp_status
1
From: Aaron Lindsay <aaron@os.amperecomputing.com>
1
In the helper functions flcmps and flcmpd we use a scratch float_status
2
so that we don't change the CPU state if the comparison raises any
3
floating point exception flags. Instead of zero-initializing this
4
scratch float_status, initialize it as a copy of env->fp_status. This
5
avoids the need to explicitly initialize settings like the NaN
6
propagation rule or others we might add to softfloat in future.
2
7
3
pmccntr_read and pmccntr_write contained duplicate code that was already
8
To do this we need to pass the CPU env pointer in to the helper.
4
being handled by pmccntr_sync. Consolidate the duplicated code into two
5
functions: pmccntr_op_start and pmccntr_op_finish. Add a companion to
6
c15_ccnt in CPUARMState so that we can simultaneously save both the
7
architectural register value and the last underlying cycle count - this
8
ensures time isn't lost and will also allow us to access the 'old'
9
architectural register value in order to detect overflows in later
10
patches.
11
9
12
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
13
Signed-off-by: Aaron Lindsay <aclindsa@gmail.com>
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Message-id: 20181211151945.29137-3-aaron@os.amperecomputing.com
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Message-id: 20241202131347.498124-33-peter.maydell@linaro.org
17
---
13
---
18
target/arm/cpu.h | 37 +++++++++++---
14
target/sparc/helper.h | 4 ++--
19
target/arm/helper.c | 118 ++++++++++++++++++++++++++------------------
15
target/sparc/fop_helper.c | 8 ++++----
20
2 files changed, 100 insertions(+), 55 deletions(-)
16
target/sparc/translate.c | 4 ++--
17
3 files changed, 8 insertions(+), 8 deletions(-)
21
18
22
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
19
diff --git a/target/sparc/helper.h b/target/sparc/helper.h
23
index XXXXXXX..XXXXXXX 100644
20
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/cpu.h
21
--- a/target/sparc/helper.h
25
+++ b/target/arm/cpu.h
22
+++ b/target/sparc/helper.h
26
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
23
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_FLAGS_3(fcmpd, TCG_CALL_NO_WG, i32, env, f64, f64)
27
uint64_t oslsr_el1; /* OS Lock Status */
24
DEF_HELPER_FLAGS_3(fcmped, TCG_CALL_NO_WG, i32, env, f64, f64)
28
uint64_t mdcr_el2;
25
DEF_HELPER_FLAGS_3(fcmpq, TCG_CALL_NO_WG, i32, env, i128, i128)
29
uint64_t mdcr_el3;
26
DEF_HELPER_FLAGS_3(fcmpeq, TCG_CALL_NO_WG, i32, env, i128, i128)
30
- /* If the counter is enabled, this stores the last time the counter
27
-DEF_HELPER_FLAGS_2(flcmps, TCG_CALL_NO_RWG_SE, i32, f32, f32)
31
- * was reset. Otherwise it stores the counter value
28
-DEF_HELPER_FLAGS_2(flcmpd, TCG_CALL_NO_RWG_SE, i32, f64, f64)
32
+ /* Stores the architectural value of the counter *the last time it was
29
+DEF_HELPER_FLAGS_3(flcmps, TCG_CALL_NO_RWG_SE, i32, env, f32, f32)
33
+ * updated* by pmccntr_op_start. Accesses should always be surrounded
30
+DEF_HELPER_FLAGS_3(flcmpd, TCG_CALL_NO_RWG_SE, i32, env, f64, f64)
34
+ * by pmccntr_op_start/pmccntr_op_finish to guarantee the latest
31
DEF_HELPER_2(raise_exception, noreturn, env, int)
35
+ * architecturally-correct value is being read/set.
32
36
*/
33
DEF_HELPER_FLAGS_3(faddd, TCG_CALL_NO_WG, f64, env, f64, f64)
37
uint64_t c15_ccnt;
34
diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c
38
+ /* Stores the delta between the architectural value and the underlying
39
+ * cycle count during normal operation. It is used to update c15_ccnt
40
+ * to be the correct architectural value before accesses. During
41
+ * accesses, c15_ccnt_delta contains the underlying count being used
42
+ * for the access, after which it reverts to the delta value in
43
+ * pmccntr_op_finish.
44
+ */
45
+ uint64_t c15_ccnt_delta;
46
uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
47
uint64_t vpidr_el2; /* Virtualization Processor ID Register */
48
uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */
49
@@ -XXX,XX +XXX,XX @@ int cpu_arm_signal_handler(int host_signum, void *pinfo,
50
void *puc);
51
52
/**
53
- * pmccntr_sync
54
+ * pmccntr_op_start/finish
55
* @env: CPUARMState
56
*
57
- * Synchronises the counter in the PMCCNTR. This must always be called twice,
58
- * once before any action that might affect the timer and again afterwards.
59
- * The function is used to swap the state of the register if required.
60
- * This only happens when not in user mode (!CONFIG_USER_ONLY)
61
+ * Convert the counter in the PMCCNTR between its delta form (the typical mode
62
+ * when it's enabled) and the guest-visible value. These two calls must always
63
+ * surround any action which might affect the counter.
64
*/
65
-void pmccntr_sync(CPUARMState *env);
66
+void pmccntr_op_start(CPUARMState *env);
67
+void pmccntr_op_finish(CPUARMState *env);
68
+
69
+/**
70
+ * pmu_op_start/finish
71
+ * @env: CPUARMState
72
+ *
73
+ * Convert all PMU counters between their delta form (the typical mode when
74
+ * they are enabled) and the guest-visible values. These two calls must
75
+ * surround any action which might affect the counters.
76
+ */
77
+void pmu_op_start(CPUARMState *env);
78
+void pmu_op_finish(CPUARMState *env);
79
80
/* SCTLR bit meanings. Several bits have been reused in newer
81
* versions of the architecture; in that case we define constants
82
diff --git a/target/arm/helper.c b/target/arm/helper.c
83
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
84
--- a/target/arm/helper.c
36
--- a/target/sparc/fop_helper.c
85
+++ b/target/arm/helper.c
37
+++ b/target/sparc/fop_helper.c
86
@@ -XXX,XX +XXX,XX @@ static inline bool arm_ccnt_enabled(CPUARMState *env)
38
@@ -XXX,XX +XXX,XX @@ uint32_t helper_fcmpeq(CPUSPARCState *env, Int128 src1, Int128 src2)
87
39
return finish_fcmp(env, r, GETPC());
88
return true;
89
}
40
}
90
-
41
91
-void pmccntr_sync(CPUARMState *env)
42
-uint32_t helper_flcmps(float32 src1, float32 src2)
92
+/*
43
+uint32_t helper_flcmps(CPUSPARCState *env, float32 src1, float32 src2)
93
+ * Ensure c15_ccnt is the guest-visible count so that operations such as
94
+ * enabling/disabling the counter or filtering, modifying the count itself,
95
+ * etc. can be done logically. This is essentially a no-op if the counter is
96
+ * not enabled at the time of the call.
97
+ */
98
+void pmccntr_op_start(CPUARMState *env)
99
{
44
{
100
- uint64_t temp_ticks;
45
/*
101
-
46
* FLCMP never raises an exception nor modifies any FSR fields.
102
- temp_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
47
* Perform the comparison with a dummy fp environment.
103
+ uint64_t cycles = 0;
48
*/
104
+ cycles = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
49
- float_status discard = { };
105
ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
50
+ float_status discard = env->fp_status;
106
51
FloatRelation r;
107
- if (env->cp15.c9_pmcr & PMCRD) {
52
108
- /* Increment once every 64 processor clock cycles */
53
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard);
109
- temp_ticks /= 64;
54
@@ -XXX,XX +XXX,XX @@ uint32_t helper_flcmps(float32 src1, float32 src2)
110
- }
55
g_assert_not_reached();
111
-
112
if (arm_ccnt_enabled(env)) {
113
- env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
114
+ uint64_t eff_cycles = cycles;
115
+ if (env->cp15.c9_pmcr & PMCRD) {
116
+ /* Increment once every 64 processor clock cycles */
117
+ eff_cycles /= 64;
118
+ }
119
+
120
+ env->cp15.c15_ccnt = eff_cycles - env->cp15.c15_ccnt_delta;
121
}
122
+ env->cp15.c15_ccnt_delta = cycles;
123
+}
124
+
125
+/*
126
+ * If PMCCNTR is enabled, recalculate the delta between the clock and the
127
+ * guest-visible count. A call to pmccntr_op_finish should follow every call to
128
+ * pmccntr_op_start.
129
+ */
130
+void pmccntr_op_finish(CPUARMState *env)
131
+{
132
+ if (arm_ccnt_enabled(env)) {
133
+ uint64_t prev_cycles = env->cp15.c15_ccnt_delta;
134
+
135
+ if (env->cp15.c9_pmcr & PMCRD) {
136
+ /* Increment once every 64 processor clock cycles */
137
+ prev_cycles /= 64;
138
+ }
139
+
140
+ env->cp15.c15_ccnt_delta = prev_cycles - env->cp15.c15_ccnt;
141
+ }
142
+}
143
+
144
+void pmu_op_start(CPUARMState *env)
145
+{
146
+ pmccntr_op_start(env);
147
+}
148
+
149
+void pmu_op_finish(CPUARMState *env)
150
+{
151
+ pmccntr_op_finish(env);
152
}
56
}
153
57
154
static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
58
-uint32_t helper_flcmpd(float64 src1, float64 src2)
155
uint64_t value)
59
+uint32_t helper_flcmpd(CPUSPARCState *env, float64 src1, float64 src2)
156
{
60
{
157
- pmccntr_sync(env);
61
- float_status discard = { };
158
+ pmu_op_start(env);
62
+ float_status discard = env->fp_status;
159
63
FloatRelation r;
160
if (value & PMCRC) {
64
161
/* The counter has been reset */
65
set_float_2nan_prop_rule(float_2nan_prop_s_ba, &discard);
162
@@ -XXX,XX +XXX,XX @@ static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
66
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
163
env->cp15.c9_pmcr &= ~0x39;
67
index XXXXXXX..XXXXXXX 100644
164
env->cp15.c9_pmcr |= (value & 0x39);
68
--- a/target/sparc/translate.c
165
69
+++ b/target/sparc/translate.c
166
- pmccntr_sync(env);
70
@@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPs(DisasContext *dc, arg_FLCMPs *a)
167
+ pmu_op_finish(env);
71
72
src1 = gen_load_fpr_F(dc, a->rs1);
73
src2 = gen_load_fpr_F(dc, a->rs2);
74
- gen_helper_flcmps(cpu_fcc[a->cc], src1, src2);
75
+ gen_helper_flcmps(cpu_fcc[a->cc], tcg_env, src1, src2);
76
return advance_pc(dc);
168
}
77
}
169
78
170
static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
79
@@ -XXX,XX +XXX,XX @@ static bool trans_FLCMPd(DisasContext *dc, arg_FLCMPd *a)
171
{
80
172
- uint64_t total_ticks;
81
src1 = gen_load_fpr_D(dc, a->rs1);
173
-
82
src2 = gen_load_fpr_D(dc, a->rs2);
174
- if (!arm_ccnt_enabled(env)) {
83
- gen_helper_flcmpd(cpu_fcc[a->cc], src1, src2);
175
- /* Counter is disabled, do not change value */
84
+ gen_helper_flcmpd(cpu_fcc[a->cc], tcg_env, src1, src2);
176
- return env->cp15.c15_ccnt;
85
return advance_pc(dc);
177
- }
178
-
179
- total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
180
- ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
181
-
182
- if (env->cp15.c9_pmcr & PMCRD) {
183
- /* Increment once every 64 processor clock cycles */
184
- total_ticks /= 64;
185
- }
186
- return total_ticks - env->cp15.c15_ccnt;
187
+ uint64_t ret;
188
+ pmccntr_op_start(env);
189
+ ret = env->cp15.c15_ccnt;
190
+ pmccntr_op_finish(env);
191
+ return ret;
192
}
86
}
193
87
194
static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
195
@@ -XXX,XX +XXX,XX @@ static void pmselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
196
static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
197
uint64_t value)
198
{
199
- uint64_t total_ticks;
200
-
201
- if (!arm_ccnt_enabled(env)) {
202
- /* Counter is disabled, set the absolute value */
203
- env->cp15.c15_ccnt = value;
204
- return;
205
- }
206
-
207
- total_ticks = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
208
- ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
209
-
210
- if (env->cp15.c9_pmcr & PMCRD) {
211
- /* Increment once every 64 processor clock cycles */
212
- total_ticks /= 64;
213
- }
214
- env->cp15.c15_ccnt = total_ticks - value;
215
+ pmccntr_op_start(env);
216
+ env->cp15.c15_ccnt = value;
217
+ pmccntr_op_finish(env);
218
}
219
220
static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
221
@@ -XXX,XX +XXX,XX @@ static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
222
223
#else /* CONFIG_USER_ONLY */
224
225
-void pmccntr_sync(CPUARMState *env)
226
+void pmccntr_op_start(CPUARMState *env)
227
+{
228
+}
229
+
230
+void pmccntr_op_finish(CPUARMState *env)
231
+{
232
+}
233
+
234
+void pmu_op_start(CPUARMState *env)
235
+{
236
+}
237
+
238
+void pmu_op_finish(CPUARMState *env)
239
{
240
}
241
242
@@ -XXX,XX +XXX,XX @@ void pmccntr_sync(CPUARMState *env)
243
static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
244
uint64_t value)
245
{
246
- pmccntr_sync(env);
247
+ pmccntr_op_start(env);
248
env->cp15.pmccfiltr_el0 = value & 0xfc000000;
249
- pmccntr_sync(env);
250
+ pmccntr_op_finish(env);
251
}
252
253
static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
254
--
88
--
255
2.20.1
89
2.34.1
256
257
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/49] hw/char/stm32f2xx_usart: Do not update data register when device is disabled
[PULL 38/72] target/ppc: Use env->fp_status in helper_compute_fprf functions
1
From: Philippe Mathieu-Daudé <philmd@redhat.com>
1
In the helper_compute_fprf functions, we pass a dummy float_status
2
in to the is_signaling_nan() function. This is unnecessary, because
3
we have convenient access to the CPU env pointer here and that
4
is already set up with the correct values for the snan_bit_is_one
5
and no_signaling_nans config settings. is_signaling_nan() doesn't
6
ever update the fp_status with any exception flags, so there is
7
no reason not to use env->fp_status here.
2
8
3
When the device is disabled, the internal circuitry keeps the data
9
Use env->fp_status instead of the dummy fp_status.
4
register loaded and doesn't update it.
5
10
6
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20190104182057.8778-1-philmd@redhat.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
13
Message-id: 20241202131347.498124-34-peter.maydell@linaro.org
10
---
14
---
11
hw/char/stm32f2xx_usart.c | 3 +--
15
target/ppc/fpu_helper.c | 3 +--
12
1 file changed, 1 insertion(+), 2 deletions(-)
16
1 file changed, 1 insertion(+), 2 deletions(-)
13
17
14
diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c
18
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
15
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/char/stm32f2xx_usart.c
20
--- a/target/ppc/fpu_helper.c
17
+++ b/hw/char/stm32f2xx_usart.c
21
+++ b/target/ppc/fpu_helper.c
18
@@ -XXX,XX +XXX,XX @@ static void stm32f2xx_usart_receive(void *opaque, const uint8_t *buf, int size)
22
@@ -XXX,XX +XXX,XX @@ void helper_compute_fprf_##tp(CPUPPCState *env, tp arg) \
19
{
23
} else if (tp##_is_infinity(arg)) { \
20
STM32F2XXUsartState *s = opaque;
24
fprf = neg ? 0x09 << FPSCR_FPRF : 0x05 << FPSCR_FPRF; \
21
25
} else { \
22
- s->usart_dr = *buf;
26
- float_status dummy = { }; /* snan_bit_is_one = 0 */ \
23
-
27
- if (tp##_is_signaling_nan(arg, &dummy)) { \
24
if (!(s->usart_cr1 & USART_CR1_UE && s->usart_cr1 & USART_CR1_RE)) {
28
+ if (tp##_is_signaling_nan(arg, &env->fp_status)) { \
25
/* USART not enabled - drop the chars */
29
fprf = 0x00 << FPSCR_FPRF; \
26
DB_PRINT("Dropping the chars\n");
30
} else { \
27
return;
31
fprf = 0x11 << FPSCR_FPRF; \
28
}
29
30
+ s->usart_dr = *buf;
31
s->usart_sr |= USART_SR_RXNE;
32
33
if (s->usart_cr1 & USART_CR1_RXNEIE) {
34
--
32
--
35
2.20.1
33
2.34.1
36
37
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/49] target/arm: Add PAuth helpers
[PULL 39/72] target/arm: Copy entire float_status in is_ebf
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The cryptographic internals are stubbed out for now,
3
Now that float_status has a bunch of fp parameters,
4
but the enable and trap bits are checked.
4
it is easier to copy an existing structure than create
5
one from scratch. Begin by copying the structure that
6
corresponds to the FPSR and make only the adjustments
7
required for BFloat16 semantics.
5
8
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20190108223129.5570-6-richard.henderson@linaro.org
12
Message-id: 20241203203949.483774-2-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
14
---
11
target/arm/Makefile.objs | 1 +
15
target/arm/tcg/vec_helper.c | 20 +++++++-------------
12
target/arm/helper-a64.h | 12 +++
16
1 file changed, 7 insertions(+), 13 deletions(-)
13
target/arm/internals.h | 6 ++
14
target/arm/pauth_helper.c | 186 ++++++++++++++++++++++++++++++++++++++
15
4 files changed, 205 insertions(+)
16
create mode 100644 target/arm/pauth_helper.c
17
17
18
diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
18
diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c
19
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/Makefile.objs
20
--- a/target/arm/tcg/vec_helper.c
21
+++ b/target/arm/Makefile.objs
21
+++ b/target/arm/tcg/vec_helper.c
22
@@ -XXX,XX +XXX,XX @@ obj-y += translate.o op_helper.o helper.o cpu.o
22
@@ -XXX,XX +XXX,XX @@ bool is_ebf(CPUARMState *env, float_status *statusp, float_status *oddstatusp)
23
obj-y += neon_helper.o iwmmxt_helper.o vec_helper.o
23
* no effect on AArch32 instructions.
24
obj-y += gdbstub.o
24
*/
25
obj-$(TARGET_AARCH64) += cpu64.o translate-a64.o helper-a64.o gdbstub64.o
25
bool ebf = is_a64(env) && env->vfp.fpcr & FPCR_EBF;
26
+obj-$(TARGET_AARCH64) += pauth_helper.o
26
- *statusp = (float_status){
27
obj-y += crypto_helper.o
27
- .tininess_before_rounding = float_tininess_before_rounding,
28
obj-$(CONFIG_SOFTMMU) += arm-powerctl.o
28
- .float_rounding_mode = float_round_to_odd_inf,
29
29
- .flush_to_zero = true,
30
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
30
- .flush_inputs_to_zero = true,
31
index XXXXXXX..XXXXXXX 100644
31
- .default_nan_mode = true,
32
--- a/target/arm/helper-a64.h
32
- };
33
+++ b/target/arm/helper-a64.h
34
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(advsimd_rinth, f16, f16, ptr)
35
DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr)
36
DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr)
37
DEF_HELPER_2(sqrt_f16, f16, f16, ptr)
38
+
33
+
39
+DEF_HELPER_FLAGS_3(pacia, TCG_CALL_NO_WG, i64, env, i64, i64)
34
+ *statusp = env->vfp.fp_status;
40
+DEF_HELPER_FLAGS_3(pacib, TCG_CALL_NO_WG, i64, env, i64, i64)
35
+ set_default_nan_mode(true, statusp);
41
+DEF_HELPER_FLAGS_3(pacda, TCG_CALL_NO_WG, i64, env, i64, i64)
36
42
+DEF_HELPER_FLAGS_3(pacdb, TCG_CALL_NO_WG, i64, env, i64, i64)
37
if (ebf) {
43
+DEF_HELPER_FLAGS_3(pacga, TCG_CALL_NO_WG, i64, env, i64, i64)
38
- float_status *fpst = &env->vfp.fp_status;
44
+DEF_HELPER_FLAGS_3(autia, TCG_CALL_NO_WG, i64, env, i64, i64)
39
- set_flush_to_zero(get_flush_to_zero(fpst), statusp);
45
+DEF_HELPER_FLAGS_3(autib, TCG_CALL_NO_WG, i64, env, i64, i64)
40
- set_flush_inputs_to_zero(get_flush_inputs_to_zero(fpst), statusp);
46
+DEF_HELPER_FLAGS_3(autda, TCG_CALL_NO_WG, i64, env, i64, i64)
41
- set_float_rounding_mode(get_float_rounding_mode(fpst), statusp);
47
+DEF_HELPER_FLAGS_3(autdb, TCG_CALL_NO_WG, i64, env, i64, i64)
42
-
48
+DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64)
43
/* EBF=1 needs to do a step with round-to-odd semantics */
49
+DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64)
44
*oddstatusp = *statusp;
50
diff --git a/target/arm/internals.h b/target/arm/internals.h
45
set_float_rounding_mode(float_round_to_odd, oddstatusp);
51
index XXXXXXX..XXXXXXX 100644
46
+ } else {
52
--- a/target/arm/internals.h
47
+ set_flush_to_zero(true, statusp);
53
+++ b/target/arm/internals.h
48
+ set_flush_inputs_to_zero(true, statusp);
54
@@ -XXX,XX +XXX,XX @@ enum arm_exception_class {
49
+ set_float_rounding_mode(float_round_to_odd_inf, statusp);
55
EC_CP14DTTRAP = 0x06,
50
}
56
EC_ADVSIMDFPACCESSTRAP = 0x07,
51
-
57
EC_FPIDTRAP = 0x08,
52
return ebf;
58
+ EC_PACTRAP = 0x09,
59
EC_CP14RRTTRAP = 0x0c,
60
EC_ILLEGALSTATE = 0x0e,
61
EC_AA32_SVC = 0x11,
62
@@ -XXX,XX +XXX,XX @@ static inline uint32_t syn_sve_access_trap(void)
63
return EC_SVEACCESSTRAP << ARM_EL_EC_SHIFT;
64
}
53
}
65
54
66
+static inline uint32_t syn_pactrap(void)
67
+{
68
+ return EC_PACTRAP << ARM_EL_EC_SHIFT;
69
+}
70
+
71
static inline uint32_t syn_insn_abort(int same_el, int ea, int s1ptw, int fsc)
72
{
73
return (EC_INSNABORT << ARM_EL_EC_SHIFT) | (same_el << ARM_EL_EC_SHIFT)
74
diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c
75
new file mode 100644
76
index XXXXXXX..XXXXXXX
77
--- /dev/null
78
+++ b/target/arm/pauth_helper.c
79
@@ -XXX,XX +XXX,XX @@
80
+/*
81
+ * ARM v8.3-PAuth Operations
82
+ *
83
+ * Copyright (c) 2019 Linaro, Ltd.
84
+ *
85
+ * This library is free software; you can redistribute it and/or
86
+ * modify it under the terms of the GNU Lesser General Public
87
+ * License as published by the Free Software Foundation; either
88
+ * version 2 of the License, or (at your option) any later version.
89
+ *
90
+ * This library is distributed in the hope that it will be useful,
91
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
92
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
93
+ * Lesser General Public License for more details.
94
+ *
95
+ * You should have received a copy of the GNU Lesser General Public
96
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
97
+ */
98
+
99
+#include "qemu/osdep.h"
100
+#include "cpu.h"
101
+#include "internals.h"
102
+#include "exec/exec-all.h"
103
+#include "exec/cpu_ldst.h"
104
+#include "exec/helper-proto.h"
105
+#include "tcg/tcg-gvec-desc.h"
106
+
107
+
108
+static uint64_t pauth_computepac(uint64_t data, uint64_t modifier,
109
+ ARMPACKey key)
110
+{
111
+ g_assert_not_reached(); /* FIXME */
112
+}
113
+
114
+static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier,
115
+ ARMPACKey *key, bool data)
116
+{
117
+ g_assert_not_reached(); /* FIXME */
118
+}
119
+
120
+static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier,
121
+ ARMPACKey *key, bool data, int keynumber)
122
+{
123
+ g_assert_not_reached(); /* FIXME */
124
+}
125
+
126
+static uint64_t pauth_strip(CPUARMState *env, uint64_t ptr, bool data)
127
+{
128
+ g_assert_not_reached(); /* FIXME */
129
+}
130
+
131
+static void QEMU_NORETURN pauth_trap(CPUARMState *env, int target_el,
132
+ uintptr_t ra)
133
+{
134
+ raise_exception_ra(env, EXCP_UDEF, syn_pactrap(), target_el, ra);
135
+}
136
+
137
+static void pauth_check_trap(CPUARMState *env, int el, uintptr_t ra)
138
+{
139
+ if (el < 2 && arm_feature(env, ARM_FEATURE_EL2)) {
140
+ uint64_t hcr = arm_hcr_el2_eff(env);
141
+ bool trap = !(hcr & HCR_API);
142
+ /* FIXME: ARMv8.1-VHE: trap only applies to EL1&0 regime. */
143
+ /* FIXME: ARMv8.3-NV: HCR_NV trap takes precedence for ERETA[AB]. */
144
+ if (trap) {
145
+ pauth_trap(env, 2, ra);
146
+ }
147
+ }
148
+ if (el < 3 && arm_feature(env, ARM_FEATURE_EL3)) {
149
+ if (!(env->cp15.scr_el3 & SCR_API)) {
150
+ pauth_trap(env, 3, ra);
151
+ }
152
+ }
153
+}
154
+
155
+static bool pauth_key_enabled(CPUARMState *env, int el, uint32_t bit)
156
+{
157
+ uint32_t sctlr;
158
+ if (el == 0) {
159
+ /* FIXME: ARMv8.1-VHE S2 translation regime. */
160
+ sctlr = env->cp15.sctlr_el[1];
161
+ } else {
162
+ sctlr = env->cp15.sctlr_el[el];
163
+ }
164
+ return (sctlr & bit) != 0;
165
+}
166
+
167
+uint64_t HELPER(pacia)(CPUARMState *env, uint64_t x, uint64_t y)
168
+{
169
+ int el = arm_current_el(env);
170
+ if (!pauth_key_enabled(env, el, SCTLR_EnIA)) {
171
+ return x;
172
+ }
173
+ pauth_check_trap(env, el, GETPC());
174
+ return pauth_addpac(env, x, y, &env->apia_key, false);
175
+}
176
+
177
+uint64_t HELPER(pacib)(CPUARMState *env, uint64_t x, uint64_t y)
178
+{
179
+ int el = arm_current_el(env);
180
+ if (!pauth_key_enabled(env, el, SCTLR_EnIB)) {
181
+ return x;
182
+ }
183
+ pauth_check_trap(env, el, GETPC());
184
+ return pauth_addpac(env, x, y, &env->apib_key, false);
185
+}
186
+
187
+uint64_t HELPER(pacda)(CPUARMState *env, uint64_t x, uint64_t y)
188
+{
189
+ int el = arm_current_el(env);
190
+ if (!pauth_key_enabled(env, el, SCTLR_EnDA)) {
191
+ return x;
192
+ }
193
+ pauth_check_trap(env, el, GETPC());
194
+ return pauth_addpac(env, x, y, &env->apda_key, true);
195
+}
196
+
197
+uint64_t HELPER(pacdb)(CPUARMState *env, uint64_t x, uint64_t y)
198
+{
199
+ int el = arm_current_el(env);
200
+ if (!pauth_key_enabled(env, el, SCTLR_EnDB)) {
201
+ return x;
202
+ }
203
+ pauth_check_trap(env, el, GETPC());
204
+ return pauth_addpac(env, x, y, &env->apdb_key, true);
205
+}
206
+
207
+uint64_t HELPER(pacga)(CPUARMState *env, uint64_t x, uint64_t y)
208
+{
209
+ uint64_t pac;
210
+
211
+ pauth_check_trap(env, arm_current_el(env), GETPC());
212
+ pac = pauth_computepac(x, y, env->apga_key);
213
+
214
+ return pac & 0xffffffff00000000ull;
215
+}
216
+
217
+uint64_t HELPER(autia)(CPUARMState *env, uint64_t x, uint64_t y)
218
+{
219
+ int el = arm_current_el(env);
220
+ if (!pauth_key_enabled(env, el, SCTLR_EnIA)) {
221
+ return x;
222
+ }
223
+ pauth_check_trap(env, el, GETPC());
224
+ return pauth_auth(env, x, y, &env->apia_key, false, 0);
225
+}
226
+
227
+uint64_t HELPER(autib)(CPUARMState *env, uint64_t x, uint64_t y)
228
+{
229
+ int el = arm_current_el(env);
230
+ if (!pauth_key_enabled(env, el, SCTLR_EnIB)) {
231
+ return x;
232
+ }
233
+ pauth_check_trap(env, el, GETPC());
234
+ return pauth_auth(env, x, y, &env->apib_key, false, 1);
235
+}
236
+
237
+uint64_t HELPER(autda)(CPUARMState *env, uint64_t x, uint64_t y)
238
+{
239
+ int el = arm_current_el(env);
240
+ if (!pauth_key_enabled(env, el, SCTLR_EnDA)) {
241
+ return x;
242
+ }
243
+ pauth_check_trap(env, el, GETPC());
244
+ return pauth_auth(env, x, y, &env->apda_key, true, 0);
245
+}
246
+
247
+uint64_t HELPER(autdb)(CPUARMState *env, uint64_t x, uint64_t y)
248
+{
249
+ int el = arm_current_el(env);
250
+ if (!pauth_key_enabled(env, el, SCTLR_EnDB)) {
251
+ return x;
252
+ }
253
+ pauth_check_trap(env, el, GETPC());
254
+ return pauth_auth(env, x, y, &env->apdb_key, true, 1);
255
+}
256
+
257
+uint64_t HELPER(xpaci)(CPUARMState *env, uint64_t a)
258
+{
259
+ return pauth_strip(env, a, false);
260
+}
261
+
262
+uint64_t HELPER(xpacd)(CPUARMState *env, uint64_t a)
263
+{
264
+ return pauth_strip(env, a, true);
265
+}
266
--
55
--
267
2.20.1
56
2.34.1
268
57
269
58
diff view generated by jsdifflib
[Qemu-devel] [PULL 45/49] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER
[PULL 40/72] fpu: Allow runtime choice of default NaN value
1
From: Aaron Lindsay <aaron@os.amperecomputing.com>
1
Currently we hardcode the default NaN value in parts64_default_nan()
2
using a compile-time ifdef ladder. This is awkward for two cases:
3
* for single-QEMU-binary we can't hard-code target-specifics like this
4
* for Arm FEAT_AFP the default NaN value depends on FPCR.AH
5
(specifically the sign bit is different)
2
6
3
Add arrays to hold the registers, the definitions themselves, access
7
Add a field to float_status to specify the default NaN value; fall
4
functions, and logic to reset counters when PMCR.P is set. Update
8
back to the old ifdef behaviour if these are not set.
5
filtering code to support counters other than PMCCNTR. Support migration
6
with raw read/write functions.
7
9
8
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
10
The default NaN value is specified by setting a uint8_t to a
9
Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
11
pattern corresponding to the sign and upper fraction parts of
12
the NaN; the lower bits of the fraction are set from bit 0 of
13
the pattern.
14
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
16
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Message-id: 20181211151945.29137-11-aaron@os.amperecomputing.com
17
Message-id: 20241202131347.498124-35-peter.maydell@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
18
---
14
target/arm/cpu.h | 3 +
19
include/fpu/softfloat-helpers.h | 11 +++++++
15
target/arm/helper.c | 296 +++++++++++++++++++++++++++++++++++++++++---
20
include/fpu/softfloat-types.h | 10 ++++++
16
2 files changed, 282 insertions(+), 17 deletions(-)
21
fpu/softfloat-specialize.c.inc | 55 ++++++++++++++++++++-------------
22
3 files changed, 54 insertions(+), 22 deletions(-)
17
23
18
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
24
diff --git a/include/fpu/softfloat-helpers.h b/include/fpu/softfloat-helpers.h
19
index XXXXXXX..XXXXXXX 100644
25
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/cpu.h
26
--- a/include/fpu/softfloat-helpers.h
21
+++ b/target/arm/cpu.h
27
+++ b/include/fpu/softfloat-helpers.h
22
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
28
@@ -XXX,XX +XXX,XX @@ static inline void set_float_infzeronan_rule(FloatInfZeroNaNRule rule,
23
* pmccntr_op_finish.
29
status->float_infzeronan_rule = rule;
24
*/
25
uint64_t c15_ccnt_delta;
26
+ uint64_t c14_pmevcntr[31];
27
+ uint64_t c14_pmevcntr_delta[31];
28
+ uint64_t c14_pmevtyper[31];
29
uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
30
uint64_t vpidr_el2; /* Virtualization Processor ID Register */
31
uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */
32
diff --git a/target/arm/helper.c b/target/arm/helper.c
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/helper.c
35
+++ b/target/arm/helper.c
36
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
37
#define PMCRDP 0x10
38
#define PMCRD 0x8
39
#define PMCRC 0x4
40
+#define PMCRP 0x2
41
#define PMCRE 0x1
42
43
#define PMXEVTYPER_P 0x80000000
44
@@ -XXX,XX +XXX,XX @@ uint64_t get_pmceid(CPUARMState *env, unsigned which)
45
return pmceid;
46
}
30
}
47
31
48
+/*
32
+static inline void set_float_default_nan_pattern(uint8_t dnan_pattern,
49
+ * Check at runtime whether a PMU event is supported for the current machine
33
+ float_status *status)
50
+ */
51
+static bool event_supported(uint16_t number)
52
+{
34
+{
53
+ if (number > MAX_EVENT_ID) {
35
+ status->default_nan_pattern = dnan_pattern;
54
+ return false;
55
+ }
56
+ return supported_event_map[number] != UNSUPPORTED_EVENT;
57
+}
36
+}
58
+
37
+
59
static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
38
static inline void set_flush_to_zero(bool val, float_status *status)
60
bool isread)
61
{
39
{
62
@@ -XXX,XX +XXX,XX @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
40
status->flush_to_zero = val;
63
prohibited = env->cp15.c9_pmcr & PMCRDP;
41
@@ -XXX,XX +XXX,XX @@ static inline FloatInfZeroNaNRule get_float_infzeronan_rule(float_status *status
64
}
42
return status->float_infzeronan_rule;
65
66
- /* TODO Remove assert, set filter to correct PMEVTYPER */
67
- assert(counter == 31);
68
- filter = env->cp15.pmccfiltr_el0;
69
+ if (counter == 31) {
70
+ filter = env->cp15.pmccfiltr_el0;
71
+ } else {
72
+ filter = env->cp15.c14_pmevtyper[counter];
73
+ }
74
75
p = filter & PMXEVTYPER_P;
76
u = filter & PMXEVTYPER_U;
77
@@ -XXX,XX +XXX,XX @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
78
filtered = m != p;
79
}
80
81
+ if (counter != 31) {
82
+ /*
83
+ * If not checking PMCCNTR, ensure the counter is setup to an event we
84
+ * support
85
+ */
86
+ uint16_t event = filter & PMXEVTYPER_EVTCOUNT;
87
+ if (!event_supported(event)) {
88
+ return false;
89
+ }
90
+ }
91
+
92
return enabled && !prohibited && !filtered;
93
}
43
}
94
44
95
@@ -XXX,XX +XXX,XX @@ void pmccntr_op_finish(CPUARMState *env)
45
+static inline uint8_t get_float_default_nan_pattern(float_status *status)
96
}
97
}
98
99
+static void pmevcntr_op_start(CPUARMState *env, uint8_t counter)
100
+{
46
+{
101
+
47
+ return status->default_nan_pattern;
102
+ uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT;
103
+ uint64_t count = 0;
104
+ if (event_supported(event)) {
105
+ uint16_t event_idx = supported_event_map[event];
106
+ count = pm_events[event_idx].get_count(env);
107
+ }
108
+
109
+ if (pmu_counter_enabled(env, counter)) {
110
+ env->cp15.c14_pmevcntr[counter] =
111
+ count - env->cp15.c14_pmevcntr_delta[counter];
112
+ }
113
+ env->cp15.c14_pmevcntr_delta[counter] = count;
114
+}
48
+}
115
+
49
+
116
+static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter)
50
static inline bool get_flush_to_zero(float_status *status)
117
+{
118
+ if (pmu_counter_enabled(env, counter)) {
119
+ env->cp15.c14_pmevcntr_delta[counter] -=
120
+ env->cp15.c14_pmevcntr[counter];
121
+ }
122
+}
123
+
124
void pmu_op_start(CPUARMState *env)
125
{
51
{
126
+ unsigned int i;
52
return status->flush_to_zero;
127
pmccntr_op_start(env);
53
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
128
+ for (i = 0; i < pmu_num_counters(env); i++) {
54
index XXXXXXX..XXXXXXX 100644
129
+ pmevcntr_op_start(env, i);
55
--- a/include/fpu/softfloat-types.h
130
+ }
56
+++ b/include/fpu/softfloat-types.h
131
}
57
@@ -XXX,XX +XXX,XX @@ typedef struct float_status {
132
58
/* should denormalised inputs go to zero and set the input_denormal flag? */
133
void pmu_op_finish(CPUARMState *env)
59
bool flush_inputs_to_zero;
60
bool default_nan_mode;
61
+ /*
62
+ * The pattern to use for the default NaN. Here the high bit specifies
63
+ * the default NaN's sign bit, and bits 6..0 specify the high bits of the
64
+ * fractional part. The low bits of the fractional part are copies of bit 0.
65
+ * The exponent of the default NaN is (as for any NaN) always all 1s.
66
+ * Note that a value of 0 here is not a valid NaN. The target must set
67
+ * this to the correct non-zero value, or we will assert when trying to
68
+ * create a default NaN.
69
+ */
70
+ uint8_t default_nan_pattern;
71
/*
72
* The flags below are not used on all specializations and may
73
* constant fold away (see snan_bit_is_one()/no_signalling_nans() in
74
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
75
index XXXXXXX..XXXXXXX 100644
76
--- a/fpu/softfloat-specialize.c.inc
77
+++ b/fpu/softfloat-specialize.c.inc
78
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
134
{
79
{
135
+ unsigned int i;
80
bool sign = 0;
136
pmccntr_op_finish(env);
81
uint64_t frac;
137
+ for (i = 0; i < pmu_num_counters(env); i++) {
82
+ uint8_t dnan_pattern = status->default_nan_pattern;
138
+ pmevcntr_op_finish(env, i);
83
139
+ }
84
+ if (dnan_pattern == 0) {
140
}
85
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
141
86
- /* !snan_bit_is_one, set all bits */
142
void pmu_pre_el_change(ARMCPU *cpu, void *ignored)
87
- frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
143
@@ -XXX,XX +XXX,XX @@ static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
88
-#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
144
env->cp15.c15_ccnt = 0;
89
+ /* Sign bit clear, all frac bits set */
145
}
90
+ dnan_pattern = 0b01111111;
146
91
+#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
147
+ if (value & PMCRP) {
92
|| defined(TARGET_MICROBLAZE)
148
+ unsigned int i;
93
- /* !snan_bit_is_one, set sign and msb */
149
+ for (i = 0; i < pmu_num_counters(env); i++) {
94
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
150
+ env->cp15.c14_pmevcntr[i] = 0;
95
- sign = 1;
151
+ }
96
+ /* Sign bit set, most significant frac bit set */
152
+ }
97
+ dnan_pattern = 0b11000000;
153
+
98
#elif defined(TARGET_HPPA)
154
/* only the DP, X, D and E bits are writable */
99
- /* snan_bit_is_one, set msb-1. */
155
env->cp15.c9_pmcr &= ~0x39;
100
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
156
env->cp15.c9_pmcr |= (value & 0x39);
101
+ /* Sign bit clear, msb-1 frac bit set */
157
@@ -XXX,XX +XXX,XX @@ void pmccntr_op_finish(CPUARMState *env)
102
+ dnan_pattern = 0b00100000;
158
{
103
#elif defined(TARGET_HEXAGON)
159
}
104
- sign = 1;
160
105
- frac = ~0ULL;
161
+void pmevcntr_op_start(CPUARMState *env, uint8_t i)
106
+ /* Sign bit set, all frac bits set. */
162
+{
107
+ dnan_pattern = 0b11111111;
163
+}
108
#else
164
+
109
- /*
165
+void pmevcntr_op_finish(CPUARMState *env, uint8_t i)
110
- * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
166
+{
111
- * S390, SH4, TriCore, and Xtensa. Our other supported targets
167
+}
112
- * do not have floating-point.
168
+
113
- */
169
void pmu_op_start(CPUARMState *env)
114
- if (snan_bit_is_one(status)) {
170
{
115
- /* set all bits other than msb */
171
}
116
- frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
172
@@ -XXX,XX +XXX,XX @@ static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri,
117
- } else {
173
env->cp15.c9_pmovsr |= value;
118
- /* set msb */
174
}
119
- frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
175
120
- }
176
-static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
177
- uint64_t value)
178
+static void pmevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
179
+ uint64_t value, const uint8_t counter)
180
{
181
+ if (counter == 31) {
182
+ pmccfiltr_write(env, ri, value);
183
+ } else if (counter < pmu_num_counters(env)) {
184
+ pmevcntr_op_start(env, counter);
185
+
186
+ /*
121
+ /*
187
+ * If this counter's event type is changing, store the current
122
+ * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
188
+ * underlying count for the new type in c14_pmevcntr_delta[counter] so
123
+ * S390, SH4, TriCore, and Xtensa. Our other supported targets
189
+ * pmevcntr_op_finish has the correct baseline when it converts back to
124
+ * do not have floating-point.
190
+ * a delta.
191
+ */
125
+ */
192
+ uint16_t old_event = env->cp15.c14_pmevtyper[counter] &
126
+ if (snan_bit_is_one(status)) {
193
+ PMXEVTYPER_EVTCOUNT;
127
+ /* sign bit clear, set all frac bits other than msb */
194
+ uint16_t new_event = value & PMXEVTYPER_EVTCOUNT;
128
+ dnan_pattern = 0b00111111;
195
+ if (old_event != new_event) {
129
+ } else {
196
+ uint64_t count = 0;
130
+ /* sign bit clear, set frac msb */
197
+ if (event_supported(new_event)) {
131
+ dnan_pattern = 0b01000000;
198
+ uint16_t event_idx = supported_event_map[new_event];
199
+ count = pm_events[event_idx].get_count(env);
200
+ }
201
+ env->cp15.c14_pmevcntr_delta[counter] = count;
202
+ }
203
+
204
+ env->cp15.c14_pmevtyper[counter] = value & PMXEVTYPER_MASK;
205
+ pmevcntr_op_finish(env, counter);
206
+ }
207
/* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
208
* PMSELR value is equal to or greater than the number of implemented
209
* counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
210
*/
211
- if (env->cp15.c9_pmselr == 0x1f) {
212
- pmccfiltr_write(env, ri, value);
213
+}
214
+
215
+static uint64_t pmevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri,
216
+ const uint8_t counter)
217
+{
218
+ if (counter == 31) {
219
+ return env->cp15.pmccfiltr_el0;
220
+ } else if (counter < pmu_num_counters(env)) {
221
+ return env->cp15.c14_pmevtyper[counter];
222
+ } else {
223
+ /*
224
+ * We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
225
+ * are CONSTRAINED UNPREDICTABLE. See comments in pmevtyper_write().
226
+ */
227
+ return 0;
228
}
229
}
230
231
+static void pmevtyper_writefn(CPUARMState *env, const ARMCPRegInfo *ri,
232
+ uint64_t value)
233
+{
234
+ uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
235
+ pmevtyper_write(env, ri, value, counter);
236
+}
237
+
238
+static void pmevtyper_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri,
239
+ uint64_t value)
240
+{
241
+ uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
242
+ env->cp15.c14_pmevtyper[counter] = value;
243
+
244
+ /*
245
+ * pmevtyper_rawwrite is called between a pair of pmu_op_start and
246
+ * pmu_op_finish calls when loading saved state for a migration. Because
247
+ * we're potentially updating the type of event here, the value written to
248
+ * c14_pmevcntr_delta by the preceeding pmu_op_start call may be for a
249
+ * different counter type. Therefore, we need to set this value to the
250
+ * current count for the counter type we're writing so that pmu_op_finish
251
+ * has the correct count for its calculation.
252
+ */
253
+ uint16_t event = value & PMXEVTYPER_EVTCOUNT;
254
+ if (event_supported(event)) {
255
+ uint16_t event_idx = supported_event_map[event];
256
+ env->cp15.c14_pmevcntr_delta[counter] =
257
+ pm_events[event_idx].get_count(env);
258
+ }
259
+}
260
+
261
+static uint64_t pmevtyper_readfn(CPUARMState *env, const ARMCPRegInfo *ri)
262
+{
263
+ uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
264
+ return pmevtyper_read(env, ri, counter);
265
+}
266
+
267
+static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
268
+ uint64_t value)
269
+{
270
+ pmevtyper_write(env, ri, value, env->cp15.c9_pmselr & 31);
271
+}
272
+
273
static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri)
274
{
275
- /* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
276
- * are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write().
277
+ return pmevtyper_read(env, ri, env->cp15.c9_pmselr & 31);
278
+}
279
+
280
+static void pmevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
281
+ uint64_t value, uint8_t counter)
282
+{
283
+ if (counter < pmu_num_counters(env)) {
284
+ pmevcntr_op_start(env, counter);
285
+ env->cp15.c14_pmevcntr[counter] = value;
286
+ pmevcntr_op_finish(env, counter);
287
+ }
288
+ /*
289
+ * We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
290
+ * are CONSTRAINED UNPREDICTABLE.
291
*/
292
- if (env->cp15.c9_pmselr == 0x1f) {
293
- return env->cp15.pmccfiltr_el0;
294
+}
295
+
296
+static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri,
297
+ uint8_t counter)
298
+{
299
+ if (counter < pmu_num_counters(env)) {
300
+ uint64_t ret;
301
+ pmevcntr_op_start(env, counter);
302
+ ret = env->cp15.c14_pmevcntr[counter];
303
+ pmevcntr_op_finish(env, counter);
304
+ return ret;
305
} else {
306
+ /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR
307
+ * are CONSTRAINED UNPREDICTABLE. */
308
return 0;
309
}
310
}
311
312
+static void pmevcntr_writefn(CPUARMState *env, const ARMCPRegInfo *ri,
313
+ uint64_t value)
314
+{
315
+ uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
316
+ pmevcntr_write(env, ri, value, counter);
317
+}
318
+
319
+static uint64_t pmevcntr_readfn(CPUARMState *env, const ARMCPRegInfo *ri)
320
+{
321
+ uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
322
+ return pmevcntr_read(env, ri, counter);
323
+}
324
+
325
+static void pmevcntr_rawwrite(CPUARMState *env, const ARMCPRegInfo *ri,
326
+ uint64_t value)
327
+{
328
+ uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
329
+ assert(counter < pmu_num_counters(env));
330
+ env->cp15.c14_pmevcntr[counter] = value;
331
+ pmevcntr_write(env, ri, value, counter);
332
+}
333
+
334
+static uint64_t pmevcntr_rawread(CPUARMState *env, const ARMCPRegInfo *ri)
335
+{
336
+ uint8_t counter = ((ri->crm & 3) << 3) | (ri->opc2 & 7);
337
+ assert(counter < pmu_num_counters(env));
338
+ return env->cp15.c14_pmevcntr[counter];
339
+}
340
+
341
+static void pmxevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
342
+ uint64_t value)
343
+{
344
+ pmevcntr_write(env, ri, value, env->cp15.c9_pmselr & 31);
345
+}
346
+
347
+static uint64_t pmxevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
348
+{
349
+ return pmevcntr_read(env, ri, env->cp15.c9_pmselr & 31);
350
+}
351
+
352
static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
353
uint64_t value)
354
{
355
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
356
.fieldoffset = offsetof(CPUARMState, cp15.pmccfiltr_el0),
357
.resetvalue = 0, },
358
{ .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
359
- .access = PL0_RW, .type = ARM_CP_NO_RAW, .accessfn = pmreg_access,
360
+ .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
361
+ .accessfn = pmreg_access,
362
.writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
363
{ .name = "PMXEVTYPER_EL0", .state = ARM_CP_STATE_AA64,
364
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 1,
365
- .access = PL0_RW, .type = ARM_CP_NO_RAW, .accessfn = pmreg_access,
366
+ .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
367
+ .accessfn = pmreg_access,
368
.writefn = pmxevtyper_write, .readfn = pmxevtyper_read },
369
- /* Unimplemented, RAZ/WI. */
370
{ .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
371
- .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
372
- .accessfn = pmreg_access_xevcntr },
373
+ .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
374
+ .accessfn = pmreg_access_xevcntr,
375
+ .writefn = pmxevcntr_write, .readfn = pmxevcntr_read },
376
+ { .name = "PMXEVCNTR_EL0", .state = ARM_CP_STATE_AA64,
377
+ .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 13, .opc2 = 2,
378
+ .access = PL0_RW, .type = ARM_CP_NO_RAW | ARM_CP_IO,
379
+ .accessfn = pmreg_access_xevcntr,
380
+ .writefn = pmxevcntr_write, .readfn = pmxevcntr_read },
381
{ .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
382
.access = PL0_R | PL1_RW, .accessfn = access_tpm,
383
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmuserenr),
384
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
385
#endif
386
/* The only field of MDCR_EL2 that has a defined architectural reset value
387
* is MDCR_EL2.HPMN which should reset to the value of PMCR_EL0.N; but we
388
- * don't impelment any PMU event counters, so using zero as a reset
389
+ * don't implement any PMU event counters, so using zero as a reset
390
* value for MDCR_EL2 is okay
391
*/
392
{ .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH,
393
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
394
* field as main ID register, and we implement only the cycle
395
* count register.
396
*/
397
+ unsigned int i, pmcrn = 0;
398
#ifndef CONFIG_USER_ONLY
399
ARMCPRegInfo pmcr = {
400
.name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
401
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
402
};
403
define_one_arm_cp_reg(cpu, &pmcr);
404
define_one_arm_cp_reg(cpu, &pmcr64);
405
+ for (i = 0; i < pmcrn; i++) {
406
+ char *pmevcntr_name = g_strdup_printf("PMEVCNTR%d", i);
407
+ char *pmevcntr_el0_name = g_strdup_printf("PMEVCNTR%d_EL0", i);
408
+ char *pmevtyper_name = g_strdup_printf("PMEVTYPER%d", i);
409
+ char *pmevtyper_el0_name = g_strdup_printf("PMEVTYPER%d_EL0", i);
410
+ ARMCPRegInfo pmev_regs[] = {
411
+ { .name = pmevcntr_name, .cp = 15, .crn = 15,
412
+ .crm = 8 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
413
+ .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
414
+ .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
415
+ .accessfn = pmreg_access },
416
+ { .name = pmevcntr_el0_name, .state = ARM_CP_STATE_AA64,
417
+ .opc0 = 3, .opc1 = 3, .crn = 15, .crm = 8 | (3 & (i >> 3)),
418
+ .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
419
+ .type = ARM_CP_IO,
420
+ .readfn = pmevcntr_readfn, .writefn = pmevcntr_writefn,
421
+ .raw_readfn = pmevcntr_rawread,
422
+ .raw_writefn = pmevcntr_rawwrite },
423
+ { .name = pmevtyper_name, .cp = 15, .crn = 15,
424
+ .crm = 12 | (3 & (i >> 3)), .opc1 = 0, .opc2 = i & 7,
425
+ .access = PL0_RW, .type = ARM_CP_IO | ARM_CP_ALIAS,
426
+ .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
427
+ .accessfn = pmreg_access },
428
+ { .name = pmevtyper_el0_name, .state = ARM_CP_STATE_AA64,
429
+ .opc0 = 3, .opc1 = 3, .crn = 15, .crm = 12 | (3 & (i >> 3)),
430
+ .opc2 = i & 7, .access = PL0_RW, .accessfn = pmreg_access,
431
+ .type = ARM_CP_IO,
432
+ .readfn = pmevtyper_readfn, .writefn = pmevtyper_writefn,
433
+ .raw_writefn = pmevtyper_rawwrite },
434
+ REGINFO_SENTINEL
435
+ };
436
+ define_arm_cp_regs(cpu, pmev_regs);
437
+ g_free(pmevcntr_name);
438
+ g_free(pmevcntr_el0_name);
439
+ g_free(pmevtyper_name);
440
+ g_free(pmevtyper_el0_name);
441
+ }
132
+ }
442
#endif
133
#endif
443
ARMCPRegInfo clidr = {
134
+ }
444
.name = "CLIDR", .state = ARM_CP_STATE_BOTH,
135
+ assert(dnan_pattern != 0);
136
+
137
+ sign = dnan_pattern >> 7;
138
+ /*
139
+ * Place default_nan_pattern [6:0] into bits [62:56],
140
+ * and replecate bit [0] down into [55:0]
141
+ */
142
+ frac = deposit64(0, DECOMPOSED_BINARY_POINT - 7, 7, dnan_pattern);
143
+ frac = deposit64(frac, 0, DECOMPOSED_BINARY_POINT - 7, -(dnan_pattern & 1));
144
145
*p = (FloatParts64) {
146
.cls = float_class_qnan,
445
--
147
--
446
2.20.1
148
2.34.1
447
448
diff view generated by jsdifflib
New patch
[PULL 41/72] tests/fp: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for the tests/fp code.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-36-peter.maydell@linaro.org
6
---
7
tests/fp/fp-bench.c | 1 +
8
tests/fp/fp-test-log2.c | 1 +
9
tests/fp/fp-test.c | 1 +
10
3 files changed, 3 insertions(+)
11
12
diff --git a/tests/fp/fp-bench.c b/tests/fp/fp-bench.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/tests/fp/fp-bench.c
15
+++ b/tests/fp/fp-bench.c
16
@@ -XXX,XX +XXX,XX @@ static void run_bench(void)
17
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &soft_status);
18
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &soft_status);
19
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &soft_status);
20
+ set_float_default_nan_pattern(0b01000000, &soft_status);
21
22
f = bench_funcs[operation][precision];
23
g_assert(f);
24
diff --git a/tests/fp/fp-test-log2.c b/tests/fp/fp-test-log2.c
25
index XXXXXXX..XXXXXXX 100644
26
--- a/tests/fp/fp-test-log2.c
27
+++ b/tests/fp/fp-test-log2.c
28
@@ -XXX,XX +XXX,XX @@ int main(int ac, char **av)
29
int i;
30
31
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
32
+ set_float_default_nan_pattern(0b01000000, &qsf);
33
set_float_rounding_mode(float_round_nearest_even, &qsf);
34
35
test.d = 0.0;
36
diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
37
index XXXXXXX..XXXXXXX 100644
38
--- a/tests/fp/fp-test.c
39
+++ b/tests/fp/fp-test.c
40
@@ -XXX,XX +XXX,XX @@ void run_test(void)
41
*/
42
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &qsf);
43
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &qsf);
44
+ set_float_default_nan_pattern(0b01000000, &qsf);
45
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, &qsf);
46
47
genCases_setLevel(test_level);
48
--
49
2.34.1
diff view generated by jsdifflib
New patch
[PULL 42/72] target/microblaze: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-37-peter.maydell@linaro.org
7
---
8
target/microblaze/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 +--
10
2 files changed, 3 insertions(+), 2 deletions(-)
11
12
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/microblaze/cpu.c
15
+++ b/target/microblaze/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void mb_cpu_reset_hold(Object *obj, ResetType type)
17
* this architecture.
18
*/
19
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
20
+ /* Default NaN: sign bit set, most significant frac bit set */
21
+ set_float_default_nan_pattern(0b11000000, &env->fp_status);
22
23
#if defined(CONFIG_USER_ONLY)
24
/* start in user mode with interrupts enabled. */
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
31
/* Sign bit clear, all frac bits set */
32
dnan_pattern = 0b01111111;
33
-#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
34
- || defined(TARGET_MICROBLAZE)
35
+#elif defined(TARGET_I386) || defined(TARGET_X86_64)
36
/* Sign bit set, most significant frac bit set */
37
dnan_pattern = 0b11000000;
38
#elif defined(TARGET_HPPA)
39
--
40
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 29/49] target/arm: Implement pauth_auth
[PULL 43/72] target/i386: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
2
3
3
This is not really functional yet, because the crypto is not yet
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
implemented. This, however follows the Auth pseudo function.
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-38-peter.maydell@linaro.org
7
---
8
target/i386/tcg/fpu_helper.c | 4 ++++
9
fpu/softfloat-specialize.c.inc | 3 ---
10
2 files changed, 4 insertions(+), 3 deletions(-)
5
11
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20190108223129.5570-26-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/pauth_helper.c | 21 ++++++++++++++++++++-
12
1 file changed, 20 insertions(+), 1 deletion(-)
13
14
diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c
15
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/pauth_helper.c
14
--- a/target/i386/tcg/fpu_helper.c
17
+++ b/target/arm/pauth_helper.c
15
+++ b/target/i386/tcg/fpu_helper.c
18
@@ -XXX,XX +XXX,XX @@ static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)
16
@@ -XXX,XX +XXX,XX @@ void cpu_init_fp_statuses(CPUX86State *env)
19
static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier,
17
*/
20
ARMPACKey *key, bool data, int keynumber)
18
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->sse_status);
21
{
19
set_float_3nan_prop_rule(float_3nan_prop_abc, &env->sse_status);
22
- g_assert_not_reached(); /* FIXME */
20
+ /* Default NaN: sign bit set, most significant frac bit set */
23
+ ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env);
21
+ set_float_default_nan_pattern(0b11000000, &env->fp_status);
24
+ ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data);
22
+ set_float_default_nan_pattern(0b11000000, &env->mmx_status);
25
+ int bot_bit, top_bit;
23
+ set_float_default_nan_pattern(0b11000000, &env->sse_status);
26
+ uint64_t pac, orig_ptr, test;
27
+
28
+ orig_ptr = pauth_original_ptr(ptr, param);
29
+ pac = pauth_computepac(orig_ptr, modifier, *key);
30
+ bot_bit = 64 - param.tsz;
31
+ top_bit = 64 - 8 * param.tbi;
32
+
33
+ test = (pac ^ ptr) & ~MAKE_64BIT_MASK(55, 1);
34
+ if (unlikely(extract64(test, bot_bit, top_bit - bot_bit))) {
35
+ int error_code = (keynumber << 1) | (keynumber ^ 1);
36
+ if (param.tbi) {
37
+ return deposit64(ptr, 53, 2, error_code);
38
+ } else {
39
+ return deposit64(ptr, 61, 2, error_code);
40
+ }
41
+ }
42
+ return orig_ptr;
43
}
24
}
44
25
45
static uint64_t pauth_strip(CPUARMState *env, uint64_t ptr, bool data)
26
static inline uint8_t save_exception_flags(CPUX86State *env)
27
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
28
index XXXXXXX..XXXXXXX 100644
29
--- a/fpu/softfloat-specialize.c.inc
30
+++ b/fpu/softfloat-specialize.c.inc
31
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
32
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
33
/* Sign bit clear, all frac bits set */
34
dnan_pattern = 0b01111111;
35
-#elif defined(TARGET_I386) || defined(TARGET_X86_64)
36
- /* Sign bit set, most significant frac bit set */
37
- dnan_pattern = 0b11000000;
38
#elif defined(TARGET_HPPA)
39
/* Sign bit clear, msb-1 frac bit set */
40
dnan_pattern = 0b00100000;
46
--
41
--
47
2.20.1
42
2.34.1
48
49
diff view generated by jsdifflib
[Qemu-devel] [PULL 28/49] target/arm: Implement pauth_strip
[PULL 44/72] target/hppa: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly, and remove the ifdef from
2
parts64_default_nan().
2
3
3
Stripping out the authentication data does not require any crypto,
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
it merely requires the virtual address parameters.
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-39-peter.maydell@linaro.org
7
---
8
target/hppa/fpu_helper.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 3 ---
10
2 files changed, 2 insertions(+), 3 deletions(-)
5
11
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
diff --git a/target/hppa/fpu_helper.c b/target/hppa/fpu_helper.c
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20190108223129.5570-25-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/pauth_helper.c | 14 +++++++++++++-
12
1 file changed, 13 insertions(+), 1 deletion(-)
13
14
diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c
15
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/pauth_helper.c
14
--- a/target/hppa/fpu_helper.c
17
+++ b/target/arm/pauth_helper.c
15
+++ b/target/hppa/fpu_helper.c
18
@@ -XXX,XX +XXX,XX @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier,
16
@@ -XXX,XX +XXX,XX @@ void HELPER(loaded_fr0)(CPUHPPAState *env)
19
g_assert_not_reached(); /* FIXME */
17
set_float_3nan_prop_rule(float_3nan_prop_abc, &env->fp_status);
18
/* For inf * 0 + NaN, return the input NaN */
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ /* Default NaN: sign bit clear, msb-1 frac bit set */
21
+ set_float_default_nan_pattern(0b00100000, &env->fp_status);
20
}
22
}
21
23
22
+static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param)
24
void cpu_hppa_loaded_fr0(CPUHPPAState *env)
23
+{
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
24
+ uint64_t extfield = -param.select;
26
index XXXXXXX..XXXXXXX 100644
25
+ int bot_pac_bit = 64 - param.tsz;
27
--- a/fpu/softfloat-specialize.c.inc
26
+ int top_pac_bit = 64 - 8 * param.tbi;
28
+++ b/fpu/softfloat-specialize.c.inc
27
+
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
28
+ return deposit64(ptr, bot_pac_bit, top_pac_bit - bot_pac_bit, extfield);
30
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
29
+}
31
/* Sign bit clear, all frac bits set */
30
+
32
dnan_pattern = 0b01111111;
31
static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier,
33
-#elif defined(TARGET_HPPA)
32
ARMPACKey *key, bool data, int keynumber)
34
- /* Sign bit clear, msb-1 frac bit set */
33
{
35
- dnan_pattern = 0b00100000;
34
@@ -XXX,XX +XXX,XX @@ static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier,
36
#elif defined(TARGET_HEXAGON)
35
37
/* Sign bit set, all frac bits set. */
36
static uint64_t pauth_strip(CPUARMState *env, uint64_t ptr, bool data)
38
dnan_pattern = 0b11111111;
37
{
38
- g_assert_not_reached(); /* FIXME */
39
+ ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env);
40
+ ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data);
41
+
42
+ return pauth_original_ptr(ptr, param);
43
}
44
45
static void QEMU_NORETURN pauth_trap(CPUARMState *env, int target_el,
46
--
39
--
47
2.20.1
40
2.34.1
48
49
diff view generated by jsdifflib
New patch
[PULL 45/72] target/alpha: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for the alpha target.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-40-peter.maydell@linaro.org
6
---
7
target/alpha/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/alpha/cpu.c
13
+++ b/target/alpha/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void alpha_cpu_initfn(Object *obj)
15
* operand in Fa. That is float_2nan_prop_ba.
16
*/
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
18
+ /* Default NaN: sign bit clear, msb frac bit set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
20
#if defined(CONFIG_USER_ONLY)
21
env->flags = ENV_FLAG_PS_USER | ENV_FLAG_FEN;
22
cpu_alpha_store_fpcr(env, (uint64_t)(FPCR_INVD | FPCR_DZED | FPCR_OVFD
23
--
24
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 44/49] target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0
[PULL 46/72] target/arm: Set default NaN pattern explicitly
1
From: Aaron Lindsay <aaron@os.amperecomputing.com>
1
Set the default NaN pattern explicitly for the arm target.
2
This includes setting it for the old linux-user nwfpe emulation.
3
For nwfpe, our default doesn't match the real kernel, but we
4
avoid making a behaviour change in this commit.
2
5
3
This commit doesn't add any supported events, but provides the framework
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
for adding them. We store the pm_event structs in a simple array, and
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
provide the mapping from the event numbers to array indexes in the
8
Message-id: 20241202131347.498124-41-peter.maydell@linaro.org
6
supported_event_map array. Because the value of PMCEID[01] depends upon
9
---
7
which events are supported at runtime, generate it dynamically.
10
linux-user/arm/nwfpe/fpa11.c | 5 +++++
11
target/arm/cpu.c | 2 ++
12
2 files changed, 7 insertions(+)
8
13
9
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
14
diff --git a/linux-user/arm/nwfpe/fpa11.c b/linux-user/arm/nwfpe/fpa11.c
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20181211151945.29137-10-aaron@os.amperecomputing.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/cpu.h | 10 ++++++++
15
target/arm/cpu.c | 19 +++++++++------
16
target/arm/cpu64.c | 4 ----
17
target/arm/helper.c | 57 +++++++++++++++++++++++++++++++++++++++++++++
18
4 files changed, 79 insertions(+), 11 deletions(-)
19
20
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
21
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
22
--- a/target/arm/cpu.h
16
--- a/linux-user/arm/nwfpe/fpa11.c
23
+++ b/target/arm/cpu.h
17
+++ b/linux-user/arm/nwfpe/fpa11.c
24
@@ -XXX,XX +XXX,XX @@ void pmu_op_finish(CPUARMState *env);
18
@@ -XXX,XX +XXX,XX @@ void resetFPA11(void)
25
void pmu_pre_el_change(ARMCPU *cpu, void *ignored);
19
* this late date.
26
void pmu_post_el_change(ARMCPU *cpu, void *ignored);
20
*/
27
21
set_float_2nan_prop_rule(float_2nan_prop_s_ab, &fpa11->fp_status);
28
+/*
22
+ /*
29
+ * get_pmceid
23
+ * Use the same default NaN value as Arm VFP. This doesn't match
30
+ * @env: CPUARMState
24
+ * the Linux kernel's nwfpe emulation, which uses an all-1s value.
31
+ * @which: which PMCEID register to return (0 or 1)
25
+ */
32
+ *
26
+ set_float_default_nan_pattern(0b01000000, &fpa11->fp_status);
33
+ * Return the PMCEID[01]_EL0 register values corresponding to the counters
27
}
34
+ * which are supported given the current configuration
28
35
+ */
29
void SetRoundingMode(const unsigned int opcode)
36
+uint64_t get_pmceid(CPUARMState *env, unsigned which);
37
+
38
/* SCTLR bit meanings. Several bits have been reused in newer
39
* versions of the architecture; in that case we define constants
40
* for both old and new bit meanings. Code which tests against those
41
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
30
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
42
index XXXXXXX..XXXXXXX 100644
31
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/cpu.c
32
--- a/target/arm/cpu.c
44
+++ b/target/arm/cpu.c
33
+++ b/target/arm/cpu.c
45
@@ -XXX,XX +XXX,XX @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
34
@@ -XXX,XX +XXX,XX @@ void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook,
46
35
* the pseudocode function the arguments are in the order c, a, b.
47
if (!cpu->has_pmu) {
36
* * 0 * Inf + NaN returns the default NaN if the input NaN is quiet,
48
unset_feature(env, ARM_FEATURE_PMU);
37
* and the input NaN if it is signalling
49
+ }
38
+ * * Default NaN has sign bit clear, msb frac bit set
50
+ if (arm_feature(env, ARM_FEATURE_PMU)) {
39
*/
51
+ cpu->pmceid0 = get_pmceid(&cpu->env, 0);
40
static void arm_set_default_fp_behaviours(float_status *s)
52
+ cpu->pmceid1 = get_pmceid(&cpu->env, 1);
41
{
53
+
42
@@ -XXX,XX +XXX,XX @@ static void arm_set_default_fp_behaviours(float_status *s)
54
+ if (!kvm_enabled()) {
43
set_float_2nan_prop_rule(float_2nan_prop_s_ab, s);
55
+ arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0);
44
set_float_3nan_prop_rule(float_3nan_prop_s_cab, s);
56
+ arm_register_el_change_hook(cpu, &pmu_post_el_change, 0);
45
set_float_infzeronan_rule(float_infzeronan_dnan_if_qnan, s);
57
+ }
46
+ set_float_default_nan_pattern(0b01000000, s);
58
+ } else {
59
cpu->id_aa64dfr0 &= ~0xf00;
60
- } else if (!kvm_enabled()) {
61
- arm_register_pre_el_change_hook(cpu, &pmu_pre_el_change, 0);
62
- arm_register_el_change_hook(cpu, &pmu_post_el_change, 0);
63
+ cpu->pmceid0 = 0;
64
+ cpu->pmceid1 = 0;
65
}
66
67
if (!arm_feature(env, ARM_FEATURE_EL2)) {
68
@@ -XXX,XX +XXX,XX @@ static void cortex_a7_initfn(Object *obj)
69
cpu->id_pfr0 = 0x00001131;
70
cpu->id_pfr1 = 0x00011011;
71
cpu->id_dfr0 = 0x02010555;
72
- cpu->pmceid0 = 0x00000000;
73
- cpu->pmceid1 = 0x00000000;
74
cpu->id_afr0 = 0x00000000;
75
cpu->id_mmfr0 = 0x10101105;
76
cpu->id_mmfr1 = 0x40000000;
77
@@ -XXX,XX +XXX,XX @@ static void cortex_a15_initfn(Object *obj)
78
cpu->id_pfr0 = 0x00001131;
79
cpu->id_pfr1 = 0x00011011;
80
cpu->id_dfr0 = 0x02010555;
81
- cpu->pmceid0 = 0x0000000;
82
- cpu->pmceid1 = 0x00000000;
83
cpu->id_afr0 = 0x00000000;
84
cpu->id_mmfr0 = 0x10201105;
85
cpu->id_mmfr1 = 0x20000000;
86
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
87
index XXXXXXX..XXXXXXX 100644
88
--- a/target/arm/cpu64.c
89
+++ b/target/arm/cpu64.c
90
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
91
cpu->isar.id_isar6 = 0;
92
cpu->isar.id_aa64pfr0 = 0x00002222;
93
cpu->id_aa64dfr0 = 0x10305106;
94
- cpu->pmceid0 = 0x00000000;
95
- cpu->pmceid1 = 0x00000000;
96
cpu->isar.id_aa64isar0 = 0x00011120;
97
cpu->isar.id_aa64mmfr0 = 0x00001124;
98
cpu->dbgdidr = 0x3516d000;
99
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
100
cpu->isar.id_isar5 = 0x00011121;
101
cpu->isar.id_aa64pfr0 = 0x00002222;
102
cpu->id_aa64dfr0 = 0x10305106;
103
- cpu->pmceid0 = 0x00000000;
104
- cpu->pmceid1 = 0x00000000;
105
cpu->isar.id_aa64isar0 = 0x00011120;
106
cpu->isar.id_aa64mmfr0 = 0x00001124;
107
cpu->dbgdidr = 0x3516d000;
108
diff --git a/target/arm/helper.c b/target/arm/helper.c
109
index XXXXXXX..XXXXXXX 100644
110
--- a/target/arm/helper.c
111
+++ b/target/arm/helper.c
112
@@ -XXX,XX +XXX,XX @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)
113
return (1 << 31) | ((1 << pmu_num_counters(env)) - 1);
114
}
47
}
115
48
116
+typedef struct pm_event {
49
static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
117
+ uint16_t number; /* PMEVTYPER.evtCount is 16 bits wide */
118
+ /* If the event is supported on this CPU (used to generate PMCEID[01]) */
119
+ bool (*supported)(CPUARMState *);
120
+ /*
121
+ * Retrieve the current count of the underlying event. The programmed
122
+ * counters hold a difference from the return value from this function
123
+ */
124
+ uint64_t (*get_count)(CPUARMState *);
125
+} pm_event;
126
+
127
+static const pm_event pm_events[] = {
128
+};
129
+
130
+/*
131
+ * Note: Before increasing MAX_EVENT_ID beyond 0x3f into the 0x40xx range of
132
+ * events (i.e. the statistical profiling extension), this implementation
133
+ * should first be updated to something sparse instead of the current
134
+ * supported_event_map[] array.
135
+ */
136
+#define MAX_EVENT_ID 0x0
137
+#define UNSUPPORTED_EVENT UINT16_MAX
138
+static uint16_t supported_event_map[MAX_EVENT_ID + 1];
139
+
140
+/*
141
+ * Called upon initialization to build PMCEID0_EL0 or PMCEID1_EL0 (indicated by
142
+ * 'which'). We also use it to build a map of ARM event numbers to indices in
143
+ * our pm_events array.
144
+ *
145
+ * Note: Events in the 0x40XX range are not currently supported.
146
+ */
147
+uint64_t get_pmceid(CPUARMState *env, unsigned which)
148
+{
149
+ uint64_t pmceid = 0;
150
+ unsigned int i;
151
+
152
+ assert(which <= 1);
153
+
154
+ for (i = 0; i < ARRAY_SIZE(supported_event_map); i++) {
155
+ supported_event_map[i] = UNSUPPORTED_EVENT;
156
+ }
157
+
158
+ for (i = 0; i < ARRAY_SIZE(pm_events); i++) {
159
+ const pm_event *cnt = &pm_events[i];
160
+ assert(cnt->number <= MAX_EVENT_ID);
161
+ /* We do not currently support events in the 0x40xx range */
162
+ assert(cnt->number <= 0x3f);
163
+
164
+ if ((cnt->number & 0x20) == (which << 6) &&
165
+ cnt->supported(env)) {
166
+ pmceid |= (1 << (cnt->number & 0x1f));
167
+ supported_event_map[cnt->number] = i;
168
+ }
169
+ }
170
+ return pmceid;
171
+}
172
+
173
static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri,
174
bool isread)
175
{
176
--
50
--
177
2.20.1
51
2.34.1
178
179
diff view generated by jsdifflib
[Qemu-devel] [PULL 24/49] target/arm: Export aa64_va_parameters to internals.h
[PULL 47/72] target/loongarch: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for loongarch.
2
2
3
We need to reuse this from helper-a64.c. Provide a stub
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
definition for CONFIG_USER_ONLY. This matches the stub
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
definitions that we removed for arm_regime_tbi{0,1} before.
5
Message-id: 20241202131347.498124-42-peter.maydell@linaro.org
6
---
7
target/loongarch/tcg/fpu_helper.c | 2 ++
8
1 file changed, 2 insertions(+)
6
9
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
diff --git a/target/loongarch/tcg/fpu_helper.c b/target/loongarch/tcg/fpu_helper.c
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20190108223129.5570-21-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/internals.h | 17 +++++++++++++++++
13
target/arm/helper.c | 4 ++--
14
2 files changed, 19 insertions(+), 2 deletions(-)
15
16
diff --git a/target/arm/internals.h b/target/arm/internals.h
17
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/internals.h
12
--- a/target/loongarch/tcg/fpu_helper.c
19
+++ b/target/arm/internals.h
13
+++ b/target/loongarch/tcg/fpu_helper.c
20
@@ -XXX,XX +XXX,XX @@ typedef struct ARMVAParameters {
14
@@ -XXX,XX +XXX,XX @@ void restore_fp_status(CPULoongArchState *env)
21
bool using64k : 1;
15
*/
22
} ARMVAParameters;
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
23
17
set_float_3nan_prop_rule(float_3nan_prop_s_cab, &env->fp_status);
24
+#ifdef CONFIG_USER_ONLY
18
+ /* Default NaN: sign bit clear, msb frac bit set */
25
+static inline ARMVAParameters aa64_va_parameters(CPUARMState *env,
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
26
+ uint64_t va,
27
+ ARMMMUIdx mmu_idx, bool data)
28
+{
29
+ return (ARMVAParameters) {
30
+ /* 48-bit address space */
31
+ .tsz = 16,
32
+ /* We can't handle tagged addresses properly in user-only mode */
33
+ .tbi = false,
34
+ };
35
+}
36
+#else
37
+ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
38
+ ARMMMUIdx mmu_idx, bool data);
39
+#endif
40
+
41
#endif
42
diff --git a/target/arm/helper.c b/target/arm/helper.c
43
index XXXXXXX..XXXXXXX 100644
44
--- a/target/arm/helper.c
45
+++ b/target/arm/helper.c
46
@@ -XXX,XX +XXX,XX @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs)
47
return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint;
48
}
20
}
49
21
50
-static ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
22
int ieee_ex_to_loongarch(int xcpt)
51
- ARMMMUIdx mmu_idx, bool data)
52
+ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
53
+ ARMMMUIdx mmu_idx, bool data)
54
{
55
uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
56
uint32_t el = regime_el(env, mmu_idx);
57
--
23
--
58
2.20.1
24
2.34.1
59
60
diff view generated by jsdifflib
New patch
[PULL 48/72] target/m68k: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for m68k.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-43-peter.maydell@linaro.org
6
---
7
target/m68k/cpu.c | 2 ++
8
fpu/softfloat-specialize.c.inc | 2 +-
9
2 files changed, 3 insertions(+), 1 deletion(-)
10
11
diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/target/m68k/cpu.c
14
+++ b/target/m68k/cpu.c
15
@@ -XXX,XX +XXX,XX @@ static void m68k_cpu_reset_hold(Object *obj, ResetType type)
16
* preceding paragraph for nonsignaling NaNs.
17
*/
18
set_float_2nan_prop_rule(float_2nan_prop_ab, &env->fp_status);
19
+ /* Default NaN: sign bit clear, all frac bits set */
20
+ set_float_default_nan_pattern(0b01111111, &env->fp_status);
21
22
nan = floatx80_default_nan(&env->fp_status);
23
for (i = 0; i < 8; i++) {
24
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
25
index XXXXXXX..XXXXXXX 100644
26
--- a/fpu/softfloat-specialize.c.inc
27
+++ b/fpu/softfloat-specialize.c.inc
28
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
29
uint8_t dnan_pattern = status->default_nan_pattern;
30
31
if (dnan_pattern == 0) {
32
-#if defined(TARGET_SPARC) || defined(TARGET_M68K)
33
+#if defined(TARGET_SPARC)
34
/* Sign bit clear, all frac bits set */
35
dnan_pattern = 0b01111111;
36
#elif defined(TARGET_HEXAGON)
37
--
38
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/49] target/arm: Add state for the ARMv8.3-PAuth extension
[PULL 49/72] target/mips: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for MIPS. Note that this
2
is our only target which currently changes the default NaN
3
at runtime (which it was previously doing indirectly when it
4
changed the snan_bit_is_one setting).
2
5
3
Add storage space for the 5 encryption keys.
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241202131347.498124-44-peter.maydell@linaro.org
9
---
10
target/mips/fpu_helper.h | 7 +++++++
11
target/mips/msa.c | 3 +++
12
2 files changed, 10 insertions(+)
4
13
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
diff --git a/target/mips/fpu_helper.h b/target/mips/fpu_helper.h
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20190108223129.5570-2-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
target/arm/cpu.h | 30 +++++++++++++++++++++++++++++-
11
1 file changed, 29 insertions(+), 1 deletion(-)
12
13
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/cpu.h
16
--- a/target/mips/fpu_helper.h
16
+++ b/target/arm/cpu.h
17
+++ b/target/mips/fpu_helper.h
17
@@ -XXX,XX +XXX,XX @@ typedef struct ARMVectorReg {
18
@@ -XXX,XX +XXX,XX @@ static inline void restore_snan_bit_mode(CPUMIPSState *env)
18
uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16);
19
set_float_infzeronan_rule(izn_rule, &env->active_fpu.fp_status);
19
} ARMVectorReg;
20
nan3_rule = nan2008 ? float_3nan_prop_s_cab : float_3nan_prop_s_abc;
20
21
set_float_3nan_prop_rule(nan3_rule, &env->active_fpu.fp_status);
21
-/* In AArch32 mode, predicate registers do not exist at all. */
22
+ /*
22
#ifdef TARGET_AARCH64
23
+ * With nan2008, the default NaN value has the sign bit clear and the
23
+/* In AArch32 mode, predicate registers do not exist at all. */
24
+ * frac msb set; with the older mode, the sign bit is clear, and all
24
typedef struct ARMPredicateReg {
25
+ * frac bits except the msb are set.
25
uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16);
26
+ */
26
} ARMPredicateReg;
27
+ set_float_default_nan_pattern(nan2008 ? 0b01000000 : 0b00111111,
27
+
28
+ &env->active_fpu.fp_status);
28
+/* In AArch32 mode, PAC keys do not exist at all. */
29
29
+typedef struct ARMPACKey {
30
+ uint64_t lo, hi;
31
+} ARMPACKey;
32
#endif
33
34
35
@@ -XXX,XX +XXX,XX @@ typedef struct CPUARMState {
36
uint32_t cregs[16];
37
} iwmmxt;
38
39
+#ifdef TARGET_AARCH64
40
+ ARMPACKey apia_key;
41
+ ARMPACKey apib_key;
42
+ ARMPACKey apda_key;
43
+ ARMPACKey apdb_key;
44
+ ARMPACKey apga_key;
45
+#endif
46
+
47
#if defined(CONFIG_USER_ONLY)
48
/* For usermode syscall translation. */
49
int eabi;
50
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id)
51
return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0;
52
}
30
}
53
31
54
+static inline bool isar_feature_aa64_pauth(const ARMISARegisters *id)
32
diff --git a/target/mips/msa.c b/target/mips/msa.c
55
+{
33
index XXXXXXX..XXXXXXX 100644
56
+ /*
34
--- a/target/mips/msa.c
57
+ * Note that while QEMU will only implement the architected algorithm
35
+++ b/target/mips/msa.c
58
+ * QARMA, and thus APA+GPA, the host cpu for kvm may use implementation
36
@@ -XXX,XX +XXX,XX @@ void msa_reset(CPUMIPSState *env)
59
+ * defined algorithms, and thus API+GPI, and this predicate controls
37
/* Inf * 0 + NaN returns the input NaN */
60
+ * migration of the 128-bit keys.
38
set_float_infzeronan_rule(float_infzeronan_dnan_never,
61
+ */
39
&env->active_tc.msa_fp_status);
62
+ return (id->id_aa64isar1 &
40
+ /* Default NaN: sign bit clear, frac msb set */
63
+ (FIELD_DP64(0, ID_AA64ISAR1, APA, -1) |
41
+ set_float_default_nan_pattern(0b01000000,
64
+ FIELD_DP64(0, ID_AA64ISAR1, API, -1) |
42
+ &env->active_tc.msa_fp_status);
65
+ FIELD_DP64(0, ID_AA64ISAR1, GPA, -1) |
43
}
66
+ FIELD_DP64(0, ID_AA64ISAR1, GPI, -1))) != 0;
67
+}
68
+
69
static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id)
70
{
71
/* We always set the AdvSIMD and FP fields identically wrt FP16. */
72
--
44
--
73
2.20.1
45
2.34.1
74
75
diff view generated by jsdifflib
New patch
[PULL 50/72] target/openrisc: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for openrisc.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-45-peter.maydell@linaro.org
6
---
7
target/openrisc/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/openrisc/cpu.c
13
+++ b/target/openrisc/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void openrisc_cpu_reset_hold(Object *obj, ResetType type)
15
*/
16
set_float_2nan_prop_rule(float_2nan_prop_x87, &cpu->env.fp_status);
17
18
+ /* Default NaN: sign bit clear, frac msb set */
19
+ set_float_default_nan_pattern(0b01000000, &cpu->env.fp_status);
20
21
#ifndef CONFIG_USER_ONLY
22
cpu->env.picmr = 0x00000000;
23
--
24
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 33/49] target/arm: Enable PAuth for -cpu max
[PULL 51/72] target/ppc: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for ppc.
2
2
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20190108223129.5570-30-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-46-peter.maydell@linaro.org
7
---
6
---
8
target/arm/cpu64.c | 4 ++++
7
target/ppc/cpu_init.c | 4 ++++
9
1 file changed, 4 insertions(+)
8
1 file changed, 4 insertions(+)
10
9
11
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
10
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
12
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/cpu64.c
12
--- a/target/ppc/cpu_init.c
14
+++ b/target/arm/cpu64.c
13
+++ b/target/ppc/cpu_init.c
15
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
14
@@ -XXX,XX +XXX,XX @@ static void ppc_cpu_reset_hold(Object *obj, ResetType type)
16
15
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
17
t = cpu->isar.id_aa64isar1;
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->vec_status);
18
t = FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1);
17
19
+ t = FIELD_DP64(t, ID_AA64ISAR1, APA, 1); /* PAuth, architected only */
18
+ /* Default NaN: sign bit clear, set frac msb */
20
+ t = FIELD_DP64(t, ID_AA64ISAR1, API, 0);
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
21
+ t = FIELD_DP64(t, ID_AA64ISAR1, GPA, 1);
20
+ set_float_default_nan_pattern(0b01000000, &env->vec_status);
22
+ t = FIELD_DP64(t, ID_AA64ISAR1, GPI, 0);
21
+
23
cpu->isar.id_aa64isar1 = t;
22
for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
24
23
ppc_spr_t *spr = &env->spr_cb[i];
25
t = cpu->isar.id_aa64pfr0;
24
26
--
25
--
27
2.20.1
26
2.34.1
28
29
diff view generated by jsdifflib
[Qemu-devel] [PULL 21/49] target/arm: Introduce arm_stage1_mmu_idx
[PULL 52/72] target/sh4: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for sh4. Note that sh4
2
is one of the only three targets (the others being HPPA and
3
sometimes MIPS) that has snan_bit_is_one set.
2
4
3
While we could expose stage_1_mmu_idx, the combination is
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
probably going to be more useful.
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-47-peter.maydell@linaro.org
8
---
9
target/sh4/cpu.c | 2 ++
10
1 file changed, 2 insertions(+)
5
11
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20190108223129.5570-18-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/internals.h | 15 +++++++++++++++
12
target/arm/helper.c | 7 +++++++
13
2 files changed, 22 insertions(+)
14
15
diff --git a/target/arm/internals.h b/target/arm/internals.h
16
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/internals.h
14
--- a/target/sh4/cpu.c
18
+++ b/target/arm/internals.h
15
+++ b/target/sh4/cpu.c
19
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_vfiq(ARMCPU *cpu);
16
@@ -XXX,XX +XXX,XX @@ static void superh_cpu_reset_hold(Object *obj, ResetType type)
20
*/
17
set_flush_to_zero(1, &env->fp_status);
21
ARMMMUIdx arm_mmu_idx(CPUARMState *env);
22
23
+/**
24
+ * arm_stage1_mmu_idx:
25
+ * @env: The cpu environment
26
+ *
27
+ * Return the ARMMMUIdx for the stage1 traversal for the current regime.
28
+ */
29
+#ifdef CONFIG_USER_ONLY
30
+static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env)
31
+{
32
+ return ARMMMUIdx_S1NSE0;
33
+}
34
+#else
35
+ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env);
36
+#endif
37
+
38
#endif
18
#endif
39
diff --git a/target/arm/helper.c b/target/arm/helper.c
19
set_default_nan_mode(1, &env->fp_status);
40
index XXXXXXX..XXXXXXX 100644
20
+ /* sign bit clear, set all frac bits other than msb */
41
--- a/target/arm/helper.c
21
+ set_float_default_nan_pattern(0b00111111, &env->fp_status);
42
+++ b/target/arm/helper.c
43
@@ -XXX,XX +XXX,XX @@ int cpu_mmu_index(CPUARMState *env, bool ifetch)
44
return arm_to_core_mmu_idx(arm_mmu_idx(env));
45
}
22
}
46
23
47
+#ifndef CONFIG_USER_ONLY
24
static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
48
+ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env)
49
+{
50
+ return stage_1_mmu_idx(arm_mmu_idx(env));
51
+}
52
+#endif
53
+
54
void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
55
target_ulong *cs_base, uint32_t *pflags)
56
{
57
--
25
--
58
2.20.1
26
2.34.1
59
60
diff view generated by jsdifflib
[Qemu-devel] [PULL 20/49] target/arm: Introduce arm_mmu_idx
[PULL 53/72] target/rx: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for rx.
2
2
3
The pattern
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-48-peter.maydell@linaro.org
6
---
7
target/rx/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
4
9
5
ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
10
diff --git a/target/rx/cpu.c b/target/rx/cpu.c
6
7
is computing the full ARMMMUIdx, stripping off the ARM bits,
8
and then putting them back.
9
10
Avoid the extra two steps with the appropriate helper function.
11
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20190108223129.5570-17-richard.henderson@linaro.org
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
target/arm/cpu.h | 9 ++++++++-
18
target/arm/internals.h | 8 ++++++++
19
target/arm/helper.c | 27 ++++++++++++++++-----------
20
3 files changed, 32 insertions(+), 12 deletions(-)
21
22
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
23
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
24
--- a/target/arm/cpu.h
12
--- a/target/rx/cpu.c
25
+++ b/target/arm/cpu.h
13
+++ b/target/rx/cpu.c
26
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
14
@@ -XXX,XX +XXX,XX @@ static void rx_cpu_reset_hold(Object *obj, ResetType type)
27
/* Return the MMU index for a v7M CPU in the specified security state */
15
* then prefer dest over source", which is float_2nan_prop_s_ab.
28
ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
16
*/
29
17
set_float_2nan_prop_rule(float_2nan_prop_x87, &env->fp_status);
30
-/* Determine the current mmu_idx to use for normal loads/stores */
18
+ /* Default NaN value: sign bit clear, set frac msb */
31
+/**
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
32
+ * cpu_mmu_index:
33
+ * @env: The cpu environment
34
+ * @ifetch: True for code access, false for data access.
35
+ *
36
+ * Return the core mmu index for the current translation regime.
37
+ * This function is used by generic TCG code paths.
38
+ */
39
int cpu_mmu_index(CPUARMState *env, bool ifetch);
40
41
/* Indexes used when registering address spaces with cpu_address_space_init */
42
diff --git a/target/arm/internals.h b/target/arm/internals.h
43
index XXXXXXX..XXXXXXX 100644
44
--- a/target/arm/internals.h
45
+++ b/target/arm/internals.h
46
@@ -XXX,XX +XXX,XX @@ void arm_cpu_update_virq(ARMCPU *cpu);
47
*/
48
void arm_cpu_update_vfiq(ARMCPU *cpu);
49
50
+/**
51
+ * arm_mmu_idx:
52
+ * @env: The cpu environment
53
+ *
54
+ * Return the full ARMMMUIdx for the current translation regime.
55
+ */
56
+ARMMMUIdx arm_mmu_idx(CPUARMState *env);
57
+
58
#endif
59
diff --git a/target/arm/helper.c b/target/arm/helper.c
60
index XXXXXXX..XXXXXXX 100644
61
--- a/target/arm/helper.c
62
+++ b/target/arm/helper.c
63
@@ -XXX,XX +XXX,XX @@ static bool v7m_push_callee_stack(ARMCPU *cpu, uint32_t lr, bool dotailchain,
64
limit = env->v7m.msplim[M_REG_S];
65
}
66
} else {
67
- mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
68
+ mmu_idx = arm_mmu_idx(env);
69
frame_sp_p = &env->regs[13];
70
limit = v7m_sp_limit(env);
71
}
72
@@ -XXX,XX +XXX,XX @@ static bool v7m_push_stack(ARMCPU *cpu)
73
CPUARMState *env = &cpu->env;
74
uint32_t xpsr = xpsr_read(env);
75
uint32_t frameptr = env->regs[13];
76
- ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
77
+ ARMMMUIdx mmu_idx = arm_mmu_idx(env);
78
79
/* Align stack pointer if the guest wants that */
80
if ((frameptr & 4) &&
81
@@ -XXX,XX +XXX,XX @@ hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr,
82
int prot;
83
bool ret;
84
ARMMMUFaultInfo fi = {};
85
- ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
86
+ ARMMMUIdx mmu_idx = arm_mmu_idx(env);
87
88
*attrs = (MemTxAttrs) {};
89
90
@@ -XXX,XX +XXX,XX @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
91
return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
92
}
20
}
93
21
94
-int cpu_mmu_index(CPUARMState *env, bool ifetch)
22
static ObjectClass *rx_cpu_class_by_name(const char *cpu_model)
95
+ARMMMUIdx arm_mmu_idx(CPUARMState *env)
96
{
97
- int el = arm_current_el(env);
98
+ int el;
99
100
if (arm_feature(env, ARM_FEATURE_M)) {
101
- ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);
102
-
103
- return arm_to_core_mmu_idx(mmu_idx);
104
+ return arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);
105
}
106
107
+ el = arm_current_el(env);
108
if (el < 2 && arm_is_secure_below_el3(env)) {
109
- return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el);
110
+ return ARMMMUIdx_S1SE0 + el;
111
+ } else {
112
+ return ARMMMUIdx_S12NSE0 + el;
113
}
114
- return el;
115
+}
116
+
117
+int cpu_mmu_index(CPUARMState *env, bool ifetch)
118
+{
119
+ return arm_to_core_mmu_idx(arm_mmu_idx(env));
120
}
121
122
void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
123
target_ulong *cs_base, uint32_t *pflags)
124
{
125
- ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false));
126
+ ARMMMUIdx mmu_idx = arm_mmu_idx(env);
127
int current_el = arm_current_el(env);
128
int fp_el = fp_exception_el(env, current_el);
129
uint32_t flags = 0;
130
--
23
--
131
2.20.1
24
2.34.1
132
133
diff view generated by jsdifflib
New patch
[PULL 54/72] target/s390x: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for s390x.
1
2
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-49-peter.maydell@linaro.org
6
---
7
target/s390x/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
9
10
diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c
11
index XXXXXXX..XXXXXXX 100644
12
--- a/target/s390x/cpu.c
13
+++ b/target/s390x/cpu.c
14
@@ -XXX,XX +XXX,XX @@ static void s390_cpu_reset_hold(Object *obj, ResetType type)
15
set_float_3nan_prop_rule(float_3nan_prop_s_abc, &env->fpu_status);
16
set_float_infzeronan_rule(float_infzeronan_dnan_always,
17
&env->fpu_status);
18
+ /* Default NaN value: sign bit clear, frac msb set */
19
+ set_float_default_nan_pattern(0b01000000, &env->fpu_status);
20
/* fall through */
21
case RESET_TYPE_S390_CPU_NORMAL:
22
env->psw.mask &= ~PSW_MASK_RI;
23
--
24
2.34.1
diff view generated by jsdifflib
New patch
[PULL 55/72] target/sparc: Set default NaN pattern explicitly
1
Set the default NaN pattern explicitly for SPARC, and remove
2
the ifdef from parts64_default_nan.
1
3
4
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20241202131347.498124-50-peter.maydell@linaro.org
7
---
8
target/sparc/cpu.c | 2 ++
9
fpu/softfloat-specialize.c.inc | 5 +----
10
2 files changed, 3 insertions(+), 4 deletions(-)
11
12
diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/sparc/cpu.c
15
+++ b/target/sparc/cpu.c
16
@@ -XXX,XX +XXX,XX @@ static void sparc_cpu_realizefn(DeviceState *dev, Error **errp)
17
set_float_3nan_prop_rule(float_3nan_prop_s_cba, &env->fp_status);
18
/* For inf * 0 + NaN, return the input NaN */
19
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
+ /* Default NaN value: sign bit clear, all frac bits set */
21
+ set_float_default_nan_pattern(0b01111111, &env->fp_status);
22
23
cpu_exec_realizefn(cs, &local_err);
24
if (local_err != NULL) {
25
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
26
index XXXXXXX..XXXXXXX 100644
27
--- a/fpu/softfloat-specialize.c.inc
28
+++ b/fpu/softfloat-specialize.c.inc
29
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
30
uint8_t dnan_pattern = status->default_nan_pattern;
31
32
if (dnan_pattern == 0) {
33
-#if defined(TARGET_SPARC)
34
- /* Sign bit clear, all frac bits set */
35
- dnan_pattern = 0b01111111;
36
-#elif defined(TARGET_HEXAGON)
37
+#if defined(TARGET_HEXAGON)
38
/* Sign bit set, all frac bits set. */
39
dnan_pattern = 0b11111111;
40
#else
41
--
42
2.34.1
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/49] target/arm: Add new_pc argument to helper_exception_return
[PULL 56/72] target/xtensa: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for xtensa.
2
2
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20190108223129.5570-12-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-51-peter.maydell@linaro.org
7
---
6
---
8
target/arm/helper-a64.h | 2 +-
7
target/xtensa/cpu.c | 2 ++
9
target/arm/helper-a64.c | 10 +++++-----
8
1 file changed, 2 insertions(+)
10
target/arm/translate-a64.c | 7 ++++++-
11
3 files changed, 12 insertions(+), 7 deletions(-)
12
9
13
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
10
diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c
14
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/helper-a64.h
12
--- a/target/xtensa/cpu.c
16
+++ b/target/arm/helper-a64.h
13
+++ b/target/xtensa/cpu.c
17
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr)
14
@@ -XXX,XX +XXX,XX @@ static void xtensa_cpu_reset_hold(Object *obj, ResetType type)
18
DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr)
15
/* For inf * 0 + NaN, return the input NaN */
19
DEF_HELPER_2(sqrt_f16, f16, f16, ptr)
16
set_float_infzeronan_rule(float_infzeronan_dnan_never, &env->fp_status);
20
17
set_no_signaling_nans(!dfpu, &env->fp_status);
21
-DEF_HELPER_1(exception_return, void, env)
18
+ /* Default NaN value: sign bit clear, set frac msb */
22
+DEF_HELPER_2(exception_return, void, env, i64)
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
23
20
xtensa_use_first_nan(env, !dfpu);
24
DEF_HELPER_FLAGS_3(pacia, TCG_CALL_NO_WG, i64, env, i64, i64)
25
DEF_HELPER_FLAGS_3(pacib, TCG_CALL_NO_WG, i64, env, i64, i64)
26
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
27
index XXXXXXX..XXXXXXX 100644
28
--- a/target/arm/helper-a64.c
29
+++ b/target/arm/helper-a64.c
30
@@ -XXX,XX +XXX,XX @@ static int el_from_spsr(uint32_t spsr)
31
}
32
}
21
}
33
22
34
-void HELPER(exception_return)(CPUARMState *env)
35
+void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
36
{
37
int cur_el = arm_current_el(env);
38
unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el);
39
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env)
40
aarch64_sync_64_to_32(env);
41
42
if (spsr & CPSR_T) {
43
- env->regs[15] = env->elr_el[cur_el] & ~0x1;
44
+ env->regs[15] = new_pc & ~0x1;
45
} else {
46
- env->regs[15] = env->elr_el[cur_el] & ~0x3;
47
+ env->regs[15] = new_pc & ~0x3;
48
}
49
qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to "
50
"AArch32 EL%d PC 0x%" PRIx32 "\n",
51
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env)
52
env->pstate &= ~PSTATE_SS;
53
}
54
aarch64_restore_sp(env, new_el);
55
- env->pc = env->elr_el[cur_el];
56
+ env->pc = new_pc;
57
qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to "
58
"AArch64 EL%d PC 0x%" PRIx64 "\n",
59
cur_el, new_el, env->pc);
60
@@ -XXX,XX +XXX,XX @@ illegal_return:
61
* no change to exception level, execution state or stack pointer
62
*/
63
env->pstate |= PSTATE_IL;
64
- env->pc = env->elr_el[cur_el];
65
+ env->pc = new_pc;
66
spsr &= PSTATE_NZCV | PSTATE_DAIF;
67
spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF);
68
pstate_write(env, spsr);
69
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
70
index XXXXXXX..XXXXXXX 100644
71
--- a/target/arm/translate-a64.c
72
+++ b/target/arm/translate-a64.c
73
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
74
static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
75
{
76
unsigned int opc, op2, op3, rn, op4;
77
+ TCGv_i64 dst;
78
79
opc = extract32(insn, 21, 4);
80
op2 = extract32(insn, 16, 5);
81
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
82
if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
83
gen_io_start();
84
}
85
- gen_helper_exception_return(cpu_env);
86
+ dst = tcg_temp_new_i64();
87
+ tcg_gen_ld_i64(dst, cpu_env,
88
+ offsetof(CPUARMState, elr_el[s->current_el]));
89
+ gen_helper_exception_return(cpu_env, dst);
90
+ tcg_temp_free_i64(dst);
91
if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
92
gen_io_end();
93
}
94
--
23
--
95
2.20.1
24
2.34.1
96
97
diff view generated by jsdifflib
[Qemu-devel] [PULL 46/49] target/arm: PMU: Add instruction and cycle events
[PULL 57/72] target/hexagon: Set default NaN pattern explicitly
1
From: Aaron Lindsay <aaron@os.amperecomputing.com>
1
Set the default NaN pattern explicitly for hexagon.
2
Remove the ifdef from parts64_default_nan(); the only
3
remaining unconverted targets all use the default case.
2
4
3
The instruction event is only enabled when icount is used, cycles are
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
always supported. Always defining get_cycle_count (but altering its
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
behavior depending on CONFIG_USER_ONLY) allows us to remove some
7
Message-id: 20241202131347.498124-52-peter.maydell@linaro.org
6
CONFIG_USER_ONLY #defines throughout the rest of the code.
8
---
9
target/hexagon/cpu.c | 2 ++
10
fpu/softfloat-specialize.c.inc | 5 -----
11
2 files changed, 2 insertions(+), 5 deletions(-)
7
12
8
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
13
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
9
Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Message-id: 20181211151945.29137-12-aaron@os.amperecomputing.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
target/arm/helper.c | 90 ++++++++++++++++++++++-----------------------
15
1 file changed, 44 insertions(+), 46 deletions(-)
16
17
diff --git a/target/arm/helper.c b/target/arm/helper.c
18
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/helper.c
15
--- a/target/hexagon/cpu.c
20
+++ b/target/arm/helper.c
16
+++ b/target/hexagon/cpu.c
21
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type)
22
#include "arm_ldst.h"
18
23
#include <zlib.h> /* For crc32 */
19
set_default_nan_mode(1, &env->fp_status);
24
#include "exec/semihost.h"
20
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
25
+#include "sysemu/cpus.h"
21
+ /* Default NaN value: sign bit set, all frac bits set */
26
#include "sysemu/kvm.h"
22
+ set_float_default_nan_pattern(0b11111111, &env->fp_status);
27
#include "fpu/softfloat.h"
28
#include "qemu/range.h"
29
@@ -XXX,XX +XXX,XX @@ typedef struct pm_event {
30
uint64_t (*get_count)(CPUARMState *);
31
} pm_event;
32
33
+static bool event_always_supported(CPUARMState *env)
34
+{
35
+ return true;
36
+}
37
+
38
+/*
39
+ * Return the underlying cycle count for the PMU cycle counters. If we're in
40
+ * usermode, simply return 0.
41
+ */
42
+static uint64_t cycles_get_count(CPUARMState *env)
43
+{
44
+#ifndef CONFIG_USER_ONLY
45
+ return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
46
+ ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
47
+#else
48
+ return cpu_get_host_ticks();
49
+#endif
50
+}
51
+
52
+#ifndef CONFIG_USER_ONLY
53
+static bool instructions_supported(CPUARMState *env)
54
+{
55
+ return use_icount == 1 /* Precise instruction counting */;
56
+}
57
+
58
+static uint64_t instructions_get_count(CPUARMState *env)
59
+{
60
+ return (uint64_t)cpu_get_icount_raw();
61
+}
62
+#endif
63
+
64
static const pm_event pm_events[] = {
65
+#ifndef CONFIG_USER_ONLY
66
+ { .number = 0x008, /* INST_RETIRED, Instruction architecturally executed */
67
+ .supported = instructions_supported,
68
+ .get_count = instructions_get_count,
69
+ },
70
+ { .number = 0x011, /* CPU_CYCLES, Cycle */
71
+ .supported = event_always_supported,
72
+ .get_count = cycles_get_count,
73
+ }
74
+#endif
75
};
76
77
/*
78
@@ -XXX,XX +XXX,XX @@ static const pm_event pm_events[] = {
79
* should first be updated to something sparse instead of the current
80
* supported_event_map[] array.
81
*/
82
-#define MAX_EVENT_ID 0x0
83
+#define MAX_EVENT_ID 0x11
84
#define UNSUPPORTED_EVENT UINT16_MAX
85
static uint16_t supported_event_map[MAX_EVENT_ID + 1];
86
87
@@ -XXX,XX +XXX,XX @@ static CPAccessResult pmreg_access_swinc(CPUARMState *env,
88
return pmreg_access(env, ri, isread);
89
}
23
}
90
24
91
-#ifndef CONFIG_USER_ONLY
25
static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info)
92
-
26
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
93
static CPAccessResult pmreg_access_selr(CPUARMState *env,
27
index XXXXXXX..XXXXXXX 100644
94
const ARMCPRegInfo *ri,
28
--- a/fpu/softfloat-specialize.c.inc
95
bool isread)
29
+++ b/fpu/softfloat-specialize.c.inc
96
@@ -XXX,XX +XXX,XX @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
30
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
97
*/
31
uint8_t dnan_pattern = status->default_nan_pattern;
98
void pmccntr_op_start(CPUARMState *env)
32
99
{
33
if (dnan_pattern == 0) {
100
- uint64_t cycles = 0;
34
-#if defined(TARGET_HEXAGON)
101
- cycles = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL),
35
- /* Sign bit set, all frac bits set. */
102
- ARM_CPU_FREQ, NANOSECONDS_PER_SECOND);
36
- dnan_pattern = 0b11111111;
103
+ uint64_t cycles = cycles_get_count(env);
37
-#else
104
38
/*
105
if (pmu_counter_enabled(env, 31)) {
39
* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
106
uint64_t eff_cycles = cycles;
40
* S390, SH4, TriCore, and Xtensa. Our other supported targets
107
@@ -XXX,XX +XXX,XX @@ static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri,
41
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
108
pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value));
42
/* sign bit clear, set frac msb */
109
}
43
dnan_pattern = 0b01000000;
110
111
-#else /* CONFIG_USER_ONLY */
112
-
113
-void pmccntr_op_start(CPUARMState *env)
114
-{
115
-}
116
-
117
-void pmccntr_op_finish(CPUARMState *env)
118
-{
119
-}
120
-
121
-void pmevcntr_op_start(CPUARMState *env, uint8_t i)
122
-{
123
-}
124
-
125
-void pmevcntr_op_finish(CPUARMState *env, uint8_t i)
126
-{
127
-}
128
-
129
-void pmu_op_start(CPUARMState *env)
130
-{
131
-}
132
-
133
-void pmu_op_finish(CPUARMState *env)
134
-{
135
-}
136
-
137
-void pmu_pre_el_change(ARMCPU *cpu, void *ignored)
138
-{
139
-}
140
-
141
-void pmu_post_el_change(ARMCPU *cpu, void *ignored)
142
-{
143
-}
144
-
145
-#endif
146
-
147
static void pmccfiltr_write(CPUARMState *env, const ARMCPRegInfo *ri,
148
uint64_t value)
149
{
150
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
151
/* Unimplemented so WI. */
152
{ .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
153
.access = PL0_W, .accessfn = pmreg_access_swinc, .type = ARM_CP_NOP },
154
-#ifndef CONFIG_USER_ONLY
155
{ .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
156
.access = PL0_RW, .type = ARM_CP_ALIAS,
157
.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmselr),
158
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
159
.fieldoffset = offsetof(CPUARMState, cp15.c15_ccnt),
160
.readfn = pmccntr_read, .writefn = pmccntr_write,
161
.raw_readfn = raw_read, .raw_writefn = raw_write, },
162
-#endif
163
{ .name = "PMCCFILTR", .cp = 15, .opc1 = 0, .crn = 14, .crm = 15, .opc2 = 7,
164
.writefn = pmccfiltr_write_a32, .readfn = pmccfiltr_read_a32,
165
.access = PL0_RW, .accessfn = pmreg_access,
166
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
167
* count register.
168
*/
169
unsigned int i, pmcrn = 0;
170
-#ifndef CONFIG_USER_ONLY
171
ARMCPRegInfo pmcr = {
172
.name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
173
.access = PL0_RW,
174
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
175
g_free(pmevtyper_name);
176
g_free(pmevtyper_el0_name);
177
}
44
}
178
-#endif
45
-#endif
179
ARMCPRegInfo clidr = {
46
}
180
.name = "CLIDR", .state = ARM_CP_STATE_BOTH,
47
assert(dnan_pattern != 0);
181
.opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
48
182
--
49
--
183
2.20.1
50
2.34.1
184
185
diff view generated by jsdifflib
[Qemu-devel] [PULL 47/49] target/arm: PMU: Set PMCR.N to 4
[PULL 58/72] target/riscv: Set default NaN pattern explicitly
1
From: Aaron Lindsay <aaron@os.amperecomputing.com>
1
Set the default NaN pattern explicitly for riscv.
2
2
3
This both advertises that we support four counters and enables them
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
because the pmu_num_counters() reads this value from PMCR.
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-53-peter.maydell@linaro.org
6
---
7
target/riscv/cpu.c | 2 ++
8
1 file changed, 2 insertions(+)
5
9
6
Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org>
10
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
7
Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20181211151945.29137-13-aaron@os.amperecomputing.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
12
target/arm/helper.c | 10 +++++-----
13
1 file changed, 5 insertions(+), 5 deletions(-)
14
15
diff --git a/target/arm/helper.c b/target/arm/helper.c
16
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/helper.c
12
--- a/target/riscv/cpu.c
18
+++ b/target/arm/helper.c
13
+++ b/target/riscv/cpu.c
19
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
14
@@ -XXX,XX +XXX,XX @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
20
.access = PL1_W, .type = ARM_CP_NOP },
15
cs->exception_index = RISCV_EXCP_NONE;
21
/* Performance monitors are implementation defined in v7,
16
env->load_res = -1;
22
* but with an ARM recommended set of registers, which we
17
set_default_nan_mode(1, &env->fp_status);
23
- * follow (although we don't actually implement any counters)
18
+ /* Default NaN value: sign bit clear, frac msb set */
24
+ * follow.
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
25
*
20
env->vill = true;
26
* Performance registers fall into three categories:
21
27
* (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
22
#ifndef CONFIG_USER_ONLY
28
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
29
}
30
if (arm_feature(env, ARM_FEATURE_V7)) {
31
/* v7 performance monitor control register: same implementor
32
- * field as main ID register, and we implement only the cycle
33
- * count register.
34
+ * field as main ID register, and we implement four counters in
35
+ * addition to the cycle count register.
36
*/
37
- unsigned int i, pmcrn = 0;
38
+ unsigned int i, pmcrn = 4;
39
ARMCPRegInfo pmcr = {
40
.name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
41
.access = PL0_RW,
42
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
43
.access = PL0_RW, .accessfn = pmreg_access,
44
.type = ARM_CP_IO,
45
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
46
- .resetvalue = cpu->midr & 0xff000000,
47
+ .resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT),
48
.writefn = pmcr_write, .raw_writefn = raw_write,
49
};
50
define_one_arm_cp_reg(cpu, &pmcr);
51
--
23
--
52
2.20.1
24
2.34.1
53
54
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/49] target/arm: Introduce raise_exception_ra
[PULL 59/72] target/tricore: Set default NaN pattern explicitly
1
From: Richard Henderson <richard.henderson@linaro.org>
1
Set the default NaN pattern explicitly for tricore.
2
2
3
This path uses cpu_loop_exit_restore to unwind current processor state.
3
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
4
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20241202131347.498124-54-peter.maydell@linaro.org
6
---
7
target/tricore/helper.c | 2 ++
8
1 file changed, 2 insertions(+)
4
9
5
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
10
diff --git a/target/tricore/helper.c b/target/tricore/helper.c
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20190108223129.5570-5-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
target/arm/internals.h | 7 +++++++
12
target/arm/op_helper.c | 19 +++++++++++++++++--
13
2 files changed, 24 insertions(+), 2 deletions(-)
14
15
diff --git a/target/arm/internals.h b/target/arm/internals.h
16
index XXXXXXX..XXXXXXX 100644
11
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/internals.h
12
--- a/target/tricore/helper.c
18
+++ b/target/arm/internals.h
13
+++ b/target/tricore/helper.c
19
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-1 prefix */
14
@@ -XXX,XX +XXX,XX @@ void fpu_set_state(CPUTriCoreState *env)
20
void QEMU_NORETURN raise_exception(CPUARMState *env, uint32_t excp,
15
set_flush_to_zero(1, &env->fp_status);
21
uint32_t syndrome, uint32_t target_el);
16
set_float_detect_tininess(float_tininess_before_rounding, &env->fp_status);
22
17
set_default_nan_mode(1, &env->fp_status);
23
+/*
18
+ /* Default NaN pattern: sign bit clear, frac msb set */
24
+ * Similarly, but also use unwinding to restore cpu state.
19
+ set_float_default_nan_pattern(0b01000000, &env->fp_status);
25
+ */
26
+void QEMU_NORETURN raise_exception_ra(CPUARMState *env, uint32_t excp,
27
+ uint32_t syndrome, uint32_t target_el,
28
+ uintptr_t ra);
29
+
30
/*
31
* For AArch64, map a given EL to an index in the banked_spsr array.
32
* Note that this mapping and the AArch32 mapping defined in bank_number()
33
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/op_helper.c
36
+++ b/target/arm/op_helper.c
37
@@ -XXX,XX +XXX,XX @@
38
#define SIGNBIT (uint32_t)0x80000000
39
#define SIGNBIT64 ((uint64_t)1 << 63)
40
41
-void raise_exception(CPUARMState *env, uint32_t excp,
42
- uint32_t syndrome, uint32_t target_el)
43
+static CPUState *do_raise_exception(CPUARMState *env, uint32_t excp,
44
+ uint32_t syndrome, uint32_t target_el)
45
{
46
CPUState *cs = CPU(arm_env_get_cpu(env));
47
48
@@ -XXX,XX +XXX,XX @@ void raise_exception(CPUARMState *env, uint32_t excp,
49
cs->exception_index = excp;
50
env->exception.syndrome = syndrome;
51
env->exception.target_el = target_el;
52
+
53
+ return cs;
54
+}
55
+
56
+void raise_exception(CPUARMState *env, uint32_t excp,
57
+ uint32_t syndrome, uint32_t target_el)
58
+{
59
+ CPUState *cs = do_raise_exception(env, excp, syndrome, target_el);
60
cpu_loop_exit(cs);
61
}
20
}
62
21
63
+void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome,
22
uint32_t psw_read(CPUTriCoreState *env)
64
+ uint32_t target_el, uintptr_t ra)
65
+{
66
+ CPUState *cs = do_raise_exception(env, excp, syndrome, target_el);
67
+ cpu_loop_exit_restore(cs, ra);
68
+}
69
+
70
static int exception_target_el(CPUARMState *env)
71
{
72
int target_el = MAX(1, arm_current_el(env));
73
--
23
--
74
2.20.1
24
2.34.1
75
76
diff view generated by jsdifflib
[Qemu-devel] [PULL 43/49] target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23]
[PULL 60/72] fpu: Remove default handling for dnan_pattern
1
From: Aaron Lindsay <aaron@os.amperecomputing.com>
1
Now that all our targets have bene converted to explicitly specify
2
their pattern for the default NaN value we can remove the remaining
3
fallback code in parts64_default_nan().
2
4
3
Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
4
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
5
Message-id: 20181211151945.29137-9-aaron@os.amperecomputing.com
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20241202131347.498124-55-peter.maydell@linaro.org
7
---
8
---
8
target/arm/cpu.h | 4 ++--
9
fpu/softfloat-specialize.c.inc | 14 --------------
9
target/arm/helper.c | 19 +++++++++++++++++--
10
1 file changed, 14 deletions(-)
10
2 files changed, 19 insertions(+), 4 deletions(-)
11
11
12
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
12
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
13
index XXXXXXX..XXXXXXX 100644
13
index XXXXXXX..XXXXXXX 100644
14
--- a/target/arm/cpu.h
14
--- a/fpu/softfloat-specialize.c.inc
15
+++ b/target/arm/cpu.h
15
+++ b/fpu/softfloat-specialize.c.inc
16
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
16
@@ -XXX,XX +XXX,XX @@ static void parts64_default_nan(FloatParts64 *p, float_status *status)
17
uint32_t id_pfr0;
17
uint64_t frac;
18
uint32_t id_pfr1;
18
uint8_t dnan_pattern = status->default_nan_pattern;
19
uint32_t id_dfr0;
19
20
- uint32_t pmceid0;
20
- if (dnan_pattern == 0) {
21
- uint32_t pmceid1;
21
- /*
22
+ uint64_t pmceid0;
22
- * This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
23
+ uint64_t pmceid1;
23
- * S390, SH4, TriCore, and Xtensa. Our other supported targets
24
uint32_t id_afr0;
24
- * do not have floating-point.
25
uint32_t id_mmfr0;
25
- */
26
uint32_t id_mmfr1;
26
- if (snan_bit_is_one(status)) {
27
diff --git a/target/arm/helper.c b/target/arm/helper.c
27
- /* sign bit clear, set all frac bits other than msb */
28
index XXXXXXX..XXXXXXX 100644
28
- dnan_pattern = 0b00111111;
29
--- a/target/arm/helper.c
29
- } else {
30
+++ b/target/arm/helper.c
30
- /* sign bit clear, set frac msb */
31
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
31
- dnan_pattern = 0b01000000;
32
} else {
32
- }
33
define_arm_cp_regs(cpu, not_v7_cp_reginfo);
33
- }
34
}
34
assert(dnan_pattern != 0);
35
+ if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
35
36
+ FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) != 0xf) {
36
sign = dnan_pattern >> 7;
37
+ ARMCPRegInfo v81_pmu_regs[] = {
38
+ { .name = "PMCEID2", .state = ARM_CP_STATE_AA32,
39
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4,
40
+ .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
41
+ .resetvalue = extract64(cpu->pmceid0, 32, 32) },
42
+ { .name = "PMCEID3", .state = ARM_CP_STATE_AA32,
43
+ .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 5,
44
+ .access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
45
+ .resetvalue = extract64(cpu->pmceid1, 32, 32) },
46
+ REGINFO_SENTINEL
47
+ };
48
+ define_arm_cp_regs(cpu, v81_pmu_regs);
49
+ }
50
if (arm_feature(env, ARM_FEATURE_V8)) {
51
/* AArch64 ID registers, which all have impdef reset values.
52
* Note that within the ID register ranges the unused slots
53
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
54
{ .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
55
.cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,
56
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
57
- .resetvalue = cpu->pmceid0 },
58
+ .resetvalue = extract64(cpu->pmceid0, 0, 32) },
59
{ .name = "PMCEID0_EL0", .state = ARM_CP_STATE_AA64,
60
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 6,
61
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
62
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
63
{ .name = "PMCEID1", .state = ARM_CP_STATE_AA32,
64
.cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 7,
65
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
66
- .resetvalue = cpu->pmceid1 },
67
+ .resetvalue = extract64(cpu->pmceid1, 0, 32) },
68
{ .name = "PMCEID1_EL0", .state = ARM_CP_STATE_AA64,
69
.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 12, .opc2 = 7,
70
.access = PL0_R, .accessfn = pmreg_access, .type = ARM_CP_CONST,
71
--
37
--
72
2.20.1
38
2.34.1
73
74
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/49] target/arm: Move helper_exception_return to helper-a64.c
[PULL 61/72] softfloat: Inline pickNaNMulAdd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This function is only used by AArch64. Code movement only.
3
Inline pickNaNMulAdd into its only caller. This makes
4
one assert redundant with the immediately preceding IF.
4
5
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20190108223129.5570-11-richard.henderson@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20241203203949.483774-3-richard.henderson@linaro.org
9
[PMM: keep comment from old code in new location]
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
11
---
10
target/arm/helper-a64.h | 2 +
12
fpu/softfloat-parts.c.inc | 41 +++++++++++++++++++++++++-
11
target/arm/helper.h | 1 -
13
fpu/softfloat-specialize.c.inc | 54 ----------------------------------
12
target/arm/helper-a64.c | 155 ++++++++++++++++++++++++++++++++++++++++
14
2 files changed, 40 insertions(+), 55 deletions(-)
13
target/arm/op_helper.c | 155 ----------------------------------------
14
4 files changed, 157 insertions(+), 156 deletions(-)
15
15
16
diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h
16
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper-a64.h
18
--- a/fpu/softfloat-parts.c.inc
19
+++ b/target/arm/helper-a64.h
19
+++ b/fpu/softfloat-parts.c.inc
20
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(advsimd_f16tosinth, i32, f16, ptr)
20
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
21
DEF_HELPER_2(advsimd_f16touinth, i32, f16, ptr)
21
}
22
DEF_HELPER_2(sqrt_f16, f16, f16, ptr)
22
23
23
if (s->default_nan_mode) {
24
+DEF_HELPER_1(exception_return, void, env)
24
+ /*
25
+ * We guarantee not to require the target to tell us how to
26
+ * pick a NaN if we're always returning the default NaN.
27
+ * But if we're not in default-NaN mode then the target must
28
+ * specify.
29
+ */
30
which = 3;
31
+ } else if (infzero) {
32
+ /*
33
+ * Inf * 0 + NaN -- some implementations return the
34
+ * default NaN here, and some return the input NaN.
35
+ */
36
+ switch (s->float_infzeronan_rule) {
37
+ case float_infzeronan_dnan_never:
38
+ which = 2;
39
+ break;
40
+ case float_infzeronan_dnan_always:
41
+ which = 3;
42
+ break;
43
+ case float_infzeronan_dnan_if_qnan:
44
+ which = is_qnan(c->cls) ? 3 : 2;
45
+ break;
46
+ default:
47
+ g_assert_not_reached();
48
+ }
49
} else {
50
- which = pickNaNMulAdd(a->cls, b->cls, c->cls, infzero, have_snan, s);
51
+ FloatClass cls[3] = { a->cls, b->cls, c->cls };
52
+ Float3NaNPropRule rule = s->float_3nan_prop_rule;
25
+
53
+
26
DEF_HELPER_FLAGS_3(pacia, TCG_CALL_NO_WG, i64, env, i64, i64)
54
+ assert(rule != float_3nan_prop_none);
27
DEF_HELPER_FLAGS_3(pacib, TCG_CALL_NO_WG, i64, env, i64, i64)
55
+ if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
28
DEF_HELPER_FLAGS_3(pacda, TCG_CALL_NO_WG, i64, env, i64, i64)
56
+ /* We have at least one SNaN input and should prefer it */
29
diff --git a/target/arm/helper.h b/target/arm/helper.h
57
+ do {
58
+ which = rule & R_3NAN_1ST_MASK;
59
+ rule >>= R_3NAN_1ST_LENGTH;
60
+ } while (!is_snan(cls[which]));
61
+ } else {
62
+ do {
63
+ which = rule & R_3NAN_1ST_MASK;
64
+ rule >>= R_3NAN_1ST_LENGTH;
65
+ } while (!is_nan(cls[which]));
66
+ }
67
}
68
69
if (which == 3) {
70
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
30
index XXXXXXX..XXXXXXX 100644
71
index XXXXXXX..XXXXXXX 100644
31
--- a/target/arm/helper.h
72
--- a/fpu/softfloat-specialize.c.inc
32
+++ b/target/arm/helper.h
73
+++ b/fpu/softfloat-specialize.c.inc
33
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_2(get_cp_reg64, i64, env, ptr)
74
@@ -XXX,XX +XXX,XX @@ static int pickNaN(FloatClass a_cls, FloatClass b_cls,
34
35
DEF_HELPER_3(msr_i_pstate, void, env, i32, i32)
36
DEF_HELPER_1(clear_pstate_ss, void, env)
37
-DEF_HELPER_1(exception_return, void, env)
38
39
DEF_HELPER_2(get_r13_banked, i32, env, i32)
40
DEF_HELPER_3(set_r13_banked, void, env, i32, i32)
41
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
42
index XXXXXXX..XXXXXXX 100644
43
--- a/target/arm/helper-a64.c
44
+++ b/target/arm/helper-a64.c
45
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(advsimd_f16touinth)(uint32_t a, void *fpstp)
46
return float16_to_uint16(a, fpst);
47
}
48
49
+static int el_from_spsr(uint32_t spsr)
50
+{
51
+ /* Return the exception level that this SPSR is requesting a return to,
52
+ * or -1 if it is invalid (an illegal return)
53
+ */
54
+ if (spsr & PSTATE_nRW) {
55
+ switch (spsr & CPSR_M) {
56
+ case ARM_CPU_MODE_USR:
57
+ return 0;
58
+ case ARM_CPU_MODE_HYP:
59
+ return 2;
60
+ case ARM_CPU_MODE_FIQ:
61
+ case ARM_CPU_MODE_IRQ:
62
+ case ARM_CPU_MODE_SVC:
63
+ case ARM_CPU_MODE_ABT:
64
+ case ARM_CPU_MODE_UND:
65
+ case ARM_CPU_MODE_SYS:
66
+ return 1;
67
+ case ARM_CPU_MODE_MON:
68
+ /* Returning to Mon from AArch64 is never possible,
69
+ * so this is an illegal return.
70
+ */
71
+ default:
72
+ return -1;
73
+ }
74
+ } else {
75
+ if (extract32(spsr, 1, 1)) {
76
+ /* Return with reserved M[1] bit set */
77
+ return -1;
78
+ }
79
+ if (extract32(spsr, 0, 4) == 1) {
80
+ /* return to EL0 with M[0] bit set */
81
+ return -1;
82
+ }
83
+ return extract32(spsr, 2, 2);
84
+ }
85
+}
86
+
87
+void HELPER(exception_return)(CPUARMState *env)
88
+{
89
+ int cur_el = arm_current_el(env);
90
+ unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el);
91
+ uint32_t spsr = env->banked_spsr[spsr_idx];
92
+ int new_el;
93
+ bool return_to_aa64 = (spsr & PSTATE_nRW) == 0;
94
+
95
+ aarch64_save_sp(env, cur_el);
96
+
97
+ arm_clear_exclusive(env);
98
+
99
+ /* We must squash the PSTATE.SS bit to zero unless both of the
100
+ * following hold:
101
+ * 1. debug exceptions are currently disabled
102
+ * 2. singlestep will be active in the EL we return to
103
+ * We check 1 here and 2 after we've done the pstate/cpsr write() to
104
+ * transition to the EL we're going to.
105
+ */
106
+ if (arm_generate_debug_exceptions(env)) {
107
+ spsr &= ~PSTATE_SS;
108
+ }
109
+
110
+ new_el = el_from_spsr(spsr);
111
+ if (new_el == -1) {
112
+ goto illegal_return;
113
+ }
114
+ if (new_el > cur_el
115
+ || (new_el == 2 && !arm_feature(env, ARM_FEATURE_EL2))) {
116
+ /* Disallow return to an EL which is unimplemented or higher
117
+ * than the current one.
118
+ */
119
+ goto illegal_return;
120
+ }
121
+
122
+ if (new_el != 0 && arm_el_is_aa64(env, new_el) != return_to_aa64) {
123
+ /* Return to an EL which is configured for a different register width */
124
+ goto illegal_return;
125
+ }
126
+
127
+ if (new_el == 2 && arm_is_secure_below_el3(env)) {
128
+ /* Return to the non-existent secure-EL2 */
129
+ goto illegal_return;
130
+ }
131
+
132
+ if (new_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) {
133
+ goto illegal_return;
134
+ }
135
+
136
+ qemu_mutex_lock_iothread();
137
+ arm_call_pre_el_change_hook(arm_env_get_cpu(env));
138
+ qemu_mutex_unlock_iothread();
139
+
140
+ if (!return_to_aa64) {
141
+ env->aarch64 = 0;
142
+ /* We do a raw CPSR write because aarch64_sync_64_to_32()
143
+ * will sort the register banks out for us, and we've already
144
+ * caught all the bad-mode cases in el_from_spsr().
145
+ */
146
+ cpsr_write(env, spsr, ~0, CPSRWriteRaw);
147
+ if (!arm_singlestep_active(env)) {
148
+ env->uncached_cpsr &= ~PSTATE_SS;
149
+ }
150
+ aarch64_sync_64_to_32(env);
151
+
152
+ if (spsr & CPSR_T) {
153
+ env->regs[15] = env->elr_el[cur_el] & ~0x1;
154
+ } else {
155
+ env->regs[15] = env->elr_el[cur_el] & ~0x3;
156
+ }
157
+ qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to "
158
+ "AArch32 EL%d PC 0x%" PRIx32 "\n",
159
+ cur_el, new_el, env->regs[15]);
160
+ } else {
161
+ env->aarch64 = 1;
162
+ pstate_write(env, spsr);
163
+ if (!arm_singlestep_active(env)) {
164
+ env->pstate &= ~PSTATE_SS;
165
+ }
166
+ aarch64_restore_sp(env, new_el);
167
+ env->pc = env->elr_el[cur_el];
168
+ qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to "
169
+ "AArch64 EL%d PC 0x%" PRIx64 "\n",
170
+ cur_el, new_el, env->pc);
171
+ }
172
+ /*
173
+ * Note that cur_el can never be 0. If new_el is 0, then
174
+ * el0_a64 is return_to_aa64, else el0_a64 is ignored.
175
+ */
176
+ aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64);
177
+
178
+ qemu_mutex_lock_iothread();
179
+ arm_call_el_change_hook(arm_env_get_cpu(env));
180
+ qemu_mutex_unlock_iothread();
181
+
182
+ return;
183
+
184
+illegal_return:
185
+ /* Illegal return events of various kinds have architecturally
186
+ * mandated behaviour:
187
+ * restore NZCV and DAIF from SPSR_ELx
188
+ * set PSTATE.IL
189
+ * restore PC from ELR_ELx
190
+ * no change to exception level, execution state or stack pointer
191
+ */
192
+ env->pstate |= PSTATE_IL;
193
+ env->pc = env->elr_el[cur_el];
194
+ spsr &= PSTATE_NZCV | PSTATE_DAIF;
195
+ spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF);
196
+ pstate_write(env, spsr);
197
+ if (!arm_singlestep_active(env)) {
198
+ env->pstate &= ~PSTATE_SS;
199
+ }
200
+ qemu_log_mask(LOG_GUEST_ERROR, "Illegal exception return at EL%d: "
201
+ "resuming execution at 0x%" PRIx64 "\n", cur_el, env->pc);
202
+}
203
+
204
/*
205
* Square Root and Reciprocal square root
206
*/
207
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
208
index XXXXXXX..XXXXXXX 100644
209
--- a/target/arm/op_helper.c
210
+++ b/target/arm/op_helper.c
211
@@ -XXX,XX +XXX,XX @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
212
}
75
}
213
}
76
}
214
77
215
-static int el_from_spsr(uint32_t spsr)
78
-/*----------------------------------------------------------------------------
79
-| Select which NaN to propagate for a three-input operation.
80
-| For the moment we assume that no CPU needs the 'larger significand'
81
-| information.
82
-| Return values : 0 : a; 1 : b; 2 : c; 3 : default-NaN
83
-*----------------------------------------------------------------------------*/
84
-static int pickNaNMulAdd(FloatClass a_cls, FloatClass b_cls, FloatClass c_cls,
85
- bool infzero, bool have_snan, float_status *status)
216
-{
86
-{
217
- /* Return the exception level that this SPSR is requesting a return to,
87
- FloatClass cls[3] = { a_cls, b_cls, c_cls };
218
- * or -1 if it is invalid (an illegal return)
88
- Float3NaNPropRule rule = status->float_3nan_prop_rule;
89
- int which;
90
-
91
- /*
92
- * We guarantee not to require the target to tell us how to
93
- * pick a NaN if we're always returning the default NaN.
94
- * But if we're not in default-NaN mode then the target must
95
- * specify.
219
- */
96
- */
220
- if (spsr & PSTATE_nRW) {
97
- assert(!status->default_nan_mode);
221
- switch (spsr & CPSR_M) {
98
-
222
- case ARM_CPU_MODE_USR:
99
- if (infzero) {
223
- return 0;
100
- /*
224
- case ARM_CPU_MODE_HYP:
101
- * Inf * 0 + NaN -- some implementations return the default NaN here,
102
- * and some return the input NaN.
103
- */
104
- switch (status->float_infzeronan_rule) {
105
- case float_infzeronan_dnan_never:
225
- return 2;
106
- return 2;
226
- case ARM_CPU_MODE_FIQ:
107
- case float_infzeronan_dnan_always:
227
- case ARM_CPU_MODE_IRQ:
108
- return 3;
228
- case ARM_CPU_MODE_SVC:
109
- case float_infzeronan_dnan_if_qnan:
229
- case ARM_CPU_MODE_ABT:
110
- return is_qnan(c_cls) ? 3 : 2;
230
- case ARM_CPU_MODE_UND:
231
- case ARM_CPU_MODE_SYS:
232
- return 1;
233
- case ARM_CPU_MODE_MON:
234
- /* Returning to Mon from AArch64 is never possible,
235
- * so this is an illegal return.
236
- */
237
- default:
111
- default:
238
- return -1;
112
- g_assert_not_reached();
239
- }
113
- }
114
- }
115
-
116
- assert(rule != float_3nan_prop_none);
117
- if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
118
- /* We have at least one SNaN input and should prefer it */
119
- do {
120
- which = rule & R_3NAN_1ST_MASK;
121
- rule >>= R_3NAN_1ST_LENGTH;
122
- } while (!is_snan(cls[which]));
240
- } else {
123
- } else {
241
- if (extract32(spsr, 1, 1)) {
124
- do {
242
- /* Return with reserved M[1] bit set */
125
- which = rule & R_3NAN_1ST_MASK;
243
- return -1;
126
- rule >>= R_3NAN_1ST_LENGTH;
244
- }
127
- } while (!is_nan(cls[which]));
245
- if (extract32(spsr, 0, 4) == 1) {
246
- /* return to EL0 with M[0] bit set */
247
- return -1;
248
- }
249
- return extract32(spsr, 2, 2);
250
- }
128
- }
129
- return which;
251
-}
130
-}
252
-
131
-
253
-void HELPER(exception_return)(CPUARMState *env)
132
/*----------------------------------------------------------------------------
254
-{
133
| Returns 1 if the double-precision floating-point value `a' is a quiet
255
- int cur_el = arm_current_el(env);
134
| NaN; otherwise returns 0.
256
- unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el);
257
- uint32_t spsr = env->banked_spsr[spsr_idx];
258
- int new_el;
259
- bool return_to_aa64 = (spsr & PSTATE_nRW) == 0;
260
-
261
- aarch64_save_sp(env, cur_el);
262
-
263
- arm_clear_exclusive(env);
264
-
265
- /* We must squash the PSTATE.SS bit to zero unless both of the
266
- * following hold:
267
- * 1. debug exceptions are currently disabled
268
- * 2. singlestep will be active in the EL we return to
269
- * We check 1 here and 2 after we've done the pstate/cpsr write() to
270
- * transition to the EL we're going to.
271
- */
272
- if (arm_generate_debug_exceptions(env)) {
273
- spsr &= ~PSTATE_SS;
274
- }
275
-
276
- new_el = el_from_spsr(spsr);
277
- if (new_el == -1) {
278
- goto illegal_return;
279
- }
280
- if (new_el > cur_el
281
- || (new_el == 2 && !arm_feature(env, ARM_FEATURE_EL2))) {
282
- /* Disallow return to an EL which is unimplemented or higher
283
- * than the current one.
284
- */
285
- goto illegal_return;
286
- }
287
-
288
- if (new_el != 0 && arm_el_is_aa64(env, new_el) != return_to_aa64) {
289
- /* Return to an EL which is configured for a different register width */
290
- goto illegal_return;
291
- }
292
-
293
- if (new_el == 2 && arm_is_secure_below_el3(env)) {
294
- /* Return to the non-existent secure-EL2 */
295
- goto illegal_return;
296
- }
297
-
298
- if (new_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) {
299
- goto illegal_return;
300
- }
301
-
302
- qemu_mutex_lock_iothread();
303
- arm_call_pre_el_change_hook(arm_env_get_cpu(env));
304
- qemu_mutex_unlock_iothread();
305
-
306
- if (!return_to_aa64) {
307
- env->aarch64 = 0;
308
- /* We do a raw CPSR write because aarch64_sync_64_to_32()
309
- * will sort the register banks out for us, and we've already
310
- * caught all the bad-mode cases in el_from_spsr().
311
- */
312
- cpsr_write(env, spsr, ~0, CPSRWriteRaw);
313
- if (!arm_singlestep_active(env)) {
314
- env->uncached_cpsr &= ~PSTATE_SS;
315
- }
316
- aarch64_sync_64_to_32(env);
317
-
318
- if (spsr & CPSR_T) {
319
- env->regs[15] = env->elr_el[cur_el] & ~0x1;
320
- } else {
321
- env->regs[15] = env->elr_el[cur_el] & ~0x3;
322
- }
323
- qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to "
324
- "AArch32 EL%d PC 0x%" PRIx32 "\n",
325
- cur_el, new_el, env->regs[15]);
326
- } else {
327
- env->aarch64 = 1;
328
- pstate_write(env, spsr);
329
- if (!arm_singlestep_active(env)) {
330
- env->pstate &= ~PSTATE_SS;
331
- }
332
- aarch64_restore_sp(env, new_el);
333
- env->pc = env->elr_el[cur_el];
334
- qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to "
335
- "AArch64 EL%d PC 0x%" PRIx64 "\n",
336
- cur_el, new_el, env->pc);
337
- }
338
- /*
339
- * Note that cur_el can never be 0. If new_el is 0, then
340
- * el0_a64 is return_to_aa64, else el0_a64 is ignored.
341
- */
342
- aarch64_sve_change_el(env, cur_el, new_el, return_to_aa64);
343
-
344
- qemu_mutex_lock_iothread();
345
- arm_call_el_change_hook(arm_env_get_cpu(env));
346
- qemu_mutex_unlock_iothread();
347
-
348
- return;
349
-
350
-illegal_return:
351
- /* Illegal return events of various kinds have architecturally
352
- * mandated behaviour:
353
- * restore NZCV and DAIF from SPSR_ELx
354
- * set PSTATE.IL
355
- * restore PC from ELR_ELx
356
- * no change to exception level, execution state or stack pointer
357
- */
358
- env->pstate |= PSTATE_IL;
359
- env->pc = env->elr_el[cur_el];
360
- spsr &= PSTATE_NZCV | PSTATE_DAIF;
361
- spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF);
362
- pstate_write(env, spsr);
363
- if (!arm_singlestep_active(env)) {
364
- env->pstate &= ~PSTATE_SS;
365
- }
366
- qemu_log_mask(LOG_GUEST_ERROR, "Illegal exception return at EL%d: "
367
- "resuming execution at 0x%" PRIx64 "\n", cur_el, env->pc);
368
-}
369
-
370
/* Return true if the linked breakpoint entry lbn passes its checks */
371
static bool linked_bp_matches(ARMCPU *cpu, int lbn)
372
{
373
--
135
--
374
2.20.1
136
2.34.1
375
137
376
138
diff view generated by jsdifflib
[Qemu-devel] [PULL 35/49] target/arm: Tidy TBI handling in gen_a64_set_pc
[PULL 62/72] softfloat: Use goto for default nan case in pick_nan_muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We can perform this with fewer operations.
3
Remove "3" as a special case for which and simply
4
branch to return the desired value.
4
5
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20190108223129.5570-32-richard.henderson@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20241203203949.483774-4-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
---
10
target/arm/translate-a64.c | 62 +++++++++++++-------------------------
11
fpu/softfloat-parts.c.inc | 20 ++++++++++----------
11
1 file changed, 21 insertions(+), 41 deletions(-)
12
1 file changed, 10 insertions(+), 10 deletions(-)
12
13
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
14
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
16
--- a/fpu/softfloat-parts.c.inc
16
+++ b/target/arm/translate-a64.c
17
+++ b/fpu/softfloat-parts.c.inc
17
@@ -XXX,XX +XXX,XX @@ void gen_a64_set_pc_im(uint64_t val)
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
18
/* Load the PC from a generic TCG variable.
19
* But if we're not in default-NaN mode then the target must
19
*
20
* specify.
20
* If address tagging is enabled via the TCR TBI bits, then loading
21
*/
21
- * an address into the PC will clear out any tag in the it:
22
- which = 3;
22
+ * an address into the PC will clear out any tag in it:
23
+ goto default_nan;
23
* + for EL2 and EL3 there is only one TBI bit, and if it is set
24
} else if (infzero) {
24
* then the address is zero-extended, clearing bits [63:56]
25
/*
25
* + for EL0 and EL1, TBI0 controls addresses with bit 55 == 0
26
* Inf * 0 + NaN -- some implementations return the
26
@@ -XXX,XX +XXX,XX @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
27
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
27
int tbi = s->tbii;
28
*/
28
29
switch (s->float_infzeronan_rule) {
29
if (s->current_el <= 1) {
30
case float_infzeronan_dnan_never:
30
- /* Test if NEITHER or BOTH TBI values are set. If so, no need to
31
- which = 2;
31
- * examine bit 55 of address, can just generate code.
32
break;
32
- * If mixed, then test via generated code
33
case float_infzeronan_dnan_always:
33
- */
34
- which = 3;
34
- if (tbi == 3) {
35
- break;
35
- TCGv_i64 tmp_reg = tcg_temp_new_i64();
36
+ goto default_nan;
36
- /* Both bits set, sign extension from bit 55 into [63:56] will
37
case float_infzeronan_dnan_if_qnan:
37
- * cover both cases
38
- which = is_qnan(c->cls) ? 3 : 2;
38
- */
39
+ if (is_qnan(c->cls)) {
39
- tcg_gen_shli_i64(tmp_reg, src, 8);
40
+ goto default_nan;
40
- tcg_gen_sari_i64(cpu_pc, tmp_reg, 8);
41
+ }
41
- tcg_temp_free_i64(tmp_reg);
42
break;
42
- } else if (tbi == 0) {
43
default:
43
- /* Neither bit set, just load it as-is */
44
g_assert_not_reached();
44
- tcg_gen_mov_i64(cpu_pc, src);
45
- } else {
46
- TCGv_i64 tcg_tmpval = tcg_temp_new_i64();
47
- TCGv_i64 tcg_bit55 = tcg_temp_new_i64();
48
- TCGv_i64 tcg_zero = tcg_const_i64(0);
49
+ if (tbi != 0) {
50
+ /* Sign-extend from bit 55. */
51
+ tcg_gen_sextract_i64(cpu_pc, src, 0, 56);
52
53
- tcg_gen_andi_i64(tcg_bit55, src, (1ull << 55));
54
+ if (tbi != 3) {
55
+ TCGv_i64 tcg_zero = tcg_const_i64(0);
56
57
- if (tbi == 1) {
58
- /* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */
59
- tcg_gen_andi_i64(tcg_tmpval, src,
60
- 0x00FFFFFFFFFFFFFFull);
61
- tcg_gen_movcond_i64(TCG_COND_EQ, cpu_pc, tcg_bit55, tcg_zero,
62
- tcg_tmpval, src);
63
- } else {
64
- /* tbi0==0, tbi1==1, so 1-fill upper byte if bit 55 = 1 */
65
- tcg_gen_ori_i64(tcg_tmpval, src,
66
- 0xFF00000000000000ull);
67
- tcg_gen_movcond_i64(TCG_COND_NE, cpu_pc, tcg_bit55, tcg_zero,
68
- tcg_tmpval, src);
69
+ /*
70
+ * The two TBI bits differ.
71
+ * If tbi0, then !tbi1: only use the extension if positive.
72
+ * if !tbi0, then tbi1: only use the extension if negative.
73
+ */
74
+ tcg_gen_movcond_i64(tbi == 1 ? TCG_COND_GE : TCG_COND_LT,
75
+ cpu_pc, cpu_pc, tcg_zero, cpu_pc, src);
76
+ tcg_temp_free_i64(tcg_zero);
77
}
78
- tcg_temp_free_i64(tcg_zero);
79
- tcg_temp_free_i64(tcg_bit55);
80
- tcg_temp_free_i64(tcg_tmpval);
81
+ return;
82
}
45
}
83
- } else { /* EL > 1 */
46
+ which = 2;
84
+ } else {
47
} else {
85
if (tbi != 0) {
48
FloatClass cls[3] = { a->cls, b->cls, c->cls };
86
/* Force tag byte to all zero */
49
Float3NaNPropRule rule = s->float_3nan_prop_rule;
87
- tcg_gen_andi_i64(cpu_pc, src, 0x00FFFFFFFFFFFFFFull);
50
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
88
- } else {
89
- /* Load unmodified address */
90
- tcg_gen_mov_i64(cpu_pc, src);
91
+ tcg_gen_extract_i64(cpu_pc, src, 0, 56);
92
+ return;
93
}
51
}
94
}
52
}
53
54
- if (which == 3) {
55
- parts_default_nan(a, s);
56
- return a;
57
- }
58
-
59
switch (which) {
60
case 0:
61
break;
62
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
63
parts_silence_nan(a, s);
64
}
65
return a;
95
+
66
+
96
+ /* Load unmodified address */
67
+ default_nan:
97
+ tcg_gen_mov_i64(cpu_pc, src);
68
+ parts_default_nan(a, s);
69
+ return a;
98
}
70
}
99
71
100
typedef struct DisasCompare64 {
72
/*
101
--
73
--
102
2.20.1
74
2.34.1
103
75
104
76
diff view generated by jsdifflib
[Qemu-devel] [PULL 22/49] target/arm: Create ARMVAParameters and helpers
[PULL 63/72] softfloat: Remove which from parts_pick_nan_muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Split out functions to extract the virtual address parameters.
3
Assign the pointer return value to 'a' directly,
4
Let the functions choose T0 or T1 address space half, if present.
4
rather than going through an intermediary index.
5
Extract (most of) the control bits that vary between EL or Tx.
6
5
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
9
Message-id: 20190108223129.5570-19-richard.henderson@linaro.org
8
Message-id: 20241203203949.483774-5-richard.henderson@linaro.org
10
[PMM: fixed minor checkpatch comment nits]
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
10
---
13
target/arm/internals.h | 14 +++
11
fpu/softfloat-parts.c.inc | 32 ++++++++++----------------------
14
target/arm/helper.c | 278 ++++++++++++++++++++++-------------------
12
1 file changed, 10 insertions(+), 22 deletions(-)
15
2 files changed, 164 insertions(+), 128 deletions(-)
16
13
17
diff --git a/target/arm/internals.h b/target/arm/internals.h
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
18
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/internals.h
16
--- a/fpu/softfloat-parts.c.inc
20
+++ b/target/arm/internals.h
17
+++ b/fpu/softfloat-parts.c.inc
21
@@ -XXX,XX +XXX,XX @@ static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env)
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
22
ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env);
19
FloatPartsN *c, float_status *s,
23
#endif
20
int ab_mask, int abc_mask)
24
21
{
25
+/*
22
- int which;
26
+ * Parameters of a given virtual address, as extracted from the
23
bool infzero = (ab_mask == float_cmask_infzero);
27
+ * translation control register (TCR) for a given regime.
24
bool have_snan = (abc_mask & float_cmask_snan);
28
+ */
25
+ FloatPartsN *ret;
29
+typedef struct ARMVAParameters {
26
30
+ unsigned tsz : 8;
27
if (unlikely(have_snan)) {
31
+ unsigned select : 1;
28
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
32
+ bool tbi : 1;
29
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
33
+ bool epd : 1;
30
default:
34
+ bool hpd : 1;
31
g_assert_not_reached();
35
+ bool using16k : 1;
32
}
36
+ bool using64k : 1;
33
- which = 2;
37
+} ARMVAParameters;
34
+ ret = c;
38
+
39
#endif
40
diff --git a/target/arm/helper.c b/target/arm/helper.c
41
index XXXXXXX..XXXXXXX 100644
42
--- a/target/arm/helper.c
43
+++ b/target/arm/helper.c
44
@@ -XXX,XX +XXX,XX @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs)
45
return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint;
46
}
47
48
+static ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
49
+ ARMMMUIdx mmu_idx, bool data)
50
+{
51
+ uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
52
+ uint32_t el = regime_el(env, mmu_idx);
53
+ bool tbi, epd, hpd, using16k, using64k;
54
+ int select, tsz;
55
+
56
+ /*
57
+ * Bit 55 is always between the two regions, and is canonical for
58
+ * determining if address tagging is enabled.
59
+ */
60
+ select = extract64(va, 55, 1);
61
+
62
+ if (el > 1) {
63
+ tsz = extract32(tcr, 0, 6);
64
+ using64k = extract32(tcr, 14, 1);
65
+ using16k = extract32(tcr, 15, 1);
66
+ if (mmu_idx == ARMMMUIdx_S2NS) {
67
+ /* VTCR_EL2 */
68
+ tbi = hpd = false;
69
+ } else {
70
+ tbi = extract32(tcr, 20, 1);
71
+ hpd = extract32(tcr, 24, 1);
72
+ }
73
+ epd = false;
74
+ } else if (!select) {
75
+ tsz = extract32(tcr, 0, 6);
76
+ epd = extract32(tcr, 7, 1);
77
+ using64k = extract32(tcr, 14, 1);
78
+ using16k = extract32(tcr, 15, 1);
79
+ tbi = extract64(tcr, 37, 1);
80
+ hpd = extract64(tcr, 41, 1);
81
+ } else {
82
+ int tg = extract32(tcr, 30, 2);
83
+ using16k = tg == 1;
84
+ using64k = tg == 3;
85
+ tsz = extract32(tcr, 16, 6);
86
+ epd = extract32(tcr, 23, 1);
87
+ tbi = extract64(tcr, 38, 1);
88
+ hpd = extract64(tcr, 42, 1);
89
+ }
90
+ tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */
91
+ tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */
92
+
93
+ return (ARMVAParameters) {
94
+ .tsz = tsz,
95
+ .select = select,
96
+ .tbi = tbi,
97
+ .epd = epd,
98
+ .hpd = hpd,
99
+ .using16k = using16k,
100
+ .using64k = using64k,
101
+ };
102
+}
103
+
104
+static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
105
+ ARMMMUIdx mmu_idx)
106
+{
107
+ uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
108
+ uint32_t el = regime_el(env, mmu_idx);
109
+ int select, tsz;
110
+ bool epd, hpd;
111
+
112
+ if (mmu_idx == ARMMMUIdx_S2NS) {
113
+ /* VTCR */
114
+ bool sext = extract32(tcr, 4, 1);
115
+ bool sign = extract32(tcr, 3, 1);
116
+
117
+ /*
118
+ * If the sign-extend bit is not the same as t0sz[3], the result
119
+ * is unpredictable. Flag this as a guest error.
120
+ */
121
+ if (sign != sext) {
122
+ qemu_log_mask(LOG_GUEST_ERROR,
123
+ "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
124
+ }
125
+ tsz = sextract32(tcr, 0, 4) + 8;
126
+ select = 0;
127
+ hpd = false;
128
+ epd = false;
129
+ } else if (el == 2) {
130
+ /* HTCR */
131
+ tsz = extract32(tcr, 0, 3);
132
+ select = 0;
133
+ hpd = extract64(tcr, 24, 1);
134
+ epd = false;
135
+ } else {
136
+ int t0sz = extract32(tcr, 0, 3);
137
+ int t1sz = extract32(tcr, 16, 3);
138
+
139
+ if (t1sz == 0) {
140
+ select = va > (0xffffffffu >> t0sz);
141
+ } else {
142
+ /* Note that we will detect errors later. */
143
+ select = va >= ~(0xffffffffu >> t1sz);
144
+ }
145
+ if (!select) {
146
+ tsz = t0sz;
147
+ epd = extract32(tcr, 7, 1);
148
+ hpd = extract64(tcr, 41, 1);
149
+ } else {
150
+ tsz = t1sz;
151
+ epd = extract32(tcr, 23, 1);
152
+ hpd = extract64(tcr, 42, 1);
153
+ }
154
+ /* For aarch32, hpd0 is not enabled without t2e as well. */
155
+ hpd &= extract32(tcr, 6, 1);
156
+ }
157
+
158
+ return (ARMVAParameters) {
159
+ .tsz = tsz,
160
+ .select = select,
161
+ .epd = epd,
162
+ .hpd = hpd,
163
+ };
164
+}
165
+
166
static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
167
MMUAccessType access_type, ARMMMUIdx mmu_idx,
168
hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
169
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
170
/* Read an LPAE long-descriptor translation table. */
171
ARMFaultType fault_type = ARMFault_Translation;
172
uint32_t level;
173
- uint32_t epd = 0;
174
- int32_t t0sz, t1sz;
175
- uint32_t tg;
176
+ ARMVAParameters param;
177
uint64_t ttbr;
178
- int ttbr_select;
179
hwaddr descaddr, indexmask, indexmask_grainsize;
180
uint32_t tableattrs;
181
- target_ulong page_size;
182
+ target_ulong page_size, top_bits;
183
uint32_t attrs;
184
- int32_t stride = 9;
185
- int32_t addrsize;
186
- int inputsize;
187
- int32_t tbi = 0;
188
+ int32_t stride;
189
+ int addrsize, inputsize;
190
TCR *tcr = regime_tcr(env, mmu_idx);
191
int ap, ns, xn, pxn;
192
uint32_t el = regime_el(env, mmu_idx);
193
- bool ttbr1_valid = true;
194
+ bool ttbr1_valid;
195
uint64_t descaddrmask;
196
bool aarch64 = arm_el_is_aa64(env, el);
197
- bool hpd = false;
198
199
/* TODO:
200
* This code does not handle the different format TCR for VTCR_EL2.
201
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
202
* support for those page table walks.
203
*/
204
if (aarch64) {
205
+ param = aa64_va_parameters(env, address, mmu_idx,
206
+ access_type != MMU_INST_FETCH);
207
level = 0;
208
- addrsize = 64;
209
- if (el > 1) {
210
- if (mmu_idx != ARMMMUIdx_S2NS) {
211
- tbi = extract64(tcr->raw_tcr, 20, 1);
212
- }
213
- } else {
214
- if (extract64(address, 55, 1)) {
215
- tbi = extract64(tcr->raw_tcr, 38, 1);
216
- } else {
217
- tbi = extract64(tcr->raw_tcr, 37, 1);
218
- }
219
- }
220
- tbi *= 8;
221
-
222
/* If we are in 64-bit EL2 or EL3 then there is no TTBR1, so mark it
223
* invalid.
224
*/
225
- if (el > 1) {
226
- ttbr1_valid = false;
227
- }
228
+ ttbr1_valid = (el < 2);
229
+ addrsize = 64 - 8 * param.tbi;
230
+ inputsize = 64 - param.tsz;
231
} else {
35
} else {
232
+ param = aa32_va_parameters(env, address, mmu_idx);
36
- FloatClass cls[3] = { a->cls, b->cls, c->cls };
233
level = 1;
37
+ FloatPartsN *val[3] = { a, b, c };
234
- addrsize = 32;
38
Float3NaNPropRule rule = s->float_3nan_prop_rule;
235
/* There is no TTBR1 for EL2 */
39
236
- if (el == 2) {
40
assert(rule != float_3nan_prop_none);
237
- ttbr1_valid = false;
41
if (have_snan && (rule & R_3NAN_SNAN_MASK)) {
238
- }
42
/* We have at least one SNaN input and should prefer it */
239
+ ttbr1_valid = (el != 2);
43
do {
240
+ addrsize = (mmu_idx == ARMMMUIdx_S2NS ? 40 : 32);
44
- which = rule & R_3NAN_1ST_MASK;
241
+ inputsize = addrsize - param.tsz;
45
+ ret = val[rule & R_3NAN_1ST_MASK];
46
rule >>= R_3NAN_1ST_LENGTH;
47
- } while (!is_snan(cls[which]));
48
+ } while (!is_snan(ret->cls));
49
} else {
50
do {
51
- which = rule & R_3NAN_1ST_MASK;
52
+ ret = val[rule & R_3NAN_1ST_MASK];
53
rule >>= R_3NAN_1ST_LENGTH;
54
- } while (!is_nan(cls[which]));
55
+ } while (!is_nan(ret->cls));
56
}
242
}
57
}
243
58
244
- /* Determine whether this address is in the region controlled by
59
- switch (which) {
245
- * TTBR0 or TTBR1 (or if it is in neither region and should fault).
60
- case 0:
246
- * This is a Non-secure PL0/1 stage 1 translation, so controlled by
61
- break;
247
- * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
62
- case 1:
248
+ /*
63
- a = b;
249
+ * We determined the region when collecting the parameters, but we
64
- break;
250
+ * have not yet validated that the address is valid for the region.
65
- case 2:
251
+ * Extract the top bits and verify that they all match select.
66
- a = c;
252
*/
67
- break;
253
- if (aarch64) {
68
- default:
254
- /* AArch64 translation. */
69
- g_assert_not_reached();
255
- t0sz = extract32(tcr->raw_tcr, 0, 6);
70
+ if (is_snan(ret->cls)) {
256
- t0sz = MIN(t0sz, 39);
71
+ parts_silence_nan(ret, s);
257
- t0sz = MAX(t0sz, 16);
72
}
258
- } else if (mmu_idx != ARMMMUIdx_S2NS) {
73
- if (is_snan(a->cls)) {
259
- /* AArch32 stage 1 translation. */
74
- parts_silence_nan(a, s);
260
- t0sz = extract32(tcr->raw_tcr, 0, 3);
261
- } else {
262
- /* AArch32 stage 2 translation. */
263
- bool sext = extract32(tcr->raw_tcr, 4, 1);
264
- bool sign = extract32(tcr->raw_tcr, 3, 1);
265
- /* Address size is 40-bit for a stage 2 translation,
266
- * and t0sz can be negative (from -8 to 7),
267
- * so we need to adjust it to use the TTBR selecting logic below.
268
- */
269
- addrsize = 40;
270
- t0sz = sextract32(tcr->raw_tcr, 0, 4) + 8;
271
-
272
- /* If the sign-extend bit is not the same as t0sz[3], the result
273
- * is unpredictable. Flag this as a guest error. */
274
- if (sign != sext) {
275
- qemu_log_mask(LOG_GUEST_ERROR,
276
- "AArch32: VTCR.S / VTCR.T0SZ[3] mismatch\n");
277
- }
278
- }
75
- }
279
- t1sz = extract32(tcr->raw_tcr, 16, 6);
76
- return a;
280
- if (aarch64) {
77
+ return ret;
281
- t1sz = MIN(t1sz, 39);
78
282
- t1sz = MAX(t1sz, 16);
79
default_nan:
283
- }
80
parts_default_nan(a, s);
284
- if (t0sz && !extract64(address, addrsize - t0sz, t0sz - tbi)) {
285
- /* there is a ttbr0 region and we are in it (high bits all zero) */
286
- ttbr_select = 0;
287
- } else if (ttbr1_valid && t1sz &&
288
- !extract64(~address, addrsize - t1sz, t1sz - tbi)) {
289
- /* there is a ttbr1 region and we are in it (high bits all one) */
290
- ttbr_select = 1;
291
- } else if (!t0sz) {
292
- /* ttbr0 region is "everything not in the ttbr1 region" */
293
- ttbr_select = 0;
294
- } else if (!t1sz && ttbr1_valid) {
295
- /* ttbr1 region is "everything not in the ttbr0 region" */
296
- ttbr_select = 1;
297
- } else {
298
- /* in the gap between the two regions, this is a Translation fault */
299
+ top_bits = sextract64(address, inputsize, addrsize - inputsize);
300
+ if (-top_bits != param.select || (param.select && !ttbr1_valid)) {
301
+ /* In the gap between the two regions, this is a Translation fault */
302
fault_type = ARMFault_Translation;
303
goto do_fault;
304
}
305
306
+ if (param.using64k) {
307
+ stride = 13;
308
+ } else if (param.using16k) {
309
+ stride = 11;
310
+ } else {
311
+ stride = 9;
312
+ }
313
+
314
/* Note that QEMU ignores shareability and cacheability attributes,
315
* so we don't need to do anything with the SH, ORGN, IRGN fields
316
* in the TTBCR. Similarly, TTBCR:A1 selects whether we get the
317
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
318
* implement any ASID-like capability so we can ignore it (instead
319
* we will always flush the TLB any time the ASID is changed).
320
*/
321
- if (ttbr_select == 0) {
322
- ttbr = regime_ttbr(env, mmu_idx, 0);
323
- if (el < 2) {
324
- epd = extract32(tcr->raw_tcr, 7, 1);
325
- }
326
- inputsize = addrsize - t0sz;
327
-
328
- tg = extract32(tcr->raw_tcr, 14, 2);
329
- if (tg == 1) { /* 64KB pages */
330
- stride = 13;
331
- }
332
- if (tg == 2) { /* 16KB pages */
333
- stride = 11;
334
- }
335
- if (aarch64 && el > 1) {
336
- hpd = extract64(tcr->raw_tcr, 24, 1);
337
- } else {
338
- hpd = extract64(tcr->raw_tcr, 41, 1);
339
- }
340
- if (!aarch64) {
341
- /* For aarch32, hpd0 is not enabled without t2e as well. */
342
- hpd &= extract64(tcr->raw_tcr, 6, 1);
343
- }
344
- } else {
345
- /* We should only be here if TTBR1 is valid */
346
- assert(ttbr1_valid);
347
-
348
- ttbr = regime_ttbr(env, mmu_idx, 1);
349
- epd = extract32(tcr->raw_tcr, 23, 1);
350
- inputsize = addrsize - t1sz;
351
-
352
- tg = extract32(tcr->raw_tcr, 30, 2);
353
- if (tg == 3) { /* 64KB pages */
354
- stride = 13;
355
- }
356
- if (tg == 1) { /* 16KB pages */
357
- stride = 11;
358
- }
359
- hpd = extract64(tcr->raw_tcr, 42, 1);
360
- if (!aarch64) {
361
- /* For aarch32, hpd1 is not enabled without t2e as well. */
362
- hpd &= extract64(tcr->raw_tcr, 6, 1);
363
- }
364
- }
365
+ ttbr = regime_ttbr(env, mmu_idx, param.select);
366
367
/* Here we should have set up all the parameters for the translation:
368
* inputsize, ttbr, epd, stride, tbi
369
*/
370
371
- if (epd) {
372
+ if (param.epd) {
373
/* Translation table walk disabled => Translation fault on TLB miss
374
* Note: This is always 0 on 64-bit EL2 and EL3.
375
*/
376
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
377
}
378
/* Merge in attributes from table descriptors */
379
attrs |= nstable << 3; /* NS */
380
- if (hpd) {
381
+ if (param.hpd) {
382
/* HPD disables all the table attributes except NSTable. */
383
break;
384
}
385
--
81
--
386
2.20.1
82
2.34.1
387
83
388
84
diff view generated by jsdifflib
[Qemu-devel] [PULL 25/49] target/arm: Add aa64_va_parameters_both
[PULL 64/72] softfloat: Pad array size in pick_nan_muladd
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We will want to check TBI for I and D simultaneously.
3
While all indices into val[] should be in [0-2], the mask
4
applied is two bits. To help static analysis see there is
5
no possibility of read beyond the end of the array, pad the
6
array to 4 entries, with the final being (implicitly) NULL.
4
7
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
7
Message-id: 20190108223129.5570-22-richard.henderson@linaro.org
10
Message-id: 20241203203949.483774-6-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
12
---
10
target/arm/internals.h | 15 ++++++++++++---
13
fpu/softfloat-parts.c.inc | 2 +-
11
target/arm/helper.c | 10 ++++++++--
14
1 file changed, 1 insertion(+), 1 deletion(-)
12
2 files changed, 20 insertions(+), 5 deletions(-)
13
15
14
diff --git a/target/arm/internals.h b/target/arm/internals.h
16
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
15
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/internals.h
18
--- a/fpu/softfloat-parts.c.inc
17
+++ b/target/arm/internals.h
19
+++ b/fpu/softfloat-parts.c.inc
18
@@ -XXX,XX +XXX,XX @@ typedef struct ARMVAParameters {
20
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
19
} ARMVAParameters;
21
}
20
22
ret = c;
21
#ifdef CONFIG_USER_ONLY
23
} else {
22
-static inline ARMVAParameters aa64_va_parameters(CPUARMState *env,
24
- FloatPartsN *val[3] = { a, b, c };
23
- uint64_t va,
25
+ FloatPartsN *val[R_3NAN_1ST_MASK + 1] = { a, b, c };
24
- ARMMMUIdx mmu_idx, bool data)
26
Float3NaNPropRule rule = s->float_3nan_prop_rule;
25
+static inline ARMVAParameters aa64_va_parameters_both(CPUARMState *env,
27
26
+ uint64_t va,
28
assert(rule != float_3nan_prop_none);
27
+ ARMMMUIdx mmu_idx)
28
{
29
return (ARMVAParameters) {
30
/* 48-bit address space */
31
@@ -XXX,XX +XXX,XX @@ static inline ARMVAParameters aa64_va_parameters(CPUARMState *env,
32
.tbi = false,
33
};
34
}
35
+
36
+static inline ARMVAParameters aa64_va_parameters(CPUARMState *env,
37
+ uint64_t va,
38
+ ARMMMUIdx mmu_idx, bool data)
39
+{
40
+ return aa64_va_parameters_both(env, va, mmu_idx);
41
+}
42
#else
43
+ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va,
44
+ ARMMMUIdx mmu_idx);
45
ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
46
ARMMMUIdx mmu_idx, bool data);
47
#endif
48
diff --git a/target/arm/helper.c b/target/arm/helper.c
49
index XXXXXXX..XXXXXXX 100644
50
--- a/target/arm/helper.c
51
+++ b/target/arm/helper.c
52
@@ -XXX,XX +XXX,XX @@ static uint8_t convert_stage2_attrs(CPUARMState *env, uint8_t s2attrs)
53
return (hiattr << 6) | (hihint << 4) | (loattr << 2) | lohint;
54
}
55
56
-ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
57
- ARMMMUIdx mmu_idx, bool data)
58
+ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va,
59
+ ARMMMUIdx mmu_idx)
60
{
61
uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
62
uint32_t el = regime_el(env, mmu_idx);
63
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
64
};
65
}
66
67
+ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
68
+ ARMMMUIdx mmu_idx, bool data)
69
+{
70
+ return aa64_va_parameters_both(env, va, mmu_idx);
71
+}
72
+
73
static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
74
ARMMMUIdx mmu_idx)
75
{
76
--
29
--
77
2.20.1
30
2.34.1
78
31
79
32
diff view generated by jsdifflib
[Qemu-devel] [PULL 18/49] target/arm: Decode Load/store register (pac)
[PULL 65/72] softfloat: Move propagateFloatx80NaN to softfloat.c
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Not that there are any stores involved, but why argue with ARM's
3
This function is part of the public interface and
4
naming convention.
4
is not "specialized" to any target in any way.
5
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Message-id: 20190108223129.5570-15-richard.henderson@linaro.org
8
Message-id: 20241203203949.483774-7-richard.henderson@linaro.org
9
[fixed trivial comment nit]
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
target/arm/translate-a64.c | 61 ++++++++++++++++++++++++++++++++++++++
11
fpu/softfloat.c | 52 ++++++++++++++++++++++++++++++++++
13
1 file changed, 61 insertions(+)
12
fpu/softfloat-specialize.c.inc | 52 ----------------------------------
13
2 files changed, 52 insertions(+), 52 deletions(-)
14
14
15
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
15
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
16
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/translate-a64.c
17
--- a/fpu/softfloat.c
18
+++ b/target/arm/translate-a64.c
18
+++ b/fpu/softfloat.c
19
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_atomic(DisasContext *s, uint32_t insn,
19
@@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr,
20
s->be_data | size | MO_ALIGN);
20
*zExpPtr = 1 - shiftCount;
21
}
21
}
22
22
23
+/*
23
+/*----------------------------------------------------------------------------
24
+ * PAC memory operations
24
+| Takes two extended double-precision floating-point values `a' and `b', one
25
+ *
25
+| of which is a NaN, and returns the appropriate NaN result. If either `a' or
26
+ * 31 30 27 26 24 22 21 12 11 10 5 0
26
+| `b' is a signaling NaN, the invalid exception is raised.
27
+ * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
27
+*----------------------------------------------------------------------------*/
28
+ * | size | 1 1 1 | V | 0 0 | M S | 1 | imm9 | W | 1 | Rn | Rt |
28
+
29
+ * +------+-------+---+-----+-----+---+--------+---+---+----+-----+
29
+floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
30
+ *
31
+ * Rt: the result register
32
+ * Rn: base address or SP
33
+ * V: vector flag (always 0 as of v8.3)
34
+ * M: clear for key DA, set for key DB
35
+ * W: pre-indexing flag
36
+ * S: sign for imm9.
37
+ */
38
+static void disas_ldst_pac(DisasContext *s, uint32_t insn,
39
+ int size, int rt, bool is_vector)
40
+{
30
+{
41
+ int rn = extract32(insn, 5, 5);
31
+ bool aIsLargerSignificand;
42
+ bool is_wback = extract32(insn, 11, 1);
32
+ FloatClass a_cls, b_cls;
43
+ bool use_key_a = !extract32(insn, 23, 1);
44
+ int offset;
45
+ TCGv_i64 tcg_addr, tcg_rt;
46
+
33
+
47
+ if (size != 3 || is_vector || !dc_isar_feature(aa64_pauth, s)) {
34
+ /* This is not complete, but is good enough for pickNaN. */
48
+ unallocated_encoding(s);
35
+ a_cls = (!floatx80_is_any_nan(a)
49
+ return;
36
+ ? float_class_normal
37
+ : floatx80_is_signaling_nan(a, status)
38
+ ? float_class_snan
39
+ : float_class_qnan);
40
+ b_cls = (!floatx80_is_any_nan(b)
41
+ ? float_class_normal
42
+ : floatx80_is_signaling_nan(b, status)
43
+ ? float_class_snan
44
+ : float_class_qnan);
45
+
46
+ if (is_snan(a_cls) || is_snan(b_cls)) {
47
+ float_raise(float_flag_invalid, status);
50
+ }
48
+ }
51
+
49
+
52
+ if (rn == 31) {
50
+ if (status->default_nan_mode) {
53
+ gen_check_sp_alignment(s);
51
+ return floatx80_default_nan(status);
54
+ }
55
+ tcg_addr = read_cpu_reg_sp(s, rn, 1);
56
+
57
+ if (s->pauth_active) {
58
+ if (use_key_a) {
59
+ gen_helper_autda(tcg_addr, cpu_env, tcg_addr, cpu_X[31]);
60
+ } else {
61
+ gen_helper_autdb(tcg_addr, cpu_env, tcg_addr, cpu_X[31]);
62
+ }
63
+ }
52
+ }
64
+
53
+
65
+ /* Form the 10-bit signed, scaled offset. */
54
+ if (a.low < b.low) {
66
+ offset = (extract32(insn, 22, 1) << 9) | extract32(insn, 12, 9);
55
+ aIsLargerSignificand = 0;
67
+ offset = sextract32(offset << size, 0, 10 + size);
56
+ } else if (b.low < a.low) {
68
+ tcg_gen_addi_i64(tcg_addr, tcg_addr, offset);
57
+ aIsLargerSignificand = 1;
58
+ } else {
59
+ aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
60
+ }
69
+
61
+
70
+ tcg_rt = cpu_reg(s, rt);
62
+ if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
71
+
63
+ if (is_snan(b_cls)) {
72
+ do_gpr_ld(s, tcg_rt, tcg_addr, size, /* is_signed */ false,
64
+ return floatx80_silence_nan(b, status);
73
+ /* extend */ false, /* iss_valid */ !is_wback,
65
+ }
74
+ /* iss_srt */ rt, /* iss_sf */ true, /* iss_ar */ false);
66
+ return b;
75
+
67
+ } else {
76
+ if (is_wback) {
68
+ if (is_snan(a_cls)) {
77
+ tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr);
69
+ return floatx80_silence_nan(a, status);
70
+ }
71
+ return a;
78
+ }
72
+ }
79
+}
73
+}
80
+
74
+
81
/* Load/store register (all forms) */
75
/*----------------------------------------------------------------------------
82
static void disas_ldst_reg(DisasContext *s, uint32_t insn)
76
| Takes an abstract floating-point value having sign `zSign', exponent `zExp',
83
{
77
| and extended significand formed by the concatenation of `zSig0' and `zSig1',
84
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_reg(DisasContext *s, uint32_t insn)
78
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
85
case 2:
79
index XXXXXXX..XXXXXXX 100644
86
disas_ldst_reg_roffset(s, insn, opc, size, rt, is_vector);
80
--- a/fpu/softfloat-specialize.c.inc
87
return;
81
+++ b/fpu/softfloat-specialize.c.inc
88
+ default:
82
@@ -XXX,XX +XXX,XX @@ floatx80 floatx80_silence_nan(floatx80 a, float_status *status)
89
+ disas_ldst_pac(s, insn, size, rt, is_vector);
83
return a;
90
+ return;
84
}
91
}
85
92
break;
86
-/*----------------------------------------------------------------------------
93
case 1:
87
-| Takes two extended double-precision floating-point values `a' and `b', one
88
-| of which is a NaN, and returns the appropriate NaN result. If either `a' or
89
-| `b' is a signaling NaN, the invalid exception is raised.
90
-*----------------------------------------------------------------------------*/
91
-
92
-floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
93
-{
94
- bool aIsLargerSignificand;
95
- FloatClass a_cls, b_cls;
96
-
97
- /* This is not complete, but is good enough for pickNaN. */
98
- a_cls = (!floatx80_is_any_nan(a)
99
- ? float_class_normal
100
- : floatx80_is_signaling_nan(a, status)
101
- ? float_class_snan
102
- : float_class_qnan);
103
- b_cls = (!floatx80_is_any_nan(b)
104
- ? float_class_normal
105
- : floatx80_is_signaling_nan(b, status)
106
- ? float_class_snan
107
- : float_class_qnan);
108
-
109
- if (is_snan(a_cls) || is_snan(b_cls)) {
110
- float_raise(float_flag_invalid, status);
111
- }
112
-
113
- if (status->default_nan_mode) {
114
- return floatx80_default_nan(status);
115
- }
116
-
117
- if (a.low < b.low) {
118
- aIsLargerSignificand = 0;
119
- } else if (b.low < a.low) {
120
- aIsLargerSignificand = 1;
121
- } else {
122
- aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
123
- }
124
-
125
- if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
126
- if (is_snan(b_cls)) {
127
- return floatx80_silence_nan(b, status);
128
- }
129
- return b;
130
- } else {
131
- if (is_snan(a_cls)) {
132
- return floatx80_silence_nan(a, status);
133
- }
134
- return a;
135
- }
136
-}
137
-
138
/*----------------------------------------------------------------------------
139
| Returns 1 if the quadruple-precision floating-point value `a' is a quiet
140
| NaN; otherwise returns 0.
94
--
141
--
95
2.20.1
142
2.34.1
96
97
diff view generated by jsdifflib
[Qemu-devel] [PULL 19/49] target/arm: Move cpu_mmu_index out of line
[PULL 66/72] softfloat: Use parts_pick_nan in propagateFloatx80NaN
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This function is, or will shortly become, too big to inline.
3
Unpacking and repacking the parts may be slightly more work
4
than we did before, but we get to reuse more code. For a
5
code path handling exceptional values, this is an improvement.
4
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20241203203949.483774-8-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
5
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20190108223129.5570-16-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
11
---
10
target/arm/cpu.h | 48 +++++----------------------------------------
12
fpu/softfloat.c | 43 +++++--------------------------------------
11
target/arm/helper.c | 44 +++++++++++++++++++++++++++++++++++++++++
13
1 file changed, 5 insertions(+), 38 deletions(-)
12
2 files changed, 49 insertions(+), 43 deletions(-)
13
14
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/target/arm/cpu.h
17
--- a/fpu/softfloat.c
17
+++ b/target/arm/cpu.h
18
+++ b/fpu/softfloat.c
18
@@ -XXX,XX +XXX,XX @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
19
@@ -XXX,XX +XXX,XX @@ void normalizeFloatx80Subnormal(uint64_t aSig, int32_t *zExpPtr,
19
}
20
20
21
floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b, float_status *status)
21
/* Return the MMU index for a v7M CPU in the specified security and
22
{
22
- * privilege state
23
- bool aIsLargerSignificand;
23
+ * privilege state.
24
- FloatClass a_cls, b_cls;
24
*/
25
+ FloatParts128 pa, pb, *pr;
25
-static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
26
26
- bool secstate,
27
- /* This is not complete, but is good enough for pickNaN. */
27
- bool priv)
28
- a_cls = (!floatx80_is_any_nan(a)
28
-{
29
- ? float_class_normal
29
- ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
30
- : floatx80_is_signaling_nan(a, status)
31
- ? float_class_snan
32
- : float_class_qnan);
33
- b_cls = (!floatx80_is_any_nan(b)
34
- ? float_class_normal
35
- : floatx80_is_signaling_nan(b, status)
36
- ? float_class_snan
37
- : float_class_qnan);
30
-
38
-
31
- if (priv) {
39
- if (is_snan(a_cls) || is_snan(b_cls)) {
32
- mmu_idx |= ARM_MMU_IDX_M_PRIV;
40
- float_raise(float_flag_invalid, status);
33
- }
41
- }
34
-
42
-
35
- if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) {
43
- if (status->default_nan_mode) {
36
- mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
44
+ if (!floatx80_unpack_canonical(&pa, a, status) ||
45
+ !floatx80_unpack_canonical(&pb, b, status)) {
46
return floatx80_default_nan(status);
47
}
48
49
- if (a.low < b.low) {
50
- aIsLargerSignificand = 0;
51
- } else if (b.low < a.low) {
52
- aIsLargerSignificand = 1;
53
- } else {
54
- aIsLargerSignificand = (a.high < b.high) ? 1 : 0;
37
- }
55
- }
38
-
56
-
39
- if (secstate) {
57
- if (pickNaN(a_cls, b_cls, aIsLargerSignificand, status)) {
40
- mmu_idx |= ARM_MMU_IDX_M_S;
58
- if (is_snan(b_cls)) {
59
- return floatx80_silence_nan(b, status);
60
- }
61
- return b;
62
- } else {
63
- if (is_snan(a_cls)) {
64
- return floatx80_silence_nan(a, status);
65
- }
66
- return a;
41
- }
67
- }
42
-
68
+ pr = parts_pick_nan(&pa, &pb, status);
43
- return mmu_idx;
69
+ return floatx80_round_pack_canonical(pr, status);
44
-}
45
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
46
+ bool secstate, bool priv);
47
48
/* Return the MMU index for a v7M CPU in the specified security state */
49
-static inline ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env,
50
- bool secstate)
51
-{
52
- bool priv = arm_current_el(env) != 0;
53
-
54
- return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
55
-}
56
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate);
57
58
/* Determine the current mmu_idx to use for normal loads/stores */
59
-static inline int cpu_mmu_index(CPUARMState *env, bool ifetch)
60
-{
61
- int el = arm_current_el(env);
62
-
63
- if (arm_feature(env, ARM_FEATURE_M)) {
64
- ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);
65
-
66
- return arm_to_core_mmu_idx(mmu_idx);
67
- }
68
-
69
- if (el < 2 && arm_is_secure_below_el3(env)) {
70
- return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el);
71
- }
72
- return el;
73
-}
74
+int cpu_mmu_index(CPUARMState *env, bool ifetch);
75
76
/* Indexes used when registering address spaces with cpu_address_space_init */
77
typedef enum ARMASIdx {
78
diff --git a/target/arm/helper.c b/target/arm/helper.c
79
index XXXXXXX..XXXXXXX 100644
80
--- a/target/arm/helper.c
81
+++ b/target/arm/helper.c
82
@@ -XXX,XX +XXX,XX @@ int fp_exception_el(CPUARMState *env, int cur_el)
83
return 0;
84
}
70
}
85
71
86
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
72
/*----------------------------------------------------------------------------
87
+ bool secstate, bool priv)
88
+{
89
+ ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
90
+
91
+ if (priv) {
92
+ mmu_idx |= ARM_MMU_IDX_M_PRIV;
93
+ }
94
+
95
+ if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) {
96
+ mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
97
+ }
98
+
99
+ if (secstate) {
100
+ mmu_idx |= ARM_MMU_IDX_M_S;
101
+ }
102
+
103
+ return mmu_idx;
104
+}
105
+
106
+/* Return the MMU index for a v7M CPU in the specified security state */
107
+ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
108
+{
109
+ bool priv = arm_current_el(env) != 0;
110
+
111
+ return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);
112
+}
113
+
114
+int cpu_mmu_index(CPUARMState *env, bool ifetch)
115
+{
116
+ int el = arm_current_el(env);
117
+
118
+ if (arm_feature(env, ARM_FEATURE_M)) {
119
+ ARMMMUIdx mmu_idx = arm_v7m_mmu_idx_for_secstate(env, env->v7m.secure);
120
+
121
+ return arm_to_core_mmu_idx(mmu_idx);
122
+ }
123
+
124
+ if (el < 2 && arm_is_secure_below_el3(env)) {
125
+ return arm_to_core_mmu_idx(ARMMMUIdx_S1SE0 + el);
126
+ }
127
+ return el;
128
+}
129
+
130
void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
131
target_ulong *cs_base, uint32_t *pflags)
132
{
133
--
73
--
134
2.20.1
74
2.34.1
135
136
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/49] target/arm: Decode PAuth within system hint space
[PULL 67/72] softfloat: Inline pickNaN
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
3
Inline pickNaN into its only caller. This makes one assert
4
redundant with the immediately preceding IF.
5
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
5
Message-id: 20190108223129.5570-7-richard.henderson@linaro.org
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20241203203949.483774-9-richard.henderson@linaro.org
6
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7
---
10
---
8
target/arm/translate-a64.c | 93 +++++++++++++++++++++++++++++++++-----
11
fpu/softfloat-parts.c.inc | 82 +++++++++++++++++++++++++----
9
1 file changed, 81 insertions(+), 12 deletions(-)
12
fpu/softfloat-specialize.c.inc | 96 ----------------------------------
10
13
2 files changed, 73 insertions(+), 105 deletions(-)
11
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
14
15
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
12
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
13
--- a/target/arm/translate-a64.c
17
--- a/fpu/softfloat-parts.c.inc
14
+++ b/target/arm/translate-a64.c
18
+++ b/fpu/softfloat-parts.c.inc
15
@@ -XXX,XX +XXX,XX @@ static void handle_hint(DisasContext *s, uint32_t insn,
19
@@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s)
20
static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
21
float_status *s)
22
{
23
+ int cmp, which;
24
+
25
if (is_snan(a->cls) || is_snan(b->cls)) {
26
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
16
}
27
}
17
28
18
switch (selector) {
29
if (s->default_nan_mode) {
19
- case 0: /* NOP */
30
parts_default_nan(a, s);
20
- return;
31
- } else {
21
- case 3: /* WFI */
32
- int cmp = frac_cmp(a, b);
22
+ case 0b00000: /* NOP */
33
- if (cmp == 0) {
23
+ break;
34
- cmp = a->sign < b->sign;
24
+ case 0b00011: /* WFI */
35
- }
25
s->base.is_jmp = DISAS_WFI;
36
+ return a;
26
- return;
37
+ }
27
+ break;
38
28
+ case 0b00001: /* YIELD */
39
- if (pickNaN(a->cls, b->cls, cmp > 0, s)) {
29
/* When running in MTTCG we don't generate jumps to the yield and
40
- a = b;
30
* WFE helpers as it won't affect the scheduling of other vCPUs.
41
- }
31
* If we wanted to more completely model WFE/SEV so we don't busy
42
+ cmp = frac_cmp(a, b);
32
* spin unnecessarily we would need to do something more involved.
43
+ if (cmp == 0) {
33
*/
44
+ cmp = a->sign < b->sign;
34
- case 1: /* YIELD */
45
+ }
35
if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
46
+
36
s->base.is_jmp = DISAS_YIELD;
47
+ switch (s->float_2nan_prop_rule) {
48
+ case float_2nan_prop_s_ab:
49
if (is_snan(a->cls)) {
50
- parts_silence_nan(a, s);
51
+ which = 0;
52
+ } else if (is_snan(b->cls)) {
53
+ which = 1;
54
+ } else if (is_qnan(a->cls)) {
55
+ which = 0;
56
+ } else {
57
+ which = 1;
37
}
58
}
38
- return;
59
+ break;
39
- case 2: /* WFE */
60
+ case float_2nan_prop_s_ba:
40
+ break;
61
+ if (is_snan(b->cls)) {
41
+ case 0b00010: /* WFE */
62
+ which = 1;
42
if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
63
+ } else if (is_snan(a->cls)) {
43
s->base.is_jmp = DISAS_WFE;
64
+ which = 0;
44
}
65
+ } else if (is_qnan(b->cls)) {
45
- return;
66
+ which = 1;
46
- case 4: /* SEV */
67
+ } else {
47
- case 5: /* SEVL */
68
+ which = 0;
48
+ break;
49
+ case 0b00100: /* SEV */
50
+ case 0b00101: /* SEVL */
51
/* we treat all as NOP at least for now */
52
- return;
53
+ break;
54
+ case 0b00111: /* XPACLRI */
55
+ if (s->pauth_active) {
56
+ gen_helper_xpaci(cpu_X[30], cpu_env, cpu_X[30]);
57
+ }
69
+ }
58
+ break;
70
+ break;
59
+ case 0b01000: /* PACIA1716 */
71
+ case float_2nan_prop_ab:
60
+ if (s->pauth_active) {
72
+ which = is_nan(a->cls) ? 0 : 1;
61
+ gen_helper_pacia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
73
+ break;
74
+ case float_2nan_prop_ba:
75
+ which = is_nan(b->cls) ? 1 : 0;
76
+ break;
77
+ case float_2nan_prop_x87:
78
+ /*
79
+ * This implements x87 NaN propagation rules:
80
+ * SNaN + QNaN => return the QNaN
81
+ * two SNaNs => return the one with the larger significand, silenced
82
+ * two QNaNs => return the one with the larger significand
83
+ * SNaN and a non-NaN => return the SNaN, silenced
84
+ * QNaN and a non-NaN => return the QNaN
85
+ *
86
+ * If we get down to comparing significands and they are the same,
87
+ * return the NaN with the positive sign bit (if any).
88
+ */
89
+ if (is_snan(a->cls)) {
90
+ if (is_snan(b->cls)) {
91
+ which = cmp > 0 ? 0 : 1;
92
+ } else {
93
+ which = is_qnan(b->cls) ? 1 : 0;
94
+ }
95
+ } else if (is_qnan(a->cls)) {
96
+ if (is_snan(b->cls) || !is_qnan(b->cls)) {
97
+ which = 0;
98
+ } else {
99
+ which = cmp > 0 ? 0 : 1;
100
+ }
101
+ } else {
102
+ which = 1;
62
+ }
103
+ }
63
+ break;
104
+ break;
64
+ case 0b01010: /* PACIB1716 */
105
+ default:
65
+ if (s->pauth_active) {
106
+ g_assert_not_reached();
66
+ gen_helper_pacib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
107
+ }
67
+ }
108
+
68
+ break;
109
+ if (which) {
69
+ case 0b01100: /* AUTIA1716 */
110
+ a = b;
70
+ if (s->pauth_active) {
111
+ }
71
+ gen_helper_autia(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
112
+ if (is_snan(a->cls)) {
72
+ }
113
+ parts_silence_nan(a, s);
73
+ break;
114
}
74
+ case 0b01110: /* AUTIB1716 */
115
return a;
75
+ if (s->pauth_active) {
116
}
76
+ gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]);
117
diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc
77
+ }
118
index XXXXXXX..XXXXXXX 100644
78
+ break;
119
--- a/fpu/softfloat-specialize.c.inc
79
+ case 0b11000: /* PACIAZ */
120
+++ b/fpu/softfloat-specialize.c.inc
80
+ if (s->pauth_active) {
121
@@ -XXX,XX +XXX,XX @@ bool float32_is_signaling_nan(float32 a_, float_status *status)
81
+ gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30],
82
+ new_tmp_a64_zero(s));
83
+ }
84
+ break;
85
+ case 0b11001: /* PACIASP */
86
+ if (s->pauth_active) {
87
+ gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
88
+ }
89
+ break;
90
+ case 0b11010: /* PACIBZ */
91
+ if (s->pauth_active) {
92
+ gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30],
93
+ new_tmp_a64_zero(s));
94
+ }
95
+ break;
96
+ case 0b11011: /* PACIBSP */
97
+ if (s->pauth_active) {
98
+ gen_helper_pacib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
99
+ }
100
+ break;
101
+ case 0b11100: /* AUTIAZ */
102
+ if (s->pauth_active) {
103
+ gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30],
104
+ new_tmp_a64_zero(s));
105
+ }
106
+ break;
107
+ case 0b11101: /* AUTIASP */
108
+ if (s->pauth_active) {
109
+ gen_helper_autia(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
110
+ }
111
+ break;
112
+ case 0b11110: /* AUTIBZ */
113
+ if (s->pauth_active) {
114
+ gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30],
115
+ new_tmp_a64_zero(s));
116
+ }
117
+ break;
118
+ case 0b11111: /* AUTIBSP */
119
+ if (s->pauth_active) {
120
+ gen_helper_autib(cpu_X[30], cpu_env, cpu_X[30], cpu_X[31]);
121
+ }
122
+ break;
123
default:
124
/* default specified as NOP equivalent */
125
- return;
126
+ break;
127
}
122
}
128
}
123
}
129
124
125
-/*----------------------------------------------------------------------------
126
-| Select which NaN to propagate for a two-input operation.
127
-| IEEE754 doesn't specify all the details of this, so the
128
-| algorithm is target-specific.
129
-| The routine is passed various bits of information about the
130
-| two NaNs and should return 0 to select NaN a and 1 for NaN b.
131
-| Note that signalling NaNs are always squashed to quiet NaNs
132
-| by the caller, by calling floatXX_silence_nan() before
133
-| returning them.
134
-|
135
-| aIsLargerSignificand is only valid if both a and b are NaNs
136
-| of some kind, and is true if a has the larger significand,
137
-| or if both a and b have the same significand but a is
138
-| positive but b is negative. It is only needed for the x87
139
-| tie-break rule.
140
-*----------------------------------------------------------------------------*/
141
-
142
-static int pickNaN(FloatClass a_cls, FloatClass b_cls,
143
- bool aIsLargerSignificand, float_status *status)
144
-{
145
- /*
146
- * We guarantee not to require the target to tell us how to
147
- * pick a NaN if we're always returning the default NaN.
148
- * But if we're not in default-NaN mode then the target must
149
- * specify via set_float_2nan_prop_rule().
150
- */
151
- assert(!status->default_nan_mode);
152
-
153
- switch (status->float_2nan_prop_rule) {
154
- case float_2nan_prop_s_ab:
155
- if (is_snan(a_cls)) {
156
- return 0;
157
- } else if (is_snan(b_cls)) {
158
- return 1;
159
- } else if (is_qnan(a_cls)) {
160
- return 0;
161
- } else {
162
- return 1;
163
- }
164
- break;
165
- case float_2nan_prop_s_ba:
166
- if (is_snan(b_cls)) {
167
- return 1;
168
- } else if (is_snan(a_cls)) {
169
- return 0;
170
- } else if (is_qnan(b_cls)) {
171
- return 1;
172
- } else {
173
- return 0;
174
- }
175
- break;
176
- case float_2nan_prop_ab:
177
- if (is_nan(a_cls)) {
178
- return 0;
179
- } else {
180
- return 1;
181
- }
182
- break;
183
- case float_2nan_prop_ba:
184
- if (is_nan(b_cls)) {
185
- return 1;
186
- } else {
187
- return 0;
188
- }
189
- break;
190
- case float_2nan_prop_x87:
191
- /*
192
- * This implements x87 NaN propagation rules:
193
- * SNaN + QNaN => return the QNaN
194
- * two SNaNs => return the one with the larger significand, silenced
195
- * two QNaNs => return the one with the larger significand
196
- * SNaN and a non-NaN => return the SNaN, silenced
197
- * QNaN and a non-NaN => return the QNaN
198
- *
199
- * If we get down to comparing significands and they are the same,
200
- * return the NaN with the positive sign bit (if any).
201
- */
202
- if (is_snan(a_cls)) {
203
- if (is_snan(b_cls)) {
204
- return aIsLargerSignificand ? 0 : 1;
205
- }
206
- return is_qnan(b_cls) ? 1 : 0;
207
- } else if (is_qnan(a_cls)) {
208
- if (is_snan(b_cls) || !is_qnan(b_cls)) {
209
- return 0;
210
- } else {
211
- return aIsLargerSignificand ? 0 : 1;
212
- }
213
- } else {
214
- return 1;
215
- }
216
- default:
217
- g_assert_not_reached();
218
- }
219
-}
220
-
221
/*----------------------------------------------------------------------------
222
| Returns 1 if the double-precision floating-point value `a' is a quiet
223
| NaN; otherwise returns 0.
130
--
224
--
131
2.20.1
225
2.34.1
132
226
133
227
diff view generated by jsdifflib
[Qemu-devel] [PULL 23/49] target/arm: Merge TBFLAG_AA_TB{0, 1} to TBII
[PULL 68/72] softfloat: Share code between parts_pick_nan cases
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
We will shortly want to talk about TBI as it relates to data.
3
Remember if there was an SNaN, and use that to simplify
4
Passing around a pair of variables is less convenient than a
4
float_2nan_prop_s_{ab,ba} to only the snan component.
5
single variable.
5
Then, fall through to the corresponding
6
float_2nan_prop_{ab,ba} case to handle any remaining
7
nans, which must be quiet.
6
8
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Message-id: 20190108223129.5570-20-richard.henderson@linaro.org
11
Message-id: 20241203203949.483774-10-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
13
---
12
target/arm/cpu.h | 3 +--
14
fpu/softfloat-parts.c.inc | 32 ++++++++++++--------------------
13
target/arm/translate.h | 3 +--
15
1 file changed, 12 insertions(+), 20 deletions(-)
14
target/arm/helper.c | 5 ++---
15
target/arm/translate-a64.c | 13 +++++++------
16
4 files changed, 11 insertions(+), 13 deletions(-)
17
16
18
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
17
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
19
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/cpu.h
19
--- a/fpu/softfloat-parts.c.inc
21
+++ b/target/arm/cpu.h
20
+++ b/fpu/softfloat-parts.c.inc
22
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_A32, HANDLER, 21, 1)
21
@@ -XXX,XX +XXX,XX @@ static void partsN(return_nan)(FloatPartsN *a, float_status *s)
23
FIELD(TBFLAG_A32, STACKCHECK, 22, 1)
22
static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
24
23
float_status *s)
25
/* Bit usage when in AArch64 state */
26
-FIELD(TBFLAG_A64, TBI0, 0, 1)
27
-FIELD(TBFLAG_A64, TBI1, 1, 1)
28
+FIELD(TBFLAG_A64, TBII, 0, 2)
29
FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
30
FIELD(TBFLAG_A64, ZCR_LEN, 4, 4)
31
FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
32
diff --git a/target/arm/translate.h b/target/arm/translate.h
33
index XXXXXXX..XXXXXXX 100644
34
--- a/target/arm/translate.h
35
+++ b/target/arm/translate.h
36
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
37
int user;
38
#endif
39
ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
40
- bool tbi0; /* TBI0 for EL0/1 or TBI for EL2/3 */
41
- bool tbi1; /* TBI1 for EL0/1, not used for EL2/3 */
42
+ uint8_t tbii; /* TBI1|TBI0 for EL0/1 or TBI for EL2/3 */
43
bool ns; /* Use non-secure CPREG bank on access */
44
int fp_excp_el; /* FP exception EL or 0 if enabled */
45
int sve_excp_el; /* SVE exception EL or 0 if enabled */
46
diff --git a/target/arm/helper.c b/target/arm/helper.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/helper.c
49
+++ b/target/arm/helper.c
50
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
51
*pc = env->pc;
52
flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1);
53
/* Get control bits for tagged addresses */
54
- flags = FIELD_DP32(flags, TBFLAG_A64, TBI0,
55
+ flags = FIELD_DP32(flags, TBFLAG_A64, TBII,
56
+ (arm_regime_tbi1(env, mmu_idx) << 1) |
57
arm_regime_tbi0(env, mmu_idx));
58
- flags = FIELD_DP32(flags, TBFLAG_A64, TBI1,
59
- arm_regime_tbi1(env, mmu_idx));
60
61
if (cpu_isar_feature(aa64_sve, cpu)) {
62
int sve_el = sve_exception_el(env, current_el);
63
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/target/arm/translate-a64.c
66
+++ b/target/arm/translate-a64.c
67
@@ -XXX,XX +XXX,XX @@ void gen_a64_set_pc_im(uint64_t val)
68
*/
69
static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
70
{
24
{
71
+ /* Note that TBII is TBI1:TBI0. */
25
+ bool have_snan = false;
72
+ int tbi = s->tbii;
26
int cmp, which;
73
27
74
if (s->current_el <= 1) {
28
if (is_snan(a->cls) || is_snan(b->cls)) {
75
/* Test if NEITHER or BOTH TBI values are set. If so, no need to
29
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
76
* examine bit 55 of address, can just generate code.
30
+ have_snan = true;
77
* If mixed, then test via generated code
31
}
78
*/
32
79
- if (s->tbi0 && s->tbi1) {
33
if (s->default_nan_mode) {
80
+ if (tbi == 3) {
34
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
81
TCGv_i64 tmp_reg = tcg_temp_new_i64();
35
82
/* Both bits set, sign extension from bit 55 into [63:56] will
36
switch (s->float_2nan_prop_rule) {
83
* cover both cases
37
case float_2nan_prop_s_ab:
84
@@ -XXX,XX +XXX,XX @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
38
- if (is_snan(a->cls)) {
85
tcg_gen_shli_i64(tmp_reg, src, 8);
39
- which = 0;
86
tcg_gen_sari_i64(cpu_pc, tmp_reg, 8);
40
- } else if (is_snan(b->cls)) {
87
tcg_temp_free_i64(tmp_reg);
41
- which = 1;
88
- } else if (!s->tbi0 && !s->tbi1) {
42
- } else if (is_qnan(a->cls)) {
89
+ } else if (tbi == 0) {
43
- which = 0;
90
/* Neither bit set, just load it as-is */
44
- } else {
91
tcg_gen_mov_i64(cpu_pc, src);
45
- which = 1;
92
} else {
46
+ if (have_snan) {
93
@@ -XXX,XX +XXX,XX @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
47
+ which = is_snan(a->cls) ? 0 : 1;
94
48
+ break;
95
tcg_gen_andi_i64(tcg_bit55, src, (1ull << 55));
96
97
- if (s->tbi0) {
98
+ if (tbi == 1) {
99
/* tbi0==1, tbi1==0, so 0-fill upper byte if bit 55 = 0 */
100
tcg_gen_andi_i64(tcg_tmpval, src,
101
0x00FFFFFFFFFFFFFFull);
102
@@ -XXX,XX +XXX,XX @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 src)
103
tcg_temp_free_i64(tcg_tmpval);
104
}
49
}
105
} else { /* EL > 1 */
50
- break;
106
- if (s->tbi0) {
51
- case float_2nan_prop_s_ba:
107
+ if (tbi != 0) {
52
- if (is_snan(b->cls)) {
108
/* Force tag byte to all zero */
53
- which = 1;
109
tcg_gen_andi_i64(cpu_pc, src, 0x00FFFFFFFFFFFFFFull);
54
- } else if (is_snan(a->cls)) {
110
} else {
55
- which = 0;
111
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
56
- } else if (is_qnan(b->cls)) {
112
dc->condexec_cond = 0;
57
- which = 1;
113
core_mmu_idx = FIELD_EX32(tb_flags, TBFLAG_ANY, MMUIDX);
58
- } else {
114
dc->mmu_idx = core_to_arm_mmu_idx(env, core_mmu_idx);
59
- which = 0;
115
- dc->tbi0 = FIELD_EX32(tb_flags, TBFLAG_A64, TBI0);
60
- }
116
- dc->tbi1 = FIELD_EX32(tb_flags, TBFLAG_A64, TBI1);
61
- break;
117
+ dc->tbii = FIELD_EX32(tb_flags, TBFLAG_A64, TBII);
62
+ /* fall through */
118
dc->current_el = arm_mmu_idx_to_el(dc->mmu_idx);
63
case float_2nan_prop_ab:
119
#if !defined(CONFIG_USER_ONLY)
64
which = is_nan(a->cls) ? 0 : 1;
120
dc->user = (dc->current_el == 0);
65
break;
66
+ case float_2nan_prop_s_ba:
67
+ if (have_snan) {
68
+ which = is_snan(b->cls) ? 1 : 0;
69
+ break;
70
+ }
71
+ /* fall through */
72
case float_2nan_prop_ba:
73
which = is_nan(b->cls) ? 1 : 0;
74
break;
121
--
75
--
122
2.20.1
76
2.34.1
123
124
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/49] target/arm: Rearrange decode in disas_uncond_b_reg
[PULL 69/72] softfloat: Sink frac_cmp in parts_pick_nan until needed
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
This will enable PAuth decode in a subsequent patch.
3
Move the fractional comparison to the end of the
4
float_2nan_prop_x87 case. This is not required for
5
any other 2nan propagation rule. Reorganize the
6
x87 case itself to break out of the switch when the
7
fractional comparison is not required.
4
8
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Message-id: 20190108223129.5570-13-richard.henderson@linaro.org
11
Message-id: 20241203203949.483774-11-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
13
---
10
target/arm/translate-a64.c | 47 +++++++++++++++++++++++++++++---------
14
fpu/softfloat-parts.c.inc | 19 +++++++++----------
11
1 file changed, 36 insertions(+), 11 deletions(-)
15
1 file changed, 9 insertions(+), 10 deletions(-)
12
16
13
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
17
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
14
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/translate-a64.c
19
--- a/fpu/softfloat-parts.c.inc
16
+++ b/target/arm/translate-a64.c
20
+++ b/fpu/softfloat-parts.c.inc
17
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
21
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
18
rn = extract32(insn, 5, 5);
22
return a;
19
op4 = extract32(insn, 0, 5);
20
21
- if (op4 != 0x0 || op3 != 0x0 || op2 != 0x1f) {
22
- unallocated_encoding(s);
23
- return;
24
+ if (op2 != 0x1f) {
25
+ goto do_unallocated;
26
}
23
}
27
24
28
switch (opc) {
25
- cmp = frac_cmp(a, b);
29
case 0: /* BR */
26
- if (cmp == 0) {
30
case 1: /* BLR */
27
- cmp = a->sign < b->sign;
31
case 2: /* RET */
28
- }
32
- gen_a64_set_pc(s, cpu_reg(s, rn));
29
-
33
+ switch (op3) {
30
switch (s->float_2nan_prop_rule) {
34
+ case 0:
31
case float_2nan_prop_s_ab:
35
+ if (op4 != 0) {
32
if (have_snan) {
36
+ goto do_unallocated;
33
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
37
+ }
34
* return the NaN with the positive sign bit (if any).
38
+ dst = cpu_reg(s, rn);
35
*/
36
if (is_snan(a->cls)) {
37
- if (is_snan(b->cls)) {
38
- which = cmp > 0 ? 0 : 1;
39
- } else {
40
+ if (!is_snan(b->cls)) {
41
which = is_qnan(b->cls) ? 1 : 0;
42
+ break;
43
}
44
} else if (is_qnan(a->cls)) {
45
if (is_snan(b->cls) || !is_qnan(b->cls)) {
46
which = 0;
47
- } else {
48
- which = cmp > 0 ? 0 : 1;
49
+ break;
50
}
51
} else {
52
which = 1;
39
+ break;
53
+ break;
40
+
54
}
41
+ default:
55
+ cmp = frac_cmp(a, b);
42
+ goto do_unallocated;
56
+ if (cmp == 0) {
57
+ cmp = a->sign < b->sign;
43
+ }
58
+ }
44
+
59
+ which = cmp > 0 ? 0 : 1;
45
+ gen_a64_set_pc(s, dst);
46
/* BLR also needs to load return address */
47
if (opc == 1) {
48
tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
49
}
50
break;
60
break;
51
+
52
case 4: /* ERET */
53
if (s->current_el == 0) {
54
- unallocated_encoding(s);
55
- return;
56
+ goto do_unallocated;
57
+ }
58
+ switch (op3) {
59
+ case 0:
60
+ if (op4 != 0) {
61
+ goto do_unallocated;
62
+ }
63
+ dst = tcg_temp_new_i64();
64
+ tcg_gen_ld_i64(dst, cpu_env,
65
+ offsetof(CPUARMState, elr_el[s->current_el]));
66
+ break;
67
+
68
+ default:
69
+ goto do_unallocated;
70
}
71
if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
72
gen_io_start();
73
}
74
- dst = tcg_temp_new_i64();
75
- tcg_gen_ld_i64(dst, cpu_env,
76
- offsetof(CPUARMState, elr_el[s->current_el]));
77
+
78
gen_helper_exception_return(cpu_env, dst);
79
tcg_temp_free_i64(dst);
80
if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) {
81
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
82
/* Must exit loop to check un-masked IRQs */
83
s->base.is_jmp = DISAS_EXIT;
84
return;
85
+
86
case 5: /* DRPS */
87
- if (rn != 0x1f) {
88
- unallocated_encoding(s);
89
+ if (op3 != 0 || op4 != 0 || rn != 0x1f) {
90
+ goto do_unallocated;
91
} else {
92
unsupported_encoding(s, insn);
93
}
94
return;
95
+
96
default:
61
default:
97
+ do_unallocated:
62
g_assert_not_reached();
98
unallocated_encoding(s);
99
return;
100
}
101
--
63
--
102
2.20.1
64
2.34.1
103
104
diff view generated by jsdifflib
[Qemu-devel] [PULL 26/49] target/arm: Decode TBID from TCR
[PULL 70/72] softfloat: Replace WHICH with RET in parts_pick_nan
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Use TBID in aa64_va_parameters depending on the data parameter.
3
Replace the "index" selecting between A and B with a result variable
4
This automatically updates all existing users of the function.
4
of the proper type. This improves clarity within the function.
5
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
8
Message-id: 20190108223129.5570-23-richard.henderson@linaro.org
8
Message-id: 20241203203949.483774-12-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
target/arm/internals.h | 1 +
11
fpu/softfloat-parts.c.inc | 28 +++++++++++++---------------
12
target/arm/helper.c | 14 +++++++++++---
12
1 file changed, 13 insertions(+), 15 deletions(-)
13
2 files changed, 12 insertions(+), 3 deletions(-)
14
13
15
diff --git a/target/arm/internals.h b/target/arm/internals.h
14
diff --git a/fpu/softfloat-parts.c.inc b/fpu/softfloat-parts.c.inc
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/internals.h
16
--- a/fpu/softfloat-parts.c.inc
18
+++ b/target/arm/internals.h
17
+++ b/fpu/softfloat-parts.c.inc
19
@@ -XXX,XX +XXX,XX @@ typedef struct ARMVAParameters {
18
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
20
unsigned tsz : 8;
19
float_status *s)
21
unsigned select : 1;
22
bool tbi : 1;
23
+ bool tbid : 1;
24
bool epd : 1;
25
bool hpd : 1;
26
bool using16k : 1;
27
diff --git a/target/arm/helper.c b/target/arm/helper.c
28
index XXXXXXX..XXXXXXX 100644
29
--- a/target/arm/helper.c
30
+++ b/target/arm/helper.c
31
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va,
32
{
20
{
33
uint64_t tcr = regime_tcr(env, mmu_idx)->raw_tcr;
21
bool have_snan = false;
34
uint32_t el = regime_el(env, mmu_idx);
22
- int cmp, which;
35
- bool tbi, epd, hpd, using16k, using64k;
23
+ FloatPartsN *ret;
36
+ bool tbi, tbid, epd, hpd, using16k, using64k;
24
+ int cmp;
37
int select, tsz;
25
38
26
if (is_snan(a->cls) || is_snan(b->cls)) {
39
/*
27
float_raise(float_flag_invalid | float_flag_invalid_snan, s);
40
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va,
28
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
41
using16k = extract32(tcr, 15, 1);
29
switch (s->float_2nan_prop_rule) {
42
if (mmu_idx == ARMMMUIdx_S2NS) {
30
case float_2nan_prop_s_ab:
43
/* VTCR_EL2 */
31
if (have_snan) {
44
- tbi = hpd = false;
32
- which = is_snan(a->cls) ? 0 : 1;
45
+ tbi = tbid = hpd = false;
33
+ ret = is_snan(a->cls) ? a : b;
34
break;
35
}
36
/* fall through */
37
case float_2nan_prop_ab:
38
- which = is_nan(a->cls) ? 0 : 1;
39
+ ret = is_nan(a->cls) ? a : b;
40
break;
41
case float_2nan_prop_s_ba:
42
if (have_snan) {
43
- which = is_snan(b->cls) ? 1 : 0;
44
+ ret = is_snan(b->cls) ? b : a;
45
break;
46
}
47
/* fall through */
48
case float_2nan_prop_ba:
49
- which = is_nan(b->cls) ? 1 : 0;
50
+ ret = is_nan(b->cls) ? b : a;
51
break;
52
case float_2nan_prop_x87:
53
/*
54
@@ -XXX,XX +XXX,XX @@ static FloatPartsN *partsN(pick_nan)(FloatPartsN *a, FloatPartsN *b,
55
*/
56
if (is_snan(a->cls)) {
57
if (!is_snan(b->cls)) {
58
- which = is_qnan(b->cls) ? 1 : 0;
59
+ ret = is_qnan(b->cls) ? b : a;
60
break;
61
}
62
} else if (is_qnan(a->cls)) {
63
if (is_snan(b->cls) || !is_qnan(b->cls)) {
64
- which = 0;
65
+ ret = a;
66
break;
67
}
46
} else {
68
} else {
47
tbi = extract32(tcr, 20, 1);
69
- which = 1;
48
hpd = extract32(tcr, 24, 1);
70
+ ret = b;
49
+ tbid = extract32(tcr, 29, 1);
71
break;
50
}
72
}
51
epd = false;
73
cmp = frac_cmp(a, b);
52
} else if (!select) {
74
if (cmp == 0) {
53
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va,
75
cmp = a->sign < b->sign;
54
using16k = extract32(tcr, 15, 1);
76
}
55
tbi = extract64(tcr, 37, 1);
77
- which = cmp > 0 ? 0 : 1;
56
hpd = extract64(tcr, 41, 1);
78
+ ret = cmp > 0 ? a : b;
57
+ tbid = extract64(tcr, 51, 1);
79
break;
58
} else {
80
default:
59
int tg = extract32(tcr, 30, 2);
81
g_assert_not_reached();
60
using16k = tg == 1;
61
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va,
62
epd = extract32(tcr, 23, 1);
63
tbi = extract64(tcr, 38, 1);
64
hpd = extract64(tcr, 42, 1);
65
+ tbid = extract64(tcr, 52, 1);
66
}
82
}
67
tsz = MIN(tsz, 39); /* TODO: ARMv8.4-TTST */
83
68
tsz = MAX(tsz, 16); /* TODO: ARMv8.2-LVA */
84
- if (which) {
69
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va,
85
- a = b;
70
.tsz = tsz,
86
+ if (is_snan(ret->cls)) {
71
.select = select,
87
+ parts_silence_nan(ret, s);
72
.tbi = tbi,
88
}
73
+ .tbid = tbid,
89
- if (is_snan(a->cls)) {
74
.epd = epd,
90
- parts_silence_nan(a, s);
75
.hpd = hpd,
91
- }
76
.using16k = using16k,
92
- return a;
77
@@ -XXX,XX +XXX,XX @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va,
78
ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va,
79
ARMMMUIdx mmu_idx, bool data)
80
{
81
- return aa64_va_parameters_both(env, va, mmu_idx);
82
+ ARMVAParameters ret = aa64_va_parameters_both(env, va, mmu_idx);
83
+
84
+ /* Present TBI as a composite with TBID. */
85
+ ret.tbi &= (data || !ret.tbid);
86
+ return ret;
93
+ return ret;
87
}
94
}
88
95
89
static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
96
static FloatPartsN *partsN(pick_nan_muladd)(FloatPartsN *a, FloatPartsN *b,
90
--
97
--
91
2.20.1
98
2.34.1
92
99
93
100
diff view generated by jsdifflib
[Qemu-devel] [PULL 42/49] target/arm: Define FIELDs for ID_DFR0
[PULL 71/72] MAINTAINERS: update email address for Leif Lindholm
1
From: Aaron Lindsay <aaron@os.amperecomputing.com>
1
From: Leif Lindholm <quic_llindhol@quicinc.com>
2
2
3
This is immediately necessary for the PMUv3 implementation to check
3
I'm migrating to Qualcomm's new open source email infrastructure, so
4
ID_DFR0.PerfMon to enable/disable specific features, but defines the
4
update my email address, and update the mailmap to match.
5
full complement of fields for possible future use elsewhere.
6
5
7
Signed-off-by: Aaron Lindsay <aaron@os.amperecomputing.com>
6
Signed-off-by: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Leif Lindholm <quic_llindhol@quicinc.com>
9
Message-id: 20181211151945.29137-8-aaron@os.amperecomputing.com
8
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
10
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
11
Message-id: 20241205114047.1125842-1-leif.lindholm@oss.qualcomm.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
13
---
12
target/arm/cpu.h | 9 +++++++++
14
MAINTAINERS | 2 +-
13
1 file changed, 9 insertions(+)
15
.mailmap | 5 +++--
16
2 files changed, 4 insertions(+), 3 deletions(-)
14
17
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
diff --git a/MAINTAINERS b/MAINTAINERS
16
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu.h
20
--- a/MAINTAINERS
18
+++ b/target/arm/cpu.h
21
+++ b/MAINTAINERS
19
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64MMFR1, PAN, 20, 4)
22
@@ -XXX,XX +XXX,XX @@ F: include/hw/ssi/imx_spi.h
20
FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
23
SBSA-REF
21
FIELD(ID_AA64MMFR1, XNX, 28, 4)
24
M: Radoslaw Biernacki <rad@semihalf.com>
22
25
M: Peter Maydell <peter.maydell@linaro.org>
23
+FIELD(ID_DFR0, COPDBG, 0, 4)
26
-R: Leif Lindholm <quic_llindhol@quicinc.com>
24
+FIELD(ID_DFR0, COPSDBG, 4, 4)
27
+R: Leif Lindholm <leif.lindholm@oss.qualcomm.com>
25
+FIELD(ID_DFR0, MMAPDBG, 8, 4)
28
R: Marcin Juszkiewicz <marcin.juszkiewicz@linaro.org>
26
+FIELD(ID_DFR0, COPTRC, 12, 4)
29
L: qemu-arm@nongnu.org
27
+FIELD(ID_DFR0, MMAPTRC, 16, 4)
30
S: Maintained
28
+FIELD(ID_DFR0, MPROFDBG, 20, 4)
31
diff --git a/.mailmap b/.mailmap
29
+FIELD(ID_DFR0, PERFMON, 24, 4)
32
index XXXXXXX..XXXXXXX 100644
30
+FIELD(ID_DFR0, TRACEFILT, 28, 4)
33
--- a/.mailmap
31
+
34
+++ b/.mailmap
32
QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
35
@@ -XXX,XX +XXX,XX @@ Huacai Chen <chenhuacai@kernel.org> <chenhc@lemote.com>
33
36
Huacai Chen <chenhuacai@kernel.org> <chenhuacai@loongson.cn>
34
/* If adding a feature bit which corresponds to a Linux ELF
37
James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
38
Juan Quintela <quintela@trasno.org> <quintela@redhat.com>
39
-Leif Lindholm <quic_llindhol@quicinc.com> <leif.lindholm@linaro.org>
40
-Leif Lindholm <quic_llindhol@quicinc.com> <leif@nuviainc.com>
41
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <quic_llindhol@quicinc.com>
42
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif.lindholm@linaro.org>
43
+Leif Lindholm <leif.lindholm@oss.qualcomm.com> <leif@nuviainc.com>
44
Luc Michel <luc@lmichel.fr> <luc.michel@git.antfield.fr>
45
Luc Michel <luc@lmichel.fr> <luc.michel@greensocs.com>
46
Luc Michel <luc@lmichel.fr> <lmichel@kalray.eu>
35
--
47
--
36
2.20.1
48
2.34.1
37
49
38
50
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/49] hw/arm/virt-acpi-build: Set COHACC override flag in IORT SMMUv3 node
[PULL 72/72] MAINTAINERS: Add correct email address for Vikram Garhwal
1
From: Eric Auger <eric.auger@redhat.com>
1
From: Vikram Garhwal <vikram.garhwal@bytedance.com>
2
2
3
Let's report IO-coherent access is supported for translation
3
Previously, maintainer role was paused due to inactive email id. Commit id:
4
table walks, descriptor fetches and queues by setting the COHACC
4
c009d715721861984c4987bcc78b7ee183e86d75.
5
override flag. Without that, we observe wrong command opcodes.
6
The DT description also advertises the dma coherency.
7
5
8
Fixes a703b4f6c1ee ("hw/arm/virt-acpi-build: Add smmuv3 node in IORT table")
6
Signed-off-by: Vikram Garhwal <vikram.garhwal@bytedance.com>
9
7
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com>
10
Signed-off-by: Eric Auger <eric.auger@redhat.com>
8
Message-id: 20241204184205.12952-1-vikram.garhwal@bytedance.com
11
Reported-by: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>
12
Tested-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
13
Reviewed-by: Andrew Jones <drjones@redhat.com>
14
Message-id: 20190107101041.765-1-eric.auger@redhat.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
10
---
17
include/hw/acpi/acpi-defs.h | 2 ++
11
MAINTAINERS | 2 ++
18
hw/arm/virt-acpi-build.c | 1 +
12
1 file changed, 2 insertions(+)
19
2 files changed, 3 insertions(+)
20
13
21
diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h
14
diff --git a/MAINTAINERS b/MAINTAINERS
22
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
23
--- a/include/hw/acpi/acpi-defs.h
16
--- a/MAINTAINERS
24
+++ b/include/hw/acpi/acpi-defs.h
17
+++ b/MAINTAINERS
25
@@ -XXX,XX +XXX,XX @@ struct AcpiIortItsGroup {
18
@@ -XXX,XX +XXX,XX @@ F: tests/qtest/fuzz-sb16-test.c
26
} QEMU_PACKED;
19
27
typedef struct AcpiIortItsGroup AcpiIortItsGroup;
20
Xilinx CAN
28
21
M: Francisco Iglesias <francisco.iglesias@amd.com>
29
+#define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE 1
22
+M: Vikram Garhwal <vikram.garhwal@bytedance.com>
30
+
23
S: Maintained
31
struct AcpiIortSmmu3 {
24
F: hw/net/can/xlnx-*
32
ACPI_IORT_NODE_HEADER_DEF
25
F: include/hw/net/xlnx-*
33
uint64_t base_address;
26
@@ -XXX,XX +XXX,XX @@ F: include/hw/rx/
34
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
27
CAN bus subsystem and hardware
35
index XXXXXXX..XXXXXXX 100644
28
M: Pavel Pisa <pisa@cmp.felk.cvut.cz>
36
--- a/hw/arm/virt-acpi-build.c
29
M: Francisco Iglesias <francisco.iglesias@amd.com>
37
+++ b/hw/arm/virt-acpi-build.c
30
+M: Vikram Garhwal <vikram.garhwal@bytedance.com>
38
@@ -XXX,XX +XXX,XX @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
31
S: Maintained
39
smmu->mapping_count = cpu_to_le32(1);
32
W: https://canbus.pages.fel.cvut.cz/
40
smmu->mapping_offset = cpu_to_le32(sizeof(*smmu));
33
F: net/can/*
41
smmu->base_address = cpu_to_le64(vms->memmap[VIRT_SMMU].base);
42
+ smmu->flags = cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE);
43
smmu->event_gsiv = cpu_to_le32(irq);
44
smmu->pri_gsiv = cpu_to_le32(irq + 1);
45
smmu->gerr_gsiv = cpu_to_le32(irq + 2);
46
--
34
--
47
2.20.1
35
2.34.1
48
49
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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