Hi,

this patchset converts the RISC-V decoder to decodetree in four major steps:

1) Convert 32-bit instructions to decodetree [Patch 1-16]:
    Many of the gen_* functions are called by the decode functions for 16-bit
    and 32-bit functions. If we move translation code from the gen_*
    functions to the generated trans_* functions of decode-tree, we get a lot of
    duplication. Therefore, we mostly generate calls to the old gen_* function
    which are properly replaced after step 2).

    Each of the trans_ functions are grouped into files corresponding to their
    ISA extension, e.g. addi which is in RV32I is translated in the file
    'trans_rvi.inc.c'.

2) Convert 16-bit instructions to decodetree [Patch 17-19]:
    All 16 bit instructions have a direct mapping to a 32 bit instruction. Thus,
    we convert the arguments in the 16 bit trans_ function to the arguments of
    the corresponding 32 bit instruction and call the 32 bit trans_ function.

3) Remove old manual decoding in gen_* function [Patch 20-30]:
    this move all manual translation code into the trans_* instructions of
    decode tree, such that we can remove the old decode_* functions.

4) Simply RVC by reusing as much as possible from the RVG decoder as suggested
   by Richard. [Patch 31-35]

full tree available at
https://github.com/bkoppelmann/qemu/tree/riscv-dt-v4

Cheers,
Bastian

v3 -> v4:
    - moved uint32_t insn removal from patch 0004 here
    - removed accidental argument removal
    - insn64.decode -> insn32-64.decode
    - shamt of shift insn is now 10 bit
    - @sh6 -> @sh
    - %sh6 -> %sh10
    - current_cpu->env_ptr -> ctx-env
    - int memop -> TCGMemop memop
    - gen_addiw -> gen_addw
    - add TARGET_LONG_BITS check for sari and shri
    - trans_addw now uses gen_addw
    - trans_subw now uses gen_subw
    - refactor tcg_gen_set_cond_tl(TCG_COND_LT,..) into gen_slt function
      and reuse gen_arith(..., &gen_slt) for all trans_slt functions.
    - Add missing sign extension to trans_srlw/sllw
    - Made rs2 == 0 a special case of srlw/sllw
    - trans_sltu/slt added to conversion

Bastian Koppelmann (35):
  target/riscv: Move CPURISCVState pointer to DisasContext
  target/riscv: Activate decodetree and implemnt LUI & AUIPC
  target/riscv: Convert RVXI branch insns to decodetree
  target/riscv: Convert RV32I load/store insns to decodetree
  target/riscv: Convert RV64I load/store insns to decodetree
  target/riscv: Convert RVXI arithmetic insns to decodetree
  target/riscv: Convert RVXI fence insns to decodetree
  target/riscv: Convert RVXI csr insns to decodetree
  target/riscv: Convert RVXM insns to decodetree
  target/riscv: Convert RV32A insns to decodetree
  target/riscv: Convert RV64A insns to decodetree
  target/riscv: Convert RV32F insns to decodetree
  target/riscv: Convert RV64F insns to decodetree
  target/riscv: Convert RV32D insns to decodetree
  target/riscv: Convert RV64D insns to decodetree
  target/riscv: Convert RV priv insns to decodetree
  target/riscv: Convert quadrant 0 of RVXC insns to decodetree
  target/riscv: Convert quadrant 1 of RVXC insns to decodetree
  target/riscv: Convert quadrant 2 of RVXC insns to decodetree
  target/riscv: Remove gen_jalr()
  target/riscv: Remove manual decoding from gen_branch()
  target/riscv: Remove manual decoding from gen_load()
  target/riscv: Remove manual decoding from gen_store()
  target/riscv: Move gen_arith_imm() decoding into trans_* functions
  target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
  target/riscv: Remove shift and slt insn manual decoding
  target/riscv: Remove manual decoding of RV32/64M insn
  target/riscv: Rename trans_arith to gen_arith
  target/riscv: Remove gen_system()
  target/riscv: Remove decode_RV32_64G()
  target/riscv: Convert @cs_2 insns to share translation
    functions<Paste>
  target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
  target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
  target/riscv: Splice remaining compressed insn pairs for riscv32 vs
    riscv64
  target/riscv: Remaining rvc insn reuse 32 bit translators

 target/riscv/Makefile.objs                    |   22 +
 target/riscv/insn16-32.decode                 |   31 +
 target/riscv/insn16-64.decode                 |   33 +
 target/riscv/insn16.decode                    |  114 ++
 target/riscv/insn32-64.decode                 |   72 +
 target/riscv/insn32.decode                    |  203 ++
 .../riscv/insn_trans/trans_privileged.inc.c   |  110 +
 target/riscv/insn_trans/trans_rva.inc.c       |  207 ++
 target/riscv/insn_trans/trans_rvc.inc.c       |  149 ++
 target/riscv/insn_trans/trans_rvd.inc.c       |  388 ++++
 target/riscv/insn_trans/trans_rvf.inc.c       |  388 ++++
 target/riscv/insn_trans/trans_rvi.inc.c       |  576 ++++++
 target/riscv/insn_trans/trans_rvm.inc.c       |  107 +
 target/riscv/translate.c                      | 1781 ++---------------
 14 files changed, 2619 insertions(+), 1562 deletions(-)
 create mode 100644 target/riscv/insn16-32.decode
 create mode 100644 target/riscv/insn16-64.decode
 create mode 100644 target/riscv/insn16.decode
 create mode 100644 target/riscv/insn32-64.decode
 create mode 100644 target/riscv/insn32.decode
 create mode 100644 target/riscv/insn_trans/trans_privileged.inc.c
 create mode 100644 target/riscv/insn_trans/trans_rva.inc.c
 create mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
 create mode 100644 target/riscv/insn_trans/trans_rvd.inc.c
 create mode 100644 target/riscv/insn_trans/trans_rvf.inc.c
 create mode 100644 target/riscv/insn_trans/trans_rvi.inc.c
 create mode 100644 target/riscv/insn_trans/trans_rvm.inc.c

-- 
2.20.1

Patchew URL: https://patchew.org/QEMU/20190118131456.32451-1-kbastian@mail.uni-paderborn.de/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH v4 00/35] target/riscv: Convert to decodetree
Type: series
Message-id: 20190118131456.32451-1-kbastian@mail.uni-paderborn.de

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
f6f73425dd target/riscv: Remaining rvc insn reuse 32 bit translators
176bc716e7 target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64
82c8d52060 target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64
ce2183c0c3 target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns
3dae5a0b0e target/riscv: Convert @cs_2 insns to share translation functions<Paste>
9eb19b0f1f target/riscv: Remove decode_RV32_64G()
668dc71c41 target/riscv: Remove gen_system()
c096f1a626 target/riscv: Rename trans_arith to gen_arith
eaa23f103b target/riscv: Remove manual decoding of RV32/64M insn
5df0d6fbad target/riscv: Remove shift and slt insn manual decoding
b67b6d1b84 target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists
36b50a0962 target/riscv: Move gen_arith_imm() decoding into trans_* functions
b71002a2a1 target/riscv: Remove manual decoding from gen_store()
af162e52bc target/riscv: Remove manual decoding from gen_load()
fcbab1187b target/riscv: Remove manual decoding from gen_branch()
0147cc97ef target/riscv: Remove gen_jalr()
57de41b36a target/riscv: Convert quadrant 2 of RVXC insns to decodetree
e128e466e1 target/riscv: Convert quadrant 1 of RVXC insns to decodetree
7911019e0e target/riscv: Convert quadrant 0 of RVXC insns to decodetree
1f5647add8 target/riscv: Convert RV priv insns to decodetree
4fd3d27809 target/riscv: Convert RV64D insns to decodetree
1e73b704d0 target/riscv: Convert RV32D insns to decodetree
dac7069330 target/riscv: Convert RV64F insns to decodetree
1ed8dbdeaa target/riscv: Convert RV32F insns to decodetree
f634a9d66c target/riscv: Convert RV64A insns to decodetree
3a8ba02eba target/riscv: Convert RV32A insns to decodetree
01b30a9bbf target/riscv: Convert RVXM insns to decodetree
8c6c462741 target/riscv: Convert RVXI csr insns to decodetree
2b28536c7e target/riscv: Convert RVXI fence insns to decodetree
350d085603 target/riscv: Convert RVXI arithmetic insns to decodetree
dcfa0400bc target/riscv: Convert RV64I load/store insns to decodetree
e5dd8d9eca target/riscv: Convert RV32I load/store insns to decodetree
4a03bffbba target/riscv: Convert RVXI branch insns to decodetree
244eaab491 target/riscv: Activate decodetree and implemnt LUI & AUIPC
5a517f6ef0 target/riscv: Move CPURISCVState pointer to DisasContext

=== OUTPUT BEGIN ===
1/35 Checking commit 5a517f6ef083 (target/riscv: Move CPURISCVState pointer to DisasContext)
2/35 Checking commit 244eaab49155 (target/riscv: Activate decodetree and implemnt LUI & AUIPC)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#33: 
new file mode 100644

ERROR: externs should be avoided in .c files
#124: FILE: target/riscv/translate.c:1687:
+bool decode_insn32(DisasContext *ctx, uint32_t insn);

total: 1 errors, 1 warnings, 125 lines checked

Patch 2/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

3/35 Checking commit 4a03bffbba6b (target/riscv: Convert RVXI branch insns to decodetree)
4/35 Checking commit e5dd8d9ecae9 (target/riscv: Convert RV32I load/store insns to decodetree)
5/35 Checking commit dcfa0400bc76 (target/riscv: Convert RV64I load/store insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#38: 
new file mode 100644

total: 0 errors, 1 warnings, 76 lines checked

Patch 5/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
6/35 Checking commit 350d085603fa (target/riscv: Convert RVXI arithmetic insns to decodetree)
7/35 Checking commit 2b28536c7ea8 (target/riscv: Convert RVXI fence insns to decodetree)
8/35 Checking commit 8c6c46274132 (target/riscv: Convert RVXI csr insns to decodetree)
9/35 Checking commit 01b30a9bbfc0 (target/riscv: Convert RVXM insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#47: 
new file mode 100644

total: 0 errors, 1 warnings, 145 lines checked

Patch 9/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
10/35 Checking commit 3a8ba02eba5b (target/riscv: Convert RV32A insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#52: 
new file mode 100644

total: 0 errors, 1 warnings, 188 lines checked

Patch 10/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
11/35 Checking commit f634a9d66c84 (target/riscv: Convert RV64A insns to decodetree)
12/35 Checking commit 1ed8dbdeaaee (target/riscv: Convert RV32F insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#76: 
new file mode 100644

total: 0 errors, 1 warnings, 397 lines checked

Patch 12/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
13/35 Checking commit dac7069330ea (target/riscv: Convert RV64F insns to decodetree)
14/35 Checking commit 1e73b704d0f9 (target/riscv: Convert RV32D insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#49: 
new file mode 100644

total: 0 errors, 1 warnings, 353 lines checked

Patch 14/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
15/35 Checking commit 4fd3d2780922 (target/riscv: Convert RV64D insns to decodetree)
16/35 Checking commit 1f5647add875 (target/riscv: Convert RV priv insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#39: 
new file mode 100644

total: 0 errors, 1 warnings, 214 lines checked

Patch 16/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/35 Checking commit 7911019e0eb8 (target/riscv: Convert quadrant 0 of RVXC insns to decodetree)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#30: 
new file mode 100644

ERROR: externs should be avoided in .c files
#245: FILE: target/riscv/translate.c:983:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);

total: 1 errors, 1 warnings, 227 lines checked

Patch 17/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

18/35 Checking commit e128e466e1c8 (target/riscv: Convert quadrant 1 of RVXC insns to decodetree)
19/35 Checking commit 57de41b36ad8 (target/riscv: Convert quadrant 2 of RVXC insns to decodetree)
20/35 Checking commit 0147cc97ef46 (target/riscv: Remove gen_jalr())
21/35 Checking commit fcbab1187bba (target/riscv: Remove manual decoding from gen_branch())
22/35 Checking commit af162e52bc2c (target/riscv: Remove manual decoding from gen_load())
23/35 Checking commit b71002a2a1c6 (target/riscv: Remove manual decoding from gen_store())
24/35 Checking commit 36b50a096255 (target/riscv: Move gen_arith_imm() decoding into trans_* functions)
25/35 Checking commit b67b6d1b8445 (target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists)
26/35 Checking commit 5df0d6fbad3e (target/riscv: Remove shift and slt insn manual decoding)
27/35 Checking commit eaa23f103bcd (target/riscv: Remove manual decoding of RV32/64M insn)
28/35 Checking commit c096f1a62601 (target/riscv: Rename trans_arith to gen_arith)
29/35 Checking commit 668dc71c417a (target/riscv: Remove gen_system())
30/35 Checking commit 9eb19b0f1f56 (target/riscv: Remove decode_RV32_64G())
31/35 Checking commit 3dae5a0b0eec (target/riscv: Convert @cs_2 insns to share translation functions<Paste>)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#41: 
new file mode 100644

ERROR: externs should be avoided in .c files
#181: FILE: target/riscv/translate.c:497:
+bool decode_insn16(DisasContext *ctx, uint16_t insn);

total: 1 errors, 1 warnings, 164 lines checked

Patch 31/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

32/35 Checking commit ce2183c0c353 (target/riscv: Convert @cl_d, @cl_w, @cs_d, @cs_w insns)
33/35 Checking commit 82c8d52060ae (target/riscv: Splice fsw_sd and flw_ld for riscv32 vs riscv64)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#27: 
new file mode 100644

total: 0 errors, 1 warnings, 287 lines checked

Patch 33/35 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
34/35 Checking commit 176bc716e7f5 (target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64)
35/35 Checking commit f6f73425dde7 (target/riscv: Remaining rvc insn reuse 32 bit translators)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20190118131456.32451-1-kbastian@mail.uni-paderborn.de/testing.checkpatch/?type=message.
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