x86 queue, 2019-01-14

[Qemu-devel] [PULL 0/5] x86 queue, 2019-01-14

Eduardo Habkost posted 5 patches 6 years, 9 months ago

Download series mbox

Test asan passed

Test checkpatch passed

Test docker-clang@ubuntu passed

Test docker-mingw@fedora passed

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20190114143432.4771-1-ehabkost@redhat.com

Maintainers: Marcelo Tosatti <mtosatti@redhat.com>, Richard Henderson <rth@twiddle.net>, Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, "Michael S. Tsirkin" <mst@redhat.com>, Paolo Bonzini <pbonzini@redhat.com>, Eduardo Habkost <ehabkost@redhat.com>

target/i386/cpu.h |  5 +++
hw/i386/pc.c      | 10 ++++++
target/i386/cpu.c | 67 +++++++++++++++++++++++++++++--------
target/i386/kvm.c | 85 +++++++++++++++++++++++++----------------------
qemu-doc.texi     | 13 ++++++++
5 files changed, 126 insertions(+), 54 deletions(-)

Expand all Fold all

[Qemu-devel] [PULL 0/5] x86 queue, 2019-01-14

Posted by Eduardo Habkost 6 years, 9 months ago

The following changes since commit 7260438b7056469610ee166f7abe9ff8a26b8b16:

  Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-3.2-part2' into staging (2019-01-14 11:41:43 +0000)

are available in the Git repository at:

  git://github.com/ehabkost/qemu.git tags/x86-next-pull-request

for you to fetch changes up to abd5fc4c862d033a989552914149f01c9476bb16:

  i386/kvm: add a comment explaining why .feat_names are commented out for Hyper-V feature bits (2019-01-14 12:28:44 -0200)

----------------------------------------------------------------
x86 queue, 2019-01-14

* Reenable RDTSCP support on Opteron_G[345] CPU models CPU models
  (Borislav Petkov)
* host-phys-bits-limit option for better control of 5-level EPT
  (Eduardo Habkost)
* Disable MPX support on named CPU models (Paolo Bonzini)
* expose HV_CPUID_ENLIGHTMENT_INFO.EAX and HV_CPUID_NESTED_FEATURES.EAX
  as feature words (Vitaly Kuznetsov)

----------------------------------------------------------------

Borislav Petkov (1):
  target-i386: Reenable RDTSCP support on Opteron_G[345] CPU models CPU
    models

Eduardo Habkost (1):
  x86: host-phys-bits-limit option

Paolo Bonzini (1):
  target/i386: Disable MPX support on named CPU models

Vitaly Kuznetsov (2):
  i386/kvm: expose HV_CPUID_ENLIGHTMENT_INFO.EAX and
    HV_CPUID_NESTED_FEATURES.EAX as feature words
  i386/kvm: add a comment explaining why .feat_names are commented out
    for Hyper-V feature bits

 target/i386/cpu.h |  5 +++
 hw/i386/pc.c      | 10 ++++++
 target/i386/cpu.c | 67 +++++++++++++++++++++++++++++--------
 target/i386/kvm.c | 85 +++++++++++++++++++++++++----------------------
 qemu-doc.texi     | 13 ++++++++
 5 files changed, 126 insertions(+), 54 deletions(-)

-- 
2.18.0.rc1.1.g3f1ff2140

Re: [Qemu-devel] [PULL 0/5] x86 queue, 2019-01-14

Posted by Peter Maydell 6 years, 9 months ago

On Mon, 14 Jan 2019 at 14:34, Eduardo Habkost <ehabkost@redhat.com> wrote:
>
> The following changes since commit 7260438b7056469610ee166f7abe9ff8a26b8b16:
>
>   Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-3.2-part2' into staging (2019-01-14 11:41:43 +0000)
>
> are available in the Git repository at:
>
>   git://github.com/ehabkost/qemu.git tags/x86-next-pull-request
>
> for you to fetch changes up to abd5fc4c862d033a989552914149f01c9476bb16:
>
>   i386/kvm: add a comment explaining why .feat_names are commented out for Hyper-V feature bits (2019-01-14 12:28:44 -0200)
>
> ----------------------------------------------------------------
> x86 queue, 2019-01-14
>
> * Reenable RDTSCP support on Opteron_G[345] CPU models CPU models
>   (Borislav Petkov)
> * host-phys-bits-limit option for better control of 5-level EPT
>   (Eduardo Habkost)
> * Disable MPX support on named CPU models (Paolo Bonzini)
> * expose HV_CPUID_ENLIGHTMENT_INFO.EAX and HV_CPUID_NESTED_FEATURES.EAX
>   as feature words (Vitaly Kuznetsov)
>


Applied, thanks.

Please update the changelog at https://wiki.qemu.org/ChangeLog/4.0
for any user-visible changes.

-- PMM