target/arm: SVE brk[ab] merging does not have s bit

[Qemu-devel] [PATCH] target/arm: SVE brk[ab] merging does not have s bit

Richard Henderson posted 1 patch 6 years, 10 months ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20181226215003.31438-1-richard.henderson@linaro.org

target/arm/sve.decode | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)

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[Qemu-devel] [PATCH] target/arm: SVE brk[ab] merging does not have s bit

Posted by Richard Henderson 6 years, 10 months ago

While brk[ab] zeroing has a flags setting option, the merging variant
does not.  Retain the same argument structure, to share expansion but
force the flag zero and do not decode bit 22.

Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---

The xml from which Alex and I extracted risu test cases does not call
out bit 22 as a field, so we did not test this illegal encoding.


r~

---
 target/arm/sve.decode | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index e10b689454..4f580a25e7 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -99,6 +99,7 @@
 
 # Two operand with governing predicate, flags setting
 @pd_pg_pn_s     ........ . s:1 ...... .. pg:4 . rn:4 . rd:4     &rpr_s
+@pd_pg_pn_s0    ........ . .   ...... .. pg:4 . rn:4 . rd:4     &rpr_s s=0
 
 # Three operand with unused vector element size
 @rd_rn_rm_e0    ........ ... rm:5 ... ... rn:5 rd:5             &rrr_esz esz=0
@@ -667,8 +668,8 @@ BRKPB           00100101 0. 00 .... 11 .... 0 .... 1 ....       @pd_pg_pn_pm_s
 # SVE partition break condition
 BRKA_z          00100101 0. 01000001 .... 0 .... 0 ....         @pd_pg_pn_s
 BRKB_z          00100101 1. 01000001 .... 0 .... 0 ....         @pd_pg_pn_s
-BRKA_m          00100101 0. 01000001 .... 0 .... 1 ....         @pd_pg_pn_s
-BRKB_m          00100101 1. 01000001 .... 0 .... 1 ....         @pd_pg_pn_s
+BRKA_m          00100101 00 01000001 .... 0 .... 1 ....         @pd_pg_pn_s0
+BRKB_m          00100101 10 01000001 .... 0 .... 1 ....         @pd_pg_pn_s0
 
 # SVE propagate break to next partition
 BRKN            00100101 0. 01100001 .... 0 .... 0 ....         @pd_pg_pn_s
-- 
2.17.2

Re: [Qemu-devel] [PATCH] target/arm: SVE brk[ab] merging does not have s bit

Posted by Peter Maydell 6 years, 10 months ago

On Wed, 26 Dec 2018 at 21:50, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> While brk[ab] zeroing has a flags setting option, the merging variant
> does not.  Retain the same argument structure, to share expansion but
> force the flag zero and do not decode bit 22.
>
> Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>
> The xml from which Alex and I extracted risu test cases does not call
> out bit 22 as a field, so we did not test this illegal encoding.
>
>
> r~



Applied to target-arm.next, thanks.

-- PMM