Patchew URL: https://patchew.org/QEMU/20181221054606.22007-1-david@gibson.dropbear.id.au/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Message-id: 20181221054606.22007-1-david@gibson.dropbear.id.au
Type: series
Subject: [Qemu-devel] [PULL 00/40] ppc-for-4.0 queue 20181221
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
3e3257b MAINTAINERS: PPC: add a XIVE section
610fd97 spapr: change default CPU type to POWER9
38d68c5 spapr: introduce an 'ic-mode' machine option
59285f4 spapr: add an extra OV5 field to the sPAPR IRQ backend
ebdbab8 spapr: add a 'reset' method to the sPAPR IRQ backend
12d2218 spapr: extend the sPAPR IRQ backend for XICS migration
a376568 spapr: allocate the interrupt thread context under the CPU core
33ffe3a spapr: add device tree support for the XIVE exploitation mode
3962d69 spapr: add hcalls support for the XIVE exploitation interrupt mode
6f6a699 spapr: introduce a new machine IRQ backend for XIVE
cca3ce9 spapr-iommu: Always advertise the maximum possible DMA window size
9875f16 spapr/xive: use the VCPU id as a NVT identifier
e0a8db4 spapr/xive: introduce a XIVE interrupt controller
9c5e723 ppc/xive: notify the CPU when the interrupt priority is more privileged
6f99321 ppc/xive: introduce a simplified XIVE presenter
5c4d7e5 ppc/xive: introduce the XIVE interrupt thread context
8c7415b ppc/xive: add support for the END Event State Buffers
50b9048 Changes requirement for "vsubsbs" instruction
fc26946 spapr: export and rename the xics_max_server_number() routine
65a9820 spapr: introduce a spapr_irq_init() routine
30986ca spapr: initialize VSMT before initializing the IRQ backend
12a92e3 ppc/xive: introduce the XIVE Event Notification Descriptors
d7e1676 ppc/xive: introduce the XiveRouter model
85f99a9 ppc/xive: introduce the XiveNotifier interface
9b72206 ppc/xive: add support for the LSI interrupt sources
ec30f00 ppc/xive: introduce a XIVE interrupt source model
e73441e e500: simplify IRQ wiring
c4c2fcb mac_newworld: simplify IRQ wiring
0c3b152 virtex_ml507: use g_new(T, n) instead of g_malloc(sizeof(T) * n)
ebb0ba1 sam460ex: use g_new(T, n) instead of g_malloc(sizeof(T) * n)
a8b6872 ppc440_bamboo: use g_new(T, n) instead of g_malloc(sizeof(T) * n)
2cc02cb ppc405_uc: use g_new(T, n) instead of g_malloc(sizeof(T) * n)
08ddb1e ppc405_boards: use g_new(T, n) instead of g_malloc(sizeof(T) * n)
b008779 spapr: use g_new(T, n) instead of g_malloc(sizeof(T) * n)
0e3b318 target/ppc: use g_new(T, n) instead of g_malloc(sizeof(T) * n)
e630f11 spapr: drop redundant statement in spapr_populate_drconf_memory()
1e34165 target/ppc: tcg: Implement addex instruction
f6eb4c0 spapr: Fix ibm, max-associativity-domains property number of nodes
9d9742d target/ppc: Remove silly GETFIELD/SETFIELD/MASK_TO_LSH macros
fc4b65a target/ppc: fix the PPC_BIT definitions
=== OUTPUT BEGIN ===
Checking PATCH 1/40: target/ppc: fix the PPC_BIT definitions...
Checking PATCH 2/40: target/ppc: Remove silly GETFIELD/SETFIELD/MASK_TO_LSH macros...
Checking PATCH 3/40: spapr: Fix ibm, max-associativity-domains property number of nodes...
Checking PATCH 4/40: target/ppc: tcg: Implement addex instruction...
ERROR: space required after that ',' (ctx:VxV)
#42: FILE: disas/ppc.c:3737:
+{ "addex", XO(31,170,0,0), XO_MASK, POWER9, { RT, RA, RB } },
^
ERROR: space required after that ',' (ctx:VxV)
#42: FILE: disas/ppc.c:3737:
+{ "addex", XO(31,170,0,0), XO_MASK, POWER9, { RT, RA, RB } },
^
ERROR: space required after that ',' (ctx:VxV)
#42: FILE: disas/ppc.c:3737:
+{ "addex", XO(31,170,0,0), XO_MASK, POWER9, { RT, RA, RB } },
^
total: 3 errors, 0 warnings, 156 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 5/40: spapr: drop redundant statement in spapr_populate_drconf_memory()...
Checking PATCH 6/40: target/ppc: use g_new(T, n) instead of g_malloc(sizeof(T) * n)...
Checking PATCH 7/40: spapr: use g_new(T, n) instead of g_malloc(sizeof(T) * n)...
Checking PATCH 8/40: ppc405_boards: use g_new(T, n) instead of g_malloc(sizeof(T) * n)...
Checking PATCH 9/40: ppc405_uc: use g_new(T, n) instead of g_malloc(sizeof(T) * n)...
Checking PATCH 10/40: ppc440_bamboo: use g_new(T, n) instead of g_malloc(sizeof(T) * n)...
Checking PATCH 11/40: sam460ex: use g_new(T, n) instead of g_malloc(sizeof(T) * n)...
Checking PATCH 12/40: virtex_ml507: use g_new(T, n) instead of g_malloc(sizeof(T) * n)...
Checking PATCH 13/40: mac_newworld: simplify IRQ wiring...
Checking PATCH 14/40: e500: simplify IRQ wiring...
Checking PATCH 15/40: ppc/xive: introduce a XIVE interrupt source model...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#61:
new file mode 100644
total: 0 errors, 1 warnings, 656 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 16/40: ppc/xive: add support for the LSI interrupt sources...
Checking PATCH 17/40: ppc/xive: introduce the XiveNotifier interface...
Checking PATCH 18/40: ppc/xive: introduce the XiveRouter model...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#173:
new file mode 100644
total: 0 errors, 1 warnings, 192 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 19/40: ppc/xive: introduce the XIVE Event Notification Descriptors...
Checking PATCH 20/40: spapr: initialize VSMT before initializing the IRQ backend...
Checking PATCH 21/40: spapr: introduce a spapr_irq_init() routine...
Checking PATCH 22/40: spapr: export and rename the xics_max_server_number() routine...
Checking PATCH 23/40: Changes requirement for "vsubsbs" instruction...
Checking PATCH 24/40: ppc/xive: add support for the END Event State Buffers...
Checking PATCH 25/40: ppc/xive: introduce the XIVE interrupt thread context...
WARNING: Block comments use a leading /* on a separate line
#92: FILE: hw/intc/xive.c:57:
+ /* QW-0 User */ 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0,
WARNING: Block comments use a leading /* on a separate line
#93: FILE: hw/intc/xive.c:58:
+ /* QW-1 OS */ 3, 3, 3, 3, 3, 3, 0, 3, 3, 3, 3, 3, 0, 0, 0, 0,
WARNING: Block comments use a leading /* on a separate line
#94: FILE: hw/intc/xive.c:59:
+ /* QW-2 POOL */ 0, 0, 3, 3, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0,
WARNING: Block comments use a leading /* on a separate line
#95: FILE: hw/intc/xive.c:60:
+ /* QW-3 PHYS */ 3, 3, 3, 3, 0, 3, 0, 3, 3, 0, 0, 3, 3, 3, 3, 0,
WARNING: Block comments use a leading /* on a separate line
#99: FILE: hw/intc/xive.c:64:
+ /* QW-0 User */ 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0,
WARNING: Block comments use a leading /* on a separate line
#100: FILE: hw/intc/xive.c:65:
+ /* QW-1 OS */ 3, 3, 3, 3, 3, 3, 0, 3, 3, 3, 3, 3, 0, 0, 0, 0,
WARNING: Block comments use a leading /* on a separate line
#101: FILE: hw/intc/xive.c:66:
+ /* QW-2 POOL */ 0, 0, 3, 3, 0, 0, 0, 0, 0, 3, 3, 3, 0, 0, 0, 0,
WARNING: Block comments use a leading /* on a separate line
#102: FILE: hw/intc/xive.c:67:
+ /* QW-3 PHYS */ 3, 3, 3, 3, 0, 3, 0, 3, 3, 0, 0, 3, 0, 0, 0, 0,
WARNING: Block comments use a leading /* on a separate line
#106: FILE: hw/intc/xive.c:71:
+ /* QW-0 User */ 3, 0, 0, 0, 0, 0, 0, 0, 3, 3, 3, 3, 0, 0, 0, 0,
WARNING: Block comments use a leading /* on a separate line
#107: FILE: hw/intc/xive.c:72:
+ /* QW-1 OS */ 2, 3, 2, 2, 2, 2, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0,
WARNING: Block comments use a leading /* on a separate line
#108: FILE: hw/intc/xive.c:73:
+ /* QW-2 POOL */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
WARNING: Block comments use a leading /* on a separate line
#109: FILE: hw/intc/xive.c:74:
+ /* QW-3 PHYS */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
WARNING: Block comments use a leading /* on a separate line
#113: FILE: hw/intc/xive.c:78:
+ /* QW-0 User */ 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
WARNING: Block comments use a leading /* on a separate line
#114: FILE: hw/intc/xive.c:79:
+ /* QW-1 OS */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
WARNING: Block comments use a leading /* on a separate line
#115: FILE: hw/intc/xive.c:80:
+ /* QW-2 POOL */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
WARNING: Block comments use a leading /* on a separate line
#116: FILE: hw/intc/xive.c:81:
+ /* QW-3 PHYS */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
WARNING: Block comments use a leading /* on a separate line
#604: FILE: include/hw/ppc/xive_regs.h:81:
+#define TM_SPC_PULL_USR_CTX 0x808 /* Load32 Pull/Invalidate user
WARNING: Block comments use a trailing */ on a separate line
#605: FILE: include/hw/ppc/xive_regs.h:82:
+ * context */
WARNING: Block comments use a leading /* on a separate line
#607: FILE: include/hw/ppc/xive_regs.h:84:
+#define TM_SPC_PULL_OS_CTX 0x818 /* Load32/Load64 Pull/Invalidate OS
WARNING: Block comments use a trailing */ on a separate line
#608: FILE: include/hw/ppc/xive_regs.h:85:
+ * context to reg */
WARNING: Block comments use a leading /* on a separate line
#609: FILE: include/hw/ppc/xive_regs.h:86:
+#define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate Pool
WARNING: Block comments use a trailing */ on a separate line
#610: FILE: include/hw/ppc/xive_regs.h:87:
+ * context to reg*/
WARNING: Block comments use a leading /* on a separate line
#612: FILE: include/hw/ppc/xive_regs.h:89:
+#define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd
WARNING: Block comments use a trailing */ on a separate line
#613: FILE: include/hw/ppc/xive_regs.h:90:
+ * line */
WARNING: Block comments use a leading /* on a separate line
#615: FILE: include/hw/ppc/xive_regs.h:92:
+#define TM_SPC_ACK_HV_POOL_EL 0xc20 /* Store8 ack HV evt pool to even
WARNING: Block comments use a trailing */ on a separate line
#616: FILE: include/hw/ppc/xive_regs.h:93:
+ * line */
total: 0 errors, 26 warnings, 572 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 26/40: ppc/xive: introduce a simplified XIVE presenter...
Checking PATCH 27/40: ppc/xive: notify the CPU when the interrupt priority is more privileged...
Checking PATCH 28/40: spapr/xive: introduce a XIVE interrupt controller...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#60:
new file mode 100644
total: 0 errors, 1 warnings, 425 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 29/40: spapr/xive: use the VCPU id as a NVT identifier...
Checking PATCH 30/40: spapr-iommu: Always advertise the maximum possible DMA window size...
Checking PATCH 31/40: spapr: introduce a new machine IRQ backend for XIVE...
Checking PATCH 32/40: spapr: add hcalls support for the XIVE exploitation interrupt mode...
WARNING: Block comments use a leading /* on a separate line
#219: FILE: hw/intc/spapr_xive.c:551:
+#define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management
WARNING: Block comments use * on subsequent lines
#220: FILE: hw/intc/spapr_xive.c:552:
+#define SPAPR_XIVE_SRC_TRIGGER PPC_BIT(62) /* Trigger and management
+ on same page */
WARNING: Block comments use a trailing */ on a separate line
#220: FILE: hw/intc/spapr_xive.c:552:
+ on same page */
total: 0 errors, 3 warnings, 1034 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 33/40: spapr: add device tree support for the XIVE exploitation mode...
Checking PATCH 34/40: spapr: allocate the interrupt thread context under the CPU core...
Checking PATCH 35/40: spapr: extend the sPAPR IRQ backend for XICS migration...
Checking PATCH 36/40: spapr: add a 'reset' method to the sPAPR IRQ backend...
Checking PATCH 37/40: spapr: add an extra OV5 field to the sPAPR IRQ backend...
Checking PATCH 38/40: spapr: introduce an 'ic-mode' machine option...
Checking PATCH 39/40: spapr: change default CPU type to POWER9...
Checking PATCH 40/40: MAINTAINERS: PPC: add a XIVE section...
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20181221054606.22007-1-david@gibson.dropbear.id.au/testing.checkpatch/?type=message.
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