[Qemu-devel] [PULL v2 00/33] tcg patch queue
[PATCH v4 00/43] tcg patch queue
1
Now include a patch to address
1
Version 4: Drop the cpu_loop noreturn patch.
2
3
qemu-system-x86_64: /home/pm215/qemu/tcg/sparc/tcg-target.inc.c:319:
4
patch_reloc: Assertion `check_fit_ptr(value, 13)' failed.
5
6
I believe it was the change to bswap64 to use the constant pool more
7
often that exposed the latent problem.
8
9
Only re-posting the new patch.
10
2
11
3
12
r~
4
r~
13
5
14
6
15
The following changes since commit 58b1f0f21edcab13f78a376b1d90267626be1275:
7
The following changes since commit 4c9af1ea1457782cf0adb293179335ef6de942aa:
16
8
17
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging (2018-12-16 12:49:06 +0000)
9
gitlab-ci: Make more custom runner jobs manual, and don't allow failure (2021-09-14 17:03:03 +0100)
18
10
19
are available in the Git repository at:
11
are available in the Git repository at:
20
12
21
https://github.com/rth7680/qemu.git tags/pull-tcg-20181216
13
https://gitlab.com/rth7680/qemu.git tags/pull-tcg-20210914-4
22
14
23
for you to fetch changes up to b7c2cd08a6f68010ad27c9c0bf2fde02fb743a0e:
15
for you to fetch changes up to e028eada62dbfcba134ac5afdefc3aa343ae202f:
24
16
25
xxhash: match output against the original xxhash32 (2018-12-17 06:04:44 +0300)
17
tcg/arm: More use of the TCGReg enum (2021-09-14 12:00:21 -0700)
26
18
27
----------------------------------------------------------------
19
----------------------------------------------------------------
28
- Remove retranslation remenents
20
Fix translation race condition for user-only.
29
- Return success from patch_reloc
21
Fix tcg/i386 encoding for VPSLLVQ, VPSRLVQ.
30
- Preserve 32-bit values as zero-extended on x86_64
22
Fix tcg/arm tcg_out_vec_op signature.
31
- Make bswap during memory ops as optional
23
Fix tcg/ppc (32bit) build with clang.
32
- Cleanup xxhash
24
Remove dupluate TCG_KICK_PERIOD definition.
33
- Revert constant pooling for tcg/sparc/
25
Remove unused tcg_global_reg_new.
26
Restrict cpu_exec_interrupt and its callees to sysemu.
27
Cleanups for tcg/arm.
34
28
35
----------------------------------------------------------------
29
----------------------------------------------------------------
36
Alistair Francis (1):
30
Bin Meng (1):
37
tcg/mips: Improve the add2/sub2 command to use TCG_TARGET_REG_BITS
31
tcg: Remove tcg_global_reg_new defines
38
32
39
Emilio G. Cota (5):
33
Ilya Leoshkevich (3):
40
tcg: Drop nargs from tcg_op_insert_{before,after}
34
accel/tcg: Add DisasContextBase argument to translator_ld*
41
qht-bench: document -p flag
35
accel/tcg: Clear PAGE_WRITE before translation
42
exec: introduce qemu_xxhash{2,4,5,6,7}
36
accel/tcg/user-exec: Fix read-modify-write of code on s390 hosts
43
include: move exec/tb-hash-xx.h to qemu/xxhash.h
44
xxhash: match output against the original xxhash32
45
37
46
Richard Henderson (27):
38
Jose R. Ziviani (1):
47
target/sparc: Remove the constant pool
39
tcg/arm: Fix tcg_out_vec_op function signature
48
tcg/i386: Always use %ebp for TCG_AREG0
49
tcg/i386: Move TCG_REG_CALL_STACK from define to enum
50
tcg/aarch64: Remove reloc_pc26_atomic
51
tcg/aarch64: Fold away "noaddr" branch routines
52
tcg/arm: Remove reloc_pc24_atomic
53
tcg/arm: Fold away "noaddr" branch routines
54
tcg/ppc: Fold away "noaddr" branch routines
55
tcg/s390: Remove retranslation code
56
tcg/sparc: Remove retranslation code
57
tcg/mips: Remove retranslation code
58
tcg: Return success from patch_reloc
59
tcg/i386: Return false on failure from patch_reloc
60
tcg/aarch64: Return false on failure from patch_reloc
61
tcg/arm: Return false on failure from patch_reloc
62
tcg/ppc: Return false on failure from patch_reloc
63
tcg/s390x: Return false on failure from patch_reloc
64
tcg/i386: Propagate is64 to tcg_out_qemu_ld_direct
65
tcg/i386: Propagate is64 to tcg_out_qemu_ld_slow_path
66
tcg/i386: Implement INDEX_op_extr{lh}_i64_i32 for 32-bit guests
67
tcg/i386: Assume 32-bit values are zero-extended
68
tcg/i386: Precompute all guest_base parameters
69
tcg/i386: Add setup_guest_base_seg for FreeBSD
70
tcg: Clean up generic bswap32
71
tcg: Clean up generic bswap64
72
tcg/optimize: Optimize bswap
73
tcg: Add TCG_TARGET_HAS_MEMORY_BSWAP
74
40
75
include/exec/tb-hash.h | 4 +-
41
Luc Michel (1):
76
include/{exec/tb-hash-xx.h => qemu/xxhash.h} | 47 ++++--
42
accel/tcg: remove redundant TCG_KICK_PERIOD define
77
tcg/aarch64/tcg-target.h | 1 +
78
tcg/arm/tcg-target.h | 1 +
79
tcg/i386/tcg-target.h | 17 +--
80
tcg/mips/tcg-target.h | 1 +
81
tcg/ppc/tcg-target.h | 1 +
82
tcg/s390/tcg-target.h | 1 +
83
tcg/sparc/tcg-target.h | 1 +
84
tcg/tcg.h | 4 +-
85
tcg/tci/tcg-target.h | 2 +
86
tcg/aarch64/tcg-target.inc.c | 71 +++------
87
tcg/arm/tcg-target.inc.c | 55 +++----
88
tcg/i386/tcg-target.inc.c | 208 ++++++++++++--------------
89
tcg/mips/tcg-target.inc.c | 12 +-
90
tcg/optimize.c | 16 +-
91
tcg/ppc/tcg-target.inc.c | 60 ++++----
92
tcg/s390/tcg-target.inc.c | 45 +++---
93
tcg/sparc/tcg-target.inc.c | 58 ++------
94
tcg/tcg-op.c | 215 ++++++++++++++++++++-------
95
tcg/tcg.c | 18 +--
96
tcg/tci/tcg-target.inc.c | 3 +-
97
tests/qht-bench.c | 5 +-
98
util/qsp.c | 14 +-
99
24 files changed, 460 insertions(+), 400 deletions(-)
100
rename include/{exec/tb-hash-xx.h => qemu/xxhash.h} (73%)
101
43
44
Philippe Mathieu-Daudé (24):
45
target/avr: Remove pointless use of CONFIG_USER_ONLY definition
46
target/i386: Restrict sysemu-only fpu_helper helpers
47
target/i386: Simplify TARGET_X86_64 #ifdef'ry
48
target/xtensa: Restrict do_transaction_failed() to sysemu
49
accel/tcg: Rename user-mode do_interrupt hack as fake_user_interrupt
50
target/alpha: Restrict cpu_exec_interrupt() handler to sysemu
51
target/arm: Restrict cpu_exec_interrupt() handler to sysemu
52
target/cris: Restrict cpu_exec_interrupt() handler to sysemu
53
target/hppa: Restrict cpu_exec_interrupt() handler to sysemu
54
target/i386: Restrict cpu_exec_interrupt() handler to sysemu
55
target/i386: Move x86_cpu_exec_interrupt() under sysemu/ folder
56
target/m68k: Restrict cpu_exec_interrupt() handler to sysemu
57
target/microblaze: Restrict cpu_exec_interrupt() handler to sysemu
58
target/mips: Restrict cpu_exec_interrupt() handler to sysemu
59
target/nios2: Restrict cpu_exec_interrupt() handler to sysemu
60
target/openrisc: Restrict cpu_exec_interrupt() handler to sysemu
61
target/ppc: Restrict cpu_exec_interrupt() handler to sysemu
62
target/riscv: Restrict cpu_exec_interrupt() handler to sysemu
63
target/sh4: Restrict cpu_exec_interrupt() handler to sysemu
64
target/sparc: Restrict cpu_exec_interrupt() handler to sysemu
65
target/rx: Restrict cpu_exec_interrupt() handler to sysemu
66
target/xtensa: Restrict cpu_exec_interrupt() handler to sysemu
67
accel/tcg: Restrict TCGCPUOps::cpu_exec_interrupt() to sysemu
68
user: Remove cpu_get_pic_interrupt() stubs
69
70
Richard Henderson (13):
71
tcg/i386: Split P_VEXW from P_REXW
72
tcg/ppc: Replace TCG_TARGET_CALL_DARWIN with _CALL_DARWIN
73
tcg/ppc: Ensure _CALL_SYSV is set for 32-bit ELF
74
tcg/arm: Remove fallback definition of __ARM_ARCH
75
tcg/arm: Standardize on tcg_out_<branch>_{reg,imm}
76
tcg/arm: Simplify use_armv5t_instructions
77
tcg/arm: Support armv4t in tcg_out_goto and tcg_out_call
78
tcg/arm: Split out tcg_out_ldstm
79
tcg/arm: Simplify usage of encode_imm
80
tcg/arm: Drop inline markers
81
tcg/arm: Give enum arm_cond_code_e a typedef and use it
82
tcg/arm: More use of the ARMInsn enum
83
tcg/arm: More use of the TCGReg enum
84
85
include/exec/translate-all.h | 1 +
86
include/exec/translator.h | 44 +--
87
include/hw/core/tcg-cpu-ops.h | 26 +-
88
include/tcg/tcg-op.h | 2 -
89
target/alpha/cpu.h | 2 +-
90
target/arm/arm_ldst.h | 12 +-
91
target/arm/cpu.h | 3 +-
92
target/cris/cpu.h | 2 +-
93
target/hppa/cpu.h | 4 +-
94
target/i386/cpu.h | 3 +
95
target/i386/tcg/helper-tcg.h | 2 +
96
target/m68k/cpu.h | 2 +
97
target/microblaze/cpu.h | 2 +
98
target/mips/tcg/tcg-internal.h | 5 +-
99
target/openrisc/cpu.h | 5 +-
100
target/ppc/cpu.h | 4 +-
101
target/riscv/cpu.h | 2 +-
102
target/rx/cpu.h | 2 +
103
target/sh4/cpu.h | 4 +-
104
target/xtensa/cpu.h | 2 +
105
tcg/arm/tcg-target.h | 27 +-
106
accel/tcg/cpu-exec.c | 14 +-
107
accel/tcg/tcg-accel-ops-rr.c | 2 -
108
accel/tcg/translate-all.c | 59 ++--
109
accel/tcg/translator.c | 39 +++
110
accel/tcg/user-exec.c | 48 ++-
111
bsd-user/i386/target_arch_cpu.c | 5 -
112
bsd-user/x86_64/target_arch_cpu.c | 5 -
113
linux-user/main.c | 7 -
114
target/alpha/cpu.c | 2 +-
115
target/alpha/helper.c | 5 +-
116
target/alpha/translate.c | 2 +-
117
target/arm/cpu.c | 7 +-
118
target/arm/cpu_tcg.c | 6 +-
119
target/arm/translate-a64.c | 2 +-
120
target/arm/translate.c | 9 +-
121
target/avr/cpu.c | 3 -
122
target/cris/cpu.c | 4 +-
123
target/cris/helper.c | 17 +-
124
target/hexagon/translate.c | 3 +-
125
target/hppa/cpu.c | 2 +-
126
target/hppa/int_helper.c | 7 +-
127
target/hppa/translate.c | 5 +-
128
target/i386/tcg/seg_helper.c | 74 +----
129
target/i386/tcg/sysemu/seg_helper.c | 62 ++++
130
target/i386/tcg/tcg-cpu.c | 8 +-
131
target/i386/tcg/translate.c | 10 +-
132
target/m68k/cpu.c | 2 +-
133
target/m68k/op_helper.c | 16 +-
134
target/m68k/translate.c | 2 +-
135
target/microblaze/cpu.c | 2 +-
136
target/microblaze/helper.c | 13 +-
137
target/mips/cpu.c | 2 +-
138
target/mips/tcg/exception.c | 18 --
139
target/mips/tcg/sysemu/tlb_helper.c | 18 ++
140
target/mips/tcg/translate.c | 8 +-
141
target/mips/tcg/user/tlb_helper.c | 5 -
142
target/nios2/cpu.c | 5 +-
143
target/openrisc/cpu.c | 2 +-
144
target/openrisc/interrupt.c | 2 -
145
target/openrisc/translate.c | 2 +-
146
target/ppc/cpu_init.c | 2 +-
147
target/ppc/excp_helper.c | 21 +-
148
target/ppc/translate.c | 5 +-
149
target/riscv/cpu.c | 2 +-
150
target/riscv/cpu_helper.c | 5 -
151
target/riscv/translate.c | 5 +-
152
target/rx/cpu.c | 2 +-
153
target/rx/helper.c | 4 +
154
target/s390x/tcg/translate.c | 16 +-
155
target/sh4/cpu.c | 2 +-
156
target/sh4/helper.c | 9 +-
157
target/sh4/translate.c | 4 +-
158
target/sparc/cpu.c | 4 +-
159
target/sparc/translate.c | 2 +-
160
target/xtensa/cpu.c | 2 +-
161
target/xtensa/exc_helper.c | 7 +-
162
target/xtensa/translate.c | 5 +-
163
target/mips/tcg/micromips_translate.c.inc | 2 +-
164
target/mips/tcg/mips16e_translate.c.inc | 4 +-
165
target/mips/tcg/nanomips_translate.c.inc | 4 +-
166
tcg/arm/tcg-target.c.inc | 517 ++++++++++++++++--------------
167
tcg/i386/tcg-target.c.inc | 13 +-
168
tcg/ppc/tcg-target.c.inc | 25 +-
169
target/openrisc/meson.build | 6 +-
170
85 files changed, 700 insertions(+), 628 deletions(-)
171
diff view generated by jsdifflib
[Qemu-devel] [PULL v2 01/33] target/sparc: Remove the constant pool
Deleted patch
1
Partially reverts ab20bdc1162. The 14-bit displacement that we
2
allowed to reach the constant pool is not always sufficient.
3
Retain the tb-relative addressing, as that is how most return
4
values from the tb are computed.
5
1
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
---
8
tcg/sparc/tcg-target.inc.c | 47 ++++++++------------------------------
9
1 file changed, 9 insertions(+), 38 deletions(-)
10
11
diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.inc.c
12
index XXXXXXX..XXXXXXX 100644
13
--- a/tcg/sparc/tcg-target.inc.c
14
+++ b/tcg/sparc/tcg-target.inc.c
15
@@ -XXX,XX +XXX,XX @@ static void patch_reloc(tcg_insn_unit *code_ptr, int type,
16
insn &= ~INSN_OFF19(-1);
17
insn |= INSN_OFF19(pcrel);
18
break;
19
- case R_SPARC_13:
20
- /* Note that we're abusing this reloc type for our own needs. */
21
- if (!check_fit_ptr(value, 13)) {
22
- int adj = (value > 0 ? 0xff8 : -0x1000);
23
- value -= adj;
24
- assert(check_fit_ptr(value, 13));
25
- *code_ptr++ = (ARITH_ADD | INSN_RD(TCG_REG_T2)
26
- | INSN_RS1(TCG_REG_TB) | INSN_IMM13(adj));
27
- insn ^= INSN_RS1(TCG_REG_TB) ^ INSN_RS1(TCG_REG_T2);
28
- }
29
- insn &= ~INSN_IMM13(-1);
30
- insn |= INSN_IMM13(value);
31
- break;
32
- case R_SPARC_32:
33
- /* Note that we're abusing this reloc type for our own needs. */
34
- code_ptr[0] = deposit32(code_ptr[0], 0, 22, value >> 10);
35
- code_ptr[1] = deposit32(code_ptr[1], 0, 10, value);
36
- return;
37
default:
38
g_assert_not_reached();
39
}
40
@@ -XXX,XX +XXX,XX @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
41
return;
42
}
43
44
+ /* A 13-bit constant relative to the TB. */
45
+ if (!in_prologue && USE_REG_TB) {
46
+ test = arg - (uintptr_t)s->code_gen_ptr;
47
+ if (check_fit_ptr(test, 13)) {
48
+ tcg_out_arithi(s, ret, TCG_REG_TB, test, ARITH_ADD);
49
+ return;
50
+ }
51
+ }
52
+
53
/* A 32-bit constant, or 32-bit zero-extended to 64-bits. */
54
if (type == TCG_TYPE_I32 || arg == (uint32_t)arg) {
55
tcg_out_sethi(s, ret, arg);
56
@@ -XXX,XX +XXX,XX @@ static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret,
57
return;
58
}
59
60
- if (!in_prologue) {
61
- if (USE_REG_TB) {
62
- intptr_t diff = arg - (uintptr_t)s->code_gen_ptr;
63
- if (check_fit_ptr(diff, 13)) {
64
- tcg_out_arithi(s, ret, TCG_REG_TB, diff, ARITH_ADD);
65
- } else {
66
- new_pool_label(s, arg, R_SPARC_13, s->code_ptr,
67
- -(intptr_t)s->code_gen_ptr);
68
- tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(TCG_REG_TB));
69
- /* May be used to extend the 13-bit range in patch_reloc. */
70
- tcg_out32(s, NOP);
71
- }
72
- } else {
73
- new_pool_label(s, arg, R_SPARC_32, s->code_ptr, 0);
74
- tcg_out_sethi(s, ret, 0);
75
- tcg_out32(s, LDX | INSN_RD(ret) | INSN_RS1(ret) | INSN_IMM13(0));
76
- }
77
- return;
78
- }
79
-
80
/* A 64-bit constant decomposed into 2 32-bit pieces. */
81
if (check_fit_i32(lo, 13)) {
82
hi = (arg - lo) >> 32;
83
--
84
2.17.2
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86
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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