[Qemu-devel] [PULL 00/37] target-arm queue
[Qemu-devel] [PULL 00/29] target-arm queue
1
First target-arm pullreq of the 4.0 series; most of this
1
First arm pullreq of 4.2...
2
is Mao's cleanups that finally let us drop sysbus::init;
3
the most interesting user-visible feature is RTH's patches
4
adding some v8.1 and v8.2 architecture features.
5
2
6
thanks
3
thanks
7
-- PMM
4
-- PMM
8
5
9
The following changes since commit 6145a6d84b3bf0f25935b88543febe076c61b0f4:
6
The following changes since commit 27608c7c66bd923eb5e5faab80e795408cbe2b51:
10
7
11
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20181212' into staging (2018-12-13 13:06:09 +0000)
8
Merge remote-tracking branch 'remotes/dgilbert/tags/pull-migration-20190814a' into staging (2019-08-16 12:00:18 +0100)
12
9
13
are available in the Git repository at:
10
are available in the Git repository at:
14
11
15
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20181213
12
https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20190816
16
13
17
for you to fetch changes up to 2d7137c10fafefe40a0a049ff8a7bd78b66e661f:
14
for you to fetch changes up to 664b7e3b97d6376f3329986c465b3782458b0f8b:
18
15
19
target/arm: Implement the ARMv8.1-LOR extension (2018-12-13 14:41:24 +0000)
16
target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word (2019-08-16 14:02:53 +0100)
20
17
21
----------------------------------------------------------------
18
----------------------------------------------------------------
22
target-arm queue:
19
target-arm queue:
23
* Convert various devices from sysbus init to instance_init
20
* target/arm: generate a custom MIDR for -cpu max
24
* Remove the now unused sysbus init support entirely
21
* hw/misc/zynq_slcr: refactor to use standard register definition
25
* Allow AArch64 processors to boot from a kernel placed over 4GB
22
* Set ENET_BD_BDU in I.MX FEC controller
26
* hw: arm: musicpal: drop TYPE_WM8750 in object_property_set_link()
23
* target/arm: Fix routing of singlestep exceptions
27
* versal: minor fixes to virtio-mmio instantation
24
* refactor a32/t32 decoder handling of PC
28
* arm: Implement the ARMv8.1-HPD extension
25
* minor optimisations/cleanups of some a32/t32 codegen
29
* arm: Implement the ARMv8.2-AA32HPD extension
26
* target/arm/cpu64: Ensure kvm really supports aarch64=off
30
* arm: Implement the ARMv8.1-LOR extension (as the trivial
27
* target/arm/cpu: Ensure we can use the pmu with kvm
31
"no limited ordering regions provided" minimum)
28
* target/arm: Minor cleanups preparatory to KVM SVE support
32
29
33
----------------------------------------------------------------
30
----------------------------------------------------------------
34
Edgar E. Iglesias (4):
31
Aaron Hill (1):
35
hw/arm: versal: Remove bogus virtio-mmio creation
32
Set ENET_BD_BDU in I.MX FEC controller
36
hw/arm: versal: Reduce number of virtio-mmio instances
37
hw/arm: versal: Use IRQs 111 - 118 for virtio-mmio
38
hw/arm: versal: Correct the nr of IRQs to 192
39
33
40
Li Qiang (1):
34
Alex Bennée (1):
41
hw: arm: musicpal: drop TYPE_WM8750 in object_property_set_link()
35
target/arm: generate a custom MIDR for -cpu max
42
36
43
Mao Zhongyi (21):
37
Andrew Jones (6):
44
musicpal: Convert sysbus init function to realize function
38
target/arm/cpu64: Ensure kvm really supports aarch64=off
45
block/noenand: Convert sysbus init function to realize function
39
target/arm/cpu: Ensure we can use the pmu with kvm
46
char/grlib_apbuart: Convert sysbus init function to realize function
40
target/arm/helper: zcr: Add build bug next to value range assumption
47
core/empty_slot: Convert sysbus init function to realize function
41
target/arm/cpu: Use div-round-up to determine predicate register array size
48
display/g364fb: Convert sysbus init function to realize function
42
target/arm/kvm64: Fix error returns
49
dma/puv3_dma: Convert sysbus init function to realize function
43
target/arm/kvm64: Move the get/put of fpsimd registers out
50
gpio/puv3_gpio: Convert sysbus init function to realize function
51
milkymist-softusb: Convert sysbus init function to realize function
52
input/pl050: Convert sysbus init function to realize function
53
intc/puv3_intc: Convert sysbus init function to realize function
54
milkymist-hpdmc: Convert sysbus init function to realize function
55
milkymist-pfpu: Convert sysbus init function to realize function
56
puv3_pm.c: Convert sysbus init function to realize function
57
nvram/ds1225y: Convert sysbus init function to realize function
58
pci-bridge/dec: Convert sysbus init function to realize function
59
timer/etraxfs_timer: Convert sysbus init function to realize function
60
timer/grlib_gptimer: Convert sysbus init function to realize function
61
timer/puv3_ost: Convert sysbus init function to realize function
62
usb/tusb6010: Convert sysbus init function to realize function
63
xen_backend: remove xen_sysdev_init() function
64
core/sysbus: remove the SysBusDeviceClass::init path
65
44
66
Peter Maydell (1):
45
Damien Hedde (1):
67
target/arm: Move id_aa64mmfr* to ARMISARegisters
46
hw/misc/zynq_slcr: use standard register definition
68
47
69
Ricardo Perez Blanco (1):
48
Peter Maydell (2):
70
Allow AArch64 processors to boot from a kernel placed over 4GB
49
target/arm: Factor out 'generate singlestep exception' function
50
target/arm: Fix routing of singlestep exceptions
71
51
72
Richard Henderson (9):
52
Richard Henderson (18):
73
target/arm: Add HCR_EL2 bits up to ARMv8.5
53
target/arm: Pass in pc to thumb_insn_is_16bit
74
target/arm: Add SCR_EL3 bits up to ARMv8.5
54
target/arm: Introduce pc_curr
75
target/arm: Fix HCR_EL2.TGE check in arm_phys_excp_target_el
55
target/arm: Introduce read_pc
76
target/arm: Tidy scr_write
56
target/arm: Introduce add_reg_for_lit
77
target/arm: Implement the ARMv8.1-HPD extension
57
target/arm: Remove redundant s->pc & ~1
78
target/arm: Implement the ARMv8.2-AA32HPD extension
58
target/arm: Replace s->pc with s->base.pc_next
79
target/arm: Introduce arm_hcr_el2_eff
59
target/arm: Replace offset with pc in gen_exception_insn
80
target/arm: Use arm_hcr_el2_eff more places
60
target/arm: Replace offset with pc in gen_exception_internal_insn
81
target/arm: Implement the ARMv8.1-LOR extension
61
target/arm: Remove offset argument to gen_exception_bkpt_insn
62
target/arm: Use unallocated_encoding for aarch32
63
target/arm: Remove helper_double_saturate
64
target/arm: Use tcg_gen_extract_i32 for shifter_out_im
65
target/arm: Use tcg_gen_deposit_i32 for PKHBT, PKHTB
66
target/arm: Remove redundant shift tests
67
target/arm: Use ror32 instead of open-coding the operation
68
target/arm: Use tcg_gen_rotri_i32 for gen_swap_half
69
target/arm: Simplify SMMLA, SMMLAR, SMMLS, SMMLSR
70
target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word
82
71
83
include/hw/arm/xlnx-versal.h | 8 +-
72
target/arm/cpu.h | 13 +-
84
include/hw/sysbus.h | 3 -
73
target/arm/helper.h | 1 -
85
target/arm/cpu.h | 141 ++++++++++++++++-----------
74
target/arm/kvm_arm.h | 28 ++
86
target/arm/internals.h | 3 +-
75
target/arm/translate-a64.h | 4 +-
87
hw/arm/boot.c | 35 ++++---
76
target/arm/translate.h | 39 ++-
88
hw/arm/musicpal.c | 11 +--
77
hw/misc/zynq_slcr.c | 450 ++++++++++++++++----------------
89
hw/arm/xlnx-versal-virt.c | 7 +-
78
hw/net/imx_fec.c | 4 +
90
hw/block/onenand.c | 16 ++--
79
target/arm/cpu.c | 30 ++-
91
hw/char/grlib_apbuart.c | 12 +--
80
target/arm/cpu64.c | 31 ++-
92
hw/core/empty_slot.c | 9 +-
81
target/arm/helper.c | 7 +
93
hw/core/sysbus.c | 15 +--
82
target/arm/kvm.c | 7 +
94
hw/display/g364fb.c | 9 +-
83
target/arm/kvm64.c | 161 +++++++-----
95
hw/dma/puv3_dma.c | 10 +-
84
target/arm/op_helper.c | 15 --
96
hw/gpio/puv3_gpio.c | 29 +++---
85
target/arm/translate-a64.c | 130 ++++------
97
hw/input/milkymist-softusb.c | 16 ++--
86
target/arm/translate-vfp.inc.c | 45 +---
98
hw/input/pl050.c | 11 +--
87
target/arm/translate.c | 572 +++++++++++++++++------------------------
99
hw/intc/arm_gicv3_cpuif.c | 21 ++--
88
16 files changed, 771 insertions(+), 766 deletions(-)
100
hw/intc/puv3_intc.c | 11 +--
101
hw/misc/milkymist-hpdmc.c | 9 +-
102
hw/misc/milkymist-pfpu.c | 12 +--
103
hw/misc/puv3_pm.c | 10 +-
104
hw/nvram/ds1225y.c | 12 +--
105
hw/pci-bridge/dec.c | 12 +--
106
hw/timer/etraxfs_timer.c | 14 +--
107
hw/timer/grlib_gptimer.c | 11 +--
108
hw/timer/puv3_ost.c | 13 ++-
109
hw/usb/tusb6010.c | 8 +-
110
hw/xen/xen_backend.c | 7 --
111
target/arm/cpu.c | 4 +
112
target/arm/cpu64.c | 11 ++-
113
target/arm/helper.c | 222 ++++++++++++++++++++++++++++++++++++-------
114
target/arm/kvm64.c | 4 +
115
target/arm/op_helper.c | 14 ++-
116
target/arm/translate-a64.c | 12 +++
117
34 files changed, 456 insertions(+), 286 deletions(-)
118
89
diff view generated by jsdifflib
[Qemu-devel] [PULL 28/37] target/arm: Move id_aa64mmfr* to ARMISARegisters
[Qemu-devel] [PULL 01/29] target/arm: generate a custom MIDR for -cpu max
1
At the same time, define the fields for these registers,
1
From: Alex Bennée <alex.bennee@linaro.org>
2
and use those defines in arm_pamax().
3
2
4
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3
While most features are now detected by probing the ID_* registers
5
Message-id: 20181203203839.757-2-richard.henderson@linaro.org
4
kernels can (and do) use MIDR_EL1 for working out of they have to
5
apply errata. This can trip up warnings in the kernel as it tries to
6
work out if it should apply workarounds to features that don't
7
actually exist in the reported CPU type.
8
9
Avoid this problem by synthesising our own MIDR value.
10
11
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
[PMM: fixed up typo (s/achf/ahcf/) belatedly spotted by RTH]
13
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
14
Message-id: 20190726113950.7499-1-alex.bennee@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
16
---
10
target/arm/cpu.h | 26 ++++++++++++++++++++++++--
17
target/arm/cpu.h | 6 ++++++
11
target/arm/internals.h | 3 ++-
18
target/arm/cpu64.c | 19 +++++++++++++++++++
12
target/arm/cpu64.c | 6 +++---
19
2 files changed, 25 insertions(+)
13
target/arm/helper.c | 4 ++--
14
target/arm/kvm64.c | 4 ++++
15
5 files changed, 35 insertions(+), 8 deletions(-)
16
20
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
21
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
index XXXXXXX..XXXXXXX 100644
22
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.h
23
--- a/target/arm/cpu.h
20
+++ b/target/arm/cpu.h
24
+++ b/target/arm/cpu.h
21
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
25
@@ -XXX,XX +XXX,XX @@ FIELD(V7M_FPCCR, ASPEN, 31, 1)
22
uint64_t id_aa64isar1;
26
/*
23
uint64_t id_aa64pfr0;
27
* System register ID fields.
24
uint64_t id_aa64pfr1;
28
*/
25
+ uint64_t id_aa64mmfr0;
29
+FIELD(MIDR_EL1, REVISION, 0, 4)
26
+ uint64_t id_aa64mmfr1;
30
+FIELD(MIDR_EL1, PARTNUM, 4, 12)
27
} isar;
31
+FIELD(MIDR_EL1, ARCHITECTURE, 16, 4)
28
uint32_t midr;
32
+FIELD(MIDR_EL1, VARIANT, 20, 4)
29
uint32_t revidr;
33
+FIELD(MIDR_EL1, IMPLEMENTER, 24, 8)
30
@@ -XXX,XX +XXX,XX @@ struct ARMCPU {
31
uint64_t id_aa64dfr1;
32
uint64_t id_aa64afr0;
33
uint64_t id_aa64afr1;
34
- uint64_t id_aa64mmfr0;
35
- uint64_t id_aa64mmfr1;
36
uint32_t dbgdidr;
37
uint32_t clidr;
38
uint64_t mp_affinity; /* MP ID without feature bits */
39
@@ -XXX,XX +XXX,XX @@ FIELD(ID_AA64PFR0, GIC, 24, 4)
40
FIELD(ID_AA64PFR0, RAS, 28, 4)
41
FIELD(ID_AA64PFR0, SVE, 32, 4)
42
43
+FIELD(ID_AA64MMFR0, PARANGE, 0, 4)
44
+FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4)
45
+FIELD(ID_AA64MMFR0, BIGEND, 8, 4)
46
+FIELD(ID_AA64MMFR0, SNSMEM, 12, 4)
47
+FIELD(ID_AA64MMFR0, BIGENDEL0, 16, 4)
48
+FIELD(ID_AA64MMFR0, TGRAN16, 20, 4)
49
+FIELD(ID_AA64MMFR0, TGRAN64, 24, 4)
50
+FIELD(ID_AA64MMFR0, TGRAN4, 28, 4)
51
+FIELD(ID_AA64MMFR0, TGRAN16_2, 32, 4)
52
+FIELD(ID_AA64MMFR0, TGRAN64_2, 36, 4)
53
+FIELD(ID_AA64MMFR0, TGRAN4_2, 40, 4)
54
+FIELD(ID_AA64MMFR0, EXS, 44, 4)
55
+
34
+
56
+FIELD(ID_AA64MMFR1, HAFDBS, 0, 4)
35
FIELD(ID_ISAR0, SWAP, 0, 4)
57
+FIELD(ID_AA64MMFR1, VMIDBITS, 4, 4)
36
FIELD(ID_ISAR0, BITCOUNT, 4, 4)
58
+FIELD(ID_AA64MMFR1, VH, 8, 4)
37
FIELD(ID_ISAR0, BITFIELD, 8, 4)
59
+FIELD(ID_AA64MMFR1, HPDS, 12, 4)
60
+FIELD(ID_AA64MMFR1, LO, 16, 4)
61
+FIELD(ID_AA64MMFR1, PAN, 20, 4)
62
+FIELD(ID_AA64MMFR1, SPECSEI, 24, 4)
63
+FIELD(ID_AA64MMFR1, XNX, 28, 4)
64
+
65
QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= R_V7M_CSSELR_INDEX_MASK);
66
67
/* If adding a feature bit which corresponds to a Linux ELF
68
diff --git a/target/arm/internals.h b/target/arm/internals.h
69
index XXXXXXX..XXXXXXX 100644
70
--- a/target/arm/internals.h
71
+++ b/target/arm/internals.h
72
@@ -XXX,XX +XXX,XX @@ static inline unsigned int arm_pamax(ARMCPU *cpu)
73
[4] = 44,
74
[5] = 48,
75
};
76
- unsigned int parange = extract32(cpu->id_aa64mmfr0, 0, 4);
77
+ unsigned int parange =
78
+ FIELD_EX64(cpu->isar.id_aa64mmfr0, ID_AA64MMFR0, PARANGE);
79
80
/* id_aa64mmfr0 is a read-only register so values outside of the
81
* supported mappings can be considered an implementation error. */
82
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
38
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
83
index XXXXXXX..XXXXXXX 100644
39
index XXXXXXX..XXXXXXX 100644
84
--- a/target/arm/cpu64.c
40
--- a/target/arm/cpu64.c
85
+++ b/target/arm/cpu64.c
41
+++ b/target/arm/cpu64.c
86
@@ -XXX,XX +XXX,XX @@ static void aarch64_a57_initfn(Object *obj)
42
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
87
cpu->pmceid0 = 0x00000000;
43
uint32_t u;
88
cpu->pmceid1 = 0x00000000;
44
aarch64_a57_initfn(obj);
89
cpu->isar.id_aa64isar0 = 0x00011120;
45
90
- cpu->id_aa64mmfr0 = 0x00001124;
46
+ /*
91
+ cpu->isar.id_aa64mmfr0 = 0x00001124;
47
+ * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
92
cpu->dbgdidr = 0x3516d000;
48
+ * one and try to apply errata workarounds or use impdef features we
93
cpu->clidr = 0x0a200023;
49
+ * don't provide.
94
cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
50
+ * An IMPLEMENTER field of 0 means "reserved for software use";
95
@@ -XXX,XX +XXX,XX @@ static void aarch64_a53_initfn(Object *obj)
51
+ * ARCHITECTURE must be 0xf indicating "v7 or later, check ID registers
96
cpu->isar.id_aa64pfr0 = 0x00002222;
52
+ * to see which features are present";
97
cpu->id_aa64dfr0 = 0x10305106;
53
+ * the VARIANT, PARTNUM and REVISION fields are all implementation
98
cpu->isar.id_aa64isar0 = 0x00011120;
54
+ * defined and we choose to define PARTNUM just in case guest
99
- cpu->id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
55
+ * code needs to distinguish this QEMU CPU from other software
100
+ cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
56
+ * implementations, though this shouldn't be needed.
101
cpu->dbgdidr = 0x3516d000;
57
+ */
102
cpu->clidr = 0x0a200023;
58
+ t = FIELD_DP64(0, MIDR_EL1, IMPLEMENTER, 0);
103
cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
59
+ t = FIELD_DP64(t, MIDR_EL1, ARCHITECTURE, 0xf);
104
@@ -XXX,XX +XXX,XX @@ static void aarch64_a72_initfn(Object *obj)
60
+ t = FIELD_DP64(t, MIDR_EL1, PARTNUM, 'Q');
105
cpu->pmceid0 = 0x00000000;
61
+ t = FIELD_DP64(t, MIDR_EL1, VARIANT, 0);
106
cpu->pmceid1 = 0x00000000;
62
+ t = FIELD_DP64(t, MIDR_EL1, REVISION, 0);
107
cpu->isar.id_aa64isar0 = 0x00011120;
63
+ cpu->midr = t;
108
- cpu->id_aa64mmfr0 = 0x00001124;
64
+
109
+ cpu->isar.id_aa64mmfr0 = 0x00001124;
65
t = cpu->isar.id_aa64isar0;
110
cpu->dbgdidr = 0x3516d000;
66
t = FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */
111
cpu->clidr = 0x0a200023;
67
t = FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1);
112
cpu->ccsidr[0] = 0x701fe00a; /* 32KB L1 dcache */
113
diff --git a/target/arm/helper.c b/target/arm/helper.c
114
index XXXXXXX..XXXXXXX 100644
115
--- a/target/arm/helper.c
116
+++ b/target/arm/helper.c
117
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
118
{ .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
119
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
120
.access = PL1_R, .type = ARM_CP_CONST,
121
- .resetvalue = cpu->id_aa64mmfr0 },
122
+ .resetvalue = cpu->isar.id_aa64mmfr0 },
123
{ .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
124
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
125
.access = PL1_R, .type = ARM_CP_CONST,
126
- .resetvalue = cpu->id_aa64mmfr1 },
127
+ .resetvalue = cpu->isar.id_aa64mmfr1 },
128
{ .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
129
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
130
.access = PL1_R, .type = ARM_CP_CONST,
131
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
132
index XXXXXXX..XXXXXXX 100644
133
--- a/target/arm/kvm64.c
134
+++ b/target/arm/kvm64.c
135
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
136
ARM64_SYS_REG(3, 0, 0, 6, 0));
137
err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1,
138
ARM64_SYS_REG(3, 0, 0, 6, 1));
139
+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr0,
140
+ ARM64_SYS_REG(3, 0, 0, 7, 0));
141
+ err |= read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64mmfr1,
142
+ ARM64_SYS_REG(3, 0, 0, 7, 1));
143
144
/*
145
* Note that if AArch32 support is not present in the host,
146
--
68
--
147
2.19.2
69
2.20.1
148
70
149
71
diff view generated by jsdifflib
[Qemu-devel] [PULL 25/37] hw/arm: versal: Reduce number of virtio-mmio instances
[Qemu-devel] [PULL 02/29] hw/misc/zynq_slcr: use standard register definition
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Damien Hedde <damien.hedde@greensocs.com>
2
2
3
Reduce number of virtio-mmio instances. This is in preparation
3
Replace the zynq_slcr registers enum and macros using the
4
for correcting the interrupt setup for Versal.
4
hw/registerfields.h macros.
5
5
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6
Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
8
Message-id: 20181129163655.20370-3-edgar.iglesias@gmail.com
9
Message-id: 20190729145654.14644-30-damien.hedde@greensocs.com
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
11
---
11
hw/arm/xlnx-versal-virt.c | 2 +-
12
hw/misc/zynq_slcr.c | 450 ++++++++++++++++++++++----------------------
12
1 file changed, 1 insertion(+), 1 deletion(-)
13
1 file changed, 225 insertions(+), 225 deletions(-)
13
14
14
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
15
diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
15
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
16
--- a/hw/arm/xlnx-versal-virt.c
17
--- a/hw/misc/zynq_slcr.c
17
+++ b/hw/arm/xlnx-versal-virt.c
18
+++ b/hw/misc/zynq_slcr.c
18
@@ -XXX,XX +XXX,XX @@ static void *versal_virt_get_dtb(const struct arm_boot_info *binfo,
19
@@ -XXX,XX +XXX,XX @@
19
return board->fdt;
20
#include "sysemu/sysemu.h"
21
#include "qemu/log.h"
22
#include "qemu/module.h"
23
+#include "hw/registerfields.h"
24
25
#ifndef ZYNQ_SLCR_ERR_DEBUG
26
#define ZYNQ_SLCR_ERR_DEBUG 0
27
@@ -XXX,XX +XXX,XX @@
28
#define XILINX_LOCK_KEY 0x767b
29
#define XILINX_UNLOCK_KEY 0xdf0d
30
31
-#define R_PSS_RST_CTRL_SOFT_RST 0x1
32
+REG32(SCL, 0x000)
33
+REG32(LOCK, 0x004)
34
+REG32(UNLOCK, 0x008)
35
+REG32(LOCKSTA, 0x00c)
36
37
-enum {
38
- SCL = 0x000 / 4,
39
- LOCK,
40
- UNLOCK,
41
- LOCKSTA,
42
+REG32(ARM_PLL_CTRL, 0x100)
43
+REG32(DDR_PLL_CTRL, 0x104)
44
+REG32(IO_PLL_CTRL, 0x108)
45
+REG32(PLL_STATUS, 0x10c)
46
+REG32(ARM_PLL_CFG, 0x110)
47
+REG32(DDR_PLL_CFG, 0x114)
48
+REG32(IO_PLL_CFG, 0x118)
49
50
- ARM_PLL_CTRL = 0x100 / 4,
51
- DDR_PLL_CTRL,
52
- IO_PLL_CTRL,
53
- PLL_STATUS,
54
- ARM_PLL_CFG,
55
- DDR_PLL_CFG,
56
- IO_PLL_CFG,
57
-
58
- ARM_CLK_CTRL = 0x120 / 4,
59
- DDR_CLK_CTRL,
60
- DCI_CLK_CTRL,
61
- APER_CLK_CTRL,
62
- USB0_CLK_CTRL,
63
- USB1_CLK_CTRL,
64
- GEM0_RCLK_CTRL,
65
- GEM1_RCLK_CTRL,
66
- GEM0_CLK_CTRL,
67
- GEM1_CLK_CTRL,
68
- SMC_CLK_CTRL,
69
- LQSPI_CLK_CTRL,
70
- SDIO_CLK_CTRL,
71
- UART_CLK_CTRL,
72
- SPI_CLK_CTRL,
73
- CAN_CLK_CTRL,
74
- CAN_MIOCLK_CTRL,
75
- DBG_CLK_CTRL,
76
- PCAP_CLK_CTRL,
77
- TOPSW_CLK_CTRL,
78
+REG32(ARM_CLK_CTRL, 0x120)
79
+REG32(DDR_CLK_CTRL, 0x124)
80
+REG32(DCI_CLK_CTRL, 0x128)
81
+REG32(APER_CLK_CTRL, 0x12c)
82
+REG32(USB0_CLK_CTRL, 0x130)
83
+REG32(USB1_CLK_CTRL, 0x134)
84
+REG32(GEM0_RCLK_CTRL, 0x138)
85
+REG32(GEM1_RCLK_CTRL, 0x13c)
86
+REG32(GEM0_CLK_CTRL, 0x140)
87
+REG32(GEM1_CLK_CTRL, 0x144)
88
+REG32(SMC_CLK_CTRL, 0x148)
89
+REG32(LQSPI_CLK_CTRL, 0x14c)
90
+REG32(SDIO_CLK_CTRL, 0x150)
91
+REG32(UART_CLK_CTRL, 0x154)
92
+REG32(SPI_CLK_CTRL, 0x158)
93
+REG32(CAN_CLK_CTRL, 0x15c)
94
+REG32(CAN_MIOCLK_CTRL, 0x160)
95
+REG32(DBG_CLK_CTRL, 0x164)
96
+REG32(PCAP_CLK_CTRL, 0x168)
97
+REG32(TOPSW_CLK_CTRL, 0x16c)
98
99
#define FPGA_CTRL_REGS(n, start) \
100
- FPGA ## n ## _CLK_CTRL = (start) / 4, \
101
- FPGA ## n ## _THR_CTRL, \
102
- FPGA ## n ## _THR_CNT, \
103
- FPGA ## n ## _THR_STA,
104
- FPGA_CTRL_REGS(0, 0x170)
105
- FPGA_CTRL_REGS(1, 0x180)
106
- FPGA_CTRL_REGS(2, 0x190)
107
- FPGA_CTRL_REGS(3, 0x1a0)
108
+ REG32(FPGA ## n ## _CLK_CTRL, (start)) \
109
+ REG32(FPGA ## n ## _THR_CTRL, (start) + 0x4)\
110
+ REG32(FPGA ## n ## _THR_CNT, (start) + 0x8)\
111
+ REG32(FPGA ## n ## _THR_STA, (start) + 0xc)
112
+FPGA_CTRL_REGS(0, 0x170)
113
+FPGA_CTRL_REGS(1, 0x180)
114
+FPGA_CTRL_REGS(2, 0x190)
115
+FPGA_CTRL_REGS(3, 0x1a0)
116
117
- BANDGAP_TRIP = 0x1b8 / 4,
118
- PLL_PREDIVISOR = 0x1c0 / 4,
119
- CLK_621_TRUE,
120
+REG32(BANDGAP_TRIP, 0x1b8)
121
+REG32(PLL_PREDIVISOR, 0x1c0)
122
+REG32(CLK_621_TRUE, 0x1c4)
123
124
- PSS_RST_CTRL = 0x200 / 4,
125
- DDR_RST_CTRL,
126
- TOPSW_RESET_CTRL,
127
- DMAC_RST_CTRL,
128
- USB_RST_CTRL,
129
- GEM_RST_CTRL,
130
- SDIO_RST_CTRL,
131
- SPI_RST_CTRL,
132
- CAN_RST_CTRL,
133
- I2C_RST_CTRL,
134
- UART_RST_CTRL,
135
- GPIO_RST_CTRL,
136
- LQSPI_RST_CTRL,
137
- SMC_RST_CTRL,
138
- OCM_RST_CTRL,
139
- FPGA_RST_CTRL = 0x240 / 4,
140
- A9_CPU_RST_CTRL,
141
+REG32(PSS_RST_CTRL, 0x200)
142
+ FIELD(PSS_RST_CTRL, SOFT_RST, 0, 1)
143
+REG32(DDR_RST_CTRL, 0x204)
144
+REG32(TOPSW_RESET_CTRL, 0x208)
145
+REG32(DMAC_RST_CTRL, 0x20c)
146
+REG32(USB_RST_CTRL, 0x210)
147
+REG32(GEM_RST_CTRL, 0x214)
148
+REG32(SDIO_RST_CTRL, 0x218)
149
+REG32(SPI_RST_CTRL, 0x21c)
150
+REG32(CAN_RST_CTRL, 0x220)
151
+REG32(I2C_RST_CTRL, 0x224)
152
+REG32(UART_RST_CTRL, 0x228)
153
+REG32(GPIO_RST_CTRL, 0x22c)
154
+REG32(LQSPI_RST_CTRL, 0x230)
155
+REG32(SMC_RST_CTRL, 0x234)
156
+REG32(OCM_RST_CTRL, 0x238)
157
+REG32(FPGA_RST_CTRL, 0x240)
158
+REG32(A9_CPU_RST_CTRL, 0x244)
159
160
- RS_AWDT_CTRL = 0x24c / 4,
161
- RST_REASON,
162
+REG32(RS_AWDT_CTRL, 0x24c)
163
+REG32(RST_REASON, 0x250)
164
165
- REBOOT_STATUS = 0x258 / 4,
166
- BOOT_MODE,
167
+REG32(REBOOT_STATUS, 0x258)
168
+REG32(BOOT_MODE, 0x25c)
169
170
- APU_CTRL = 0x300 / 4,
171
- WDT_CLK_SEL,
172
+REG32(APU_CTRL, 0x300)
173
+REG32(WDT_CLK_SEL, 0x304)
174
175
- TZ_DMA_NS = 0x440 / 4,
176
- TZ_DMA_IRQ_NS,
177
- TZ_DMA_PERIPH_NS,
178
+REG32(TZ_DMA_NS, 0x440)
179
+REG32(TZ_DMA_IRQ_NS, 0x444)
180
+REG32(TZ_DMA_PERIPH_NS, 0x448)
181
182
- PSS_IDCODE = 0x530 / 4,
183
+REG32(PSS_IDCODE, 0x530)
184
185
- DDR_URGENT = 0x600 / 4,
186
- DDR_CAL_START = 0x60c / 4,
187
- DDR_REF_START = 0x614 / 4,
188
- DDR_CMD_STA,
189
- DDR_URGENT_SEL,
190
- DDR_DFI_STATUS,
191
+REG32(DDR_URGENT, 0x600)
192
+REG32(DDR_CAL_START, 0x60c)
193
+REG32(DDR_REF_START, 0x614)
194
+REG32(DDR_CMD_STA, 0x618)
195
+REG32(DDR_URGENT_SEL, 0x61c)
196
+REG32(DDR_DFI_STATUS, 0x620)
197
198
- MIO = 0x700 / 4,
199
+REG32(MIO, 0x700)
200
#define MIO_LENGTH 54
201
202
- MIO_LOOPBACK = 0x804 / 4,
203
- MIO_MST_TRI0,
204
- MIO_MST_TRI1,
205
+REG32(MIO_LOOPBACK, 0x804)
206
+REG32(MIO_MST_TRI0, 0x808)
207
+REG32(MIO_MST_TRI1, 0x80c)
208
209
- SD0_WP_CD_SEL = 0x830 / 4,
210
- SD1_WP_CD_SEL,
211
+REG32(SD0_WP_CD_SEL, 0x830)
212
+REG32(SD1_WP_CD_SEL, 0x834)
213
214
- LVL_SHFTR_EN = 0x900 / 4,
215
- OCM_CFG = 0x910 / 4,
216
+REG32(LVL_SHFTR_EN, 0x900)
217
+REG32(OCM_CFG, 0x910)
218
219
- CPU_RAM = 0xa00 / 4,
220
+REG32(CPU_RAM, 0xa00)
221
222
- IOU = 0xa30 / 4,
223
+REG32(IOU, 0xa30)
224
225
- DMAC_RAM = 0xa50 / 4,
226
+REG32(DMAC_RAM, 0xa50)
227
228
- AFI0 = 0xa60 / 4,
229
- AFI1 = AFI0 + 3,
230
- AFI2 = AFI1 + 3,
231
- AFI3 = AFI2 + 3,
232
+REG32(AFI0, 0xa60)
233
+REG32(AFI1, 0xa6c)
234
+REG32(AFI2, 0xa78)
235
+REG32(AFI3, 0xa84)
236
#define AFI_LENGTH 3
237
238
- OCM = 0xa90 / 4,
239
+REG32(OCM, 0xa90)
240
241
- DEVCI_RAM = 0xaa0 / 4,
242
+REG32(DEVCI_RAM, 0xaa0)
243
244
- CSG_RAM = 0xab0 / 4,
245
+REG32(CSG_RAM, 0xab0)
246
247
- GPIOB_CTRL = 0xb00 / 4,
248
- GPIOB_CFG_CMOS18,
249
- GPIOB_CFG_CMOS25,
250
- GPIOB_CFG_CMOS33,
251
- GPIOB_CFG_HSTL = 0xb14 / 4,
252
- GPIOB_DRVR_BIAS_CTRL,
253
+REG32(GPIOB_CTRL, 0xb00)
254
+REG32(GPIOB_CFG_CMOS18, 0xb04)
255
+REG32(GPIOB_CFG_CMOS25, 0xb08)
256
+REG32(GPIOB_CFG_CMOS33, 0xb0c)
257
+REG32(GPIOB_CFG_HSTL, 0xb14)
258
+REG32(GPIOB_DRVR_BIAS_CTRL, 0xb18)
259
260
- DDRIOB = 0xb40 / 4,
261
+REG32(DDRIOB, 0xb40)
262
#define DDRIOB_LENGTH 14
263
-};
264
265
#define ZYNQ_SLCR_MMIO_SIZE 0x1000
266
#define ZYNQ_SLCR_NUM_REGS (ZYNQ_SLCR_MMIO_SIZE / 4)
267
@@ -XXX,XX +XXX,XX @@ static void zynq_slcr_reset(DeviceState *d)
268
269
DB_PRINT("RESET\n");
270
271
- s->regs[LOCKSTA] = 1;
272
+ s->regs[R_LOCKSTA] = 1;
273
/* 0x100 - 0x11C */
274
- s->regs[ARM_PLL_CTRL] = 0x0001A008;
275
- s->regs[DDR_PLL_CTRL] = 0x0001A008;
276
- s->regs[IO_PLL_CTRL] = 0x0001A008;
277
- s->regs[PLL_STATUS] = 0x0000003F;
278
- s->regs[ARM_PLL_CFG] = 0x00014000;
279
- s->regs[DDR_PLL_CFG] = 0x00014000;
280
- s->regs[IO_PLL_CFG] = 0x00014000;
281
+ s->regs[R_ARM_PLL_CTRL] = 0x0001A008;
282
+ s->regs[R_DDR_PLL_CTRL] = 0x0001A008;
283
+ s->regs[R_IO_PLL_CTRL] = 0x0001A008;
284
+ s->regs[R_PLL_STATUS] = 0x0000003F;
285
+ s->regs[R_ARM_PLL_CFG] = 0x00014000;
286
+ s->regs[R_DDR_PLL_CFG] = 0x00014000;
287
+ s->regs[R_IO_PLL_CFG] = 0x00014000;
288
289
/* 0x120 - 0x16C */
290
- s->regs[ARM_CLK_CTRL] = 0x1F000400;
291
- s->regs[DDR_CLK_CTRL] = 0x18400003;
292
- s->regs[DCI_CLK_CTRL] = 0x01E03201;
293
- s->regs[APER_CLK_CTRL] = 0x01FFCCCD;
294
- s->regs[USB0_CLK_CTRL] = s->regs[USB1_CLK_CTRL] = 0x00101941;
295
- s->regs[GEM0_RCLK_CTRL] = s->regs[GEM1_RCLK_CTRL] = 0x00000001;
296
- s->regs[GEM0_CLK_CTRL] = s->regs[GEM1_CLK_CTRL] = 0x00003C01;
297
- s->regs[SMC_CLK_CTRL] = 0x00003C01;
298
- s->regs[LQSPI_CLK_CTRL] = 0x00002821;
299
- s->regs[SDIO_CLK_CTRL] = 0x00001E03;
300
- s->regs[UART_CLK_CTRL] = 0x00003F03;
301
- s->regs[SPI_CLK_CTRL] = 0x00003F03;
302
- s->regs[CAN_CLK_CTRL] = 0x00501903;
303
- s->regs[DBG_CLK_CTRL] = 0x00000F03;
304
- s->regs[PCAP_CLK_CTRL] = 0x00000F01;
305
+ s->regs[R_ARM_CLK_CTRL] = 0x1F000400;
306
+ s->regs[R_DDR_CLK_CTRL] = 0x18400003;
307
+ s->regs[R_DCI_CLK_CTRL] = 0x01E03201;
308
+ s->regs[R_APER_CLK_CTRL] = 0x01FFCCCD;
309
+ s->regs[R_USB0_CLK_CTRL] = s->regs[R_USB1_CLK_CTRL] = 0x00101941;
310
+ s->regs[R_GEM0_RCLK_CTRL] = s->regs[R_GEM1_RCLK_CTRL] = 0x00000001;
311
+ s->regs[R_GEM0_CLK_CTRL] = s->regs[R_GEM1_CLK_CTRL] = 0x00003C01;
312
+ s->regs[R_SMC_CLK_CTRL] = 0x00003C01;
313
+ s->regs[R_LQSPI_CLK_CTRL] = 0x00002821;
314
+ s->regs[R_SDIO_CLK_CTRL] = 0x00001E03;
315
+ s->regs[R_UART_CLK_CTRL] = 0x00003F03;
316
+ s->regs[R_SPI_CLK_CTRL] = 0x00003F03;
317
+ s->regs[R_CAN_CLK_CTRL] = 0x00501903;
318
+ s->regs[R_DBG_CLK_CTRL] = 0x00000F03;
319
+ s->regs[R_PCAP_CLK_CTRL] = 0x00000F01;
320
321
/* 0x170 - 0x1AC */
322
- s->regs[FPGA0_CLK_CTRL] = s->regs[FPGA1_CLK_CTRL] = s->regs[FPGA2_CLK_CTRL]
323
- = s->regs[FPGA3_CLK_CTRL] = 0x00101800;
324
- s->regs[FPGA0_THR_STA] = s->regs[FPGA1_THR_STA] = s->regs[FPGA2_THR_STA]
325
- = s->regs[FPGA3_THR_STA] = 0x00010000;
326
+ s->regs[R_FPGA0_CLK_CTRL] = s->regs[R_FPGA1_CLK_CTRL]
327
+ = s->regs[R_FPGA2_CLK_CTRL]
328
+ = s->regs[R_FPGA3_CLK_CTRL] = 0x00101800;
329
+ s->regs[R_FPGA0_THR_STA] = s->regs[R_FPGA1_THR_STA]
330
+ = s->regs[R_FPGA2_THR_STA]
331
+ = s->regs[R_FPGA3_THR_STA] = 0x00010000;
332
333
/* 0x1B0 - 0x1D8 */
334
- s->regs[BANDGAP_TRIP] = 0x0000001F;
335
- s->regs[PLL_PREDIVISOR] = 0x00000001;
336
- s->regs[CLK_621_TRUE] = 0x00000001;
337
+ s->regs[R_BANDGAP_TRIP] = 0x0000001F;
338
+ s->regs[R_PLL_PREDIVISOR] = 0x00000001;
339
+ s->regs[R_CLK_621_TRUE] = 0x00000001;
340
341
/* 0x200 - 0x25C */
342
- s->regs[FPGA_RST_CTRL] = 0x01F33F0F;
343
- s->regs[RST_REASON] = 0x00000040;
344
+ s->regs[R_FPGA_RST_CTRL] = 0x01F33F0F;
345
+ s->regs[R_RST_REASON] = 0x00000040;
346
347
- s->regs[BOOT_MODE] = 0x00000001;
348
+ s->regs[R_BOOT_MODE] = 0x00000001;
349
350
/* 0x700 - 0x7D4 */
351
for (i = 0; i < 54; i++) {
352
- s->regs[MIO + i] = 0x00001601;
353
+ s->regs[R_MIO + i] = 0x00001601;
354
}
355
for (i = 2; i <= 8; i++) {
356
- s->regs[MIO + i] = 0x00000601;
357
+ s->regs[R_MIO + i] = 0x00000601;
358
}
359
360
- s->regs[MIO_MST_TRI0] = s->regs[MIO_MST_TRI1] = 0xFFFFFFFF;
361
+ s->regs[R_MIO_MST_TRI0] = s->regs[R_MIO_MST_TRI1] = 0xFFFFFFFF;
362
363
- s->regs[CPU_RAM + 0] = s->regs[CPU_RAM + 1] = s->regs[CPU_RAM + 3]
364
- = s->regs[CPU_RAM + 4] = s->regs[CPU_RAM + 7]
365
- = 0x00010101;
366
- s->regs[CPU_RAM + 2] = s->regs[CPU_RAM + 5] = 0x01010101;
367
- s->regs[CPU_RAM + 6] = 0x00000001;
368
+ s->regs[R_CPU_RAM + 0] = s->regs[R_CPU_RAM + 1] = s->regs[R_CPU_RAM + 3]
369
+ = s->regs[R_CPU_RAM + 4] = s->regs[R_CPU_RAM + 7]
370
+ = 0x00010101;
371
+ s->regs[R_CPU_RAM + 2] = s->regs[R_CPU_RAM + 5] = 0x01010101;
372
+ s->regs[R_CPU_RAM + 6] = 0x00000001;
373
374
- s->regs[IOU + 0] = s->regs[IOU + 1] = s->regs[IOU + 2] = s->regs[IOU + 3]
375
- = 0x09090909;
376
- s->regs[IOU + 4] = s->regs[IOU + 5] = 0x00090909;
377
- s->regs[IOU + 6] = 0x00000909;
378
+ s->regs[R_IOU + 0] = s->regs[R_IOU + 1] = s->regs[R_IOU + 2]
379
+ = s->regs[R_IOU + 3] = 0x09090909;
380
+ s->regs[R_IOU + 4] = s->regs[R_IOU + 5] = 0x00090909;
381
+ s->regs[R_IOU + 6] = 0x00000909;
382
383
- s->regs[DMAC_RAM] = 0x00000009;
384
+ s->regs[R_DMAC_RAM] = 0x00000009;
385
386
- s->regs[AFI0 + 0] = s->regs[AFI0 + 1] = 0x09090909;
387
- s->regs[AFI1 + 0] = s->regs[AFI1 + 1] = 0x09090909;
388
- s->regs[AFI2 + 0] = s->regs[AFI2 + 1] = 0x09090909;
389
- s->regs[AFI3 + 0] = s->regs[AFI3 + 1] = 0x09090909;
390
- s->regs[AFI0 + 2] = s->regs[AFI1 + 2] = s->regs[AFI2 + 2]
391
- = s->regs[AFI3 + 2] = 0x00000909;
392
+ s->regs[R_AFI0 + 0] = s->regs[R_AFI0 + 1] = 0x09090909;
393
+ s->regs[R_AFI1 + 0] = s->regs[R_AFI1 + 1] = 0x09090909;
394
+ s->regs[R_AFI2 + 0] = s->regs[R_AFI2 + 1] = 0x09090909;
395
+ s->regs[R_AFI3 + 0] = s->regs[R_AFI3 + 1] = 0x09090909;
396
+ s->regs[R_AFI0 + 2] = s->regs[R_AFI1 + 2] = s->regs[R_AFI2 + 2]
397
+ = s->regs[R_AFI3 + 2] = 0x00000909;
398
399
- s->regs[OCM + 0] = 0x01010101;
400
- s->regs[OCM + 1] = s->regs[OCM + 2] = 0x09090909;
401
+ s->regs[R_OCM + 0] = 0x01010101;
402
+ s->regs[R_OCM + 1] = s->regs[R_OCM + 2] = 0x09090909;
403
404
- s->regs[DEVCI_RAM] = 0x00000909;
405
- s->regs[CSG_RAM] = 0x00000001;
406
+ s->regs[R_DEVCI_RAM] = 0x00000909;
407
+ s->regs[R_CSG_RAM] = 0x00000001;
408
409
- s->regs[DDRIOB + 0] = s->regs[DDRIOB + 1] = s->regs[DDRIOB + 2]
410
- = s->regs[DDRIOB + 3] = 0x00000e00;
411
- s->regs[DDRIOB + 4] = s->regs[DDRIOB + 5] = s->regs[DDRIOB + 6]
412
- = 0x00000e00;
413
- s->regs[DDRIOB + 12] = 0x00000021;
414
+ s->regs[R_DDRIOB + 0] = s->regs[R_DDRIOB + 1] = s->regs[R_DDRIOB + 2]
415
+ = s->regs[R_DDRIOB + 3] = 0x00000e00;
416
+ s->regs[R_DDRIOB + 4] = s->regs[R_DDRIOB + 5] = s->regs[R_DDRIOB + 6]
417
+ = 0x00000e00;
418
+ s->regs[R_DDRIOB + 12] = 0x00000021;
20
}
419
}
21
420
22
-#define NUM_VIRTIO_TRANSPORT 32
421
23
+#define NUM_VIRTIO_TRANSPORT 8
422
static bool zynq_slcr_check_offset(hwaddr offset, bool rnw)
24
static void create_virtio_regions(VersalVirt *s)
25
{
423
{
26
int virtio_mmio_size = 0x200;
424
switch (offset) {
425
- case LOCK:
426
- case UNLOCK:
427
- case DDR_CAL_START:
428
- case DDR_REF_START:
429
+ case R_LOCK:
430
+ case R_UNLOCK:
431
+ case R_DDR_CAL_START:
432
+ case R_DDR_REF_START:
433
return !rnw; /* Write only */
434
- case LOCKSTA:
435
- case FPGA0_THR_STA:
436
- case FPGA1_THR_STA:
437
- case FPGA2_THR_STA:
438
- case FPGA3_THR_STA:
439
- case BOOT_MODE:
440
- case PSS_IDCODE:
441
- case DDR_CMD_STA:
442
- case DDR_DFI_STATUS:
443
- case PLL_STATUS:
444
+ case R_LOCKSTA:
445
+ case R_FPGA0_THR_STA:
446
+ case R_FPGA1_THR_STA:
447
+ case R_FPGA2_THR_STA:
448
+ case R_FPGA3_THR_STA:
449
+ case R_BOOT_MODE:
450
+ case R_PSS_IDCODE:
451
+ case R_DDR_CMD_STA:
452
+ case R_DDR_DFI_STATUS:
453
+ case R_PLL_STATUS:
454
return rnw;/* read only */
455
- case SCL:
456
- case ARM_PLL_CTRL ... IO_PLL_CTRL:
457
- case ARM_PLL_CFG ... IO_PLL_CFG:
458
- case ARM_CLK_CTRL ... TOPSW_CLK_CTRL:
459
- case FPGA0_CLK_CTRL ... FPGA0_THR_CNT:
460
- case FPGA1_CLK_CTRL ... FPGA1_THR_CNT:
461
- case FPGA2_CLK_CTRL ... FPGA2_THR_CNT:
462
- case FPGA3_CLK_CTRL ... FPGA3_THR_CNT:
463
- case BANDGAP_TRIP:
464
- case PLL_PREDIVISOR:
465
- case CLK_621_TRUE:
466
- case PSS_RST_CTRL ... A9_CPU_RST_CTRL:
467
- case RS_AWDT_CTRL:
468
- case RST_REASON:
469
- case REBOOT_STATUS:
470
- case APU_CTRL:
471
- case WDT_CLK_SEL:
472
- case TZ_DMA_NS ... TZ_DMA_PERIPH_NS:
473
- case DDR_URGENT:
474
- case DDR_URGENT_SEL:
475
- case MIO ... MIO + MIO_LENGTH - 1:
476
- case MIO_LOOPBACK ... MIO_MST_TRI1:
477
- case SD0_WP_CD_SEL:
478
- case SD1_WP_CD_SEL:
479
- case LVL_SHFTR_EN:
480
- case OCM_CFG:
481
- case CPU_RAM:
482
- case IOU:
483
- case DMAC_RAM:
484
- case AFI0 ... AFI3 + AFI_LENGTH - 1:
485
- case OCM:
486
- case DEVCI_RAM:
487
- case CSG_RAM:
488
- case GPIOB_CTRL ... GPIOB_CFG_CMOS33:
489
- case GPIOB_CFG_HSTL:
490
- case GPIOB_DRVR_BIAS_CTRL:
491
- case DDRIOB ... DDRIOB + DDRIOB_LENGTH - 1:
492
+ case R_SCL:
493
+ case R_ARM_PLL_CTRL ... R_IO_PLL_CTRL:
494
+ case R_ARM_PLL_CFG ... R_IO_PLL_CFG:
495
+ case R_ARM_CLK_CTRL ... R_TOPSW_CLK_CTRL:
496
+ case R_FPGA0_CLK_CTRL ... R_FPGA0_THR_CNT:
497
+ case R_FPGA1_CLK_CTRL ... R_FPGA1_THR_CNT:
498
+ case R_FPGA2_CLK_CTRL ... R_FPGA2_THR_CNT:
499
+ case R_FPGA3_CLK_CTRL ... R_FPGA3_THR_CNT:
500
+ case R_BANDGAP_TRIP:
501
+ case R_PLL_PREDIVISOR:
502
+ case R_CLK_621_TRUE:
503
+ case R_PSS_RST_CTRL ... R_A9_CPU_RST_CTRL:
504
+ case R_RS_AWDT_CTRL:
505
+ case R_RST_REASON:
506
+ case R_REBOOT_STATUS:
507
+ case R_APU_CTRL:
508
+ case R_WDT_CLK_SEL:
509
+ case R_TZ_DMA_NS ... R_TZ_DMA_PERIPH_NS:
510
+ case R_DDR_URGENT:
511
+ case R_DDR_URGENT_SEL:
512
+ case R_MIO ... R_MIO + MIO_LENGTH - 1:
513
+ case R_MIO_LOOPBACK ... R_MIO_MST_TRI1:
514
+ case R_SD0_WP_CD_SEL:
515
+ case R_SD1_WP_CD_SEL:
516
+ case R_LVL_SHFTR_EN:
517
+ case R_OCM_CFG:
518
+ case R_CPU_RAM:
519
+ case R_IOU:
520
+ case R_DMAC_RAM:
521
+ case R_AFI0 ... R_AFI3 + AFI_LENGTH - 1:
522
+ case R_OCM:
523
+ case R_DEVCI_RAM:
524
+ case R_CSG_RAM:
525
+ case R_GPIOB_CTRL ... R_GPIOB_CFG_CMOS33:
526
+ case R_GPIOB_CFG_HSTL:
527
+ case R_GPIOB_DRVR_BIAS_CTRL:
528
+ case R_DDRIOB ... R_DDRIOB + DDRIOB_LENGTH - 1:
529
return true;
530
default:
531
return false;
532
@@ -XXX,XX +XXX,XX @@ static void zynq_slcr_write(void *opaque, hwaddr offset,
533
}
534
535
switch (offset) {
536
- case SCL:
537
- s->regs[SCL] = val & 0x1;
538
+ case R_SCL:
539
+ s->regs[R_SCL] = val & 0x1;
540
return;
541
- case LOCK:
542
+ case R_LOCK:
543
if ((val & 0xFFFF) == XILINX_LOCK_KEY) {
544
DB_PRINT("XILINX LOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,
545
(unsigned)val & 0xFFFF);
546
- s->regs[LOCKSTA] = 1;
547
+ s->regs[R_LOCKSTA] = 1;
548
} else {
549
DB_PRINT("WRONG XILINX LOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
550
(int)offset, (unsigned)val & 0xFFFF);
551
}
552
return;
553
- case UNLOCK:
554
+ case R_UNLOCK:
555
if ((val & 0xFFFF) == XILINX_UNLOCK_KEY) {
556
DB_PRINT("XILINX UNLOCK 0xF8000000 + 0x%x <= 0x%x\n", (int)offset,
557
(unsigned)val & 0xFFFF);
558
- s->regs[LOCKSTA] = 0;
559
+ s->regs[R_LOCKSTA] = 0;
560
} else {
561
DB_PRINT("WRONG XILINX UNLOCK KEY 0xF8000000 + 0x%x <= 0x%x\n",
562
(int)offset, (unsigned)val & 0xFFFF);
563
@@ -XXX,XX +XXX,XX @@ static void zynq_slcr_write(void *opaque, hwaddr offset,
564
return;
565
}
566
567
- if (s->regs[LOCKSTA]) {
568
+ if (s->regs[R_LOCKSTA]) {
569
qemu_log_mask(LOG_GUEST_ERROR,
570
"SCLR registers are locked. Unlock them first\n");
571
return;
572
@@ -XXX,XX +XXX,XX @@ static void zynq_slcr_write(void *opaque, hwaddr offset,
573
s->regs[offset] = val;
574
575
switch (offset) {
576
- case PSS_RST_CTRL:
577
- if (val & R_PSS_RST_CTRL_SOFT_RST) {
578
+ case R_PSS_RST_CTRL:
579
+ if (FIELD_EX32(val, PSS_RST_CTRL, SOFT_RST)) {
580
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
581
}
582
break;
27
--
583
--
28
2.19.2
584
2.20.1
29
585
30
586
diff view generated by jsdifflib
[Qemu-devel] [PULL 02/37] Allow AArch64 processors to boot from a kernel placed over 4GB
[Qemu-devel] [PULL 03/29] Set ENET_BD_BDU in I.MX FEC controller
1
From: Ricardo Perez Blanco <ricardo.perez_blanco@nokia.com>
1
From: Aaron Hill <aa1ronham@gmail.com>
2
2
3
Architecturally, it's possible for an AArch64 machine to have
3
This commit properly sets the ENET_BD_BDU flag once the emulated FEC controller
4
all of its RAM over the 4GB mark, but our kernel/initrd loading
4
has finished processing the last descriptor. This is done for both transmit
5
code in boot.c assumes that the upper half of the addresses
5
and receive descriptors.
6
to load these images to is always zero. Write the whole 64 bit
7
address into the bootloader code fragment, not just the low half.
8
6
9
Note that, currently, none of the existing QEMU machines have
7
This allows the QNX 7.0.0 BSP for the Sabrelite board (which can be
10
their main memory over 4GBs, so this was not a user-visible bug.
8
found at http://blackberry.qnx.com/en/developers/bsp) to properly
9
control the FEC. Without this patch, the BSP ethernet driver will never
10
re-use FEC descriptors, as the unset ENET_BD_BDU flag will cause
11
it to believe that the descriptors are still in use by the NIC.
11
12
12
Signed-off-by: Ricardo Perez Blanco <ricardo.perez_blanco@nokia.com>
13
Note that Linux does not appear to use this field at all, and is
13
[PMM: revised commit message and tweaked some long lines]
14
unaffected by this patch.
15
16
Without this patch, QNX will think that the NIC is still processing its
17
transaction descriptors, and won't send any more data over the network.
18
19
For reference:
20
21
On page 1192 of the I.MX 6DQ reference manual revision (Rev. 5, 06/2018),
22
which can be found at https://www.nxp.com/products/processors-and-microcontrollers/arm-based-processors-and-mcus/i.mx-applications-processors/i.mx-6-processors/i.mx-6quad-processors-high-performance-3d-graphics-hd-video-arm-cortex-a9-core:i.MX6Q?&tab=Documentation_Tab&linkline=Application-Note
23
24
the 'BDU' field is described as follows for the 'Enhanced transmit
25
buffer descriptor':
26
27
'Last buffer descriptor update done. Indicates that the last BD data has been updated by
28
uDMA. This field is written by the user (=0) and uDMA (=1).'
29
30
The same description is used for the receive buffer descriptor.
31
32
Signed-off-by: Aaron Hill <aa1ronham@gmail.com>
33
Message-id: 20190805142417.10433-1-aaron.hill@alertinnovation.com
14
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
34
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
35
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
36
---
17
hw/arm/boot.c | 35 ++++++++++++++++++++++-------------
37
hw/net/imx_fec.c | 4 ++++
18
1 file changed, 22 insertions(+), 13 deletions(-)
38
1 file changed, 4 insertions(+)
19
39
20
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
40
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
21
index XXXXXXX..XXXXXXX 100644
41
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/arm/boot.c
42
--- a/hw/net/imx_fec.c
23
+++ b/hw/arm/boot.c
43
+++ b/hw/net/imx_fec.c
24
@@ -XXX,XX +XXX,XX @@ typedef enum {
44
@@ -XXX,XX +XXX,XX @@ static void imx_enet_do_tx(IMXFECState *s, uint32_t index)
25
FIXUP_TERMINATOR, /* end of insns */
45
if (bd.option & ENET_BD_TX_INT) {
26
FIXUP_BOARDID, /* overwrite with board ID number */
46
s->regs[ENET_EIR] |= int_txf;
27
FIXUP_BOARD_SETUP, /* overwrite with board specific setup code address */
28
- FIXUP_ARGPTR, /* overwrite with pointer to kernel args */
29
- FIXUP_ENTRYPOINT, /* overwrite with kernel entry point */
30
+ FIXUP_ARGPTR_LO, /* overwrite with pointer to kernel args */
31
+ FIXUP_ARGPTR_HI, /* overwrite with pointer to kernel args (high half) */
32
+ FIXUP_ENTRYPOINT_LO, /* overwrite with kernel entry point */
33
+ FIXUP_ENTRYPOINT_HI, /* overwrite with kernel entry point (high half) */
34
FIXUP_GIC_CPU_IF, /* overwrite with GIC CPU interface address */
35
FIXUP_BOOTREG, /* overwrite with boot register address */
36
FIXUP_DSB, /* overwrite with correct DSB insn for cpu */
37
@@ -XXX,XX +XXX,XX @@ static const ARMInsnFixup bootloader_aarch64[] = {
38
{ 0xaa1f03e3 }, /* mov x3, xzr */
39
{ 0x58000084 }, /* ldr x4, entry ; Load the lower 32-bits of kernel entry */
40
{ 0xd61f0080 }, /* br x4 ; Jump to the kernel entry point */
41
- { 0, FIXUP_ARGPTR }, /* arg: .word @DTB Lower 32-bits */
42
- { 0 }, /* .word @DTB Higher 32-bits */
43
- { 0, FIXUP_ENTRYPOINT }, /* entry: .word @Kernel Entry Lower 32-bits */
44
- { 0 }, /* .word @Kernel Entry Higher 32-bits */
45
+ { 0, FIXUP_ARGPTR_LO }, /* arg: .word @DTB Lower 32-bits */
46
+ { 0, FIXUP_ARGPTR_HI}, /* .word @DTB Higher 32-bits */
47
+ { 0, FIXUP_ENTRYPOINT_LO }, /* entry: .word @Kernel Entry Lower 32-bits */
48
+ { 0, FIXUP_ENTRYPOINT_HI }, /* .word @Kernel Entry Higher 32-bits */
49
{ 0, FIXUP_TERMINATOR }
50
};
51
52
@@ -XXX,XX +XXX,XX @@ static const ARMInsnFixup bootloader[] = {
53
{ 0xe59f2004 }, /* ldr r2, [pc, #4] */
54
{ 0xe59ff004 }, /* ldr pc, [pc, #4] */
55
{ 0, FIXUP_BOARDID },
56
- { 0, FIXUP_ARGPTR },
57
- { 0, FIXUP_ENTRYPOINT },
58
+ { 0, FIXUP_ARGPTR_LO },
59
+ { 0, FIXUP_ENTRYPOINT_LO },
60
{ 0, FIXUP_TERMINATOR }
61
};
62
63
@@ -XXX,XX +XXX,XX @@ static void write_bootloader(const char *name, hwaddr addr,
64
break;
65
case FIXUP_BOARDID:
66
case FIXUP_BOARD_SETUP:
67
- case FIXUP_ARGPTR:
68
- case FIXUP_ENTRYPOINT:
69
+ case FIXUP_ARGPTR_LO:
70
+ case FIXUP_ARGPTR_HI:
71
+ case FIXUP_ENTRYPOINT_LO:
72
+ case FIXUP_ENTRYPOINT_HI:
73
case FIXUP_GIC_CPU_IF:
74
case FIXUP_BOOTREG:
75
case FIXUP_DSB:
76
@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
77
/* Place the DTB after the initrd in memory with alignment. */
78
info->dtb_start = QEMU_ALIGN_UP(info->initrd_start + initrd_size,
79
align);
80
- fixupcontext[FIXUP_ARGPTR] = info->dtb_start;
81
+ fixupcontext[FIXUP_ARGPTR_LO] = info->dtb_start;
82
+ fixupcontext[FIXUP_ARGPTR_HI] = info->dtb_start >> 32;
83
} else {
84
- fixupcontext[FIXUP_ARGPTR] = info->loader_start + KERNEL_ARGS_ADDR;
85
+ fixupcontext[FIXUP_ARGPTR_LO] =
86
+ info->loader_start + KERNEL_ARGS_ADDR;
87
+ fixupcontext[FIXUP_ARGPTR_HI] =
88
+ (info->loader_start + KERNEL_ARGS_ADDR) >> 32;
89
if (info->ram_size >= (1ULL << 32)) {
90
error_report("RAM size must be less than 4GB to boot"
91
" Linux kernel using ATAGS (try passing a device tree"
92
@@ -XXX,XX +XXX,XX @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
93
exit(1);
94
}
47
}
48
+ /* Indicate that we've updated the last buffer descriptor. */
49
+ bd.last_buffer = ENET_BD_BDU;
95
}
50
}
96
- fixupcontext[FIXUP_ENTRYPOINT] = entry;
51
if (bd.option & ENET_BD_TX_INT) {
97
+ fixupcontext[FIXUP_ENTRYPOINT_LO] = entry;
52
s->regs[ENET_EIR] |= int_txb;
98
+ fixupcontext[FIXUP_ENTRYPOINT_HI] = entry >> 32;
53
@@ -XXX,XX +XXX,XX @@ static ssize_t imx_enet_receive(NetClientState *nc, const uint8_t *buf,
99
54
/* Last buffer in frame. */
100
write_bootloader("bootloader", info->loader_start,
55
bd.flags |= flags | ENET_BD_L;
101
primary_loader, fixupcontext, as);
56
FEC_PRINTF("rx frame flags %04x\n", bd.flags);
57
+ /* Indicate that we've updated the last buffer descriptor. */
58
+ bd.last_buffer = ENET_BD_BDU;
59
if (bd.option & ENET_BD_RX_INT) {
60
s->regs[ENET_EIR] |= ENET_INT_RXF;
61
}
102
--
62
--
103
2.19.2
63
2.20.1
104
64
105
65
diff view generated by jsdifflib
[Qemu-devel] [PULL 20/37] timer/puv3_ost: Convert sysbus init function to realize function
[Qemu-devel] [PULL 04/29] target/arm: Factor out 'generate singlestep exception' function
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
Factor out code to 'generate a singlestep exception', which is
2
currently repeated in four places.
2
3
3
Use DeviceClass rather than SysBusDeviceClass in
4
To do this we need to also pull the identical copies of the
4
puv3_ost_class_init().
5
gen-exception() function out of translate-a64.c and translate.c
6
into translate.h.
5
7
6
Cc: gxt@mprc.pku.edu.cn
8
(There is a bug in the code: we're taking the exception to the wrong
9
target EL. This will be simpler to fix if there's only one place to
10
do it.)
7
11
8
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Message-id: 20181130093852.20739-19-maozhongyi@cmss.chinamobile.com
14
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Message-id: 20190805130952.4415-2-peter.maydell@linaro.org
13
---
16
---
14
hw/timer/puv3_ost.c | 13 ++++++-------
17
target/arm/translate.h | 23 +++++++++++++++++++++++
15
1 file changed, 6 insertions(+), 7 deletions(-)
18
target/arm/translate-a64.c | 19 ++-----------------
19
target/arm/translate.c | 20 ++------------------
20
3 files changed, 27 insertions(+), 35 deletions(-)
16
21
17
diff --git a/hw/timer/puv3_ost.c b/hw/timer/puv3_ost.c
22
diff --git a/target/arm/translate.h b/target/arm/translate.h
18
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/timer/puv3_ost.c
24
--- a/target/arm/translate.h
20
+++ b/hw/timer/puv3_ost.c
25
+++ b/target/arm/translate.h
21
@@ -XXX,XX +XXX,XX @@ static void puv3_ost_tick(void *opaque)
26
@@ -XXX,XX +XXX,XX @@
27
#define TARGET_ARM_TRANSLATE_H
28
29
#include "exec/translator.h"
30
+#include "internals.h"
31
32
33
/* internal defines */
34
@@ -XXX,XX +XXX,XX @@ static inline void gen_ss_advance(DisasContext *s)
22
}
35
}
23
}
36
}
24
37
25
-static int puv3_ost_init(SysBusDevice *dev)
38
+static inline void gen_exception(int excp, uint32_t syndrome,
26
+static void puv3_ost_realize(DeviceState *dev, Error **errp)
39
+ uint32_t target_el)
40
+{
41
+ TCGv_i32 tcg_excp = tcg_const_i32(excp);
42
+ TCGv_i32 tcg_syn = tcg_const_i32(syndrome);
43
+ TCGv_i32 tcg_el = tcg_const_i32(target_el);
44
+
45
+ gen_helper_exception_with_syndrome(cpu_env, tcg_excp,
46
+ tcg_syn, tcg_el);
47
+
48
+ tcg_temp_free_i32(tcg_el);
49
+ tcg_temp_free_i32(tcg_syn);
50
+ tcg_temp_free_i32(tcg_excp);
51
+}
52
+
53
+/* Generate an architectural singlestep exception */
54
+static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
55
+{
56
+ gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, isv, ex),
57
+ default_exception_el(s));
58
+}
59
+
60
/*
61
* Given a VFP floating point constant encoded into an 8 bit immediate in an
62
* instruction, expand it to the actual constant value of the specified
63
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
64
index XXXXXXX..XXXXXXX 100644
65
--- a/target/arm/translate-a64.c
66
+++ b/target/arm/translate-a64.c
67
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal(int excp)
68
tcg_temp_free_i32(tcg_excp);
69
}
70
71
-static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el)
72
-{
73
- TCGv_i32 tcg_excp = tcg_const_i32(excp);
74
- TCGv_i32 tcg_syn = tcg_const_i32(syndrome);
75
- TCGv_i32 tcg_el = tcg_const_i32(target_el);
76
-
77
- gen_helper_exception_with_syndrome(cpu_env, tcg_excp,
78
- tcg_syn, tcg_el);
79
- tcg_temp_free_i32(tcg_el);
80
- tcg_temp_free_i32(tcg_syn);
81
- tcg_temp_free_i32(tcg_excp);
82
-}
83
-
84
static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
27
{
85
{
28
PUV3OSTState *s = PUV3_OST(dev);
86
gen_a64_set_pc_im(s->pc - offset);
29
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
87
@@ -XXX,XX +XXX,XX @@ static void gen_step_complete_exception(DisasContext *s)
30
88
* of the exception, and our syndrome information is always correct.
31
s->reg_OIER = 0;
89
*/
32
s->reg_OSSR = 0;
90
gen_ss_advance(s);
33
s->reg_OSMR0 = 0;
91
- gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex),
34
s->reg_OSCR = 0;
92
- default_exception_el(s));
35
93
+ gen_swstep_exception(s, 1, s->is_ldex);
36
- sysbus_init_irq(dev, &s->irq);
94
s->base.is_jmp = DISAS_NORETURN;
37
+ sysbus_init_irq(sbd, &s->irq);
95
}
38
96
39
s->bh = qemu_bh_new(puv3_ost_tick, s);
97
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
40
s->ptimer = ptimer_init(s->bh, PTIMER_POLICY_DEFAULT);
98
* bits should be zero.
41
@@ -XXX,XX +XXX,XX @@ static int puv3_ost_init(SysBusDevice *dev)
99
*/
42
100
assert(dc->base.num_insns == 1);
43
memory_region_init_io(&s->iomem, OBJECT(s), &puv3_ost_ops, s, "puv3_ost",
101
- gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0),
44
PUV3_REGS_OFFSET);
102
- default_exception_el(dc));
45
- sysbus_init_mmio(dev, &s->iomem);
103
+ gen_swstep_exception(dc, 0, 0);
104
dc->base.is_jmp = DISAS_NORETURN;
105
} else {
106
disas_a64_insn(env, dc);
107
diff --git a/target/arm/translate.c b/target/arm/translate.c
108
index XXXXXXX..XXXXXXX 100644
109
--- a/target/arm/translate.c
110
+++ b/target/arm/translate.c
111
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal(int excp)
112
tcg_temp_free_i32(tcg_excp);
113
}
114
115
-static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el)
116
-{
117
- TCGv_i32 tcg_excp = tcg_const_i32(excp);
118
- TCGv_i32 tcg_syn = tcg_const_i32(syndrome);
119
- TCGv_i32 tcg_el = tcg_const_i32(target_el);
46
-
120
-
47
- return 0;
121
- gen_helper_exception_with_syndrome(cpu_env, tcg_excp,
48
+ sysbus_init_mmio(sbd, &s->iomem);
122
- tcg_syn, tcg_el);
123
-
124
- tcg_temp_free_i32(tcg_el);
125
- tcg_temp_free_i32(tcg_syn);
126
- tcg_temp_free_i32(tcg_excp);
127
-}
128
-
129
static void gen_step_complete_exception(DisasContext *s)
130
{
131
/* We just completed step of an insn. Move from Active-not-pending
132
@@ -XXX,XX +XXX,XX @@ static void gen_step_complete_exception(DisasContext *s)
133
* of the exception, and our syndrome information is always correct.
134
*/
135
gen_ss_advance(s);
136
- gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex),
137
- default_exception_el(s));
138
+ gen_swstep_exception(s, 1, s->is_ldex);
139
s->base.is_jmp = DISAS_NORETURN;
49
}
140
}
50
141
51
static void puv3_ost_class_init(ObjectClass *klass, void *data)
142
@@ -XXX,XX +XXX,XX @@ static bool arm_pre_translate_insn(DisasContext *dc)
52
{
143
* bits should be zero.
53
- SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
144
*/
54
+ DeviceClass *dc = DEVICE_CLASS(klass);
145
assert(dc->base.num_insns == 1);
55
146
- gen_exception(EXCP_UDEF, syn_swstep(dc->ss_same_el, 0, 0),
56
- sdc->init = puv3_ost_init;
147
- default_exception_el(dc));
57
+ dc->realize = puv3_ost_realize;
148
+ gen_swstep_exception(dc, 0, 0);
58
}
149
dc->base.is_jmp = DISAS_NORETURN;
59
150
return true;
60
static const TypeInfo puv3_ost_info = {
151
}
61
--
152
--
62
2.19.2
153
2.20.1
63
154
64
155
diff view generated by jsdifflib
[Qemu-devel] [PULL 37/37] target/arm: Implement the ARMv8.1-LOR extension
[Qemu-devel] [PULL 05/29] target/arm: Fix routing of singlestep exceptions
1
From: Richard Henderson <richard.henderson@linaro.org>
1
When generating an architectural single-step exception we were
2
routing it to the "default exception level", which is to say
3
the same exception level we execute at except that EL0 exceptions
4
go to EL1. This is incorrect because the debug exception level
5
can be configured by the guest for situations such as single
6
stepping of EL0 and EL1 code by EL2.
2
7
3
Provide a trivial implementation with zero limited ordering regions,
8
We have to track the target debug exception level in the TB
4
which causes the LDLAR and STLLR instructions to devolve into the
9
flags, because it is dependent on CPU state like HCR_EL2.TGE
5
LDAR and STLR instructions from the base ARMv8.0 instruction set.
10
and MDCR_EL2.TDE. (That we were previously calling the
11
arm_debug_target_el() function to determine dc->ss_same_el
12
is itself a bug, though one that would only have manifested
13
as incorrect syndrome information.) Since we are out of TB
14
flag bits unless we want to expand into the cs_base field,
15
we share some bits with the M-profile only HANDLER and
16
STACKCHECK bits, since only A-profile has this singlestep.
6
17
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Fixes: https://bugs.launchpad.net/qemu/+bug/1838913
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20181210150501.7990-4-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
20
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
21
Tested-by: Alex Bennée <alex.bennee@linaro.org>
22
Message-id: 20190805130952.4415-3-peter.maydell@linaro.org
11
---
23
---
12
target/arm/cpu.h | 5 +++
24
target/arm/cpu.h | 5 +++++
13
target/arm/cpu64.c | 1 +
25
target/arm/translate.h | 15 +++++++++++----
14
target/arm/helper.c | 75 ++++++++++++++++++++++++++++++++++++++
26
target/arm/helper.c | 6 ++++++
15
target/arm/translate-a64.c | 12 ++++++
27
target/arm/translate-a64.c | 2 +-
16
4 files changed, 93 insertions(+)
28
target/arm/translate.c | 4 +++-
29
5 files changed, 26 insertions(+), 6 deletions(-)
17
30
18
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
31
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
19
index XXXXXXX..XXXXXXX 100644
32
index XXXXXXX..XXXXXXX 100644
20
--- a/target/arm/cpu.h
33
--- a/target/arm/cpu.h
21
+++ b/target/arm/cpu.h
34
+++ b/target/arm/cpu.h
22
@@ -XXX,XX +XXX,XX @@ static inline bool isar_feature_aa64_sve(const ARMISARegisters *id)
35
@@ -XXX,XX +XXX,XX @@ FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1)
23
return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) != 0;
36
/* Target EL if we take a floating-point-disabled exception */
37
FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2)
38
FIELD(TBFLAG_ANY, BE_DATA, 23, 1)
39
+/*
40
+ * For A-profile only, target EL for debug exceptions.
41
+ * Note that this overlaps with the M-profile-only HANDLER and STACKCHECK bits.
42
+ */
43
+FIELD(TBFLAG_ANY, DEBUG_TARGET_EL, 21, 2)
44
45
/* Bit usage when in AArch32 state: */
46
FIELD(TBFLAG_A32, THUMB, 0, 1)
47
diff --git a/target/arm/translate.h b/target/arm/translate.h
48
index XXXXXXX..XXXXXXX 100644
49
--- a/target/arm/translate.h
50
+++ b/target/arm/translate.h
51
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
52
uint32_t svc_imm;
53
int aarch64;
54
int current_el;
55
+ /* Debug target exception level for single-step exceptions */
56
+ int debug_target_el;
57
GHashTable *cp_regs;
58
uint64_t features; /* CPU features bits */
59
/* Because unallocated encodings generate different exception syndrome
60
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
61
* ie A64 LDX*, LDAX*, A32/T32 LDREX*, LDAEX*.
62
*/
63
bool is_ldex;
64
- /* True if a single-step exception will be taken to the current EL */
65
- bool ss_same_el;
66
/* True if v8.3-PAuth is active. */
67
bool pauth_active;
68
/* True with v8.5-BTI and SCTLR_ELx.BT* set. */
69
@@ -XXX,XX +XXX,XX @@ static inline void gen_exception(int excp, uint32_t syndrome,
70
/* Generate an architectural singlestep exception */
71
static inline void gen_swstep_exception(DisasContext *s, int isv, int ex)
72
{
73
- gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, isv, ex),
74
- default_exception_el(s));
75
+ bool same_el = (s->debug_target_el == s->current_el);
76
+
77
+ /*
78
+ * If singlestep is targeting a lower EL than the current one,
79
+ * then s->ss_active must be false and we can never get here.
80
+ */
81
+ assert(s->debug_target_el >= s->current_el);
82
+
83
+ gen_exception(EXCP_UDEF, syn_swstep(same_el, isv, ex), s->debug_target_el);
24
}
84
}
25
85
26
+static inline bool isar_feature_aa64_lor(const ARMISARegisters *id)
27
+{
28
+ return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, LO) != 0;
29
+}
30
+
31
/*
86
/*
32
* Forward to the above feature tests given an ARMCPU pointer.
33
*/
34
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
35
index XXXXXXX..XXXXXXX 100644
36
--- a/target/arm/cpu64.c
37
+++ b/target/arm/cpu64.c
38
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
39
40
t = cpu->isar.id_aa64mmfr1;
41
t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
42
+ t = FIELD_DP64(t, ID_AA64MMFR1, LO, 1);
43
cpu->isar.id_aa64mmfr1 = t;
44
45
/* Replicate the same data to the 32-bit id registers. */
46
diff --git a/target/arm/helper.c b/target/arm/helper.c
87
diff --git a/target/arm/helper.c b/target/arm/helper.c
47
index XXXXXXX..XXXXXXX 100644
88
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/helper.c
89
--- a/target/arm/helper.c
49
+++ b/target/arm/helper.c
90
+++ b/target/arm/helper.c
50
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
91
@@ -XXX,XX +XXX,XX @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
51
{
52
/* Begin with base v8.0 state. */
53
uint32_t valid_mask = 0x3fff;
54
+ ARMCPU *cpu = arm_env_get_cpu(env);
55
56
if (arm_el_is_aa64(env, 3)) {
57
value |= SCR_FW | SCR_AW; /* these two bits are RES1. */
58
@@ -XXX,XX +XXX,XX @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
59
valid_mask &= ~SCR_SMD;
60
}
92
}
61
}
93
}
62
+ if (cpu_isar_feature(aa64_lor, cpu)) {
94
63
+ valid_mask |= SCR_TLOR;
95
+ if (!arm_feature(env, ARM_FEATURE_M)) {
64
+ }
96
+ int target_el = arm_debug_target_el(env);
65
66
/* Clear all-context RES0 bits. */
67
value &= valid_mask;
68
@@ -XXX,XX +XXX,XX @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
69
*/
70
valid_mask &= ~HCR_TSC;
71
}
72
+ if (cpu_isar_feature(aa64_lor, cpu)) {
73
+ valid_mask |= HCR_TLOR;
74
+ }
75
76
/* Clear RES0 bits. */
77
value &= valid_mask;
78
@@ -XXX,XX +XXX,XX @@ static uint64_t id_aa64pfr0_read(CPUARMState *env, const ARMCPRegInfo *ri)
79
return pfr0;
80
}
81
82
+/* Shared logic between LORID and the rest of the LOR* registers.
83
+ * Secure state has already been delt with.
84
+ */
85
+static CPAccessResult access_lor_ns(CPUARMState *env)
86
+{
87
+ int el = arm_current_el(env);
88
+
97
+
89
+ if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TLOR)) {
98
+ flags = FIELD_DP32(flags, TBFLAG_ANY, DEBUG_TARGET_EL, target_el);
90
+ return CP_ACCESS_TRAP_EL2;
91
+ }
92
+ if (el < 3 && (env->cp15.scr_el3 & SCR_TLOR)) {
93
+ return CP_ACCESS_TRAP_EL3;
94
+ }
95
+ return CP_ACCESS_OK;
96
+}
97
+
98
+static CPAccessResult access_lorid(CPUARMState *env, const ARMCPRegInfo *ri,
99
+ bool isread)
100
+{
101
+ if (arm_is_secure_below_el3(env)) {
102
+ /* Access ok in secure mode. */
103
+ return CP_ACCESS_OK;
104
+ }
105
+ return access_lor_ns(env);
106
+}
107
+
108
+static CPAccessResult access_lor_other(CPUARMState *env,
109
+ const ARMCPRegInfo *ri, bool isread)
110
+{
111
+ if (arm_is_secure_below_el3(env)) {
112
+ /* Access denied in secure mode. */
113
+ return CP_ACCESS_TRAP;
114
+ }
115
+ return access_lor_ns(env);
116
+}
117
+
118
void register_cp_regs_for_features(ARMCPU *cpu)
119
{
120
/* Register all the coprocessor registers based on feature bits */
121
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
122
define_one_arm_cp_reg(cpu, &sctlr);
123
}
124
125
+ if (cpu_isar_feature(aa64_lor, cpu)) {
126
+ /*
127
+ * A trivial implementation of ARMv8.1-LOR leaves all of these
128
+ * registers fixed at 0, which indicates that there are zero
129
+ * supported Limited Ordering regions.
130
+ */
131
+ static const ARMCPRegInfo lor_reginfo[] = {
132
+ { .name = "LORSA_EL1", .state = ARM_CP_STATE_AA64,
133
+ .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 0,
134
+ .access = PL1_RW, .accessfn = access_lor_other,
135
+ .type = ARM_CP_CONST, .resetvalue = 0 },
136
+ { .name = "LOREA_EL1", .state = ARM_CP_STATE_AA64,
137
+ .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 1,
138
+ .access = PL1_RW, .accessfn = access_lor_other,
139
+ .type = ARM_CP_CONST, .resetvalue = 0 },
140
+ { .name = "LORN_EL1", .state = ARM_CP_STATE_AA64,
141
+ .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 2,
142
+ .access = PL1_RW, .accessfn = access_lor_other,
143
+ .type = ARM_CP_CONST, .resetvalue = 0 },
144
+ { .name = "LORC_EL1", .state = ARM_CP_STATE_AA64,
145
+ .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 3,
146
+ .access = PL1_RW, .accessfn = access_lor_other,
147
+ .type = ARM_CP_CONST, .resetvalue = 0 },
148
+ { .name = "LORID_EL1", .state = ARM_CP_STATE_AA64,
149
+ .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 4, .opc2 = 7,
150
+ .access = PL1_R, .accessfn = access_lorid,
151
+ .type = ARM_CP_CONST, .resetvalue = 0 },
152
+ REGINFO_SENTINEL
153
+ };
154
+ define_arm_cp_regs(cpu, lor_reginfo);
155
+ }
99
+ }
156
+
100
+
157
if (cpu_isar_feature(aa64_sve, cpu)) {
101
*pflags = flags;
158
define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);
102
*cs_base = 0;
159
if (arm_feature(env, ARM_FEATURE_EL2)) {
103
}
160
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
104
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
161
index XXXXXXX..XXXXXXX 100644
105
index XXXXXXX..XXXXXXX 100644
162
--- a/target/arm/translate-a64.c
106
--- a/target/arm/translate-a64.c
163
+++ b/target/arm/translate-a64.c
107
+++ b/target/arm/translate-a64.c
164
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
108
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
165
}
109
dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE);
166
return;
110
dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS);
167
111
dc->is_ldex = false;
168
+ case 0x8: /* STLLR */
112
- dc->ss_same_el = (arm_debug_target_el(env) == dc->current_el);
169
+ if (!dc_isar_feature(aa64_lor, s)) {
113
+ dc->debug_target_el = FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL);
170
+ break;
114
171
+ }
115
/* Bound the number of insns to execute to those left on the page. */
172
+ /* StoreLORelease is the same as Store-Release for QEMU. */
116
bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
173
+ /* fall through */
117
diff --git a/target/arm/translate.c b/target/arm/translate.c
174
case 0x9: /* STLR */
118
index XXXXXXX..XXXXXXX 100644
175
/* Generate ISS for non-exclusive accesses including LASR. */
119
--- a/target/arm/translate.c
176
if (rn == 31) {
120
+++ b/target/arm/translate.c
177
@@ -XXX,XX +XXX,XX @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
121
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
178
disas_ldst_compute_iss_sf(size, false, 0), is_lasr);
122
dc->ss_active = FIELD_EX32(tb_flags, TBFLAG_ANY, SS_ACTIVE);
179
return;
123
dc->pstate_ss = FIELD_EX32(tb_flags, TBFLAG_ANY, PSTATE_SS);
180
124
dc->is_ldex = false;
181
+ case 0xc: /* LDLAR */
125
- dc->ss_same_el = false; /* Can't be true since EL_d must be AArch64 */
182
+ if (!dc_isar_feature(aa64_lor, s)) {
126
+ if (!arm_feature(env, ARM_FEATURE_M)) {
183
+ break;
127
+ dc->debug_target_el = FIELD_EX32(tb_flags, TBFLAG_ANY, DEBUG_TARGET_EL);
184
+ }
128
+ }
185
+ /* LoadLOAcquire is the same as Load-Acquire for QEMU. */
129
186
+ /* fall through */
130
dc->page_start = dc->base.pc_first & TARGET_PAGE_MASK;
187
case 0xd: /* LDAR */
131
188
/* Generate ISS for non-exclusive accesses including LASR. */
189
if (rn == 31) {
190
--
132
--
191
2.19.2
133
2.20.1
192
134
193
135
diff view generated by jsdifflib
[Qemu-devel] [PULL 19/37] timer/grlib_gptimer: Convert sysbus init function to realize function
[Qemu-devel] [PULL 06/29] target/arm: Pass in pc to thumb_insn_is_16bit
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Use DeviceClass rather than SysBusDeviceClass in
3
This function is used in two different contexts, and it will be
4
grlib_gptimer_class_init().
4
clearer if the function is given the address to which it applies.
5
5
6
Cc: chouteau@adacore.com
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
9
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Message-id: 20181130093852.20739-18-maozhongyi@cmss.chinamobile.com
9
Message-id: 20190807045335.1361-2-richard.henderson@linaro.org
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
11
---
14
hw/timer/grlib_gptimer.c | 11 +++++------
12
target/arm/translate.c | 14 +++++++-------
15
1 file changed, 5 insertions(+), 6 deletions(-)
13
1 file changed, 7 insertions(+), 7 deletions(-)
16
14
17
diff --git a/hw/timer/grlib_gptimer.c b/hw/timer/grlib_gptimer.c
15
diff --git a/target/arm/translate.c b/target/arm/translate.c
18
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/timer/grlib_gptimer.c
17
--- a/target/arm/translate.c
20
+++ b/hw/timer/grlib_gptimer.c
18
+++ b/target/arm/translate.c
21
@@ -XXX,XX +XXX,XX @@ static void grlib_gptimer_reset(DeviceState *d)
19
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
22
}
20
}
23
}
21
}
24
22
25
-static int grlib_gptimer_init(SysBusDevice *dev)
23
-static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn)
26
+static void grlib_gptimer_realize(DeviceState *dev, Error **errp)
24
+static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t insn)
27
{
25
{
28
GPTimerUnit *unit = GRLIB_GPTIMER(dev);
26
- /* Return true if this is a 16 bit instruction. We must be precise
29
unsigned int i;
27
- * about this (matching the decode). We assume that s->pc still
30
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
28
- * points to the first 16 bits of the insn.
31
29
+ /*
32
assert(unit->nr_timers > 0);
30
+ * Return true if this is a 16 bit instruction. We must be precise
33
assert(unit->nr_timers <= GPTIMER_MAX_TIMERS);
31
+ * about this (matching the decode).
34
@@ -XXX,XX +XXX,XX @@ static int grlib_gptimer_init(SysBusDevice *dev)
32
*/
35
timer->id = i;
33
if ((insn >> 11) < 0x1d) {
36
34
/* Definitely a 16-bit instruction */
37
/* One IRQ line for each timer */
35
@@ -XXX,XX +XXX,XX @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t insn)
38
- sysbus_init_irq(dev, &timer->irq);
36
return false;
39
+ sysbus_init_irq(sbd, &timer->irq);
40
41
ptimer_set_freq(timer->ptimer, unit->freq_hz);
42
}
37
}
43
@@ -XXX,XX +XXX,XX @@ static int grlib_gptimer_init(SysBusDevice *dev)
38
44
unit, "gptimer",
39
- if ((insn >> 11) == 0x1e && s->pc - s->page_start < TARGET_PAGE_SIZE - 3) {
45
UNIT_REG_SIZE + GPTIMER_REG_SIZE * unit->nr_timers);
40
+ if ((insn >> 11) == 0x1e && pc - s->page_start < TARGET_PAGE_SIZE - 3) {
46
41
/* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix, and the suffix
47
- sysbus_init_mmio(dev, &unit->iomem);
42
* is not on the next page; we merge this into a 32-bit
48
- return 0;
43
* insn.
49
+ sysbus_init_mmio(sbd, &unit->iomem);
44
@@ -XXX,XX +XXX,XX @@ static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
45
*/
46
uint16_t insn = arm_lduw_code(env, s->pc, s->sctlr_b);
47
48
- return !thumb_insn_is_16bit(s, insn);
49
+ return !thumb_insn_is_16bit(s, s->pc, insn);
50
}
50
}
51
51
52
static Property grlib_gptimer_properties[] = {
52
static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
53
@@ -XXX,XX +XXX,XX @@ static Property grlib_gptimer_properties[] = {
53
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
54
static void grlib_gptimer_class_init(ObjectClass *klass, void *data)
54
}
55
{
55
56
DeviceClass *dc = DEVICE_CLASS(klass);
56
insn = arm_lduw_code(env, dc->pc, dc->sctlr_b);
57
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
57
- is_16bit = thumb_insn_is_16bit(dc, insn);
58
58
+ is_16bit = thumb_insn_is_16bit(dc, dc->pc, insn);
59
- k->init = grlib_gptimer_init;
59
dc->pc += 2;
60
+ dc->realize = grlib_gptimer_realize;
60
if (!is_16bit) {
61
dc->reset = grlib_gptimer_reset;
61
uint32_t insn2 = arm_lduw_code(env, dc->pc, dc->sctlr_b);
62
dc->props = grlib_gptimer_properties;
63
}
64
--
62
--
65
2.19.2
63
2.20.1
66
64
67
65
diff view generated by jsdifflib
[Qemu-devel] [PULL 27/37] hw/arm: versal: Correct the nr of IRQs to 192
[Qemu-devel] [PULL 07/29] target/arm: Introduce pc_curr
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Correct the nr of IRQs to 192.
3
Add a new field to retain the address of the instruction currently
4
4
being translated. The 32-bit uses are all within subroutines used
5
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
5
by a32 and t32. This will become less obvious when t16 support is
6
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
6
merged with a32+t32, and having a clear definition will help.
7
Message-id: 20181129163655.20370-5-edgar.iglesias@gmail.com
7
8
Convert aarch64 as well for consistency. Note that there is one
9
instance of a pre-assert fprintf that used the wrong value for the
10
address of the current instruction.
11
12
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
13
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
14
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Message-id: 20190807045335.1361-3-richard.henderson@linaro.org
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
17
---
10
include/hw/arm/xlnx-versal.h | 2 +-
18
target/arm/translate-a64.h | 2 +-
11
1 file changed, 1 insertion(+), 1 deletion(-)
19
target/arm/translate.h | 2 ++
12
20
target/arm/translate-a64.c | 21 +++++++++++----------
13
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
21
target/arm/translate.c | 14 ++++++++------
14
index XXXXXXX..XXXXXXX 100644
22
4 files changed, 22 insertions(+), 17 deletions(-)
15
--- a/include/hw/arm/xlnx-versal.h
23
16
+++ b/include/hw/arm/xlnx-versal.h
24
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
17
@@ -XXX,XX +XXX,XX @@
25
index XXXXXXX..XXXXXXX 100644
18
#define XLNX_VERSAL_NR_ACPUS 2
26
--- a/target/arm/translate-a64.h
19
#define XLNX_VERSAL_NR_UARTS 2
27
+++ b/target/arm/translate-a64.h
20
#define XLNX_VERSAL_NR_GEMS 2
28
@@ -XXX,XX +XXX,XX @@ void unallocated_encoding(DisasContext *s);
21
-#define XLNX_VERSAL_NR_IRQS 256
29
qemu_log_mask(LOG_UNIMP, \
22
+#define XLNX_VERSAL_NR_IRQS 192
30
"%s:%d: unsupported instruction encoding 0x%08x " \
23
31
"at pc=%016" PRIx64 "\n", \
24
typedef struct Versal {
32
- __FILE__, __LINE__, insn, s->pc - 4); \
25
/*< private >*/
33
+ __FILE__, __LINE__, insn, s->pc_curr); \
34
unallocated_encoding(s); \
35
} while (0)
36
37
diff --git a/target/arm/translate.h b/target/arm/translate.h
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/translate.h
40
+++ b/target/arm/translate.h
41
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
42
const ARMISARegisters *isar;
43
44
target_ulong pc;
45
+ /* The address of the current instruction being translated. */
46
+ target_ulong pc_curr;
47
target_ulong page_start;
48
uint32_t insn;
49
/* Nonzero if this instruction has been conditionally skipped. */
50
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/target/arm/translate-a64.c
53
+++ b/target/arm/translate-a64.c
54
@@ -XXX,XX +XXX,XX @@ static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table,
55
*/
56
static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
57
{
58
- uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4;
59
+ uint64_t addr = s->pc_curr + sextract32(insn, 0, 26) * 4;
60
61
if (insn & (1U << 31)) {
62
/* BL Branch with link */
63
@@ -XXX,XX +XXX,XX @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
64
sf = extract32(insn, 31, 1);
65
op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */
66
rt = extract32(insn, 0, 5);
67
- addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
68
+ addr = s->pc_curr + sextract32(insn, 5, 19) * 4;
69
70
tcg_cmp = read_cpu_reg(s, rt, sf);
71
label_match = gen_new_label();
72
@@ -XXX,XX +XXX,XX @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn)
73
74
bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5);
75
op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */
76
- addr = s->pc + sextract32(insn, 5, 14) * 4 - 4;
77
+ addr = s->pc_curr + sextract32(insn, 5, 14) * 4;
78
rt = extract32(insn, 0, 5);
79
80
tcg_cmp = tcg_temp_new_i64();
81
@@ -XXX,XX +XXX,XX @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
82
unallocated_encoding(s);
83
return;
84
}
85
- addr = s->pc + sextract32(insn, 5, 19) * 4 - 4;
86
+ addr = s->pc_curr + sextract32(insn, 5, 19) * 4;
87
cond = extract32(insn, 0, 4);
88
89
reset_btype(s);
90
@@ -XXX,XX +XXX,XX @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
91
TCGv_i32 tcg_syn, tcg_isread;
92
uint32_t syndrome;
93
94
- gen_a64_set_pc_im(s->pc - 4);
95
+ gen_a64_set_pc_im(s->pc_curr);
96
tmpptr = tcg_const_ptr(ri);
97
syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread);
98
tcg_syn = tcg_const_i32(syndrome);
99
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
100
/* The pre HVC helper handles cases when HVC gets trapped
101
* as an undefined insn by runtime configuration.
102
*/
103
- gen_a64_set_pc_im(s->pc - 4);
104
+ gen_a64_set_pc_im(s->pc_curr);
105
gen_helper_pre_hvc(cpu_env);
106
gen_ss_advance(s);
107
gen_exception_insn(s, 0, EXCP_HVC, syn_aa64_hvc(imm16), 2);
108
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
109
unallocated_encoding(s);
110
break;
111
}
112
- gen_a64_set_pc_im(s->pc - 4);
113
+ gen_a64_set_pc_im(s->pc_curr);
114
tmp = tcg_const_i32(syn_aa64_smc(imm16));
115
gen_helper_pre_smc(cpu_env, tmp);
116
tcg_temp_free_i32(tmp);
117
@@ -XXX,XX +XXX,XX @@ static void disas_ld_lit(DisasContext *s, uint32_t insn)
118
119
tcg_rt = cpu_reg(s, rt);
120
121
- clean_addr = tcg_const_i64((s->pc - 4) + imm);
122
+ clean_addr = tcg_const_i64(s->pc_curr + imm);
123
if (is_vector) {
124
do_fp_ld(s, rt, clean_addr, size);
125
} else {
126
@@ -XXX,XX +XXX,XX @@ static void disas_pc_rel_adr(DisasContext *s, uint32_t insn)
127
offset = sextract64(insn, 5, 19);
128
offset = offset << 2 | extract32(insn, 29, 2);
129
rd = extract32(insn, 0, 5);
130
- base = s->pc - 4;
131
+ base = s->pc_curr;
132
133
if (page) {
134
/* ADRP (page based) */
135
@@ -XXX,XX +XXX,XX @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
136
break;
137
default:
138
fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
139
- __func__, insn, fpopcode, s->pc);
140
+ __func__, insn, fpopcode, s->pc_curr);
141
g_assert_not_reached();
142
}
143
144
@@ -XXX,XX +XXX,XX @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
145
{
146
uint32_t insn;
147
148
+ s->pc_curr = s->pc;
149
insn = arm_ldl_code(env, s->pc, s->sctlr_b);
150
s->insn = insn;
151
s->pc += 4;
152
diff --git a/target/arm/translate.c b/target/arm/translate.c
153
index XXXXXXX..XXXXXXX 100644
154
--- a/target/arm/translate.c
155
+++ b/target/arm/translate.c
156
@@ -XXX,XX +XXX,XX @@ static inline void gen_hvc(DisasContext *s, int imm16)
157
* as an undefined insn by runtime configuration (ie before
158
* the insn really executes).
159
*/
160
- gen_set_pc_im(s, s->pc - 4);
161
+ gen_set_pc_im(s, s->pc_curr);
162
gen_helper_pre_hvc(cpu_env);
163
/* Otherwise we will treat this as a real exception which
164
* happens after execution of the insn. (The distinction matters
165
@@ -XXX,XX +XXX,XX @@ static inline void gen_smc(DisasContext *s)
166
*/
167
TCGv_i32 tmp;
168
169
- gen_set_pc_im(s, s->pc - 4);
170
+ gen_set_pc_im(s, s->pc_curr);
171
tmp = tcg_const_i32(syn_aa32_smc());
172
gen_helper_pre_smc(cpu_env, tmp);
173
tcg_temp_free_i32(tmp);
174
@@ -XXX,XX +XXX,XX @@ static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn)
175
176
/* Sync state because msr_banked() can raise exceptions */
177
gen_set_condexec(s);
178
- gen_set_pc_im(s, s->pc - 4);
179
+ gen_set_pc_im(s, s->pc_curr);
180
tcg_reg = load_reg(s, rn);
181
tcg_tgtmode = tcg_const_i32(tgtmode);
182
tcg_regno = tcg_const_i32(regno);
183
@@ -XXX,XX +XXX,XX @@ static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn)
184
185
/* Sync state because mrs_banked() can raise exceptions */
186
gen_set_condexec(s);
187
- gen_set_pc_im(s, s->pc - 4);
188
+ gen_set_pc_im(s, s->pc_curr);
189
tcg_reg = tcg_temp_new_i32();
190
tcg_tgtmode = tcg_const_i32(tgtmode);
191
tcg_regno = tcg_const_i32(regno);
192
@@ -XXX,XX +XXX,XX @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
193
}
194
195
gen_set_condexec(s);
196
- gen_set_pc_im(s, s->pc - 4);
197
+ gen_set_pc_im(s, s->pc_curr);
198
tmpptr = tcg_const_ptr(ri);
199
tcg_syn = tcg_const_i32(syndrome);
200
tcg_isread = tcg_const_i32(isread);
201
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
202
tmp = tcg_const_i32(mode);
203
/* get_r13_banked() will raise an exception if called from System mode */
204
gen_set_condexec(s);
205
- gen_set_pc_im(s, s->pc - 4);
206
+ gen_set_pc_im(s, s->pc_curr);
207
gen_helper_get_r13_banked(addr, cpu_env, tmp);
208
tcg_temp_free_i32(tmp);
209
switch (amode) {
210
@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
211
return;
212
}
213
214
+ dc->pc_curr = dc->pc;
215
insn = arm_ldl_code(env, dc->pc, dc->sctlr_b);
216
dc->insn = insn;
217
dc->pc += 4;
218
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
219
return;
220
}
221
222
+ dc->pc_curr = dc->pc;
223
insn = arm_lduw_code(env, dc->pc, dc->sctlr_b);
224
is_16bit = thumb_insn_is_16bit(dc, dc->pc, insn);
225
dc->pc += 2;
26
--
226
--
27
2.19.2
227
2.20.1
28
228
29
229
diff view generated by jsdifflib
[Qemu-devel] [PULL 33/37] target/arm: Implement the ARMv8.1-HPD extension
[Qemu-devel] [PULL 08/29] target/arm: Introduce read_pc
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Since the TCR_*.HPD bits were RES0 in ARMv8.0, we can simply
3
We currently have 3 different ways of computing the architectural
4
interpret the bits as if ARMv8.1-HPD is present without checking.
4
value of "PC" as seen in the ARM ARM.
5
We will need a slightly different check for hpd for aarch32.
5
6
6
The value of s->pc has been incremented past the current insn,
7
but that is all. Thus for a32, PC = s->pc + 4; for t32, PC = s->pc;
8
for t16, PC = s->pc + 2. These differing computations make it
9
impossible at present to unify the various code paths.
10
11
With the newly introduced s->pc_curr, we can compute the correct
12
value for all cases, using the formula given in the ARM ARM.
13
14
This changes the behaviour for load_reg() and load_reg_var()
15
when called with reg==15 from a 32-bit Thumb instruction:
16
previously they would have returned the incorrect value
17
of pc_curr + 6, and now they will return the architecturally
18
correct value of PC, which is pc_curr + 4. This will not
19
affect well-behaved guest software, because all of the places
20
we call these functions from T32 code are instructions where
21
using r15 is UNPREDICTABLE. Using the architectural PC value
22
here is more consistent with the T16 and A32 behaviour.
23
24
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
25
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
26
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Message-id: 20181203203839.757-10-richard.henderson@linaro.org
27
Message-id: 20190807045335.1361-4-richard.henderson@linaro.org
28
[PMM: added commit message note about UNPREDICTABLE T32 cases]
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
29
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
30
---
12
target/arm/cpu64.c | 4 ++++
31
target/arm/translate.c | 59 ++++++++++++++++--------------------------
13
target/arm/helper.c | 27 ++++++++++++++++++++-------
32
1 file changed, 23 insertions(+), 36 deletions(-)
14
2 files changed, 24 insertions(+), 7 deletions(-)
33
15
34
diff --git a/target/arm/translate.c b/target/arm/translate.c
16
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
17
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/cpu64.c
36
--- a/target/arm/translate.c
19
+++ b/target/arm/cpu64.c
37
+++ b/target/arm/translate.c
20
@@ -XXX,XX +XXX,XX @@ static void aarch64_max_initfn(Object *obj)
38
@@ -XXX,XX +XXX,XX @@ static inline void store_cpu_offset(TCGv_i32 var, int offset)
21
t = FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1);
39
#define store_cpu_field(var, name) \
22
cpu->isar.id_aa64pfr0 = t;
40
store_cpu_offset(var, offsetof(CPUARMState, name))
23
41
24
+ t = cpu->isar.id_aa64mmfr1;
42
+/* The architectural value of PC. */
25
+ t = FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */
43
+static uint32_t read_pc(DisasContext *s)
26
+ cpu->isar.id_aa64mmfr1 = t;
44
+{
45
+ return s->pc_curr + (s->thumb ? 4 : 8);
46
+}
27
+
47
+
28
/* Replicate the same data to the 32-bit id registers. */
48
/* Set a variable to the value of a CPU register. */
29
u = cpu->isar.id_isar5;
49
static void load_reg_var(DisasContext *s, TCGv_i32 var, int reg)
30
u = FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */
50
{
31
diff --git a/target/arm/helper.c b/target/arm/helper.c
51
if (reg == 15) {
32
index XXXXXXX..XXXXXXX 100644
52
- uint32_t addr;
33
--- a/target/arm/helper.c
53
- /* normally, since we updated PC, we need only to add one insn */
34
+++ b/target/arm/helper.c
54
- if (s->thumb)
35
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
55
- addr = (long)s->pc + 2;
36
bool ttbr1_valid = true;
56
- else
37
uint64_t descaddrmask;
57
- addr = (long)s->pc + 4;
38
bool aarch64 = arm_el_is_aa64(env, el);
58
- tcg_gen_movi_i32(var, addr);
39
+ bool hpd = false;
59
+ tcg_gen_movi_i32(var, read_pc(s));
40
60
} else {
41
/* TODO:
61
tcg_gen_mov_i32(var, cpu_R[reg]);
42
* This code does not handle the different format TCR for VTCR_EL2.
62
}
43
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
63
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
44
if (tg == 2) { /* 16KB pages */
64
/* branch link and change to thumb (blx <offset>) */
45
stride = 11;
65
int32_t offset;
66
67
- val = (uint32_t)s->pc;
68
tmp = tcg_temp_new_i32();
69
- tcg_gen_movi_i32(tmp, val);
70
+ tcg_gen_movi_i32(tmp, s->pc);
71
store_reg(s, 14, tmp);
72
/* Sign-extend the 24-bit offset */
73
offset = (((int32_t)insn) << 8) >> 8;
74
+ val = read_pc(s);
75
/* offset * 4 + bit24 * 2 + (thumb bit) */
76
val += (offset << 2) | ((insn >> 23) & 2) | 1;
77
- /* pipeline offset */
78
- val += 4;
79
/* protected by ARCH(5); above, near the start of uncond block */
80
gen_bx_im(s, val);
81
return;
82
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
83
} else {
84
/* store */
85
if (i == 15) {
86
- /* special case: r15 = PC + 8 */
87
- val = (long)s->pc + 4;
88
tmp = tcg_temp_new_i32();
89
- tcg_gen_movi_i32(tmp, val);
90
+ tcg_gen_movi_i32(tmp, read_pc(s));
91
} else if (user) {
92
tmp = tcg_temp_new_i32();
93
tmp2 = tcg_const_i32(i);
94
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
95
int32_t offset;
96
97
/* branch (and link) */
98
- val = (int32_t)s->pc;
99
if (insn & (1 << 24)) {
100
tmp = tcg_temp_new_i32();
101
- tcg_gen_movi_i32(tmp, val);
102
+ tcg_gen_movi_i32(tmp, s->pc);
103
store_reg(s, 14, tmp);
104
}
105
offset = sextract32(insn << 2, 0, 26);
106
- val += offset + 4;
107
- gen_jmp(s, val);
108
+ gen_jmp(s, read_pc(s) + offset);
109
}
110
break;
111
case 0xc:
112
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
113
tcg_temp_free_i32(addr);
114
} else if ((insn & (7 << 5)) == 0) {
115
/* Table Branch. */
116
- if (rn == 15) {
117
- addr = tcg_temp_new_i32();
118
- tcg_gen_movi_i32(addr, s->pc);
119
- } else {
120
- addr = load_reg(s, rn);
121
- }
122
+ addr = load_reg(s, rn);
123
tmp = load_reg(s, rm);
124
tcg_gen_add_i32(addr, addr, tmp);
125
if (insn & (1 << 4)) {
126
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
127
}
128
tcg_temp_free_i32(addr);
129
tcg_gen_shli_i32(tmp, tmp, 1);
130
- tcg_gen_addi_i32(tmp, tmp, s->pc);
131
+ tcg_gen_addi_i32(tmp, tmp, read_pc(s));
132
store_reg(s, 15, tmp);
133
} else {
134
bool is_lasr = false;
135
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
136
tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
137
}
138
139
- offset += s->pc;
140
+ offset += read_pc(s);
141
if (insn & (1 << 12)) {
142
/* b/bl */
143
gen_jmp(s, offset);
144
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
145
offset |= (insn & (1 << 11)) << 8;
146
147
/* jump to the offset */
148
- gen_jmp(s, s->pc + offset);
149
+ gen_jmp(s, read_pc(s) + offset);
150
}
151
} else {
152
/*
153
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
154
if (insn & (1 << 11)) {
155
rd = (insn >> 8) & 7;
156
/* load pc-relative. Bit 1 of PC is ignored. */
157
- val = s->pc + 2 + ((insn & 0xff) * 4);
158
+ val = read_pc(s) + ((insn & 0xff) * 4);
159
val &= ~(uint32_t)2;
160
addr = tcg_temp_new_i32();
161
tcg_gen_movi_i32(addr, val);
162
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
163
} else {
164
/* PC. bit 1 is ignored. */
165
tmp = tcg_temp_new_i32();
166
- tcg_gen_movi_i32(tmp, (s->pc + 2) & ~(uint32_t)2);
167
+ tcg_gen_movi_i32(tmp, read_pc(s) & ~(uint32_t)2);
46
}
168
}
47
+ if (aarch64) {
169
val = (insn & 0xff) * 4;
48
+ if (el > 1) {
170
tcg_gen_addi_i32(tmp, tmp, val);
49
+ hpd = extract64(tcr->raw_tcr, 24, 1);
171
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
50
+ } else {
172
tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 0, s->condlabel);
51
+ hpd = extract64(tcr->raw_tcr, 41, 1);
173
tcg_temp_free_i32(tmp);
52
+ }
174
offset = ((insn & 0xf8) >> 2) | (insn & 0x200) >> 3;
53
+ }
175
- val = (uint32_t)s->pc + 2;
54
} else {
176
- val += offset;
55
/* We should only be here if TTBR1 is valid */
177
- gen_jmp(s, val);
56
assert(ttbr1_valid);
178
+ gen_jmp(s, read_pc(s) + offset);
57
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
179
break;
58
if (tg == 1) { /* 16KB pages */
180
59
stride = 11;
181
case 15: /* IT, nop-hint. */
60
}
182
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
61
+ if (aarch64) {
183
arm_skip_unless(s, cond);
62
+ hpd = extract64(tcr->raw_tcr, 42, 1);
184
63
+ }
185
/* jump to the offset */
64
}
186
- val = (uint32_t)s->pc + 2;
65
187
+ val = read_pc(s);
66
/* Here we should have set up all the parameters for the translation:
188
offset = ((int32_t)insn << 24) >> 24;
67
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
189
val += offset << 1;
68
descaddr = descriptor & descaddrmask;
190
gen_jmp(s, val);
69
191
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
70
if ((descriptor & 2) && (level < 3)) {
71
- /* Table entry. The top five bits are attributes which may
72
+ /* Table entry. The top five bits are attributes which may
73
* propagate down through lower levels of the table (and
74
* which are all arranged so that 0 means "no effect", so
75
* we can gather them up by ORing in the bits at each level).
76
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
77
break;
192
break;
78
}
193
}
79
/* Merge in attributes from table descriptors */
194
/* unconditional branch */
80
- attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
195
- val = (uint32_t)s->pc;
81
- attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
196
+ val = read_pc(s);
82
+ attrs |= nstable << 3; /* NS */
197
offset = ((int32_t)insn << 21) >> 21;
83
+ if (hpd) {
198
- val += (offset << 1) + 2;
84
+ /* HPD disables all the table attributes except NSTable. */
199
+ val += offset << 1;
85
+ break;
200
gen_jmp(s, val);
86
+ }
201
break;
87
+ attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
202
88
/* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
203
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
89
* means "force PL1 access only", which means forcing AP[1] to 0.
204
/* 0b1111_0xxx_xxxx_xxxx : BL/BLX prefix */
90
*/
205
uint32_t uoffset = ((int32_t)insn << 21) >> 9;
91
- if (extract32(tableattrs, 2, 1)) {
206
92
- attrs &= ~(1 << 4);
207
- tcg_gen_movi_i32(cpu_R[14], s->pc + 2 + uoffset);
93
- }
208
+ tcg_gen_movi_i32(cpu_R[14], read_pc(s) + uoffset);
94
- attrs |= nstable << 3; /* NS */
209
}
95
+ attrs &= ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] => AP[1] */
96
+ attrs |= extract32(tableattrs, 3, 1) << 5; /* APT[1] => AP[2] */
97
break;
210
break;
98
}
211
}
99
/* Here descaddr is the final physical address, and attributes
100
--
212
--
101
2.19.2
213
2.20.1
102
214
103
215
diff view generated by jsdifflib
[Qemu-devel] [PULL 08/37] dma/puv3_dma: Convert sysbus init function to realize function
[Qemu-devel] [PULL 09/29] target/arm: Introduce add_reg_for_lit
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Use DeviceClass rather than SysBusDeviceClass in
3
Provide a common routine for the places that require ALIGN(PC, 4)
4
puv3_dma_class_init().
4
as the base address as opposed to plain PC. The two are always
5
5
the same for A32, but the difference is meaningful for thumb mode.
6
Cc: gxt@mprc.pku.edu.cn
6
7
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
9
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Message-id: 20181130093852.20739-7-maozhongyi@cmss.chinamobile.com
10
Message-id: 20190807045335.1361-5-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
12
---
15
hw/dma/puv3_dma.c | 10 ++++------
13
target/arm/translate-vfp.inc.c | 38 ++------
16
1 file changed, 4 insertions(+), 6 deletions(-)
14
target/arm/translate.c | 166 +++++++++++++++------------------
17
15
2 files changed, 82 insertions(+), 122 deletions(-)
18
diff --git a/hw/dma/puv3_dma.c b/hw/dma/puv3_dma.c
16
17
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
19
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/dma/puv3_dma.c
19
--- a/target/arm/translate-vfp.inc.c
21
+++ b/hw/dma/puv3_dma.c
20
+++ b/target/arm/translate-vfp.inc.c
22
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps puv3_dma_ops = {
21
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VLDR_VSTR_sp *a)
23
.endianness = DEVICE_NATIVE_ENDIAN,
22
offset = -offset;
24
};
23
}
25
24
26
-static int puv3_dma_init(SysBusDevice *dev)
25
- if (s->thumb && a->rn == 15) {
27
+static void puv3_dma_realize(DeviceState *dev, Error **errp)
26
- /* This is actually UNPREDICTABLE */
28
{
27
- addr = tcg_temp_new_i32();
29
PUV3DMAState *s = PUV3_DMA(dev);
28
- tcg_gen_movi_i32(addr, s->pc & ~2);
30
int i;
29
- } else {
31
@@ -XXX,XX +XXX,XX @@ static int puv3_dma_init(SysBusDevice *dev)
30
- addr = load_reg(s, a->rn);
32
31
- }
33
memory_region_init_io(&s->iomem, OBJECT(s), &puv3_dma_ops, s, "puv3_dma",
32
- tcg_gen_addi_i32(addr, addr, offset);
34
PUV3_REGS_OFFSET);
33
+ /* For thumb, use of PC is UNPREDICTABLE. */
35
- sysbus_init_mmio(dev, &s->iomem);
34
+ addr = add_reg_for_lit(s, a->rn, offset);
36
-
35
tmp = tcg_temp_new_i32();
37
- return 0;
36
if (a->l) {
38
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
37
gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
38
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLDR_VSTR_dp *a)
39
offset = -offset;
40
}
41
42
- if (s->thumb && a->rn == 15) {
43
- /* This is actually UNPREDICTABLE */
44
- addr = tcg_temp_new_i32();
45
- tcg_gen_movi_i32(addr, s->pc & ~2);
46
- } else {
47
- addr = load_reg(s, a->rn);
48
- }
49
- tcg_gen_addi_i32(addr, addr, offset);
50
+ /* For thumb, use of PC is UNPREDICTABLE. */
51
+ addr = add_reg_for_lit(s, a->rn, offset);
52
tmp = tcg_temp_new_i64();
53
if (a->l) {
54
gen_aa32_ld64(s, tmp, addr, get_mem_index(s));
55
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_VLDM_VSTM_sp *a)
56
return true;
57
}
58
59
- if (s->thumb && a->rn == 15) {
60
- /* This is actually UNPREDICTABLE */
61
- addr = tcg_temp_new_i32();
62
- tcg_gen_movi_i32(addr, s->pc & ~2);
63
- } else {
64
- addr = load_reg(s, a->rn);
65
- }
66
+ /* For thumb, use of PC is UNPREDICTABLE. */
67
+ addr = add_reg_for_lit(s, a->rn, 0);
68
if (a->p) {
69
/* pre-decrement */
70
tcg_gen_addi_i32(addr, addr, -(a->imm << 2));
71
@@ -XXX,XX +XXX,XX @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_VLDM_VSTM_dp *a)
72
return true;
73
}
74
75
- if (s->thumb && a->rn == 15) {
76
- /* This is actually UNPREDICTABLE */
77
- addr = tcg_temp_new_i32();
78
- tcg_gen_movi_i32(addr, s->pc & ~2);
79
- } else {
80
- addr = load_reg(s, a->rn);
81
- }
82
+ /* For thumb, use of PC is UNPREDICTABLE. */
83
+ addr = add_reg_for_lit(s, a->rn, 0);
84
if (a->p) {
85
/* pre-decrement */
86
tcg_gen_addi_i32(addr, addr, -(a->imm << 2));
87
diff --git a/target/arm/translate.c b/target/arm/translate.c
88
index XXXXXXX..XXXXXXX 100644
89
--- a/target/arm/translate.c
90
+++ b/target/arm/translate.c
91
@@ -XXX,XX +XXX,XX @@ static inline TCGv_i32 load_reg(DisasContext *s, int reg)
92
return tmp;
39
}
93
}
40
94
41
static void puv3_dma_class_init(ObjectClass *klass, void *data)
95
+/*
42
{
96
+ * Create a new temp, REG + OFS, except PC is ALIGN(PC, 4).
43
- SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
97
+ * This is used for load/store for which use of PC implies (literal),
44
+ DeviceClass *dc = DEVICE_CLASS(klass);
98
+ * or ADD that implies ADR.
45
99
+ */
46
- sdc->init = puv3_dma_init;
100
+static TCGv_i32 add_reg_for_lit(DisasContext *s, int reg, int ofs)
47
+ dc->realize = puv3_dma_realize;
101
+{
48
}
102
+ TCGv_i32 tmp = tcg_temp_new_i32();
49
103
+
50
static const TypeInfo puv3_dma_info = {
104
+ if (reg == 15) {
105
+ tcg_gen_movi_i32(tmp, (read_pc(s) & ~3) + ofs);
106
+ } else {
107
+ tcg_gen_addi_i32(tmp, cpu_R[reg], ofs);
108
+ }
109
+ return tmp;
110
+}
111
+
112
/* Set a CPU register. The source must be a temporary and will be
113
marked as dead. */
114
static void store_reg(DisasContext *s, int reg, TCGv_i32 var)
115
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
116
*/
117
bool wback = extract32(insn, 21, 1);
118
119
- if (rn == 15) {
120
- if (insn & (1 << 21)) {
121
- /* UNPREDICTABLE */
122
- goto illegal_op;
123
- }
124
- addr = tcg_temp_new_i32();
125
- tcg_gen_movi_i32(addr, s->pc & ~3);
126
- } else {
127
- addr = load_reg(s, rn);
128
+ if (rn == 15 && (insn & (1 << 21))) {
129
+ /* UNPREDICTABLE */
130
+ goto illegal_op;
131
}
132
+
133
+ addr = add_reg_for_lit(s, rn, 0);
134
offset = (insn & 0xff) * 4;
135
if ((insn & (1 << 23)) == 0) {
136
offset = -offset;
137
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
138
store_reg(s, rd, tmp);
139
} else {
140
/* Add/sub 12-bit immediate. */
141
- if (rn == 15) {
142
- offset = s->pc & ~(uint32_t)3;
143
- if (insn & (1 << 23))
144
- offset -= imm;
145
- else
146
- offset += imm;
147
- tmp = tcg_temp_new_i32();
148
- tcg_gen_movi_i32(tmp, offset);
149
- store_reg(s, rd, tmp);
150
+ if (insn & (1 << 23)) {
151
+ imm = -imm;
152
+ }
153
+ tmp = add_reg_for_lit(s, rn, imm);
154
+ if (rn == 13 && rd == 13) {
155
+ /* ADD SP, SP, imm or SUB SP, SP, imm */
156
+ store_sp_checked(s, tmp);
157
} else {
158
- tmp = load_reg(s, rn);
159
- if (insn & (1 << 23))
160
- tcg_gen_subi_i32(tmp, tmp, imm);
161
- else
162
- tcg_gen_addi_i32(tmp, tmp, imm);
163
- if (rn == 13 && rd == 13) {
164
- /* ADD SP, SP, imm or SUB SP, SP, imm */
165
- store_sp_checked(s, tmp);
166
- } else {
167
- store_reg(s, rd, tmp);
168
- }
169
+ store_reg(s, rd, tmp);
170
}
171
}
172
}
173
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
174
}
175
}
176
memidx = get_mem_index(s);
177
- if (rn == 15) {
178
- addr = tcg_temp_new_i32();
179
- /* PC relative. */
180
- /* s->pc has already been incremented by 4. */
181
- imm = s->pc & 0xfffffffc;
182
- if (insn & (1 << 23))
183
- imm += insn & 0xfff;
184
- else
185
- imm -= insn & 0xfff;
186
- tcg_gen_movi_i32(addr, imm);
187
+ imm = insn & 0xfff;
188
+ if (insn & (1 << 23)) {
189
+ /* PC relative or Positive offset. */
190
+ addr = add_reg_for_lit(s, rn, imm);
191
+ } else if (rn == 15) {
192
+ /* PC relative with negative offset. */
193
+ addr = add_reg_for_lit(s, rn, -imm);
194
} else {
195
addr = load_reg(s, rn);
196
- if (insn & (1 << 23)) {
197
- /* Positive offset. */
198
- imm = insn & 0xfff;
199
- tcg_gen_addi_i32(addr, addr, imm);
200
- } else {
201
- imm = insn & 0xff;
202
- switch ((insn >> 8) & 0xf) {
203
- case 0x0: /* Shifted Register. */
204
- shift = (insn >> 4) & 0xf;
205
- if (shift > 3) {
206
- tcg_temp_free_i32(addr);
207
- goto illegal_op;
208
- }
209
- tmp = load_reg(s, rm);
210
- if (shift)
211
- tcg_gen_shli_i32(tmp, tmp, shift);
212
- tcg_gen_add_i32(addr, addr, tmp);
213
- tcg_temp_free_i32(tmp);
214
- break;
215
- case 0xc: /* Negative offset. */
216
- tcg_gen_addi_i32(addr, addr, -imm);
217
- break;
218
- case 0xe: /* User privilege. */
219
- tcg_gen_addi_i32(addr, addr, imm);
220
- memidx = get_a32_user_mem_index(s);
221
- break;
222
- case 0x9: /* Post-decrement. */
223
- imm = -imm;
224
- /* Fall through. */
225
- case 0xb: /* Post-increment. */
226
- postinc = 1;
227
- writeback = 1;
228
- break;
229
- case 0xd: /* Pre-decrement. */
230
- imm = -imm;
231
- /* Fall through. */
232
- case 0xf: /* Pre-increment. */
233
- writeback = 1;
234
- break;
235
- default:
236
+ imm = insn & 0xff;
237
+ switch ((insn >> 8) & 0xf) {
238
+ case 0x0: /* Shifted Register. */
239
+ shift = (insn >> 4) & 0xf;
240
+ if (shift > 3) {
241
tcg_temp_free_i32(addr);
242
goto illegal_op;
243
}
244
+ tmp = load_reg(s, rm);
245
+ if (shift) {
246
+ tcg_gen_shli_i32(tmp, tmp, shift);
247
+ }
248
+ tcg_gen_add_i32(addr, addr, tmp);
249
+ tcg_temp_free_i32(tmp);
250
+ break;
251
+ case 0xc: /* Negative offset. */
252
+ tcg_gen_addi_i32(addr, addr, -imm);
253
+ break;
254
+ case 0xe: /* User privilege. */
255
+ tcg_gen_addi_i32(addr, addr, imm);
256
+ memidx = get_a32_user_mem_index(s);
257
+ break;
258
+ case 0x9: /* Post-decrement. */
259
+ imm = -imm;
260
+ /* Fall through. */
261
+ case 0xb: /* Post-increment. */
262
+ postinc = 1;
263
+ writeback = 1;
264
+ break;
265
+ case 0xd: /* Pre-decrement. */
266
+ imm = -imm;
267
+ /* Fall through. */
268
+ case 0xf: /* Pre-increment. */
269
+ writeback = 1;
270
+ break;
271
+ default:
272
+ tcg_temp_free_i32(addr);
273
+ goto illegal_op;
274
}
275
}
276
277
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
278
if (insn & (1 << 11)) {
279
rd = (insn >> 8) & 7;
280
/* load pc-relative. Bit 1 of PC is ignored. */
281
- val = read_pc(s) + ((insn & 0xff) * 4);
282
- val &= ~(uint32_t)2;
283
- addr = tcg_temp_new_i32();
284
- tcg_gen_movi_i32(addr, val);
285
+ addr = add_reg_for_lit(s, 15, (insn & 0xff) * 4);
286
tmp = tcg_temp_new_i32();
287
gen_aa32_ld32u_iss(s, tmp, addr, get_mem_index(s),
288
rd | ISSIs16Bit);
289
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
290
* - Add PC/SP (immediate)
291
*/
292
rd = (insn >> 8) & 7;
293
- if (insn & (1 << 11)) {
294
- /* SP */
295
- tmp = load_reg(s, 13);
296
- } else {
297
- /* PC. bit 1 is ignored. */
298
- tmp = tcg_temp_new_i32();
299
- tcg_gen_movi_i32(tmp, read_pc(s) & ~(uint32_t)2);
300
- }
301
val = (insn & 0xff) * 4;
302
- tcg_gen_addi_i32(tmp, tmp, val);
303
+ tmp = add_reg_for_lit(s, insn & (1 << 11) ? 13 : 15, val);
304
store_reg(s, rd, tmp);
305
break;
306
51
--
307
--
52
2.19.2
308
2.20.1
53
309
54
310
diff view generated by jsdifflib
[Qemu-devel] [PULL 15/37] puv3_pm.c: Convert sysbus init function to realize function
[Qemu-devel] [PULL 10/29] target/arm: Remove redundant s->pc & ~1
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Use DeviceClass rather than SysBusDeviceClass in
3
The thumb bit has already been removed from s->pc, and is always even.
4
puv3_pm_class_init().
5
4
6
Cc: gxt@mprc.pku.edu.cn
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
8
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
9
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
6
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Message-id: 20181130093852.20739-14-maozhongyi@cmss.chinamobile.com
8
Message-id: 20190807045335.1361-6-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
10
---
15
hw/misc/puv3_pm.c | 10 ++++------
11
target/arm/translate.c | 10 +++++-----
16
1 file changed, 4 insertions(+), 6 deletions(-)
12
1 file changed, 5 insertions(+), 5 deletions(-)
17
13
18
diff --git a/hw/misc/puv3_pm.c b/hw/misc/puv3_pm.c
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
19
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/misc/puv3_pm.c
16
--- a/target/arm/translate.c
21
+++ b/hw/misc/puv3_pm.c
17
+++ b/target/arm/translate.c
22
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps puv3_pm_ops = {
18
@@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, int offset, uint32_t syn)
23
.endianness = DEVICE_NATIVE_ENDIAN,
19
/* Force a TB lookup after an instruction that changes the CPU state. */
24
};
20
static inline void gen_lookup_tb(DisasContext *s)
25
26
-static int puv3_pm_init(SysBusDevice *dev)
27
+static void puv3_pm_realize(DeviceState *dev, Error **errp)
28
{
21
{
29
PUV3PMState *s = PUV3_PM(dev);
22
- tcg_gen_movi_i32(cpu_R[15], s->pc & ~1);
30
23
+ tcg_gen_movi_i32(cpu_R[15], s->pc);
31
@@ -XXX,XX +XXX,XX @@ static int puv3_pm_init(SysBusDevice *dev)
24
s->base.is_jmp = DISAS_EXIT;
32
33
memory_region_init_io(&s->iomem, OBJECT(s), &puv3_pm_ops, s, "puv3_pm",
34
PUV3_REGS_OFFSET);
35
- sysbus_init_mmio(dev, &s->iomem);
36
-
37
- return 0;
38
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
39
}
25
}
40
26
41
static void puv3_pm_class_init(ObjectClass *klass, void *data)
27
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
42
{
28
* self-modifying code correctly and also to take
43
- SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
29
* any pending interrupts immediately.
44
+ DeviceClass *dc = DEVICE_CLASS(klass);
30
*/
45
31
- gen_goto_tb(s, 0, s->pc & ~1);
46
- sdc->init = puv3_pm_init;
32
+ gen_goto_tb(s, 0, s->pc);
47
+ dc->realize = puv3_pm_realize;
33
return;
48
}
34
case 7: /* sb */
49
35
if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) {
50
static const TypeInfo puv3_pm_info = {
36
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
37
* for TCG; MB and end the TB instead.
38
*/
39
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
40
- gen_goto_tb(s, 0, s->pc & ~1);
41
+ gen_goto_tb(s, 0, s->pc);
42
return;
43
default:
44
goto illegal_op;
45
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
46
* and also to take any pending interrupts
47
* immediately.
48
*/
49
- gen_goto_tb(s, 0, s->pc & ~1);
50
+ gen_goto_tb(s, 0, s->pc);
51
break;
52
case 7: /* sb */
53
if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) {
54
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
55
* for TCG; MB and end the TB instead.
56
*/
57
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
58
- gen_goto_tb(s, 0, s->pc & ~1);
59
+ gen_goto_tb(s, 0, s->pc);
60
break;
61
default:
62
goto illegal_op;
51
--
63
--
52
2.19.2
64
2.20.1
53
65
54
66
diff view generated by jsdifflib
[Qemu-devel] [PULL 26/37] hw/arm: versal: Use IRQs 111 - 118 for virtio-mmio
[Qemu-devel] [PULL 11/29] target/arm: Replace s->pc with s->base.pc_next
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Use IRQs 111 - 118 for virtio-mmio. The interrupts we're currently
3
We must update s->base.pc_next when we return from the translate_insn
4
using 160+ are not available in the Versal GIC.
4
hook to the main translator loop. By incrementing s->base.pc_next
5
immediately after reading the insn word, "pc_next" contains the address
6
of the next instruction throughout translation.
5
7
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8
All remaining uses of s->pc are referencing the address of the next insn,
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
9
so this is now a simple global replacement. Remove the "s->pc" field.
8
Message-id: 20181129163655.20370-4-edgar.iglesias@gmail.com
10
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
13
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
14
Message-id: 20190807045335.1361-7-richard.henderson@linaro.org
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
16
---
11
include/hw/arm/xlnx-versal.h | 6 +++---
17
target/arm/translate.h | 1 -
12
hw/arm/xlnx-versal-virt.c | 4 ++--
18
target/arm/translate-a64.c | 51 +++++++++---------
13
2 files changed, 5 insertions(+), 5 deletions(-)
19
target/arm/translate.c | 103 ++++++++++++++++++-------------------
20
3 files changed, 72 insertions(+), 83 deletions(-)
14
21
15
diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
22
diff --git a/target/arm/translate.h b/target/arm/translate.h
16
index XXXXXXX..XXXXXXX 100644
23
index XXXXXXX..XXXXXXX 100644
17
--- a/include/hw/arm/xlnx-versal.h
24
--- a/target/arm/translate.h
18
+++ b/include/hw/arm/xlnx-versal.h
25
+++ b/target/arm/translate.h
19
@@ -XXX,XX +XXX,XX @@ typedef struct Versal {
26
@@ -XXX,XX +XXX,XX @@ typedef struct DisasContext {
20
#define VERSAL_GEM1_IRQ_0 58
27
DisasContextBase base;
21
#define VERSAL_GEM1_WAKE_IRQ_0 59
28
const ARMISARegisters *isar;
22
29
23
-/* Architecturally eserved IRQs suitable for virtualization. */
30
- target_ulong pc;
24
-#define VERSAL_RSVD_HIGH_IRQ_FIRST 160
31
/* The address of the current instruction being translated. */
25
-#define VERSAL_RSVD_HIGH_IRQ_LAST 255
32
target_ulong pc_curr;
26
+/* Architecturally reserved IRQs suitable for virtualization. */
33
target_ulong page_start;
27
+#define VERSAL_RSVD_IRQ_FIRST 111
34
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
28
+#define VERSAL_RSVD_IRQ_LAST 118
29
30
#define MM_TOP_RSVD 0xa0000000U
31
#define MM_TOP_RSVD_SIZE 0x4000000
32
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
33
index XXXXXXX..XXXXXXX 100644
35
index XXXXXXX..XXXXXXX 100644
34
--- a/hw/arm/xlnx-versal-virt.c
36
--- a/target/arm/translate-a64.c
35
+++ b/hw/arm/xlnx-versal-virt.c
37
+++ b/target/arm/translate-a64.c
36
@@ -XXX,XX +XXX,XX @@ static void create_virtio_regions(VersalVirt *s)
38
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal(int excp)
37
for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) {
39
38
char *name = g_strdup_printf("virtio%d", i);;
40
static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
39
hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size;
41
{
40
- int irq = VERSAL_RSVD_HIGH_IRQ_FIRST + i;
42
- gen_a64_set_pc_im(s->pc - offset);
41
+ int irq = VERSAL_RSVD_IRQ_FIRST + i;
43
+ gen_a64_set_pc_im(s->base.pc_next - offset);
42
MemoryRegion *mr;
44
gen_exception_internal(excp);
43
DeviceState *dev;
45
s->base.is_jmp = DISAS_NORETURN;
44
qemu_irq pic_irq;
46
}
45
@@ -XXX,XX +XXX,XX @@ static void create_virtio_regions(VersalVirt *s)
47
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
46
48
static void gen_exception_insn(DisasContext *s, int offset, int excp,
47
for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) {
49
uint32_t syndrome, uint32_t target_el)
48
hwaddr base = MM_TOP_RSVD + i * virtio_mmio_size;
50
{
49
- int irq = VERSAL_RSVD_HIGH_IRQ_FIRST + i;
51
- gen_a64_set_pc_im(s->pc - offset);
50
+ int irq = VERSAL_RSVD_IRQ_FIRST + i;
52
+ gen_a64_set_pc_im(s->base.pc_next - offset);
51
char *name = g_strdup_printf("/virtio_mmio@%" PRIx64, base);
53
gen_exception(excp, syndrome, target_el);
52
54
s->base.is_jmp = DISAS_NORETURN;
53
qemu_fdt_add_subnode(s->fdt, name);
55
}
56
@@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, int offset,
57
{
58
TCGv_i32 tcg_syn;
59
60
- gen_a64_set_pc_im(s->pc - offset);
61
+ gen_a64_set_pc_im(s->base.pc_next - offset);
62
tcg_syn = tcg_const_i32(syndrome);
63
gen_helper_exception_bkpt_insn(cpu_env, tcg_syn);
64
tcg_temp_free_i32(tcg_syn);
65
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_imm(DisasContext *s, uint32_t insn)
66
67
if (insn & (1U << 31)) {
68
/* BL Branch with link */
69
- tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
70
+ tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next);
71
}
72
73
/* B Branch / BL Branch with link */
74
@@ -XXX,XX +XXX,XX @@ static void disas_comp_b_imm(DisasContext *s, uint32_t insn)
75
tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
76
tcg_cmp, 0, label_match);
77
78
- gen_goto_tb(s, 0, s->pc);
79
+ gen_goto_tb(s, 0, s->base.pc_next);
80
gen_set_label(label_match);
81
gen_goto_tb(s, 1, addr);
82
}
83
@@ -XXX,XX +XXX,XX @@ static void disas_test_b_imm(DisasContext *s, uint32_t insn)
84
tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ,
85
tcg_cmp, 0, label_match);
86
tcg_temp_free_i64(tcg_cmp);
87
- gen_goto_tb(s, 0, s->pc);
88
+ gen_goto_tb(s, 0, s->base.pc_next);
89
gen_set_label(label_match);
90
gen_goto_tb(s, 1, addr);
91
}
92
@@ -XXX,XX +XXX,XX @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
93
/* genuinely conditional branches */
94
TCGLabel *label_match = gen_new_label();
95
arm_gen_test_cc(cond, label_match);
96
- gen_goto_tb(s, 0, s->pc);
97
+ gen_goto_tb(s, 0, s->base.pc_next);
98
gen_set_label(label_match);
99
gen_goto_tb(s, 1, addr);
100
} else {
101
@@ -XXX,XX +XXX,XX @@ static void handle_sync(DisasContext *s, uint32_t insn,
102
* any pending interrupts immediately.
103
*/
104
reset_btype(s);
105
- gen_goto_tb(s, 0, s->pc);
106
+ gen_goto_tb(s, 0, s->base.pc_next);
107
return;
108
109
case 7: /* SB */
110
@@ -XXX,XX +XXX,XX @@ static void handle_sync(DisasContext *s, uint32_t insn,
111
* MB and end the TB instead.
112
*/
113
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
114
- gen_goto_tb(s, 0, s->pc);
115
+ gen_goto_tb(s, 0, s->base.pc_next);
116
return;
117
118
default:
119
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
120
gen_a64_set_pc(s, dst);
121
/* BLR also needs to load return address */
122
if (opc == 1) {
123
- tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
124
+ tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next);
125
}
126
break;
127
128
@@ -XXX,XX +XXX,XX @@ static void disas_uncond_b_reg(DisasContext *s, uint32_t insn)
129
gen_a64_set_pc(s, dst);
130
/* BLRAA also needs to load return address */
131
if (opc == 9) {
132
- tcg_gen_movi_i64(cpu_reg(s, 30), s->pc);
133
+ tcg_gen_movi_i64(cpu_reg(s, 30), s->base.pc_next);
134
}
135
break;
136
137
@@ -XXX,XX +XXX,XX @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
138
{
139
uint32_t insn;
140
141
- s->pc_curr = s->pc;
142
- insn = arm_ldl_code(env, s->pc, s->sctlr_b);
143
+ s->pc_curr = s->base.pc_next;
144
+ insn = arm_ldl_code(env, s->base.pc_next, s->sctlr_b);
145
s->insn = insn;
146
- s->pc += 4;
147
+ s->base.pc_next += 4;
148
149
s->fp_access_checked = false;
150
151
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
152
int bound, core_mmu_idx;
153
154
dc->isar = &arm_cpu->isar;
155
- dc->pc = dc->base.pc_first;
156
dc->condjmp = 0;
157
158
dc->aarch64 = 1;
159
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
160
{
161
DisasContext *dc = container_of(dcbase, DisasContext, base);
162
163
- tcg_gen_insn_start(dc->pc, 0, 0);
164
+ tcg_gen_insn_start(dc->base.pc_next, 0, 0);
165
dc->insn_start = tcg_last_op();
166
}
167
168
@@ -XXX,XX +XXX,XX @@ static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
169
DisasContext *dc = container_of(dcbase, DisasContext, base);
170
171
if (bp->flags & BP_CPU) {
172
- gen_a64_set_pc_im(dc->pc);
173
+ gen_a64_set_pc_im(dc->base.pc_next);
174
gen_helper_check_breakpoints(cpu_env);
175
/* End the TB early; it likely won't be executed */
176
dc->base.is_jmp = DISAS_TOO_MANY;
177
@@ -XXX,XX +XXX,XX @@ static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
178
to for it to be properly cleared -- thus we
179
increment the PC here so that the logic setting
180
tb->size below does the right thing. */
181
- dc->pc += 4;
182
+ dc->base.pc_next += 4;
183
dc->base.is_jmp = DISAS_NORETURN;
184
}
185
186
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
187
disas_a64_insn(env, dc);
188
}
189
190
- dc->base.pc_next = dc->pc;
191
translator_loop_temp_check(&dc->base);
192
}
193
194
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
195
*/
196
switch (dc->base.is_jmp) {
197
default:
198
- gen_a64_set_pc_im(dc->pc);
199
+ gen_a64_set_pc_im(dc->base.pc_next);
200
/* fall through */
201
case DISAS_EXIT:
202
case DISAS_JUMP:
203
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
204
switch (dc->base.is_jmp) {
205
case DISAS_NEXT:
206
case DISAS_TOO_MANY:
207
- gen_goto_tb(dc, 1, dc->pc);
208
+ gen_goto_tb(dc, 1, dc->base.pc_next);
209
break;
210
default:
211
case DISAS_UPDATE:
212
- gen_a64_set_pc_im(dc->pc);
213
+ gen_a64_set_pc_im(dc->base.pc_next);
214
/* fall through */
215
case DISAS_EXIT:
216
tcg_gen_exit_tb(NULL, 0);
217
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
218
case DISAS_SWI:
219
break;
220
case DISAS_WFE:
221
- gen_a64_set_pc_im(dc->pc);
222
+ gen_a64_set_pc_im(dc->base.pc_next);
223
gen_helper_wfe(cpu_env);
224
break;
225
case DISAS_YIELD:
226
- gen_a64_set_pc_im(dc->pc);
227
+ gen_a64_set_pc_im(dc->base.pc_next);
228
gen_helper_yield(cpu_env);
229
break;
230
case DISAS_WFI:
231
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
232
*/
233
TCGv_i32 tmp = tcg_const_i32(4);
234
235
- gen_a64_set_pc_im(dc->pc);
236
+ gen_a64_set_pc_im(dc->base.pc_next);
237
gen_helper_wfi(cpu_env, tmp);
238
tcg_temp_free_i32(tmp);
239
/* The helper doesn't necessarily throw an exception, but we
240
@@ -XXX,XX +XXX,XX @@ static void aarch64_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
241
}
242
}
243
}
244
-
245
- /* Functions above can change dc->pc, so re-align db->pc_next */
246
- dc->base.pc_next = dc->pc;
247
}
248
249
static void aarch64_tr_disas_log(const DisasContextBase *dcbase,
250
diff --git a/target/arm/translate.c b/target/arm/translate.c
251
index XXXXXXX..XXXXXXX 100644
252
--- a/target/arm/translate.c
253
+++ b/target/arm/translate.c
254
@@ -XXX,XX +XXX,XX @@ static inline void gen_blxns(DisasContext *s, int rm)
255
* We do however need to set the PC, because the blxns helper reads it.
256
* The blxns helper may throw an exception.
257
*/
258
- gen_set_pc_im(s, s->pc);
259
+ gen_set_pc_im(s, s->base.pc_next);
260
gen_helper_v7m_blxns(cpu_env, var);
261
tcg_temp_free_i32(var);
262
s->base.is_jmp = DISAS_EXIT;
263
@@ -XXX,XX +XXX,XX @@ static inline void gen_hvc(DisasContext *s, int imm16)
264
* for single stepping.)
265
*/
266
s->svc_imm = imm16;
267
- gen_set_pc_im(s, s->pc);
268
+ gen_set_pc_im(s, s->base.pc_next);
269
s->base.is_jmp = DISAS_HVC;
270
}
271
272
@@ -XXX,XX +XXX,XX @@ static inline void gen_smc(DisasContext *s)
273
tmp = tcg_const_i32(syn_aa32_smc());
274
gen_helper_pre_smc(cpu_env, tmp);
275
tcg_temp_free_i32(tmp);
276
- gen_set_pc_im(s, s->pc);
277
+ gen_set_pc_im(s, s->base.pc_next);
278
s->base.is_jmp = DISAS_SMC;
279
}
280
281
static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
282
{
283
gen_set_condexec(s);
284
- gen_set_pc_im(s, s->pc - offset);
285
+ gen_set_pc_im(s, s->base.pc_next - offset);
286
gen_exception_internal(excp);
287
s->base.is_jmp = DISAS_NORETURN;
288
}
289
@@ -XXX,XX +XXX,XX @@ static void gen_exception_insn(DisasContext *s, int offset, int excp,
290
int syn, uint32_t target_el)
291
{
292
gen_set_condexec(s);
293
- gen_set_pc_im(s, s->pc - offset);
294
+ gen_set_pc_im(s, s->base.pc_next - offset);
295
gen_exception(excp, syn, target_el);
296
s->base.is_jmp = DISAS_NORETURN;
297
}
298
@@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, int offset, uint32_t syn)
299
TCGv_i32 tcg_syn;
300
301
gen_set_condexec(s);
302
- gen_set_pc_im(s, s->pc - offset);
303
+ gen_set_pc_im(s, s->base.pc_next - offset);
304
tcg_syn = tcg_const_i32(syn);
305
gen_helper_exception_bkpt_insn(cpu_env, tcg_syn);
306
tcg_temp_free_i32(tcg_syn);
307
@@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, int offset, uint32_t syn)
308
/* Force a TB lookup after an instruction that changes the CPU state. */
309
static inline void gen_lookup_tb(DisasContext *s)
310
{
311
- tcg_gen_movi_i32(cpu_R[15], s->pc);
312
+ tcg_gen_movi_i32(cpu_R[15], s->base.pc_next);
313
s->base.is_jmp = DISAS_EXIT;
314
}
315
316
@@ -XXX,XX +XXX,XX @@ static inline bool use_goto_tb(DisasContext *s, target_ulong dest)
317
{
318
#ifndef CONFIG_USER_ONLY
319
return (s->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) ||
320
- ((s->pc - 1) & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
321
+ ((s->base.pc_next - 1) & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
322
#else
323
return true;
324
#endif
325
@@ -XXX,XX +XXX,XX @@ static void gen_nop_hint(DisasContext *s, int val)
326
*/
327
case 1: /* yield */
328
if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
329
- gen_set_pc_im(s, s->pc);
330
+ gen_set_pc_im(s, s->base.pc_next);
331
s->base.is_jmp = DISAS_YIELD;
332
}
333
break;
334
case 3: /* wfi */
335
- gen_set_pc_im(s, s->pc);
336
+ gen_set_pc_im(s, s->base.pc_next);
337
s->base.is_jmp = DISAS_WFI;
338
break;
339
case 2: /* wfe */
340
if (!(tb_cflags(s->base.tb) & CF_PARALLEL)) {
341
- gen_set_pc_im(s, s->pc);
342
+ gen_set_pc_im(s, s->base.pc_next);
343
s->base.is_jmp = DISAS_WFE;
344
}
345
break;
346
@@ -XXX,XX +XXX,XX @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
347
if (isread) {
348
return 1;
349
}
350
- gen_set_pc_im(s, s->pc);
351
+ gen_set_pc_im(s, s->base.pc_next);
352
s->base.is_jmp = DISAS_WFI;
353
return 0;
354
default:
355
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
356
* self-modifying code correctly and also to take
357
* any pending interrupts immediately.
358
*/
359
- gen_goto_tb(s, 0, s->pc);
360
+ gen_goto_tb(s, 0, s->base.pc_next);
361
return;
362
case 7: /* sb */
363
if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) {
364
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
365
* for TCG; MB and end the TB instead.
366
*/
367
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
368
- gen_goto_tb(s, 0, s->pc);
369
+ gen_goto_tb(s, 0, s->base.pc_next);
370
return;
371
default:
372
goto illegal_op;
373
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
374
int32_t offset;
375
376
tmp = tcg_temp_new_i32();
377
- tcg_gen_movi_i32(tmp, s->pc);
378
+ tcg_gen_movi_i32(tmp, s->base.pc_next);
379
store_reg(s, 14, tmp);
380
/* Sign-extend the 24-bit offset */
381
offset = (((int32_t)insn) << 8) >> 8;
382
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
383
/* branch link/exchange thumb (blx) */
384
tmp = load_reg(s, rm);
385
tmp2 = tcg_temp_new_i32();
386
- tcg_gen_movi_i32(tmp2, s->pc);
387
+ tcg_gen_movi_i32(tmp2, s->base.pc_next);
388
store_reg(s, 14, tmp2);
389
gen_bx(s, tmp);
390
break;
391
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
392
/* branch (and link) */
393
if (insn & (1 << 24)) {
394
tmp = tcg_temp_new_i32();
395
- tcg_gen_movi_i32(tmp, s->pc);
396
+ tcg_gen_movi_i32(tmp, s->base.pc_next);
397
store_reg(s, 14, tmp);
398
}
399
offset = sextract32(insn << 2, 0, 26);
400
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
401
break;
402
case 0xf:
403
/* swi */
404
- gen_set_pc_im(s, s->pc);
405
+ gen_set_pc_im(s, s->base.pc_next);
406
s->svc_imm = extract32(insn, 0, 24);
407
s->base.is_jmp = DISAS_SWI;
408
break;
409
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
410
411
if (insn & (1 << 14)) {
412
/* Branch and link. */
413
- tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
414
+ tcg_gen_movi_i32(cpu_R[14], s->base.pc_next | 1);
415
}
416
417
offset += read_pc(s);
418
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
419
* and also to take any pending interrupts
420
* immediately.
421
*/
422
- gen_goto_tb(s, 0, s->pc);
423
+ gen_goto_tb(s, 0, s->base.pc_next);
424
break;
425
case 7: /* sb */
426
if ((insn & 0xf) || !dc_isar_feature(aa32_sb, s)) {
427
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
428
* for TCG; MB and end the TB instead.
429
*/
430
tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
431
- gen_goto_tb(s, 0, s->pc);
432
+ gen_goto_tb(s, 0, s->base.pc_next);
433
break;
434
default:
435
goto illegal_op;
436
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
437
/* BLX/BX */
438
tmp = load_reg(s, rm);
439
if (link) {
440
- val = (uint32_t)s->pc | 1;
441
+ val = (uint32_t)s->base.pc_next | 1;
442
tmp2 = tcg_temp_new_i32();
443
tcg_gen_movi_i32(tmp2, val);
444
store_reg(s, 14, tmp2);
445
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
446
447
if (cond == 0xf) {
448
/* swi */
449
- gen_set_pc_im(s, s->pc);
450
+ gen_set_pc_im(s, s->base.pc_next);
451
s->svc_imm = extract32(insn, 0, 8);
452
s->base.is_jmp = DISAS_SWI;
453
break;
454
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
455
tcg_gen_andi_i32(tmp, tmp, 0xfffffffc);
456
457
tmp2 = tcg_temp_new_i32();
458
- tcg_gen_movi_i32(tmp2, s->pc | 1);
459
+ tcg_gen_movi_i32(tmp2, s->base.pc_next | 1);
460
store_reg(s, 14, tmp2);
461
gen_bx(s, tmp);
462
break;
463
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
464
tcg_gen_addi_i32(tmp, tmp, offset);
465
466
tmp2 = tcg_temp_new_i32();
467
- tcg_gen_movi_i32(tmp2, s->pc | 1);
468
+ tcg_gen_movi_i32(tmp2, s->base.pc_next | 1);
469
store_reg(s, 14, tmp2);
470
gen_bx(s, tmp);
471
} else {
472
@@ -XXX,XX +XXX,XX @@ undef:
473
474
static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
475
{
476
- /* Return true if the insn at dc->pc might cross a page boundary.
477
+ /* Return true if the insn at dc->base.pc_next might cross a page boundary.
478
* (False positives are OK, false negatives are not.)
479
* We know this is a Thumb insn, and our caller ensures we are
480
- * only called if dc->pc is less than 4 bytes from the page
481
+ * only called if dc->base.pc_next is less than 4 bytes from the page
482
* boundary, so we cross the page if the first 16 bits indicate
483
* that this is a 32 bit insn.
484
*/
485
- uint16_t insn = arm_lduw_code(env, s->pc, s->sctlr_b);
486
+ uint16_t insn = arm_lduw_code(env, s->base.pc_next, s->sctlr_b);
487
488
- return !thumb_insn_is_16bit(s, s->pc, insn);
489
+ return !thumb_insn_is_16bit(s, s->base.pc_next, insn);
490
}
491
492
static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
493
@@ -XXX,XX +XXX,XX @@ static void arm_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs)
494
uint32_t condexec, core_mmu_idx;
495
496
dc->isar = &cpu->isar;
497
- dc->pc = dc->base.pc_first;
498
dc->condjmp = 0;
499
500
dc->aarch64 = 0;
501
@@ -XXX,XX +XXX,XX @@ static void arm_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
502
{
503
DisasContext *dc = container_of(dcbase, DisasContext, base);
504
505
- tcg_gen_insn_start(dc->pc,
506
+ tcg_gen_insn_start(dc->base.pc_next,
507
(dc->condexec_cond << 4) | (dc->condexec_mask >> 1),
508
0);
509
dc->insn_start = tcg_last_op();
510
@@ -XXX,XX +XXX,XX @@ static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
511
512
if (bp->flags & BP_CPU) {
513
gen_set_condexec(dc);
514
- gen_set_pc_im(dc, dc->pc);
515
+ gen_set_pc_im(dc, dc->base.pc_next);
516
gen_helper_check_breakpoints(cpu_env);
517
/* End the TB early; it's likely not going to be executed */
518
dc->base.is_jmp = DISAS_TOO_MANY;
519
@@ -XXX,XX +XXX,XX @@ static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
520
tb->size below does the right thing. */
521
/* TODO: Advance PC by correct instruction length to
522
* avoid disassembler error messages */
523
- dc->pc += 2;
524
+ dc->base.pc_next += 2;
525
dc->base.is_jmp = DISAS_NORETURN;
526
}
527
528
@@ -XXX,XX +XXX,XX @@ static bool arm_pre_translate_insn(DisasContext *dc)
529
{
530
#ifdef CONFIG_USER_ONLY
531
/* Intercept jump to the magic kernel page. */
532
- if (dc->pc >= 0xffff0000) {
533
+ if (dc->base.pc_next >= 0xffff0000) {
534
/* We always get here via a jump, so know we are not in a
535
conditional execution block. */
536
gen_exception_internal(EXCP_KERNEL_TRAP);
537
@@ -XXX,XX +XXX,XX @@ static void arm_post_translate_insn(DisasContext *dc)
538
gen_set_label(dc->condlabel);
539
dc->condjmp = 0;
540
}
541
- dc->base.pc_next = dc->pc;
542
translator_loop_temp_check(&dc->base);
543
}
544
545
@@ -XXX,XX +XXX,XX @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
546
return;
547
}
548
549
- dc->pc_curr = dc->pc;
550
- insn = arm_ldl_code(env, dc->pc, dc->sctlr_b);
551
+ dc->pc_curr = dc->base.pc_next;
552
+ insn = arm_ldl_code(env, dc->base.pc_next, dc->sctlr_b);
553
dc->insn = insn;
554
- dc->pc += 4;
555
+ dc->base.pc_next += 4;
556
disas_arm_insn(dc, insn);
557
558
arm_post_translate_insn(dc);
559
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
560
return;
561
}
562
563
- dc->pc_curr = dc->pc;
564
- insn = arm_lduw_code(env, dc->pc, dc->sctlr_b);
565
- is_16bit = thumb_insn_is_16bit(dc, dc->pc, insn);
566
- dc->pc += 2;
567
+ dc->pc_curr = dc->base.pc_next;
568
+ insn = arm_lduw_code(env, dc->base.pc_next, dc->sctlr_b);
569
+ is_16bit = thumb_insn_is_16bit(dc, dc->base.pc_next, insn);
570
+ dc->base.pc_next += 2;
571
if (!is_16bit) {
572
- uint32_t insn2 = arm_lduw_code(env, dc->pc, dc->sctlr_b);
573
+ uint32_t insn2 = arm_lduw_code(env, dc->base.pc_next, dc->sctlr_b);
574
575
insn = insn << 16 | insn2;
576
- dc->pc += 2;
577
+ dc->base.pc_next += 2;
578
}
579
dc->insn = insn;
580
581
@@ -XXX,XX +XXX,XX @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
582
* but isn't very efficient).
583
*/
584
if (dc->base.is_jmp == DISAS_NEXT
585
- && (dc->pc - dc->page_start >= TARGET_PAGE_SIZE
586
- || (dc->pc - dc->page_start >= TARGET_PAGE_SIZE - 3
587
+ && (dc->base.pc_next - dc->page_start >= TARGET_PAGE_SIZE
588
+ || (dc->base.pc_next - dc->page_start >= TARGET_PAGE_SIZE - 3
589
&& insn_crosses_page(env, dc)))) {
590
dc->base.is_jmp = DISAS_TOO_MANY;
591
}
592
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
593
case DISAS_NEXT:
594
case DISAS_TOO_MANY:
595
case DISAS_UPDATE:
596
- gen_set_pc_im(dc, dc->pc);
597
+ gen_set_pc_im(dc, dc->base.pc_next);
598
/* fall through */
599
default:
600
/* FIXME: Single stepping a WFI insn will not halt the CPU. */
601
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
602
switch(dc->base.is_jmp) {
603
case DISAS_NEXT:
604
case DISAS_TOO_MANY:
605
- gen_goto_tb(dc, 1, dc->pc);
606
+ gen_goto_tb(dc, 1, dc->base.pc_next);
607
break;
608
case DISAS_JUMP:
609
gen_goto_ptr();
610
break;
611
case DISAS_UPDATE:
612
- gen_set_pc_im(dc, dc->pc);
613
+ gen_set_pc_im(dc, dc->base.pc_next);
614
/* fall through */
615
default:
616
/* indicate that the hash table must be used to find the next TB */
617
@@ -XXX,XX +XXX,XX @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)
618
gen_set_label(dc->condlabel);
619
gen_set_condexec(dc);
620
if (unlikely(is_singlestepping(dc))) {
621
- gen_set_pc_im(dc, dc->pc);
622
+ gen_set_pc_im(dc, dc->base.pc_next);
623
gen_singlestep_exception(dc);
624
} else {
625
- gen_goto_tb(dc, 1, dc->pc);
626
+ gen_goto_tb(dc, 1, dc->base.pc_next);
627
}
628
}
629
-
630
- /* Functions above can change dc->pc, so re-align db->pc_next */
631
- dc->base.pc_next = dc->pc;
632
}
633
634
static void arm_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu)
54
--
635
--
55
2.19.2
636
2.20.1
56
637
57
638
diff view generated by jsdifflib
[Qemu-devel] [PULL 11/37] input/pl050: Convert sysbus init function to realize function
[Qemu-devel] [PULL 12/29] target/arm: Replace offset with pc in gen_exception_insn
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Use DeviceClass rather than SysBusDeviceClass in
3
The offset is variable depending on the instruction set, whereas
4
pl050_class_init().
4
we have stored values for the current pc and the next pc. Passing
5
5
in the actual value is clearer in intent.
6
Cc: peter.maydell@linaro.org
6
7
Cc: qemu-arm@nongnu.org
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
10
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Message-id: 20181130093852.20739-10-maozhongyi@cmss.chinamobile.com
10
Message-id: 20190807045335.1361-8-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
12
---
15
hw/input/pl050.c | 11 +++++------
13
target/arm/translate-a64.c | 25 ++++++++++++++-----------
16
1 file changed, 5 insertions(+), 6 deletions(-)
14
target/arm/translate-vfp.inc.c | 6 +++---
17
15
target/arm/translate.c | 31 ++++++++++++++++---------------
18
diff --git a/hw/input/pl050.c b/hw/input/pl050.c
16
3 files changed, 33 insertions(+), 29 deletions(-)
17
18
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
19
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/input/pl050.c
20
--- a/target/arm/translate-a64.c
21
+++ b/hw/input/pl050.c
21
+++ b/target/arm/translate-a64.c
22
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps pl050_ops = {
22
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
23
.endianness = DEVICE_NATIVE_ENDIAN,
23
s->base.is_jmp = DISAS_NORETURN;
24
};
24
}
25
25
26
-static int pl050_initfn(SysBusDevice *dev)
26
-static void gen_exception_insn(DisasContext *s, int offset, int excp,
27
+static void pl050_realize(DeviceState *dev, Error **errp)
27
+static void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
28
{
28
uint32_t syndrome, uint32_t target_el)
29
PL050State *s = PL050(dev);
29
{
30
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
30
- gen_a64_set_pc_im(s->base.pc_next - offset);
31
31
+ gen_a64_set_pc_im(pc);
32
memory_region_init_io(&s->iomem, OBJECT(s), &pl050_ops, s, "pl050", 0x1000);
32
gen_exception(excp, syndrome, target_el);
33
- sysbus_init_mmio(dev, &s->iomem);
33
s->base.is_jmp = DISAS_NORETURN;
34
- sysbus_init_irq(dev, &s->irq);
34
}
35
+ sysbus_init_mmio(sbd, &s->iomem);
35
@@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
36
+ sysbus_init_irq(sbd, &s->irq);
36
void unallocated_encoding(DisasContext *s)
37
if (s->is_mouse) {
37
{
38
s->dev = ps2_mouse_init(pl050_update, s);
38
/* Unallocated and reserved encodings are uncategorized */
39
} else {
39
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
40
s->dev = ps2_kbd_init(pl050_update, s);
40
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
41
}
41
default_exception_el(s));
42
- return 0;
42
}
43
}
43
44
44
@@ -XXX,XX +XXX,XX @@ static inline bool fp_access_check(DisasContext *s)
45
static void pl050_keyboard_init(Object *obj)
45
return true;
46
@@ -XXX,XX +XXX,XX @@ static const TypeInfo pl050_mouse_info = {
46
}
47
static void pl050_class_init(ObjectClass *oc, void *data)
47
48
{
48
- gen_exception_insn(s, 4, EXCP_UDEF, syn_fp_access_trap(1, 0xe, false),
49
DeviceClass *dc = DEVICE_CLASS(oc);
49
- s->fp_excp_el);
50
- SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(oc);
50
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
51
51
+ syn_fp_access_trap(1, 0xe, false), s->fp_excp_el);
52
- sdc->init = pl050_initfn;
52
return false;
53
+ dc->realize = pl050_realize;
53
}
54
dc->vmsd = &vmstate_pl050;
54
55
}
55
@@ -XXX,XX +XXX,XX @@ static inline bool fp_access_check(DisasContext *s)
56
bool sve_access_check(DisasContext *s)
57
{
58
if (s->sve_excp_el) {
59
- gen_exception_insn(s, 4, EXCP_UDEF, syn_sve_access_trap(),
60
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_sve_access_trap(),
61
s->sve_excp_el);
62
return false;
63
}
64
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
65
switch (op2_ll) {
66
case 1: /* SVC */
67
gen_ss_advance(s);
68
- gen_exception_insn(s, 0, EXCP_SWI, syn_aa64_svc(imm16),
69
- default_exception_el(s));
70
+ gen_exception_insn(s, s->base.pc_next, EXCP_SWI,
71
+ syn_aa64_svc(imm16), default_exception_el(s));
72
break;
73
case 2: /* HVC */
74
if (s->current_el == 0) {
75
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
76
gen_a64_set_pc_im(s->pc_curr);
77
gen_helper_pre_hvc(cpu_env);
78
gen_ss_advance(s);
79
- gen_exception_insn(s, 0, EXCP_HVC, syn_aa64_hvc(imm16), 2);
80
+ gen_exception_insn(s, s->base.pc_next, EXCP_HVC,
81
+ syn_aa64_hvc(imm16), 2);
82
break;
83
case 3: /* SMC */
84
if (s->current_el == 0) {
85
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
86
gen_helper_pre_smc(cpu_env, tmp);
87
tcg_temp_free_i32(tmp);
88
gen_ss_advance(s);
89
- gen_exception_insn(s, 0, EXCP_SMC, syn_aa64_smc(imm16), 3);
90
+ gen_exception_insn(s, s->base.pc_next, EXCP_SMC,
91
+ syn_aa64_smc(imm16), 3);
92
break;
93
default:
94
unallocated_encoding(s);
95
@@ -XXX,XX +XXX,XX @@ static void disas_a64_insn(CPUARMState *env, DisasContext *s)
96
if (s->btype != 0
97
&& s->guarded_page
98
&& !btype_destination_ok(insn, s->bt, s->btype)) {
99
- gen_exception_insn(s, 4, EXCP_UDEF, syn_btitrap(s->btype),
100
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
101
+ syn_btitrap(s->btype),
102
default_exception_el(s));
103
return;
104
}
105
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
106
index XXXXXXX..XXXXXXX 100644
107
--- a/target/arm/translate-vfp.inc.c
108
+++ b/target/arm/translate-vfp.inc.c
109
@@ -XXX,XX +XXX,XX @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
110
{
111
if (s->fp_excp_el) {
112
if (arm_dc_feature(s, ARM_FEATURE_M)) {
113
- gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(),
114
+ gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized(),
115
s->fp_excp_el);
116
} else {
117
- gen_exception_insn(s, 4, EXCP_UDEF,
118
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
119
syn_fp_access_trap(1, 0xe, false),
120
s->fp_excp_el);
121
}
122
@@ -XXX,XX +XXX,XX @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
123
124
if (!s->vfp_enabled && !ignore_vfp_enabled) {
125
assert(!arm_dc_feature(s, ARM_FEATURE_M));
126
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
127
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
128
default_exception_el(s));
129
return false;
130
}
131
diff --git a/target/arm/translate.c b/target/arm/translate.c
132
index XXXXXXX..XXXXXXX 100644
133
--- a/target/arm/translate.c
134
+++ b/target/arm/translate.c
135
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
136
s->base.is_jmp = DISAS_NORETURN;
137
}
138
139
-static void gen_exception_insn(DisasContext *s, int offset, int excp,
140
+static void gen_exception_insn(DisasContext *s, uint32_t pc, int excp,
141
int syn, uint32_t target_el)
142
{
143
gen_set_condexec(s);
144
- gen_set_pc_im(s, s->base.pc_next - offset);
145
+ gen_set_pc_im(s, pc);
146
gen_exception(excp, syn, target_el);
147
s->base.is_jmp = DISAS_NORETURN;
148
}
149
@@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm)
150
return;
151
}
152
153
- gen_exception_insn(s, s->thumb ? 2 : 4, EXCP_UDEF, syn_uncategorized(),
154
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
155
default_exception_el(s));
156
}
157
158
@@ -XXX,XX +XXX,XX @@ static bool msr_banked_access_decode(DisasContext *s, int r, int sysm, int rn,
159
160
undef:
161
/* If we get here then some access check did not pass */
162
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), exc_target);
163
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
164
+ syn_uncategorized(), exc_target);
165
return false;
166
}
167
168
@@ -XXX,XX +XXX,XX @@ static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
169
* for attempts to execute invalid vfp/neon encodings with FP disabled.
170
*/
171
if (s->fp_excp_el) {
172
- gen_exception_insn(s, 4, EXCP_UDEF,
173
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
174
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
175
return 0;
176
}
177
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
178
* for attempts to execute invalid vfp/neon encodings with FP disabled.
179
*/
180
if (s->fp_excp_el) {
181
- gen_exception_insn(s, 4, EXCP_UDEF,
182
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
183
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
184
return 0;
185
}
186
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
187
}
188
189
if (s->fp_excp_el) {
190
- gen_exception_insn(s, 4, EXCP_UDEF,
191
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
192
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
193
return 0;
194
}
195
@@ -XXX,XX +XXX,XX @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
196
off_rm = vfp_reg_offset(0, rm);
197
}
198
if (s->fp_excp_el) {
199
- gen_exception_insn(s, 4, EXCP_UDEF,
200
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
201
syn_simd_access_trap(1, 0xe, false), s->fp_excp_el);
202
return 0;
203
}
204
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
205
* For the UNPREDICTABLE cases we choose to UNDEF.
206
*/
207
if (s->current_el == 1 && !s->ns && mode == ARM_CPU_MODE_MON) {
208
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), 3);
209
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(), 3);
210
return;
211
}
212
213
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
214
}
215
216
if (undef) {
217
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
218
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
219
default_exception_el(s));
220
return;
221
}
222
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
223
* UsageFault exception.
224
*/
225
if (arm_dc_feature(s, ARM_FEATURE_M)) {
226
- gen_exception_insn(s, 4, EXCP_INVSTATE, syn_uncategorized(),
227
+ gen_exception_insn(s, s->pc_curr, EXCP_INVSTATE, syn_uncategorized(),
228
default_exception_el(s));
229
return;
230
}
231
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
232
break;
233
default:
234
illegal_op:
235
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
236
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
237
default_exception_el(s));
238
break;
239
}
240
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
241
}
242
243
/* All other insns: NOCP */
244
- gen_exception_insn(s, 4, EXCP_NOCP, syn_uncategorized(),
245
+ gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized(),
246
default_exception_el(s));
247
break;
248
}
249
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
250
}
251
return;
252
illegal_op:
253
- gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(),
254
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
255
default_exception_el(s));
256
}
257
258
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
259
return;
260
illegal_op:
261
undef:
262
- gen_exception_insn(s, 2, EXCP_UDEF, syn_uncategorized(),
263
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
264
default_exception_el(s));
265
}
56
266
57
--
267
--
58
2.19.2
268
2.20.1
59
269
60
270
diff view generated by jsdifflib
[Qemu-devel] [PULL 18/37] timer/etraxfs_timer: Convert sysbus init function to realize function
[Qemu-devel] [PULL 13/29] target/arm: Replace offset with pc in gen_exception_internal_insn
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Use DeviceClass rather than SysBusDeviceClass in
3
The offset is variable depending on the instruction set.
4
etraxfs_timer_class_init().
4
Passing in the actual value is clearer in intent.
5
5
6
Cc: edgar.iglesias@gmail.com
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
9
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
9
Message-id: 20190807045335.1361-9-richard.henderson@linaro.org
12
Message-id: 20181130093852.20739-17-maozhongyi@cmss.chinamobile.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
11
---
15
hw/timer/etraxfs_timer.c | 14 +++++++-------
12
target/arm/translate-a64.c | 8 ++++----
16
1 file changed, 7 insertions(+), 7 deletions(-)
13
target/arm/translate.c | 8 ++++----
14
2 files changed, 8 insertions(+), 8 deletions(-)
17
15
18
diff --git a/hw/timer/etraxfs_timer.c b/hw/timer/etraxfs_timer.c
16
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
19
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/timer/etraxfs_timer.c
18
--- a/target/arm/translate-a64.c
21
+++ b/hw/timer/etraxfs_timer.c
19
+++ b/target/arm/translate-a64.c
22
@@ -XXX,XX +XXX,XX @@ static void etraxfs_timer_reset(void *opaque)
20
@@ -XXX,XX +XXX,XX @@ static void gen_exception_internal(int excp)
23
qemu_irq_lower(t->irq);
21
tcg_temp_free_i32(tcg_excp);
24
}
22
}
25
23
26
-static int etraxfs_timer_init(SysBusDevice *dev)
24
-static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
27
+static void etraxfs_timer_realize(DeviceState *dev, Error **errp)
25
+static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int excp)
28
{
26
{
29
ETRAXTimerState *t = ETRAX_TIMER(dev);
27
- gen_a64_set_pc_im(s->base.pc_next - offset);
30
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
28
+ gen_a64_set_pc_im(pc);
31
29
gen_exception_internal(excp);
32
t->bh_t0 = qemu_bh_new(timer0_hit, t);
30
s->base.is_jmp = DISAS_NORETURN;
33
t->bh_t1 = qemu_bh_new(timer1_hit, t);
34
@@ -XXX,XX +XXX,XX @@ static int etraxfs_timer_init(SysBusDevice *dev)
35
t->ptimer_t1 = ptimer_init(t->bh_t1, PTIMER_POLICY_DEFAULT);
36
t->ptimer_wd = ptimer_init(t->bh_wd, PTIMER_POLICY_DEFAULT);
37
38
- sysbus_init_irq(dev, &t->irq);
39
- sysbus_init_irq(dev, &t->nmi);
40
+ sysbus_init_irq(sbd, &t->irq);
41
+ sysbus_init_irq(sbd, &t->nmi);
42
43
memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
44
"etraxfs-timer", 0x5c);
45
- sysbus_init_mmio(dev, &t->mmio);
46
+ sysbus_init_mmio(sbd, &t->mmio);
47
qemu_register_reset(etraxfs_timer_reset, t);
48
- return 0;
49
}
31
}
50
32
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
51
static void etraxfs_timer_class_init(ObjectClass *klass, void *data)
33
break;
34
}
35
#endif
36
- gen_exception_internal_insn(s, 0, EXCP_SEMIHOST);
37
+ gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST);
38
} else {
39
unsupported_encoding(s, insn);
40
}
41
@@ -XXX,XX +XXX,XX @@ static bool aarch64_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
42
/* End the TB early; it likely won't be executed */
43
dc->base.is_jmp = DISAS_TOO_MANY;
44
} else {
45
- gen_exception_internal_insn(dc, 0, EXCP_DEBUG);
46
+ gen_exception_internal_insn(dc, dc->base.pc_next, EXCP_DEBUG);
47
/* The address covered by the breakpoint must be
48
included in [tb->pc, tb->pc + tb->size) in order
49
to for it to be properly cleared -- thus we
50
diff --git a/target/arm/translate.c b/target/arm/translate.c
51
index XXXXXXX..XXXXXXX 100644
52
--- a/target/arm/translate.c
53
+++ b/target/arm/translate.c
54
@@ -XXX,XX +XXX,XX @@ static inline void gen_smc(DisasContext *s)
55
s->base.is_jmp = DISAS_SMC;
56
}
57
58
-static void gen_exception_internal_insn(DisasContext *s, int offset, int excp)
59
+static void gen_exception_internal_insn(DisasContext *s, uint32_t pc, int excp)
52
{
60
{
53
- SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
61
gen_set_condexec(s);
54
+ DeviceClass *dc = DEVICE_CLASS(klass);
62
- gen_set_pc_im(s, s->base.pc_next - offset);
55
63
+ gen_set_pc_im(s, pc);
56
- sdc->init = etraxfs_timer_init;
64
gen_exception_internal(excp);
57
+ dc->realize = etraxfs_timer_realize;
65
s->base.is_jmp = DISAS_NORETURN;
58
}
66
}
59
67
@@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm)
60
static const TypeInfo etraxfs_timer_info = {
68
s->current_el != 0 &&
69
#endif
70
(imm == (s->thumb ? 0x3c : 0xf000))) {
71
- gen_exception_internal_insn(s, 0, EXCP_SEMIHOST);
72
+ gen_exception_internal_insn(s, s->base.pc_next, EXCP_SEMIHOST);
73
return;
74
}
75
76
@@ -XXX,XX +XXX,XX @@ static bool arm_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
77
/* End the TB early; it's likely not going to be executed */
78
dc->base.is_jmp = DISAS_TOO_MANY;
79
} else {
80
- gen_exception_internal_insn(dc, 0, EXCP_DEBUG);
81
+ gen_exception_internal_insn(dc, dc->base.pc_next, EXCP_DEBUG);
82
/* The address covered by the breakpoint must be
83
included in [tb->pc, tb->pc + tb->size) in order
84
to for it to be properly cleared -- thus we
61
--
85
--
62
2.19.2
86
2.20.1
63
87
64
88
diff view generated by jsdifflib
[Qemu-devel] [PULL 21/37] usb/tusb6010: Convert sysbus init function to realize function
[Qemu-devel] [PULL 14/29] target/arm: Remove offset argument to gen_exception_bkpt_insn
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Use DeviceClass rather than SysBusDeviceClass in
3
Unlike the other more generic gen_exception{,_internal}_insn
4
tusb6010_class_init().
4
interfaces, breakpoints always refer to the current instruction.
5
5
6
Cc: kraxel@redhat.com
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
9
Message-id: 20190807045335.1361-10-richard.henderson@linaro.org
10
Message-id: 20181130093852.20739-20-maozhongyi@cmss.chinamobile.com
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
11
---
13
hw/usb/tusb6010.c | 8 +++-----
12
target/arm/translate-a64.c | 7 +++----
14
1 file changed, 3 insertions(+), 5 deletions(-)
13
target/arm/translate.c | 8 ++++----
14
2 files changed, 7 insertions(+), 8 deletions(-)
15
15
16
diff --git a/hw/usb/tusb6010.c b/hw/usb/tusb6010.c
16
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
17
index XXXXXXX..XXXXXXX 100644
17
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/usb/tusb6010.c
18
--- a/target/arm/translate-a64.c
19
+++ b/hw/usb/tusb6010.c
19
+++ b/target/arm/translate-a64.c
20
@@ -XXX,XX +XXX,XX @@ static void tusb6010_reset(DeviceState *dev)
20
@@ -XXX,XX +XXX,XX @@ static void gen_exception_insn(DisasContext *s, uint64_t pc, int excp,
21
musb_reset(s->musb);
21
s->base.is_jmp = DISAS_NORETURN;
22
}
22
}
23
23
24
-static int tusb6010_init(SysBusDevice *sbd)
24
-static void gen_exception_bkpt_insn(DisasContext *s, int offset,
25
+static void tusb6010_realize(DeviceState *dev, Error **errp)
25
- uint32_t syndrome)
26
+static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome)
26
{
27
{
27
- DeviceState *dev = DEVICE(sbd);
28
TCGv_i32 tcg_syn;
28
TUSBState *s = TUSB(dev);
29
29
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
30
- gen_a64_set_pc_im(s->base.pc_next - offset);
30
31
+ gen_a64_set_pc_im(s->pc_curr);
31
s->otg_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tusb_otg_tick, s);
32
tcg_syn = tcg_const_i32(syndrome);
32
s->pwr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tusb_power_tick, s);
33
gen_helper_exception_bkpt_insn(cpu_env, tcg_syn);
33
@@ -XXX,XX +XXX,XX @@ static int tusb6010_init(SysBusDevice *sbd)
34
tcg_temp_free_i32(tcg_syn);
34
sysbus_init_irq(sbd, &s->irq);
35
@@ -XXX,XX +XXX,XX @@ static void disas_exc(DisasContext *s, uint32_t insn)
35
qdev_init_gpio_in(dev, tusb6010_irq, musb_irq_max + 1);
36
break;
36
s->musb = musb_init(dev, 1);
37
}
37
- return 0;
38
/* BRK */
39
- gen_exception_bkpt_insn(s, 4, syn_aa64_bkpt(imm16));
40
+ gen_exception_bkpt_insn(s, syn_aa64_bkpt(imm16));
41
break;
42
case 2:
43
if (op2_ll != 0) {
44
diff --git a/target/arm/translate.c b/target/arm/translate.c
45
index XXXXXXX..XXXXXXX 100644
46
--- a/target/arm/translate.c
47
+++ b/target/arm/translate.c
48
@@ -XXX,XX +XXX,XX @@ static void gen_exception_insn(DisasContext *s, uint32_t pc, int excp,
49
s->base.is_jmp = DISAS_NORETURN;
38
}
50
}
39
51
40
static void tusb6010_class_init(ObjectClass *klass, void *data)
52
-static void gen_exception_bkpt_insn(DisasContext *s, int offset, uint32_t syn)
53
+static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
41
{
54
{
42
DeviceClass *dc = DEVICE_CLASS(klass);
55
TCGv_i32 tcg_syn;
43
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
56
44
57
gen_set_condexec(s);
45
- k->init = tusb6010_init;
58
- gen_set_pc_im(s, s->base.pc_next - offset);
46
+ dc->realize = tusb6010_realize;
59
+ gen_set_pc_im(s, s->pc_curr);
47
dc->reset = tusb6010_reset;
60
tcg_syn = tcg_const_i32(syn);
48
}
61
gen_helper_exception_bkpt_insn(cpu_env, tcg_syn);
62
tcg_temp_free_i32(tcg_syn);
63
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
64
case 1:
65
/* bkpt */
66
ARCH(5);
67
- gen_exception_bkpt_insn(s, 4, syn_aa32_bkpt(imm16, false));
68
+ gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm16, false));
69
break;
70
case 2:
71
/* Hypervisor call (v7) */
72
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
73
{
74
int imm8 = extract32(insn, 0, 8);
75
ARCH(5);
76
- gen_exception_bkpt_insn(s, 2, syn_aa32_bkpt(imm8, true));
77
+ gen_exception_bkpt_insn(s, syn_aa32_bkpt(imm8, true));
78
break;
79
}
49
80
50
--
81
--
51
2.19.2
82
2.20.1
52
83
53
84
diff view generated by jsdifflib
[Qemu-devel] [PULL 06/37] core/empty_slot: Convert sysbus init function to realize function
[Qemu-devel] [PULL 15/29] target/arm: Use unallocated_encoding for aarch32
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Use DeviceClass rather than SysBusDeviceClass in
3
Promote this function from aarch64 to fully general use.
4
empty_slot_class_init().
4
Use it to unify the code sequences for generating illegal
5
opcode exceptions.
5
6
6
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
9
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Message-id: 20181130093852.20739-5-maozhongyi@cmss.chinamobile.com
10
Message-id: 20190807045335.1361-11-richard.henderson@linaro.org
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
12
---
13
hw/core/empty_slot.c | 9 ++++-----
13
target/arm/translate-a64.h | 2 --
14
1 file changed, 4 insertions(+), 5 deletions(-)
14
target/arm/translate.h | 2 ++
15
target/arm/translate-a64.c | 7 -------
16
target/arm/translate-vfp.inc.c | 3 +--
17
target/arm/translate.c | 22 ++++++++++++----------
18
5 files changed, 15 insertions(+), 21 deletions(-)
15
19
16
diff --git a/hw/core/empty_slot.c b/hw/core/empty_slot.c
20
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
17
index XXXXXXX..XXXXXXX 100644
21
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/core/empty_slot.c
22
--- a/target/arm/translate-a64.h
19
+++ b/hw/core/empty_slot.c
23
+++ b/target/arm/translate-a64.h
20
@@ -XXX,XX +XXX,XX @@ void empty_slot_init(hwaddr addr, uint64_t slot_size)
24
@@ -XXX,XX +XXX,XX @@
25
#ifndef TARGET_ARM_TRANSLATE_A64_H
26
#define TARGET_ARM_TRANSLATE_A64_H
27
28
-void unallocated_encoding(DisasContext *s);
29
-
30
#define unsupported_encoding(s, insn) \
31
do { \
32
qemu_log_mask(LOG_UNIMP, \
33
diff --git a/target/arm/translate.h b/target/arm/translate.h
34
index XXXXXXX..XXXXXXX 100644
35
--- a/target/arm/translate.h
36
+++ b/target/arm/translate.h
37
@@ -XXX,XX +XXX,XX @@ typedef struct DisasCompare {
38
bool value_global;
39
} DisasCompare;
40
41
+void unallocated_encoding(DisasContext *s);
42
+
43
/* Share the TCG temporaries common between 32 and 64 bit modes. */
44
extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF;
45
extern TCGv_i64 cpu_exclusive_addr;
46
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
47
index XXXXXXX..XXXXXXX 100644
48
--- a/target/arm/translate-a64.c
49
+++ b/target/arm/translate-a64.c
50
@@ -XXX,XX +XXX,XX @@ static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest)
21
}
51
}
22
}
52
}
23
53
24
-static int empty_slot_init1(SysBusDevice *dev)
54
-void unallocated_encoding(DisasContext *s)
25
+static void empty_slot_realize(DeviceState *dev, Error **errp)
55
-{
56
- /* Unallocated and reserved encodings are uncategorized */
57
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
58
- default_exception_el(s));
59
-}
60
-
61
static void init_tmp_a64_array(DisasContext *s)
26
{
62
{
27
EmptySlot *s = EMPTY_SLOT(dev);
63
#ifdef CONFIG_DEBUG_TCG
28
64
diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
29
memory_region_init_io(&s->iomem, OBJECT(s), &empty_slot_ops, s,
65
index XXXXXXX..XXXXXXX 100644
30
"empty-slot", s->size);
66
--- a/target/arm/translate-vfp.inc.c
31
- sysbus_init_mmio(dev, &s->iomem);
67
+++ b/target/arm/translate-vfp.inc.c
32
- return 0;
68
@@ -XXX,XX +XXX,XX @@ static bool full_vfp_access_check(DisasContext *s, bool ignore_vfp_enabled)
33
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
69
70
if (!s->vfp_enabled && !ignore_vfp_enabled) {
71
assert(!arm_dc_feature(s, ARM_FEATURE_M));
72
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
73
- default_exception_el(s));
74
+ unallocated_encoding(s);
75
return false;
76
}
77
78
diff --git a/target/arm/translate.c b/target/arm/translate.c
79
index XXXXXXX..XXXXXXX 100644
80
--- a/target/arm/translate.c
81
+++ b/target/arm/translate.c
82
@@ -XXX,XX +XXX,XX @@ static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn)
83
s->base.is_jmp = DISAS_NORETURN;
34
}
84
}
35
85
36
static void empty_slot_class_init(ObjectClass *klass, void *data)
86
+void unallocated_encoding(DisasContext *s)
87
+{
88
+ /* Unallocated and reserved encodings are uncategorized */
89
+ gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
90
+ default_exception_el(s));
91
+}
92
+
93
/* Force a TB lookup after an instruction that changes the CPU state. */
94
static inline void gen_lookup_tb(DisasContext *s)
37
{
95
{
38
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
96
@@ -XXX,XX +XXX,XX @@ static inline void gen_hlt(DisasContext *s, int imm)
39
+ DeviceClass *dc = DEVICE_CLASS(klass);
97
return;
40
98
}
41
- k->init = empty_slot_init1;
99
42
+ dc->realize = empty_slot_realize;
100
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
101
- default_exception_el(s));
102
+ unallocated_encoding(s);
43
}
103
}
44
104
45
static const TypeInfo empty_slot_info = {
105
static inline void gen_add_data_offset(DisasContext *s, unsigned int insn,
106
@@ -XXX,XX +XXX,XX @@ static void gen_srs(DisasContext *s,
107
}
108
109
if (undef) {
110
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
111
- default_exception_el(s));
112
+ unallocated_encoding(s);
113
return;
114
}
115
116
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
117
break;
118
default:
119
illegal_op:
120
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
121
- default_exception_el(s));
122
+ unallocated_encoding(s);
123
break;
124
}
125
}
126
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
127
}
128
return;
129
illegal_op:
130
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
131
- default_exception_el(s));
132
+ unallocated_encoding(s);
133
}
134
135
static void disas_thumb_insn(DisasContext *s, uint32_t insn)
136
@@ -XXX,XX +XXX,XX @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
137
return;
138
illegal_op:
139
undef:
140
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF, syn_uncategorized(),
141
- default_exception_el(s));
142
+ unallocated_encoding(s);
143
}
144
145
static bool insn_crosses_page(CPUARMState *env, DisasContext *s)
46
--
146
--
47
2.19.2
147
2.20.1
48
148
49
149
diff view generated by jsdifflib
[Qemu-devel] [PULL 36/37] target/arm: Use arm_hcr_el2_eff more places
[Qemu-devel] [PULL 16/29] target/arm: Remove helper_double_saturate
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Since arm_hcr_el2_eff includes a check against
3
Replace x = double_saturate(y) with x = add_saturate(y, y).
4
arm_is_secure_below_el3, we can often remove a
4
There is no need for a separate more specialized helper.
5
nearby check against secure state.
6
5
7
In some cases, sort the call to arm_hcr_el2_eff
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
to the end of a short-circuit logical sequence.
9
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Message-id: 20181210150501.7990-3-richard.henderson@linaro.org
9
Message-id: 20190807045335.1361-12-richard.henderson@linaro.org
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
11
---
15
target/arm/helper.c | 12 +++++-------
12
target/arm/helper.h | 1 -
16
target/arm/op_helper.c | 14 ++++++--------
13
target/arm/op_helper.c | 15 ---------------
17
2 files changed, 11 insertions(+), 15 deletions(-)
14
target/arm/translate.c | 4 ++--
15
3 files changed, 2 insertions(+), 18 deletions(-)
18
16
19
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
diff --git a/target/arm/helper.h b/target/arm/helper.h
20
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
21
--- a/target/arm/helper.c
19
--- a/target/arm/helper.h
22
+++ b/target/arm/helper.c
20
+++ b/target/arm/helper.h
23
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tdosa(CPUARMState *env, const ARMCPRegInfo *ri,
21
@@ -XXX,XX +XXX,XX @@ DEF_HELPER_3(add_saturate, i32, env, i32, i32)
24
int el = arm_current_el(env);
22
DEF_HELPER_3(sub_saturate, i32, env, i32, i32)
25
bool mdcr_el2_tdosa = (env->cp15.mdcr_el2 & MDCR_TDOSA) ||
23
DEF_HELPER_3(add_usaturate, i32, env, i32, i32)
26
(env->cp15.mdcr_el2 & MDCR_TDE) ||
24
DEF_HELPER_3(sub_usaturate, i32, env, i32, i32)
27
- (env->cp15.hcr_el2 & HCR_TGE);
25
-DEF_HELPER_2(double_saturate, i32, env, s32)
28
+ (arm_hcr_el2_eff(env) & HCR_TGE);
26
DEF_HELPER_FLAGS_2(sdiv, TCG_CALL_NO_RWG_SE, s32, s32, s32)
29
27
DEF_HELPER_FLAGS_2(udiv, TCG_CALL_NO_RWG_SE, i32, i32, i32)
30
if (el < 2 && mdcr_el2_tdosa && !arm_is_secure_below_el3(env)) {
28
DEF_HELPER_FLAGS_1(rbit, TCG_CALL_NO_RWG_SE, i32, i32)
31
return CP_ACCESS_TRAP_EL2;
32
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tdra(CPUARMState *env, const ARMCPRegInfo *ri,
33
int el = arm_current_el(env);
34
bool mdcr_el2_tdra = (env->cp15.mdcr_el2 & MDCR_TDRA) ||
35
(env->cp15.mdcr_el2 & MDCR_TDE) ||
36
- (env->cp15.hcr_el2 & HCR_TGE);
37
+ (arm_hcr_el2_eff(env) & HCR_TGE);
38
39
if (el < 2 && mdcr_el2_tdra && !arm_is_secure_below_el3(env)) {
40
return CP_ACCESS_TRAP_EL2;
41
@@ -XXX,XX +XXX,XX @@ static CPAccessResult access_tda(CPUARMState *env, const ARMCPRegInfo *ri,
42
int el = arm_current_el(env);
43
bool mdcr_el2_tda = (env->cp15.mdcr_el2 & MDCR_TDA) ||
44
(env->cp15.mdcr_el2 & MDCR_TDE) ||
45
- (env->cp15.hcr_el2 & HCR_TGE);
46
+ (arm_hcr_el2_eff(env) & HCR_TGE);
47
48
if (el < 2 && mdcr_el2_tda && !arm_is_secure_below_el3(env)) {
49
return CP_ACCESS_TRAP_EL2;
50
@@ -XXX,XX +XXX,XX @@ int sve_exception_el(CPUARMState *env, int el)
51
if (disabled) {
52
/* route_to_el2 */
53
return (arm_feature(env, ARM_FEATURE_EL2)
54
- && !arm_is_secure(env)
55
- && (env->cp15.hcr_el2 & HCR_TGE) ? 2 : 1);
56
+ && (arm_hcr_el2_eff(env) & HCR_TGE) ? 2 : 1);
57
}
58
59
/* Check CPACR.FPEN. */
60
@@ -XXX,XX +XXX,XX @@ static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType write_type)
61
* and CPS are treated as illegal mode changes.
62
*/
63
if (write_type == CPSRWriteByInstr &&
64
- (env->cp15.hcr_el2 & HCR_TGE) &&
65
(env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_MON &&
66
- !arm_is_secure_below_el3(env)) {
67
+ (arm_hcr_el2_eff(env) & HCR_TGE)) {
68
return 1;
69
}
70
return 0;
71
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
29
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
72
index XXXXXXX..XXXXXXX 100644
30
index XXXXXXX..XXXXXXX 100644
73
--- a/target/arm/op_helper.c
31
--- a/target/arm/op_helper.c
74
+++ b/target/arm/op_helper.c
32
+++ b/target/arm/op_helper.c
75
@@ -XXX,XX +XXX,XX @@ void raise_exception(CPUARMState *env, uint32_t excp,
33
@@ -XXX,XX +XXX,XX @@ uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
34
return res;
35
}
36
37
-uint32_t HELPER(double_saturate)(CPUARMState *env, int32_t val)
38
-{
39
- uint32_t res;
40
- if (val >= 0x40000000) {
41
- res = ~SIGNBIT;
42
- env->QF = 1;
43
- } else if (val <= (int32_t)0xc0000000) {
44
- res = SIGNBIT;
45
- env->QF = 1;
46
- } else {
47
- res = val << 1;
48
- }
49
- return res;
50
-}
51
-
52
uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
76
{
53
{
77
CPUState *cs = CPU(arm_env_get_cpu(env));
54
uint32_t res = a + b;
78
55
diff --git a/target/arm/translate.c b/target/arm/translate.c
79
- if ((env->cp15.hcr_el2 & HCR_TGE) &&
56
index XXXXXXX..XXXXXXX 100644
80
- target_el == 1 && !arm_is_secure(env)) {
57
--- a/target/arm/translate.c
81
+ if (target_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) {
58
+++ b/target/arm/translate.c
82
/*
59
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
83
* Redirect NS EL1 exceptions to NS EL2. These are reported with
60
tmp = load_reg(s, rm);
84
* their original syndrome register value, with the exception of
61
tmp2 = load_reg(s, rn);
85
@@ -XXX,XX +XXX,XX @@ static inline int check_wfx_trap(CPUARMState *env, bool is_wfe)
62
if (op1 & 2)
86
* No need for ARM_FEATURE check as if HCR_EL2 doesn't exist the
63
- gen_helper_double_saturate(tmp2, cpu_env, tmp2);
87
* bits will be zero indicating no trap.
64
+ gen_helper_add_saturate(tmp2, cpu_env, tmp2, tmp2);
88
*/
65
if (op1 & 1)
89
- if (cur_el < 2 && !arm_is_secure(env)) {
66
gen_helper_sub_saturate(tmp, cpu_env, tmp, tmp2);
90
- mask = (is_wfe) ? HCR_TWE : HCR_TWI;
67
else
91
- if (env->cp15.hcr_el2 & mask) {
68
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
92
+ if (cur_el < 2) {
69
tmp = load_reg(s, rn);
93
+ mask = is_wfe ? HCR_TWE : HCR_TWI;
70
tmp2 = load_reg(s, rm);
94
+ if (arm_hcr_el2_eff(env) & mask) {
71
if (op & 1)
95
return 2;
72
- gen_helper_double_saturate(tmp, cpu_env, tmp);
96
}
73
+ gen_helper_add_saturate(tmp, cpu_env, tmp, tmp);
97
}
74
if (op & 2)
98
@@ -XXX,XX +XXX,XX @@ void HELPER(pre_smc)(CPUARMState *env, uint32_t syndrome)
75
gen_helper_sub_saturate(tmp, cpu_env, tmp2, tmp);
99
exception_target_el(env));
76
else
100
}
101
102
- if (!secure && cur_el == 1 && (env->cp15.hcr_el2 & HCR_TSC)) {
103
+ if (cur_el == 1 && (arm_hcr_el2_eff(env) & HCR_TSC)) {
104
/* In NS EL1, HCR controlled routing to EL2 has priority over SMD.
105
* We also want an EL2 guest to be able to forbid its EL1 from
106
* making PSCI calls into QEMU's "firmware" via HCR.TSC.
107
@@ -XXX,XX +XXX,XX @@ void HELPER(exception_return)(CPUARMState *env)
108
goto illegal_return;
109
}
110
111
- if (new_el == 1 && (env->cp15.hcr_el2 & HCR_TGE)
112
- && !arm_is_secure_below_el3(env)) {
113
+ if (new_el == 1 && (arm_hcr_el2_eff(env) & HCR_TGE)) {
114
goto illegal_return;
115
}
116
117
--
77
--
118
2.19.2
78
2.20.1
119
79
120
80
diff view generated by jsdifflib
[Qemu-devel] [PULL 17/37] pci-bridge/dec: Convert sysbus init function to realize function
[Qemu-devel] [PULL 17/29] target/arm/cpu64: Ensure kvm really supports aarch64=off
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
From: Andrew Jones <drjones@redhat.com>
2
2
3
Use DeviceClass rather than SysBusDeviceClass in
3
If -cpu <cpu>,aarch64=off is used then KVM must also be used, and it
4
pci_dec_21154_device_class_init().
4
and the host must support running the vcpu in 32-bit mode. Also, if
5
-cpu <cpu>,aarch64=on is used, then it doesn't matter if kvm is
6
enabled or not.
5
7
6
Cc: david@gibson.dropbear.id.au
8
Signed-off-by: Andrew Jones <drjones@redhat.com>
7
Cc: mst@redhat.com
9
Reviewed-by: Eric Auger <eric.auger@redhat.com>
8
Cc: marcel.apfelbaum@gmail.com
9
Cc: qemu-ppc@nongnu.org
10
11
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
12
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
13
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
14
Acked-by: David Gibson <david@gibson.dropbear.id.au>
15
Message-id: 20181130093852.20739-16-maozhongyi@cmss.chinamobile.com
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
11
---
18
hw/pci-bridge/dec.c | 12 ++++++------
12
target/arm/kvm_arm.h | 14 ++++++++++++++
19
1 file changed, 6 insertions(+), 6 deletions(-)
13
target/arm/cpu64.c | 12 ++++++------
14
target/arm/kvm64.c | 9 +++++++++
15
3 files changed, 29 insertions(+), 6 deletions(-)
20
16
21
diff --git a/hw/pci-bridge/dec.c b/hw/pci-bridge/dec.c
17
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
22
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/pci-bridge/dec.c
19
--- a/target/arm/kvm_arm.h
24
+++ b/hw/pci-bridge/dec.c
20
+++ b/target/arm/kvm_arm.h
25
@@ -XXX,XX +XXX,XX @@ PCIBus *pci_dec_21154_init(PCIBus *parent_bus, int devfn)
21
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf);
26
return pci_bridge_get_sec_bus(br);
22
*/
23
void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu);
24
25
+/**
26
+ * kvm_arm_aarch32_supported:
27
+ * @cs: CPUState
28
+ *
29
+ * Returns: true if the KVM VCPU can enable AArch32 mode
30
+ * and false otherwise.
31
+ */
32
+bool kvm_arm_aarch32_supported(CPUState *cs);
33
+
34
/**
35
* kvm_arm_get_max_vm_ipa_size - Returns the number of bits in the
36
* IPA address space supported by KVM
37
@@ -XXX,XX +XXX,XX @@ static inline void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
38
cpu->host_cpu_probe_failed = true;
27
}
39
}
28
40
29
-static int pci_dec_21154_device_init(SysBusDevice *dev)
41
+static inline bool kvm_arm_aarch32_supported(CPUState *cs)
30
+static void pci_dec_21154_device_realize(DeviceState *dev, Error **errp)
42
+{
43
+ return false;
44
+}
45
+
46
static inline int kvm_arm_get_max_vm_ipa_size(MachineState *ms)
31
{
47
{
32
PCIHostState *phb;
48
return -ENOENT;
33
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
49
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
34
50
index XXXXXXX..XXXXXXX 100644
35
phb = PCI_HOST_BRIDGE(dev);
51
--- a/target/arm/cpu64.c
36
52
+++ b/target/arm/cpu64.c
37
@@ -XXX,XX +XXX,XX @@ static int pci_dec_21154_device_init(SysBusDevice *dev)
53
@@ -XXX,XX +XXX,XX @@ static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
38
dev, "pci-conf-idx", 0x1000);
54
* restriction allows us to avoid fixing up functionality that assumes a
39
memory_region_init_io(&phb->data_mem, OBJECT(dev), &pci_host_data_le_ops,
55
* uniform execution state like do_interrupt.
40
dev, "pci-data-idx", 0x1000);
56
*/
41
- sysbus_init_mmio(dev, &phb->conf_mem);
57
- if (!kvm_enabled()) {
42
- sysbus_init_mmio(dev, &phb->data_mem);
58
- error_setg(errp, "'aarch64' feature cannot be disabled "
43
- return 0;
59
- "unless KVM is enabled");
44
+ sysbus_init_mmio(sbd, &phb->conf_mem);
60
- return;
45
+ sysbus_init_mmio(sbd, &phb->data_mem);
61
- }
62
-
63
if (value == false) {
64
+ if (!kvm_enabled() || !kvm_arm_aarch32_supported(CPU(cpu))) {
65
+ error_setg(errp, "'aarch64' feature cannot be disabled "
66
+ "unless KVM is enabled and 32-bit EL1 "
67
+ "is supported");
68
+ return;
69
+ }
70
unset_feature(&cpu->env, ARM_FEATURE_AARCH64);
71
} else {
72
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
73
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
74
index XXXXXXX..XXXXXXX 100644
75
--- a/target/arm/kvm64.c
76
+++ b/target/arm/kvm64.c
77
@@ -XXX,XX +XXX,XX @@
78
#include "exec/gdbstub.h"
79
#include "sysemu/sysemu.h"
80
#include "sysemu/kvm.h"
81
+#include "sysemu/kvm_int.h"
82
#include "kvm_arm.h"
83
+#include "hw/boards.h"
84
#include "internals.h"
85
86
static bool have_guest_debug;
87
@@ -XXX,XX +XXX,XX @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ahcf)
88
return true;
46
}
89
}
47
90
48
static void dec_21154_pci_host_realize(PCIDevice *d, Error **errp)
91
+bool kvm_arm_aarch32_supported(CPUState *cpu)
49
@@ -XXX,XX +XXX,XX @@ static const TypeInfo dec_21154_pci_host_info = {
92
+{
50
93
+ KVMState *s = KVM_STATE(current_machine->accelerator);
51
static void pci_dec_21154_device_class_init(ObjectClass *klass, void *data)
94
+
52
{
95
+ return kvm_check_extension(s, KVM_CAP_ARM_EL1_32BIT);
53
- SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
96
+}
54
+ DeviceClass *dc = DEVICE_CLASS(klass);
97
+
55
98
#define ARM_CPU_ID_MPIDR 3, 0, 0, 0, 5
56
- sdc->init = pci_dec_21154_device_init;
99
57
+ dc->realize = pci_dec_21154_device_realize;
100
int kvm_arch_init_vcpu(CPUState *cs)
58
}
59
60
static const TypeInfo pci_dec_21154_device_info = {
61
--
101
--
62
2.19.2
102
2.20.1
63
103
64
104
diff view generated by jsdifflib
[Qemu-devel] [PULL 13/37] milkymist-hpdmc: Convert sysbus init function to realize function
[Qemu-devel] [PULL 18/29] target/arm/cpu: Ensure we can use the pmu with kvm
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
From: Andrew Jones <drjones@redhat.com>
2
2
3
Use DeviceClass rather than SysBusDeviceClass in
3
We first convert the pmu property from a static property to one with
4
milkymist_hpdmc_class_init().
4
its own accessors. Then we use the set accessor to check if the PMU is
5
supported when using KVM. Indeed a 32-bit KVM host does not support
6
the PMU, so this check will catch an attempt to use it at property-set
7
time.
5
8
6
Cc: gxt@mprc.pku.edu.cn
9
Signed-off-by: Andrew Jones <drjones@redhat.com>
7
Cc: michael@walle.cc
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
8
9
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
10
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Message-id: 20181130093852.20739-12-maozhongyi@cmss.chinamobile.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
12
---
15
hw/misc/milkymist-hpdmc.c | 9 +++------
13
target/arm/kvm_arm.h | 14 ++++++++++++++
16
1 file changed, 3 insertions(+), 6 deletions(-)
14
target/arm/cpu.c | 30 +++++++++++++++++++++++++-----
15
target/arm/kvm.c | 7 +++++++
16
3 files changed, 46 insertions(+), 5 deletions(-)
17
17
18
diff --git a/hw/misc/milkymist-hpdmc.c b/hw/misc/milkymist-hpdmc.c
18
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
19
index XXXXXXX..XXXXXXX 100644
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/misc/milkymist-hpdmc.c
20
--- a/target/arm/kvm_arm.h
21
+++ b/hw/misc/milkymist-hpdmc.c
21
+++ b/target/arm/kvm_arm.h
22
@@ -XXX,XX +XXX,XX @@ static void milkymist_hpdmc_reset(DeviceState *d)
22
@@ -XXX,XX +XXX,XX @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu);
23
| IODELAY_PLL2_LOCKED;
23
*/
24
bool kvm_arm_aarch32_supported(CPUState *cs);
25
26
+/**
27
+ * bool kvm_arm_pmu_supported:
28
+ * @cs: CPUState
29
+ *
30
+ * Returns: true if the KVM VCPU can enable its PMU
31
+ * and false otherwise.
32
+ */
33
+bool kvm_arm_pmu_supported(CPUState *cs);
34
+
35
/**
36
* kvm_arm_get_max_vm_ipa_size - Returns the number of bits in the
37
* IPA address space supported by KVM
38
@@ -XXX,XX +XXX,XX @@ static inline bool kvm_arm_aarch32_supported(CPUState *cs)
39
return false;
24
}
40
}
25
41
26
-static int milkymist_hpdmc_init(SysBusDevice *dev)
42
+static inline bool kvm_arm_pmu_supported(CPUState *cs)
27
+static void milkymist_hpdmc_realize(DeviceState *dev, Error **errp)
43
+{
44
+ return false;
45
+}
46
+
47
static inline int kvm_arm_get_max_vm_ipa_size(MachineState *ms)
28
{
48
{
29
MilkymistHpdmcState *s = MILKYMIST_HPDMC(dev);
49
return -ENOENT;
30
50
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
31
memory_region_init_io(&s->regs_region, OBJECT(dev), &hpdmc_mmio_ops, s,
51
index XXXXXXX..XXXXXXX 100644
32
"milkymist-hpdmc", R_MAX * 4);
52
--- a/target/arm/cpu.c
33
- sysbus_init_mmio(dev, &s->regs_region);
53
+++ b/target/arm/cpu.c
54
@@ -XXX,XX +XXX,XX @@ static Property arm_cpu_has_el3_property =
55
static Property arm_cpu_cfgend_property =
56
DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
57
58
-/* use property name "pmu" to match other archs and virt tools */
59
-static Property arm_cpu_has_pmu_property =
60
- DEFINE_PROP_BOOL("pmu", ARMCPU, has_pmu, true);
34
-
61
-
35
- return 0;
62
static Property arm_cpu_has_vfp_property =
36
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->regs_region);
63
DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true);
64
65
@@ -XXX,XX +XXX,XX @@ static Property arm_cpu_pmsav7_dregion_property =
66
pmsav7_dregion,
67
qdev_prop_uint32, uint32_t);
68
69
+static bool arm_get_pmu(Object *obj, Error **errp)
70
+{
71
+ ARMCPU *cpu = ARM_CPU(obj);
72
+
73
+ return cpu->has_pmu;
74
+}
75
+
76
+static void arm_set_pmu(Object *obj, bool value, Error **errp)
77
+{
78
+ ARMCPU *cpu = ARM_CPU(obj);
79
+
80
+ if (value) {
81
+ if (kvm_enabled() && !kvm_arm_pmu_supported(CPU(cpu))) {
82
+ error_setg(errp, "'pmu' feature not supported by KVM on this host");
83
+ return;
84
+ }
85
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
86
+ } else {
87
+ unset_feature(&cpu->env, ARM_FEATURE_PMU);
88
+ }
89
+ cpu->has_pmu = value;
90
+}
91
+
92
static void arm_get_init_svtor(Object *obj, Visitor *v, const char *name,
93
void *opaque, Error **errp)
94
{
95
@@ -XXX,XX +XXX,XX @@ void arm_cpu_post_init(Object *obj)
96
}
97
98
if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) {
99
- qdev_property_add_static(DEVICE(obj), &arm_cpu_has_pmu_property,
100
+ cpu->has_pmu = true;
101
+ object_property_add_bool(obj, "pmu", arm_get_pmu, arm_set_pmu,
102
&error_abort);
103
}
104
105
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
106
index XXXXXXX..XXXXXXX 100644
107
--- a/target/arm/kvm.c
108
+++ b/target/arm/kvm.c
109
@@ -XXX,XX +XXX,XX @@ void kvm_arm_set_cpu_features_from_host(ARMCPU *cpu)
110
env->features = arm_host_cpu_features.features;
37
}
111
}
38
112
39
static const VMStateDescription vmstate_milkymist_hpdmc = {
113
+bool kvm_arm_pmu_supported(CPUState *cpu)
40
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_milkymist_hpdmc = {
114
+{
41
static void milkymist_hpdmc_class_init(ObjectClass *klass, void *data)
115
+ KVMState *s = KVM_STATE(current_machine->accelerator);
116
+
117
+ return kvm_check_extension(s, KVM_CAP_ARM_PMU_V3);
118
+}
119
+
120
int kvm_arm_get_max_vm_ipa_size(MachineState *ms)
42
{
121
{
43
DeviceClass *dc = DEVICE_CLASS(klass);
122
KVMState *s = KVM_STATE(ms->accelerator);
44
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
45
46
- k->init = milkymist_hpdmc_init;
47
+ dc->realize = milkymist_hpdmc_realize;
48
dc->reset = milkymist_hpdmc_reset;
49
dc->vmsd = &vmstate_milkymist_hpdmc;
50
}
51
--
123
--
52
2.19.2
124
2.20.1
53
125
54
126
diff view generated by jsdifflib
[Qemu-devel] [PULL 31/37] target/arm: Fix HCR_EL2.TGE check in arm_phys_excp_target_el
[Qemu-devel] [PULL 19/29] target/arm/helper: zcr: Add build bug next to value range assumption
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Andrew Jones <drjones@redhat.com>
2
2
3
The enable for TGE has already occurred within arm_hcr_el2_amo
3
The current implementation of ZCR_ELx matches the architecture, only
4
and friends. Moreover, when E2H is also set, the sense is
4
implementing the lower four bits, with the rest RAZ/WI. This puts
5
supposed to be reversed, which has also already occurred within
5
a strict limit on ARM_MAX_VQ of 16. Make sure we don't let ARM_MAX_VQ
6
the helpers.
6
grow without a corresponding update here.
7
7
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Suggested-by: Dave Martin <Dave.Martin@arm.com>
9
Message-id: 20181203203839.757-5-richard.henderson@linaro.org
9
Signed-off-by: Andrew Jones <drjones@redhat.com>
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
11
Reviewed-by: Eric Auger <eric.auger@redhat.com>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
13
---
13
target/arm/helper.c | 3 ---
14
target/arm/helper.c | 1 +
14
1 file changed, 3 deletions(-)
15
1 file changed, 1 insertion(+)
15
16
16
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
diff --git a/target/arm/helper.c b/target/arm/helper.c
17
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
18
--- a/target/arm/helper.c
19
--- a/target/arm/helper.c
19
+++ b/target/arm/helper.c
20
+++ b/target/arm/helper.c
20
@@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
21
@@ -XXX,XX +XXX,XX @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
21
break;
22
int new_len;
22
};
23
23
24
/* Bits other than [3:0] are RAZ/WI. */
24
- /* If HCR.TGE is set then HCR is treated as being 1 */
25
+ QEMU_BUILD_BUG_ON(ARM_MAX_VQ > 16);
25
- hcr |= ((env->cp15.hcr_el2 & HCR_TGE) == HCR_TGE);
26
raw_write(env, ri, value & 0xf);
26
-
27
27
/* Perform a table-lookup for the target EL given the current state */
28
/*
28
target_el = target_el_table[is64][scr][rw][hcr][secure][cur_el];
29
30
--
29
--
31
2.19.2
30
2.20.1
32
31
33
32
diff view generated by jsdifflib
[Qemu-devel] [PULL 34/37] target/arm: Implement the ARMv8.2-AA32HPD extension
[Qemu-devel] [PULL 20/29] target/arm/cpu: Use div-round-up to determine predicate register array size
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Andrew Jones <drjones@redhat.com>
2
2
3
The bulk of the work here, beyond base HPD, is defining the
3
Unless we're guaranteed to always increase ARM_MAX_VQ by a multiple of
4
TTBCR2 register. In addition we must check TTBCR.T2E, which
4
four, then we should use DIV_ROUND_UP to ensure we get an appropriate
5
is not present (RES0) for AArch64.
5
array size.
6
6
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
7
Signed-off-by: Andrew Jones <drjones@redhat.com>
8
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20181203203839.757-11-richard.henderson@linaro.org
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
10
---
12
target/arm/cpu.h | 9 +++++++++
11
target/arm/cpu.h | 2 +-
13
target/arm/cpu.c | 4 ++++
12
1 file changed, 1 insertion(+), 1 deletion(-)
14
target/arm/helper.c | 37 +++++++++++++++++++++++++++++--------
15
3 files changed, 42 insertions(+), 8 deletions(-)
16
13
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
18
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.h
16
--- a/target/arm/cpu.h
20
+++ b/target/arm/cpu.h
17
+++ b/target/arm/cpu.h
21
@@ -XXX,XX +XXX,XX @@ FIELD(ID_ISAR6, FHM, 8, 4)
18
@@ -XXX,XX +XXX,XX @@ typedef struct ARMVectorReg {
22
FIELD(ID_ISAR6, SB, 12, 4)
19
#ifdef TARGET_AARCH64
23
FIELD(ID_ISAR6, SPECRES, 16, 4)
20
/* In AArch32 mode, predicate registers do not exist at all. */
24
21
typedef struct ARMPredicateReg {
25
+FIELD(ID_MMFR4, SPECSEI, 0, 4)
22
- uint64_t p[2 * ARM_MAX_VQ / 8] QEMU_ALIGNED(16);
26
+FIELD(ID_MMFR4, AC2, 4, 4)
23
+ uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16);
27
+FIELD(ID_MMFR4, XNX, 8, 4)
24
} ARMPredicateReg;
28
+FIELD(ID_MMFR4, CNP, 12, 4)
25
29
+FIELD(ID_MMFR4, HPDS, 16, 4)
26
/* In AArch32 mode, PAC keys do not exist at all. */
30
+FIELD(ID_MMFR4, LSM, 20, 4)
31
+FIELD(ID_MMFR4, CCIDX, 24, 4)
32
+FIELD(ID_MMFR4, EVT, 28, 4)
33
+
34
FIELD(ID_AA64ISAR0, AES, 4, 4)
35
FIELD(ID_AA64ISAR0, SHA1, 8, 4)
36
FIELD(ID_AA64ISAR0, SHA2, 12, 4)
37
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
38
index XXXXXXX..XXXXXXX 100644
39
--- a/target/arm/cpu.c
40
+++ b/target/arm/cpu.c
41
@@ -XXX,XX +XXX,XX @@ static void arm_max_initfn(Object *obj)
42
t = cpu->isar.id_isar6;
43
t = FIELD_DP32(t, ID_ISAR6, DP, 1);
44
cpu->isar.id_isar6 = t;
45
+
46
+ t = cpu->id_mmfr4;
47
+ t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
48
+ cpu->id_mmfr4 = t;
49
}
50
#endif
51
}
52
diff --git a/target/arm/helper.c b/target/arm/helper.c
53
index XXXXXXX..XXXXXXX 100644
54
--- a/target/arm/helper.c
55
+++ b/target/arm/helper.c
56
@@ -XXX,XX +XXX,XX @@ static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
57
uint64_t value)
58
{
59
ARMCPU *cpu = arm_env_get_cpu(env);
60
+ TCR *tcr = raw_ptr(env, ri);
61
62
if (arm_feature(env, ARM_FEATURE_LPAE)) {
63
/* With LPAE the TTBCR could result in a change of ASID
64
@@ -XXX,XX +XXX,XX @@ static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
65
*/
66
tlb_flush(CPU(cpu));
67
}
68
+ /* Preserve the high half of TCR_EL1, set via TTBCR2. */
69
+ value = deposit64(tcr->raw_tcr, 0, 32, value);
70
vmsa_ttbcr_raw_write(env, ri, value);
71
}
72
73
@@ -XXX,XX +XXX,XX @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
74
REGINFO_SENTINEL
75
};
76
77
+/* Note that unlike TTBCR, writing to TTBCR2 does not require flushing
78
+ * qemu tlbs nor adjusting cached masks.
79
+ */
80
+static const ARMCPRegInfo ttbcr2_reginfo = {
81
+ .name = "TTBCR2", .cp = 15, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 3,
82
+ .access = PL1_RW, .type = ARM_CP_ALIAS,
83
+ .bank_fieldoffsets = { offsetofhigh32(CPUARMState, cp15.tcr_el[3]),
84
+ offsetofhigh32(CPUARMState, cp15.tcr_el[1]) },
85
+};
86
+
87
static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
88
uint64_t value)
89
{
90
@@ -XXX,XX +XXX,XX @@ void register_cp_regs_for_features(ARMCPU *cpu)
91
} else {
92
define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
93
define_arm_cp_regs(cpu, vmsa_cp_reginfo);
94
+ /* TTCBR2 is introduced with ARMv8.2-A32HPD. */
95
+ if (FIELD_EX32(cpu->id_mmfr4, ID_MMFR4, HPDS) != 0) {
96
+ define_one_arm_cp_reg(cpu, &ttbcr2_reginfo);
97
+ }
98
}
99
if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
100
define_arm_cp_regs(cpu, t2ee_cp_reginfo);
101
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
102
if (tg == 2) { /* 16KB pages */
103
stride = 11;
104
}
105
- if (aarch64) {
106
- if (el > 1) {
107
- hpd = extract64(tcr->raw_tcr, 24, 1);
108
- } else {
109
- hpd = extract64(tcr->raw_tcr, 41, 1);
110
- }
111
+ if (aarch64 && el > 1) {
112
+ hpd = extract64(tcr->raw_tcr, 24, 1);
113
+ } else {
114
+ hpd = extract64(tcr->raw_tcr, 41, 1);
115
+ }
116
+ if (!aarch64) {
117
+ /* For aarch32, hpd0 is not enabled without t2e as well. */
118
+ hpd &= extract64(tcr->raw_tcr, 6, 1);
119
}
120
} else {
121
/* We should only be here if TTBR1 is valid */
122
@@ -XXX,XX +XXX,XX @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
123
if (tg == 1) { /* 16KB pages */
124
stride = 11;
125
}
126
- if (aarch64) {
127
- hpd = extract64(tcr->raw_tcr, 42, 1);
128
+ hpd = extract64(tcr->raw_tcr, 42, 1);
129
+ if (!aarch64) {
130
+ /* For aarch32, hpd1 is not enabled without t2e as well. */
131
+ hpd &= extract64(tcr->raw_tcr, 6, 1);
132
}
133
}
134
135
--
27
--
136
2.19.2
28
2.20.1
137
29
138
30
diff view generated by jsdifflib
[Qemu-devel] [PULL 24/37] hw/arm: versal: Remove bogus virtio-mmio creation
[Qemu-devel] [PULL 21/29] target/arm/kvm64: Fix error returns
1
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
1
From: Andrew Jones <drjones@redhat.com>
2
2
3
Remove bogus virtio-mmio creation. This was an accidental
3
A couple return -EINVAL's forgot their '-'s.
4
left-over an experiment.
5
4
6
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
5
Signed-off-by: Andrew Jones <drjones@redhat.com>
7
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
6
Reviewed-by: Eric Auger <eric.auger@redhat.com>
8
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
7
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
9
Message-id: 20181129163655.20370-2-edgar.iglesias@gmail.com
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
9
---
12
hw/arm/xlnx-versal-virt.c | 1 -
10
target/arm/kvm64.c | 4 ++--
13
1 file changed, 1 deletion(-)
11
1 file changed, 2 insertions(+), 2 deletions(-)
14
12
15
diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c
13
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
16
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
17
--- a/hw/arm/xlnx-versal-virt.c
15
--- a/target/arm/kvm64.c
18
+++ b/hw/arm/xlnx-versal-virt.c
16
+++ b/target/arm/kvm64.c
19
@@ -XXX,XX +XXX,XX @@ static void create_virtio_regions(VersalVirt *s)
17
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
20
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic_irq);
18
write_cpustate_to_list(cpu, true);
21
mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0);
19
22
memory_region_add_subregion(&s->soc.mr_ps, base, mr);
20
if (!write_list_to_kvmstate(cpu, level)) {
23
- sysbus_create_simple("virtio-mmio", base, pic_irq);
21
- return EINVAL;
22
+ return -EINVAL;
24
}
23
}
25
24
26
for (i = 0; i < NUM_VIRTIO_TRANSPORT; i++) {
25
kvm_arm_sync_mpstate_to_kvm(cpu);
26
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
27
}
28
29
if (!write_kvmstate_to_list(cpu)) {
30
- return EINVAL;
31
+ return -EINVAL;
32
}
33
/* Note that it's OK to have registers which aren't in CPUState,
34
* so we can ignore a failure return here.
27
--
35
--
28
2.19.2
36
2.20.1
29
37
30
38
diff view generated by jsdifflib
[Qemu-devel] [PULL 14/37] milkymist-pfpu: Convert sysbus init function to realize function
[Qemu-devel] [PULL 22/29] target/arm/kvm64: Move the get/put of fpsimd registers out
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
From: Andrew Jones <drjones@redhat.com>
2
2
3
Use DeviceClass rather than SysBusDeviceClass in
3
Move the getting/putting of the fpsimd registers out of
4
milkymist_pfpu_class_init().
4
kvm_arch_get/put_registers() into their own helper functions
5
5
to prepare for alternatively getting/putting SVE registers.
6
Cc: michael@walle.cc
6
7
7
No functional change.
8
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
8
9
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
9
Signed-off-by: Andrew Jones <drjones@redhat.com>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
10
Reviewed-by: Eric Auger <eric.auger@redhat.com>
11
Message-id: 20181130093852.20739-13-maozhongyi@cmss.chinamobile.com
11
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
13
---
14
hw/misc/milkymist-pfpu.c | 12 +++++-------
14
target/arm/kvm64.c | 148 +++++++++++++++++++++++++++------------------
15
1 file changed, 5 insertions(+), 7 deletions(-)
15
1 file changed, 88 insertions(+), 60 deletions(-)
16
16
17
diff --git a/hw/misc/milkymist-pfpu.c b/hw/misc/milkymist-pfpu.c
17
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
18
index XXXXXXX..XXXXXXX 100644
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/misc/milkymist-pfpu.c
19
--- a/target/arm/kvm64.c
20
+++ b/hw/misc/milkymist-pfpu.c
20
+++ b/target/arm/kvm64.c
21
@@ -XXX,XX +XXX,XX @@ static void milkymist_pfpu_reset(DeviceState *d)
21
@@ -XXX,XX +XXX,XX @@ int kvm_arm_cpreg_level(uint64_t regidx)
22
}
22
#define AARCH64_SIMD_CTRL_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U32 | \
23
KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
24
25
+static int kvm_arch_put_fpsimd(CPUState *cs)
26
+{
27
+ ARMCPU *cpu = ARM_CPU(cs);
28
+ CPUARMState *env = &cpu->env;
29
+ struct kvm_one_reg reg;
30
+ uint32_t fpr;
31
+ int i, ret;
32
+
33
+ for (i = 0; i < 32; i++) {
34
+ uint64_t *q = aa64_vfp_qreg(env, i);
35
+#ifdef HOST_WORDS_BIGENDIAN
36
+ uint64_t fp_val[2] = { q[1], q[0] };
37
+ reg.addr = (uintptr_t)fp_val;
38
+#else
39
+ reg.addr = (uintptr_t)q;
40
+#endif
41
+ reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
42
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
43
+ if (ret) {
44
+ return ret;
45
+ }
46
+ }
47
+
48
+ reg.addr = (uintptr_t)(&fpr);
49
+ fpr = vfp_get_fpsr(env);
50
+ reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
51
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
52
+ if (ret) {
53
+ return ret;
54
+ }
55
+
56
+ reg.addr = (uintptr_t)(&fpr);
57
+ fpr = vfp_get_fpcr(env);
58
+ reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
59
+ ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
60
+ if (ret) {
61
+ return ret;
62
+ }
63
+
64
+ return 0;
65
+}
66
+
67
int kvm_arch_put_registers(CPUState *cs, int level)
68
{
69
struct kvm_one_reg reg;
70
- uint32_t fpr;
71
uint64_t val;
72
- int i;
73
- int ret;
74
+ int i, ret;
75
unsigned int el;
76
77
ARMCPU *cpu = ARM_CPU(cs);
78
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
79
}
80
}
81
82
- /* Advanced SIMD and FP registers. */
83
- for (i = 0; i < 32; i++) {
84
- uint64_t *q = aa64_vfp_qreg(env, i);
85
-#ifdef HOST_WORDS_BIGENDIAN
86
- uint64_t fp_val[2] = { q[1], q[0] };
87
- reg.addr = (uintptr_t)fp_val;
88
-#else
89
- reg.addr = (uintptr_t)q;
90
-#endif
91
- reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
92
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
93
- if (ret) {
94
- return ret;
95
- }
96
- }
97
-
98
- reg.addr = (uintptr_t)(&fpr);
99
- fpr = vfp_get_fpsr(env);
100
- reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
101
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
102
- if (ret) {
103
- return ret;
104
- }
105
-
106
- fpr = vfp_get_fpcr(env);
107
- reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
108
- ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &reg);
109
+ ret = kvm_arch_put_fpsimd(cs);
110
if (ret) {
111
return ret;
112
}
113
@@ -XXX,XX +XXX,XX @@ int kvm_arch_put_registers(CPUState *cs, int level)
114
return ret;
23
}
115
}
24
116
25
-static int milkymist_pfpu_init(SysBusDevice *dev)
117
+static int kvm_arch_get_fpsimd(CPUState *cs)
26
+static void milkymist_pfpu_realize(DeviceState *dev, Error **errp)
118
+{
119
+ ARMCPU *cpu = ARM_CPU(cs);
120
+ CPUARMState *env = &cpu->env;
121
+ struct kvm_one_reg reg;
122
+ uint32_t fpr;
123
+ int i, ret;
124
+
125
+ for (i = 0; i < 32; i++) {
126
+ uint64_t *q = aa64_vfp_qreg(env, i);
127
+ reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
128
+ reg.addr = (uintptr_t)q;
129
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
130
+ if (ret) {
131
+ return ret;
132
+ } else {
133
+#ifdef HOST_WORDS_BIGENDIAN
134
+ uint64_t t;
135
+ t = q[0], q[0] = q[1], q[1] = t;
136
+#endif
137
+ }
138
+ }
139
+
140
+ reg.addr = (uintptr_t)(&fpr);
141
+ reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
142
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
143
+ if (ret) {
144
+ return ret;
145
+ }
146
+ vfp_set_fpsr(env, fpr);
147
+
148
+ reg.addr = (uintptr_t)(&fpr);
149
+ reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
150
+ ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
151
+ if (ret) {
152
+ return ret;
153
+ }
154
+ vfp_set_fpcr(env, fpr);
155
+
156
+ return 0;
157
+}
158
+
159
int kvm_arch_get_registers(CPUState *cs)
27
{
160
{
28
MilkymistPFPUState *s = MILKYMIST_PFPU(dev);
161
struct kvm_one_reg reg;
29
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
162
uint64_t val;
30
163
- uint32_t fpr;
31
- sysbus_init_irq(dev, &s->irq);
164
unsigned int el;
32
+ sysbus_init_irq(sbd, &s->irq);
165
- int i;
33
166
- int ret;
34
memory_region_init_io(&s->regs_region, OBJECT(dev), &pfpu_mmio_ops, s,
167
+ int i, ret;
35
"milkymist-pfpu", MICROCODE_END * 4);
168
36
- sysbus_init_mmio(dev, &s->regs_region);
169
ARMCPU *cpu = ARM_CPU(cs);
37
-
170
CPUARMState *env = &cpu->env;
38
- return 0;
171
@@ -XXX,XX +XXX,XX @@ int kvm_arch_get_registers(CPUState *cs)
39
+ sysbus_init_mmio(sbd, &s->regs_region);
172
env->spsr = env->banked_spsr[i];
40
}
173
}
41
174
42
static const VMStateDescription vmstate_milkymist_pfpu = {
175
- /* Advanced SIMD and FP registers */
43
@@ -XXX,XX +XXX,XX @@ static const VMStateDescription vmstate_milkymist_pfpu = {
176
- for (i = 0; i < 32; i++) {
44
static void milkymist_pfpu_class_init(ObjectClass *klass, void *data)
177
- uint64_t *q = aa64_vfp_qreg(env, i);
45
{
178
- reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
46
DeviceClass *dc = DEVICE_CLASS(klass);
179
- reg.addr = (uintptr_t)q;
47
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
180
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
48
181
- if (ret) {
49
- k->init = milkymist_pfpu_init;
182
- return ret;
50
+ dc->realize = milkymist_pfpu_realize;
183
- } else {
51
dc->reset = milkymist_pfpu_reset;
184
-#ifdef HOST_WORDS_BIGENDIAN
52
dc->vmsd = &vmstate_milkymist_pfpu;
185
- uint64_t t;
53
}
186
- t = q[0], q[0] = q[1], q[1] = t;
187
-#endif
188
- }
189
- }
190
-
191
- reg.addr = (uintptr_t)(&fpr);
192
- reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
193
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
194
+ ret = kvm_arch_get_fpsimd(cs);
195
if (ret) {
196
return ret;
197
}
198
- vfp_set_fpsr(env, fpr);
199
-
200
- reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
201
- ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &reg);
202
- if (ret) {
203
- return ret;
204
- }
205
- vfp_set_fpcr(env, fpr);
206
207
ret = kvm_get_vcpu_events(cpu);
208
if (ret) {
54
--
209
--
55
2.19.2
210
2.20.1
56
211
57
212
diff view generated by jsdifflib
[Qemu-devel] [PULL 16/37] nvram/ds1225y: Convert sysbus init function to realize function
[Qemu-devel] [PULL 23/29] target/arm: Use tcg_gen_extract_i32 for shifter_out_im
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Use DeviceClass rather than SysBusDeviceClass in
3
Extract is a compact combination of shift + and.
4
nvram_sysbus_class_init().
5
4
6
Cc: pbonzini@redhat.com
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Cc: marcandre.lureau@redhat.com
6
Message-id: 20190808202616.13782-2-richard.henderson@linaro.org
8
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
10
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Message-id: 20181130093852.20739-15-maozhongyi@cmss.chinamobile.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
9
---
15
hw/nvram/ds1225y.c | 12 +++++-------
10
target/arm/translate.c | 9 +--------
16
1 file changed, 5 insertions(+), 7 deletions(-)
11
1 file changed, 1 insertion(+), 8 deletions(-)
17
12
18
diff --git a/hw/nvram/ds1225y.c b/hw/nvram/ds1225y.c
13
diff --git a/target/arm/translate.c b/target/arm/translate.c
19
index XXXXXXX..XXXXXXX 100644
14
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/nvram/ds1225y.c
15
--- a/target/arm/translate.c
21
+++ b/hw/nvram/ds1225y.c
16
+++ b/target/arm/translate.c
22
@@ -XXX,XX +XXX,XX @@
17
@@ -XXX,XX +XXX,XX @@ static void gen_sar(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1)
23
#include "qemu/osdep.h"
18
24
#include "hw/sysbus.h"
19
static void shifter_out_im(TCGv_i32 var, int shift)
25
#include "trace.h"
26
+#include "qemu/error-report.h"
27
28
typedef struct {
29
MemoryRegion iomem;
30
@@ -XXX,XX +XXX,XX @@ typedef struct {
31
NvRamState nvram;
32
} SysBusNvRamState;
33
34
-static int nvram_sysbus_initfn(SysBusDevice *dev)
35
+static void nvram_sysbus_realize(DeviceState *dev, Error **errp)
36
{
20
{
37
SysBusNvRamState *sys = DS1225Y(dev);
21
- if (shift == 0) {
38
NvRamState *s = &sys->nvram;
22
- tcg_gen_andi_i32(cpu_CF, var, 1);
39
@@ -XXX,XX +XXX,XX @@ static int nvram_sysbus_initfn(SysBusDevice *dev)
23
- } else {
40
24
- tcg_gen_shri_i32(cpu_CF, var, shift);
41
memory_region_init_io(&s->iomem, OBJECT(s), &nvram_ops, s,
25
- if (shift != 31) {
42
"nvram", s->chip_size);
26
- tcg_gen_andi_i32(cpu_CF, cpu_CF, 1);
43
- sysbus_init_mmio(dev, &s->iomem);
27
- }
44
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
28
- }
45
29
+ tcg_gen_extract_i32(cpu_CF, var, shift, 1);
46
/* Read current file */
47
file = s->filename ? fopen(s->filename, "rb") : NULL;
48
if (file) {
49
/* Read nvram contents */
50
if (fread(s->contents, s->chip_size, 1, file) != 1) {
51
- printf("nvram_sysbus_initfn: short read\n");
52
+ error_report("nvram_sysbus_realize: short read");
53
}
54
fclose(file);
55
}
56
nvram_post_load(s, 0);
57
-
58
- return 0;
59
}
30
}
60
31
61
static Property nvram_sysbus_properties[] = {
32
/* Shift by immediate. Includes special handling for shift == 0. */
62
@@ -XXX,XX +XXX,XX @@ static Property nvram_sysbus_properties[] = {
63
static void nvram_sysbus_class_init(ObjectClass *klass, void *data)
64
{
65
DeviceClass *dc = DEVICE_CLASS(klass);
66
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
67
68
- k->init = nvram_sysbus_initfn;
69
+ dc->realize = nvram_sysbus_realize;
70
dc->vmsd = &vmstate_nvram;
71
dc->props = nvram_sysbus_properties;
72
}
73
--
33
--
74
2.19.2
34
2.20.1
75
35
76
36
diff view generated by jsdifflib
[Qemu-devel] [PULL 29/37] target/arm: Add HCR_EL2 bits up to ARMv8.5
[Qemu-devel] [PULL 24/29] target/arm: Use tcg_gen_deposit_i32 for PKHBT, PKHTB
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Post v8.3 bits taken from SysReg_v85_xml-00bet8.
3
Use deposit as the composit operation to merge the
4
bits from the two inputs.
4
5
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20181203203839.757-3-richard.henderson@linaro.org
7
Message-id: 20190808202616.13782-3-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
---
10
target/arm/cpu.h | 22 +++++++++++++++++++++-
11
target/arm/translate.c | 26 ++++++++++----------------
11
1 file changed, 21 insertions(+), 1 deletion(-)
12
1 file changed, 10 insertions(+), 16 deletions(-)
12
13
13
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/cpu.h
16
--- a/target/arm/translate.c
16
+++ b/target/arm/cpu.h
17
+++ b/target/arm/translate.c
17
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
18
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
18
#define HCR_TIDCP (1ULL << 20)
19
shift = (insn >> 7) & 0x1f;
19
#define HCR_TACR (1ULL << 21)
20
if (insn & (1 << 6)) {
20
#define HCR_TSW (1ULL << 22)
21
/* pkhtb */
21
-#define HCR_TPC (1ULL << 23)
22
- if (shift == 0)
22
+#define HCR_TPCP (1ULL << 23)
23
+ if (shift == 0) {
23
#define HCR_TPU (1ULL << 24)
24
shift = 31;
24
#define HCR_TTLB (1ULL << 25)
25
+ }
25
#define HCR_TVM (1ULL << 26)
26
tcg_gen_sari_i32(tmp2, tmp2, shift);
26
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
27
- tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
27
#define HCR_CD (1ULL << 32)
28
- tcg_gen_ext16u_i32(tmp2, tmp2);
28
#define HCR_ID (1ULL << 33)
29
+ tcg_gen_deposit_i32(tmp, tmp, tmp2, 0, 16);
29
#define HCR_E2H (1ULL << 34)
30
} else {
30
+#define HCR_TLOR (1ULL << 35)
31
/* pkhbt */
31
+#define HCR_TERR (1ULL << 36)
32
- if (shift)
32
+#define HCR_TEA (1ULL << 37)
33
- tcg_gen_shli_i32(tmp2, tmp2, shift);
33
+#define HCR_MIOCNCE (1ULL << 38)
34
- tcg_gen_ext16u_i32(tmp, tmp);
34
+#define HCR_APK (1ULL << 40)
35
- tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
35
+#define HCR_API (1ULL << 41)
36
+ tcg_gen_shli_i32(tmp2, tmp2, shift);
36
+#define HCR_NV (1ULL << 42)
37
+ tcg_gen_deposit_i32(tmp, tmp2, tmp, 0, 16);
37
+#define HCR_NV1 (1ULL << 43)
38
}
38
+#define HCR_AT (1ULL << 44)
39
- tcg_gen_or_i32(tmp, tmp, tmp2);
39
+#define HCR_NV2 (1ULL << 45)
40
tcg_temp_free_i32(tmp2);
40
+#define HCR_FWB (1ULL << 46)
41
store_reg(s, rd, tmp);
41
+#define HCR_FIEN (1ULL << 47)
42
} else if ((insn & 0x00200020) == 0x00200000) {
42
+#define HCR_TID4 (1ULL << 49)
43
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
43
+#define HCR_TICAB (1ULL << 50)
44
shift = ((insn >> 10) & 0x1c) | ((insn >> 6) & 0x3);
44
+#define HCR_TOCU (1ULL << 52)
45
if (insn & (1 << 5)) {
45
+#define HCR_TTLBIS (1ULL << 54)
46
/* pkhtb */
46
+#define HCR_TTLBOS (1ULL << 55)
47
- if (shift == 0)
47
+#define HCR_ATA (1ULL << 56)
48
+ if (shift == 0) {
48
+#define HCR_DCT (1ULL << 57)
49
shift = 31;
49
+
50
+ }
50
/*
51
tcg_gen_sari_i32(tmp2, tmp2, shift);
51
* When we actually implement ARMv8.1-VHE we should add HCR_E2H to
52
- tcg_gen_andi_i32(tmp, tmp, 0xffff0000);
52
* HCR_MASK and then clear it again if the feature bit is not set in
53
- tcg_gen_ext16u_i32(tmp2, tmp2);
54
+ tcg_gen_deposit_i32(tmp, tmp, tmp2, 0, 16);
55
} else {
56
/* pkhbt */
57
- if (shift)
58
- tcg_gen_shli_i32(tmp2, tmp2, shift);
59
- tcg_gen_ext16u_i32(tmp, tmp);
60
- tcg_gen_andi_i32(tmp2, tmp2, 0xffff0000);
61
+ tcg_gen_shli_i32(tmp2, tmp2, shift);
62
+ tcg_gen_deposit_i32(tmp, tmp2, tmp, 0, 16);
63
}
64
- tcg_gen_or_i32(tmp, tmp, tmp2);
65
tcg_temp_free_i32(tmp2);
66
store_reg(s, rd, tmp);
67
} else {
53
--
68
--
54
2.19.2
69
2.20.1
55
70
56
71
diff view generated by jsdifflib
[Qemu-devel] [PULL 32/37] target/arm: Tidy scr_write
[Qemu-devel] [PULL 25/29] target/arm: Remove redundant shift tests
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Because EL3 has a fixed execution mode, we can properly decide
3
The immediate shift generator functions already test for,
4
which of the bits are RES{0,1}.
4
and eliminate, the case of a shift by zero.
5
5
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Message-id: 20181203203839.757-8-richard.henderson@linaro.org
7
Message-id: 20190808202616.13782-4-richard.henderson@linaro.org
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
---
10
---
11
target/arm/cpu.h | 2 --
11
target/arm/translate.c | 19 +++++++------------
12
target/arm/helper.c | 14 +++++++++-----
12
1 file changed, 7 insertions(+), 12 deletions(-)
13
2 files changed, 9 insertions(+), 7 deletions(-)
14
13
15
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
16
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
17
--- a/target/arm/cpu.h
16
--- a/target/arm/translate.c
18
+++ b/target/arm/cpu.h
17
+++ b/target/arm/translate.c
19
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
18
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
20
#define SCR_FIEN (1U << 21)
19
shift = (insn >> 10) & 3;
21
#define SCR_ENSCXT (1U << 25)
20
/* ??? In many cases it's not necessary to do a
22
#define SCR_ATA (1U << 26)
21
rotate, a shift is sufficient. */
23
-#define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
22
- if (shift != 0)
24
-#define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
23
- tcg_gen_rotri_i32(tmp, tmp, shift * 8);
25
24
+ tcg_gen_rotri_i32(tmp, tmp, shift * 8);
26
/* Return the current FPSCR value. */
25
op1 = (insn >> 20) & 7;
27
uint32_t vfp_get_fpscr(CPUARMState *env);
26
switch (op1) {
28
diff --git a/target/arm/helper.c b/target/arm/helper.c
27
case 0: gen_sxtb16(tmp); break;
29
index XXXXXXX..XXXXXXX 100644
28
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
30
--- a/target/arm/helper.c
29
shift = (insn >> 4) & 3;
31
+++ b/target/arm/helper.c
30
/* ??? In many cases it's not necessary to do a
32
@@ -XXX,XX +XXX,XX @@ static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
31
rotate, a shift is sufficient. */
33
32
- if (shift != 0)
34
static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
33
- tcg_gen_rotri_i32(tmp, tmp, shift * 8);
35
{
34
+ tcg_gen_rotri_i32(tmp, tmp, shift * 8);
36
- /* We only mask off bits that are RES0 both for AArch64 and AArch32.
35
op = (insn >> 20) & 7;
37
- * For bits that vary between AArch32/64, code needs to check the
36
switch (op) {
38
- * current execution mode before directly using the feature bit.
37
case 0: gen_sxth(tmp); break;
39
- */
38
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
40
- uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK;
39
case 7:
41
+ /* Begin with base v8.0 state. */
40
goto illegal_op;
42
+ uint32_t valid_mask = 0x3fff;
41
default: /* Saturate. */
43
+
42
- if (shift) {
44
+ if (arm_el_is_aa64(env, 3)) {
43
- if (op & 1)
45
+ value |= SCR_FW | SCR_AW; /* these two bits are RES1. */
44
- tcg_gen_sari_i32(tmp, tmp, shift);
46
+ valid_mask &= ~SCR_NET;
45
- else
47
+ } else {
46
- tcg_gen_shli_i32(tmp, tmp, shift);
48
+ valid_mask &= ~(SCR_RW | SCR_ST);
47
+ if (op & 1) {
49
+ }
48
+ tcg_gen_sari_i32(tmp, tmp, shift);
50
49
+ } else {
51
if (!arm_feature(env, ARM_FEATURE_EL2)) {
50
+ tcg_gen_shli_i32(tmp, tmp, shift);
52
valid_mask &= ~SCR_HCE;
51
}
52
tmp2 = tcg_const_i32(imm);
53
if (op & 4) {
54
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
55
goto illegal_op;
56
}
57
tmp = load_reg(s, rm);
58
- if (shift) {
59
- tcg_gen_shli_i32(tmp, tmp, shift);
60
- }
61
+ tcg_gen_shli_i32(tmp, tmp, shift);
62
tcg_gen_add_i32(addr, addr, tmp);
63
tcg_temp_free_i32(tmp);
64
break;
53
--
65
--
54
2.19.2
66
2.20.1
55
67
56
68
diff view generated by jsdifflib
[Qemu-devel] [PULL 01/37] hw: arm: musicpal: drop TYPE_WM8750 in object_property_set_link()
[Qemu-devel] [PULL 26/29] target/arm: Use ror32 instead of open-coding the operation
1
From: Li Qiang <liq3ea@gmail.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
The third argument of object_property_set_link() is the name of
3
The helper function is more documentary, and also already
4
property, not related with the QOM type name, using the constant
4
handles the case of rotate by zero.
5
string instead.
6
5
7
Signed-off-by: Li Qiang <liq3ea@gmail.com>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
7
Message-id: 20190808202616.13782-5-richard.henderson@linaro.org
9
Message-id: 1542880825-2604-1-git-send-email-liq3ea@gmail.com
10
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
11
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12
---
10
---
13
hw/arm/musicpal.c | 2 +-
11
target/arm/translate.c | 7 ++-----
14
1 file changed, 1 insertion(+), 1 deletion(-)
12
1 file changed, 2 insertions(+), 5 deletions(-)
15
13
16
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
17
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
18
--- a/hw/arm/musicpal.c
16
--- a/target/arm/translate.c
19
+++ b/hw/arm/musicpal.c
17
+++ b/target/arm/translate.c
20
@@ -XXX,XX +XXX,XX @@ static void musicpal_init(MachineState *machine)
18
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
21
dev = qdev_create(NULL, TYPE_MV88W8618_AUDIO);
19
/* CPSR = immediate */
22
s = SYS_BUS_DEVICE(dev);
20
val = insn & 0xff;
23
object_property_set_link(OBJECT(dev), OBJECT(wm8750_dev),
21
shift = ((insn >> 8) & 0xf) * 2;
24
- TYPE_WM8750, NULL);
22
- if (shift)
25
+ "wm8750", NULL);
23
- val = (val >> shift) | (val << (32 - shift));
26
qdev_init_nofail(dev);
24
+ val = ror32(val, shift);
27
sysbus_mmio_map(s, 0, MP_AUDIO_BASE);
25
i = ((insn & (1 << 22)) != 0);
28
sysbus_connect_irq(s, 0, pic[MP_AUDIO_IRQ]);
26
if (gen_set_psr_im(s, msr_mask(s, (insn >> 16) & 0xf, i),
27
i, val)) {
28
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
29
/* immediate operand */
30
val = insn & 0xff;
31
shift = ((insn >> 8) & 0xf) * 2;
32
- if (shift) {
33
- val = (val >> shift) | (val << (32 - shift));
34
- }
35
+ val = ror32(val, shift);
36
tmp2 = tcg_temp_new_i32();
37
tcg_gen_movi_i32(tmp2, val);
38
if (logic_cc && shift) {
29
--
39
--
30
2.19.2
40
2.20.1
31
41
32
42
diff view generated by jsdifflib
[Qemu-devel] [PULL 03/37] musicpal: Convert sysbus init function to realize function
Deleted patch
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
2
1
3
Use DeviceClass rather than SysBusDeviceClass in
4
mv88w8618_wlan_class_init().
5
6
Cc: jan.kiszka@web.de
7
Cc: peter.maydell@linaro.org
8
Cc: qemu-arm@nongnu.org
9
10
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
11
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Message-id: 20181130093852.20739-2-maozhongyi@cmss.chinamobile.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/arm/musicpal.c | 9 ++++-----
17
1 file changed, 4 insertions(+), 5 deletions(-)
18
19
diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/arm/musicpal.c
22
+++ b/hw/arm/musicpal.c
23
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps mv88w8618_wlan_ops = {
24
.endianness = DEVICE_NATIVE_ENDIAN,
25
};
26
27
-static int mv88w8618_wlan_init(SysBusDevice *dev)
28
+static void mv88w8618_wlan_realize(DeviceState *dev, Error **errp)
29
{
30
MemoryRegion *iomem = g_new(MemoryRegion, 1);
31
32
memory_region_init_io(iomem, OBJECT(dev), &mv88w8618_wlan_ops, NULL,
33
"musicpal-wlan", MP_WLAN_SIZE);
34
- sysbus_init_mmio(dev, iomem);
35
- return 0;
36
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), iomem);
37
}
38
39
/* GPIO register offsets */
40
@@ -XXX,XX +XXX,XX @@ DEFINE_MACHINE("musicpal", musicpal_machine_init)
41
42
static void mv88w8618_wlan_class_init(ObjectClass *klass, void *data)
43
{
44
- SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
45
+ DeviceClass *dc = DEVICE_CLASS(klass);
46
47
- sdc->init = mv88w8618_wlan_init;
48
+ dc->realize = mv88w8618_wlan_realize;
49
}
50
51
static const TypeInfo mv88w8618_wlan_info = {
52
--
53
2.19.2
54
55
diff view generated by jsdifflib
[Qemu-devel] [PULL 04/37] block/noenand: Convert sysbus init function to realize function
Deleted patch
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
2
1
3
Use DeviceClass rather than SysBusDeviceClass in
4
onenand_class_init().
5
6
Cc: kwolf@redhat.com
7
Cc: mreitz@redhat.com
8
Cc: qemu-block@nongnu.org
9
10
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
11
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Message-id: 20181130093852.20739-3-maozhongyi@cmss.chinamobile.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/block/onenand.c | 16 +++++++---------
17
1 file changed, 7 insertions(+), 9 deletions(-)
18
19
diff --git a/hw/block/onenand.c b/hw/block/onenand.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/block/onenand.c
22
+++ b/hw/block/onenand.c
23
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps onenand_ops = {
24
.endianness = DEVICE_NATIVE_ENDIAN,
25
};
26
27
-static int onenand_initfn(SysBusDevice *sbd)
28
+static void onenand_realize(DeviceState *dev, Error **errp)
29
{
30
- DeviceState *dev = DEVICE(sbd);
31
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
32
OneNANDState *s = ONE_NAND(dev);
33
uint32_t size = 1 << (24 + ((s->id.dev >> 4) & 7));
34
void *ram;
35
@@ -XXX,XX +XXX,XX @@ static int onenand_initfn(SysBusDevice *sbd)
36
0xff, size + (size >> 5));
37
} else {
38
if (blk_is_read_only(s->blk)) {
39
- error_report("Can't use a read-only drive");
40
- return -1;
41
+ error_setg(errp, "Can't use a read-only drive");
42
+ return;
43
}
44
blk_set_perm(s->blk, BLK_PERM_CONSISTENT_READ | BLK_PERM_WRITE,
45
BLK_PERM_ALL, &local_err);
46
if (local_err) {
47
- error_report_err(local_err);
48
- return -1;
49
+ error_propagate(errp, local_err);
50
+ return;
51
}
52
s->blk_cur = s->blk;
53
}
54
@@ -XXX,XX +XXX,XX @@ static int onenand_initfn(SysBusDevice *sbd)
55
| ((s->id.dev & 0xff) << 8)
56
| (s->id.ver & 0xff),
57
&vmstate_onenand, s);
58
- return 0;
59
}
60
61
static Property onenand_properties[] = {
62
@@ -XXX,XX +XXX,XX @@ static Property onenand_properties[] = {
63
static void onenand_class_init(ObjectClass *klass, void *data)
64
{
65
DeviceClass *dc = DEVICE_CLASS(klass);
66
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
67
68
- k->init = onenand_initfn;
69
+ dc->realize = onenand_realize;
70
dc->reset = onenand_system_reset;
71
dc->props = onenand_properties;
72
}
73
--
74
2.19.2
75
76
diff view generated by jsdifflib
[Qemu-devel] [PULL 05/37] char/grlib_apbuart: Convert sysbus init function to realize function
Deleted patch
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
2
1
3
Use DeviceClass rather than SysBusDeviceClass in
4
grlib_apbuart_class_init().
5
6
Cc: chouteau@adacore.com
7
Cc: marcandre.lureau@redhat.com
8
Cc: pbonzini@redhat.com
9
10
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
11
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
12
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
13
Message-id: 20181130093852.20739-4-maozhongyi@cmss.chinamobile.com
14
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15
---
16
hw/char/grlib_apbuart.c | 12 +++++-------
17
1 file changed, 5 insertions(+), 7 deletions(-)
18
19
diff --git a/hw/char/grlib_apbuart.c b/hw/char/grlib_apbuart.c
20
index XXXXXXX..XXXXXXX 100644
21
--- a/hw/char/grlib_apbuart.c
22
+++ b/hw/char/grlib_apbuart.c
23
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps grlib_apbuart_ops = {
24
.endianness = DEVICE_NATIVE_ENDIAN,
25
};
26
27
-static int grlib_apbuart_init(SysBusDevice *dev)
28
+static void grlib_apbuart_realize(DeviceState *dev, Error **errp)
29
{
30
UART *uart = GRLIB_APB_UART(dev);
31
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
32
33
qemu_chr_fe_set_handlers(&uart->chr,
34
grlib_apbuart_can_receive,
35
@@ -XXX,XX +XXX,XX @@ static int grlib_apbuart_init(SysBusDevice *dev)
36
grlib_apbuart_event,
37
NULL, uart, NULL, true);
38
39
- sysbus_init_irq(dev, &uart->irq);
40
+ sysbus_init_irq(sbd, &uart->irq);
41
42
memory_region_init_io(&uart->iomem, OBJECT(uart), &grlib_apbuart_ops, uart,
43
"uart", UART_REG_SIZE);
44
45
- sysbus_init_mmio(dev, &uart->iomem);
46
-
47
- return 0;
48
+ sysbus_init_mmio(sbd, &uart->iomem);
49
}
50
51
static void grlib_apbuart_reset(DeviceState *d)
52
@@ -XXX,XX +XXX,XX @@ static Property grlib_apbuart_properties[] = {
53
static void grlib_apbuart_class_init(ObjectClass *klass, void *data)
54
{
55
DeviceClass *dc = DEVICE_CLASS(klass);
56
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
57
58
- k->init = grlib_apbuart_init;
59
+ dc->realize = grlib_apbuart_realize;
60
dc->reset = grlib_apbuart_reset;
61
dc->props = grlib_apbuart_properties;
62
}
63
--
64
2.19.2
65
66
diff view generated by jsdifflib
[Qemu-devel] [PULL 07/37] display/g364fb: Convert sysbus init function to realize function
Deleted patch
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
2
1
3
Use DeviceClass rather than SysBusDeviceClass in
4
g364fb_sysbus_class_init().
5
6
Cc: pbonzini@redhat.com
7
Cc: kraxel@redhat.com
8
Cc: f4bug@amsat.org
9
Cc: alistair.francis@wdc.com
10
11
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
12
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
13
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
14
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
15
Message-id: 20181130093852.20739-6-maozhongyi@cmss.chinamobile.com
16
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
17
---
18
hw/display/g364fb.c | 9 +++------
19
1 file changed, 3 insertions(+), 6 deletions(-)
20
21
diff --git a/hw/display/g364fb.c b/hw/display/g364fb.c
22
index XXXXXXX..XXXXXXX 100644
23
--- a/hw/display/g364fb.c
24
+++ b/hw/display/g364fb.c
25
@@ -XXX,XX +XXX,XX @@ typedef struct {
26
G364State g364;
27
} G364SysBusState;
28
29
-static int g364fb_sysbus_init(SysBusDevice *sbd)
30
+static void g364fb_sysbus_realize(DeviceState *dev, Error **errp)
31
{
32
- DeviceState *dev = DEVICE(sbd);
33
G364SysBusState *sbs = G364(dev);
34
G364State *s = &sbs->g364;
35
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
36
37
g364fb_init(dev, s);
38
sysbus_init_irq(sbd, &s->irq);
39
sysbus_init_mmio(sbd, &s->mem_ctrl);
40
sysbus_init_mmio(sbd, &s->mem_vram);
41
-
42
- return 0;
43
}
44
45
static void g364fb_sysbus_reset(DeviceState *d)
46
@@ -XXX,XX +XXX,XX @@ static Property g364fb_sysbus_properties[] = {
47
static void g364fb_sysbus_class_init(ObjectClass *klass, void *data)
48
{
49
DeviceClass *dc = DEVICE_CLASS(klass);
50
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
51
52
- k->init = g364fb_sysbus_init;
53
+ dc->realize = g364fb_sysbus_realize;
54
set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories);
55
dc->desc = "G364 framebuffer";
56
dc->reset = g364fb_sysbus_reset;
57
--
58
2.19.2
59
60
diff view generated by jsdifflib
[Qemu-devel] [PULL 09/37] gpio/puv3_gpio: Convert sysbus init function to realize function
Deleted patch
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
2
1
3
Use DeviceClass rather than SysBusDeviceClass in
4
puv3_gpio_class_init().
5
6
Cc: gxt@mprc.pku.edu.cn
7
Cc: peter.maydell@linaro.org
8
9
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
10
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
11
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
12
Message-id: 20181130093852.20739-8-maozhongyi@cmss.chinamobile.com
13
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14
---
15
hw/gpio/puv3_gpio.c | 29 ++++++++++++++---------------
16
1 file changed, 14 insertions(+), 15 deletions(-)
17
18
diff --git a/hw/gpio/puv3_gpio.c b/hw/gpio/puv3_gpio.c
19
index XXXXXXX..XXXXXXX 100644
20
--- a/hw/gpio/puv3_gpio.c
21
+++ b/hw/gpio/puv3_gpio.c
22
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps puv3_gpio_ops = {
23
.endianness = DEVICE_NATIVE_ENDIAN,
24
};
25
26
-static int puv3_gpio_init(SysBusDevice *dev)
27
+static void puv3_gpio_realize(DeviceState *dev, Error **errp)
28
{
29
PUV3GPIOState *s = PUV3_GPIO(dev);
30
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
31
32
s->reg_GPLR = 0;
33
s->reg_GPDR = 0;
34
35
/* FIXME: these irqs not handled yet */
36
- sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW0]);
37
- sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW1]);
38
- sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW2]);
39
- sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW3]);
40
- sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW4]);
41
- sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW5]);
42
- sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW6]);
43
- sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOLOW7]);
44
- sysbus_init_irq(dev, &s->irq[PUV3_IRQS_GPIOHIGH]);
45
+ sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW0]);
46
+ sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW1]);
47
+ sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW2]);
48
+ sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW3]);
49
+ sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW4]);
50
+ sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW5]);
51
+ sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW6]);
52
+ sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOLOW7]);
53
+ sysbus_init_irq(sbd, &s->irq[PUV3_IRQS_GPIOHIGH]);
54
55
memory_region_init_io(&s->iomem, OBJECT(s), &puv3_gpio_ops, s, "puv3_gpio",
56
PUV3_REGS_OFFSET);
57
- sysbus_init_mmio(dev, &s->iomem);
58
-
59
- return 0;
60
+ sysbus_init_mmio(sbd, &s->iomem);
61
}
62
63
static void puv3_gpio_class_init(ObjectClass *klass, void *data)
64
{
65
- SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
66
+ DeviceClass *dc = DEVICE_CLASS(klass);
67
68
- sdc->init = puv3_gpio_init;
69
+ dc->realize = puv3_gpio_realize;
70
}
71
72
static const TypeInfo puv3_gpio_info = {
73
--
74
2.19.2
75
76
diff view generated by jsdifflib
[Qemu-devel] [PULL 10/37] milkymist-softusb: Convert sysbus init function to realize function
Deleted patch
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
2
1
3
Use DeviceClass rather than SysBusDeviceClass in
4
milkymist_softusb_class_init().
5
6
Cc: michael@walle.cc
7
8
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
9
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Message-id: 20181130093852.20739-9-maozhongyi@cmss.chinamobile.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/input/milkymist-softusb.c | 16 +++++++---------
15
1 file changed, 7 insertions(+), 9 deletions(-)
16
17
diff --git a/hw/input/milkymist-softusb.c b/hw/input/milkymist-softusb.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/input/milkymist-softusb.c
20
+++ b/hw/input/milkymist-softusb.c
21
@@ -XXX,XX +XXX,XX @@ static void milkymist_softusb_reset(DeviceState *d)
22
s->regs[R_CTRL] = CTRL_RESET;
23
}
24
25
-static int milkymist_softusb_init(SysBusDevice *dev)
26
+static void milkymist_softusb_realize(DeviceState *dev, Error **errp)
27
{
28
MilkymistSoftUsbState *s = MILKYMIST_SOFTUSB(dev);
29
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
30
31
- sysbus_init_irq(dev, &s->irq);
32
+ sysbus_init_irq(sbd, &s->irq);
33
34
memory_region_init_io(&s->regs_region, OBJECT(s), &softusb_mmio_ops, s,
35
"milkymist-softusb", R_MAX * 4);
36
- sysbus_init_mmio(dev, &s->regs_region);
37
+ sysbus_init_mmio(sbd, &s->regs_region);
38
39
/* register pmem and dmem */
40
memory_region_init_ram_nomigrate(&s->pmem, OBJECT(s), "milkymist-softusb.pmem",
41
s->pmem_size, &error_fatal);
42
vmstate_register_ram_global(&s->pmem);
43
s->pmem_ptr = memory_region_get_ram_ptr(&s->pmem);
44
- sysbus_init_mmio(dev, &s->pmem);
45
+ sysbus_init_mmio(sbd, &s->pmem);
46
memory_region_init_ram_nomigrate(&s->dmem, OBJECT(s), "milkymist-softusb.dmem",
47
s->dmem_size, &error_fatal);
48
vmstate_register_ram_global(&s->dmem);
49
s->dmem_ptr = memory_region_get_ram_ptr(&s->dmem);
50
- sysbus_init_mmio(dev, &s->dmem);
51
+ sysbus_init_mmio(sbd, &s->dmem);
52
53
hid_init(&s->hid_kbd, HID_KEYBOARD, softusb_kbd_hid_datain);
54
hid_init(&s->hid_mouse, HID_MOUSE, softusb_mouse_hid_datain);
55
-
56
- return 0;
57
}
58
59
static const VMStateDescription vmstate_milkymist_softusb = {
60
@@ -XXX,XX +XXX,XX @@ static Property milkymist_softusb_properties[] = {
61
static void milkymist_softusb_class_init(ObjectClass *klass, void *data)
62
{
63
DeviceClass *dc = DEVICE_CLASS(klass);
64
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
65
66
- k->init = milkymist_softusb_init;
67
+ dc->realize = milkymist_softusb_realize;
68
dc->reset = milkymist_softusb_reset;
69
dc->vmsd = &vmstate_milkymist_softusb;
70
dc->props = milkymist_softusb_properties;
71
--
72
2.19.2
73
74
diff view generated by jsdifflib
[Qemu-devel] [PULL 12/37] intc/puv3_intc: Convert sysbus init function to realize function
Deleted patch
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
2
1
3
Use DeviceClass rather than SysBusDeviceClass in
4
puv3_intc_class_init().
5
6
Cc: gxt@mprc.pku.edu.cn
7
8
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
9
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
10
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
11
Message-id: 20181130093852.20739-11-maozhongyi@cmss.chinamobile.com
12
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
13
---
14
hw/intc/puv3_intc.c | 11 ++++-------
15
1 file changed, 4 insertions(+), 7 deletions(-)
16
17
diff --git a/hw/intc/puv3_intc.c b/hw/intc/puv3_intc.c
18
index XXXXXXX..XXXXXXX 100644
19
--- a/hw/intc/puv3_intc.c
20
+++ b/hw/intc/puv3_intc.c
21
@@ -XXX,XX +XXX,XX @@ static const MemoryRegionOps puv3_intc_ops = {
22
.endianness = DEVICE_NATIVE_ENDIAN,
23
};
24
25
-static int puv3_intc_init(SysBusDevice *sbd)
26
+static void puv3_intc_realize(DeviceState *dev, Error **errp)
27
{
28
- DeviceState *dev = DEVICE(sbd);
29
PUV3INTCState *s = PUV3_INTC(dev);
30
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
31
32
qdev_init_gpio_in(dev, puv3_intc_handler, PUV3_IRQS_NR);
33
sysbus_init_irq(sbd, &s->parent_irq);
34
@@ -XXX,XX +XXX,XX @@ static int puv3_intc_init(SysBusDevice *sbd)
35
memory_region_init_io(&s->iomem, OBJECT(s), &puv3_intc_ops, s, "puv3_intc",
36
PUV3_REGS_OFFSET);
37
sysbus_init_mmio(sbd, &s->iomem);
38
-
39
- return 0;
40
}
41
42
static void puv3_intc_class_init(ObjectClass *klass, void *data)
43
{
44
- SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
45
-
46
- sdc->init = puv3_intc_init;
47
+ DeviceClass *dc = DEVICE_CLASS(klass);
48
+ dc->realize = puv3_intc_realize;
49
}
50
51
static const TypeInfo puv3_intc_info = {
52
--
53
2.19.2
54
55
diff view generated by jsdifflib
[Qemu-devel] [PULL 22/37] xen_backend: remove xen_sysdev_init() function
Deleted patch
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
2
1
3
The init function doesn't do anything at all, so we
4
just omit it.
5
6
Cc: sstabellini@kernel.org
7
Cc: anthony.perard@citrix.com
8
Cc: xen-devel@lists.xenproject.org
9
Cc: peter.maydell@linaro.org
10
11
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
12
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
13
Acked-by: Anthony PERARD <anthony.perard@citrix.com>
14
Message-id: 20181130093852.20739-21-maozhongyi@cmss.chinamobile.com
15
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
16
---
17
hw/xen/xen_backend.c | 7 -------
18
1 file changed, 7 deletions(-)
19
20
diff --git a/hw/xen/xen_backend.c b/hw/xen/xen_backend.c
21
index XXXXXXX..XXXXXXX 100644
22
--- a/hw/xen/xen_backend.c
23
+++ b/hw/xen/xen_backend.c
24
@@ -XXX,XX +XXX,XX @@ static const TypeInfo xensysbus_info = {
25
}
26
};
27
28
-static int xen_sysdev_init(SysBusDevice *dev)
29
-{
30
- return 0;
31
-}
32
-
33
static Property xen_sysdev_properties[] = {
34
{/* end of property list */},
35
};
36
@@ -XXX,XX +XXX,XX @@ static Property xen_sysdev_properties[] = {
37
static void xen_sysdev_class_init(ObjectClass *klass, void *data)
38
{
39
DeviceClass *dc = DEVICE_CLASS(klass);
40
- SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
41
42
- k->init = xen_sysdev_init;
43
dc->props = xen_sysdev_properties;
44
dc->bus_type = TYPE_XENSYSBUS;
45
}
46
--
47
2.19.2
48
49
diff view generated by jsdifflib
[Qemu-devel] [PULL 23/37] core/sysbus: remove the SysBusDeviceClass::init path
[Qemu-devel] [PULL 27/29] target/arm: Use tcg_gen_rotri_i32 for gen_swap_half
1
From: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Currently, all sysbus devices have been converted to realize(),
3
Rotate is the more compact and obvious way to swap 16-bit
4
so remove this path.
4
elements of a 32-bit word.
5
5
6
Cc: ehabkost@redhat.com
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Cc: thuth@redhat.com
7
Message-id: 20190808202616.13782-6-richard.henderson@linaro.org
8
Cc: pbonzini@redhat.com
9
Cc: armbru@redhat.com
10
Cc: peter.maydell@linaro.org
11
Cc: richard.henderson@linaro.org
12
Cc: alistair.francis@wdc.com
13
14
Signed-off-by: Mao Zhongyi <maozhongyi@cmss.chinamobile.com>
15
Signed-off-by: Zhang Shengju <zhangshengju@cmss.chinamobile.com>
16
Message-id: 20181130093852.20739-22-maozhongyi@cmss.chinamobile.com
17
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
18
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
19
---
10
---
20
include/hw/sysbus.h | 3 ---
11
target/arm/translate.c | 6 +-----
21
hw/core/sysbus.c | 15 +++++----------
12
1 file changed, 1 insertion(+), 5 deletions(-)
22
2 files changed, 5 insertions(+), 13 deletions(-)
23
13
24
diff --git a/include/hw/sysbus.h b/include/hw/sysbus.h
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
25
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
26
--- a/include/hw/sysbus.h
16
--- a/target/arm/translate.c
27
+++ b/include/hw/sysbus.h
17
+++ b/target/arm/translate.c
28
@@ -XXX,XX +XXX,XX @@ typedef struct SysBusDevice SysBusDevice;
18
@@ -XXX,XX +XXX,XX @@ static TCGv_i64 gen_muls_i64_i32(TCGv_i32 a, TCGv_i32 b)
29
typedef struct SysBusDeviceClass {
19
/* Swap low and high halfwords. */
30
/*< private >*/
20
static void gen_swap_half(TCGv_i32 var)
31
DeviceClass parent_class;
21
{
32
- /*< public >*/
22
- TCGv_i32 tmp = tcg_temp_new_i32();
33
-
23
- tcg_gen_shri_i32(tmp, var, 16);
34
- int (*init)(SysBusDevice *dev);
24
- tcg_gen_shli_i32(var, var, 16);
35
25
- tcg_gen_or_i32(var, var, tmp);
36
/*
26
- tcg_temp_free_i32(tmp);
37
* Let the sysbus device format its own non-PIO, non-MMIO unit address.
27
+ tcg_gen_rotri_i32(var, var, 16);
38
diff --git a/hw/core/sysbus.c b/hw/core/sysbus.c
39
index XXXXXXX..XXXXXXX 100644
40
--- a/hw/core/sysbus.c
41
+++ b/hw/core/sysbus.c
42
@@ -XXX,XX +XXX,XX @@ void sysbus_init_ioports(SysBusDevice *dev, uint32_t ioport, uint32_t size)
43
}
44
}
28
}
45
29
46
-/* TODO remove once all sysbus devices have been converted to realize */
30
/* Dual 16-bit add. Result placed in t0 and t1 is marked as dead.
47
+/* The purpose of preserving this empty realize function
48
+ * is to prevent the parent_realize field of some subclasses
49
+ * from being set to NULL to break the normal init/realize
50
+ * of some devices.
51
+ */
52
static void sysbus_realize(DeviceState *dev, Error **errp)
53
{
54
- SysBusDevice *sd = SYS_BUS_DEVICE(dev);
55
- SysBusDeviceClass *sbc = SYS_BUS_DEVICE_GET_CLASS(sd);
56
-
57
- if (!sbc->init) {
58
- return;
59
- }
60
- if (sbc->init(sd) < 0) {
61
- error_setg(errp, "Device initialization failed");
62
- }
63
}
64
65
DeviceState *sysbus_create_varargs(const char *name,
66
--
31
--
67
2.19.2
32
2.20.1
68
33
69
34
diff view generated by jsdifflib
[Qemu-devel] [PULL 35/37] target/arm: Introduce arm_hcr_el2_eff
[Qemu-devel] [PULL 28/29] target/arm: Simplify SMMLA, SMMLAR, SMMLS, SMMLSR
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Replace arm_hcr_el2_{fmo,imo,amo} with a more general routine
3
All of the inputs to these instructions are 32-bits. Rather than
4
that also takes SCR_EL3.NS (aka arm_is_secure_below_el3) into
4
extend each input to 64-bits and then extract the high 32-bits of
5
account, as documented for the plethora of bits in HCR_EL2.
5
the output, use tcg_gen_muls2_i32 and other 32-bit generator functions.
6
6
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
7
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
8
Message-id: 20181210150501.7990-2-richard.henderson@linaro.org
8
Message-id: 20190808202616.13782-7-richard.henderson@linaro.org
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
10
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
11
---
11
---
12
target/arm/cpu.h | 67 +++++++++------------------------------
12
target/arm/translate.c | 72 +++++++++++++++---------------------------
13
hw/intc/arm_gicv3_cpuif.c | 21 ++++++------
13
1 file changed, 26 insertions(+), 46 deletions(-)
14
target/arm/helper.c | 66 ++++++++++++++++++++++++++++++++------
15
3 files changed, 83 insertions(+), 71 deletions(-)
16
14
17
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
15
diff --git a/target/arm/translate.c b/target/arm/translate.c
18
index XXXXXXX..XXXXXXX 100644
16
index XXXXXXX..XXXXXXX 100644
19
--- a/target/arm/cpu.h
17
--- a/target/arm/translate.c
20
+++ b/target/arm/cpu.h
18
+++ b/target/arm/translate.c
21
@@ -XXX,XX +XXX,XX @@ static inline bool arm_is_secure(CPUARMState *env)
19
@@ -XXX,XX +XXX,XX @@ static void gen_revsh(TCGv_i32 var)
20
tcg_gen_ext16s_i32(var, var);
22
}
21
}
23
#endif
22
24
23
-/* Return (b << 32) + a. Mark inputs as dead */
25
+/**
24
-static TCGv_i64 gen_addq_msw(TCGv_i64 a, TCGv_i32 b)
26
+ * arm_hcr_el2_eff(): Return the effective value of HCR_EL2.
27
+ * E.g. when in secure state, fields in HCR_EL2 are suppressed,
28
+ * "for all purposes other than a direct read or write access of HCR_EL2."
29
+ * Not included here is HCR_RW.
30
+ */
31
+uint64_t arm_hcr_el2_eff(CPUARMState *env);
32
+
33
/* Return true if the specified exception level is running in AArch64 state. */
34
static inline bool arm_el_is_aa64(CPUARMState *env, int el)
35
{
36
@@ -XXX,XX +XXX,XX @@ bool write_cpustate_to_list(ARMCPU *cpu);
37
# define TARGET_VIRT_ADDR_SPACE_BITS 32
38
#endif
39
40
-/**
41
- * arm_hcr_el2_imo(): Return the effective value of HCR_EL2.IMO.
42
- * Depending on the values of HCR_EL2.E2H and TGE, this may be
43
- * "behaves as 1 for all purposes other than direct read/write" or
44
- * "behaves as 0 for all purposes other than direct read/write"
45
- */
46
-static inline bool arm_hcr_el2_imo(CPUARMState *env)
47
-{
25
-{
48
- switch (env->cp15.hcr_el2 & (HCR_TGE | HCR_E2H)) {
26
- TCGv_i64 tmp64 = tcg_temp_new_i64();
49
- case HCR_TGE:
27
-
50
- return true;
28
- tcg_gen_extu_i32_i64(tmp64, b);
51
- case HCR_TGE | HCR_E2H:
29
- tcg_temp_free_i32(b);
52
- return false;
30
- tcg_gen_shli_i64(tmp64, tmp64, 32);
53
- default:
31
- tcg_gen_add_i64(a, tmp64, a);
54
- return env->cp15.hcr_el2 & HCR_IMO;
32
-
55
- }
33
- tcg_temp_free_i64(tmp64);
34
- return a;
56
-}
35
-}
57
-
36
-
58
-/**
37
-/* Return (b << 32) - a. Mark inputs as dead. */
59
- * arm_hcr_el2_fmo(): Return the effective value of HCR_EL2.FMO.
38
-static TCGv_i64 gen_subq_msw(TCGv_i64 a, TCGv_i32 b)
60
- */
61
-static inline bool arm_hcr_el2_fmo(CPUARMState *env)
62
-{
39
-{
63
- switch (env->cp15.hcr_el2 & (HCR_TGE | HCR_E2H)) {
40
- TCGv_i64 tmp64 = tcg_temp_new_i64();
64
- case HCR_TGE:
41
-
65
- return true;
42
- tcg_gen_extu_i32_i64(tmp64, b);
66
- case HCR_TGE | HCR_E2H:
43
- tcg_temp_free_i32(b);
67
- return false;
44
- tcg_gen_shli_i64(tmp64, tmp64, 32);
68
- default:
45
- tcg_gen_sub_i64(a, tmp64, a);
69
- return env->cp15.hcr_el2 & HCR_FMO;
46
-
70
- }
47
- tcg_temp_free_i64(tmp64);
48
- return a;
71
-}
49
-}
72
-
50
-
73
-/**
51
/* 32x32->64 multiply. Marks inputs as dead. */
74
- * arm_hcr_el2_amo(): Return the effective value of HCR_EL2.AMO.
52
static TCGv_i64 gen_mulu_i64_i32(TCGv_i32 a, TCGv_i32 b)
75
- */
76
-static inline bool arm_hcr_el2_amo(CPUARMState *env)
77
-{
78
- switch (env->cp15.hcr_el2 & (HCR_TGE | HCR_E2H)) {
79
- case HCR_TGE:
80
- return true;
81
- case HCR_TGE | HCR_E2H:
82
- return false;
83
- default:
84
- return env->cp15.hcr_el2 & HCR_AMO;
85
- }
86
-}
87
-
88
static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
89
unsigned int target_el)
90
{
53
{
91
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
54
@@ -XXX,XX +XXX,XX @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
92
bool secure = arm_is_secure(env);
55
(SMMUL, SMMLA, SMMLS) */
93
bool pstate_unmasked;
56
tmp = load_reg(s, rm);
94
int8_t unmasked = 0;
57
tmp2 = load_reg(s, rs);
95
+ uint64_t hcr_el2;
58
- tmp64 = gen_muls_i64_i32(tmp, tmp2);
96
59
+ tcg_gen_muls2_i32(tmp2, tmp, tmp, tmp2);
97
/* Don't take exceptions if they target a lower EL.
60
98
* This check should catch any exceptions that would not be taken but left
61
if (rd != 15) {
99
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
62
- tmp = load_reg(s, rd);
100
return false;
63
+ tmp3 = load_reg(s, rd);
101
}
64
if (insn & (1 << 6)) {
102
65
- tmp64 = gen_subq_msw(tmp64, tmp);
103
+ hcr_el2 = arm_hcr_el2_eff(env);
66
+ tcg_gen_sub_i32(tmp, tmp, tmp3);
104
+
67
} else {
105
switch (excp_idx) {
68
- tmp64 = gen_addq_msw(tmp64, tmp);
106
case EXCP_FIQ:
69
+ tcg_gen_add_i32(tmp, tmp, tmp3);
107
pstate_unmasked = !(env->daif & PSTATE_F);
70
}
108
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
71
+ tcg_temp_free_i32(tmp3);
109
break;
72
}
110
73
if (insn & (1 << 5)) {
111
case EXCP_VFIQ:
74
- tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
112
- if (secure || !arm_hcr_el2_fmo(env) || (env->cp15.hcr_el2 & HCR_TGE)) {
75
+ /*
113
+ if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
76
+ * Adding 0x80000000 to the 64-bit quantity
114
/* VFIQs are only taken when hypervized and non-secure. */
77
+ * means that we have carry in to the high
115
return false;
78
+ * word when the low word has the high bit set.
116
}
79
+ */
117
return !(env->daif & PSTATE_F);
80
+ tcg_gen_shri_i32(tmp2, tmp2, 31);
118
case EXCP_VIRQ:
81
+ tcg_gen_add_i32(tmp, tmp, tmp2);
119
- if (secure || !arm_hcr_el2_imo(env) || (env->cp15.hcr_el2 & HCR_TGE)) {
82
}
120
+ if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
83
- tcg_gen_shri_i64(tmp64, tmp64, 32);
121
/* VIRQs are only taken when hypervized and non-secure. */
84
- tmp = tcg_temp_new_i32();
122
return false;
85
- tcg_gen_extrl_i64_i32(tmp, tmp64);
123
}
86
- tcg_temp_free_i64(tmp64);
124
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
87
+ tcg_temp_free_i32(tmp2);
125
* to the CPSR.F setting otherwise we further assess the state
88
store_reg(s, rn, tmp);
126
* below.
89
break;
127
*/
90
case 0:
128
- hcr = arm_hcr_el2_fmo(env);
91
@@ -XXX,XX +XXX,XX @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
129
+ hcr = hcr_el2 & HCR_FMO;
92
}
130
scr = (env->cp15.scr_el3 & SCR_FIQ);
131
132
/* When EL3 is 32-bit, the SCR.FW bit controls whether the
133
@@ -XXX,XX +XXX,XX @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
134
* when setting the target EL, so it does not have a further
135
* affect here.
136
*/
137
- hcr = arm_hcr_el2_imo(env);
138
+ hcr = hcr_el2 & HCR_IMO;
139
scr = false;
140
break;
93
break;
141
default:
94
case 5: case 6: /* 32 * 32 -> 32msb (SMMUL, SMMLA, SMMLS) */
142
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
95
- tmp64 = gen_muls_i64_i32(tmp, tmp2);
143
index XXXXXXX..XXXXXXX 100644
96
+ tcg_gen_muls2_i32(tmp2, tmp, tmp, tmp2);
144
--- a/hw/intc/arm_gicv3_cpuif.c
97
if (rs != 15) {
145
+++ b/hw/intc/arm_gicv3_cpuif.c
98
- tmp = load_reg(s, rs);
146
@@ -XXX,XX +XXX,XX @@ static bool icv_access(CPUARMState *env, int hcr_flags)
99
+ tmp3 = load_reg(s, rs);
147
* * access if NS EL1 and either IMO or FMO == 1:
100
if (insn & (1 << 20)) {
148
* CTLR, DIR, PMR, RPR
101
- tmp64 = gen_addq_msw(tmp64, tmp);
149
*/
102
+ tcg_gen_add_i32(tmp, tmp, tmp3);
150
- bool flagmatch = ((hcr_flags & HCR_IMO) && arm_hcr_el2_imo(env)) ||
103
} else {
151
- ((hcr_flags & HCR_FMO) && arm_hcr_el2_fmo(env));
104
- tmp64 = gen_subq_msw(tmp64, tmp);
152
+ uint64_t hcr_el2 = arm_hcr_el2_eff(env);
105
+ tcg_gen_sub_i32(tmp, tmp, tmp3);
153
+ bool flagmatch = hcr_el2 & hcr_flags & (HCR_IMO | HCR_FMO);
106
}
154
107
+ tcg_temp_free_i32(tmp3);
155
return flagmatch && arm_current_el(env) == 1
108
}
156
&& !arm_is_secure_below_el3(env);
109
if (insn & (1 << 4)) {
157
@@ -XXX,XX +XXX,XX @@ static void icc_dir_write(CPUARMState *env, const ARMCPRegInfo *ri,
110
- tcg_gen_addi_i64(tmp64, tmp64, 0x80000000u);
158
/* No need to include !IsSecure in route_*_to_el2 as it's only
111
+ /*
159
* tested in cases where we know !IsSecure is true.
112
+ * Adding 0x80000000 to the 64-bit quantity
160
*/
113
+ * means that we have carry in to the high
161
- route_fiq_to_el2 = arm_hcr_el2_fmo(env);
114
+ * word when the low word has the high bit set.
162
- route_irq_to_el2 = arm_hcr_el2_imo(env);
115
+ */
163
+ uint64_t hcr_el2 = arm_hcr_el2_eff(env);
116
+ tcg_gen_shri_i32(tmp2, tmp2, 31);
164
+ route_fiq_to_el2 = hcr_el2 & HCR_FMO;
117
+ tcg_gen_add_i32(tmp, tmp, tmp2);
165
+ route_irq_to_el2 = hcr_el2 & HCR_IMO;
118
}
166
119
- tcg_gen_shri_i64(tmp64, tmp64, 32);
167
switch (arm_current_el(env)) {
120
- tmp = tcg_temp_new_i32();
168
case 3:
121
- tcg_gen_extrl_i64_i32(tmp, tmp64);
169
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gicv3_irqfiq_access(CPUARMState *env,
122
- tcg_temp_free_i64(tmp64);
170
if ((env->cp15.scr_el3 & (SCR_FIQ | SCR_IRQ)) == (SCR_FIQ | SCR_IRQ)) {
123
+ tcg_temp_free_i32(tmp2);
171
switch (el) {
124
break;
172
case 1:
125
case 7: /* Unsigned sum of absolute differences. */
173
- if (arm_is_secure_below_el3(env) ||
126
gen_helper_usad8(tmp, tmp, tmp2);
174
- (arm_hcr_el2_imo(env) == 0 && arm_hcr_el2_fmo(env) == 0)) {
175
+ /* Note that arm_hcr_el2_eff takes secure state into account. */
176
+ if ((arm_hcr_el2_eff(env) & (HCR_IMO | HCR_FMO)) == 0) {
177
r = CP_ACCESS_TRAP_EL3;
178
}
179
break;
180
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gicv3_dir_access(CPUARMState *env,
181
static CPAccessResult gicv3_sgi_access(CPUARMState *env,
182
const ARMCPRegInfo *ri, bool isread)
183
{
184
- if ((arm_hcr_el2_imo(env) || arm_hcr_el2_fmo(env)) &&
185
- arm_current_el(env) == 1 && !arm_is_secure_below_el3(env)) {
186
+ if (arm_current_el(env) == 1 &&
187
+ (arm_hcr_el2_eff(env) & (HCR_IMO | HCR_FMO)) != 0) {
188
/* Takes priority over a possible EL3 trap */
189
return CP_ACCESS_TRAP_EL2;
190
}
191
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gicv3_fiq_access(CPUARMState *env,
192
if (env->cp15.scr_el3 & SCR_FIQ) {
193
switch (el) {
194
case 1:
195
- if (arm_is_secure_below_el3(env) || !arm_hcr_el2_fmo(env)) {
196
+ if ((arm_hcr_el2_eff(env) & HCR_FMO) == 0) {
197
r = CP_ACCESS_TRAP_EL3;
198
}
199
break;
200
@@ -XXX,XX +XXX,XX @@ static CPAccessResult gicv3_irq_access(CPUARMState *env,
201
if (env->cp15.scr_el3 & SCR_IRQ) {
202
switch (el) {
203
case 1:
204
- if (arm_is_secure_below_el3(env) || !arm_hcr_el2_imo(env)) {
205
+ if ((arm_hcr_el2_eff(env) & HCR_IMO) == 0) {
206
r = CP_ACCESS_TRAP_EL3;
207
}
208
break;
209
diff --git a/target/arm/helper.c b/target/arm/helper.c
210
index XXXXXXX..XXXXXXX 100644
211
--- a/target/arm/helper.c
212
+++ b/target/arm/helper.c
213
@@ -XXX,XX +XXX,XX @@ static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
214
static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
215
{
216
CPUState *cs = ENV_GET_CPU(env);
217
+ uint64_t hcr_el2 = arm_hcr_el2_eff(env);
218
uint64_t ret = 0;
219
220
- if (arm_hcr_el2_imo(env)) {
221
+ if (hcr_el2 & HCR_IMO) {
222
if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
223
ret |= CPSR_I;
224
}
225
@@ -XXX,XX +XXX,XX @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
226
}
227
}
228
229
- if (arm_hcr_el2_fmo(env)) {
230
+ if (hcr_el2 & HCR_FMO) {
231
if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) {
232
ret |= CPSR_F;
233
}
234
@@ -XXX,XX +XXX,XX @@ static void hcr_writelow(CPUARMState *env, const ARMCPRegInfo *ri,
235
hcr_write(env, NULL, value);
236
}
237
238
+/*
239
+ * Return the effective value of HCR_EL2.
240
+ * Bits that are not included here:
241
+ * RW (read from SCR_EL3.RW as needed)
242
+ */
243
+uint64_t arm_hcr_el2_eff(CPUARMState *env)
244
+{
245
+ uint64_t ret = env->cp15.hcr_el2;
246
+
247
+ if (arm_is_secure_below_el3(env)) {
248
+ /*
249
+ * "This register has no effect if EL2 is not enabled in the
250
+ * current Security state". This is ARMv8.4-SecEL2 speak for
251
+ * !(SCR_EL3.NS==1 || SCR_EL3.EEL2==1).
252
+ *
253
+ * Prior to that, the language was "In an implementation that
254
+ * includes EL3, when the value of SCR_EL3.NS is 0 the PE behaves
255
+ * as if this field is 0 for all purposes other than a direct
256
+ * read or write access of HCR_EL2". With lots of enumeration
257
+ * on a per-field basis. In current QEMU, this is condition
258
+ * is arm_is_secure_below_el3.
259
+ *
260
+ * Since the v8.4 language applies to the entire register, and
261
+ * appears to be backward compatible, use that.
262
+ */
263
+ ret = 0;
264
+ } else if (ret & HCR_TGE) {
265
+ /* These bits are up-to-date as of ARMv8.4. */
266
+ if (ret & HCR_E2H) {
267
+ ret &= ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO |
268
+ HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE |
269
+ HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU |
270
+ HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE);
271
+ } else {
272
+ ret |= HCR_FMO | HCR_IMO | HCR_AMO;
273
+ }
274
+ ret &= ~(HCR_SWIO | HCR_PTW | HCR_VF | HCR_VI | HCR_VSE |
275
+ HCR_FB | HCR_TID1 | HCR_TID3 | HCR_TSC | HCR_TACR |
276
+ HCR_TSW | HCR_TTLB | HCR_TVM | HCR_HCD | HCR_TRVM |
277
+ HCR_TLOR);
278
+ }
279
+
280
+ return ret;
281
+}
282
+
283
static const ARMCPRegInfo el2_cp_reginfo[] = {
284
{ .name = "HCR_EL2", .state = ARM_CP_STATE_AA64,
285
.type = ARM_CP_IO,
286
@@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
287
uint32_t cur_el, bool secure)
288
{
289
CPUARMState *env = cs->env_ptr;
290
- int rw;
291
- int scr;
292
- int hcr;
293
+ bool rw;
294
+ bool scr;
295
+ bool hcr;
296
int target_el;
297
/* Is the highest EL AArch64? */
298
- int is64 = arm_feature(env, ARM_FEATURE_AARCH64);
299
+ bool is64 = arm_feature(env, ARM_FEATURE_AARCH64);
300
+ uint64_t hcr_el2;
301
302
if (arm_feature(env, ARM_FEATURE_EL3)) {
303
rw = ((env->cp15.scr_el3 & SCR_RW) == SCR_RW);
304
@@ -XXX,XX +XXX,XX @@ uint32_t arm_phys_excp_target_el(CPUState *cs, uint32_t excp_idx,
305
rw = is64;
306
}
307
308
+ hcr_el2 = arm_hcr_el2_eff(env);
309
switch (excp_idx) {
310
case EXCP_IRQ:
311
scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
312
- hcr = arm_hcr_el2_imo(env);
313
+ hcr = hcr_el2 & HCR_IMO;
314
break;
315
case EXCP_FIQ:
316
scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ);
317
- hcr = arm_hcr_el2_fmo(env);
318
+ hcr = hcr_el2 & HCR_FMO;
319
break;
320
default:
321
scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA);
322
- hcr = arm_hcr_el2_amo(env);
323
+ hcr = hcr_el2 & HCR_AMO;
324
break;
325
};
326
327
--
127
--
328
2.19.2
128
2.20.1
329
129
330
130
diff view generated by jsdifflib
[Qemu-devel] [PULL 30/37] target/arm: Add SCR_EL3 bits up to ARMv8.5
[Qemu-devel] [PULL 29/29] target/arm: Use tcg_gen_extrh_i64_i32 to extract the high word
1
From: Richard Henderson <richard.henderson@linaro.org>
1
From: Richard Henderson <richard.henderson@linaro.org>
2
2
3
Post v8.4 bits taken from SysReg_v85_xml-00bet8.
3
Separate shift + extract low will result in one extra insn
4
for hosts like RISC-V, MIPS, and Sparc.
4
5
5
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
6
Message-id: 20181203203839.757-4-richard.henderson@linaro.org
7
Message-id: 20190808202616.13782-8-richard.henderson@linaro.org
7
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
8
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
9
---
10
---
10
target/arm/cpu.h | 10 ++++++++++
11
target/arm/translate.c | 18 ++++++------------
11
1 file changed, 10 insertions(+)
12
1 file changed, 6 insertions(+), 12 deletions(-)
12
13
13
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
14
diff --git a/target/arm/translate.c b/target/arm/translate.c
14
index XXXXXXX..XXXXXXX 100644
15
index XXXXXXX..XXXXXXX 100644
15
--- a/target/arm/cpu.h
16
--- a/target/arm/translate.c
16
+++ b/target/arm/cpu.h
17
+++ b/target/arm/translate.c
17
@@ -XXX,XX +XXX,XX @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
18
@@ -XXX,XX +XXX,XX @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn)
18
#define SCR_ST (1U << 11)
19
if (insn & ARM_CP_RW_BIT) { /* TMRRC */
19
#define SCR_TWI (1U << 12)
20
iwmmxt_load_reg(cpu_V0, wrd);
20
#define SCR_TWE (1U << 13)
21
tcg_gen_extrl_i64_i32(cpu_R[rdlo], cpu_V0);
21
+#define SCR_TLOR (1U << 14)
22
- tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
22
+#define SCR_TERR (1U << 15)
23
- tcg_gen_extrl_i64_i32(cpu_R[rdhi], cpu_V0);
23
+#define SCR_APK (1U << 16)
24
+ tcg_gen_extrh_i64_i32(cpu_R[rdhi], cpu_V0);
24
+#define SCR_API (1U << 17)
25
} else { /* TMCRR */
25
+#define SCR_EEL2 (1U << 18)
26
tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
26
+#define SCR_EASE (1U << 19)
27
iwmmxt_store_reg(cpu_V0, wrd);
27
+#define SCR_NMEA (1U << 20)
28
@@ -XXX,XX +XXX,XX @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn)
28
+#define SCR_FIEN (1U << 21)
29
if (insn & ARM_CP_RW_BIT) { /* MRA */
29
+#define SCR_ENSCXT (1U << 25)
30
iwmmxt_load_reg(cpu_V0, acc);
30
+#define SCR_ATA (1U << 26)
31
tcg_gen_extrl_i64_i32(cpu_R[rdlo], cpu_V0);
31
#define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
32
- tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
32
#define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
33
- tcg_gen_extrl_i64_i32(cpu_R[rdhi], cpu_V0);
34
+ tcg_gen_extrh_i64_i32(cpu_R[rdhi], cpu_V0);
35
tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - 1);
36
} else { /* MAR */
37
tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]);
38
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
39
gen_helper_neon_narrow_high_u16(tmp, cpu_V0);
40
break;
41
case 2:
42
- tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
43
- tcg_gen_extrl_i64_i32(tmp, cpu_V0);
44
+ tcg_gen_extrh_i64_i32(tmp, cpu_V0);
45
break;
46
default: abort();
47
}
48
@@ -XXX,XX +XXX,XX @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
49
break;
50
case 2:
51
tcg_gen_addi_i64(cpu_V0, cpu_V0, 1u << 31);
52
- tcg_gen_shri_i64(cpu_V0, cpu_V0, 32);
53
- tcg_gen_extrl_i64_i32(tmp, cpu_V0);
54
+ tcg_gen_extrh_i64_i32(tmp, cpu_V0);
55
break;
56
default: abort();
57
}
58
@@ -XXX,XX +XXX,XX @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
59
tmp = tcg_temp_new_i32();
60
tcg_gen_extrl_i64_i32(tmp, tmp64);
61
store_reg(s, rt, tmp);
62
- tcg_gen_shri_i64(tmp64, tmp64, 32);
63
tmp = tcg_temp_new_i32();
64
- tcg_gen_extrl_i64_i32(tmp, tmp64);
65
+ tcg_gen_extrh_i64_i32(tmp, tmp64);
66
tcg_temp_free_i64(tmp64);
67
store_reg(s, rt2, tmp);
68
} else {
69
@@ -XXX,XX +XXX,XX @@ static void gen_storeq_reg(DisasContext *s, int rlow, int rhigh, TCGv_i64 val)
70
tcg_gen_extrl_i64_i32(tmp, val);
71
store_reg(s, rlow, tmp);
72
tmp = tcg_temp_new_i32();
73
- tcg_gen_shri_i64(val, val, 32);
74
- tcg_gen_extrl_i64_i32(tmp, val);
75
+ tcg_gen_extrh_i64_i32(tmp, val);
76
store_reg(s, rhigh, tmp);
77
}
33
78
34
--
79
--
35
2.19.2
80
2.20.1
36
81
37
82
diff view generated by jsdifflib

Patchew 2.1-devel-b67e4c2

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