ppc-for-4.0 queue 20181213

[Qemu-devel] [PULL 00/27] ppc-for-4.0 queue 20181213

Posted by David Gibson 5 years, 4 months ago

The following changes since commit 4b3aab204204ca742836219b97b538d90584f4f2:

  Merge remote-tracking branch 'remotes/vivier2/tags/trivial-patches-pull-request' into staging (2018-12-11 22:26:44 +0000)

are available in the Git repository at:

  git://github.com/dgibson/qemu.git tags/ppc-for-4.0-20181213

for you to fetch changes up to 67888a17b6683600ae3fa64ca275c737ba8a9a45:

  spapr/xive: use the VCPU id as a NVT identifier (2018-12-13 09:44:04 +1100)

----------------------------------------------------------------
ppc patch queue 2018-12-13

Here's the first ppc and spapr pull request for 4.0.  Highlights are:

 * The start of support for the POWER9 "XIVE" interrupt controller
   (not complete enough to use yet, but we're getting there)
 * A number of g_new vs. g_malloc cleanups
 * Some IRQ wiring cleanups
 * A fix for how we advertise NUMA nodes to the guest for pseries

----------------------------------------------------------------
Cédric Le Goater (14):
      ppc/xive: introduce a XIVE interrupt source model
      ppc/xive: add support for the LSI interrupt sources
      ppc/xive: introduce the XiveNotifier interface
      ppc/xive: introduce the XiveRouter model
      ppc/xive: introduce the XIVE Event Notification Descriptors
      spapr: initialize VSMT before initializing the IRQ backend
      spapr: introduce a spapr_irq_init() routine
      spapr: export and rename the xics_max_server_number() routine
      ppc/xive: add support for the END Event State Buffers
      ppc/xive: introduce the XIVE interrupt thread context
      ppc/xive: introduce a simplified XIVE presenter
      ppc/xive: notify the CPU when the interrupt priority is more privileged
      spapr/xive: introduce a XIVE interrupt controller
      spapr/xive: use the VCPU id as a NVT identifier

Greg Kurz (10):
      spapr: drop redundant statement in spapr_populate_drconf_memory()
      target/ppc: use g_new(T, n) instead of g_malloc(sizeof(T) * n)
      spapr: use g_new(T, n) instead of g_malloc(sizeof(T) * n)
      ppc405_boards: use g_new(T, n) instead of g_malloc(sizeof(T) * n)
      ppc405_uc: use g_new(T, n) instead of g_malloc(sizeof(T) * n)
      ppc440_bamboo: use g_new(T, n) instead of g_malloc(sizeof(T) * n)
      sam460ex: use g_new(T, n) instead of g_malloc(sizeof(T) * n)
      virtex_ml507: use g_new(T, n) instead of g_malloc(sizeof(T) * n)
      mac_newworld: simplify IRQ wiring
      e500: simplify IRQ wiring

Paul A. Clarke (1):
      Changes requirement for "vsubsbs" instruction

Serhii Popovych (1):
      spapr: Fix ibm,max-associativity-domains property number of nodes

Suraj Jitindar Singh (1):
      target/ppc: tcg: Implement addex instruction

 default-configs/ppc64-softmmu.mak  |    2 +
 disas/ppc.c                        |    2 +
 hw/intc/Makefile.objs              |    2 +
 hw/intc/spapr_xive.c               |  420 ++++++++++
 hw/intc/xive.c                     | 1568 ++++++++++++++++++++++++++++++++++++
 hw/ppc/e500.c                      |   18 +-
 hw/ppc/mac_newworld.c              |   30 +-
 hw/ppc/ppc405_boards.c             |    4 +-
 hw/ppc/ppc405_uc.c                 |    4 +-
 hw/ppc/ppc440_bamboo.c             |    5 +-
 hw/ppc/sam460ex.c                  |    2 +-
 hw/ppc/spapr.c                     |   22 +-
 hw/ppc/spapr_iommu.c               |    2 +-
 hw/ppc/spapr_irq.c                 |   16 +-
 hw/ppc/spapr_vio.c                 |    2 +-
 hw/ppc/virtex_ml507.c              |    2 +-
 include/hw/ppc/openpic.h           |    2 +
 include/hw/ppc/spapr.h             |    1 +
 include/hw/ppc/spapr_irq.h         |    1 +
 include/hw/ppc/spapr_xive.h        |   45 ++
 include/hw/ppc/xive.h              |  428 ++++++++++
 include/hw/ppc/xive_regs.h         |  213 +++++
 target/ppc/translate.c             |   60 +-
 target/ppc/translate/vmx-ops.inc.c |    2 +-
 target/ppc/translate_init.inc.c    |    6 +-
 25 files changed, 2773 insertions(+), 86 deletions(-)
 create mode 100644 hw/intc/spapr_xive.c
 create mode 100644 hw/intc/xive.c
 create mode 100644 include/hw/ppc/spapr_xive.h
 create mode 100644 include/hw/ppc/xive.h
 create mode 100644 include/hw/ppc/xive_regs.h

Re: [Qemu-devel] [PULL 00/27] ppc-for-4.0 queue 20181213

Posted by Peter Maydell 5 years, 4 months ago

On Thu, 13 Dec 2018 at 04:01, David Gibson <david@gibson.dropbear.id.au> wrote:
>
> The following changes since commit 4b3aab204204ca742836219b97b538d90584f4f2:
>
>   Merge remote-tracking branch 'remotes/vivier2/tags/trivial-patches-pull-request' into staging (2018-12-11 22:26:44 +0000)
>
> are available in the Git repository at:
>
>   git://github.com/dgibson/qemu.git tags/ppc-for-4.0-20181213
>
> for you to fetch changes up to 67888a17b6683600ae3fa64ca275c737ba8a9a45:
>
>   spapr/xive: use the VCPU id as a NVT identifier (2018-12-13 09:44:04 +1100)
>
> ----------------------------------------------------------------
> ppc patch queue 2018-12-13
>
> Here's the first ppc and spapr pull request for 4.0.  Highlights are:
>
>  * The start of support for the POWER9 "XIVE" interrupt controller
>    (not complete enough to use yet, but we're getting there)
>  * A number of g_new vs. g_malloc cleanups
>  * Some IRQ wiring cleanups
>  * A fix for how we advertise NUMA nodes to the guest for pseries
>
> ---------------------------------------------------------------


Compile errors in the windows cross-build. These look like
they're assumptions that "long" is 64 bits, which it is not on Windows.
For instance the PPC_BIT macro should be using the ULL suffix, not UL
("UL" is almost always a bug: either the constant is 32-bit, in
which case "U" is what you want, or it's 64-bit and you need "ULL").

Using __builtin_ffsl() directly in target/ppc/cpu.h also looks
a bit dubious -- this should be rephrased to use ctz32() or ctz64()
instead.

In file included from /home/petmay01/qemu-for-merges/hw/intc/xive.c:13:0:
/home/petmay01/qemu-for-merges/hw/intc/xive.c: In function 'xive_router_notify':
/home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
in implicit constant conversion [-Werror=overflow]
 #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
                                 ^
/home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
definition of macro 'MASK_TO_LSH'
 # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
                                                  ^
/home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
note: in expansion of macro 'GETFIELD'
 #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
                                  ^
/home/petmay01/qemu-for-merges/hw/intc/xive.c:1366:28: note: in
expansion of macro 'GETFIELD_BE64'
                            GETFIELD_BE64(EAS_END_BLOCK, eas.w),
                            ^
/home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:120:25:
note: in expansion of macro 'PPC_BITMASK'
 #define EAS_END_BLOCK   PPC_BITMASK(4, 7)        /* Destination END block# */
                         ^
/home/petmay01/qemu-for-merges/hw/intc/xive.c:1366:42: note: in
expansion of macro 'EAS_END_BLOCK'
                            GETFIELD_BE64(EAS_END_BLOCK, eas.w),
                                          ^
/home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
shift count is negative [-Werror=shift-count-negative]
 #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
                                              ^
/home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
note: in expansion of macro 'GETFIELD'
 #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
                                  ^
/home/petmay01/qemu-for-merges/hw/intc/xive.c:1366:28: note: in
expansion of macro 'GETFIELD_BE64'
                            GETFIELD_BE64(EAS_END_BLOCK, eas.w),
                            ^
/home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
in implicit constant conversion [-Werror=overflow]
 #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
                                 ^
/home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
definition of macro 'MASK_TO_LSH'
 # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
                                                  ^
/home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
note: in expansion of macro 'GETFIELD'
 #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
                                  ^
/home/petmay01/qemu-for-merges/hw/intc/xive.c:1367:28: note: in
expansion of macro 'GETFIELD_BE64'
                            GETFIELD_BE64(EAS_END_INDEX, eas.w),
                            ^
/home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:121:25:
note: in expansion of macro 'PPC_BITMASK'
 #define EAS_END_INDEX   PPC_BITMASK(8, 31)       /* Destination END index */
                         ^
/home/petmay01/qemu-for-merges/hw/intc/xive.c:1367:42: note: in
expansion of macro 'EAS_END_INDEX'
                            GETFIELD_BE64(EAS_END_INDEX, eas.w),
                                          ^
/home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
shift count is negative [-Werror=shift-count-negative]
 #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
                                              ^
/home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
note: in expansion of macro 'GETFIELD'
 #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
                                  ^
/home/petmay01/qemu-for-merges/hw/intc/xive.c:1367:28: note: in
expansion of macro 'GETFIELD_BE64'
                            GETFIELD_BE64(EAS_END_INDEX, eas.w),
                            ^
/home/petmay01/qemu-for-merges/hw/intc/xive.c: In function
'xive_eas_pic_print_info':
/home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
in implicit constant conversion [-Werror=overflow]
 #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
                                 ^
/home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
definition of macro 'MASK_TO_LSH'
 # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
                                                  ^
/home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
note: in expansion of macro 'GETFIELD'
 #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
                                  ^
/home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:31: note: in
expansion of macro 'GETFIELD_BE64'
                    (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
                               ^
/home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:120:25:
note: in expansion of macro 'PPC_BITMASK'
 #define EAS_END_BLOCK   PPC_BITMASK(4, 7)        /* Destination END block# */
                         ^
/home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:45: note: in
expansion of macro 'EAS_END_BLOCK'
                    (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
                                             ^
/home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
shift count is negative [-Werror=shift-count-negative]
 #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
                                              ^
/home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
note: in expansion of macro 'GETFIELD'
 #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
                                  ^
/home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:31: note: in
expansion of macro 'GETFIELD_BE64'
                    (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
                               ^
/home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:120:25:
note: in expansion of macro 'PPC_BITMASK'
 #define EAS_END_BLOCK   PPC_BITMASK(4, 7)        /* Destination END block# */
                         ^
/home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:45: note: in
expansion of macro 'EAS_END_BLOCK'
                    (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
                                             ^
/home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
shift count is negative [-Werror=shift-count-negative]
 #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
                                              ^
/home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
note: in expansion of macro 'GETFIELD'
 #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
                                  ^
/home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:31: note: in
expansion of macro 'GETFIELD_BE64'
                    (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
                               ^
/home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
in implicit constant conversion [-Werror=overflow]
 #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
                                 ^
/home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
definition of macro 'MASK_TO_LSH'
 # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
                                                  ^
/home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
note: in expansion of macro 'GETFIELD'
 #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
                                  ^
/home/petmay01/qemu-for-merges/hw/intc/xive.c:1401:31: note: in
expansion of macro 'GETFIELD_BE64'
                    (uint32_t) GETFIELD_BE64(EAS_END_INDEX, eas->w),
                               ^
/home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:121:25:
note: in expansion of macro 'PPC_BITMASK'
 #define EAS_END_INDEX   PPC_BITMASK(8, 31)       /* Destination END index */
                         ^
/home/petmay01/qemu-for-merges/hw/intc/xive.c:1401:45: note: in
expansion of macro 'EAS_END_INDEX'
                    (uint32_t) GETFIELD_BE64(EAS_END_INDEX, eas->w),
                                             ^
/home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
shift count is negative [-Werror=shift-count-negative]
 #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
                                              ^
/home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
note: in expansion of macro 'GETFIELD'
 #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
                                  ^
/home/petmay01/qemu-for-merges/hw/intc/xive.c:1401:31: note: in
expansion of macro 'GETFIELD_BE64'
                    (uint32_t) GETFIELD_BE64(EAS_END_INDEX, eas->w),
                               ^


thanks
-- PMM

Re: [Qemu-devel] [PULL 00/27] ppc-for-4.0 queue 20181213

Posted by Cédric Le Goater 5 years, 4 months ago

On 12/14/18 5:03 PM, Peter Maydell wrote:
> On Thu, 13 Dec 2018 at 04:01, David Gibson <david@gibson.dropbear.id.au> wrote:
>>
>> The following changes since commit 4b3aab204204ca742836219b97b538d90584f4f2:
>>
>>   Merge remote-tracking branch 'remotes/vivier2/tags/trivial-patches-pull-request' into staging (2018-12-11 22:26:44 +0000)
>>
>> are available in the Git repository at:
>>
>>   git://github.com/dgibson/qemu.git tags/ppc-for-4.0-20181213
>>
>> for you to fetch changes up to 67888a17b6683600ae3fa64ca275c737ba8a9a45:
>>
>>   spapr/xive: use the VCPU id as a NVT identifier (2018-12-13 09:44:04 +1100)
>>
>> ----------------------------------------------------------------
>> ppc patch queue 2018-12-13
>>
>> Here's the first ppc and spapr pull request for 4.0.  Highlights are:
>>
>>  * The start of support for the POWER9 "XIVE" interrupt controller
>>    (not complete enough to use yet, but we're getting there)
>>  * A number of g_new vs. g_malloc cleanups
>>  * Some IRQ wiring cleanups
>>  * A fix for how we advertise NUMA nodes to the guest for pseries
>>
>> ---------------------------------------------------------------
> 
> 
> Compile errors in the windows cross-build. 

are you compiling with the mingw64-* packages ? as documented in :

	https://wiki.qemu.org/Hosts/W32

> These look like
> they're assumptions that "long" is 64 bits, which it is not on Windows.
> For instance the PPC_BIT macro should be using the ULL suffix, not UL
> ("UL" is almost always a bug: either the constant is 32-bit, in
> which case "U" is what you want, or it's 64-bit and you need "ULL").

ok. These definitions come from our skiboot firmware which I wanted 
to keep as it was. It seems I will need to adapt.

> Using __builtin_ffsl() directly in target/ppc/cpu.h also looks
> a bit dubious -- this should be rephrased to use ctz32() or ctz64()
> instead.

ok. I will work on a fix.

Thanks,

C.


> In file included from /home/petmay01/qemu-for-merges/hw/intc/xive.c:13:0:
> /home/petmay01/qemu-for-merges/hw/intc/xive.c: In function 'xive_router_notify':
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
> in implicit constant conversion [-Werror=overflow]
>  #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
>                                  ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
> definition of macro 'MASK_TO_LSH'
>  # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
>                                                   ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> note: in expansion of macro 'GETFIELD'
>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>                                   ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1366:28: note: in
> expansion of macro 'GETFIELD_BE64'
>                             GETFIELD_BE64(EAS_END_BLOCK, eas.w),
>                             ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:120:25:
> note: in expansion of macro 'PPC_BITMASK'
>  #define EAS_END_BLOCK   PPC_BITMASK(4, 7)        /* Destination END block# */
>                          ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1366:42: note: in
> expansion of macro 'EAS_END_BLOCK'
>                             GETFIELD_BE64(EAS_END_BLOCK, eas.w),
>                                           ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
> shift count is negative [-Werror=shift-count-negative]
>  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
>                                               ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> note: in expansion of macro 'GETFIELD'
>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>                                   ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1366:28: note: in
> expansion of macro 'GETFIELD_BE64'
>                             GETFIELD_BE64(EAS_END_BLOCK, eas.w),
>                             ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
> in implicit constant conversion [-Werror=overflow]
>  #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
>                                  ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
> definition of macro 'MASK_TO_LSH'
>  # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
>                                                   ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> note: in expansion of macro 'GETFIELD'
>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>                                   ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1367:28: note: in
> expansion of macro 'GETFIELD_BE64'
>                             GETFIELD_BE64(EAS_END_INDEX, eas.w),
>                             ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:121:25:
> note: in expansion of macro 'PPC_BITMASK'
>  #define EAS_END_INDEX   PPC_BITMASK(8, 31)       /* Destination END index */
>                          ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1367:42: note: in
> expansion of macro 'EAS_END_INDEX'
>                             GETFIELD_BE64(EAS_END_INDEX, eas.w),
>                                           ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
> shift count is negative [-Werror=shift-count-negative]
>  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
>                                               ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> note: in expansion of macro 'GETFIELD'
>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>                                   ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1367:28: note: in
> expansion of macro 'GETFIELD_BE64'
>                             GETFIELD_BE64(EAS_END_INDEX, eas.w),
>                             ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c: In function
> 'xive_eas_pic_print_info':
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
> in implicit constant conversion [-Werror=overflow]
>  #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
>                                  ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
> definition of macro 'MASK_TO_LSH'
>  # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
>                                                   ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> note: in expansion of macro 'GETFIELD'
>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>                                   ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:31: note: in
> expansion of macro 'GETFIELD_BE64'
>                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
>                                ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:120:25:
> note: in expansion of macro 'PPC_BITMASK'
>  #define EAS_END_BLOCK   PPC_BITMASK(4, 7)        /* Destination END block# */
>                          ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:45: note: in
> expansion of macro 'EAS_END_BLOCK'
>                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
>                                              ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
> shift count is negative [-Werror=shift-count-negative]
>  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
>                                               ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> note: in expansion of macro 'GETFIELD'
>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>                                   ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:31: note: in
> expansion of macro 'GETFIELD_BE64'
>                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
>                                ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:120:25:
> note: in expansion of macro 'PPC_BITMASK'
>  #define EAS_END_BLOCK   PPC_BITMASK(4, 7)        /* Destination END block# */
>                          ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:45: note: in
> expansion of macro 'EAS_END_BLOCK'
>                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
>                                              ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
> shift count is negative [-Werror=shift-count-negative]
>  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
>                                               ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> note: in expansion of macro 'GETFIELD'
>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>                                   ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:31: note: in
> expansion of macro 'GETFIELD_BE64'
>                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
>                                ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
> in implicit constant conversion [-Werror=overflow]
>  #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
>                                  ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
> definition of macro 'MASK_TO_LSH'
>  # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
>                                                   ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> note: in expansion of macro 'GETFIELD'
>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>                                   ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1401:31: note: in
> expansion of macro 'GETFIELD_BE64'
>                     (uint32_t) GETFIELD_BE64(EAS_END_INDEX, eas->w),
>                                ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:121:25:
> note: in expansion of macro 'PPC_BITMASK'
>  #define EAS_END_INDEX   PPC_BITMASK(8, 31)       /* Destination END index */
>                          ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1401:45: note: in
> expansion of macro 'EAS_END_INDEX'
>                     (uint32_t) GETFIELD_BE64(EAS_END_INDEX, eas->w),
>                                              ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
> shift count is negative [-Werror=shift-count-negative]
>  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
>                                               ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> note: in expansion of macro 'GETFIELD'
>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>                                   ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1401:31: note: in
> expansion of macro 'GETFIELD_BE64'
>                     (uint32_t) GETFIELD_BE64(EAS_END_INDEX, eas->w),
>                                ^
> 
> 
> thanks
> -- PMM
>

Re: [Qemu-devel] [PULL 00/27] ppc-for-4.0 queue 20181213

Posted by David Gibson 5 years, 4 months ago

On Fri, Dec 14, 2018 at 06:49:55PM +0100, Cédric Le Goater wrote:
> On 12/14/18 5:03 PM, Peter Maydell wrote:
> > On Thu, 13 Dec 2018 at 04:01, David Gibson <david@gibson.dropbear.id.au> wrote:
> >>
> >> The following changes since commit 4b3aab204204ca742836219b97b538d90584f4f2:
> >>
> >>   Merge remote-tracking branch 'remotes/vivier2/tags/trivial-patches-pull-request' into staging (2018-12-11 22:26:44 +0000)
> >>
> >> are available in the Git repository at:
> >>
> >>   git://github.com/dgibson/qemu.git tags/ppc-for-4.0-20181213
> >>
> >> for you to fetch changes up to 67888a17b6683600ae3fa64ca275c737ba8a9a45:
> >>
> >>   spapr/xive: use the VCPU id as a NVT identifier (2018-12-13 09:44:04 +1100)
> >>
> >> ----------------------------------------------------------------
> >> ppc patch queue 2018-12-13
> >>
> >> Here's the first ppc and spapr pull request for 4.0.  Highlights are:
> >>
> >>  * The start of support for the POWER9 "XIVE" interrupt controller
> >>    (not complete enough to use yet, but we're getting there)
> >>  * A number of g_new vs. g_malloc cleanups
> >>  * Some IRQ wiring cleanups
> >>  * A fix for how we advertise NUMA nodes to the guest for pseries
> >>
> >> ---------------------------------------------------------------
> > 
> > 
> > Compile errors in the windows cross-build. 
> 
> are you compiling with the mingw64-* packages ? as documented in :
> 
> 	https://wiki.qemu.org/Hosts/W32
> 
> > These look like
> > they're assumptions that "long" is 64 bits, which it is not on Windows.
> > For instance the PPC_BIT macro should be using the ULL suffix, not UL
> > ("UL" is almost always a bug: either the constant is 32-bit, in
> > which case "U" is what you want, or it's 64-bit and you need "ULL").
> 
> ok. These definitions come from our skiboot firmware which I wanted 
> to keep as it was. It seems I will need to adapt.
> 
> > Using __builtin_ffsl() directly in target/ppc/cpu.h also looks
> > a bit dubious -- this should be rephrased to use ctz32() or ctz64()
> > instead.
> 
> ok. I will work on a fix.

So, I tried to confirm the problem, before applying Cédric's fix, but
I don't seem to be able to.  I'm getting a bunch of failures in the
windows cross-build on master, which look like gcc8 problems - but
nothing new or different in my tree.

$ ./configure --cross-prefix=i686-w64-mingw32-

[...]

$ make -k

	CHK version_gen.h
  CC      block/sheepdog.o
block/sheepdog.c: In function 'find_vdi_name':
block/sheepdog.c:1239:5: error: 'strncpy' specified bound 256 equals destination size [-Werror=stringop-truncation]
     strncpy(buf + SD_MAX_VDI_LEN, tag, SD_MAX_VDI_TAG_LEN);
     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
make: *** [/home/dwg/src/qemu/rules.mak:69: block/sheepdog.o] Error 1
  CC      hw/acpi/core.o
In function 'acpi_table_install',
    inlined from 'acpi_table_add' at hw/acpi/core.c:296:5:
hw/acpi/core.c:184:9: error: 'strncpy' specified bound 4 equals destination size [-Werror=stringop-truncation]
         strncpy(ext_hdr->sig, hdrs->sig, sizeof ext_hdr->sig);
         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
hw/acpi/core.c:203:9: error: 'strncpy' specified bound 6 equals destination size [-Werror=stringop-truncation]
         strncpy(ext_hdr->oem_id, hdrs->oem_id, sizeof ext_hdr->oem_id);
         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
hw/acpi/core.c:207:9: error: 'strncpy' specified bound 8 equals destination size [-Werror=stringop-truncation]
         strncpy(ext_hdr->oem_table_id, hdrs->oem_table_id,
         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                 sizeof ext_hdr->oem_table_id);
                 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
hw/acpi/core.c:216:9: error: 'strncpy' specified bound 4 equals destination size [-Werror=stringop-truncation]
         strncpy(ext_hdr->asl_compiler_id, hdrs->asl_compiler_id,
         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                 sizeof ext_hdr->asl_compiler_id);
                 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
make: *** [/home/dwg/src/qemu/rules.mak:69: hw/acpi/core.o] Error 1
  CC      hw/acpi/aml-build.o
hw/acpi/aml-build.c: In function 'build_header':
hw/acpi/aml-build.c:1535:9: error: 'strncpy' specified bound 6 equals destination size [-Werror=stringop-truncation]
         strncpy((char *)h->oem_id, oem_id, sizeof h->oem_id);
         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
hw/acpi/aml-build.c:1541:9: error: 'strncpy' specified bound 8 equals destination size [-Werror=stringop-truncation]
         strncpy((char *)h->oem_table_id, oem_table_id, sizeof(h->oem_table_id));
         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
make: *** [/home/dwg/src/qemu/rules.mak:69: hw/acpi/aml-build.o] Error 1
  CC      migration/global_state.o
migration/global_state.c: In function 'global_state_store_running':
migration/global_state.c:45:5: error: 'strncpy' specified bound 100 equals destination size [-Werror=stringop-truncation]
     strncpy((char *)global_state.runstate,
     ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
            state, sizeof(global_state.runstate));
            ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
cc1: all warnings being treated as errors
make: *** [/home/dwg/src/qemu/rules.mak:69: migration/global_state.o] Error 1
make: Target 'all' not remade because of errors.


> 
> Thanks,
> 
> C.
> 
> 
> > In file included from /home/petmay01/qemu-for-merges/hw/intc/xive.c:13:0:
> > /home/petmay01/qemu-for-merges/hw/intc/xive.c: In function 'xive_router_notify':
> > /home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
> > in implicit constant conversion [-Werror=overflow]
> >  #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
> >                                  ^
> > /home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
> > definition of macro 'MASK_TO_LSH'
> >  # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
> >                                                   ^
> > /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> > note: in expansion of macro 'GETFIELD'
> >  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
> >                                   ^
> > /home/petmay01/qemu-for-merges/hw/intc/xive.c:1366:28: note: in
> > expansion of macro 'GETFIELD_BE64'
> >                             GETFIELD_BE64(EAS_END_BLOCK, eas.w),
> >                             ^
> > /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:120:25:
> > note: in expansion of macro 'PPC_BITMASK'
> >  #define EAS_END_BLOCK   PPC_BITMASK(4, 7)        /* Destination END block# */
> >                          ^
> > /home/petmay01/qemu-for-merges/hw/intc/xive.c:1366:42: note: in
> > expansion of macro 'EAS_END_BLOCK'
> >                             GETFIELD_BE64(EAS_END_BLOCK, eas.w),
> >                                           ^
> > /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
> > shift count is negative [-Werror=shift-count-negative]
> >  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
> >                                               ^
> > /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> > note: in expansion of macro 'GETFIELD'
> >  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
> >                                   ^
> > /home/petmay01/qemu-for-merges/hw/intc/xive.c:1366:28: note: in
> > expansion of macro 'GETFIELD_BE64'
> >                             GETFIELD_BE64(EAS_END_BLOCK, eas.w),
> >                             ^
> > /home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
> > in implicit constant conversion [-Werror=overflow]
> >  #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
> >                                  ^
> > /home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
> > definition of macro 'MASK_TO_LSH'
> >  # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
> >                                                   ^
> > /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> > note: in expansion of macro 'GETFIELD'
> >  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
> >                                   ^
> > /home/petmay01/qemu-for-merges/hw/intc/xive.c:1367:28: note: in
> > expansion of macro 'GETFIELD_BE64'
> >                             GETFIELD_BE64(EAS_END_INDEX, eas.w),
> >                             ^
> > /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:121:25:
> > note: in expansion of macro 'PPC_BITMASK'
> >  #define EAS_END_INDEX   PPC_BITMASK(8, 31)       /* Destination END index */
> >                          ^
> > /home/petmay01/qemu-for-merges/hw/intc/xive.c:1367:42: note: in
> > expansion of macro 'EAS_END_INDEX'
> >                             GETFIELD_BE64(EAS_END_INDEX, eas.w),
> >                                           ^
> > /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
> > shift count is negative [-Werror=shift-count-negative]
> >  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
> >                                               ^
> > /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> > note: in expansion of macro 'GETFIELD'
> >  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
> >                                   ^
> > /home/petmay01/qemu-for-merges/hw/intc/xive.c:1367:28: note: in
> > expansion of macro 'GETFIELD_BE64'
> >                             GETFIELD_BE64(EAS_END_INDEX, eas.w),
> >                             ^
> > /home/petmay01/qemu-for-merges/hw/intc/xive.c: In function
> > 'xive_eas_pic_print_info':
> > /home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
> > in implicit constant conversion [-Werror=overflow]
> >  #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
> >                                  ^
> > /home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
> > definition of macro 'MASK_TO_LSH'
> >  # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
> >                                                   ^
> > /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> > note: in expansion of macro 'GETFIELD'
> >  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
> >                                   ^
> > /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:31: note: in
> > expansion of macro 'GETFIELD_BE64'
> >                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
> >                                ^
> > /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:120:25:
> > note: in expansion of macro 'PPC_BITMASK'
> >  #define EAS_END_BLOCK   PPC_BITMASK(4, 7)        /* Destination END block# */
> >                          ^
> > /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:45: note: in
> > expansion of macro 'EAS_END_BLOCK'
> >                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
> >                                              ^
> > /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
> > shift count is negative [-Werror=shift-count-negative]
> >  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
> >                                               ^
> > /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> > note: in expansion of macro 'GETFIELD'
> >  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
> >                                   ^
> > /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:31: note: in
> > expansion of macro 'GETFIELD_BE64'
> >                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
> >                                ^
> > /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:120:25:
> > note: in expansion of macro 'PPC_BITMASK'
> >  #define EAS_END_BLOCK   PPC_BITMASK(4, 7)        /* Destination END block# */
> >                          ^
> > /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:45: note: in
> > expansion of macro 'EAS_END_BLOCK'
> >                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
> >                                              ^
> > /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
> > shift count is negative [-Werror=shift-count-negative]
> >  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
> >                                               ^
> > /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> > note: in expansion of macro 'GETFIELD'
> >  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
> >                                   ^
> > /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:31: note: in
> > expansion of macro 'GETFIELD_BE64'
> >                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
> >                                ^
> > /home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
> > in implicit constant conversion [-Werror=overflow]
> >  #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
> >                                  ^
> > /home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
> > definition of macro 'MASK_TO_LSH'
> >  # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
> >                                                   ^
> > /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> > note: in expansion of macro 'GETFIELD'
> >  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
> >                                   ^
> > /home/petmay01/qemu-for-merges/hw/intc/xive.c:1401:31: note: in
> > expansion of macro 'GETFIELD_BE64'
> >                     (uint32_t) GETFIELD_BE64(EAS_END_INDEX, eas->w),
> >                                ^
> > /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:121:25:
> > note: in expansion of macro 'PPC_BITMASK'
> >  #define EAS_END_INDEX   PPC_BITMASK(8, 31)       /* Destination END index */
> >                          ^
> > /home/petmay01/qemu-for-merges/hw/intc/xive.c:1401:45: note: in
> > expansion of macro 'EAS_END_INDEX'
> >                     (uint32_t) GETFIELD_BE64(EAS_END_INDEX, eas->w),
> >                                              ^
> > /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
> > shift count is negative [-Werror=shift-count-negative]
> >  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
> >                                               ^
> > /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> > note: in expansion of macro 'GETFIELD'
> >  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
> >                                   ^
> > /home/petmay01/qemu-for-merges/hw/intc/xive.c:1401:31: note: in
> > expansion of macro 'GETFIELD_BE64'
> >                     (uint32_t) GETFIELD_BE64(EAS_END_INDEX, eas->w),
> >                                ^
> > 
> > 
> > thanks
> > -- PMM
> > 
> 

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

Re: [Qemu-devel] [Qemu-ppc] [PULL 00/27] ppc-for-4.0 queue 20181213

Posted by Howard Spoelstra 5 years, 4 months ago

On Mon, Dec 17, 2018 at 4:31 AM David Gibson
<david@gibson.dropbear.id.au> wrote:
>
> On Fri, Dec 14, 2018 at 06:49:55PM +0100, Cédric Le Goater wrote:
> > On 12/14/18 5:03 PM, Peter Maydell wrote:
> > > On Thu, 13 Dec 2018 at 04:01, David Gibson <david@gibson.dropbear.id.au> wrote:
> > >>
> > >> The following changes since commit 4b3aab204204ca742836219b97b538d90584f4f2:
> > >>
> > >>   Merge remote-tracking branch 'remotes/vivier2/tags/trivial-patches-pull-request' into staging (2018-12-11 22:26:44 +0000)
> > >>
> > >> are available in the Git repository at:
> > >>
> > >>   git://github.com/dgibson/qemu.git tags/ppc-for-4.0-20181213
> > >>
> > >> for you to fetch changes up to 67888a17b6683600ae3fa64ca275c737ba8a9a45:
> > >>
> > >>   spapr/xive: use the VCPU id as a NVT identifier (2018-12-13 09:44:04 +1100)
> > >>
> > >> ----------------------------------------------------------------
> > >> ppc patch queue 2018-12-13
> > >>
> > >> Here's the first ppc and spapr pull request for 4.0.  Highlights are:
> > >>
> > >>  * The start of support for the POWER9 "XIVE" interrupt controller
> > >>    (not complete enough to use yet, but we're getting there)
> > >>  * A number of g_new vs. g_malloc cleanups
> > >>  * Some IRQ wiring cleanups
> > >>  * A fix for how we advertise NUMA nodes to the guest for pseries
> > >>
> > >> ---------------------------------------------------------------
> > >
> > >
> > > Compile errors in the windows cross-build.
> >
> > are you compiling with the mingw64-* packages ? as documented in :
> >
> >       https://wiki.qemu.org/Hosts/W32
> >
> > > These look like
> > > they're assumptions that "long" is 64 bits, which it is not on Windows.
> > > For instance the PPC_BIT macro should be using the ULL suffix, not UL
> > > ("UL" is almost always a bug: either the constant is 32-bit, in
> > > which case "U" is what you want, or it's 64-bit and you need "ULL").
> >
> > ok. These definitions come from our skiboot firmware which I wanted
> > to keep as it was. It seems I will need to adapt.
> >
> > > Using __builtin_ffsl() directly in target/ppc/cpu.h also looks
> > > a bit dubious -- this should be rephrased to use ctz32() or ctz64()
> > > instead.
> >
> > ok. I will work on a fix.
>
> So, I tried to confirm the problem, before applying Cédric's fix, but
> I don't seem to be able to.  I'm getting a bunch of failures in the
> windows cross-build on master, which look like gcc8 problems - but
> nothing new or different in my tree.
>
> $ ./configure --cross-prefix=i686-w64-mingw32-
>
> [...]
>
> $ make -k
>
>         CHK version_gen.h
>   CC      block/sheepdog.o
> block/sheepdog.c: In function 'find_vdi_name':
> block/sheepdog.c:1239:5: error: 'strncpy' specified bound 256 equals destination size [-Werror=stringop-truncation]
>      strncpy(buf + SD_MAX_VDI_LEN, tag, SD_MAX_VDI_TAG_LEN);
>      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> cc1: all warnings being treated as errors
> make: *** [/home/dwg/src/qemu/rules.mak:69: block/sheepdog.o] Error 1
>   CC      hw/acpi/core.o
> In function 'acpi_table_install',
>     inlined from 'acpi_table_add' at hw/acpi/core.c:296:5:
> hw/acpi/core.c:184:9: error: 'strncpy' specified bound 4 equals destination size [-Werror=stringop-truncation]
>          strncpy(ext_hdr->sig, hdrs->sig, sizeof ext_hdr->sig);
>          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> hw/acpi/core.c:203:9: error: 'strncpy' specified bound 6 equals destination size [-Werror=stringop-truncation]
>          strncpy(ext_hdr->oem_id, hdrs->oem_id, sizeof ext_hdr->oem_id);
>          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> hw/acpi/core.c:207:9: error: 'strncpy' specified bound 8 equals destination size [-Werror=stringop-truncation]
>          strncpy(ext_hdr->oem_table_id, hdrs->oem_table_id,
>          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>                  sizeof ext_hdr->oem_table_id);
>                  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> hw/acpi/core.c:216:9: error: 'strncpy' specified bound 4 equals destination size [-Werror=stringop-truncation]
>          strncpy(ext_hdr->asl_compiler_id, hdrs->asl_compiler_id,
>          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>                  sizeof ext_hdr->asl_compiler_id);
>                  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> cc1: all warnings being treated as errors
> make: *** [/home/dwg/src/qemu/rules.mak:69: hw/acpi/core.o] Error 1
>   CC      hw/acpi/aml-build.o
> hw/acpi/aml-build.c: In function 'build_header':
> hw/acpi/aml-build.c:1535:9: error: 'strncpy' specified bound 6 equals destination size [-Werror=stringop-truncation]
>          strncpy((char *)h->oem_id, oem_id, sizeof h->oem_id);
>          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> hw/acpi/aml-build.c:1541:9: error: 'strncpy' specified bound 8 equals destination size [-Werror=stringop-truncation]
>          strncpy((char *)h->oem_table_id, oem_table_id, sizeof(h->oem_table_id));
>          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> cc1: all warnings being treated as errors
> make: *** [/home/dwg/src/qemu/rules.mak:69: hw/acpi/aml-build.o] Error 1
>   CC      migration/global_state.o
> migration/global_state.c: In function 'global_state_store_running':
> migration/global_state.c:45:5: error: 'strncpy' specified bound 100 equals destination size [-Werror=stringop-truncation]
>      strncpy((char *)global_state.runstate,
>      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>             state, sizeof(global_state.runstate));
>             ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> cc1: all warnings being treated as errors
> make: *** [/home/dwg/src/qemu/rules.mak:69: migration/global_state.o] Error 1
> make: Target 'all' not remade because of errors.
>
>
> >
> > Thanks,
> >
> > C.
> >
> >
> > > In file included from /home/petmay01/qemu-for-merges/hw/intc/xive.c:13:0:
> > > /home/petmay01/qemu-for-merges/hw/intc/xive.c: In function 'xive_router_notify':
> > > /home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
> > > in implicit constant conversion [-Werror=overflow]
> > >  #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
> > >                                  ^
> > > /home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
> > > definition of macro 'MASK_TO_LSH'
> > >  # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
> > >                                                   ^
> > > /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> > > note: in expansion of macro 'GETFIELD'
> > >  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
> > >                                   ^
> > > /home/petmay01/qemu-for-merges/hw/intc/xive.c:1366:28: note: in
> > > expansion of macro 'GETFIELD_BE64'
> > >                             GETFIELD_BE64(EAS_END_BLOCK, eas.w),
> > >                             ^
> > > /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:120:25:
> > > note: in expansion of macro 'PPC_BITMASK'
> > >  #define EAS_END_BLOCK   PPC_BITMASK(4, 7)        /* Destination END block# */
> > >                          ^
> > > /home/petmay01/qemu-for-merges/hw/intc/xive.c:1366:42: note: in
> > > expansion of macro 'EAS_END_BLOCK'
> > >                             GETFIELD_BE64(EAS_END_BLOCK, eas.w),
> > >                                           ^
> > > /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
> > > shift count is negative [-Werror=shift-count-negative]
> > >  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
> > >                                               ^
> > > /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> > > note: in expansion of macro 'GETFIELD'
> > >  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
> > >                                   ^
> > > /home/petmay01/qemu-for-merges/hw/intc/xive.c:1366:28: note: in
> > > expansion of macro 'GETFIELD_BE64'
> > >                             GETFIELD_BE64(EAS_END_BLOCK, eas.w),
> > >                             ^
> > > /home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
> > > in implicit constant conversion [-Werror=overflow]
> > >  #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
> > >                                  ^
> > > /home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
> > > definition of macro 'MASK_TO_LSH'
> > >  # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
> > >                                                   ^
> > > /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> > > note: in expansion of macro 'GETFIELD'
> > >  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
> > >                                   ^
> > > /home/petmay01/qemu-for-merges/hw/intc/xive.c:1367:28: note: in
> > > expansion of macro 'GETFIELD_BE64'
> > >                             GETFIELD_BE64(EAS_END_INDEX, eas.w),
> > >                             ^
> > > /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:121:25:
> > > note: in expansion of macro 'PPC_BITMASK'
> > >  #define EAS_END_INDEX   PPC_BITMASK(8, 31)       /* Destination END index */
> > >                          ^
> > > /home/petmay01/qemu-for-merges/hw/intc/xive.c:1367:42: note: in
> > > expansion of macro 'EAS_END_INDEX'
> > >                             GETFIELD_BE64(EAS_END_INDEX, eas.w),
> > >                                           ^
> > > /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
> > > shift count is negative [-Werror=shift-count-negative]
> > >  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
> > >                                               ^
> > > /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> > > note: in expansion of macro 'GETFIELD'
> > >  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
> > >                                   ^
> > > /home/petmay01/qemu-for-merges/hw/intc/xive.c:1367:28: note: in
> > > expansion of macro 'GETFIELD_BE64'
> > >                             GETFIELD_BE64(EAS_END_INDEX, eas.w),
> > >                             ^
> > > /home/petmay01/qemu-for-merges/hw/intc/xive.c: In function
> > > 'xive_eas_pic_print_info':
> > > /home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
> > > in implicit constant conversion [-Werror=overflow]
> > >  #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
> > >                                  ^
> > > /home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
> > > definition of macro 'MASK_TO_LSH'
> > >  # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
> > >                                                   ^
> > > /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> > > note: in expansion of macro 'GETFIELD'
> > >  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
> > >                                   ^
> > > /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:31: note: in
> > > expansion of macro 'GETFIELD_BE64'
> > >                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
> > >                                ^
> > > /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:120:25:
> > > note: in expansion of macro 'PPC_BITMASK'
> > >  #define EAS_END_BLOCK   PPC_BITMASK(4, 7)        /* Destination END block# */
> > >                          ^
> > > /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:45: note: in
> > > expansion of macro 'EAS_END_BLOCK'
> > >                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
> > >                                              ^
> > > /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
> > > shift count is negative [-Werror=shift-count-negative]
> > >  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
> > >                                               ^
> > > /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> > > note: in expansion of macro 'GETFIELD'
> > >  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
> > >                                   ^
> > > /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:31: note: in
> > > expansion of macro 'GETFIELD_BE64'
> > >                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
> > >                                ^
> > > /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:120:25:
> > > note: in expansion of macro 'PPC_BITMASK'
> > >  #define EAS_END_BLOCK   PPC_BITMASK(4, 7)        /* Destination END block# */
> > >                          ^
> > > /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:45: note: in
> > > expansion of macro 'EAS_END_BLOCK'
> > >                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
> > >                                              ^
> > > /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
> > > shift count is negative [-Werror=shift-count-negative]
> > >  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
> > >                                               ^
> > > /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> > > note: in expansion of macro 'GETFIELD'
> > >  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
> > >                                   ^
> > > /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:31: note: in
> > > expansion of macro 'GETFIELD_BE64'
> > >                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
> > >                                ^
> > > /home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
> > > in implicit constant conversion [-Werror=overflow]
> > >  #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
> > >                                  ^
> > > /home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
> > > definition of macro 'MASK_TO_LSH'
> > >  # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
> > >                                                   ^
> > > /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> > > note: in expansion of macro 'GETFIELD'
> > >  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
> > >                                   ^
> > > /home/petmay01/qemu-for-merges/hw/intc/xive.c:1401:31: note: in
> > > expansion of macro 'GETFIELD_BE64'
> > >                     (uint32_t) GETFIELD_BE64(EAS_END_INDEX, eas->w),
> > >                                ^
> > > /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:121:25:
> > > note: in expansion of macro 'PPC_BITMASK'
> > >  #define EAS_END_INDEX   PPC_BITMASK(8, 31)       /* Destination END index */
> > >                          ^
> > > /home/petmay01/qemu-for-merges/hw/intc/xive.c:1401:45: note: in
> > > expansion of macro 'EAS_END_INDEX'
> > >                     (uint32_t) GETFIELD_BE64(EAS_END_INDEX, eas->w),
> > >                                              ^
> > > /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
> > > shift count is negative [-Werror=shift-count-negative]
> > >  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
> > >                                               ^
> > > /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> > > note: in expansion of macro 'GETFIELD'
> > >  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
> > >                                   ^
> > > /home/petmay01/qemu-for-merges/hw/intc/xive.c:1401:31: note: in
> > > expansion of macro 'GETFIELD_BE64'
> > >                     (uint32_t) GETFIELD_BE64(EAS_END_INDEX, eas->w),
> > >                                ^
> > >
> > >
> > > thanks
> > > -- PMM
> > >
> >
>
> --
> David Gibson                    | I'll have my music baroque, and my code
> david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
>                                 | _way_ _around_!
> http://www.ozlabs.org/~dgibson

Hi,

We had a discussion about the strncpy errors and windows builds
SIGSEGV-ing here:
https://lists.nongnu.org/archive/html/qemu-devel/2018-08/msg03310.html

A solution was suggested here:
https://lists.nongnu.org/archive/html/qemu-devel/2018-08/msg03761.html.

Nevertheless, I still compile with --disable-werror and
--disable-stack-protector to get a working binary. (Cross-compiling on
Fedora 29).

Best,
Howard

Re: [Qemu-devel] [PULL 00/27] ppc-for-4.0 queue 20181213

Posted by Cédric Le Goater 5 years, 4 months ago

On 12/17/18 2:03 AM, David Gibson wrote:
> On Fri, Dec 14, 2018 at 06:49:55PM +0100, Cédric Le Goater wrote:
>> On 12/14/18 5:03 PM, Peter Maydell wrote:
>>> On Thu, 13 Dec 2018 at 04:01, David Gibson <david@gibson.dropbear.id.au> wrote:
>>>>
>>>> The following changes since commit 4b3aab204204ca742836219b97b538d90584f4f2:
>>>>
>>>>   Merge remote-tracking branch 'remotes/vivier2/tags/trivial-patches-pull-request' into staging (2018-12-11 22:26:44 +0000)
>>>>
>>>> are available in the Git repository at:
>>>>
>>>>   git://github.com/dgibson/qemu.git tags/ppc-for-4.0-20181213
>>>>
>>>> for you to fetch changes up to 67888a17b6683600ae3fa64ca275c737ba8a9a45:
>>>>
>>>>   spapr/xive: use the VCPU id as a NVT identifier (2018-12-13 09:44:04 +1100)
>>>>
>>>> ----------------------------------------------------------------
>>>> ppc patch queue 2018-12-13
>>>>
>>>> Here's the first ppc and spapr pull request for 4.0.  Highlights are:
>>>>
>>>>  * The start of support for the POWER9 "XIVE" interrupt controller
>>>>    (not complete enough to use yet, but we're getting there)
>>>>  * A number of g_new vs. g_malloc cleanups
>>>>  * Some IRQ wiring cleanups
>>>>  * A fix for how we advertise NUMA nodes to the guest for pseries
>>>>
>>>> ---------------------------------------------------------------
>>>
>>>
>>> Compile errors in the windows cross-build. 
>>
>> are you compiling with the mingw64-* packages ? as documented in :
>>
>> 	https://wiki.qemu.org/Hosts/W32
>>
>>> These look like
>>> they're assumptions that "long" is 64 bits, which it is not on Windows.
>>> For instance the PPC_BIT macro should be using the ULL suffix, not UL
>>> ("UL" is almost always a bug: either the constant is 32-bit, in
>>> which case "U" is what you want, or it's 64-bit and you need "ULL").
>>
>> ok. These definitions come from our skiboot firmware which I wanted 
>> to keep as it was. It seems I will need to adapt.
>>
>>> Using __builtin_ffsl() directly in target/ppc/cpu.h also looks
>>> a bit dubious -- this should be rephrased to use ctz32() or ctz64()
>>> instead.
>>
>> ok. I will work on a fix.
> 
> So, I tried to confirm the problem, before applying Cédric's fix, but
> I don't seem to be able to.  I'm getting a bunch of failures in the
> windows cross-build on master, which look like gcc8 problems - but
> nothing new or different in my tree.
> 
> $ ./configure --cross-prefix=i686-w64-mingw32-

I am still using f28. Another reason to update.

Thanks,

C.

 
> [...]
> 
> $ make -k
> 
> 	CHK version_gen.h
>   CC      block/sheepdog.o
> block/sheepdog.c: In function 'find_vdi_name':
> block/sheepdog.c:1239:5: error: 'strncpy' specified bound 256 equals destination size [-Werror=stringop-truncation]
>      strncpy(buf + SD_MAX_VDI_LEN, tag, SD_MAX_VDI_TAG_LEN);
>      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> cc1: all warnings being treated as errors
> make: *** [/home/dwg/src/qemu/rules.mak:69: block/sheepdog.o] Error 1
>   CC      hw/acpi/core.o
> In function 'acpi_table_install',
>     inlined from 'acpi_table_add' at hw/acpi/core.c:296:5:
> hw/acpi/core.c:184:9: error: 'strncpy' specified bound 4 equals destination size [-Werror=stringop-truncation]
>          strncpy(ext_hdr->sig, hdrs->sig, sizeof ext_hdr->sig);
>          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> hw/acpi/core.c:203:9: error: 'strncpy' specified bound 6 equals destination size [-Werror=stringop-truncation]
>          strncpy(ext_hdr->oem_id, hdrs->oem_id, sizeof ext_hdr->oem_id);
>          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> hw/acpi/core.c:207:9: error: 'strncpy' specified bound 8 equals destination size [-Werror=stringop-truncation]
>          strncpy(ext_hdr->oem_table_id, hdrs->oem_table_id,
>          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>                  sizeof ext_hdr->oem_table_id);
>                  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> hw/acpi/core.c:216:9: error: 'strncpy' specified bound 4 equals destination size [-Werror=stringop-truncation]
>          strncpy(ext_hdr->asl_compiler_id, hdrs->asl_compiler_id,
>          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>                  sizeof ext_hdr->asl_compiler_id);
>                  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> cc1: all warnings being treated as errors
> make: *** [/home/dwg/src/qemu/rules.mak:69: hw/acpi/core.o] Error 1
>   CC      hw/acpi/aml-build.o
> hw/acpi/aml-build.c: In function 'build_header':
> hw/acpi/aml-build.c:1535:9: error: 'strncpy' specified bound 6 equals destination size [-Werror=stringop-truncation]
>          strncpy((char *)h->oem_id, oem_id, sizeof h->oem_id);
>          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> hw/acpi/aml-build.c:1541:9: error: 'strncpy' specified bound 8 equals destination size [-Werror=stringop-truncation]
>          strncpy((char *)h->oem_table_id, oem_table_id, sizeof(h->oem_table_id));
>          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> cc1: all warnings being treated as errors
> make: *** [/home/dwg/src/qemu/rules.mak:69: hw/acpi/aml-build.o] Error 1
>   CC      migration/global_state.o
> migration/global_state.c: In function 'global_state_store_running':
> migration/global_state.c:45:5: error: 'strncpy' specified bound 100 equals destination size [-Werror=stringop-truncation]
>      strncpy((char *)global_state.runstate,
>      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>             state, sizeof(global_state.runstate));
>             ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
> cc1: all warnings being treated as errors
> make: *** [/home/dwg/src/qemu/rules.mak:69: migration/global_state.o] Error 1
> make: Target 'all' not remade because of errors.
> 
> 
>>
>> Thanks,
>>
>> C.
>>
>>
>>> In file included from /home/petmay01/qemu-for-merges/hw/intc/xive.c:13:0:
>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c: In function 'xive_router_notify':
>>> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
>>> in implicit constant conversion [-Werror=overflow]
>>>  #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
>>>                                  ^
>>> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
>>> definition of macro 'MASK_TO_LSH'
>>>  # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
>>>                                                   ^
>>> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
>>> note: in expansion of macro 'GETFIELD'
>>>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>>>                                   ^
>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1366:28: note: in
>>> expansion of macro 'GETFIELD_BE64'
>>>                             GETFIELD_BE64(EAS_END_BLOCK, eas.w),
>>>                             ^
>>> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:120:25:
>>> note: in expansion of macro 'PPC_BITMASK'
>>>  #define EAS_END_BLOCK   PPC_BITMASK(4, 7)        /* Destination END block# */
>>>                          ^
>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1366:42: note: in
>>> expansion of macro 'EAS_END_BLOCK'
>>>                             GETFIELD_BE64(EAS_END_BLOCK, eas.w),
>>>                                           ^
>>> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
>>> shift count is negative [-Werror=shift-count-negative]
>>>  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
>>>                                               ^
>>> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
>>> note: in expansion of macro 'GETFIELD'
>>>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>>>                                   ^
>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1366:28: note: in
>>> expansion of macro 'GETFIELD_BE64'
>>>                             GETFIELD_BE64(EAS_END_BLOCK, eas.w),
>>>                             ^
>>> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
>>> in implicit constant conversion [-Werror=overflow]
>>>  #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
>>>                                  ^
>>> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
>>> definition of macro 'MASK_TO_LSH'
>>>  # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
>>>                                                   ^
>>> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
>>> note: in expansion of macro 'GETFIELD'
>>>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>>>                                   ^
>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1367:28: note: in
>>> expansion of macro 'GETFIELD_BE64'
>>>                             GETFIELD_BE64(EAS_END_INDEX, eas.w),
>>>                             ^
>>> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:121:25:
>>> note: in expansion of macro 'PPC_BITMASK'
>>>  #define EAS_END_INDEX   PPC_BITMASK(8, 31)       /* Destination END index */
>>>                          ^
>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1367:42: note: in
>>> expansion of macro 'EAS_END_INDEX'
>>>                             GETFIELD_BE64(EAS_END_INDEX, eas.w),
>>>                                           ^
>>> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
>>> shift count is negative [-Werror=shift-count-negative]
>>>  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
>>>                                               ^
>>> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
>>> note: in expansion of macro 'GETFIELD'
>>>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>>>                                   ^
>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1367:28: note: in
>>> expansion of macro 'GETFIELD_BE64'
>>>                             GETFIELD_BE64(EAS_END_INDEX, eas.w),
>>>                             ^
>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c: In function
>>> 'xive_eas_pic_print_info':
>>> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
>>> in implicit constant conversion [-Werror=overflow]
>>>  #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
>>>                                  ^
>>> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
>>> definition of macro 'MASK_TO_LSH'
>>>  # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
>>>                                                   ^
>>> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
>>> note: in expansion of macro 'GETFIELD'
>>>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>>>                                   ^
>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:31: note: in
>>> expansion of macro 'GETFIELD_BE64'
>>>                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
>>>                                ^
>>> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:120:25:
>>> note: in expansion of macro 'PPC_BITMASK'
>>>  #define EAS_END_BLOCK   PPC_BITMASK(4, 7)        /* Destination END block# */
>>>                          ^
>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:45: note: in
>>> expansion of macro 'EAS_END_BLOCK'
>>>                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
>>>                                              ^
>>> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
>>> shift count is negative [-Werror=shift-count-negative]
>>>  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
>>>                                               ^
>>> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
>>> note: in expansion of macro 'GETFIELD'
>>>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>>>                                   ^
>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:31: note: in
>>> expansion of macro 'GETFIELD_BE64'
>>>                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
>>>                                ^
>>> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:120:25:
>>> note: in expansion of macro 'PPC_BITMASK'
>>>  #define EAS_END_BLOCK   PPC_BITMASK(4, 7)        /* Destination END block# */
>>>                          ^
>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:45: note: in
>>> expansion of macro 'EAS_END_BLOCK'
>>>                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
>>>                                              ^
>>> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
>>> shift count is negative [-Werror=shift-count-negative]
>>>  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
>>>                                               ^
>>> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
>>> note: in expansion of macro 'GETFIELD'
>>>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>>>                                   ^
>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:31: note: in
>>> expansion of macro 'GETFIELD_BE64'
>>>                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
>>>                                ^
>>> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
>>> in implicit constant conversion [-Werror=overflow]
>>>  #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
>>>                                  ^
>>> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
>>> definition of macro 'MASK_TO_LSH'
>>>  # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
>>>                                                   ^
>>> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
>>> note: in expansion of macro 'GETFIELD'
>>>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>>>                                   ^
>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1401:31: note: in
>>> expansion of macro 'GETFIELD_BE64'
>>>                     (uint32_t) GETFIELD_BE64(EAS_END_INDEX, eas->w),
>>>                                ^
>>> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:121:25:
>>> note: in expansion of macro 'PPC_BITMASK'
>>>  #define EAS_END_INDEX   PPC_BITMASK(8, 31)       /* Destination END index */
>>>                          ^
>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1401:45: note: in
>>> expansion of macro 'EAS_END_INDEX'
>>>                     (uint32_t) GETFIELD_BE64(EAS_END_INDEX, eas->w),
>>>                                              ^
>>> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
>>> shift count is negative [-Werror=shift-count-negative]
>>>  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
>>>                                               ^
>>> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
>>> note: in expansion of macro 'GETFIELD'
>>>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>>>                                   ^
>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1401:31: note: in
>>> expansion of macro 'GETFIELD_BE64'
>>>                     (uint32_t) GETFIELD_BE64(EAS_END_INDEX, eas->w),
>>>                                ^
>>>
>>>
>>> thanks
>>> -- PMM
>>>
>>
>

Re: [Qemu-devel] [PULL 00/27] ppc-for-4.0 queue 20181213

Posted by Cédric Le Goater 5 years, 4 months ago

On 12/17/18 9:04 AM, Cédric Le Goater wrote:
> On 12/17/18 2:03 AM, David Gibson wrote:
>> On Fri, Dec 14, 2018 at 06:49:55PM +0100, Cédric Le Goater wrote:
>>> On 12/14/18 5:03 PM, Peter Maydell wrote:
>>>> On Thu, 13 Dec 2018 at 04:01, David Gibson <david@gibson.dropbear.id.au> wrote:
>>>>>
>>>>> The following changes since commit 4b3aab204204ca742836219b97b538d90584f4f2:
>>>>>
>>>>>   Merge remote-tracking branch 'remotes/vivier2/tags/trivial-patches-pull-request' into staging (2018-12-11 22:26:44 +0000)
>>>>>
>>>>> are available in the Git repository at:
>>>>>
>>>>>   git://github.com/dgibson/qemu.git tags/ppc-for-4.0-20181213
>>>>>
>>>>> for you to fetch changes up to 67888a17b6683600ae3fa64ca275c737ba8a9a45:
>>>>>
>>>>>   spapr/xive: use the VCPU id as a NVT identifier (2018-12-13 09:44:04 +1100)
>>>>>
>>>>> ----------------------------------------------------------------
>>>>> ppc patch queue 2018-12-13
>>>>>
>>>>> Here's the first ppc and spapr pull request for 4.0.  Highlights are:
>>>>>
>>>>>  * The start of support for the POWER9 "XIVE" interrupt controller
>>>>>    (not complete enough to use yet, but we're getting there)
>>>>>  * A number of g_new vs. g_malloc cleanups
>>>>>  * Some IRQ wiring cleanups
>>>>>  * A fix for how we advertise NUMA nodes to the guest for pseries
>>>>>
>>>>> ---------------------------------------------------------------
>>>>
>>>>
>>>> Compile errors in the windows cross-build. 
>>>
>>> are you compiling with the mingw64-* packages ? as documented in :
>>>
>>> 	https://wiki.qemu.org/Hosts/W32
>>>
>>>> These look like
>>>> they're assumptions that "long" is 64 bits, which it is not on Windows.
>>>> For instance the PPC_BIT macro should be using the ULL suffix, not UL
>>>> ("UL" is almost always a bug: either the constant is 32-bit, in
>>>> which case "U" is what you want, or it's 64-bit and you need "ULL").
>>>
>>> ok. These definitions come from our skiboot firmware which I wanted 
>>> to keep as it was. It seems I will need to adapt.
>>>
>>>> Using __builtin_ffsl() directly in target/ppc/cpu.h also looks
>>>> a bit dubious -- this should be rephrased to use ctz32() or ctz64()
>>>> instead.
>>>
>>> ok. I will work on a fix.
>>
>> So, I tried to confirm the problem, before applying Cédric's fix, but
>> I don't seem to be able to.  I'm getting a bunch of failures in the
>> windows cross-build on master, which look like gcc8 problems - but
>> nothing new or different in my tree.
>>
>> $ ./configure --cross-prefix=i686-w64-mingw32-
> 
> I am still using f28. Another reason to update.

I gave it a try on a f29 with : 

  $ x86_64-w64-mingw32-gcc --version 
  x86_64-w64-mingw32-gcc (GCC) 8.2.0 20180726 (Fedora MinGW 8.2.0-3.fc29)

and it compiles if configured with --disable-werror as suggested by Howard.

Anyhow, we need to discuss a little more on the cpu.h fix, regarding the ctz, 
and the hcalls also need some fixing :

  -        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %lx\n", lisn);
  +        qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN " TARGET_FMT_lx "\n",
  +                      lisn);


For v9. 

Thanks,
 
C.

  
>> [...]
>>
>> $ make -k
>>
>> 	CHK version_gen.h
>>   CC      block/sheepdog.o
>> block/sheepdog.c: In function 'find_vdi_name':
>> block/sheepdog.c:1239:5: error: 'strncpy' specified bound 256 equals destination size [-Werror=stringop-truncation]
>>      strncpy(buf + SD_MAX_VDI_LEN, tag, SD_MAX_VDI_TAG_LEN);
>>      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> cc1: all warnings being treated as errors
>> make: *** [/home/dwg/src/qemu/rules.mak:69: block/sheepdog.o] Error 1
>>   CC      hw/acpi/core.o
>> In function 'acpi_table_install',
>>     inlined from 'acpi_table_add' at hw/acpi/core.c:296:5:
>> hw/acpi/core.c:184:9: error: 'strncpy' specified bound 4 equals destination size [-Werror=stringop-truncation]
>>          strncpy(ext_hdr->sig, hdrs->sig, sizeof ext_hdr->sig);
>>          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> hw/acpi/core.c:203:9: error: 'strncpy' specified bound 6 equals destination size [-Werror=stringop-truncation]
>>          strncpy(ext_hdr->oem_id, hdrs->oem_id, sizeof ext_hdr->oem_id);
>>          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> hw/acpi/core.c:207:9: error: 'strncpy' specified bound 8 equals destination size [-Werror=stringop-truncation]
>>          strncpy(ext_hdr->oem_table_id, hdrs->oem_table_id,
>>          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>>                  sizeof ext_hdr->oem_table_id);
>>                  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> hw/acpi/core.c:216:9: error: 'strncpy' specified bound 4 equals destination size [-Werror=stringop-truncation]
>>          strncpy(ext_hdr->asl_compiler_id, hdrs->asl_compiler_id,
>>          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>>                  sizeof ext_hdr->asl_compiler_id);
>>                  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> cc1: all warnings being treated as errors
>> make: *** [/home/dwg/src/qemu/rules.mak:69: hw/acpi/core.o] Error 1
>>   CC      hw/acpi/aml-build.o
>> hw/acpi/aml-build.c: In function 'build_header':
>> hw/acpi/aml-build.c:1535:9: error: 'strncpy' specified bound 6 equals destination size [-Werror=stringop-truncation]
>>          strncpy((char *)h->oem_id, oem_id, sizeof h->oem_id);
>>          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> hw/acpi/aml-build.c:1541:9: error: 'strncpy' specified bound 8 equals destination size [-Werror=stringop-truncation]
>>          strncpy((char *)h->oem_table_id, oem_table_id, sizeof(h->oem_table_id));
>>          ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> cc1: all warnings being treated as errors
>> make: *** [/home/dwg/src/qemu/rules.mak:69: hw/acpi/aml-build.o] Error 1
>>   CC      migration/global_state.o
>> migration/global_state.c: In function 'global_state_store_running':
>> migration/global_state.c:45:5: error: 'strncpy' specified bound 100 equals destination size [-Werror=stringop-truncation]
>>      strncpy((char *)global_state.runstate,
>>      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>>             state, sizeof(global_state.runstate));
>>             ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> cc1: all warnings being treated as errors
>> make: *** [/home/dwg/src/qemu/rules.mak:69: migration/global_state.o] Error 1
>> make: Target 'all' not remade because of errors.
>>
>>
>>>
>>> Thanks,
>>>
>>> C.
>>>
>>>
>>>> In file included from /home/petmay01/qemu-for-merges/hw/intc/xive.c:13:0:
>>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c: In function 'xive_router_notify':
>>>> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
>>>> in implicit constant conversion [-Werror=overflow]
>>>>  #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
>>>>                                  ^
>>>> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
>>>> definition of macro 'MASK_TO_LSH'
>>>>  # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
>>>>                                                   ^
>>>> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
>>>> note: in expansion of macro 'GETFIELD'
>>>>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>>>>                                   ^
>>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1366:28: note: in
>>>> expansion of macro 'GETFIELD_BE64'
>>>>                             GETFIELD_BE64(EAS_END_BLOCK, eas.w),
>>>>                             ^
>>>> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:120:25:
>>>> note: in expansion of macro 'PPC_BITMASK'
>>>>  #define EAS_END_BLOCK   PPC_BITMASK(4, 7)        /* Destination END block# */
>>>>                          ^
>>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1366:42: note: in
>>>> expansion of macro 'EAS_END_BLOCK'
>>>>                             GETFIELD_BE64(EAS_END_BLOCK, eas.w),
>>>>                                           ^
>>>> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
>>>> shift count is negative [-Werror=shift-count-negative]
>>>>  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
>>>>                                               ^
>>>> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
>>>> note: in expansion of macro 'GETFIELD'
>>>>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>>>>                                   ^
>>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1366:28: note: in
>>>> expansion of macro 'GETFIELD_BE64'
>>>>                             GETFIELD_BE64(EAS_END_BLOCK, eas.w),
>>>>                             ^
>>>> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
>>>> in implicit constant conversion [-Werror=overflow]
>>>>  #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
>>>>                                  ^
>>>> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
>>>> definition of macro 'MASK_TO_LSH'
>>>>  # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
>>>>                                                   ^
>>>> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
>>>> note: in expansion of macro 'GETFIELD'
>>>>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>>>>                                   ^
>>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1367:28: note: in
>>>> expansion of macro 'GETFIELD_BE64'
>>>>                             GETFIELD_BE64(EAS_END_INDEX, eas.w),
>>>>                             ^
>>>> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:121:25:
>>>> note: in expansion of macro 'PPC_BITMASK'
>>>>  #define EAS_END_INDEX   PPC_BITMASK(8, 31)       /* Destination END index */
>>>>                          ^
>>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1367:42: note: in
>>>> expansion of macro 'EAS_END_INDEX'
>>>>                             GETFIELD_BE64(EAS_END_INDEX, eas.w),
>>>>                                           ^
>>>> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
>>>> shift count is negative [-Werror=shift-count-negative]
>>>>  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
>>>>                                               ^
>>>> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
>>>> note: in expansion of macro 'GETFIELD'
>>>>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>>>>                                   ^
>>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1367:28: note: in
>>>> expansion of macro 'GETFIELD_BE64'
>>>>                             GETFIELD_BE64(EAS_END_INDEX, eas.w),
>>>>                             ^
>>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c: In function
>>>> 'xive_eas_pic_print_info':
>>>> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
>>>> in implicit constant conversion [-Werror=overflow]
>>>>  #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
>>>>                                  ^
>>>> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
>>>> definition of macro 'MASK_TO_LSH'
>>>>  # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
>>>>                                                   ^
>>>> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
>>>> note: in expansion of macro 'GETFIELD'
>>>>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>>>>                                   ^
>>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:31: note: in
>>>> expansion of macro 'GETFIELD_BE64'
>>>>                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
>>>>                                ^
>>>> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:120:25:
>>>> note: in expansion of macro 'PPC_BITMASK'
>>>>  #define EAS_END_BLOCK   PPC_BITMASK(4, 7)        /* Destination END block# */
>>>>                          ^
>>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:45: note: in
>>>> expansion of macro 'EAS_END_BLOCK'
>>>>                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
>>>>                                              ^
>>>> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
>>>> shift count is negative [-Werror=shift-count-negative]
>>>>  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
>>>>                                               ^
>>>> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
>>>> note: in expansion of macro 'GETFIELD'
>>>>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>>>>                                   ^
>>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:31: note: in
>>>> expansion of macro 'GETFIELD_BE64'
>>>>                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
>>>>                                ^
>>>> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:120:25:
>>>> note: in expansion of macro 'PPC_BITMASK'
>>>>  #define EAS_END_BLOCK   PPC_BITMASK(4, 7)        /* Destination END block# */
>>>>                          ^
>>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:45: note: in
>>>> expansion of macro 'EAS_END_BLOCK'
>>>>                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
>>>>                                              ^
>>>> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
>>>> shift count is negative [-Werror=shift-count-negative]
>>>>  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
>>>>                                               ^
>>>> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
>>>> note: in expansion of macro 'GETFIELD'
>>>>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>>>>                                   ^
>>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:31: note: in
>>>> expansion of macro 'GETFIELD_BE64'
>>>>                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
>>>>                                ^
>>>> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
>>>> in implicit constant conversion [-Werror=overflow]
>>>>  #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
>>>>                                  ^
>>>> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
>>>> definition of macro 'MASK_TO_LSH'
>>>>  # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
>>>>                                                   ^
>>>> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
>>>> note: in expansion of macro 'GETFIELD'
>>>>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>>>>                                   ^
>>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1401:31: note: in
>>>> expansion of macro 'GETFIELD_BE64'
>>>>                     (uint32_t) GETFIELD_BE64(EAS_END_INDEX, eas->w),
>>>>                                ^
>>>> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:121:25:
>>>> note: in expansion of macro 'PPC_BITMASK'
>>>>  #define EAS_END_INDEX   PPC_BITMASK(8, 31)       /* Destination END index */
>>>>                          ^
>>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1401:45: note: in
>>>> expansion of macro 'EAS_END_INDEX'
>>>>                     (uint32_t) GETFIELD_BE64(EAS_END_INDEX, eas->w),
>>>>                                              ^
>>>> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
>>>> shift count is negative [-Werror=shift-count-negative]
>>>>  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
>>>>                                               ^
>>>> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
>>>> note: in expansion of macro 'GETFIELD'
>>>>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>>>>                                   ^
>>>> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1401:31: note: in
>>>> expansion of macro 'GETFIELD_BE64'
>>>>                     (uint32_t) GETFIELD_BE64(EAS_END_INDEX, eas->w),
>>>>                                ^
>>>>
>>>>
>>>> thanks
>>>> -- PMM
>>>>
>>>
>>
>

Re: [Qemu-devel] [PULL 00/27] ppc-for-4.0 queue 20181213

Posted by David Gibson 5 years, 4 months ago

On Fri, Dec 14, 2018 at 04:03:08PM +0000, Peter Maydell wrote:
> On Thu, 13 Dec 2018 at 04:01, David Gibson <david@gibson.dropbear.id.au> wrote:
> >
> > The following changes since commit 4b3aab204204ca742836219b97b538d90584f4f2:
> >
> >   Merge remote-tracking branch 'remotes/vivier2/tags/trivial-patches-pull-request' into staging (2018-12-11 22:26:44 +0000)
> >
> > are available in the Git repository at:
> >
> >   git://github.com/dgibson/qemu.git tags/ppc-for-4.0-20181213
> >
> > for you to fetch changes up to 67888a17b6683600ae3fa64ca275c737ba8a9a45:
> >
> >   spapr/xive: use the VCPU id as a NVT identifier (2018-12-13 09:44:04 +1100)
> >
> > ----------------------------------------------------------------
> > ppc patch queue 2018-12-13
> >
> > Here's the first ppc and spapr pull request for 4.0.  Highlights are:
> >
> >  * The start of support for the POWER9 "XIVE" interrupt controller
> >    (not complete enough to use yet, but we're getting there)
> >  * A number of g_new vs. g_malloc cleanups
> >  * Some IRQ wiring cleanups
> >  * A fix for how we advertise NUMA nodes to the guest for pseries
> >
> > ---------------------------------------------------------------
> 
> 
> Compile errors in the windows cross-build. These look like
> they're assumptions that "long" is 64 bits, which it is not on Windows.
> For instance the PPC_BIT macro should be using the ULL suffix, not UL
> ("UL" is almost always a bug: either the constant is 32-bit, in
> which case "U" is what you want, or it's 64-bit and you need "ULL").

Bother, sorry.  I got sidetracked debugging some problems that turned
out to be in master and forgot to run the windows builds.


> Using __builtin_ffsl() directly in target/ppc/cpu.h also looks
> a bit dubious -- this should be rephrased to use ctz32() or ctz64()
> instead.
> 
> In file included from /home/petmay01/qemu-for-merges/hw/intc/xive.c:13:0:
> /home/petmay01/qemu-for-merges/hw/intc/xive.c: In function 'xive_router_notify':
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
> in implicit constant conversion [-Werror=overflow]
>  #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
>                                  ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
> definition of macro 'MASK_TO_LSH'
>  # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
>                                                   ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> note: in expansion of macro 'GETFIELD'
>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>                                   ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1366:28: note: in
> expansion of macro 'GETFIELD_BE64'
>                             GETFIELD_BE64(EAS_END_BLOCK, eas.w),
>                             ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:120:25:
> note: in expansion of macro 'PPC_BITMASK'
>  #define EAS_END_BLOCK   PPC_BITMASK(4, 7)        /* Destination END block# */
>                          ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1366:42: note: in
> expansion of macro 'EAS_END_BLOCK'
>                             GETFIELD_BE64(EAS_END_BLOCK, eas.w),
>                                           ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
> shift count is negative [-Werror=shift-count-negative]
>  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
>                                               ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> note: in expansion of macro 'GETFIELD'
>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>                                   ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1366:28: note: in
> expansion of macro 'GETFIELD_BE64'
>                             GETFIELD_BE64(EAS_END_BLOCK, eas.w),
>                             ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
> in implicit constant conversion [-Werror=overflow]
>  #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
>                                  ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
> definition of macro 'MASK_TO_LSH'
>  # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
>                                                   ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> note: in expansion of macro 'GETFIELD'
>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>                                   ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1367:28: note: in
> expansion of macro 'GETFIELD_BE64'
>                             GETFIELD_BE64(EAS_END_INDEX, eas.w),
>                             ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:121:25:
> note: in expansion of macro 'PPC_BITMASK'
>  #define EAS_END_INDEX   PPC_BITMASK(8, 31)       /* Destination END index */
>                          ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1367:42: note: in
> expansion of macro 'EAS_END_INDEX'
>                             GETFIELD_BE64(EAS_END_INDEX, eas.w),
>                                           ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
> shift count is negative [-Werror=shift-count-negative]
>  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
>                                               ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> note: in expansion of macro 'GETFIELD'
>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>                                   ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1367:28: note: in
> expansion of macro 'GETFIELD_BE64'
>                             GETFIELD_BE64(EAS_END_INDEX, eas.w),
>                             ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c: In function
> 'xive_eas_pic_print_info':
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
> in implicit constant conversion [-Werror=overflow]
>  #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
>                                  ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
> definition of macro 'MASK_TO_LSH'
>  # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
>                                                   ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> note: in expansion of macro 'GETFIELD'
>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>                                   ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:31: note: in
> expansion of macro 'GETFIELD_BE64'
>                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
>                                ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:120:25:
> note: in expansion of macro 'PPC_BITMASK'
>  #define EAS_END_BLOCK   PPC_BITMASK(4, 7)        /* Destination END block# */
>                          ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:45: note: in
> expansion of macro 'EAS_END_BLOCK'
>                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
>                                              ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
> shift count is negative [-Werror=shift-count-negative]
>  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
>                                               ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> note: in expansion of macro 'GETFIELD'
>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>                                   ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:31: note: in
> expansion of macro 'GETFIELD_BE64'
>                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
>                                ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:120:25:
> note: in expansion of macro 'PPC_BITMASK'
>  #define EAS_END_BLOCK   PPC_BITMASK(4, 7)        /* Destination END block# */
>                          ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:45: note: in
> expansion of macro 'EAS_END_BLOCK'
>                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
>                                              ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
> shift count is negative [-Werror=shift-count-negative]
>  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
>                                               ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> note: in expansion of macro 'GETFIELD'
>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>                                   ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1400:31: note: in
> expansion of macro 'GETFIELD_BE64'
>                     (uint8_t)  GETFIELD_BE64(EAS_END_BLOCK, eas->w),
>                                ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:76:33: error: overflow
> in implicit constant conversion [-Werror=overflow]
>  #define PPC_BITMASK(bs, be)     ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
>                                  ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:84:50: note: in
> definition of macro 'MASK_TO_LSH'
>  # define MASK_TO_LSH(m)          (__builtin_ffsl(m) - 1)
>                                                   ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> note: in expansion of macro 'GETFIELD'
>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>                                   ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1401:31: note: in
> expansion of macro 'GETFIELD_BE64'
>                     (uint32_t) GETFIELD_BE64(EAS_END_INDEX, eas->w),
>                                ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:121:25:
> note: in expansion of macro 'PPC_BITMASK'
>  #define EAS_END_INDEX   PPC_BITMASK(8, 31)       /* Destination END index */
>                          ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1401:45: note: in
> expansion of macro 'EAS_END_INDEX'
>                     (uint32_t) GETFIELD_BE64(EAS_END_INDEX, eas->w),
>                                              ^
> /home/petmay01/qemu-for-merges/target/ppc/cpu.h:89:46: error: right
> shift count is negative [-Werror=shift-count-negative]
>  #define GETFIELD(m, v)          (((v) & (m)) >> MASK_TO_LSH(m))
>                                               ^
> /home/petmay01/qemu-for-merges/include/hw/ppc/xive_regs.h:129:34:
> note: in expansion of macro 'GETFIELD'
>  #define GETFIELD_BE64(m, v)      GETFIELD(m, be64_to_cpu(v))
>                                   ^
> /home/petmay01/qemu-for-merges/hw/intc/xive.c:1401:31: note: in
> expansion of macro 'GETFIELD_BE64'
>                     (uint32_t) GETFIELD_BE64(EAS_END_INDEX, eas->w),
>                                ^
> 
> 
> thanks
> -- PMM
> 

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

Re: [Qemu-devel] [PULL 00/27] ppc-for-4.0 queue 20181213

Posted by no-reply@patchew.org 5 years, 4 months ago

Patchew URL: https://patchew.org/QEMU/20181213040126.6768-1-david@gibson.dropbear.id.au/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Type: series
Message-id: 20181213040126.6768-1-david@gibson.dropbear.id.au
Subject: [Qemu-devel] [PULL 00/27] ppc-for-4.0 queue 20181213

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
ad20d15 spapr/xive: use the VCPU id as a NVT identifier
936bcd5 spapr/xive: introduce a XIVE interrupt controller
c13abc0 ppc/xive: notify the CPU when the interrupt priority is more privileged
58a0735 ppc/xive: introduce a simplified XIVE presenter
f463196 ppc/xive: introduce the XIVE interrupt thread context
b5b9c85 ppc/xive: add support for the END Event State Buffers
11d0460 Changes requirement for "vsubsbs" instruction
37e7503 spapr: export and rename the xics_max_server_number() routine
4d7a081 spapr: introduce a spapr_irq_init() routine
22e14d8 spapr: initialize VSMT before initializing the IRQ backend
e85821f ppc/xive: introduce the XIVE Event Notification Descriptors
37adf84 ppc/xive: introduce the XiveRouter model
b17c216 ppc/xive: introduce the XiveNotifier interface
e9aa0c9 ppc/xive: add support for the LSI interrupt sources
afa26a0 ppc/xive: introduce a XIVE interrupt source model
4052b1a e500: simplify IRQ wiring
f01edd5 mac_newworld: simplify IRQ wiring
dd09168 virtex_ml507: use g_new(T, n) instead of g_malloc(sizeof(T) * n)
6666001 sam460ex: use g_new(T, n) instead of g_malloc(sizeof(T) * n)
ae12a4c ppc440_bamboo: use g_new(T, n) instead of g_malloc(sizeof(T) * n)
0126aee ppc405_uc: use g_new(T, n) instead of g_malloc(sizeof(T) * n)
f9a1d51 ppc405_boards: use g_new(T, n) instead of g_malloc(sizeof(T) * n)
1dc1282 spapr: use g_new(T, n) instead of g_malloc(sizeof(T) * n)
61eb9c6 target/ppc: use g_new(T, n) instead of g_malloc(sizeof(T) * n)
db6492f spapr: drop redundant statement in spapr_populate_drconf_memory()
61d6352 target/ppc: tcg: Implement addex instruction
17ee949 spapr: Fix ibm, max-associativity-domains property number of nodes

=== OUTPUT BEGIN ===
Checking PATCH 1/27: spapr: Fix ibm, max-associativity-domains property number of nodes...
Checking PATCH 2/27: target/ppc: tcg: Implement addex instruction...
ERROR: space required after that ',' (ctx:VxV)
#42: FILE: disas/ppc.c:3737:
+{ "addex",   XO(31,170,0,0), XO_MASK,   POWER9,         { RT, RA, RB } },
                   ^

ERROR: space required after that ',' (ctx:VxV)
#42: FILE: disas/ppc.c:3737:
+{ "addex",   XO(31,170,0,0), XO_MASK,   POWER9,         { RT, RA, RB } },
                       ^

ERROR: space required after that ',' (ctx:VxV)
#42: FILE: disas/ppc.c:3737:
+{ "addex",   XO(31,170,0,0), XO_MASK,   POWER9,         { RT, RA, RB } },
                         ^

total: 3 errors, 0 warnings, 156 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 3/27: spapr: drop redundant statement in spapr_populate_drconf_memory()...
Checking PATCH 4/27: target/ppc: use g_new(T, n) instead of g_malloc(sizeof(T) * n)...
Checking PATCH 5/27: spapr: use g_new(T, n) instead of g_malloc(sizeof(T) * n)...
Checking PATCH 6/27: ppc405_boards: use g_new(T, n) instead of g_malloc(sizeof(T) * n)...
Checking PATCH 7/27: ppc405_uc: use g_new(T, n) instead of g_malloc(sizeof(T) * n)...
Checking PATCH 8/27: ppc440_bamboo: use g_new(T, n) instead of g_malloc(sizeof(T) * n)...
Checking PATCH 9/27: sam460ex: use g_new(T, n) instead of g_malloc(sizeof(T) * n)...
Checking PATCH 10/27: virtex_ml507: use g_new(T, n) instead of g_malloc(sizeof(T) * n)...
Checking PATCH 11/27: mac_newworld: simplify IRQ wiring...
Checking PATCH 12/27: e500: simplify IRQ wiring...
Checking PATCH 13/27: ppc/xive: introduce a XIVE interrupt source model...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#61: 
new file mode 100644

total: 0 errors, 1 warnings, 656 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 14/27: ppc/xive: add support for the LSI interrupt sources...
Checking PATCH 15/27: ppc/xive: introduce the XiveNotifier interface...
Checking PATCH 16/27: ppc/xive: introduce the XiveRouter model...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#170: 
new file mode 100644

total: 0 errors, 1 warnings, 179 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 17/27: ppc/xive: introduce the XIVE Event Notification Descriptors...
Checking PATCH 18/27: spapr: initialize VSMT before initializing the IRQ backend...
Checking PATCH 19/27: spapr: introduce a spapr_irq_init() routine...
Checking PATCH 20/27: spapr: export and rename the xics_max_server_number() routine...
Checking PATCH 21/27: Changes requirement for "vsubsbs" instruction...
Checking PATCH 22/27: ppc/xive: add support for the END Event State Buffers...
Checking PATCH 23/27: ppc/xive: introduce the XIVE interrupt thread context...
Checking PATCH 24/27: ppc/xive: introduce a simplified XIVE presenter...
Checking PATCH 25/27: ppc/xive: notify the CPU when the interrupt priority is more privileged...
Checking PATCH 26/27: spapr/xive: introduce a XIVE interrupt controller...
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#59: 
new file mode 100644

total: 0 errors, 1 warnings, 425 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 27/27: spapr/xive: use the VCPU id as a NVT identifier...
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20181213040126.6768-1-david@gibson.dropbear.id.au/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com

Re: [Qemu-devel] [PULL 00/27] ppc-for-4.0 queue 20181213

Posted by David Gibson 5 years, 4 months ago

On Wed, Dec 12, 2018 at 11:43:40PM -0800, no-reply@patchew.org wrote:
> Patchew URL: https://patchew.org/QEMU/20181213040126.6768-1-david@gibson.dropbear.id.au/
> 
> 
> 
> Hi,
> 
> This series seems to have some coding style problems. See output below for
> more information:
> 
> Type: series
> Message-id: 20181213040126.6768-1-david@gibson.dropbear.id.au
> Subject: [Qemu-devel] [PULL 00/27] ppc-for-4.0 queue 20181213

[snip]
> === OUTPUT BEGIN ===
> Checking PATCH 1/27: spapr: Fix ibm, max-associativity-domains property number of nodes...
> Checking PATCH 2/27: target/ppc: tcg: Implement addex instruction...
> ERROR: space required after that ',' (ctx:VxV)
> #42: FILE: disas/ppc.c:3737:
> +{ "addex",   XO(31,170,0,0), XO_MASK,   POWER9,         { RT, RA, RB } },
>                    ^
> 
> ERROR: space required after that ',' (ctx:VxV)
> #42: FILE: disas/ppc.c:3737:
> +{ "addex",   XO(31,170,0,0), XO_MASK,   POWER9,         { RT, RA, RB } },
>                        ^
> 
> ERROR: space required after that ',' (ctx:VxV)
> #42: FILE: disas/ppc.c:3737:
> +{ "addex",   XO(31,170,0,0), XO_MASK,   POWER9,         { RT, RA, RB } },
>                          ^
> 
> total: 3 errors, 0 warnings, 156 lines checked

These are sorta-false positives.  There's a whole old set of macro
conventions in that file that are a real mess coding style wise
(amongst other ways).  For the time being, internal consistency is
more important than consistency outside here.

[snip]
> Checking PATCH 13/27: ppc/xive: introduce a XIVE interrupt source model...
> WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
> #61: 
> new file mode 100644
> 
> total: 0 errors, 1 warnings, 656 lines checked
> 
> Your patch has style problems, please review.  If any of these errors
> are false positives report them to the maintainer, see
> CHECKPATCH in MAINTAINERS.
> Checking PATCH 14/27: ppc/xive: add support for the LSI interrupt sources...
> Checking PATCH 15/27: ppc/xive: introduce the XiveNotifier interface...
> Checking PATCH 16/27: ppc/xive: introduce the XiveRouter model...
> WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
> #170: 
> new file mode 100644

These do need a MAINTAINERS update, which I plan to do in followup.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

Re: [Qemu-devel] [PULL 00/27] ppc-for-4.0 queue 20181213

Posted by Cédric Le Goater 5 years, 4 months ago

>> Your patch has style problems, please review.  If any of these errors
>> are false positives report them to the maintainer, see
>> CHECKPATCH in MAINTAINERS.
>> Checking PATCH 14/27: ppc/xive: add support for the LSI interrupt sources...
>> Checking PATCH 15/27: ppc/xive: introduce the XiveNotifier interface...
>> Checking PATCH 16/27: ppc/xive: introduce the XiveRouter model...
>> WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
>> #170: 
>> new file mode 100644
> 
> These do need a MAINTAINERS update, which I plan to do in followup.

Yes. I should have. Please add my name also. 

Thanks,

C.